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// soc_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
output wire [7:0] hps_0_f2h_axi_slave_awid, // hps_0_f2h_axi_slave.awid
output wire [31:0] hps_0_f2h_axi_slave_awaddr, // .awaddr
output wire [3:0] hps_0_f2h_axi_slave_awlen, // .awlen
output wire [2:0] hps_0_f2h_axi_slave_awsize, // .awsize
output wire [1:0] hps_0_f2h_axi_slave_awburst, // .awburst
output wire [1:0] hps_0_f2h_axi_slave_awlock, // .awlock
output wire [3:0] hps_0_f2h_axi_slave_awcache, // .awcache
output wire [2:0] hps_0_f2h_axi_slave_awprot, // .awprot
output wire [4:0] hps_0_f2h_axi_slave_awuser, // .awuser
output wire hps_0_f2h_axi_slave_awvalid, // .awvalid
input wire hps_0_f2h_axi_slave_awready, // .awready
output wire [7:0] hps_0_f2h_axi_slave_wid, // .wid
output wire [127:0] hps_0_f2h_axi_slave_wdata, // .wdata
output wire [15:0] hps_0_f2h_axi_slave_wstrb, // .wstrb
output wire hps_0_f2h_axi_slave_wlast, // .wlast
output wire hps_0_f2h_axi_slave_wvalid, // .wvalid
input wire hps_0_f2h_axi_slave_wready, // .wready
input wire [7:0] hps_0_f2h_axi_slave_bid, // .bid
input wire [1:0] hps_0_f2h_axi_slave_bresp, // .bresp
input wire hps_0_f2h_axi_slave_bvalid, // .bvalid
output wire hps_0_f2h_axi_slave_bready, // .bready
output wire [7:0] hps_0_f2h_axi_slave_arid, // .arid
output wire [31:0] hps_0_f2h_axi_slave_araddr, // .araddr
output wire [3:0] hps_0_f2h_axi_slave_arlen, // .arlen
output wire [2:0] hps_0_f2h_axi_slave_arsize, // .arsize
output wire [1:0] hps_0_f2h_axi_slave_arburst, // .arburst
output wire [1:0] hps_0_f2h_axi_slave_arlock, // .arlock
output wire [3:0] hps_0_f2h_axi_slave_arcache, // .arcache
output wire [2:0] hps_0_f2h_axi_slave_arprot, // .arprot
output wire [4:0] hps_0_f2h_axi_slave_aruser, // .aruser
output wire hps_0_f2h_axi_slave_arvalid, // .arvalid
input wire hps_0_f2h_axi_slave_arready, // .arready
input wire [7:0] hps_0_f2h_axi_slave_rid, // .rid
input wire [127:0] hps_0_f2h_axi_slave_rdata, // .rdata
input wire [1:0] hps_0_f2h_axi_slave_rresp, // .rresp
input wire hps_0_f2h_axi_slave_rlast, // .rlast
input wire hps_0_f2h_axi_slave_rvalid, // .rvalid
output wire hps_0_f2h_axi_slave_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset, // alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset.reset
input wire hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
input wire master_secure_clk_reset_reset_bridge_in_reset_reset, // master_secure_clk_reset_reset_bridge_in_reset.reset
input wire [31:0] alt_vip_vfr_vga_avalon_master_address, // alt_vip_vfr_vga_avalon_master.address
output wire alt_vip_vfr_vga_avalon_master_waitrequest, // .waitrequest
input wire [5:0] alt_vip_vfr_vga_avalon_master_burstcount, // .burstcount
input wire alt_vip_vfr_vga_avalon_master_read, // .read
output wire [127:0] alt_vip_vfr_vga_avalon_master_readdata, // .readdata
output wire alt_vip_vfr_vga_avalon_master_readdatavalid, // .readdatavalid
input wire [31:0] master_secure_master_address, // master_secure_master.address
output wire master_secure_master_waitrequest, // .waitrequest
input wire [3:0] master_secure_master_byteenable, // .byteenable
input wire master_secure_master_read, // .read
output wire [31:0] master_secure_master_readdata, // .readdata
output wire master_secure_master_readdatavalid, // .readdatavalid
input wire master_secure_master_write, // .write
input wire [31:0] master_secure_master_writedata // .writedata
);
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_waitrequest; // alt_vip_vfr_vga_avalon_master_agent:av_waitrequest -> alt_vip_vfr_vga_avalon_master_translator:uav_waitrequest
wire [127:0] alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdata; // alt_vip_vfr_vga_avalon_master_agent:av_readdata -> alt_vip_vfr_vga_avalon_master_translator:uav_readdata
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_debugaccess; // alt_vip_vfr_vga_avalon_master_translator:uav_debugaccess -> alt_vip_vfr_vga_avalon_master_agent:av_debugaccess
wire [31:0] alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_address; // alt_vip_vfr_vga_avalon_master_translator:uav_address -> alt_vip_vfr_vga_avalon_master_agent:av_address
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_read; // alt_vip_vfr_vga_avalon_master_translator:uav_read -> alt_vip_vfr_vga_avalon_master_agent:av_read
wire [15:0] alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_byteenable; // alt_vip_vfr_vga_avalon_master_translator:uav_byteenable -> alt_vip_vfr_vga_avalon_master_agent:av_byteenable
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdatavalid; // alt_vip_vfr_vga_avalon_master_agent:av_readdatavalid -> alt_vip_vfr_vga_avalon_master_translator:uav_readdatavalid
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_lock; // alt_vip_vfr_vga_avalon_master_translator:uav_lock -> alt_vip_vfr_vga_avalon_master_agent:av_lock
wire alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_write; // alt_vip_vfr_vga_avalon_master_translator:uav_write -> alt_vip_vfr_vga_avalon_master_agent:av_write
wire [127:0] alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_writedata; // alt_vip_vfr_vga_avalon_master_translator:uav_writedata -> alt_vip_vfr_vga_avalon_master_agent:av_writedata
wire [9:0] alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_burstcount; // alt_vip_vfr_vga_avalon_master_translator:uav_burstcount -> alt_vip_vfr_vga_avalon_master_agent:av_burstcount
wire master_secure_master_translator_avalon_universal_master_0_waitrequest; // master_secure_master_agent:av_waitrequest -> master_secure_master_translator:uav_waitrequest
wire [31:0] master_secure_master_translator_avalon_universal_master_0_readdata; // master_secure_master_agent:av_readdata -> master_secure_master_translator:uav_readdata
wire master_secure_master_translator_avalon_universal_master_0_debugaccess; // master_secure_master_translator:uav_debugaccess -> master_secure_master_agent:av_debugaccess
wire [31:0] master_secure_master_translator_avalon_universal_master_0_address; // master_secure_master_translator:uav_address -> master_secure_master_agent:av_address
wire master_secure_master_translator_avalon_universal_master_0_read; // master_secure_master_translator:uav_read -> master_secure_master_agent:av_read
wire [3:0] master_secure_master_translator_avalon_universal_master_0_byteenable; // master_secure_master_translator:uav_byteenable -> master_secure_master_agent:av_byteenable
wire master_secure_master_translator_avalon_universal_master_0_readdatavalid; // master_secure_master_agent:av_readdatavalid -> master_secure_master_translator:uav_readdatavalid
wire master_secure_master_translator_avalon_universal_master_0_lock; // master_secure_master_translator:uav_lock -> master_secure_master_agent:av_lock
wire master_secure_master_translator_avalon_universal_master_0_write; // master_secure_master_translator:uav_write -> master_secure_master_agent:av_write
wire [31:0] master_secure_master_translator_avalon_universal_master_0_writedata; // master_secure_master_translator:uav_writedata -> master_secure_master_agent:av_writedata
wire [2:0] master_secure_master_translator_avalon_universal_master_0_burstcount; // master_secure_master_translator:uav_burstcount -> master_secure_master_agent:av_burstcount
wire alt_vip_vfr_vga_avalon_master_agent_cp_valid; // alt_vip_vfr_vga_avalon_master_agent:cp_valid -> router:sink_valid
wire [228:0] alt_vip_vfr_vga_avalon_master_agent_cp_data; // alt_vip_vfr_vga_avalon_master_agent:cp_data -> router:sink_data
wire alt_vip_vfr_vga_avalon_master_agent_cp_ready; // router:sink_ready -> alt_vip_vfr_vga_avalon_master_agent:cp_ready
wire alt_vip_vfr_vga_avalon_master_agent_cp_startofpacket; // alt_vip_vfr_vga_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire alt_vip_vfr_vga_avalon_master_agent_cp_endofpacket; // alt_vip_vfr_vga_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire master_secure_master_agent_cp_valid; // master_secure_master_agent:cp_valid -> router_001:sink_valid
wire [120:0] master_secure_master_agent_cp_data; // master_secure_master_agent:cp_data -> router_001:sink_data
wire master_secure_master_agent_cp_ready; // router_001:sink_ready -> master_secure_master_agent:cp_ready
wire master_secure_master_agent_cp_startofpacket; // master_secure_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire master_secure_master_agent_cp_endofpacket; // master_secure_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_valid; // hps_0_f2h_axi_slave_agent:write_rp_valid -> router_002:sink_valid
wire [228:0] hps_0_f2h_axi_slave_agent_write_rp_data; // hps_0_f2h_axi_slave_agent:write_rp_data -> router_002:sink_data
wire hps_0_f2h_axi_slave_agent_write_rp_ready; // router_002:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
wire hps_0_f2h_axi_slave_agent_write_rp_startofpacket; // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> router_002:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_endofpacket; // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [228:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_valid; // hps_0_f2h_axi_slave_agent:read_rp_valid -> router_003:sink_valid
wire [228:0] hps_0_f2h_axi_slave_agent_read_rp_data; // hps_0_f2h_axi_slave_agent:read_rp_data -> router_003:sink_data
wire hps_0_f2h_axi_slave_agent_read_rp_ready; // router_003:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
wire hps_0_f2h_axi_slave_agent_read_rp_startofpacket; // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> router_003:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_endofpacket; // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [228:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [1:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_src_valid; // router:src_valid -> alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_valid
wire [228:0] router_src_data; // router:src_data -> alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_data
wire router_src_ready; // alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> alt_vip_vfr_vga_avalon_master_limiter:cmd_sink_endofpacket
wire [228:0] alt_vip_vfr_vga_avalon_master_limiter_cmd_src_data; // alt_vip_vfr_vga_avalon_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire alt_vip_vfr_vga_avalon_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> alt_vip_vfr_vga_avalon_master_limiter:cmd_src_ready
wire [1:0] alt_vip_vfr_vga_avalon_master_limiter_cmd_src_channel; // alt_vip_vfr_vga_avalon_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire alt_vip_vfr_vga_avalon_master_limiter_cmd_src_startofpacket; // alt_vip_vfr_vga_avalon_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire alt_vip_vfr_vga_avalon_master_limiter_cmd_src_endofpacket; // alt_vip_vfr_vga_avalon_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_valid
wire [228:0] rsp_mux_src_data; // rsp_mux:src_data -> alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> alt_vip_vfr_vga_avalon_master_limiter:rsp_sink_endofpacket
wire alt_vip_vfr_vga_avalon_master_limiter_rsp_src_valid; // alt_vip_vfr_vga_avalon_master_limiter:rsp_src_valid -> alt_vip_vfr_vga_avalon_master_agent:rp_valid
wire [228:0] alt_vip_vfr_vga_avalon_master_limiter_rsp_src_data; // alt_vip_vfr_vga_avalon_master_limiter:rsp_src_data -> alt_vip_vfr_vga_avalon_master_agent:rp_data
wire alt_vip_vfr_vga_avalon_master_limiter_rsp_src_ready; // alt_vip_vfr_vga_avalon_master_agent:rp_ready -> alt_vip_vfr_vga_avalon_master_limiter:rsp_src_ready
wire [1:0] alt_vip_vfr_vga_avalon_master_limiter_rsp_src_channel; // alt_vip_vfr_vga_avalon_master_limiter:rsp_src_channel -> alt_vip_vfr_vga_avalon_master_agent:rp_channel
wire alt_vip_vfr_vga_avalon_master_limiter_rsp_src_startofpacket; // alt_vip_vfr_vga_avalon_master_limiter:rsp_src_startofpacket -> alt_vip_vfr_vga_avalon_master_agent:rp_startofpacket
wire alt_vip_vfr_vga_avalon_master_limiter_rsp_src_endofpacket; // alt_vip_vfr_vga_avalon_master_limiter:rsp_src_endofpacket -> alt_vip_vfr_vga_avalon_master_agent:rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> master_secure_master_limiter:cmd_sink_valid
wire [120:0] router_001_src_data; // router_001:src_data -> master_secure_master_limiter:cmd_sink_data
wire router_001_src_ready; // master_secure_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> master_secure_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> master_secure_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> master_secure_master_limiter:cmd_sink_endofpacket
wire master_secure_master_limiter_rsp_src_valid; // master_secure_master_limiter:rsp_src_valid -> master_secure_master_agent:rp_valid
wire [120:0] master_secure_master_limiter_rsp_src_data; // master_secure_master_limiter:rsp_src_data -> master_secure_master_agent:rp_data
wire master_secure_master_limiter_rsp_src_ready; // master_secure_master_agent:rp_ready -> master_secure_master_limiter:rsp_src_ready
wire [1:0] master_secure_master_limiter_rsp_src_channel; // master_secure_master_limiter:rsp_src_channel -> master_secure_master_agent:rp_channel
wire master_secure_master_limiter_rsp_src_startofpacket; // master_secure_master_limiter:rsp_src_startofpacket -> master_secure_master_agent:rp_startofpacket
wire master_secure_master_limiter_rsp_src_endofpacket; // master_secure_master_limiter:rsp_src_endofpacket -> master_secure_master_agent:rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_0_f2h_axi_slave_wr_burst_adapter:sink0_valid
wire [228:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_0_f2h_axi_slave_wr_burst_adapter:sink0_data
wire cmd_mux_src_ready; // hps_0_f2h_axi_slave_wr_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_0_f2h_axi_slave_wr_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_0_f2h_axi_slave_wr_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_0_f2h_axi_slave_wr_burst_adapter:sink0_endofpacket
wire hps_0_f2h_axi_slave_wr_burst_adapter_source0_valid; // hps_0_f2h_axi_slave_wr_burst_adapter:source0_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
wire [228:0] hps_0_f2h_axi_slave_wr_burst_adapter_source0_data; // hps_0_f2h_axi_slave_wr_burst_adapter:source0_data -> hps_0_f2h_axi_slave_agent:write_cp_data
wire hps_0_f2h_axi_slave_wr_burst_adapter_source0_ready; // hps_0_f2h_axi_slave_agent:write_cp_ready -> hps_0_f2h_axi_slave_wr_burst_adapter:source0_ready
wire [1:0] hps_0_f2h_axi_slave_wr_burst_adapter_source0_channel; // hps_0_f2h_axi_slave_wr_burst_adapter:source0_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
wire hps_0_f2h_axi_slave_wr_burst_adapter_source0_startofpacket; // hps_0_f2h_axi_slave_wr_burst_adapter:source0_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
wire hps_0_f2h_axi_slave_wr_burst_adapter_source0_endofpacket; // hps_0_f2h_axi_slave_wr_burst_adapter:source0_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> hps_0_f2h_axi_slave_rd_burst_adapter:sink0_valid
wire [228:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> hps_0_f2h_axi_slave_rd_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // hps_0_f2h_axi_slave_rd_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> hps_0_f2h_axi_slave_rd_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> hps_0_f2h_axi_slave_rd_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> hps_0_f2h_axi_slave_rd_burst_adapter:sink0_endofpacket
wire hps_0_f2h_axi_slave_rd_burst_adapter_source0_valid; // hps_0_f2h_axi_slave_rd_burst_adapter:source0_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
wire [228:0] hps_0_f2h_axi_slave_rd_burst_adapter_source0_data; // hps_0_f2h_axi_slave_rd_burst_adapter:source0_data -> hps_0_f2h_axi_slave_agent:read_cp_data
wire hps_0_f2h_axi_slave_rd_burst_adapter_source0_ready; // hps_0_f2h_axi_slave_agent:read_cp_ready -> hps_0_f2h_axi_slave_rd_burst_adapter:source0_ready
wire [1:0] hps_0_f2h_axi_slave_rd_burst_adapter_source0_channel; // hps_0_f2h_axi_slave_rd_burst_adapter:source0_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
wire hps_0_f2h_axi_slave_rd_burst_adapter_source0_startofpacket; // hps_0_f2h_axi_slave_rd_burst_adapter:source0_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
wire hps_0_f2h_axi_slave_rd_burst_adapter_source0_endofpacket; // hps_0_f2h_axi_slave_rd_burst_adapter:source0_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [228:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [228:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [228:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [228:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [1:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [228:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [228:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [228:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [228:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [1:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire [0:0] master_secure_master_limiter_cmd_src_valid; // master_secure_master_limiter:cmd_src_valid -> master_secure_master_cmd_width_adapter:in_valid
wire [120:0] master_secure_master_limiter_cmd_src_data; // master_secure_master_limiter:cmd_src_data -> master_secure_master_cmd_width_adapter:in_data
wire master_secure_master_limiter_cmd_src_ready; // master_secure_master_cmd_width_adapter:in_ready -> master_secure_master_limiter:cmd_src_ready
wire [1:0] master_secure_master_limiter_cmd_src_channel; // master_secure_master_limiter:cmd_src_channel -> master_secure_master_cmd_width_adapter:in_channel
wire master_secure_master_limiter_cmd_src_startofpacket; // master_secure_master_limiter:cmd_src_startofpacket -> master_secure_master_cmd_width_adapter:in_startofpacket
wire master_secure_master_limiter_cmd_src_endofpacket; // master_secure_master_limiter:cmd_src_endofpacket -> master_secure_master_cmd_width_adapter:in_endofpacket
wire master_secure_master_cmd_width_adapter_src_valid; // master_secure_master_cmd_width_adapter:out_valid -> cmd_demux_001:sink_valid
wire [228:0] master_secure_master_cmd_width_adapter_src_data; // master_secure_master_cmd_width_adapter:out_data -> cmd_demux_001:sink_data
wire master_secure_master_cmd_width_adapter_src_ready; // cmd_demux_001:sink_ready -> master_secure_master_cmd_width_adapter:out_ready
wire [1:0] master_secure_master_cmd_width_adapter_src_channel; // master_secure_master_cmd_width_adapter:out_channel -> cmd_demux_001:sink_channel
wire master_secure_master_cmd_width_adapter_src_startofpacket; // master_secure_master_cmd_width_adapter:out_startofpacket -> cmd_demux_001:sink_startofpacket
wire master_secure_master_cmd_width_adapter_src_endofpacket; // master_secure_master_cmd_width_adapter:out_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> master_secure_master_rsp_width_adapter:in_valid
wire [228:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> master_secure_master_rsp_width_adapter:in_data
wire rsp_mux_001_src_ready; // master_secure_master_rsp_width_adapter:in_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> master_secure_master_rsp_width_adapter:in_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> master_secure_master_rsp_width_adapter:in_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> master_secure_master_rsp_width_adapter:in_endofpacket
wire master_secure_master_rsp_width_adapter_src_valid; // master_secure_master_rsp_width_adapter:out_valid -> master_secure_master_limiter:rsp_sink_valid
wire [120:0] master_secure_master_rsp_width_adapter_src_data; // master_secure_master_rsp_width_adapter:out_data -> master_secure_master_limiter:rsp_sink_data
wire master_secure_master_rsp_width_adapter_src_ready; // master_secure_master_limiter:rsp_sink_ready -> master_secure_master_rsp_width_adapter:out_ready
wire [1:0] master_secure_master_rsp_width_adapter_src_channel; // master_secure_master_rsp_width_adapter:out_channel -> master_secure_master_limiter:rsp_sink_channel
wire master_secure_master_rsp_width_adapter_src_startofpacket; // master_secure_master_rsp_width_adapter:out_startofpacket -> master_secure_master_limiter:rsp_sink_startofpacket
wire master_secure_master_rsp_width_adapter_src_endofpacket; // master_secure_master_rsp_width_adapter:out_endofpacket -> master_secure_master_limiter:rsp_sink_endofpacket
wire [1:0] alt_vip_vfr_vga_avalon_master_limiter_cmd_valid_data; // alt_vip_vfr_vga_avalon_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (128),
.AV_BURSTCOUNT_W (6),
.AV_BYTEENABLE_W (16),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (16),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) alt_vip_vfr_vga_avalon_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (alt_vip_vfr_vga_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (alt_vip_vfr_vga_avalon_master_waitrequest), // .waitrequest
.av_burstcount (alt_vip_vfr_vga_avalon_master_burstcount), // .burstcount
.av_read (alt_vip_vfr_vga_avalon_master_read), // .read
.av_readdata (alt_vip_vfr_vga_avalon_master_readdata), // .readdata
.av_readdatavalid (alt_vip_vfr_vga_avalon_master_readdatavalid), // .readdatavalid
.av_byteenable (16'b1111111111111111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_secure_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_secure_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_secure_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_secure_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_secure_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_secure_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_secure_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_secure_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_secure_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_secure_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_secure_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_secure_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_secure_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_secure_master_waitrequest), // .waitrequest
.av_byteenable (master_secure_master_byteenable), // .byteenable
.av_read (master_secure_master_read), // .read
.av_readdata (master_secure_master_readdata), // .readdata
.av_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.av_write (master_secure_master_write), // .write
.av_writedata (master_secure_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (228),
.PKT_ORI_BURST_SIZE_L (226),
.PKT_RESPONSE_STATUS_H (225),
.PKT_RESPONSE_STATUS_L (224),
.PKT_QOS_H (213),
.PKT_QOS_L (213),
.PKT_DATA_SIDEBAND_H (211),
.PKT_DATA_SIDEBAND_L (211),
.PKT_ADDR_SIDEBAND_H (210),
.PKT_ADDR_SIDEBAND_L (206),
.PKT_BURST_TYPE_H (205),
.PKT_BURST_TYPE_L (204),
.PKT_CACHE_H (223),
.PKT_CACHE_L (220),
.PKT_THREAD_ID_H (216),
.PKT_THREAD_ID_L (216),
.PKT_BURST_SIZE_H (203),
.PKT_BURST_SIZE_L (201),
.PKT_TRANS_EXCLUSIVE (181),
.PKT_TRANS_LOCK (180),
.PKT_BEGIN_BURST (212),
.PKT_PROTECTION_H (219),
.PKT_PROTECTION_L (217),
.PKT_BURSTWRAP_H (200),
.PKT_BURSTWRAP_L (192),
.PKT_BYTE_CNT_H (191),
.PKT_BYTE_CNT_L (182),
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.PKT_DATA_H (127),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_SRC_ID_H (214),
.PKT_SRC_ID_L (214),
.PKT_DEST_ID_H (215),
.PKT_DEST_ID_L (215),
.ST_DATA_W (229),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (511),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alt_vip_vfr_vga_avalon_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (alt_vip_vfr_vga_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (alt_vip_vfr_vga_avalon_master_agent_cp_valid), // cp.valid
.cp_data (alt_vip_vfr_vga_avalon_master_agent_cp_data), // .data
.cp_startofpacket (alt_vip_vfr_vga_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (alt_vip_vfr_vga_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (alt_vip_vfr_vga_avalon_master_agent_cp_ready), // .ready
.rp_valid (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_valid), // rp.valid
.rp_data (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_data), // .data
.rp_channel (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (120),
.PKT_ORI_BURST_SIZE_L (118),
.PKT_RESPONSE_STATUS_H (117),
.PKT_RESPONSE_STATUS_L (116),
.PKT_QOS_H (105),
.PKT_QOS_L (105),
.PKT_DATA_SIDEBAND_H (103),
.PKT_DATA_SIDEBAND_L (103),
.PKT_ADDR_SIDEBAND_H (102),
.PKT_ADDR_SIDEBAND_L (98),
.PKT_BURST_TYPE_H (97),
.PKT_BURST_TYPE_L (96),
.PKT_CACHE_H (115),
.PKT_CACHE_L (112),
.PKT_THREAD_ID_H (108),
.PKT_THREAD_ID_L (108),
.PKT_BURST_SIZE_H (95),
.PKT_BURST_SIZE_L (93),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (104),
.PKT_PROTECTION_H (111),
.PKT_PROTECTION_L (109),
.PKT_BURSTWRAP_H (92),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (106),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (107),
.PKT_DEST_ID_L (107),
.ST_DATA_W (121),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (1),
.BURSTWRAP_VALUE (511),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_secure_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_secure_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_secure_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_secure_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_secure_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_secure_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_secure_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_secure_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_secure_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_secure_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_secure_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_secure_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_secure_master_agent_cp_valid), // cp.valid
.cp_data (master_secure_master_agent_cp_data), // .data
.cp_startofpacket (master_secure_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_secure_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_secure_master_agent_cp_ready), // .ready
.rp_valid (master_secure_master_limiter_rsp_src_valid), // rp.valid
.rp_data (master_secure_master_limiter_rsp_src_data), // .data
.rp_channel (master_secure_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (master_secure_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (master_secure_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (master_secure_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_slave_ni #(
.PKT_QOS_H (213),
.PKT_QOS_L (213),
.PKT_THREAD_ID_H (216),
.PKT_THREAD_ID_L (216),
.PKT_RESPONSE_STATUS_H (225),
.PKT_RESPONSE_STATUS_L (224),
.PKT_BEGIN_BURST (212),
.PKT_CACHE_H (223),
.PKT_CACHE_L (220),
.PKT_DATA_SIDEBAND_H (211),
.PKT_DATA_SIDEBAND_L (211),
.PKT_ADDR_SIDEBAND_H (210),
.PKT_ADDR_SIDEBAND_L (206),
.PKT_BURST_TYPE_H (205),
.PKT_BURST_TYPE_L (204),
.PKT_PROTECTION_H (219),
.PKT_PROTECTION_L (217),
.PKT_BURST_SIZE_H (203),
.PKT_BURST_SIZE_L (201),
.PKT_BURSTWRAP_H (200),
.PKT_BURSTWRAP_L (192),
.PKT_BYTE_CNT_H (191),
.PKT_BYTE_CNT_L (182),
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_TRANS_EXCLUSIVE (181),
.PKT_TRANS_LOCK (180),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.PKT_DATA_H (127),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_SRC_ID_H (214),
.PKT_SRC_ID_L (214),
.PKT_DEST_ID_H (215),
.PKT_DEST_ID_L (215),
.PKT_ORI_BURST_SIZE_L (226),
.PKT_ORI_BURST_SIZE_H (228),
.ADDR_USER_WIDTH (5),
.DATA_USER_WIDTH (1),
.ST_DATA_W (229),
.ADDR_WIDTH (32),
.RDATA_WIDTH (128),
.WDATA_WIDTH (128),
.ST_CHANNEL_W (2),
.AXI_SLAVE_ID_W (8),
.PASS_ID_TO_SLAVE (0),
.AXI_VERSION ("AXI3"),
.WRITE_ACCEPTANCE_CAPABILITY (8),
.READ_ACCEPTANCE_CAPABILITY (8)
) hps_0_f2h_axi_slave_agent (
.aclk (clk_0_clk_clk), // clock_sink.clk
.aresetn (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // reset_sink.reset_n
.read_cp_valid (hps_0_f2h_axi_slave_rd_burst_adapter_source0_valid), // read_cp.valid
.read_cp_ready (hps_0_f2h_axi_slave_rd_burst_adapter_source0_ready), // .ready
.read_cp_data (hps_0_f2h_axi_slave_rd_burst_adapter_source0_data), // .data
.read_cp_channel (hps_0_f2h_axi_slave_rd_burst_adapter_source0_channel), // .channel
.read_cp_startofpacket (hps_0_f2h_axi_slave_rd_burst_adapter_source0_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_f2h_axi_slave_rd_burst_adapter_source0_endofpacket), // .endofpacket
.write_cp_ready (hps_0_f2h_axi_slave_wr_burst_adapter_source0_ready), // write_cp.ready
.write_cp_valid (hps_0_f2h_axi_slave_wr_burst_adapter_source0_valid), // .valid
.write_cp_data (hps_0_f2h_axi_slave_wr_burst_adapter_source0_data), // .data
.write_cp_channel (hps_0_f2h_axi_slave_wr_burst_adapter_source0_channel), // .channel
.write_cp_startofpacket (hps_0_f2h_axi_slave_wr_burst_adapter_source0_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_f2h_axi_slave_wr_burst_adapter_source0_endofpacket), // .endofpacket
.read_rp_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // read_rp.ready
.read_rp_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.read_rp_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.read_rp_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.write_rp_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // write_rp.ready
.write_rp_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.write_rp_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.awid (hps_0_f2h_axi_slave_awid), // altera_axi_master.awid
.awaddr (hps_0_f2h_axi_slave_awaddr), // .awaddr
.awlen (hps_0_f2h_axi_slave_awlen), // .awlen
.awsize (hps_0_f2h_axi_slave_awsize), // .awsize
.awburst (hps_0_f2h_axi_slave_awburst), // .awburst
.awlock (hps_0_f2h_axi_slave_awlock), // .awlock
.awcache (hps_0_f2h_axi_slave_awcache), // .awcache
.awprot (hps_0_f2h_axi_slave_awprot), // .awprot
.awuser (hps_0_f2h_axi_slave_awuser), // .awuser
.awvalid (hps_0_f2h_axi_slave_awvalid), // .awvalid
.awready (hps_0_f2h_axi_slave_awready), // .awready
.wid (hps_0_f2h_axi_slave_wid), // .wid
.wdata (hps_0_f2h_axi_slave_wdata), // .wdata
.wstrb (hps_0_f2h_axi_slave_wstrb), // .wstrb
.wlast (hps_0_f2h_axi_slave_wlast), // .wlast
.wvalid (hps_0_f2h_axi_slave_wvalid), // .wvalid
.wready (hps_0_f2h_axi_slave_wready), // .wready
.bid (hps_0_f2h_axi_slave_bid), // .bid
.bresp (hps_0_f2h_axi_slave_bresp), // .bresp
.bvalid (hps_0_f2h_axi_slave_bvalid), // .bvalid
.bready (hps_0_f2h_axi_slave_bready), // .bready
.arid (hps_0_f2h_axi_slave_arid), // .arid
.araddr (hps_0_f2h_axi_slave_araddr), // .araddr
.arlen (hps_0_f2h_axi_slave_arlen), // .arlen
.arsize (hps_0_f2h_axi_slave_arsize), // .arsize
.arburst (hps_0_f2h_axi_slave_arburst), // .arburst
.arlock (hps_0_f2h_axi_slave_arlock), // .arlock
.arcache (hps_0_f2h_axi_slave_arcache), // .arcache
.arprot (hps_0_f2h_axi_slave_arprot), // .arprot
.aruser (hps_0_f2h_axi_slave_aruser), // .aruser
.arvalid (hps_0_f2h_axi_slave_arvalid), // .arvalid
.arready (hps_0_f2h_axi_slave_arready), // .arready
.rid (hps_0_f2h_axi_slave_rid), // .rid
.rdata (hps_0_f2h_axi_slave_rdata), // .rdata
.rresp (hps_0_f2h_axi_slave_rresp), // .rresp
.rlast (hps_0_f2h_axi_slave_rlast), // .rlast
.rvalid (hps_0_f2h_axi_slave_rvalid), // .rvalid
.rready (hps_0_f2h_axi_slave_rready) // .rready
);
soc_system_mm_interconnect_0_router router (
.sink_ready (alt_vip_vfr_vga_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (alt_vip_vfr_vga_avalon_master_agent_cp_valid), // .valid
.sink_data (alt_vip_vfr_vga_avalon_master_agent_cp_data), // .data
.sink_startofpacket (alt_vip_vfr_vga_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (alt_vip_vfr_vga_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (master_secure_master_agent_cp_ready), // sink.ready
.sink_valid (master_secure_master_agent_cp_valid), // .valid
.sink_data (master_secure_master_agent_cp_data), // .data
.sink_startofpacket (master_secure_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_secure_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_002 router_003 (
.sink_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (215),
.PKT_DEST_ID_L (215),
.PKT_SRC_ID_H (214),
.PKT_SRC_ID_L (214),
.PKT_BYTE_CNT_H (191),
.PKT_BYTE_CNT_L (182),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.MAX_OUTSTANDING_RESPONSES (18),
.PIPELINED (0),
.ST_DATA_W (229),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) alt_vip_vfr_vga_avalon_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_data), // .data
.cmd_src_channel (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_data), // .data
.rsp_src_channel (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (alt_vip_vfr_vga_avalon_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (alt_vip_vfr_vga_avalon_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (107),
.PKT_DEST_ID_L (107),
.PKT_SRC_ID_H (106),
.PKT_SRC_ID_L (106),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (18),
.PIPELINED (0),
.ST_DATA_W (121),
.ST_CHANNEL_W (2),
.VALID_WIDTH (1),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) master_secure_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (master_secure_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (master_secure_master_limiter_cmd_src_data), // .data
.cmd_src_channel (master_secure_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (master_secure_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (master_secure_master_limiter_cmd_src_endofpacket), // .endofpacket
.cmd_src_valid (master_secure_master_limiter_cmd_src_valid), // .valid
.rsp_sink_ready (master_secure_master_rsp_width_adapter_src_ready), // rsp_sink.ready
.rsp_sink_valid (master_secure_master_rsp_width_adapter_src_valid), // .valid
.rsp_sink_channel (master_secure_master_rsp_width_adapter_src_channel), // .channel
.rsp_sink_data (master_secure_master_rsp_width_adapter_src_data), // .data
.rsp_sink_startofpacket (master_secure_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (master_secure_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.rsp_src_ready (master_secure_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (master_secure_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (master_secure_master_limiter_rsp_src_data), // .data
.rsp_src_channel (master_secure_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (master_secure_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (master_secure_master_limiter_rsp_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_BEGIN_BURST (212),
.PKT_BYTE_CNT_H (191),
.PKT_BYTE_CNT_L (182),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_BURST_SIZE_H (203),
.PKT_BURST_SIZE_L (201),
.PKT_BURST_TYPE_H (205),
.PKT_BURST_TYPE_L (204),
.PKT_BURSTWRAP_H (200),
.PKT_BURSTWRAP_L (192),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.OUT_NARROW_SIZE (1),
.IN_NARROW_SIZE (1),
.OUT_FIXED (1),
.OUT_COMPLETE_WRAP (1),
.ST_DATA_W (229),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (190),
.OUT_BURSTWRAP_H (200),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (511),
.BURSTWRAP_CONST_VALUE (511),
.ADAPTER_VERSION ("13.1")
) hps_0_f2h_axi_slave_wr_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (hps_0_f2h_axi_slave_wr_burst_adapter_source0_valid), // source0.valid
.source0_data (hps_0_f2h_axi_slave_wr_burst_adapter_source0_data), // .data
.source0_channel (hps_0_f2h_axi_slave_wr_burst_adapter_source0_channel), // .channel
.source0_startofpacket (hps_0_f2h_axi_slave_wr_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (hps_0_f2h_axi_slave_wr_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (hps_0_f2h_axi_slave_wr_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_BEGIN_BURST (212),
.PKT_BYTE_CNT_H (191),
.PKT_BYTE_CNT_L (182),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_BURST_SIZE_H (203),
.PKT_BURST_SIZE_L (201),
.PKT_BURST_TYPE_H (205),
.PKT_BURST_TYPE_L (204),
.PKT_BURSTWRAP_H (200),
.PKT_BURSTWRAP_L (192),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.OUT_NARROW_SIZE (1),
.IN_NARROW_SIZE (1),
.OUT_FIXED (1),
.OUT_COMPLETE_WRAP (1),
.ST_DATA_W (229),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (190),
.OUT_BURSTWRAP_H (200),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (511),
.BURSTWRAP_CONST_VALUE (511),
.ADAPTER_VERSION ("13.1")
) hps_0_f2h_axi_slave_rd_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (hps_0_f2h_axi_slave_rd_burst_adapter_source0_valid), // source0.valid
.source0_data (hps_0_f2h_axi_slave_rd_burst_adapter_source0_data), // .data
.source0_channel (hps_0_f2h_axi_slave_rd_burst_adapter_source0_channel), // .channel
.source0_startofpacket (hps_0_f2h_axi_slave_rd_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (hps_0_f2h_axi_slave_rd_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (hps_0_f2h_axi_slave_rd_burst_adapter_source0_ready) // .ready
);
soc_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_channel), // .channel
.sink_data (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_data), // .data
.sink_startofpacket (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (alt_vip_vfr_vga_avalon_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (alt_vip_vfr_vga_avalon_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (master_secure_master_cmd_width_adapter_src_ready), // sink.ready
.sink_channel (master_secure_master_cmd_width_adapter_src_channel), // .channel
.sink_data (master_secure_master_cmd_width_adapter_src_data), // .data
.sink_startofpacket (master_secure_master_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (master_secure_master_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (master_secure_master_cmd_width_adapter_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_001 rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (83),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (92),
.IN_PKT_BURSTWRAP_L (84),
.IN_PKT_BURST_SIZE_H (95),
.IN_PKT_BURST_SIZE_L (93),
.IN_PKT_RESPONSE_STATUS_H (117),
.IN_PKT_RESPONSE_STATUS_L (116),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (97),
.IN_PKT_BURST_TYPE_L (96),
.IN_PKT_ORI_BURST_SIZE_L (118),
.IN_PKT_ORI_BURST_SIZE_H (120),
.IN_ST_DATA_W (121),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (191),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (203),
.OUT_PKT_BURST_SIZE_L (201),
.OUT_PKT_RESPONSE_STATUS_H (225),
.OUT_PKT_RESPONSE_STATUS_L (224),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (205),
.OUT_PKT_BURST_TYPE_L (204),
.OUT_PKT_ORI_BURST_SIZE_L (226),
.OUT_PKT_ORI_BURST_SIZE_H (228),
.OUT_ST_DATA_W (229),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) master_secure_master_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (master_secure_master_limiter_cmd_src_valid), // sink.valid
.in_channel (master_secure_master_limiter_cmd_src_channel), // .channel
.in_startofpacket (master_secure_master_limiter_cmd_src_startofpacket), // .startofpacket
.in_endofpacket (master_secure_master_limiter_cmd_src_endofpacket), // .endofpacket
.in_ready (master_secure_master_limiter_cmd_src_ready), // .ready
.in_data (master_secure_master_limiter_cmd_src_data), // .data
.out_endofpacket (master_secure_master_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (master_secure_master_cmd_width_adapter_src_data), // .data
.out_channel (master_secure_master_cmd_width_adapter_src_channel), // .channel
.out_valid (master_secure_master_cmd_width_adapter_src_valid), // .valid
.out_ready (master_secure_master_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (master_secure_master_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (191),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_TRANS_WRITE (178),
.IN_PKT_BURSTWRAP_H (200),
.IN_PKT_BURSTWRAP_L (192),
.IN_PKT_BURST_SIZE_H (203),
.IN_PKT_BURST_SIZE_L (201),
.IN_PKT_RESPONSE_STATUS_H (225),
.IN_PKT_RESPONSE_STATUS_L (224),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (205),
.IN_PKT_BURST_TYPE_L (204),
.IN_PKT_ORI_BURST_SIZE_L (226),
.IN_PKT_ORI_BURST_SIZE_H (228),
.IN_ST_DATA_W (229),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (83),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (95),
.OUT_PKT_BURST_SIZE_L (93),
.OUT_PKT_RESPONSE_STATUS_H (117),
.OUT_PKT_RESPONSE_STATUS_L (116),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (97),
.OUT_PKT_BURST_TYPE_L (96),
.OUT_PKT_ORI_BURST_SIZE_L (118),
.OUT_PKT_ORI_BURST_SIZE_H (120),
.OUT_ST_DATA_W (121),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) master_secure_master_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_mux_001_src_valid), // sink.valid
.in_channel (rsp_mux_001_src_channel), // .channel
.in_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.in_ready (rsp_mux_001_src_ready), // .ready
.in_data (rsp_mux_001_src_data), // .data
.out_endofpacket (master_secure_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (master_secure_master_rsp_width_adapter_src_data), // .data
.out_channel (master_secure_master_rsp_width_adapter_src_channel), // .channel
.out_valid (master_secure_master_rsp_width_adapter_src_valid), // .valid
.out_ready (master_secure_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (master_secure_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_sample_multi_next_buckets_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_sample_multi_next_buckets(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
nfa_accept_sample_multi_next_buckets_ram nfa_accept_sample_multi_next_buckets_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_2_V
`define SKY130_FD_SC_LS__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_2_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_a (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "c.matrix_mult.autotvin_a.dat",
TV_OUT = "impl_rtl.matrix_mult.autotvout_a.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 8;
parameter ADDR_WIDTH = 32'd 5;
parameter DEPTH = 32'd 25;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_SYMBOL_V
`define SKY130_FD_SC_LP__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_SYMBOL_V
|
/// date :2016/3/4
/// engineer :ZhaiShaoMin
/// module name :memory_state_data_ram
/// module function : here is placed the ram of state and data
/// because of design division
/// note: state[3:0] is directory
/// state[5:4] is home directory state .00 :R(dir),01 :W(id),10 TR(dir),11 TW(id).
/// every home memeory has 2KB
module memory_state_data_ram(// input
clk,
state_we_in,
state_re_in,
addr_in,
state_in,
data_we_in,
data_re_in,
data_in,
// output
state_out,
data_out);
input clk;
input state_we_in;
input state_re_in;
input [31:0] addr_in;
input [5:0] state_in;
input data_we_in;
input data_re_in;
input [127:0] data_in;
//output
output [5:0] state_out;
output [127:0] data_out;
/*wire [31:0] seled_addr;
wire [5:0] m_state_out;
wire [127:0] seled_data;
wire [127:0] data_read; */
/////////////////////////////////////////////////////////////////////////
////////////// directory_ram and data_ram////////////////////////////////////
////////////////////////////////////////////////////////////////////////
SP_BRAM_SRd #(128,6,7) tag_ram(.clk(clk), .we(state_we_in), .re(state_re_in), .a(addr_in[10:4]), .di(state_in), .dout(state_out));
SP_BRAM_SRd #(128,128,7) data_ram(.clk(clk), .we(data_we_in), .re(data_re_in), .a(addr_in[10:4]), .di(data_in), .dout(data_out));
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: vga_font_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vga_font_rom (
address,
clock,
q);
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../font.rif"
`else
altsyncram_component.init_file = "../font.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../font.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../font.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LFSR scrambler
*/
module lfsr_scramble #
(
// width of LFSR
parameter LFSR_WIDTH = 58,
// LFSR polynomial
parameter LFSR_POLY = 58'h8000000001,
// Initial state
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}},
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// bit-reverse input and output
parameter REVERSE = 1,
// width of data bus
parameter DATA_WIDTH = 64,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_valid,
output wire [DATA_WIDTH-1:0] data_out
);
/*
Fully parametrizable combinatorial parallel LFSR CRC module. Implements an unrolled LFSR
next state computation.
Ports:
clk
Clock input
rst
Reset module, set state to LFSR_INIT
data_in
Unscrambled data input (DATA_WIDTH bits)
data_in_valid
Shift input data through CRC when asserted
data_out
Scrambled data output (DATA_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_INIT
Initial state of LFSR. Defaults to all 1s.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output.
DATA_WIDTH
Specify width of the data bus. The module will perform one shift per input data bit.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT;
reg [DATA_WIDTH-1:0] output_reg = 0;
wire [DATA_WIDTH-1:0] lfsr_data;
wire [LFSR_WIDTH-1:0] lfsr_state;
assign data_out = output_reg;
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(0),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
lfsr_inst (
.data_in(data_in),
.state_in(state_reg),
.data_out(lfsr_data),
.state_out(lfsr_state)
);
always @(posedge clk) begin
if (rst) begin
state_reg <= LFSR_INIT;
output_reg <= 0;
end else begin
if (data_in_valid) begin
state_reg <= lfsr_state;
output_reg <= lfsr_data;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_1_V
`define SKY130_FD_SC_HS__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_1 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_1 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_1_V
|
module var15_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O;
output valid;
wire [7:0] min_value = 8'd120;
wire [7:0] max_weight = 8'd60;
wire [7:0] max_volume = 8'd60;
wire [7:0] total_value =
A * 8'd4
+ B * 8'd8
+ C * 8'd0
+ D * 8'd20
+ E * 8'd10
+ F * 8'd12
+ G * 8'd18
+ H * 8'd14
+ I * 8'd6
+ J * 8'd15
+ K * 8'd30
+ L * 8'd8
+ M * 8'd16
+ N * 8'd18
+ O * 8'd18;
wire [7:0] total_weight =
A * 8'd28
+ B * 8'd8
+ C * 8'd27
+ D * 8'd18
+ E * 8'd27
+ F * 8'd28
+ G * 8'd6
+ H * 8'd1
+ I * 8'd20
+ J * 8'd0
+ K * 8'd5
+ L * 8'd13
+ M * 8'd8
+ N * 8'd14
+ O * 8'd22;
wire [7:0] total_volume =
A * 8'd27
+ B * 8'd27
+ C * 8'd4
+ D * 8'd4
+ E * 8'd0
+ F * 8'd24
+ G * 8'd4
+ H * 8'd20
+ I * 8'd12
+ J * 8'd15
+ K * 8'd5
+ L * 8'd2
+ M * 8'd9
+ N * 8'd28
+ O * 8'd19;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
//=======================================================
// ECE3400 Fall 2017
// Lab 3: Template top-level module
//
// Top-level skeleton from Terasic
// Modified by Claire Chen for ECE3400 Fall 2017
//=======================================================
`define ONE_SEC 25000000
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
localparam ONE_SEC = 25000000; // one second in 25MHz clock cycles
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//output [7:0] q; //DAC
/////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg CLOCK_25;
wire reset; // active high reset signal
reg address; // sin table stuff
wire [9:0] PIXEL_COORD_X; // current x-coord from VGA driver
wire [9:0] PIXEL_COORD_Y; // current y-coord from VGA driver
wire [7:0] PIXEL_COLOR; // input 8-bit pixel color for current coords
reg [24:0] led_counter; // timer to keep track of when to toggle LED
reg led_state; // 1 is on, 0 is off
reg [7:0] q; //DAC
// Module outputs coordinates of next pixel to be written onto screen
VGA_DRIVER driver(
.RESET(reset),
.CLOCK(CLOCK_25),
.PIXEL_COLOR_IN(PIXEL_COLOR),
.PIXEL_X(PIXEL_COORD_X),
.PIXEL_Y(PIXEL_COORD_Y),
.PIXEL_COLOR_OUT({GPIO_0_D[9],GPIO_0_D[11],GPIO_0_D[13],GPIO_0_D[15],GPIO_0_D[17],GPIO_0_D[19],GPIO_0_D[21],GPIO_0_D[23]}),
.H_SYNC_NEG(GPIO_0_D[7]),
.V_SYNC_NEG(GPIO_0_D[5])
);
assign reset = ~KEY[0]; // reset when KEY0 is pressed
assign PIXEL_COLOR = 8'b000_111_00; // Green
assign LED[0] = led_state;
assign GPIO_0_D[7:0] = q[7:0];
reg [7:0] sin[0:15];
//PUT the sintable in rom!
initial
begin
$readmemb("sinetable.txt", sin);
end
//=======================================================
// Structural coding
//=======================================================
// Generate 25MHz clock for VGA, FPGA has 50 MHz clock
always @ (posedge CLOCK_50) begin
CLOCK_25 <= ~CLOCK_25;
end // always @ (posedge CLOCK_50)
// Simple state machine to toggle LED0 every one second
always @ (posedge CLOCK_25) begin
if (reset) begin
led_state <= 1'b0;
led_counter <= 25'b0;
end
if (led_counter == ONE_SEC) begin
led_state <= ~led_state;
led_counter <= 25'b0;
end
else begin
led_state <= led_state;
led_counter <= led_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
// Read from requested address of ROM
always @ (posedge CLOCK_25)
begin
q <= sin[address];
address = address+1;
end
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [22:0] c;
// Output of stage 2
wire [22:0] cx;
// Output of stage 3
wire [10:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [22:0] e;
reg [22:0] r_e;
// 2nd stage
reg [22:0] r_c;
reg [22:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [22:0] r_qx;
reg [10:0] rb;
reg clk,reset;
reg [22:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000100000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00001000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00100000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
//------------------------------------------------------------------------------
// File : tri_mode_eth_mac_v5_2_block.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This is the block level Verilog design for the Tri-Mode
// Ethernet MAC Example Design.
//
// This block level:
//
// * instantiates the axi4-lite ipif module to convert to the core IPIC
// interface
//
// * instantiates appropriate PHY interface module (GMII/MII/RGMII)
// as required based on the user configuration;
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Tri-Mode Ethernet MAC User Gude for further information.
//
//
// -----------------------------------------|
// | BLOCK LEVEL WRAPPER |
// | |
// | --------------------- |
// | | ETHERNET MAC | |
// | | CORE | --------- |
// | | | | | |
// --|--->| Tx Tx |--| |--->|
// | | AXI PHY | | | |
// | | I/F I/F | | | |
// | | | | PHY | |
// | | | | I/F | |
// | | | | | |
// | | Rx Rx | | | |
// | | AXI PHY | | | |
// <-|----| I/F I/F |<-| |<---|
// | | | --------- |
// | | | |
// | --------------------- |
// | | | |
// | -------------------- |
// | | | |
// --|------>| AXI4-Lite IPIF | |
// <-|-------| | |
// | | | |
// | -------------------- |
// | |
// -----------------------------------------|
//
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// The entity declaration for the block level example design.
//------------------------------------------------------------------------------
module tri_mode_eth_mac_v5_2_block #(
parameter C_BASE_ADDRESS = 32'h00
) (
input gtx_clk,
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
// Receiver Interface
//--------------------------
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
output rx_mac_aclk,
output rx_reset,
output [7:0] rx_axis_mac_tdata,
output rx_axis_mac_tvalid,
output rx_axis_mac_tlast,
output rx_axis_mac_tuser,
// Transmitter Interface
//-----------------------------
input [7:0] tx_ifg_delay,
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
output tx_reset,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
input tx_axis_mac_tuser,
output tx_axis_mac_tready,
output tx_collision,
output tx_retransmit,
// MAC Control Interface
//----------------------
input pause_req,
input [15:0] pause_val,
// Reference clock for IDELAYCTRL's
input refclk,
// GMII Interface
//---------------
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
output gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
input gmii_col,
input gmii_crs,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
// AXI-Lite Interface
//---------------
input s_axi_aclk,
input s_axi_resetn,
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready
);
//---------------------------------------------------------------------------
// internal signals used in this block level wrapper.
//---------------------------------------------------------------------------
wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL refclk domain.
reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse.
reg idelayctrl_reset; // The reset pulse for the IDELAYCTRL.
wire gmii_tx_en_int; // Internal gmii_tx_en signal.
wire gmii_tx_er_int; // Internal gmii_tx_er signal.
wire [7:0] gmii_txd_int; // Internal gmii_txd signal.
wire gmii_rx_dv_int; // gmii_rx_dv registered in IOBs.
wire gmii_rx_er_int; // gmii_rx_er registered in IOBs.
wire [7:0] gmii_rxd_int; // gmii_rxd registered in IOBs.
wire gmii_col_int; // Collision signal from the PHY module
wire gmii_crs_int; // Carrier Sense signal from the PHY module
wire speedis100; // Asserted when speed is 100Mb/s.
wire speedis10100; // Asserted when speed is 10Mb/s or 100Mb/s.
(* KEEP = "TRUE" *)
wire rx_mac_aclk_int; // Internal receive gmii/mii clock signal.
(* KEEP = "TRUE" *)
wire tx_mac_aclk_int; // Internal transmit gmii/mii clock signal.
wire glbl_rst;
wire tx_reset_int; // Synchronous reset in the MAC and gmii Tx domain
wire rx_reset_int; // Synchronous reset in the MAC and gmii Rx domain
wire [27:0] rx_statistics_vector_int;
wire rx_statistics_valid_int;
wire [31:0] tx_statistics_vector_int;
wire tx_statistics_valid_int;
wire bus2ip_clk;
wire bus2ip_reset;
wire [31:0] bus2ip_addr;
wire bus2ip_cs;
wire bus2ip_rdce;
wire bus2ip_wrce;
wire [31:0] bus2ip_data;
wire [31:0] ip2bus_data;
wire ip2bus_wrack;
wire ip2bus_rdack;
wire ip2bus_error;
// assign outputs
assign rx_reset = rx_reset_int;
assign tx_reset = tx_reset_int;
// Assign the internal clock signals to output ports.
assign rx_mac_aclk = rx_mac_aclk_int;
assign glbl_rst = !glbl_rstn;
//---------------------------------------------------------------------------
// An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
// mode of the IDELAY.
// All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
// to be LOC'ed in the UCF file.
//---------------------------------------------------------------------------
IDELAYCTRL dlyctrl (
.RDY (),
.REFCLK (refclk),
.RST (idelayctrl_reset)
);
// Create a synchronous reset in the IDELAYCTRL refclk clock domain.
reset_sync idelayctrl_reset_gen (
.clk (refclk),
.enable (1'b1),
.reset_in (glbl_rst),
.reset_out (idelayctrl_reset_sync)
);
// Reset circuitry for the IDELAYCTRL reset.
// The IDELAYCTRL must experience a pulse which is at least 50 ns in
// duration. This is ten clock cycles of the 200MHz refclk. Here we
// drive the reset pulse for 12 clock cycles.
always @(posedge refclk)
begin
if (idelayctrl_reset_sync) begin
idelay_reset_cnt <= 4'b0000;
idelayctrl_reset <= 1'b1;
end
else begin
case (idelay_reset_cnt)
4'b0000 : idelay_reset_cnt <= 4'b0001;
4'b0001 : idelay_reset_cnt <= 4'b0010;
4'b0010 : idelay_reset_cnt <= 4'b0011;
4'b0011 : idelay_reset_cnt <= 4'b0100;
4'b0100 : idelay_reset_cnt <= 4'b0101;
4'b0101 : idelay_reset_cnt <= 4'b0110;
4'b0110 : idelay_reset_cnt <= 4'b0111;
4'b0111 : idelay_reset_cnt <= 4'b1000;
4'b1000 : idelay_reset_cnt <= 4'b1001;
4'b1001 : idelay_reset_cnt <= 4'b1010;
4'b1010 : idelay_reset_cnt <= 4'b1011;
4'b1011 : idelay_reset_cnt <= 4'b1100;
default : idelay_reset_cnt <= 4'b1100;
endcase
if (idelay_reset_cnt === 4'b1100) begin
idelayctrl_reset <= 1'b0;
end
else begin
idelayctrl_reset <= 1'b1;
end
end
end
assign tx_mac_aclk_int = gtx_clk;
//---------------------------------------------------------------------------
// Instantiate GMII Interface
//---------------------------------------------------------------------------
// Instantiate the GMII physical interface logic
gmii_if gmii_interface(
// Synchronous resets
.tx_reset (tx_reset_int),
.rx_reset (rx_reset_int),
// The following ports are the GMII physical interface: these will be at
// pins on the FPGA
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
// The following ports are the internal GMII connections from IOB logic
// to the TEMAC core
.txd_from_mac (gmii_txd_int),
.tx_en_from_mac (gmii_tx_en_int),
.tx_er_from_mac (gmii_tx_er_int),
.tx_clk (tx_mac_aclk_int),
.col_to_mac (gmii_col_int),
.crs_to_mac (gmii_crs_int),
.rxd_to_mac (gmii_rxd_int),
.rx_dv_to_mac (gmii_rx_dv_int),
.rx_er_to_mac (gmii_rx_er_int),
// Receiver clock for the MAC and Client Logic
.rx_clk (rx_mac_aclk_int)
);
//---------------------------------------------------------------------------
// Instantiate the axi_ipif block
//---------------------------------------------------------------------------
axi4_lite_ipif_wrapper #(
.C_BASE_ADDRESS (C_BASE_ADDRESS)
) axi4_lite_ipif (
// System signals
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_resetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// controls to the ipif
.bus2ip_clk (bus2ip_clk),
.bus2ip_reset (bus2ip_reset),
.bus2ip_addr (bus2ip_addr),
.bus2ip_cs (bus2ip_cs),
.bus2ip_rdce (bus2ip_rdce),
.bus2ip_wrce (bus2ip_wrce),
.bus2ip_data (bus2ip_data),
.ip2bus_data (ip2bus_data),
.ip2bus_wrack (ip2bus_wrack),
.ip2bus_rdack (ip2bus_rdack),
.ip2bus_error (ip2bus_error)
);
assign rx_statistics_vector = rx_statistics_vector_int;
assign rx_statistics_valid = rx_statistics_valid_int;
assign tx_statistics_vector = tx_statistics_vector_int;
assign tx_statistics_valid = tx_statistics_valid_int;
//---------------------------------------------------------------------------
// Instantiate the TEMAC core
//---------------------------------------------------------------------------
tri_mode_eth_mac_v5_2 trimac_core(
//----------------------------------------------
// asynchronous reset
.glbl_rstn (glbl_rstn),
.rx_axi_rstn (rx_axi_rstn),
.tx_axi_rstn (tx_axi_rstn),
//----------------------------------------------
// Receiver Interface
.rx_axi_clk (rx_mac_aclk_int),
.rx_reset_out (rx_reset_int),
.rx_axis_mac_tdata (rx_axis_mac_tdata),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid),
.rx_axis_mac_tlast (rx_axis_mac_tlast),
.rx_axis_mac_tuser (rx_axis_mac_tuser),
//----------------------------------------------
// Receiver Statistics
.rx_statistics_vector (rx_statistics_vector_int),
.rx_statistics_valid (rx_statistics_valid_int),
//----------------------------------------------
// Transmitter Interface
.tx_axi_clk (tx_mac_aclk_int),
.tx_reset_out (tx_reset_int),
.tx_axis_mac_tdata (tx_axis_mac_tdata),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid),
.tx_axis_mac_tlast (tx_axis_mac_tlast),
.tx_axis_mac_tuser (tx_axis_mac_tuser),
.tx_axis_mac_tready (tx_axis_mac_tready),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit),
.tx_ifg_delay (tx_ifg_delay),
//----------------------------------------------
// Transmitter Statistics
.tx_statistics_vector (tx_statistics_vector_int),
.tx_statistics_valid (tx_statistics_valid_int),
//----------------------------------------------
// MAC Control Interface
.pause_req (pause_req),
.pause_val (pause_val),
//----------------------------------------------
// Current Speed Indication
.speed_is_100 (speedis100),
.speed_is_10_100 (speedis10100),
//----------------------------------------------
// Physical Interface of the core
.gmii_txd (gmii_txd_int),
.gmii_tx_en (gmii_tx_en_int),
.gmii_tx_er (gmii_tx_er_int),
.gmii_crs (gmii_crs_int),
.gmii_col (gmii_col_int),
.gmii_rxd (gmii_rxd_int),
.gmii_rx_dv (gmii_rx_dv_int),
.gmii_rx_er (gmii_rx_er_int),
//----------------------------------------------
// MDIO Interface
.mdc_out (mdc),
.mdio_in (mdio_i),
.mdio_out (mdio_o),
.mdio_tri (mdio_t),
//----------------------------------------------
// IPIC Interface
.bus2ip_clk (bus2ip_clk),
.bus2ip_reset (bus2ip_reset),
.bus2ip_addr (bus2ip_addr),
.bus2ip_cs (bus2ip_cs),
.bus2ip_rdce (bus2ip_rdce),
.bus2ip_wrce (bus2ip_wrce),
.bus2ip_data (bus2ip_data),
.ip2bus_data (ip2bus_data),
.ip2bus_wrack (ip2bus_wrack),
.ip2bus_rdack (ip2bus_rdack),
.ip2bus_error (ip2bus_error),
.mac_irq ()
);
endmodule
|
// DE1_SoC_Compputer.v
module DE1_SoC_Computer
(
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
// SDRAM
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
// I2C Bus for Configuration of the Audio and Video-In Chips
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
// 40-Pin Headers
GPIO_0,
GPIO_1,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// IR
IRDA_RXD,
IRDA_TXD,
// Pushbuttons
KEY,
// LEDs
LEDR,
// PS2 Ports
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
// Slider Switches
SW,
// Video-In
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
// VGA
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
HPS_DDR3_ADDR,
HPS_DDR3_BA,
HPS_DDR3_CAS_N,
HPS_DDR3_CKE,
HPS_DDR3_CK_N,
HPS_DDR3_CK_P,
HPS_DDR3_CS_N,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_N,
HPS_DDR3_DQS_P,
HPS_DDR3_ODT,
HPS_DDR3_RAS_N,
HPS_DDR3_RESET_N,
HPS_DDR3_RZQ,
HPS_DDR3_WE_N,
// Ethernet
HPS_ENET_GTX_CLK,
HPS_ENET_INT_N,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
// Flash
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
// Accelerometer
HPS_GSENSOR_INT,
// General Purpose I/O
HPS_GPIO,
// I2C
HPS_I2C_CONTROL,
HPS_I2C1_SCLK,
HPS_I2C1_SDAT,
HPS_I2C2_SCLK,
HPS_I2C2_SDAT,
// Pushbutton
HPS_KEY,
// LED
HPS_LED,
// SD Card
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
// SPI
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
// UART
HPS_UART_RX,
HPS_UART_TX,
// USB
HPS_CONV_USB_N,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_STP
);
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input CLOCK4_50;
// ADC
inout ADC_CS_N;
output ADC_DIN;
input ADC_DOUT;
output ADC_SCLK;
// Audio
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
// SDRAM
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_RAS_N;
output DRAM_UDQM;
output DRAM_WE_N;
// I2C Bus for Configuration of the Audio and Video-In Chips
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
// 40-pin headers
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
// Seven Segment Displays
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
// IR
input IRDA_RXD;
output IRDA_TXD;
// Pushbuttons
input [3:0] KEY;
// LEDs
output [9:0] LEDR;
// PS2 Ports
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
// Slider Switches
input [9:0] SW;
// Video-In
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
// VGA
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
output [14:0] HPS_DDR3_ADDR;
output [2:0] HPS_DDR3_BA;
output HPS_DDR3_CAS_N;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_N;
output HPS_DDR3_CK_P;
output HPS_DDR3_CS_N;
output [3:0] HPS_DDR3_DM;
inout [31:0] HPS_DDR3_DQ;
inout [3:0] HPS_DDR3_DQS_N;
inout [3:0] HPS_DDR3_DQS_P;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_N;
output HPS_DDR3_RESET_N;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_N;
// Ethernet
output HPS_ENET_GTX_CLK;
inout HPS_ENET_INT_N;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
input HPS_ENET_RX_CLK;
input [3:0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [3:0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
// Flash
inout [3:0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
// Accelerometer
inout HPS_GSENSOR_INT;
// General Purpose I/O
inout [1:0] HPS_GPIO;
// I2C
inout HPS_I2C_CONTROL;
inout HPS_I2C1_SCLK;
inout HPS_I2C1_SDAT;
inout HPS_I2C2_SCLK;
inout HPS_I2C2_SDAT;
// Pushbutton
inout HPS_KEY;
// LED
inout HPS_LED;
// SD Card
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [3:0] HPS_SD_DATA;
// SPI
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
inout HPS_SPIM_SS;
// UART
input HPS_UART_RX;
output HPS_UART_TX;
// USB
inout HPS_CONV_USB_N;
input HPS_USB_CLKOUT;
inout [70] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_STP;
//=======================================================
// REG/WIRE declarations
//=======================================================
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX1 = 7'b1111111;
//=======================================================
// Bus controller for AVALON bus-master
//=======================================================
// computes DDS for sine wave and fills audio FIFO
// reads audio FIFO and loops it back
// MUST configure (in Qsys) Audio Config module
// -- Line in to ADC
// -- uncheck both bypass options
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
wire bus_ack; // Avalon bus raises this when done
wire [31:0] bus_read_data; // data from Avalon bus
wire rst, hps_rst;
assign rst = ~KEY[0] || hps_rst;
wire [31:0] delta_left;
wire [31:0] delta_right;
wire delta_mode_left, delta_mode_right;
wire [9:0] triangle_wave_max_left, triangle_wave_max_right;
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(CLOCK_50),
.rst(rst | hps_rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data),
.delta_left(delta_left),
.delta_right(delta_right),
.out_sel(SW[9]),
.delta_mode_left(delta_mode_left),
.delta_mode_right(delta_mode_right),
.triangle_wave_max_right(triangle_wave_max_right),
.triangle_wave_max_left(triangle_wave_max_left)
);
Computer_System The_System
(
////////////////////////////////////
// FPGA Side
////////////////////////////////////
// Global signals
.system_pll_ref_clk_clk (CLOCK_50),
.system_pll_ref_reset_reset (1'b0),
// AV Config
.av_config_SCLK (FPGA_I2C_SCLK),
.av_config_SDAT (FPGA_I2C_SDAT),
// Audio Subsystem
.audio_pll_ref_clk_clk (CLOCK3_50),
.audio_pll_ref_reset_reset (1'b0),
.audio_clk_clk (AUD_XCK),
.audio_ADCDAT (AUD_ADCDAT),
.audio_ADCLRCK (AUD_ADCLRCK),
.audio_BCLK (AUD_BCLK),
.audio_DACDAT (AUD_DACDAT),
.audio_DACLRCK (AUD_DACLRCK),
// HPS slaves
.reset_slave_external_connection_export (hps_rst),
.delta_left_slave_external_connection_export (delta_left),
.delta_right_slave_external_connection_export (delta_right),
.triangle_wave_max_left_slave_external_connection_export (triangle_wave_max_left),
.triangle_wave_max_right_slave_external_connection_export (triangle_wave_max_right),
.delta_mode_right_slave_external_connection_export (delta_mode_right),
.delta_mode_left_slave_external_connection_export (delta_mode_left),
// bus-master state machine interface
.bus_master_audio_external_interface_address (bus_addr),
.bus_master_audio_external_interface_byte_enable (bus_byte_enable),
.bus_master_audio_external_interface_read (bus_read),
.bus_master_audio_external_interface_write (bus_write),
.bus_master_audio_external_interface_write_data (bus_write_data),
.bus_master_audio_external_interface_acknowledge (bus_ack),
.bus_master_audio_external_interface_read_data (bus_read_data),
// VGA Subsystem
.vga_pll_ref_clk_clk (CLOCK2_50),
.vga_pll_ref_reset_reset (1'b0),
.vga_CLK (VGA_CLK),
.vga_BLANK (VGA_BLANK_N),
.vga_SYNC (VGA_SYNC_N),
.vga_HS (VGA_HS),
.vga_VS (VGA_VS),
.vga_R (VGA_R),
.vga_G (VGA_G),
.vga_B (VGA_B),
// SDRAM
.sdram_clk_clk (DRAM_CLK),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm ({DRAM_UDQM,DRAM_LDQM}),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
////////////////////////////////////
// HPS Side
////////////////////////////////////
// DDR3 SDRAM
.memory_mem_a (HPS_DDR3_ADDR),
.memory_mem_ba (HPS_DDR3_BA),
.memory_mem_ck (HPS_DDR3_CK_P),
.memory_mem_ck_n (HPS_DDR3_CK_N),
.memory_mem_cke (HPS_DDR3_CKE),
.memory_mem_cs_n (HPS_DDR3_CS_N),
.memory_mem_ras_n (HPS_DDR3_RAS_N),
.memory_mem_cas_n (HPS_DDR3_CAS_N),
.memory_mem_we_n (HPS_DDR3_WE_N),
.memory_mem_reset_n (HPS_DDR3_RESET_N),
.memory_mem_dq (HPS_DDR3_DQ),
.memory_mem_dqs (HPS_DDR3_DQS_P),
.memory_mem_dqs_n (HPS_DDR3_DQS_N),
.memory_mem_odt (HPS_DDR3_ODT),
.memory_mem_dm (HPS_DDR3_DM),
.memory_oct_rzqin (HPS_DDR3_RZQ),
// Ethernet
.hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),
.hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),
.hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),
.hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),
.hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),
.hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),
.hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
.hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
.hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),
.hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),
.hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),
// Flash
.hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),
.hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),
.hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),
.hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),
.hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),
.hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),
// Accelerometer
.hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
//.adc_sclk (ADC_SCLK),
//.adc_cs_n (ADC_CS_N),
//.adc_dout (ADC_DOUT),
//.adc_din (ADC_DIN),
// General Purpose I/O
.hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
.hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),
// I2C
.hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
.hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT),
.hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK),
// Pushbutton
.hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),
// LED
.hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),
// SD Card
.hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),
.hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
.hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
.hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),
.hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
.hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),
// SPI
.hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK),
.hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI),
.hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO),
.hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS),
// UART
.hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),
.hps_io_hps_io_uart0_inst_TX (HPS_UART_TX),
// USB
.hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),
.hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),
.hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),
.hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),
.hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),
.hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),
.hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),
.hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),
.hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),
.hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),
.hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),
.hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT)
);
endmodule // DE1_SoC_Computer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_2_V
`define SKY130_FD_SC_HD__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_2_V
`define SKY130_FD_SC_HD__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_2_V
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx(tx),
.ser_rx(rx),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : rom_1p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Rom Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module rom_1p (
clk ,
cen_i ,
oen_i ,
addr_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 32;
parameter Addr_Width = 8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input [Addr_Width-1:0] addr_i; // address input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(posedge clk) begin
if (!cen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_BEHAVIORAL_PP_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Testbench of whitening function for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, [email protected] ////
//// - Younjoo Kim, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module tb_WF;
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
reg i_op ;
reg[63:0] i_wf_in ;
reg[31:0] i_wk ;
wire[63:0] o_wf_out ;
//=====================================
//
//
//
//=====================================
// uud0
WF uut0_WF(
.i_op (i_op ),
.i_wf_in (i_wf_in ),
.i_wk (i_wk ),
.o_wf_out(o_wf_out)
);
//=====================================
//
// STIMULUS
//
//=====================================
// stimulus
integer i;
initial begin
#1000;
$display("//===============================//");
$display("//========= SIM START ===========//");
$display("//===============================//");
$display("********** Test vectors 1 *********");
i_op = 1'b0;
i_wf_in = 64'h00_00_00_00_00_00_00_00 ;
i_wk = 32'h00_11_22_33 ;
#50;
$display ("Encryption(I) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h0000001100220033) ? "Correct" : "Wrong", o_wf_out );
#50;
i_op = 1'b0;
i_wf_in = 64'h00_38_18_d1_d9_a1_03_f3;
i_wk = 32'hcc_dd_ee_ff;
#50;
$display ("Encryption(F) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h00f418aed94f03f2) ? "Correct" : "Wrong", o_wf_out );
#50;
i_op = 1'b1;
i_wf_in = 64'h00_f4_18_ae_d9_4f_03_f2 ;
i_wk = 32'hcc_dd_ee_ff ;
#50;
$display ("Decryption (F-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h003818d1d9a103f3) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'h00_00_00_11_00_22_00_33;
i_wk = 32'h00_11_22_33;
#50;
$display ("Decryption (I-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h0000000000000000) ? "Correct" : "Wrong", o_wf_out);
#50;
$display("********** Test vectors 2 *********");
i_op = 1'b0;
i_wf_in = 64'h00_11_22_33_44_55_66_77 ;
i_wk = 32'hff_ee_dd_cc ;
#50;
$display ("Encryption(I) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h00ee222144886643) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b0;
i_wf_in = 64'h23_fd_9f_50_e5_52_e6_d8;
i_wk = 32'h33_22_11_00;
#50;
$display ("Encryption(F) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h23ce9f72e543e6d8) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'h23_ce_9f_72_e5_43_e6_d8 ;
i_wk = 32'h33_22_11_00 ;
#50;
$display ("Decryption(F-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h23fd9f50e552e6d8) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'h00_ee_22_21_44_88_66_43;
i_wk = 32'hff_ee_dd_cc;
#50;
$display ("Decryption(I-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h0011223344556677) ? "Correct" : "Wrong", o_wf_out);
#50;
$display("********** Test vectors 3 *********");
i_op = 1'b0;
i_wf_in = 64'h01_23_45_67_89_ab_cd_ef ;
i_wk = 32'h00_01_02_03 ;
#50;
$display ("Encryption(I) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h0123456889a9cdf2) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b0;
i_wf_in = 64'h7a_63_b2_95_8d_2d_f4_57;
i_wk = 32'h0c_0d_0e_0f;
#50;
$display ("Encryption(F) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'h7a6fb2a28d23f466) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'h7a_6f_b2_a2_8d_23_f4_66 ;
i_wk = 32'h0c_0d_0e_0f ;
#50;
$display ("Decryption(F-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h7a63b2958d2df457) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'h01_23_45_68_89_a9_cd_f2;
i_wk = 32'h00_01_02_03;
#50;
$display ("Decryption(I-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'h0123456789abcdef) ? "Correct" : "Wrong", o_wf_out);
#50;
$display("********** Test vectors 4 *********");
i_op = 1'b0;
i_wf_in = 64'hb4_1e_6b_e2_eb_a8_4a_14 ;
i_wk = 32'h28_db_c3_bc ;
#50;
$display ("Encryption(I) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'hb4366bbdeb6b4ad0) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b0;
i_wf_in = 64'hcc_19_7a_33_20_b7_1f_df;
i_wk = 32'h1d_42_2b_e7;
#50;
$display ("Encryption(F) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h" , i_wf_in, i_wk, (o_wf_out == 64'hcc047a75209c1fc6) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'hcc_04_7a_75_20_9c_1f_c6 ;
i_wk = 32'h1d_42_2b_e7 ;
#50;
$display ("Decryption(F-) : i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'hcc197a3320b71fdf) ? "Correct" : "Wrong", o_wf_out);
#50;
i_op = 1'b1;
i_wf_in = 64'hb4_36_6b_bd_eb_6b_4a_d0;
i_wk = 32'h28_db_c3_bc;
#50;
$display ("Decryption(I-): i_wf_in = %16h, i_wk = %8h ==> o_wf_out (%s) = %16h ", i_wf_in, i_wk, (o_wf_out == 64'hb41e6be2eba84a14) ? "Correct" : "Wrong", o_wf_out);
#50;
$display("========== SIM END ==========");
$finish;
end
// vcd dump
initial begin
$dumpfile("dump/sim_tb_WF.vcd");
$dumpvars(0, tb_WF);
end
endmodule
|
// simulates multiplier ip core provided by xilinx
module mpemu(
input wire clk,
input wire [23:0] mpcand_i,
input wire [23:0] mplier_i,
output wire [27:0] mprod_o);
`ifndef NO_IP
// A: signed 24 bit
// B: signed 24 bit
// P: Custom Output Width MSB=46 LSB=19
// Pipeline Stages 5
mp mp(
.clk(clk),
.a(mpcand_i),
.b(mplier_i),
.p(mprod_o));
`else
reg [23:0] delay_a[4:0];
reg [23:0] delay_b[4:0];
always @(posedge clk) begin
delay_a[0] <= mpcand_i;
delay_a[1] <= delay_a[0];
delay_a[2] <= delay_a[1];
delay_a[3] <= delay_a[2];
delay_a[4] <= delay_a[3];
delay_b[0] <= mplier_i;
delay_b[1] <= delay_b[0];
delay_b[2] <= delay_b[1];
delay_b[3] <= delay_b[2];
delay_b[4] <= delay_b[3];
end
wire [23:0] delayed_a = delay_a[4];
wire [23:0] delayed_b = delay_b[4];
wire [46:0] prod_full = $signed(delayed_a) * $signed(delayed_b);
assign mprod_o = prod_full[46:19];
`endif
endmodule
module mpemu_scale(
input wire clk,
input wire [23:0] mpcand_i,
input wire [31:0] scale_i,
output wire [31:0] mprod_o);
`ifndef NO_IP
// A: signed 24 bit
// B: unsigned 32 bit
// P: Custom Output Width MSB=55 LSB=24
// Pipeline Stages 6
mp_scale mp_scale(
.clk(clk),
.a(mpcand_i),
.b(scale_i),
.p(mprod_o));
`else
reg [23:0] delay_a[6:0];
reg [31:0] delay_b[6:0];
always @(posedge clk) begin
delay_a[0] <= mpcand_i;
delay_a[1] <= delay_a[0];
delay_a[2] <= delay_a[1];
delay_a[3] <= delay_a[2];
delay_a[4] <= delay_a[3];
delay_a[5] <= delay_a[4];
delay_a[6] <= delay_a[5];
delay_b[0] <= scale_i;
delay_b[1] <= delay_b[0];
delay_b[2] <= delay_b[1];
delay_b[3] <= delay_b[2];
delay_b[4] <= delay_b[3];
delay_b[5] <= delay_b[4];
delay_b[6] <= delay_b[5];
end
wire [23:0] delayed_a = delay_a[5];
wire [31:0] delayed_b = delay_b[5];
wire signed [32:0] delayed_b_signed = {1'b0, delay_b[5]};
// for saturated delay
wire [23:0] delayed_a2 = delay_a[6];
wire [31:0] delayed_b2 = delay_b[6];
wire signed [55:0] prod_full = $signed(delayed_a) * $signed(delayed_b_signed);
assign mprod_o = prod_full[55:24];
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
|
`include "defines.v"
module mem_wb(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//À´×Էôæ½×¶ÎµÄÐÅÏ¢
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
//Ë͵½»Øд½×¶ÎµÄÐÅÏ¢
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value,
output reg wb_cp0_reg_we,
output reg[4:0] wb_cp0_reg_write_addr,
output reg[`RegBus] wb_cp0_reg_data
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(flush == 1'b1 ) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
wb_cp0_reg_we <= mem_cp0_reg_we;
wb_cp0_reg_write_addr <= mem_cp0_reg_write_addr;
wb_cp0_reg_data <= mem_cp0_reg_data;
end //if
end //always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_1_V
`define SKY130_FD_SC_HDLL__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_1_V
|
`timescale 1ns / 1ps
`include "collaterals.v"
`include "z80_opcode_definitions.v"
`include "aDefinitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module dzcpu
(
input wire iClock,
input wire iReset,
input wire [7:0] iMCUData,
output wire [7:0] oMCUData,
output wire [15:0] oMCUAddr,
output wire oMcuReadRequest,
input wire [3:0] iInterruptRequests,
output reg oMCUwe,
output wire [7:0] oCurrentZ80Insn,
output wire oEof,
output wire oInterruptJump,
output wire oBranchTaken
);
wire[15:0] wPc, wRegData, wUopSrc, wX16, wY16, wZ16, wInitialPc, wInterruptVectorAddress, wXY16 ;
wire [7:0] wBitMask, wX8, wY8;
wire [9:0] wuOpBasicFlowIdx,wuOpExtendedFlowIdx, wuOpFlowIdx, wuPc, wNextFlow;
wire wIPC,wEof, wZ, wN;
wire [14:0] wUop;
wire [4:0 ] wuCmd;
wire [4:0] wMcuAdrrSel;
wire [2:0] wUopRegReadAddr0, wUopRegReadAddr1, rUopRegWriteAddr;
wire [7:0] wB,wC,wD, wE, wH,wL,wA, wSpL, wSpH, wFlags, wUopSrcRegData0;
wire [7:0] wSHR_RegData, wUopSrcRegData1, wNextUopFlowIdx;
wire [3:0] wInterruptRequestBitMap, wInterruptRequestBitMaps_pre;
wire wInterruptsEnabled, wTimerTick;
reg rSetiWe,rSetiVal; // set FF_INTENABLE
reg rClearIntLatch; // clean FF_INTSIGNAL
reg rLatchInsn;
reg rResetFlow,rFlowEnable, rRegWe, rSetMCOAddr, rOverWritePc, rCarry, rMcuReadRequest;
reg [4:0] rRegSelect;
reg [7:0] rZ80Result, rWriteSelect;
reg [15:0] rUopDstRegData;
reg rHalt; //Flag to stop microflow
wire wContFlow; //Flag to continue microflow
assign oInterruptJump = wInterruptRoutineJumpDetected;
assign oBranchTaken = rOverWritePc | wInterruptRoutineJumpDetected;
assign wUopSrc = wUop[4:0];
assign wIPC = wUop[13]; //Increment Macro Insn program counter
assign wuCmd = wUop[9:5];
assign oEof = wEof & rFlowEnable & ~wInterruptRoutineJumpDetected;
assign wContFlow = rHalt | |iInterruptRequests;
MUXFULLPARALELL_3SEL_GENERIC # ( 1'b1 ) MUX_EOF
(
.Sel( wUop[12:10] ),
.I0( 1'b0 ), //op
.I1( 1'b1 ), //eof
.I2( wFlags[`flag_c] ), //eof_c
.I3( ~wFlags[`flag_c] ), //eof_nc
.I4( wFlags[`flag_z] ), //eof_z
.I5( ~wFlags[`flag_z] ), //eof_nz
.I6( 1'b0 ), //Reserved
.I7( 1'b0 ), //Reserved
.O( wEof )
);
dzcpu_ucode_rom urom
(
.iAddr( wuPc ),
.oUop( wUop )
);
dzcpu_ucode_lut ulut
(
.iMop( iMCUData ),
.oUopFlowIdx( wuOpBasicFlowIdx )
);
dzcpu_ucode_cblut ucblut
(
.iMop( iMCUData ),
.oUopFlowIdx( wuOpExtendedFlowIdx )
);
wire wJcbDetected, wInterruptRoutineJumpDetected;
//If at leaast 1 bit from iInterruptRequests is set and interrupts are enable,
//then we have an interrupt
assign wInterruptRoutineJumpDetected = |iInterruptRequests & wInterruptsEnabled;
assign wJcbDetected = ( rFlowEnable & wuCmd == `jcb ) ? 1'b1 : 1'b0;
//Hold the int signal while we wait for current flow to finish
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 )FF_INTSIGNAL( iClock, iReset | rClearIntLatch, 1'b1 , iInterruptRequests, wInterruptRequestBitMaps_pre );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 )FF_INTENABLE( iClock, iReset, rFlowEnable & rSetiWe, rSetiVal, wInterruptsEnabled );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FF_Z80_INSN( iClock, iReset, rLatchInsn, iMCUData, oCurrentZ80Insn );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 )FF_TIMER_TICK( iClock, iReset, 1'b1, rLatchInsn, wTimerTick );
//Disregard interrupts if interrupts are disabled
assign wInterruptRequestBitMap = ( wInterruptsEnabled == 1'b1) ? wInterruptRequestBitMaps_pre : 4'b0;
UPCOUNTER_POSEDGE # (10) UPC
(
.Clock( iClock ),
.Reset( iReset | rResetFlow | wJcbDetected ),
.Initial( wNextFlow ),
.Enable( rFlowEnable & wContFlow ),
.Q( wuPc )
);
assign wNextFlow = (iReset) ? 10'b0 : wuOpFlowIdx;
MUXFULLPARALELL_2SEL_GENERIC # (10) MUX_NEXT_FLOW
(
.Sel({wInterruptRoutineJumpDetected,wJcbDetected}),
.I0( wuOpBasicFlowIdx ),
.I1( wuOpExtendedFlowIdx ),
.I2( `FLOW_ID_INTERRUPT ),
.I3( `FLOW_ID_INTERRUPT ),
.O( wuOpFlowIdx )
);
MUXFULLPARALELL_4SEL_GENERIC # (16) MUX_INTERRUPT
(
.Sel( wInterruptRequestBitMap ),
.I0( wPc ), //0000 No interrupts, use the normal flow
.I1( `INT_ADDR_VBLANK ), //0001 -- Interrupt routine 0x40
.I2( `INT_ADDR_LCD_STATUS_TRIGGER), //0010
.I3( `INT_ADDR_VBLANK ), //0011 -- Interrupt routine 0x40
.I4( `INT_ADDR_TIMER_OVERFLOW), //0100
.I5( `INT_ADDR_VBLANK), //0101
.I6( `INT_ADDR_TIMER_OVERFLOW), //0110
.I7( `INT_ADDR_VBLANK ), //0111
.I8( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1000
.I9( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1001
.I10( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1010
.I11( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1011
.I12( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1100
.I13( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1101
.I14( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1110
.I15( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1111
.O( wInterruptVectorAddress )
);
`ifdef SKIP_BIOS
assign wInitialPc = ( rOverWritePc ) ? rUopDstRegData : 16'h100;
`else
assign wInitialPc = ( rOverWritePc ) ? rUopDstRegData : 16'b0;
`endif
UPCOUNTER_POSEDGE # (16) PC
(
.Clock( iClock ),
.Reset( iReset | (rOverWritePc & rFlowEnable)),
.Initial( wInitialPc ),
`ifdef DISABLE_CPU
.Enable( 1'b0 ),
`else
.Enable( wIPC & rFlowEnable ),
`endif
.Q( wPc )
);
//--------------------------------------------------------
// Current State Logic //
reg [7:0] rCurrentState,rNextState;
always @(posedge iClock )
begin
if( iReset!=1 )
rCurrentState <= rNextState;
else
rCurrentState <= `DZCPU_AFTER_RESET;
end
//--------------------------------------------------------
always @( * )
begin
case (rCurrentState)
//----------------------------------------
`DZCPU_AFTER_RESET:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rLatchInsn = 1'b0;
rNextState = `DZCPU_START_FLOW;
end
//----------------------------------------
`DZCPU_START_FLOW:
begin
rResetFlow = 1'b1;
rFlowEnable = 1'b0;
rLatchInsn = 1'b1;
if (iReset)
rNextState = `DZCPU_AFTER_RESET;
else
rNextState = `DZCPU_RUN_FLOW;
end
//----------------------------------------
`DZCPU_RUN_FLOW:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b1;
rLatchInsn = 1'b0;
if (wEof)
rNextState = `DZCPU_END_FLOW;
else
rNextState = `DZCPU_RUN_FLOW;
end
//----------------------------------------
`DZCPU_END_FLOW:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rLatchInsn = 1'b0;
rNextState = `DZCPU_START_FLOW;
end
//----------------------------------------
default:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rLatchInsn = 1'b0;
rNextState = `DZCPU_AFTER_RESET;
end
endcase
end
reg [13:0] rRegWriteSelect;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFB ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[0], (( rRegWriteSelect[1] & rRegWriteSelect[0])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wB );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFC ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[1], rUopDstRegData[7:0], wC );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[2], (( rRegWriteSelect[2] & rRegWriteSelect[3])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wD );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFE ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[3], rUopDstRegData[7:0], wE );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFH ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[4], (( rRegWriteSelect[4] & rRegWriteSelect[5])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wH );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFL ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[5], rUopDstRegData[7:0], wL );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFA ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[6], rUopDstRegData[7:0], wA );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFSPL( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[7], rUopDstRegData[7:0], wSpL );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFSPH( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[8], (( rRegWriteSelect[7] & rRegWriteSelect[8])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wSpH );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFX8 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[9], rUopDstRegData[7:0], wX8 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFX16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[10], rUopDstRegData[15:0], wX16 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFY16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[11], rUopDstRegData[15:0], wY8 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFZ16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[12], rUopDstRegData[15:0], wZ16 );
//wire[15:0] wUopDstRegData_Prev;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FF_RESULT_PREV ( iClock, iReset, 1'b1, rUopDstRegData, wUopDstRegData_Prev);
reg [1:0] rFlagsZ, rFlagsN, rFlagsH, rFlagsC;
wire wFlagsWe;
wire wCarry, wCarry12, wHalfCarry_Inc, wHalfCarry_Add, wHalfCarry_Sub, wHalfCarry_Dec, wCpnHalf, wHalfCarry_AddC;
wire [7:0] wFlagsUpdate;
reg rCarry16;
wire [3:0] wNibble_Add, wNibble_Sub;
assign wHalfCarry_Inc = ((rUopDstRegData[3:0] ) == 4'h0) ? 1'b1 : 1'b0;
assign wHalfCarry_Dec = ((rUopDstRegData[3:0] ) == 4'hf) ? 1'b1 : 1'b0;
assign {wHalfCarry_AddC, wNibble_Add} = wRegData[3:0] + wX16[3:0] + wFlags[`flag_c];
assign {wHalfCarry_Add, wNibble_Add} = wRegData[3:0] + wX16[3:0];
assign {wHalfCarry_Sub, wNibble_Sub} = wX16[3:0] - wRegData[3:0];
assign wCpnHalf = (rUopDstRegData[3:0] > wA[3:0]) ? 1'b1 : 1'b0;
//assign wHalfCarry = wUopDstRegData_Prev[4]; //Need value from prev CC
assign wCarry = rUopDstRegData[8];
//assign wCarry16 = rUopDstRegData[15];
assign wCarry12 = rUopDstRegData[12];
assign wFlagsWe = rFlowEnable & (wUop[ `uop_flags_update_enable ] == 1'b1 || wuCmd == `z801bop )
& ( rFlagsZ[1] | rFlagsN[1] | rFlagsH[1] | rFlagsC[1] );
assign wFlagsUpdate[`flag_z ] = ( rFlagsZ[1] == 1'b1 ) ? rFlagsZ[0] : wFlags[`flag_z ] ;
assign wFlagsUpdate[`flag_h ] = ( rFlagsH[1] == 1'b1 ) ? rFlagsH[0] : wFlags[`flag_h ] ;
assign wFlagsUpdate[`flag_n ] = ( rFlagsN[1] == 1'b1 ) ? rFlagsN[0] : wFlags[`flag_n ] ;
assign wFlagsUpdate[`flag_c ] = ( rFlagsC[1] == 1'b1 ) ? rFlagsC[0] : wFlags[`flag_c ] ;
assign wFlagsUpdate[3:0] = 4'b0;
wire [7:0] wNewFlags;
wire wOverWriteFlagswithRegister;
assign wOverWriteFlagswithRegister = (rFlowEnable & rRegWe & rRegWriteSelect[13]) ? 1'b1 : 1'b0;
assign wNewFlags = ( wOverWriteFlagswithRegister ) ? rUopDstRegData : wFlagsUpdate;
FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( 8 )FFFLAGS( iClock, iReset, wFlagsWe | wOverWriteFlagswithRegister , 8'hb0,wNewFlags, wFlags );
FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( 5 )FFMCUADR( iClock, iReset, rFlowEnable & rSetMCOAddr, `pc , wUop[4:0], wMcuAdrrSel );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 )FF_RREQ( iClock, iReset, rFlowEnable & ~oMCUwe, rMcuReadRequest, oMcuReadRequest );
MUXFULLPARALELL_5SEL_GENERIC # (16) MUX_MCUADR
(
.Sel( wMcuAdrrSel),
.I0({8'b0,wB}), .I1({8'b0,wC}), .I2({8'b0,wD}), .I3({8'b0,wE}),
.I4({8'b0,wH}), .I5({8'b0,wL}), .I6({wH,wL}), .I7({8'b0,wA}),
.I8(wPc), .I9({8'b0,wPc[15:8]}), .I10({wSpH,wSpL}), .I11({8'b0,wFlags}) ,
.I12({8'b0,wSpL}), .I13( {8'b0,wSpH} ), .I14( wY16 ), .I15( wZ16 ),
.I16({8'b0,wX8 }), .I17( wX16), .I18({8'hff,wC}), .I19({wD,wE}),
.I20({8'b0,wFlags }), .I21({wB,wC}), .I22({wA,wFlags}), .I23(16'b0),
.I24(16'b0), .I25({8'b0,wY8} ), .I26({wX8,wY8 }), .I27(16'hff0f),
.I28(16'b0), .I29(16'b0), .I30(16'b0), .I31(16'b0),
.O( oMCUAddr )
);
MUXFULLPARALELL_5SEL_GENERIC # (16) MUX_REGDATA
(
.Sel( rRegSelect),
.I0({8'b0,wB}), .I1({8'b0,wC}), .I2({8'b0,wD}), .I3({8'b0,wE}),
.I4({8'b0,wH}), .I5({8'b0,wL}), .I6({wH,wL}), .I7({8'b0,wA}),
.I8(wPc), .I9({8'b0,wPc[15:8]}), .I10({wSpH,wSpL}), .I11({8'b0,wFlags}) ,
.I12({8'b0,wSpL}), .I13( {8'b0,wSpH} ), .I14( wY16 ), .I15( wZ16 ),
.I16({8'b0,wX8 }), .I17( wX16), .I18({8'hff,wC}), .I19({wD,wE}),
.I20({8'b0,wFlags }), .I21({wB,wC}), .I22({wA,wFlags}), .I23({8'b0,iMCUData}),
.I24({15'b0,wFlags[`flag_c]}), .I25( {8'b0,wY8 } ), .I26( {wX8,wY8 }), .I27(16'b0),
.I28(16'b0), .I29(16'b0), .I30(16'b0), .I31(16'b0),
.O( wRegData )
);
MUXFULLPARALELL_5SEL_GENERIC # (8) MUX_MCUDATA_OUT
(
.Sel( rRegSelect),
.I0(wB), .I1(wC), .I2(wD), .I3(wE),
.I4(wH), .I5(wL), .I6(wL), .I7(wA),
.I8(wPc[7:0]), .I9(wPc[15:8]), .I10(wSpL), .I11(wFlags) ,
.I12(wSpL), .I13( wSpH ), .I14( wY16[7:0] ), .I15( wZ16[7:0] ),
.I16(wX8 ), .I17( wX16[7:0]), .I18(wC), .I19(wE),
.I20(wFlags ), .I21(wC), .I22(wFlags), .I23(8'b0),
.I24({7'b0,wFlags[`flag_c]}), .I25( wY8 ), .I26( wX8 ), .I27(8'b0),
.I28(8'b0), .I29(8'b0), .I30(8'b0), .I31(8'b0),
.O( oMCUData )
);
always @ ( * )
begin
case (rWriteSelect)
`b: rRegWriteSelect = 14'b00000000000001;
`c: rRegWriteSelect = 14'b00000000000010;
`bc: rRegWriteSelect = 14'b00000000000011;
`d: rRegWriteSelect = 14'b00000000000100;
`e: rRegWriteSelect = 14'b00000000001000;
`de: rRegWriteSelect = 14'b00000000001100;
`h: rRegWriteSelect = 14'b00000000010000;
`l: rRegWriteSelect = 14'b00000000100000;
`hl: rRegWriteSelect = 14'b00000000110000;
`a: rRegWriteSelect = 14'b00000001000000;
`spl: rRegWriteSelect = 14'b00000010000000;
`sph: rRegWriteSelect = 14'b00000100000000;
`sp: rRegWriteSelect = 14'b00000110000000;
`x8: rRegWriteSelect = 14'b00001000000000;
`x16: rRegWriteSelect = 14'b00010000000000;
`y8: rRegWriteSelect = 14'b00100000000000;
`xy16: rRegWriteSelect = 14'b01000000000000;
`f: rRegWriteSelect = 14'b10000000000000;
default: rRegWriteSelect = 13'b0;
endcase
end
assign wZ = (rUopDstRegData[7:0] ==8'b0) ? 1'b1 : 1'b0;
assign wN = (rUopDstRegData[15] == 1'b1) ? 1'b1 : 1'b0;
assign wSHR_RegData = wRegData >> 1;
always @ ( * )
begin
case (wuCmd)
`nop:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`sma:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b1;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b1;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`srm:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = iMCUData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`smw:
begin
oMCUwe = 1'b1;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`dec16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = wRegData - 16'd1;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`inc16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = wRegData + 1'b1;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`xorx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wX16 ^ {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`subx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wX16 - {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`xora:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `a;
{rCarry16,rUopDstRegData} = {8'b0,wA} ^ {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`anda:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `a;
{rCarry16,rUopDstRegData} = {8'b0,wA} & {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`addx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wX16 + {{8{wRegData[7]}},wRegData[7:0]}; //sign extended 2'complement
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`addx16u:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wX16 + wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`addx16c:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wX16 + wRegData + wFlags[`flag_c];
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`spc:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = wRegData;
rOverWritePc = 1'b1;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`jint: //Jump to interrupt routine
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = `pc;
{rCarry16,rUopDstRegData} = wInterruptVectorAddress;
rOverWritePc = 1'b1;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b1;
rHalt = 1'b1;
end
`jcb: //Jump to extended Z80 flow (0xCB command)
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
{rCarry16,rWriteSelect} = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`srx8:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
{rCarry16,rWriteSelect} = wUopSrc[7:0];
rUopDstRegData = wX8;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`srx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = wX16;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`z801bop:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = ( iMCUData[7:6] == 2'b01 ) ? iMCUData[5:3] : wUopSrc[7:0];
{rCarry16,rUopDstRegData} = rZ80Result;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`shl:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
{rCarry16,rUopDstRegData} = (wRegData << 1) + wFlags[`flag_c];
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`rrot:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
{rCarry16,rUopDstRegData} = {wFlags[`flag_c], wSHR_RegData[6:0] };
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`shr:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
{rCarry16,rUopDstRegData} = wSHR_RegData[7:0];
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`bit:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = wRegData & wBitMask;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`sx8r:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x8;
{rCarry16,rUopDstRegData} = wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`sx16r:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
{rCarry16,rUopDstRegData} = wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`seti:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b1;
rSetiVal = 1'b1;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`ceti: //Disable interruption
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b1;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
`cibit:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b1;
rHalt = 1'b1;
end
`hlt:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b0;
end
default:
begin
oMCUwe = 1'b0;
rRegSelect = `pc;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
{rCarry16,rUopDstRegData} = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
rHalt = 1'b1;
end
endcase
end
//Flags
// +----+-----+----+----+---------+
// | Z | N | H | C | 4'b0 |
// +----+-----+----+----+---------+
wire [7:0] wCurrentFlow;
wire wCBFlow, wIsCBFlow;
assign wIsCBFlow = (wuCmd == `jcb) ? 1'b1 : 1'b0;
FFD_POSEDGE_SYNCRONOUS_RESET # (8) FFD_CURFLOW (
iClock, iReset, (rResetFlow | wIsCBFlow),iMCUData, wCurrentFlow);
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD_CBFLOW (
iClock, iReset, 1'b1 ,wIsCBFlow, wCBFlow);
always @ ( * )
begin
case ({wCBFlow,wCurrentFlow})
{1'b0,`INCr_a},{1'b0,`INCr_b},{1'b0,`INCr_c},{1'b0,`INCr_d},
{1'b0,`INCr_e},{1'b0,`INCr_h},{1'b0,`INCr_l}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0}; //Can never be neg
rFlagsH = {1'b1,wHalfCarry_Inc};
rFlagsC = {1'b0,1'b0};
end
{1'b0,`DECr_b},{1'b0,`DECr_c},{1'b0,`DECr_d},{1'b0,`DECr_e},
{1'b0,`DECr_h},{1'b0,`DECr_l},{1'b0,`DECr_a}, {1'b0,`DECHL},{1'b0,`DECHLm}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b1}; //Gearboy behaves like this
rFlagsH = {1'b1,wHalfCarry_Dec};
rFlagsC = {1'b0,1'b0}; //This is needed to make BIOS work...
end
{1'b0,`ADDHLHL}, {1'b0,`ADDHLDE}:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,wCarry12};
rFlagsC = {1'b1,rCarry16};
end
{1'b0,`ADDr_a}, {1'b0,`ADDr_b}, {1'b0,`ADDr_c},{1'b0, `ADDr_d},
{1'b0,`ADDr_h}, {1'b0,`ADDr_l}, {1'b0,`ADDr_e},{1'b0, `ADDn}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,wHalfCarry_Add};
rFlagsC = {1'b1,wCarry};
end
{1'b0,`ADCn}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,wHalfCarry_AddC};
rFlagsC = {1'b1,wCarry};
end
{1'b0,`SUBr_a}, {1'b0,`SUBr_b}, {1'b0,`SUBr_e},{1'b0, `SUBr_d},
{1'b0,`SUBr_h}, {1'b0,`SUBr_l},{1'b0,`SUBn}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b1};
rFlagsH = {1'b1,wHalfCarry_Sub};
rFlagsC = {1'b1,wCarry};
end
{1'b0,`CPn}:
begin
rFlagsZ = {1'b1,wZ}; // A == n
rFlagsN = {1'b1,1'b1};
rFlagsH = {1'b1,wCpnHalf}; //A > n
rFlagsC = {1'b1,wN}; //A < n
end
{1'b0,`ANDr_a},{1'b0,`ANDr_b},
{1'b0,`ANDr_c},{1'b0,`ANDn},
{1'b0,`ANDr_d},{1'b0,`ANDr_e},
{1'b0,`ANDr_h},{1'b0,`ANDr_l}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b1}; //H is set
rFlagsC = {1'b1,1'b0};
end
{1'b0, `LDHLSPn}:
begin
rFlagsZ = {1'b1,1'b0}; //Clear this flag
rFlagsN = {1'b1,1'b0}; //Clear this flag
rFlagsH = {1'b1,rUopDstRegData[3]};
rFlagsC = {1'b1,wCarry};
end
{1'b0,`RLA}:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wA[7]};
end
{1'b0,`RRA}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wA[0]};
end
{1'b1,`RLr_a},{1'b1,`RLr_b},{1'b1,`RLr_d},{1'b1,`RLr_e},
{1'b1,`RLr_h},{1'b1,`RLr_l},{1'b1,`RLr_c}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,wN};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wRegData[7]};
end
{1'b1,`SRLr_a},{1'b1,`SRLr_b},{1'b1,`SRLr_d},{1'b1,`SRLr_e},
{1'b1,`SRLr_h},{1'b1,`SRLr_l},{1'b1,`SRLr_c}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,wN};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wRegData[0]};
end
{1'b0,`ORr_a}, {1'b0,`ORr_b}, {1'b0,`ORr_d},{1'b0,`ORr_c},
{1'b0,`ORr_e}, {1'b0,`ORr_h}, {1'b0,`ORr_l},{1'b0,`XORn},{1'b0,`ORHL},
{1'b0,`XORr_a},{1'b0,`XORr_b},{1'b0,`XORr_d},{1'b0,`XORr_c},
{1'b0,`XORr_e},{1'b0,`XORr_h},{1'b0,`XORr_l},{1'b0,`XORHL}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,1'b0}; //C is reset
end
{1'b1, `RLCr_b}, {1'b1, `RLCr_c}, {1'b1,`RLCr_d}, {1'b1,`RLCr_e},
{1'b1, `RLCr_h}, {1'b1, `RLCr_l}, {1'b1,`RLCr_a}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b0};
rFlagsC = {1'b1,wRegData[7]};
end
{1'b1, `RRCr_b}, {1'b1, `RRCr_c}, {1'b1, `RRCr_d}, {1'b1, `RRCr_e},
{1'b1, `RRCr_h}, {1'b1, `RRCr_l},
{1'b1, `RRr_b}, {1'b1, `RRr_c}, {1'b1, `RRr_d}, {1'b1, `RRr_e},
{1'b1, `RRr_h}, {1'b1, `RRr_l},{1'b1, `RRr_a}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b0};
rFlagsC = {1'b1,wRegData[0]};
end
{1'b1, `BIT7h }, {1'b1, `BIT7l }, {1'b1, `BIT7m }, {1'b1, `BIT7a }:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b0,1'b0};
rFlagsC = {1'b0,1'b0};
end
default:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b0,1'b0};
rFlagsC = {1'b0,1'b0};
end
endcase
end
DECODER_MASK_3_BITS BIT_MASK( iMCUData[5:3], wBitMask );
always @ ( * )
begin
case (iMCUData[7:3])
5'b10100: rZ80Result = wA & wRegData; //AND
5'b10101: rZ80Result = wA ^ wRegData; //XOR
5'b10110: rZ80Result = wA | wRegData; //OR
5'b01000, 5'b01001, 5'b01010, 5'b01011, 5'b01100, 5'b01101, 5'b01110, 5'b01111: rZ80Result = wRegData; //ldrr
default: rZ80Result = 8'hcc;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_2_V
`define SKY130_FD_SC_LS__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_2_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:49 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wtiS0_SThreadBusy O 1 reg
// wtiS0_SReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wtiS0_MCmd I 3 reg
// wtiS0_MData I 64 reg
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWSICaptureWorker4B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wtiS0_MCmd,
wtiS0_MData,
wtiS0_SThreadBusy,
wtiS0_SReset_n);
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// action method wtiS0_mCmd
input [2 : 0] wtiS0_MCmd;
// action method wtiS0_mData
input [63 : 0] wtiS0_MData;
// value method wtiS0_sThreadBusy
output wtiS0_SThreadBusy;
// value method wtiS0_sReset_n
output wtiS0_SReset_n;
// signals for module outputs
wire [31 : 0] wciS0_SData;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wtiS0_SReset_n,
wtiS0_SThreadBusy;
// inlined wires
wire [95 : 0] wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [66 : 0] wtiS_wtiReq_wget;
wire [63 : 0] nowW_wget, wti_Es_mData_w_wget;
wire [60 : 0] wsiS_wsiReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] dataBram_0_serverAdapterA_outData_enqData_wget,
dataBram_0_serverAdapterA_outData_outData_wget,
dataBram_0_serverAdapterB_outData_enqData_wget,
dataBram_0_serverAdapterB_outData_outData_wget,
metaBram_0_serverAdapterA_outData_enqData_wget,
metaBram_0_serverAdapterA_outData_outData_wget,
metaBram_0_serverAdapterB_outData_enqData_wget,
metaBram_0_serverAdapterB_outData_outData_wget,
metaBram_1_serverAdapterA_outData_enqData_wget,
metaBram_1_serverAdapterA_outData_outData_wget,
metaBram_1_serverAdapterB_outData_enqData_wget,
metaBram_1_serverAdapterB_outData_outData_wget,
metaBram_2_serverAdapterA_outData_enqData_wget,
metaBram_2_serverAdapterA_outData_outData_wget,
metaBram_2_serverAdapterB_outData_enqData_wget,
metaBram_2_serverAdapterB_outData_outData_wget,
metaBram_3_serverAdapterA_outData_enqData_wget,
metaBram_3_serverAdapterA_outData_outData_wget,
metaBram_3_serverAdapterB_outData_enqData_wget,
metaBram_3_serverAdapterB_outData_outData_wget,
statusReg_w_wget,
wci_wci_Es_mAddr_w_wget,
wci_wci_Es_mData_w_wget,
wsi_Es_mData_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget, wsi_Es_mByteEn_w_wget;
wire [2 : 0] dataBram_0_serverAdapterA_cnt_1_wget,
dataBram_0_serverAdapterA_cnt_2_wget,
dataBram_0_serverAdapterA_cnt_3_wget,
dataBram_0_serverAdapterB_cnt_1_wget,
dataBram_0_serverAdapterB_cnt_2_wget,
dataBram_0_serverAdapterB_cnt_3_wget,
metaBram_0_serverAdapterA_cnt_1_wget,
metaBram_0_serverAdapterA_cnt_2_wget,
metaBram_0_serverAdapterA_cnt_3_wget,
metaBram_0_serverAdapterB_cnt_1_wget,
metaBram_0_serverAdapterB_cnt_2_wget,
metaBram_0_serverAdapterB_cnt_3_wget,
metaBram_1_serverAdapterA_cnt_1_wget,
metaBram_1_serverAdapterA_cnt_2_wget,
metaBram_1_serverAdapterA_cnt_3_wget,
metaBram_1_serverAdapterB_cnt_1_wget,
metaBram_1_serverAdapterB_cnt_2_wget,
metaBram_1_serverAdapterB_cnt_3_wget,
metaBram_2_serverAdapterA_cnt_1_wget,
metaBram_2_serverAdapterA_cnt_2_wget,
metaBram_2_serverAdapterA_cnt_3_wget,
metaBram_2_serverAdapterB_cnt_1_wget,
metaBram_2_serverAdapterB_cnt_2_wget,
metaBram_2_serverAdapterB_cnt_3_wget,
metaBram_3_serverAdapterA_cnt_1_wget,
metaBram_3_serverAdapterA_cnt_2_wget,
metaBram_3_serverAdapterA_cnt_3_wget,
metaBram_3_serverAdapterB_cnt_1_wget,
metaBram_3_serverAdapterB_cnt_2_wget,
metaBram_3_serverAdapterB_cnt_3_wget,
wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget,
wti_Es_mCmd_w_wget;
wire [1 : 0] dataBram_0_serverAdapterA_s1_1_wget,
dataBram_0_serverAdapterA_writeWithResp_wget,
dataBram_0_serverAdapterB_s1_1_wget,
dataBram_0_serverAdapterB_writeWithResp_wget,
metaBram_0_serverAdapterA_s1_1_wget,
metaBram_0_serverAdapterA_writeWithResp_wget,
metaBram_0_serverAdapterB_s1_1_wget,
metaBram_0_serverAdapterB_writeWithResp_wget,
metaBram_1_serverAdapterA_s1_1_wget,
metaBram_1_serverAdapterA_writeWithResp_wget,
metaBram_1_serverAdapterB_s1_1_wget,
metaBram_1_serverAdapterB_writeWithResp_wget,
metaBram_2_serverAdapterA_s1_1_wget,
metaBram_2_serverAdapterA_writeWithResp_wget,
metaBram_2_serverAdapterB_s1_1_wget,
metaBram_2_serverAdapterB_writeWithResp_wget,
metaBram_3_serverAdapterA_s1_1_wget,
metaBram_3_serverAdapterA_writeWithResp_wget,
metaBram_3_serverAdapterB_s1_1_wget,
metaBram_3_serverAdapterB_writeWithResp_wget;
wire dataBram_0_serverAdapterA_cnt_1_whas,
dataBram_0_serverAdapterA_cnt_2_whas,
dataBram_0_serverAdapterA_cnt_3_whas,
dataBram_0_serverAdapterA_outData_deqCalled_whas,
dataBram_0_serverAdapterA_outData_enqData_whas,
dataBram_0_serverAdapterA_outData_outData_whas,
dataBram_0_serverAdapterA_s1_1_whas,
dataBram_0_serverAdapterA_writeWithResp_whas,
dataBram_0_serverAdapterB_cnt_1_whas,
dataBram_0_serverAdapterB_cnt_2_whas,
dataBram_0_serverAdapterB_cnt_3_whas,
dataBram_0_serverAdapterB_outData_deqCalled_whas,
dataBram_0_serverAdapterB_outData_enqData_whas,
dataBram_0_serverAdapterB_outData_outData_whas,
dataBram_0_serverAdapterB_s1_1_whas,
dataBram_0_serverAdapterB_writeWithResp_whas,
metaBram_0_serverAdapterA_cnt_1_whas,
metaBram_0_serverAdapterA_cnt_2_whas,
metaBram_0_serverAdapterA_cnt_3_whas,
metaBram_0_serverAdapterA_outData_deqCalled_whas,
metaBram_0_serverAdapterA_outData_enqData_whas,
metaBram_0_serverAdapterA_outData_outData_whas,
metaBram_0_serverAdapterA_s1_1_whas,
metaBram_0_serverAdapterA_writeWithResp_whas,
metaBram_0_serverAdapterB_cnt_1_whas,
metaBram_0_serverAdapterB_cnt_2_whas,
metaBram_0_serverAdapterB_cnt_3_whas,
metaBram_0_serverAdapterB_outData_deqCalled_whas,
metaBram_0_serverAdapterB_outData_enqData_whas,
metaBram_0_serverAdapterB_outData_outData_whas,
metaBram_0_serverAdapterB_s1_1_whas,
metaBram_0_serverAdapterB_writeWithResp_whas,
metaBram_1_serverAdapterA_cnt_1_whas,
metaBram_1_serverAdapterA_cnt_2_whas,
metaBram_1_serverAdapterA_cnt_3_whas,
metaBram_1_serverAdapterA_outData_deqCalled_whas,
metaBram_1_serverAdapterA_outData_enqData_whas,
metaBram_1_serverAdapterA_outData_outData_whas,
metaBram_1_serverAdapterA_s1_1_whas,
metaBram_1_serverAdapterA_writeWithResp_whas,
metaBram_1_serverAdapterB_cnt_1_whas,
metaBram_1_serverAdapterB_cnt_2_whas,
metaBram_1_serverAdapterB_cnt_3_whas,
metaBram_1_serverAdapterB_outData_deqCalled_whas,
metaBram_1_serverAdapterB_outData_enqData_whas,
metaBram_1_serverAdapterB_outData_outData_whas,
metaBram_1_serverAdapterB_s1_1_whas,
metaBram_1_serverAdapterB_writeWithResp_whas,
metaBram_2_serverAdapterA_cnt_1_whas,
metaBram_2_serverAdapterA_cnt_2_whas,
metaBram_2_serverAdapterA_cnt_3_whas,
metaBram_2_serverAdapterA_outData_deqCalled_whas,
metaBram_2_serverAdapterA_outData_enqData_whas,
metaBram_2_serverAdapterA_outData_outData_whas,
metaBram_2_serverAdapterA_s1_1_whas,
metaBram_2_serverAdapterA_writeWithResp_whas,
metaBram_2_serverAdapterB_cnt_1_whas,
metaBram_2_serverAdapterB_cnt_2_whas,
metaBram_2_serverAdapterB_cnt_3_whas,
metaBram_2_serverAdapterB_outData_deqCalled_whas,
metaBram_2_serverAdapterB_outData_enqData_whas,
metaBram_2_serverAdapterB_outData_outData_whas,
metaBram_2_serverAdapterB_s1_1_whas,
metaBram_2_serverAdapterB_writeWithResp_whas,
metaBram_3_serverAdapterA_cnt_1_whas,
metaBram_3_serverAdapterA_cnt_2_whas,
metaBram_3_serverAdapterA_cnt_3_whas,
metaBram_3_serverAdapterA_outData_deqCalled_whas,
metaBram_3_serverAdapterA_outData_enqData_whas,
metaBram_3_serverAdapterA_outData_outData_whas,
metaBram_3_serverAdapterA_s1_1_whas,
metaBram_3_serverAdapterA_writeWithResp_whas,
metaBram_3_serverAdapterB_cnt_1_whas,
metaBram_3_serverAdapterB_cnt_2_whas,
metaBram_3_serverAdapterB_cnt_3_whas,
metaBram_3_serverAdapterB_outData_deqCalled_whas,
metaBram_3_serverAdapterB_outData_enqData_whas,
metaBram_3_serverAdapterB_outData_outData_whas,
metaBram_3_serverAdapterB_s1_1_whas,
metaBram_3_serverAdapterB_writeWithResp_whas,
nowW_whas,
statusReg_w_whas,
wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas,
wtiS_operateD_1_wget,
wtiS_operateD_1_whas,
wtiS_wtiReq_whas,
wti_Es_mCmd_w_whas,
wti_Es_mData_w_whas;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register dataBram_0_serverAdapterA_cnt
reg [2 : 0] dataBram_0_serverAdapterA_cnt;
wire [2 : 0] dataBram_0_serverAdapterA_cnt_D_IN;
wire dataBram_0_serverAdapterA_cnt_EN;
// register dataBram_0_serverAdapterA_s1
reg [1 : 0] dataBram_0_serverAdapterA_s1;
wire [1 : 0] dataBram_0_serverAdapterA_s1_D_IN;
wire dataBram_0_serverAdapterA_s1_EN;
// register dataBram_0_serverAdapterB_cnt
reg [2 : 0] dataBram_0_serverAdapterB_cnt;
wire [2 : 0] dataBram_0_serverAdapterB_cnt_D_IN;
wire dataBram_0_serverAdapterB_cnt_EN;
// register dataBram_0_serverAdapterB_s1
reg [1 : 0] dataBram_0_serverAdapterB_s1;
wire [1 : 0] dataBram_0_serverAdapterB_s1_D_IN;
wire dataBram_0_serverAdapterB_s1_EN;
// register dataCount
reg [31 : 0] dataCount;
reg [31 : 0] dataCount_D_IN;
wire dataCount_EN;
// register isFirst
reg isFirst;
wire isFirst_D_IN, isFirst_EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar_D_IN;
wire mesgLengthSoFar_EN;
// register metaBram_0_serverAdapterA_cnt
reg [2 : 0] metaBram_0_serverAdapterA_cnt;
wire [2 : 0] metaBram_0_serverAdapterA_cnt_D_IN;
wire metaBram_0_serverAdapterA_cnt_EN;
// register metaBram_0_serverAdapterA_s1
reg [1 : 0] metaBram_0_serverAdapterA_s1;
wire [1 : 0] metaBram_0_serverAdapterA_s1_D_IN;
wire metaBram_0_serverAdapterA_s1_EN;
// register metaBram_0_serverAdapterB_cnt
reg [2 : 0] metaBram_0_serverAdapterB_cnt;
wire [2 : 0] metaBram_0_serverAdapterB_cnt_D_IN;
wire metaBram_0_serverAdapterB_cnt_EN;
// register metaBram_0_serverAdapterB_s1
reg [1 : 0] metaBram_0_serverAdapterB_s1;
wire [1 : 0] metaBram_0_serverAdapterB_s1_D_IN;
wire metaBram_0_serverAdapterB_s1_EN;
// register metaBram_1_serverAdapterA_cnt
reg [2 : 0] metaBram_1_serverAdapterA_cnt;
wire [2 : 0] metaBram_1_serverAdapterA_cnt_D_IN;
wire metaBram_1_serverAdapterA_cnt_EN;
// register metaBram_1_serverAdapterA_s1
reg [1 : 0] metaBram_1_serverAdapterA_s1;
wire [1 : 0] metaBram_1_serverAdapterA_s1_D_IN;
wire metaBram_1_serverAdapterA_s1_EN;
// register metaBram_1_serverAdapterB_cnt
reg [2 : 0] metaBram_1_serverAdapterB_cnt;
wire [2 : 0] metaBram_1_serverAdapterB_cnt_D_IN;
wire metaBram_1_serverAdapterB_cnt_EN;
// register metaBram_1_serverAdapterB_s1
reg [1 : 0] metaBram_1_serverAdapterB_s1;
wire [1 : 0] metaBram_1_serverAdapterB_s1_D_IN;
wire metaBram_1_serverAdapterB_s1_EN;
// register metaBram_2_serverAdapterA_cnt
reg [2 : 0] metaBram_2_serverAdapterA_cnt;
wire [2 : 0] metaBram_2_serverAdapterA_cnt_D_IN;
wire metaBram_2_serverAdapterA_cnt_EN;
// register metaBram_2_serverAdapterA_s1
reg [1 : 0] metaBram_2_serverAdapterA_s1;
wire [1 : 0] metaBram_2_serverAdapterA_s1_D_IN;
wire metaBram_2_serverAdapterA_s1_EN;
// register metaBram_2_serverAdapterB_cnt
reg [2 : 0] metaBram_2_serverAdapterB_cnt;
wire [2 : 0] metaBram_2_serverAdapterB_cnt_D_IN;
wire metaBram_2_serverAdapterB_cnt_EN;
// register metaBram_2_serverAdapterB_s1
reg [1 : 0] metaBram_2_serverAdapterB_s1;
wire [1 : 0] metaBram_2_serverAdapterB_s1_D_IN;
wire metaBram_2_serverAdapterB_s1_EN;
// register metaBram_3_serverAdapterA_cnt
reg [2 : 0] metaBram_3_serverAdapterA_cnt;
wire [2 : 0] metaBram_3_serverAdapterA_cnt_D_IN;
wire metaBram_3_serverAdapterA_cnt_EN;
// register metaBram_3_serverAdapterA_s1
reg [1 : 0] metaBram_3_serverAdapterA_s1;
wire [1 : 0] metaBram_3_serverAdapterA_s1_D_IN;
wire metaBram_3_serverAdapterA_s1_EN;
// register metaBram_3_serverAdapterB_cnt
reg [2 : 0] metaBram_3_serverAdapterB_cnt;
wire [2 : 0] metaBram_3_serverAdapterB_cnt_D_IN;
wire metaBram_3_serverAdapterB_cnt_EN;
// register metaBram_3_serverAdapterB_s1
reg [1 : 0] metaBram_3_serverAdapterB_s1;
wire [1 : 0] metaBram_3_serverAdapterB_s1_D_IN;
wire metaBram_3_serverAdapterB_s1_EN;
// register metaCount
reg [31 : 0] metaCount;
reg [31 : 0] metaCount_D_IN;
wire metaCount_EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight_D_IN, splitReadInFlight_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// register wtiS_isReset_isInReset
reg wtiS_isReset_isInReset;
wire wtiS_isReset_isInReset_D_IN, wtiS_isReset_isInReset_EN;
// register wtiS_nowReq
reg [66 : 0] wtiS_nowReq;
wire [66 : 0] wtiS_nowReq_D_IN;
wire wtiS_nowReq_EN;
// register wtiS_operateD
reg wtiS_operateD;
wire wtiS_operateD_D_IN, wtiS_operateD_EN;
// ports of submodule dataBram_0_memory
wire [31 : 0] dataBram_0_memory_DIA,
dataBram_0_memory_DIB,
dataBram_0_memory_DOA,
dataBram_0_memory_DOB;
wire [9 : 0] dataBram_0_memory_ADDRA, dataBram_0_memory_ADDRB;
wire dataBram_0_memory_ENA,
dataBram_0_memory_ENB,
dataBram_0_memory_WEA,
dataBram_0_memory_WEB;
// ports of submodule dataBram_0_serverAdapterA_outDataCore
wire [31 : 0] dataBram_0_serverAdapterA_outDataCore_D_IN,
dataBram_0_serverAdapterA_outDataCore_D_OUT;
wire dataBram_0_serverAdapterA_outDataCore_CLR,
dataBram_0_serverAdapterA_outDataCore_DEQ,
dataBram_0_serverAdapterA_outDataCore_EMPTY_N,
dataBram_0_serverAdapterA_outDataCore_ENQ,
dataBram_0_serverAdapterA_outDataCore_FULL_N;
// ports of submodule dataBram_0_serverAdapterB_outDataCore
wire [31 : 0] dataBram_0_serverAdapterB_outDataCore_D_IN,
dataBram_0_serverAdapterB_outDataCore_D_OUT;
wire dataBram_0_serverAdapterB_outDataCore_CLR,
dataBram_0_serverAdapterB_outDataCore_DEQ,
dataBram_0_serverAdapterB_outDataCore_EMPTY_N,
dataBram_0_serverAdapterB_outDataCore_ENQ,
dataBram_0_serverAdapterB_outDataCore_FULL_N;
// ports of submodule metaBram_0_memory
wire [31 : 0] metaBram_0_memory_DIA,
metaBram_0_memory_DIB,
metaBram_0_memory_DOA,
metaBram_0_memory_DOB;
wire [9 : 0] metaBram_0_memory_ADDRA, metaBram_0_memory_ADDRB;
wire metaBram_0_memory_ENA,
metaBram_0_memory_ENB,
metaBram_0_memory_WEA,
metaBram_0_memory_WEB;
// ports of submodule metaBram_0_serverAdapterA_outDataCore
wire [31 : 0] metaBram_0_serverAdapterA_outDataCore_D_IN,
metaBram_0_serverAdapterA_outDataCore_D_OUT;
wire metaBram_0_serverAdapterA_outDataCore_CLR,
metaBram_0_serverAdapterA_outDataCore_DEQ,
metaBram_0_serverAdapterA_outDataCore_EMPTY_N,
metaBram_0_serverAdapterA_outDataCore_ENQ,
metaBram_0_serverAdapterA_outDataCore_FULL_N;
// ports of submodule metaBram_0_serverAdapterB_outDataCore
wire [31 : 0] metaBram_0_serverAdapterB_outDataCore_D_IN,
metaBram_0_serverAdapterB_outDataCore_D_OUT;
wire metaBram_0_serverAdapterB_outDataCore_CLR,
metaBram_0_serverAdapterB_outDataCore_DEQ,
metaBram_0_serverAdapterB_outDataCore_EMPTY_N,
metaBram_0_serverAdapterB_outDataCore_ENQ,
metaBram_0_serverAdapterB_outDataCore_FULL_N;
// ports of submodule metaBram_1_memory
wire [31 : 0] metaBram_1_memory_DIA,
metaBram_1_memory_DIB,
metaBram_1_memory_DOA,
metaBram_1_memory_DOB;
wire [9 : 0] metaBram_1_memory_ADDRA, metaBram_1_memory_ADDRB;
wire metaBram_1_memory_ENA,
metaBram_1_memory_ENB,
metaBram_1_memory_WEA,
metaBram_1_memory_WEB;
// ports of submodule metaBram_1_serverAdapterA_outDataCore
wire [31 : 0] metaBram_1_serverAdapterA_outDataCore_D_IN,
metaBram_1_serverAdapterA_outDataCore_D_OUT;
wire metaBram_1_serverAdapterA_outDataCore_CLR,
metaBram_1_serverAdapterA_outDataCore_DEQ,
metaBram_1_serverAdapterA_outDataCore_EMPTY_N,
metaBram_1_serverAdapterA_outDataCore_ENQ,
metaBram_1_serverAdapterA_outDataCore_FULL_N;
// ports of submodule metaBram_1_serverAdapterB_outDataCore
wire [31 : 0] metaBram_1_serverAdapterB_outDataCore_D_IN,
metaBram_1_serverAdapterB_outDataCore_D_OUT;
wire metaBram_1_serverAdapterB_outDataCore_CLR,
metaBram_1_serverAdapterB_outDataCore_DEQ,
metaBram_1_serverAdapterB_outDataCore_EMPTY_N,
metaBram_1_serverAdapterB_outDataCore_ENQ,
metaBram_1_serverAdapterB_outDataCore_FULL_N;
// ports of submodule metaBram_2_memory
wire [31 : 0] metaBram_2_memory_DIA,
metaBram_2_memory_DIB,
metaBram_2_memory_DOA,
metaBram_2_memory_DOB;
wire [9 : 0] metaBram_2_memory_ADDRA, metaBram_2_memory_ADDRB;
wire metaBram_2_memory_ENA,
metaBram_2_memory_ENB,
metaBram_2_memory_WEA,
metaBram_2_memory_WEB;
// ports of submodule metaBram_2_serverAdapterA_outDataCore
wire [31 : 0] metaBram_2_serverAdapterA_outDataCore_D_IN,
metaBram_2_serverAdapterA_outDataCore_D_OUT;
wire metaBram_2_serverAdapterA_outDataCore_CLR,
metaBram_2_serverAdapterA_outDataCore_DEQ,
metaBram_2_serverAdapterA_outDataCore_EMPTY_N,
metaBram_2_serverAdapterA_outDataCore_ENQ,
metaBram_2_serverAdapterA_outDataCore_FULL_N;
// ports of submodule metaBram_2_serverAdapterB_outDataCore
wire [31 : 0] metaBram_2_serverAdapterB_outDataCore_D_IN,
metaBram_2_serverAdapterB_outDataCore_D_OUT;
wire metaBram_2_serverAdapterB_outDataCore_CLR,
metaBram_2_serverAdapterB_outDataCore_DEQ,
metaBram_2_serverAdapterB_outDataCore_EMPTY_N,
metaBram_2_serverAdapterB_outDataCore_ENQ,
metaBram_2_serverAdapterB_outDataCore_FULL_N;
// ports of submodule metaBram_3_memory
wire [31 : 0] metaBram_3_memory_DIA,
metaBram_3_memory_DIB,
metaBram_3_memory_DOA,
metaBram_3_memory_DOB;
wire [9 : 0] metaBram_3_memory_ADDRA, metaBram_3_memory_ADDRB;
wire metaBram_3_memory_ENA,
metaBram_3_memory_ENB,
metaBram_3_memory_WEA,
metaBram_3_memory_WEB;
// ports of submodule metaBram_3_serverAdapterA_outDataCore
wire [31 : 0] metaBram_3_serverAdapterA_outDataCore_D_IN,
metaBram_3_serverAdapterA_outDataCore_D_OUT;
wire metaBram_3_serverAdapterA_outDataCore_CLR,
metaBram_3_serverAdapterA_outDataCore_DEQ,
metaBram_3_serverAdapterA_outDataCore_EMPTY_N,
metaBram_3_serverAdapterA_outDataCore_ENQ,
metaBram_3_serverAdapterA_outDataCore_FULL_N;
// ports of submodule metaBram_3_serverAdapterB_outDataCore
wire [31 : 0] metaBram_3_serverAdapterB_outDataCore_D_IN,
metaBram_3_serverAdapterB_outDataCore_D_OUT;
wire metaBram_3_serverAdapterB_outDataCore_CLR,
metaBram_3_serverAdapterB_outDataCore_DEQ,
metaBram_3_serverAdapterB_outDataCore_EMPTY_N,
metaBram_3_serverAdapterB_outDataCore_ENQ,
metaBram_3_serverAdapterB_outDataCore_FULL_N;
// ports of submodule splaF
wire [2 : 0] splaF_D_IN, splaF_D_OUT;
wire splaF_CLR, splaF_DEQ, splaF_EMPTY_N, splaF_ENQ, splaF_FULL_N;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_advance_split_response,
CAN_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3;
wire [31 : 0] MUX_dataCount_write_1__VAL_2, MUX_metaCount_write_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2;
wire MUX_controlReg_write_1__SEL_1,
MUX_controlReg_write_1__SEL_2,
MUX_dataCount_write_1__SEL_1,
MUX_dataCount_write_1__SEL_2,
MUX_metaCount_write_1__SEL_1,
MUX_metaCount_write_1__SEL_2,
MUX_splitReadInFlight_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wci_wslv_respF_x_wire_wset_1__SEL_1,
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h25329,
v__h26261,
v__h26550,
v__h26755,
v__h3586,
v__h3761,
v__h3905;
reg [31 : 0] SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940,
v__h26736;
reg CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909,
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914,
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975,
IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979;
wire [31 : 0] g_data__h27820,
rdat___1__h26833,
rdat___1__h26917,
rdat___1__h26972,
rdat___1__h26986,
rdat___1__h26994,
v__h25458,
y_avValue__h25982,
y_avValue__h26025,
y_avValue__h26065,
y_avValue__h26105,
y_avValue__h26145;
wire [13 : 0] mlB__h23202, mlInc__h23201;
wire [2 : 0] dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325,
metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443,
metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561,
metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679,
metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797,
x__h23250,
x__h23262,
x__h23274,
y__h23251,
y__h23263,
y__h23275;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916,
NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854,
_dfoo1,
_dfoo3,
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876,
dataCount_35_ULT_1024___d836,
metaCount_32_ULT_1024___d833;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wtiS0_sThreadBusy
assign wtiS0_SThreadBusy = wtiS_isReset_isInReset ;
// value method wtiS0_sReset_n
assign wtiS0_SReset_n = !wtiS_isReset_isInReset && wtiS_operateD ;
// submodule dataBram_0_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) dataBram_0_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(dataBram_0_memory_ADDRA),
.ADDRB(dataBram_0_memory_ADDRB),
.DIA(dataBram_0_memory_DIA),
.DIB(dataBram_0_memory_DIB),
.WEA(dataBram_0_memory_WEA),
.WEB(dataBram_0_memory_WEB),
.ENA(dataBram_0_memory_ENA),
.ENB(dataBram_0_memory_ENB),
.DOA(dataBram_0_memory_DOA),
.DOB(dataBram_0_memory_DOB));
// submodule dataBram_0_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) dataBram_0_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(dataBram_0_serverAdapterA_outDataCore_D_IN),
.ENQ(dataBram_0_serverAdapterA_outDataCore_ENQ),
.DEQ(dataBram_0_serverAdapterA_outDataCore_DEQ),
.CLR(dataBram_0_serverAdapterA_outDataCore_CLR),
.D_OUT(dataBram_0_serverAdapterA_outDataCore_D_OUT),
.FULL_N(dataBram_0_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(dataBram_0_serverAdapterA_outDataCore_EMPTY_N));
// submodule dataBram_0_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) dataBram_0_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(dataBram_0_serverAdapterB_outDataCore_D_IN),
.ENQ(dataBram_0_serverAdapterB_outDataCore_ENQ),
.DEQ(dataBram_0_serverAdapterB_outDataCore_DEQ),
.CLR(dataBram_0_serverAdapterB_outDataCore_CLR),
.D_OUT(dataBram_0_serverAdapterB_outDataCore_D_OUT),
.FULL_N(dataBram_0_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(dataBram_0_serverAdapterB_outDataCore_EMPTY_N));
// submodule metaBram_0_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) metaBram_0_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(metaBram_0_memory_ADDRA),
.ADDRB(metaBram_0_memory_ADDRB),
.DIA(metaBram_0_memory_DIA),
.DIB(metaBram_0_memory_DIB),
.WEA(metaBram_0_memory_WEA),
.WEB(metaBram_0_memory_WEB),
.ENA(metaBram_0_memory_ENA),
.ENB(metaBram_0_memory_ENB),
.DOA(metaBram_0_memory_DOA),
.DOB(metaBram_0_memory_DOB));
// submodule metaBram_0_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_0_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_0_serverAdapterA_outDataCore_D_IN),
.ENQ(metaBram_0_serverAdapterA_outDataCore_ENQ),
.DEQ(metaBram_0_serverAdapterA_outDataCore_DEQ),
.CLR(metaBram_0_serverAdapterA_outDataCore_CLR),
.D_OUT(metaBram_0_serverAdapterA_outDataCore_D_OUT),
.FULL_N(metaBram_0_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(metaBram_0_serverAdapterA_outDataCore_EMPTY_N));
// submodule metaBram_0_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_0_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_0_serverAdapterB_outDataCore_D_IN),
.ENQ(metaBram_0_serverAdapterB_outDataCore_ENQ),
.DEQ(metaBram_0_serverAdapterB_outDataCore_DEQ),
.CLR(metaBram_0_serverAdapterB_outDataCore_CLR),
.D_OUT(metaBram_0_serverAdapterB_outDataCore_D_OUT),
.FULL_N(metaBram_0_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(metaBram_0_serverAdapterB_outDataCore_EMPTY_N));
// submodule metaBram_1_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) metaBram_1_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(metaBram_1_memory_ADDRA),
.ADDRB(metaBram_1_memory_ADDRB),
.DIA(metaBram_1_memory_DIA),
.DIB(metaBram_1_memory_DIB),
.WEA(metaBram_1_memory_WEA),
.WEB(metaBram_1_memory_WEB),
.ENA(metaBram_1_memory_ENA),
.ENB(metaBram_1_memory_ENB),
.DOA(metaBram_1_memory_DOA),
.DOB(metaBram_1_memory_DOB));
// submodule metaBram_1_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_1_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_1_serverAdapterA_outDataCore_D_IN),
.ENQ(metaBram_1_serverAdapterA_outDataCore_ENQ),
.DEQ(metaBram_1_serverAdapterA_outDataCore_DEQ),
.CLR(metaBram_1_serverAdapterA_outDataCore_CLR),
.D_OUT(metaBram_1_serverAdapterA_outDataCore_D_OUT),
.FULL_N(metaBram_1_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(metaBram_1_serverAdapterA_outDataCore_EMPTY_N));
// submodule metaBram_1_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_1_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_1_serverAdapterB_outDataCore_D_IN),
.ENQ(metaBram_1_serverAdapterB_outDataCore_ENQ),
.DEQ(metaBram_1_serverAdapterB_outDataCore_DEQ),
.CLR(metaBram_1_serverAdapterB_outDataCore_CLR),
.D_OUT(metaBram_1_serverAdapterB_outDataCore_D_OUT),
.FULL_N(metaBram_1_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(metaBram_1_serverAdapterB_outDataCore_EMPTY_N));
// submodule metaBram_2_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) metaBram_2_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(metaBram_2_memory_ADDRA),
.ADDRB(metaBram_2_memory_ADDRB),
.DIA(metaBram_2_memory_DIA),
.DIB(metaBram_2_memory_DIB),
.WEA(metaBram_2_memory_WEA),
.WEB(metaBram_2_memory_WEB),
.ENA(metaBram_2_memory_ENA),
.ENB(metaBram_2_memory_ENB),
.DOA(metaBram_2_memory_DOA),
.DOB(metaBram_2_memory_DOB));
// submodule metaBram_2_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_2_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_2_serverAdapterA_outDataCore_D_IN),
.ENQ(metaBram_2_serverAdapterA_outDataCore_ENQ),
.DEQ(metaBram_2_serverAdapterA_outDataCore_DEQ),
.CLR(metaBram_2_serverAdapterA_outDataCore_CLR),
.D_OUT(metaBram_2_serverAdapterA_outDataCore_D_OUT),
.FULL_N(metaBram_2_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(metaBram_2_serverAdapterA_outDataCore_EMPTY_N));
// submodule metaBram_2_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_2_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_2_serverAdapterB_outDataCore_D_IN),
.ENQ(metaBram_2_serverAdapterB_outDataCore_ENQ),
.DEQ(metaBram_2_serverAdapterB_outDataCore_DEQ),
.CLR(metaBram_2_serverAdapterB_outDataCore_CLR),
.D_OUT(metaBram_2_serverAdapterB_outDataCore_D_OUT),
.FULL_N(metaBram_2_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(metaBram_2_serverAdapterB_outDataCore_EMPTY_N));
// submodule metaBram_3_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) metaBram_3_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(metaBram_3_memory_ADDRA),
.ADDRB(metaBram_3_memory_ADDRB),
.DIA(metaBram_3_memory_DIA),
.DIB(metaBram_3_memory_DIB),
.WEA(metaBram_3_memory_WEA),
.WEB(metaBram_3_memory_WEB),
.ENA(metaBram_3_memory_ENA),
.ENB(metaBram_3_memory_ENB),
.DOA(metaBram_3_memory_DOA),
.DOB(metaBram_3_memory_DOB));
// submodule metaBram_3_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_3_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_3_serverAdapterA_outDataCore_D_IN),
.ENQ(metaBram_3_serverAdapterA_outDataCore_ENQ),
.DEQ(metaBram_3_serverAdapterA_outDataCore_DEQ),
.CLR(metaBram_3_serverAdapterA_outDataCore_CLR),
.D_OUT(metaBram_3_serverAdapterA_outDataCore_D_OUT),
.FULL_N(metaBram_3_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(metaBram_3_serverAdapterA_outDataCore_EMPTY_N));
// submodule metaBram_3_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) metaBram_3_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaBram_3_serverAdapterB_outDataCore_D_IN),
.ENQ(metaBram_3_serverAdapterB_outDataCore_ENQ),
.DEQ(metaBram_3_serverAdapterB_outDataCore_DEQ),
.CLR(metaBram_3_serverAdapterB_outDataCore_CLR),
.D_OUT(metaBram_3_serverAdapterB_outDataCore_D_OUT),
.FULL_N(metaBram_3_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(metaBram_3_serverAdapterB_outDataCore_EMPTY_N));
// submodule splaF
FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(splaF_D_IN),
.ENQ(splaF_ENQ),
.DEQ(splaF_DEQ),
.CLR(splaF_CLR),
.D_OUT(splaF_D_OUT),
.FULL_N(splaF_FULL_N),
.EMPTY_N(splaF_EMPTY_N));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_wslv_reqF_EMPTY_N &&
IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 &&
(wci_wslv_reqF_D_OUT[63:52] == 12'h800 ||
wci_wslv_reqF_D_OUT[63:52] == 12'h400 ||
wci_wslv_respF_cntr_r != 2'd2) &&
wci_wslv_wci_cfrd_pw_whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_dataBram_0_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] == 12'h800 ;
// rule RL_metaBram_0_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd0 &&
wci_wslv_reqF_D_OUT[63:52] == 12'h400 ;
// rule RL_metaBram_1_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd1 &&
wci_wslv_reqF_D_OUT[63:52] == 12'h400 ;
// rule RL_metaBram_2_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd2 &&
wci_wslv_reqF_D_OUT[63:52] == 12'h400 ;
// rule RL_metaBram_3_serverAdapterB_stageReadResponseAlways
assign WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd3 &&
wci_wslv_reqF_D_OUT[63:52] == 12'h400 ;
// rule RL_advance_split_response
assign CAN_FIRE_RL_advance_split_response =
wci_wslv_respF_cntr_r != 2'd2 && splaF_EMPTY_N &&
IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916 &&
!wci_wslv_wci_cfwr_pw_whas &&
splitReadInFlight ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_dataBram_0_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq =
dataBram_0_serverAdapterB_outDataCore_EMPTY_N &&
dataBram_0_serverAdapterB_outDataCore_FULL_N &&
dataBram_0_serverAdapterB_outData_deqCalled_whas &&
dataBram_0_serverAdapterB_outData_enqData_whas ;
// rule RL_metaBram_0_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq =
metaBram_0_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_0_serverAdapterB_outDataCore_FULL_N &&
metaBram_0_serverAdapterB_outData_deqCalled_whas &&
metaBram_0_serverAdapterB_outData_enqData_whas ;
// rule RL_metaBram_1_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq =
metaBram_1_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_1_serverAdapterB_outDataCore_FULL_N &&
metaBram_1_serverAdapterB_outData_deqCalled_whas &&
metaBram_1_serverAdapterB_outData_enqData_whas ;
// rule RL_metaBram_2_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq =
metaBram_2_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_2_serverAdapterB_outDataCore_FULL_N &&
metaBram_2_serverAdapterB_outData_deqCalled_whas &&
metaBram_2_serverAdapterB_outData_enqData_whas ;
// rule RL_metaBram_3_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq =
metaBram_3_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_3_serverAdapterB_outDataCore_FULL_N &&
metaBram_3_serverAdapterB_outData_deqCalled_whas &&
metaBram_3_serverAdapterB_outData_enqData_whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_controlReg_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
assign MUX_controlReg_write_1__SEL_2 =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
assign MUX_dataCount_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h08 ;
assign MUX_dataCount_write_1__SEL_2 =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 ;
assign MUX_metaCount_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
assign MUX_metaCount_write_1__SEL_2 =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 &&
wsiS_reqFifo_D_OUT[57] ;
assign MUX_splitReadInFlight_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfrd &&
(wci_wslv_reqF_D_OUT[63:52] == 12'h800 ||
wci_wslv_reqF_D_OUT[63:52] == 12'h400) ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__SEL_1 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] != 12'h800 &&
wci_wslv_reqF_D_OUT[63:52] != 12'h400 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 =
CAN_FIRE_RL_advance_split_response &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiS_reqFifo_EMPTY_N &&
NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854 &&
wci_wslv_cState == 3'd2 ;
assign MUX_dataCount_write_1__VAL_2 = dataCount + 32'd1 ;
assign MUX_metaCount_write_1__VAL_2 = metaCount + 32'd1 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(MUX_wci_wslv_respF_x_wire_wset_1__SEL_1 or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_x_wire_wset_1__SEL_1:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 = { 2'd1, g_data__h27820 } ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_3 = { 2'd1, v__h25458 } ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] != 12'h800 &&
wci_wslv_reqF_D_OUT[63:52] != 12'h400 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
MUX_controlReg_write_1__SEL_2 ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wtiS_wtiReq_wget = 67'h0 ;
assign wtiS_wtiReq_whas = 1'b0 ;
assign wtiS_operateD_1_wget = 1'b0 ;
assign wtiS_operateD_1_whas = 1'b0 ;
assign nowW_wget = wtiS_nowReq[63:0] ;
assign nowW_whas = 1'd1 ;
assign statusReg_w_wget = rdat___1__h26833 ;
assign statusReg_w_whas = 1'd1 ;
assign dataBram_0_serverAdapterA_outData_enqData_wget =
dataBram_0_memory_DOA ;
assign dataBram_0_serverAdapterA_outData_enqData_whas =
(!dataBram_0_serverAdapterA_s1[0] ||
dataBram_0_serverAdapterA_outDataCore_FULL_N) &&
dataBram_0_serverAdapterA_s1[1] &&
dataBram_0_serverAdapterA_s1[0] ;
assign dataBram_0_serverAdapterA_outData_outData_wget =
dataBram_0_serverAdapterA_outDataCore_EMPTY_N ?
dataBram_0_serverAdapterA_outDataCore_D_OUT :
dataBram_0_memory_DOA ;
assign dataBram_0_serverAdapterA_outData_outData_whas =
dataBram_0_serverAdapterA_outDataCore_EMPTY_N ||
!dataBram_0_serverAdapterA_outDataCore_EMPTY_N &&
dataBram_0_serverAdapterA_outData_enqData_whas ;
assign dataBram_0_serverAdapterA_cnt_1_wget = 3'd1 ;
assign dataBram_0_serverAdapterA_cnt_1_whas = 1'b0 ;
assign dataBram_0_serverAdapterA_cnt_2_wget = 3'h0 ;
assign dataBram_0_serverAdapterA_cnt_2_whas = 1'b0 ;
assign dataBram_0_serverAdapterA_cnt_3_wget = 3'h0 ;
assign dataBram_0_serverAdapterA_cnt_3_whas = 1'b0 ;
assign dataBram_0_serverAdapterA_writeWithResp_wget = 2'd2 ;
assign dataBram_0_serverAdapterA_writeWithResp_whas =
MUX_dataCount_write_1__SEL_2 ;
assign dataBram_0_serverAdapterA_s1_1_wget = 2'd2 ;
assign dataBram_0_serverAdapterA_s1_1_whas = MUX_dataCount_write_1__SEL_2 ;
assign dataBram_0_serverAdapterB_outData_enqData_wget =
dataBram_0_memory_DOB ;
assign dataBram_0_serverAdapterB_outData_enqData_whas =
(!dataBram_0_serverAdapterB_s1[0] ||
dataBram_0_serverAdapterB_outDataCore_FULL_N) &&
dataBram_0_serverAdapterB_s1[1] &&
dataBram_0_serverAdapterB_s1[0] ;
assign dataBram_0_serverAdapterB_outData_outData_wget = y_avValue__h25982 ;
assign dataBram_0_serverAdapterB_outData_outData_whas =
dataBram_0_serverAdapterB_outDataCore_EMPTY_N ||
!dataBram_0_serverAdapterB_outDataCore_EMPTY_N &&
dataBram_0_serverAdapterB_outData_enqData_whas ;
assign dataBram_0_serverAdapterB_cnt_1_wget = 3'd1 ;
assign dataBram_0_serverAdapterB_cnt_1_whas =
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ;
assign dataBram_0_serverAdapterB_cnt_2_wget = 3'd7 ;
assign dataBram_0_serverAdapterB_cnt_2_whas =
dataBram_0_serverAdapterB_outData_deqCalled_whas ;
assign dataBram_0_serverAdapterB_cnt_3_wget = 3'h0 ;
assign dataBram_0_serverAdapterB_cnt_3_whas = 1'b0 ;
assign dataBram_0_serverAdapterB_writeWithResp_wget = 2'd0 ;
assign dataBram_0_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ;
assign dataBram_0_serverAdapterB_s1_1_wget = 2'd3 ;
assign dataBram_0_serverAdapterB_s1_1_whas =
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ;
assign metaBram_0_serverAdapterA_outData_enqData_wget =
metaBram_0_memory_DOA ;
assign metaBram_0_serverAdapterA_outData_enqData_whas =
(!metaBram_0_serverAdapterA_s1[0] ||
metaBram_0_serverAdapterA_outDataCore_FULL_N) &&
metaBram_0_serverAdapterA_s1[1] &&
metaBram_0_serverAdapterA_s1[0] ;
assign metaBram_0_serverAdapterA_outData_outData_wget =
metaBram_0_serverAdapterA_outDataCore_EMPTY_N ?
metaBram_0_serverAdapterA_outDataCore_D_OUT :
metaBram_0_memory_DOA ;
assign metaBram_0_serverAdapterA_outData_outData_whas =
metaBram_0_serverAdapterA_outDataCore_EMPTY_N ||
!metaBram_0_serverAdapterA_outDataCore_EMPTY_N &&
metaBram_0_serverAdapterA_outData_enqData_whas ;
assign metaBram_0_serverAdapterA_cnt_1_wget = 3'd1 ;
assign metaBram_0_serverAdapterA_cnt_1_whas = 1'b0 ;
assign metaBram_0_serverAdapterA_cnt_2_wget = 3'h0 ;
assign metaBram_0_serverAdapterA_cnt_2_whas = 1'b0 ;
assign metaBram_0_serverAdapterA_cnt_3_wget = 3'h0 ;
assign metaBram_0_serverAdapterA_cnt_3_whas = 1'b0 ;
assign metaBram_0_serverAdapterA_writeWithResp_wget = 2'd2 ;
assign metaBram_0_serverAdapterA_writeWithResp_whas =
MUX_metaCount_write_1__SEL_2 ;
assign metaBram_0_serverAdapterA_s1_1_wget = 2'd2 ;
assign metaBram_0_serverAdapterA_s1_1_whas = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_0_serverAdapterB_outData_enqData_wget =
metaBram_0_memory_DOB ;
assign metaBram_0_serverAdapterB_outData_enqData_whas =
(!metaBram_0_serverAdapterB_s1[0] ||
metaBram_0_serverAdapterB_outDataCore_FULL_N) &&
metaBram_0_serverAdapterB_s1[1] &&
metaBram_0_serverAdapterB_s1[0] ;
assign metaBram_0_serverAdapterB_outData_outData_wget = y_avValue__h26025 ;
assign metaBram_0_serverAdapterB_outData_outData_whas =
metaBram_0_serverAdapterB_outDataCore_EMPTY_N ||
!metaBram_0_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_0_serverAdapterB_outData_enqData_whas ;
assign metaBram_0_serverAdapterB_cnt_1_wget = 3'd1 ;
assign metaBram_0_serverAdapterB_cnt_1_whas =
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ;
assign metaBram_0_serverAdapterB_cnt_2_wget = 3'd7 ;
assign metaBram_0_serverAdapterB_cnt_2_whas =
metaBram_0_serverAdapterB_outData_deqCalled_whas ;
assign metaBram_0_serverAdapterB_cnt_3_wget = 3'h0 ;
assign metaBram_0_serverAdapterB_cnt_3_whas = 1'b0 ;
assign metaBram_0_serverAdapterB_writeWithResp_wget = 2'd0 ;
assign metaBram_0_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ;
assign metaBram_0_serverAdapterB_s1_1_wget = 2'd3 ;
assign metaBram_0_serverAdapterB_s1_1_whas =
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ;
assign metaBram_1_serverAdapterA_outData_enqData_wget =
metaBram_1_memory_DOA ;
assign metaBram_1_serverAdapterA_outData_enqData_whas =
(!metaBram_1_serverAdapterA_s1[0] ||
metaBram_1_serverAdapterA_outDataCore_FULL_N) &&
metaBram_1_serverAdapterA_s1[1] &&
metaBram_1_serverAdapterA_s1[0] ;
assign metaBram_1_serverAdapterA_outData_outData_wget =
metaBram_1_serverAdapterA_outDataCore_EMPTY_N ?
metaBram_1_serverAdapterA_outDataCore_D_OUT :
metaBram_1_memory_DOA ;
assign metaBram_1_serverAdapterA_outData_outData_whas =
metaBram_1_serverAdapterA_outDataCore_EMPTY_N ||
!metaBram_1_serverAdapterA_outDataCore_EMPTY_N &&
metaBram_1_serverAdapterA_outData_enqData_whas ;
assign metaBram_1_serverAdapterA_cnt_1_wget = 3'd1 ;
assign metaBram_1_serverAdapterA_cnt_1_whas = 1'b0 ;
assign metaBram_1_serverAdapterA_cnt_2_wget = 3'h0 ;
assign metaBram_1_serverAdapterA_cnt_2_whas = 1'b0 ;
assign metaBram_1_serverAdapterA_cnt_3_wget = 3'h0 ;
assign metaBram_1_serverAdapterA_cnt_3_whas = 1'b0 ;
assign metaBram_1_serverAdapterA_writeWithResp_wget = 2'd2 ;
assign metaBram_1_serverAdapterA_writeWithResp_whas =
MUX_metaCount_write_1__SEL_2 ;
assign metaBram_1_serverAdapterA_s1_1_wget = 2'd2 ;
assign metaBram_1_serverAdapterA_s1_1_whas = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_1_serverAdapterB_outData_enqData_wget =
metaBram_1_memory_DOB ;
assign metaBram_1_serverAdapterB_outData_enqData_whas =
(!metaBram_1_serverAdapterB_s1[0] ||
metaBram_1_serverAdapterB_outDataCore_FULL_N) &&
metaBram_1_serverAdapterB_s1[1] &&
metaBram_1_serverAdapterB_s1[0] ;
assign metaBram_1_serverAdapterB_outData_outData_wget = y_avValue__h26065 ;
assign metaBram_1_serverAdapterB_outData_outData_whas =
metaBram_1_serverAdapterB_outDataCore_EMPTY_N ||
!metaBram_1_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_1_serverAdapterB_outData_enqData_whas ;
assign metaBram_1_serverAdapterB_cnt_1_wget = 3'd1 ;
assign metaBram_1_serverAdapterB_cnt_1_whas =
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ;
assign metaBram_1_serverAdapterB_cnt_2_wget = 3'd7 ;
assign metaBram_1_serverAdapterB_cnt_2_whas =
metaBram_1_serverAdapterB_outData_deqCalled_whas ;
assign metaBram_1_serverAdapterB_cnt_3_wget = 3'h0 ;
assign metaBram_1_serverAdapterB_cnt_3_whas = 1'b0 ;
assign metaBram_1_serverAdapterB_writeWithResp_wget = 2'd0 ;
assign metaBram_1_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ;
assign metaBram_1_serverAdapterB_s1_1_wget = 2'd3 ;
assign metaBram_1_serverAdapterB_s1_1_whas =
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ;
assign metaBram_2_serverAdapterA_outData_enqData_wget =
metaBram_2_memory_DOA ;
assign metaBram_2_serverAdapterA_outData_enqData_whas =
(!metaBram_2_serverAdapterA_s1[0] ||
metaBram_2_serverAdapterA_outDataCore_FULL_N) &&
metaBram_2_serverAdapterA_s1[1] &&
metaBram_2_serverAdapterA_s1[0] ;
assign metaBram_2_serverAdapterA_outData_outData_wget =
metaBram_2_serverAdapterA_outDataCore_EMPTY_N ?
metaBram_2_serverAdapterA_outDataCore_D_OUT :
metaBram_2_memory_DOA ;
assign metaBram_2_serverAdapterA_outData_outData_whas =
metaBram_2_serverAdapterA_outDataCore_EMPTY_N ||
!metaBram_2_serverAdapterA_outDataCore_EMPTY_N &&
metaBram_2_serverAdapterA_outData_enqData_whas ;
assign metaBram_2_serverAdapterA_cnt_1_wget = 3'd1 ;
assign metaBram_2_serverAdapterA_cnt_1_whas = 1'b0 ;
assign metaBram_2_serverAdapterA_cnt_2_wget = 3'h0 ;
assign metaBram_2_serverAdapterA_cnt_2_whas = 1'b0 ;
assign metaBram_2_serverAdapterA_cnt_3_wget = 3'h0 ;
assign metaBram_2_serverAdapterA_cnt_3_whas = 1'b0 ;
assign metaBram_2_serverAdapterA_writeWithResp_wget = 2'd2 ;
assign metaBram_2_serverAdapterA_writeWithResp_whas =
MUX_metaCount_write_1__SEL_2 ;
assign metaBram_2_serverAdapterA_s1_1_wget = 2'd2 ;
assign metaBram_2_serverAdapterA_s1_1_whas = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_2_serverAdapterB_outData_enqData_wget =
metaBram_2_memory_DOB ;
assign metaBram_2_serverAdapterB_outData_enqData_whas =
(!metaBram_2_serverAdapterB_s1[0] ||
metaBram_2_serverAdapterB_outDataCore_FULL_N) &&
metaBram_2_serverAdapterB_s1[1] &&
metaBram_2_serverAdapterB_s1[0] ;
assign metaBram_2_serverAdapterB_outData_outData_wget = y_avValue__h26105 ;
assign metaBram_2_serverAdapterB_outData_outData_whas =
metaBram_2_serverAdapterB_outDataCore_EMPTY_N ||
!metaBram_2_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_2_serverAdapterB_outData_enqData_whas ;
assign metaBram_2_serverAdapterB_cnt_1_wget = 3'd1 ;
assign metaBram_2_serverAdapterB_cnt_1_whas =
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ;
assign metaBram_2_serverAdapterB_cnt_2_wget = 3'd7 ;
assign metaBram_2_serverAdapterB_cnt_2_whas =
metaBram_2_serverAdapterB_outData_deqCalled_whas ;
assign metaBram_2_serverAdapterB_cnt_3_wget = 3'h0 ;
assign metaBram_2_serverAdapterB_cnt_3_whas = 1'b0 ;
assign metaBram_2_serverAdapterB_writeWithResp_wget = 2'd0 ;
assign metaBram_2_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ;
assign metaBram_2_serverAdapterB_s1_1_wget = 2'd3 ;
assign metaBram_2_serverAdapterB_s1_1_whas =
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ;
assign metaBram_3_serverAdapterA_outData_enqData_wget =
metaBram_3_memory_DOA ;
assign metaBram_3_serverAdapterA_outData_enqData_whas =
(!metaBram_3_serverAdapterA_s1[0] ||
metaBram_3_serverAdapterA_outDataCore_FULL_N) &&
metaBram_3_serverAdapterA_s1[1] &&
metaBram_3_serverAdapterA_s1[0] ;
assign metaBram_3_serverAdapterA_outData_outData_wget =
metaBram_3_serverAdapterA_outDataCore_EMPTY_N ?
metaBram_3_serverAdapterA_outDataCore_D_OUT :
metaBram_3_memory_DOA ;
assign metaBram_3_serverAdapterA_outData_outData_whas =
metaBram_3_serverAdapterA_outDataCore_EMPTY_N ||
!metaBram_3_serverAdapterA_outDataCore_EMPTY_N &&
metaBram_3_serverAdapterA_outData_enqData_whas ;
assign metaBram_3_serverAdapterA_cnt_1_wget = 3'd1 ;
assign metaBram_3_serverAdapterA_cnt_1_whas = 1'b0 ;
assign metaBram_3_serverAdapterA_cnt_2_wget = 3'h0 ;
assign metaBram_3_serverAdapterA_cnt_2_whas = 1'b0 ;
assign metaBram_3_serverAdapterA_cnt_3_wget = 3'h0 ;
assign metaBram_3_serverAdapterA_cnt_3_whas = 1'b0 ;
assign metaBram_3_serverAdapterA_writeWithResp_wget = 2'd2 ;
assign metaBram_3_serverAdapterA_writeWithResp_whas =
MUX_metaCount_write_1__SEL_2 ;
assign metaBram_3_serverAdapterA_s1_1_wget = 2'd2 ;
assign metaBram_3_serverAdapterA_s1_1_whas = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_3_serverAdapterB_outData_enqData_wget =
metaBram_3_memory_DOB ;
assign metaBram_3_serverAdapterB_outData_enqData_whas =
(!metaBram_3_serverAdapterB_s1[0] ||
metaBram_3_serverAdapterB_outDataCore_FULL_N) &&
metaBram_3_serverAdapterB_s1[1] &&
metaBram_3_serverAdapterB_s1[0] ;
assign metaBram_3_serverAdapterB_outData_outData_wget = y_avValue__h26145 ;
assign metaBram_3_serverAdapterB_outData_outData_whas =
metaBram_3_serverAdapterB_outDataCore_EMPTY_N ||
!metaBram_3_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_3_serverAdapterB_outData_enqData_whas ;
assign metaBram_3_serverAdapterB_cnt_1_wget = 3'd1 ;
assign metaBram_3_serverAdapterB_cnt_1_whas =
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ;
assign metaBram_3_serverAdapterB_cnt_2_wget = 3'd7 ;
assign metaBram_3_serverAdapterB_cnt_2_whas =
metaBram_3_serverAdapterB_outData_deqCalled_whas ;
assign metaBram_3_serverAdapterB_cnt_3_wget = 3'h0 ;
assign metaBram_3_serverAdapterB_cnt_3_whas = 1'b0 ;
assign metaBram_3_serverAdapterB_writeWithResp_wget = 2'd0 ;
assign metaBram_3_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ;
assign metaBram_3_serverAdapterB_s1_1_wget = 2'd3 ;
assign metaBram_3_serverAdapterB_s1_1_whas =
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wti_Es_mCmd_w_wget = wtiS0_MCmd ;
assign wti_Es_mCmd_w_whas = 1'd1 ;
assign wti_Es_mData_w_wget = wtiS0_MData ;
assign wti_Es_mData_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] != 12'h800 &&
wci_wslv_reqF_D_OUT[63:52] != 12'h400 ||
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign dataBram_0_serverAdapterA_outData_deqCalled_whas = 1'b0 ;
assign dataBram_0_serverAdapterB_outData_deqCalled_whas =
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 && splaF_D_OUT[2] &&
splaF_D_OUT[1:0] == 2'd0 ;
assign metaBram_0_serverAdapterA_outData_deqCalled_whas = 1'b0 ;
assign metaBram_0_serverAdapterB_outData_deqCalled_whas =
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 &&
splaF_D_OUT[1:0] == 2'd0 &&
!splaF_D_OUT[2] ;
assign metaBram_1_serverAdapterA_outData_deqCalled_whas = 1'b0 ;
assign metaBram_1_serverAdapterB_outData_deqCalled_whas =
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 &&
splaF_D_OUT[1:0] == 2'd1 &&
!splaF_D_OUT[2] ;
assign metaBram_2_serverAdapterA_outData_deqCalled_whas = 1'b0 ;
assign metaBram_2_serverAdapterB_outData_deqCalled_whas =
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 &&
splaF_D_OUT[1:0] == 2'd2 &&
!splaF_D_OUT[2] ;
assign metaBram_3_serverAdapterA_outData_deqCalled_whas = 1'b0 ;
assign metaBram_3_serverAdapterB_outData_deqCalled_whas =
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 &&
splaF_D_OUT[1:0] == 2'd3 &&
!splaF_D_OUT[2] ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
// register controlReg
assign controlReg_D_IN =
MUX_controlReg_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign controlReg_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ||
MUX_controlReg_write_1__SEL_2 ;
// register dataBram_0_serverAdapterA_cnt
assign dataBram_0_serverAdapterA_cnt_D_IN =
dataBram_0_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign dataBram_0_serverAdapterA_cnt_EN = 1'b0 ;
// register dataBram_0_serverAdapterA_s1
assign dataBram_0_serverAdapterA_s1_D_IN =
{ MUX_dataCount_write_1__SEL_2, 1'b0 } ;
assign dataBram_0_serverAdapterA_s1_EN = 1'd1 ;
// register dataBram_0_serverAdapterB_cnt
assign dataBram_0_serverAdapterB_cnt_D_IN =
dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325 ;
assign dataBram_0_serverAdapterB_cnt_EN =
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ||
dataBram_0_serverAdapterB_outData_deqCalled_whas ;
// register dataBram_0_serverAdapterB_s1
assign dataBram_0_serverAdapterB_s1_D_IN =
{ WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign dataBram_0_serverAdapterB_s1_EN = 1'd1 ;
// register dataCount
always@(MUX_dataCount_write_1__SEL_1 or
wci_wslv_reqF_D_OUT or
MUX_dataCount_write_1__SEL_2 or
MUX_dataCount_write_1__VAL_2 or MUX_controlReg_write_1__SEL_2)
case (1'b1)
MUX_dataCount_write_1__SEL_1: dataCount_D_IN = wci_wslv_reqF_D_OUT[31:0];
MUX_dataCount_write_1__SEL_2:
dataCount_D_IN = MUX_dataCount_write_1__VAL_2;
MUX_controlReg_write_1__SEL_2: dataCount_D_IN = 32'd0;
default: dataCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign dataCount_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 ||
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h08 ||
MUX_controlReg_write_1__SEL_2 ;
// register isFirst
assign isFirst_D_IN = 1'b0 ;
assign isFirst_EN = 1'b0 ;
// register mesgLengthSoFar
assign mesgLengthSoFar_D_IN = wsiS_reqFifo_D_OUT[57] ? 14'd0 : mlB__h23202 ;
assign mesgLengthSoFar_EN = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register metaBram_0_serverAdapterA_cnt
assign metaBram_0_serverAdapterA_cnt_D_IN =
metaBram_0_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign metaBram_0_serverAdapterA_cnt_EN = 1'b0 ;
// register metaBram_0_serverAdapterA_s1
assign metaBram_0_serverAdapterA_s1_D_IN =
{ MUX_metaCount_write_1__SEL_2, 1'b0 } ;
assign metaBram_0_serverAdapterA_s1_EN = 1'd1 ;
// register metaBram_0_serverAdapterB_cnt
assign metaBram_0_serverAdapterB_cnt_D_IN =
metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443 ;
assign metaBram_0_serverAdapterB_cnt_EN =
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ||
metaBram_0_serverAdapterB_outData_deqCalled_whas ;
// register metaBram_0_serverAdapterB_s1
assign metaBram_0_serverAdapterB_s1_D_IN =
{ WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign metaBram_0_serverAdapterB_s1_EN = 1'd1 ;
// register metaBram_1_serverAdapterA_cnt
assign metaBram_1_serverAdapterA_cnt_D_IN =
metaBram_1_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign metaBram_1_serverAdapterA_cnt_EN = 1'b0 ;
// register metaBram_1_serverAdapterA_s1
assign metaBram_1_serverAdapterA_s1_D_IN =
{ MUX_metaCount_write_1__SEL_2, 1'b0 } ;
assign metaBram_1_serverAdapterA_s1_EN = 1'd1 ;
// register metaBram_1_serverAdapterB_cnt
assign metaBram_1_serverAdapterB_cnt_D_IN =
metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561 ;
assign metaBram_1_serverAdapterB_cnt_EN =
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ||
metaBram_1_serverAdapterB_outData_deqCalled_whas ;
// register metaBram_1_serverAdapterB_s1
assign metaBram_1_serverAdapterB_s1_D_IN =
{ WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign metaBram_1_serverAdapterB_s1_EN = 1'd1 ;
// register metaBram_2_serverAdapterA_cnt
assign metaBram_2_serverAdapterA_cnt_D_IN =
metaBram_2_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign metaBram_2_serverAdapterA_cnt_EN = 1'b0 ;
// register metaBram_2_serverAdapterA_s1
assign metaBram_2_serverAdapterA_s1_D_IN =
{ MUX_metaCount_write_1__SEL_2, 1'b0 } ;
assign metaBram_2_serverAdapterA_s1_EN = 1'd1 ;
// register metaBram_2_serverAdapterB_cnt
assign metaBram_2_serverAdapterB_cnt_D_IN =
metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679 ;
assign metaBram_2_serverAdapterB_cnt_EN =
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ||
metaBram_2_serverAdapterB_outData_deqCalled_whas ;
// register metaBram_2_serverAdapterB_s1
assign metaBram_2_serverAdapterB_s1_D_IN =
{ WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign metaBram_2_serverAdapterB_s1_EN = 1'd1 ;
// register metaBram_3_serverAdapterA_cnt
assign metaBram_3_serverAdapterA_cnt_D_IN =
metaBram_3_serverAdapterA_cnt + 3'd0 + 3'd0 ;
assign metaBram_3_serverAdapterA_cnt_EN = 1'b0 ;
// register metaBram_3_serverAdapterA_s1
assign metaBram_3_serverAdapterA_s1_D_IN =
{ MUX_metaCount_write_1__SEL_2, 1'b0 } ;
assign metaBram_3_serverAdapterA_s1_EN = 1'd1 ;
// register metaBram_3_serverAdapterB_cnt
assign metaBram_3_serverAdapterB_cnt_D_IN =
metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797 ;
assign metaBram_3_serverAdapterB_cnt_EN =
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ||
metaBram_3_serverAdapterB_outData_deqCalled_whas ;
// register metaBram_3_serverAdapterB_s1
assign metaBram_3_serverAdapterB_s1_D_IN =
{ WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways,
1'b1 } ;
assign metaBram_3_serverAdapterB_s1_EN = 1'd1 ;
// register metaCount
always@(MUX_metaCount_write_1__SEL_1 or
wci_wslv_reqF_D_OUT or
MUX_metaCount_write_1__SEL_2 or
MUX_metaCount_write_1__VAL_2 or MUX_controlReg_write_1__SEL_2)
case (1'b1)
MUX_metaCount_write_1__SEL_1: metaCount_D_IN = wci_wslv_reqF_D_OUT[31:0];
MUX_metaCount_write_1__SEL_2:
metaCount_D_IN = MUX_metaCount_write_1__VAL_2;
MUX_controlReg_write_1__SEL_2: metaCount_D_IN = 32'd0;
default: metaCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign metaCount_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 &&
wsiS_reqFifo_D_OUT[57] ||
MUX_controlReg_write_1__SEL_2 ;
// register splitReadInFlight
assign splitReadInFlight_D_IN = MUX_splitReadInFlight_write_1__SEL_1 ;
assign splitReadInFlight_EN =
WILL_FIRE_RL_wci_cfrd &&
(wci_wslv_reqF_D_OUT[63:52] == 12'h800 ||
wci_wslv_reqF_D_OUT[63:52] == 12'h400) ||
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[57] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wtiS_isReset_isInReset
assign wtiS_isReset_isInReset_D_IN = 1'd0 ;
assign wtiS_isReset_isInReset_EN = wtiS_isReset_isInReset ;
// register wtiS_nowReq
assign wtiS_nowReq_D_IN = { wtiS0_MCmd, wtiS0_MData } ;
assign wtiS_nowReq_EN = 1'd1 ;
// register wtiS_operateD
assign wtiS_operateD_D_IN = 1'b1 ;
assign wtiS_operateD_EN = 1'd1 ;
// submodule dataBram_0_memory
assign dataBram_0_memory_ADDRA = dataCount[9:0] ;
assign dataBram_0_memory_ADDRB = wci_wslv_reqF_D_OUT[43:34] ;
assign dataBram_0_memory_DIA = wsiS_reqFifo_D_OUT[43:12] ;
assign dataBram_0_memory_DIB = 32'd0 ;
assign dataBram_0_memory_WEA = 1'd1 ;
assign dataBram_0_memory_WEB = 1'd0 ;
assign dataBram_0_memory_ENA = MUX_dataCount_write_1__SEL_2 ;
assign dataBram_0_memory_ENB =
WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ;
// submodule dataBram_0_serverAdapterA_outDataCore
assign dataBram_0_serverAdapterA_outDataCore_D_IN = dataBram_0_memory_DOA ;
assign dataBram_0_serverAdapterA_outDataCore_ENQ =
dataBram_0_serverAdapterA_outDataCore_FULL_N &&
dataBram_0_serverAdapterA_outData_enqData_whas ;
assign dataBram_0_serverAdapterA_outDataCore_DEQ = 1'b0 ;
assign dataBram_0_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule dataBram_0_serverAdapterB_outDataCore
assign dataBram_0_serverAdapterB_outDataCore_D_IN = dataBram_0_memory_DOB ;
assign dataBram_0_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq ||
dataBram_0_serverAdapterB_outDataCore_FULL_N &&
!dataBram_0_serverAdapterB_outData_deqCalled_whas &&
dataBram_0_serverAdapterB_outData_enqData_whas ;
assign dataBram_0_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq ||
dataBram_0_serverAdapterB_outDataCore_EMPTY_N &&
dataBram_0_serverAdapterB_outData_deqCalled_whas &&
!dataBram_0_serverAdapterB_outData_enqData_whas ;
assign dataBram_0_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule metaBram_0_memory
assign metaBram_0_memory_ADDRA = metaCount[9:0] ;
assign metaBram_0_memory_ADDRB = wci_wslv_reqF_D_OUT[45:36] ;
assign metaBram_0_memory_DIA = { 18'd0, mlB__h23202 } ;
assign metaBram_0_memory_DIB = 32'd0 ;
assign metaBram_0_memory_WEA = 1'd1 ;
assign metaBram_0_memory_WEB = 1'd0 ;
assign metaBram_0_memory_ENA = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_0_memory_ENB =
WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ;
// submodule metaBram_0_serverAdapterA_outDataCore
assign metaBram_0_serverAdapterA_outDataCore_D_IN = metaBram_0_memory_DOA ;
assign metaBram_0_serverAdapterA_outDataCore_ENQ =
metaBram_0_serverAdapterA_outDataCore_FULL_N &&
metaBram_0_serverAdapterA_outData_enqData_whas ;
assign metaBram_0_serverAdapterA_outDataCore_DEQ = 1'b0 ;
assign metaBram_0_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule metaBram_0_serverAdapterB_outDataCore
assign metaBram_0_serverAdapterB_outDataCore_D_IN = metaBram_0_memory_DOB ;
assign metaBram_0_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq ||
metaBram_0_serverAdapterB_outDataCore_FULL_N &&
!metaBram_0_serverAdapterB_outData_deqCalled_whas &&
metaBram_0_serverAdapterB_outData_enqData_whas ;
assign metaBram_0_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq ||
metaBram_0_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_0_serverAdapterB_outData_deqCalled_whas &&
!metaBram_0_serverAdapterB_outData_enqData_whas ;
assign metaBram_0_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule metaBram_1_memory
assign metaBram_1_memory_ADDRA = metaCount[9:0] ;
assign metaBram_1_memory_ADDRB = wci_wslv_reqF_D_OUT[45:36] ;
assign metaBram_1_memory_DIA = { 24'd0, wsiS_reqFifo_D_OUT[7:0] } ;
assign metaBram_1_memory_DIB = 32'd0 ;
assign metaBram_1_memory_WEA = 1'd1 ;
assign metaBram_1_memory_WEB = 1'd0 ;
assign metaBram_1_memory_ENA = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_1_memory_ENB =
WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ;
// submodule metaBram_1_serverAdapterA_outDataCore
assign metaBram_1_serverAdapterA_outDataCore_D_IN = metaBram_1_memory_DOA ;
assign metaBram_1_serverAdapterA_outDataCore_ENQ =
metaBram_1_serverAdapterA_outDataCore_FULL_N &&
metaBram_1_serverAdapterA_outData_enqData_whas ;
assign metaBram_1_serverAdapterA_outDataCore_DEQ = 1'b0 ;
assign metaBram_1_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule metaBram_1_serverAdapterB_outDataCore
assign metaBram_1_serverAdapterB_outDataCore_D_IN = metaBram_1_memory_DOB ;
assign metaBram_1_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq ||
metaBram_1_serverAdapterB_outDataCore_FULL_N &&
!metaBram_1_serverAdapterB_outData_deqCalled_whas &&
metaBram_1_serverAdapterB_outData_enqData_whas ;
assign metaBram_1_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq ||
metaBram_1_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_1_serverAdapterB_outData_deqCalled_whas &&
!metaBram_1_serverAdapterB_outData_enqData_whas ;
assign metaBram_1_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule metaBram_2_memory
assign metaBram_2_memory_ADDRA = metaCount[9:0] ;
assign metaBram_2_memory_ADDRB = wci_wslv_reqF_D_OUT[45:36] ;
assign metaBram_2_memory_DIA = nowW_wget[63:32] ;
assign metaBram_2_memory_DIB = 32'd0 ;
assign metaBram_2_memory_WEA = 1'd1 ;
assign metaBram_2_memory_WEB = 1'd0 ;
assign metaBram_2_memory_ENA = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_2_memory_ENB =
WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ;
// submodule metaBram_2_serverAdapterA_outDataCore
assign metaBram_2_serverAdapterA_outDataCore_D_IN = metaBram_2_memory_DOA ;
assign metaBram_2_serverAdapterA_outDataCore_ENQ =
metaBram_2_serverAdapterA_outDataCore_FULL_N &&
metaBram_2_serverAdapterA_outData_enqData_whas ;
assign metaBram_2_serverAdapterA_outDataCore_DEQ = 1'b0 ;
assign metaBram_2_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule metaBram_2_serverAdapterB_outDataCore
assign metaBram_2_serverAdapterB_outDataCore_D_IN = metaBram_2_memory_DOB ;
assign metaBram_2_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq ||
metaBram_2_serverAdapterB_outDataCore_FULL_N &&
!metaBram_2_serverAdapterB_outData_deqCalled_whas &&
metaBram_2_serverAdapterB_outData_enqData_whas ;
assign metaBram_2_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq ||
metaBram_2_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_2_serverAdapterB_outData_deqCalled_whas &&
!metaBram_2_serverAdapterB_outData_enqData_whas ;
assign metaBram_2_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule metaBram_3_memory
assign metaBram_3_memory_ADDRA = metaCount[9:0] ;
assign metaBram_3_memory_ADDRB = wci_wslv_reqF_D_OUT[45:36] ;
assign metaBram_3_memory_DIA = nowW_wget[31:0] ;
assign metaBram_3_memory_DIB = 32'd0 ;
assign metaBram_3_memory_WEA = 1'd1 ;
assign metaBram_3_memory_WEB = 1'd0 ;
assign metaBram_3_memory_ENA = MUX_metaCount_write_1__SEL_2 ;
assign metaBram_3_memory_ENB =
WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ;
// submodule metaBram_3_serverAdapterA_outDataCore
assign metaBram_3_serverAdapterA_outDataCore_D_IN = metaBram_3_memory_DOA ;
assign metaBram_3_serverAdapterA_outDataCore_ENQ =
metaBram_3_serverAdapterA_outDataCore_FULL_N &&
metaBram_3_serverAdapterA_outData_enqData_whas ;
assign metaBram_3_serverAdapterA_outDataCore_DEQ = 1'b0 ;
assign metaBram_3_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule metaBram_3_serverAdapterB_outDataCore
assign metaBram_3_serverAdapterB_outDataCore_D_IN = metaBram_3_memory_DOB ;
assign metaBram_3_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq ||
metaBram_3_serverAdapterB_outDataCore_FULL_N &&
!metaBram_3_serverAdapterB_outData_deqCalled_whas &&
metaBram_3_serverAdapterB_outData_enqData_whas ;
assign metaBram_3_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq ||
metaBram_3_serverAdapterB_outDataCore_EMPTY_N &&
metaBram_3_serverAdapterB_outData_deqCalled_whas &&
!metaBram_3_serverAdapterB_outData_enqData_whas ;
assign metaBram_3_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule splaF
assign splaF_D_IN =
(wci_wslv_reqF_D_OUT[63:52] == 12'h800) ?
3'd4 :
{ 1'd0, wci_wslv_reqF_D_OUT[35:34] } ;
assign splaF_ENQ = MUX_splitReadInFlight_write_1__SEL_1 ;
assign splaF_DEQ = MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 ;
assign splaF_CLR = 1'b0 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916 =
splaF_D_OUT[2] ?
(splaF_D_OUT[1:0] != 2'd0 ||
dataBram_0_serverAdapterB_outDataCore_EMPTY_N ||
dataBram_0_serverAdapterB_outData_enqData_whas) &&
(splaF_D_OUT[1:0] != 2'd0 ||
dataBram_0_serverAdapterB_outData_outData_whas) :
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 &&
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 ;
assign NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854 =
!controlReg[0] ||
controlReg[1] &&
(!metaCount_32_ULT_1024___d833 ||
!dataCount_35_ULT_1024___d836) ||
(dataBram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(!wsiS_reqFifo_D_OUT[57] ||
(metaBram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(metaBram_1_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(metaBram_2_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
(metaBram_3_serverAdapterA_cnt ^ 3'h4) < 3'd7) ;
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 =
controlReg[0] &&
(!controlReg[1] ||
metaCount_32_ULT_1024___d833 && dataCount_35_ULT_1024___d836) ;
assign dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325 =
dataBram_0_serverAdapterB_cnt +
(WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(dataBram_0_serverAdapterB_outData_deqCalled_whas ?
3'd7 :
3'd0) ;
assign dataCount_35_ULT_1024___d836 = dataCount < 32'd1024 ;
assign g_data__h27820 =
(wci_wslv_reqF_D_OUT[63:52] == 12'h0) ? v__h26736 : 32'd0 ;
assign metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443 =
metaBram_0_serverAdapterB_cnt +
(WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(metaBram_0_serverAdapterB_outData_deqCalled_whas ?
3'd7 :
3'd0) ;
assign metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561 =
metaBram_1_serverAdapterB_cnt +
(WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(metaBram_1_serverAdapterB_outData_deqCalled_whas ?
3'd7 :
3'd0) ;
assign metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679 =
metaBram_2_serverAdapterB_cnt +
(WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(metaBram_2_serverAdapterB_outData_deqCalled_whas ?
3'd7 :
3'd0) ;
assign metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797 =
metaBram_3_serverAdapterB_cnt +
(WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ?
3'd1 :
3'd0) +
(metaBram_3_serverAdapterB_outData_deqCalled_whas ?
3'd7 :
3'd0) ;
assign metaCount_32_ULT_1024___d833 = metaCount < 32'd1024 ;
assign mlB__h23202 = mesgLengthSoFar + mlInc__h23201 ;
assign mlInc__h23201 =
wsiS_reqFifo_D_OUT[57] ?
{ 11'd0, x__h23250 + y__h23251 } :
14'd4 ;
assign rdat___1__h26833 =
{ 6'd40,
!metaCount_32_ULT_1024___d833,
!dataCount_35_ULT_1024___d836,
24'd2361866 } ;
assign rdat___1__h26917 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ;
assign rdat___1__h26972 =
hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat___1__h26986 =
hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat___1__h26994 =
hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign v__h25458 =
splaF_D_OUT[2] ?
y_avValue__h25982 :
SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x__h23250 = x__h23262 + y__h23263 ;
assign x__h23262 = x__h23274 + y__h23275 ;
assign x__h23274 = { 2'd0, wsiS_reqFifo_D_OUT[11] } ;
assign y__h23251 = { 2'd0, wsiS_reqFifo_D_OUT[8] } ;
assign y__h23263 = { 2'd0, wsiS_reqFifo_D_OUT[9] } ;
assign y__h23275 = { 2'd0, wsiS_reqFifo_D_OUT[10] } ;
assign y_avValue__h25982 =
dataBram_0_serverAdapterB_outDataCore_EMPTY_N ?
dataBram_0_serverAdapterB_outDataCore_D_OUT :
dataBram_0_memory_DOB ;
assign y_avValue__h26025 =
metaBram_0_serverAdapterB_outDataCore_EMPTY_N ?
metaBram_0_serverAdapterB_outDataCore_D_OUT :
metaBram_0_memory_DOB ;
assign y_avValue__h26065 =
metaBram_1_serverAdapterB_outDataCore_EMPTY_N ?
metaBram_1_serverAdapterB_outDataCore_D_OUT :
metaBram_1_memory_DOB ;
assign y_avValue__h26105 =
metaBram_2_serverAdapterB_outDataCore_EMPTY_N ?
metaBram_2_serverAdapterB_outDataCore_D_OUT :
metaBram_2_memory_DOB ;
assign y_avValue__h26145 =
metaBram_3_serverAdapterB_outDataCore_EMPTY_N ?
metaBram_3_serverAdapterB_outDataCore_D_OUT :
metaBram_3_memory_DOB ;
always@(wci_wslv_reqF_D_OUT or
metaBram_0_serverAdapterB_cnt or
metaBram_1_serverAdapterB_cnt or
metaBram_2_serverAdapterB_cnt or metaBram_3_serverAdapterB_cnt)
begin
case (wci_wslv_reqF_D_OUT[35:34])
2'd0:
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 =
(metaBram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7;
2'd1:
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 =
(metaBram_1_serverAdapterB_cnt ^ 3'h4) < 3'd7;
2'd2:
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 =
(metaBram_2_serverAdapterB_cnt ^ 3'h4) < 3'd7;
2'd3:
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 =
(metaBram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7;
endcase
end
always@(wci_wslv_reqF_D_OUT or
controlReg or
metaCount or
dataCount or
rdat___1__h26833 or
rdat___1__h26917 or
rdat___1__h26972 or rdat___1__h26986 or rdat___1__h26994)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: v__h26736 = controlReg;
8'h04: v__h26736 = metaCount;
8'h08: v__h26736 = dataCount;
8'h0C: v__h26736 = rdat___1__h26833;
8'h10: v__h26736 = rdat___1__h26917;
8'h14: v__h26736 = rdat___1__h26972;
8'h18: v__h26736 = rdat___1__h26986;
8'h1C: v__h26736 = rdat___1__h26994;
default: v__h26736 = 32'd0;
endcase
end
always@(wci_wslv_reqF_D_OUT or
splaF_FULL_N or
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 or
dataBram_0_serverAdapterB_cnt)
begin
case (wci_wslv_reqF_D_OUT[63:52])
12'h0: IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 = 1'b1;
12'h800:
IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 =
(dataBram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7 && splaF_FULL_N;
default: IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 =
wci_wslv_reqF_D_OUT[63:52] != 12'h400 ||
splaF_FULL_N &&
CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975;
endcase
end
always@(splaF_D_OUT or
y_avValue__h26025 or
y_avValue__h26065 or y_avValue__h26105 or y_avValue__h26145)
begin
case (splaF_D_OUT[1:0])
2'd0:
SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 =
y_avValue__h26025;
2'd1:
SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 =
y_avValue__h26065;
2'd2:
SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 =
y_avValue__h26105;
2'd3:
SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 =
y_avValue__h26145;
endcase
end
always@(splaF_D_OUT or
metaBram_0_serverAdapterB_outDataCore_EMPTY_N or
metaBram_0_serverAdapterB_outData_enqData_whas or
metaBram_1_serverAdapterB_outDataCore_EMPTY_N or
metaBram_1_serverAdapterB_outData_enqData_whas or
metaBram_2_serverAdapterB_outDataCore_EMPTY_N or
metaBram_2_serverAdapterB_outData_enqData_whas or
metaBram_3_serverAdapterB_outDataCore_EMPTY_N or
metaBram_3_serverAdapterB_outData_enqData_whas)
begin
case (splaF_D_OUT[1:0])
2'd0:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 =
metaBram_0_serverAdapterB_outDataCore_EMPTY_N ||
metaBram_0_serverAdapterB_outData_enqData_whas;
2'd1:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 =
metaBram_1_serverAdapterB_outDataCore_EMPTY_N ||
metaBram_1_serverAdapterB_outData_enqData_whas;
2'd2:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 =
metaBram_2_serverAdapterB_outDataCore_EMPTY_N ||
metaBram_2_serverAdapterB_outData_enqData_whas;
2'd3:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 =
metaBram_3_serverAdapterB_outDataCore_EMPTY_N ||
metaBram_3_serverAdapterB_outData_enqData_whas;
endcase
end
always@(splaF_D_OUT or
metaBram_0_serverAdapterB_outData_outData_whas or
metaBram_1_serverAdapterB_outData_outData_whas or
metaBram_2_serverAdapterB_outData_outData_whas or
metaBram_3_serverAdapterB_outData_outData_whas)
begin
case (splaF_D_OUT[1:0])
2'd0:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 =
metaBram_0_serverAdapterB_outData_outData_whas;
2'd1:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 =
metaBram_1_serverAdapterB_outData_outData_whas;
2'd2:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 =
metaBram_2_serverAdapterB_outData_outData_whas;
2'd3:
CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 =
metaBram_3_serverAdapterB_outData_outData_whas;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
dataBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
dataBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
dataBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
dataBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
isFirst <= `BSV_ASSIGNMENT_DELAY 1'd1;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
metaBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
metaBram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
metaBram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
wtiS_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (dataBram_0_serverAdapterA_cnt_EN)
dataBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
dataBram_0_serverAdapterA_cnt_D_IN;
if (dataBram_0_serverAdapterA_s1_EN)
dataBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
dataBram_0_serverAdapterA_s1_D_IN;
if (dataBram_0_serverAdapterB_cnt_EN)
dataBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
dataBram_0_serverAdapterB_cnt_D_IN;
if (dataBram_0_serverAdapterB_s1_EN)
dataBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
dataBram_0_serverAdapterB_s1_D_IN;
if (isFirst_EN) isFirst <= `BSV_ASSIGNMENT_DELAY isFirst_D_IN;
if (mesgLengthSoFar_EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar_D_IN;
if (metaBram_0_serverAdapterA_cnt_EN)
metaBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_0_serverAdapterA_cnt_D_IN;
if (metaBram_0_serverAdapterA_s1_EN)
metaBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_0_serverAdapterA_s1_D_IN;
if (metaBram_0_serverAdapterB_cnt_EN)
metaBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_0_serverAdapterB_cnt_D_IN;
if (metaBram_0_serverAdapterB_s1_EN)
metaBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_0_serverAdapterB_s1_D_IN;
if (metaBram_1_serverAdapterA_cnt_EN)
metaBram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_1_serverAdapterA_cnt_D_IN;
if (metaBram_1_serverAdapterA_s1_EN)
metaBram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_1_serverAdapterA_s1_D_IN;
if (metaBram_1_serverAdapterB_cnt_EN)
metaBram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_1_serverAdapterB_cnt_D_IN;
if (metaBram_1_serverAdapterB_s1_EN)
metaBram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_1_serverAdapterB_s1_D_IN;
if (metaBram_2_serverAdapterA_cnt_EN)
metaBram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_2_serverAdapterA_cnt_D_IN;
if (metaBram_2_serverAdapterA_s1_EN)
metaBram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_2_serverAdapterA_s1_D_IN;
if (metaBram_2_serverAdapterB_cnt_EN)
metaBram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_2_serverAdapterB_cnt_D_IN;
if (metaBram_2_serverAdapterB_s1_EN)
metaBram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_2_serverAdapterB_s1_D_IN;
if (metaBram_3_serverAdapterA_cnt_EN)
metaBram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_3_serverAdapterA_cnt_D_IN;
if (metaBram_3_serverAdapterA_s1_EN)
metaBram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_3_serverAdapterA_s1_D_IN;
if (metaBram_3_serverAdapterB_cnt_EN)
metaBram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
metaBram_3_serverAdapterB_cnt_D_IN;
if (metaBram_3_serverAdapterB_s1_EN)
metaBram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
metaBram_3_serverAdapterB_s1_D_IN;
if (splitReadInFlight_EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight_D_IN;
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
if (wtiS_nowReq_EN)
wtiS_nowReq <= `BSV_ASSIGNMENT_DELAY wtiS_nowReq_D_IN;
if (wtiS_operateD_EN)
wtiS_operateD <= `BSV_ASSIGNMENT_DELAY wtiS_operateD_D_IN;
end
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
if (dataCount_EN) dataCount <= `BSV_ASSIGNMENT_DELAY dataCount_D_IN;
if (metaCount_EN) metaCount <= `BSV_ASSIGNMENT_DELAY metaCount_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wtiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
if (wtiS_isReset_isInReset_EN)
wtiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wtiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
controlReg = 32'hAAAAAAAA;
dataBram_0_serverAdapterA_cnt = 3'h2;
dataBram_0_serverAdapterA_s1 = 2'h2;
dataBram_0_serverAdapterB_cnt = 3'h2;
dataBram_0_serverAdapterB_s1 = 2'h2;
dataCount = 32'hAAAAAAAA;
isFirst = 1'h0;
mesgLengthSoFar = 14'h2AAA;
metaBram_0_serverAdapterA_cnt = 3'h2;
metaBram_0_serverAdapterA_s1 = 2'h2;
metaBram_0_serverAdapterB_cnt = 3'h2;
metaBram_0_serverAdapterB_s1 = 2'h2;
metaBram_1_serverAdapterA_cnt = 3'h2;
metaBram_1_serverAdapterA_s1 = 2'h2;
metaBram_1_serverAdapterB_cnt = 3'h2;
metaBram_1_serverAdapterB_s1 = 2'h2;
metaBram_2_serverAdapterA_cnt = 3'h2;
metaBram_2_serverAdapterA_s1 = 2'h2;
metaBram_2_serverAdapterB_cnt = 3'h2;
metaBram_2_serverAdapterB_s1 = 2'h2;
metaBram_3_serverAdapterA_cnt = 3'h2;
metaBram_3_serverAdapterA_s1 = 2'h2;
metaBram_3_serverAdapterB_cnt = 3'h2;
metaBram_3_serverAdapterB_s1 = 2'h2;
metaCount = 32'hAAAAAAAA;
splitReadInFlight = 1'h0;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
wtiS_isReset_isInReset = 1'h0;
wtiS_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiS_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3586 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3586,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] == 12'h0)
begin
v__h26755 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[63:52] == 12'h0)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h26755,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
v__h26736);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 &&
wsiS_reqFifo_D_OUT[57])
begin
v__h25329 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 &&
wsiS_reqFifo_D_OUT[57])
$display("[%0d]: %m: doMessageAccept DWM metaCount:%0x WSI opcode:%0x length:%0x",
v__h25329,
metaCount,
wsiS_reqFifo_D_OUT[7:0],
mlB__h23202);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h26550 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h26550,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3905 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3905,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3761 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3761,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (dataBram_0_serverAdapterA_s1[1] &&
!dataBram_0_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (dataBram_0_serverAdapterB_s1[1] &&
!dataBram_0_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_0_serverAdapterA_s1[1] &&
!metaBram_0_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_0_serverAdapterB_s1[1] &&
!metaBram_0_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_1_serverAdapterA_s1[1] &&
!metaBram_1_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_1_serverAdapterB_s1[1] &&
!metaBram_1_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_2_serverAdapterA_s1[1] &&
!metaBram_2_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_2_serverAdapterB_s1[1] &&
!metaBram_2_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_3_serverAdapterA_s1[1] &&
!metaBram_3_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (metaBram_3_serverAdapterB_s1[1] &&
!metaBram_3_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
begin
v__h26261 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h26261, v__h25458);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_controlReg_write_1__SEL_2)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_controlReg_write_1__SEL_2)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_controlReg_write_1__SEL_2 &&
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_controlReg_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_controlReg_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO &&
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_OrE &&
MUX_wci_wslv_respF_x_wire_wset_1__SEL_3)
$display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 76: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkWSICaptureWorker4B
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../conb/sky130_fd_sc_hd__conb.v"
`include "../nor2/sky130_fd_sc_hd__nor2.v"
`include "../inv/sky130_fd_sc_hd__inv.v"
`include "../nand2/sky130_fd_sc_hd__nand2.v"
`celldefine
module sky130_fd_sc_hd__macro_sparecell (
LO ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output LO ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire nor2left ;
wire invleft ;
wire nor2right;
wire invright ;
wire nd2left ;
wire nd2right ;
wire tielo ;
wire net7 ;
// Name Output Other arguments
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
buf buf0 (LO , tielo );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module ym_regs(
input PHI_M,
input nRESET,
input nWRITE_S,
input [1:0] ADDR_S,
input [7:0] DATA_S,
output reg BUSY_MMR,
// SSG
output reg [11:0] SSG_FREQ_A,
output reg [11:0] SSG_FREQ_B,
output reg [11:0] SSG_FREQ_C,
output reg [4:0] SSG_NOISE,
output reg [5:0] SSG_EN,
output reg [4:0] SSG_VOL_A,
output reg [4:0] SSG_VOL_B,
output reg [4:0] SSG_VOL_C,
output reg [15:0] SSG_ENV_FREQ,
output reg [3:0] SSG_ENV,
// Timer
output reg [9:0] YMTIMER_TA_LOAD,
output reg [7:0] YMTIMER_TB_LOAD,
output reg [5:0] YMTIMER_CONFIG,
output reg clr_run_A, set_run_A, clr_run_B, set_run_B,
// ADPCM-A
output reg [7:0] PCMA_KEYON,
output reg [7:0] PCMA_KEYOFF,
output reg [5:0] PCMA_MVOL,
output reg [7:0] PCMA_VOLPAN_A,
output reg [7:0] PCMA_VOLPAN_B,
output reg [7:0] PCMA_VOLPAN_C,
output reg [7:0] PCMA_VOLPAN_D,
output reg [7:0] PCMA_VOLPAN_E,
output reg [7:0] PCMA_VOLPAN_F,
output reg [15:0] PCMA_START_A,
output reg [15:0] PCMA_START_B,
output reg [15:0] PCMA_START_C,
output reg [15:0] PCMA_START_D,
output reg [15:0] PCMA_START_E,
output reg [15:0] PCMA_START_F,
output reg [15:0] PCMA_STOP_A,
output reg [15:0] PCMA_STOP_B,
output reg [15:0] PCMA_STOP_C,
output reg [15:0] PCMA_STOP_D,
output reg [15:0] PCMA_STOP_E,
output reg [15:0] PCMA_STOP_F,
output reg [5:0] PCMA_FLAGMASK,
output reg PCMA_FLAGMASK_PCMB,
// ADPCM-B
output reg PCMB_RESET, PCMB_REPEAT, PCMB_START,
output reg [1:0] PCMB_PAN,
output reg [15:0] PCMB_START_ADDR,
output reg [15:0] PCMB_STOP_ADDR,
output reg [15:0] PCMB_DELTA,
output reg [7:0] PCMB_TL
);
// Internal - Seems there's only one address register + 1-bit reg to select part A/B
reg [7:0] REG_ADDR;
reg PART;
// FM (todo)
reg [3:0] FM_LFO;
reg [7:0] FM_KEYON;
reg [6:0] FM_DTMUL[3:0];
reg [6:0] FM_TL[3:0];
reg [7:0] FM_KSAR[3:0];
reg [7:0] FM_AMDR[3:0];
reg [4:0] FM_SR[3:0];
reg [7:0] FM_SLRR[3:0];
reg [3:0] FM_SSGEG[3:0];
reg [13:0] FM_FNUM13;
reg [13:0] FM_FNUM24;
reg [13:0] FM_2FNUM13;
reg [13:0] FM_2FNUM24;
reg [5:0] FM_FBALGO13;
reg [5:0] FM_FBALGO24;
reg [7:0] FM_PAN13;
reg [7:0] FM_PAN24;
always @(posedge PHI_M)
begin
if (!nRESET)
begin
// Registers init
// Registers inits
BUSY_MMR <= 0;
REG_ADDR <= 0; // ?
PART <= 0; // ?
PCMA_FLAGMASK <= 0;
PCMA_FLAGMASK_PCMB <= 0;
PCMA_KEYON <= 0;
PCMA_KEYOFF <= 0;
PCMA_MVOL <= 0;
PCMA_VOLPAN_A <= 0;
PCMA_VOLPAN_B <= 0;
PCMA_VOLPAN_C <= 0;
PCMA_VOLPAN_D <= 0;
PCMA_VOLPAN_E <= 0;
PCMA_VOLPAN_F <= 0;
PCMA_START_A <= 0;
PCMA_START_B <= 0;
PCMA_START_C <= 0;
PCMA_START_D <= 0;
PCMA_START_E <= 0;
PCMA_START_F <= 0;
PCMA_STOP_A <= 0;
PCMA_STOP_B <= 0;
PCMA_STOP_C <= 0;
PCMA_STOP_D <= 0;
PCMA_STOP_E <= 0;
PCMA_STOP_F <= 0;
PCMB_RESET <= 0;
PCMB_REPEAT <= 0;
PCMB_START <= 0;
PCMB_PAN <= 0;
// Timers
{ YMTIMER_TA_LOAD, YMTIMER_TB_LOAD } <= 18'd0;
YMTIMER_CONFIG <= 6'd0;
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'b1100;
end
else
begin
if (!nWRITE_S && !BUSY_MMR)
begin
// CPU write
BUSY_MMR <= 1'b1;
if (!ADDR_S[0]) // Set address
begin
REG_ADDR <= DATA_S;
PART <= ADDR_S[1];
if (!ADDR_S[1])
$display("YM2610 part A address register %H", DATA_S); // DEBUG
else
$display("YM2610 part B address register %H", DATA_S); // DEBUG
end
else // Set register data
begin
if (ADDR_S[1] == PART) // This is correct, ADDR_S[1] needs to match set PART value
begin
if (!ADDR_S[1])
begin
$display("YM2610 part A set register %H to %H", REG_ADDR, DATA_S); // DEBUG
case (REG_ADDR)
8'h00: SSG_FREQ_A[7:0] <= DATA_S;
8'h01: SSG_FREQ_A[11:8] <= DATA_S[3:0];
8'h02: SSG_FREQ_B[7:0] <= DATA_S;
8'h03: SSG_FREQ_B[11:8] <= DATA_S[3:0];
8'h04: SSG_FREQ_C[7:0] <= DATA_S;
8'h05: SSG_FREQ_C[11:8] <= DATA_S[3:0];
8'h06: SSG_NOISE <= DATA_S[4:0];
8'h07: SSG_EN <= DATA_S[5:0];
8'h08: SSG_VOL_A <= DATA_S[4:0];
8'h09: SSG_VOL_B <= DATA_S[4:0];
8'h0A: SSG_VOL_C <= DATA_S[4:0];
8'h0B: SSG_ENV_FREQ[7:0] <= DATA_S;
8'h0C: SSG_ENV_FREQ[15:8] <= DATA_S;
8'h0D: SSG_ENV <= DATA_S[4:0];
8'h10:
begin
PCMB_RESET <= DATA_S[0];
PCMB_REPEAT <= DATA_S[4];
PCMB_START <= DATA_S[7];
end
8'h11: PCMB_PAN <= DATA_S[7:6];
8'h12: PCMB_START_ADDR[7:0] <= DATA_S;
8'h13: PCMB_START_ADDR[15:8] <= DATA_S;
8'h14: PCMB_STOP_ADDR[7:0] <= DATA_S;
8'h15: PCMB_STOP_ADDR[15:8] <= DATA_S;
8'h19: PCMB_DELTA[7:0] <= DATA_S;
8'h1A: PCMB_DELTA[15:8] <= DATA_S;
8'h1B: PCMB_TL <= DATA_S;
8'h1C:
begin
PCMA_FLAGMASK <= DATA_S[5:0];
PCMA_FLAGMASK_PCMB <= DATA_S[7];
end
8'h24: YMTIMER_TA_LOAD[7:0] <= DATA_S;
8'h25: YMTIMER_TA_LOAD[9:8] <= DATA_S[1:0];
8'h26: YMTIMER_TB_LOAD <= DATA_S;
8'h27:
begin
// CSM <= DATA_S[7];
YMTIMER_CONFIG <= DATA_S[5:0];
clr_run_A <= ~DATA_S[0];
set_run_A <= DATA_S[0];
clr_run_B <= ~DATA_S[1];
set_run_B <= DATA_S[1];
end
// FM: Todo
// Default needed
endcase
end
else
begin
$display("YM2610 part B set register %H to %H", REG_ADDR, DATA_S); // DEBUG
case (REG_ADDR)
8'h00:
begin
if (!DATA_S[7])
PCMA_KEYON <= DATA_S;
else
PCMA_KEYOFF <= DATA_S;
end
8'h01: PCMA_MVOL <= DATA_S[5:0];
8'b00001000: PCMA_VOLPAN_A <= DATA_S;
8'b00001001: PCMA_VOLPAN_B <= DATA_S;
8'b00001010: PCMA_VOLPAN_C <= DATA_S;
8'b00001011: PCMA_VOLPAN_D <= DATA_S;
8'b00001100: PCMA_VOLPAN_E <= DATA_S;
8'b00001101: PCMA_VOLPAN_F <= DATA_S;
8'b00010000: PCMA_START_A[7:0] <= DATA_S;
8'b00010001: PCMA_START_B[7:0] <= DATA_S;
8'b00010010: PCMA_START_C[7:0] <= DATA_S;
8'b00010011: PCMA_START_D[7:0] <= DATA_S;
8'b00010100: PCMA_START_E[7:0] <= DATA_S;
8'b00010101: PCMA_START_F[7:0] <= DATA_S;
8'b00011000: PCMA_START_A[15:8] <= DATA_S;
8'b00011001: PCMA_START_B[15:8] <= DATA_S;
8'b00011010: PCMA_START_C[15:8] <= DATA_S;
8'b00011011: PCMA_START_D[15:8] <= DATA_S;
8'b00011100: PCMA_START_E[15:8] <= DATA_S;
8'b00011101: PCMA_START_F[15:8] <= DATA_S;
8'b00100000: PCMA_STOP_A[7:0] <= DATA_S;
8'b00100001: PCMA_STOP_B[7:0] <= DATA_S;
8'b00100010: PCMA_STOP_C[7:0] <= DATA_S;
8'b00100011: PCMA_STOP_D[7:0] <= DATA_S;
8'b00100100: PCMA_STOP_E[7:0] <= DATA_S;
8'b00100101: PCMA_STOP_F[7:0] <= DATA_S;
8'b00101000: PCMA_STOP_A[15:8] <= DATA_S;
8'b00101001: PCMA_STOP_B[15:8] <= DATA_S;
8'b00101010: PCMA_STOP_C[15:8] <= DATA_S;
8'b00101011: PCMA_STOP_D[15:8] <= DATA_S;
8'b00101100: PCMA_STOP_E[15:8] <= DATA_S;
8'b00101101: PCMA_STOP_F[15:8] <= DATA_S;
// Default needed
endcase
end
end
end
end
else
begin
BUSY_MMR <= 0; // DEBUG
YMTIMER_CONFIG[5:4] <= 2'd0;
YMTIMER_CONFIG[1:0] <= 2'd0;
PCMA_KEYON <= 0; // ?
PCMA_KEYOFF <= 0; // ?
PCMB_RESET <= 0; // ?
PCMB_START <= 0; // ?
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'd0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_0_V
`define SKY130_FD_SC_LP__A41OI_0_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_0 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_0 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_0_V
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: nf2_core.v 5145 2009-03-03 01:47:05Z grg $
//
// Module: nf2_core.v
// Project: NetFPGA
// Description: Core module for a NetFPGA design.
//
// This is instantiated within the nf2_top module.
// This should contain internal logic only - not I/O buffers or pads.
//
///////////////////////////////////////////////////////////////////////////////
module nf2_core #(
parameter UDP_REG_SRC_WIDTH = 2
)
(
// JTAG Interface
input wire [26:0] control_port_address,
input wire control_port_read,
output wire [31:0] control_port_readdata,
input wire control_port_write,
input wire [31:0] control_port_writedata,
output wire control_port_waitrequest,
output wire control_port_read_datavalid,
output wire [31:0] rxm_port_readdata,
output [7:0] gmac_tx_data_1_out,
output gmac_tx_dvld_1_out,
input gmac_tx_ack_1_out,
output end_of_packet_1_out,
output start_of_packet_1_out,
input [7:0] gmac_rx_data_1_in,
input gmac_rx_dvld_1_in,
input gmac_rx_frame_error_1_in,
output [7:0] gmac_tx_data_2_out,
output gmac_tx_dvld_2_out,
input gmac_tx_ack_2_out,
output end_of_packet_2_out,
output start_of_packet_2_out,
input [7:0] gmac_rx_data_2_in,
input gmac_rx_dvld_2_in,
input gmac_rx_frame_error_2_in,
output [7:0] gmac_tx_data_3_out,
output gmac_tx_dvld_3_out,
input gmac_tx_ack_3_out,
output end_of_packet_3_out,
output start_of_packet_3_out,
input [7:0] gmac_rx_data_3_in,
input gmac_rx_dvld_3_in,
input gmac_rx_frame_error_3_in,
output [7:0] gmac_tx_data_0_out,
output gmac_tx_dvld_0_out,
input gmac_tx_ack_0_out,
output end_of_packet_0_out,
output start_of_packet_0_out,
input [7:0] gmac_rx_data_0_in,
input gmac_rx_dvld_0_in,
input gmac_rx_frame_error_0_in,
// input tx_rgmii_clk_int,
// input rx_rgmii_0_clk_int,
// input rx_rgmii_1_clk_int,
// input rx_rgmii_2_clk_int,
// input rx_rgmii_3_clk_int,
// core clock
input core_clk_int,
// misc
input reset
);
//------------- local parameters --------------
localparam DATA_WIDTH = 64;
localparam CTRL_WIDTH = DATA_WIDTH/8;
localparam NUM_QUEUES = 8;
localparam PKT_LEN_CNT_WIDTH = 11;
//---------------- Wires/regs ------------------
// FIXME
assign nf2_err = 1'b 0;
// Do NOT disable resets
assign disable_reset = 1'b0;
wire [NUM_QUEUES-1:0] out_wr;
wire [NUM_QUEUES-1:0] out_rdy;
wire [DATA_WIDTH-1:0] out_data [NUM_QUEUES-1:0];
wire [CTRL_WIDTH-1:0] out_ctrl [NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] in_wr;
wire [NUM_QUEUES-1:0] in_rdy;
wire [DATA_WIDTH-1:0] in_data [NUM_QUEUES-1:0];
wire [CTRL_WIDTH-1:0] in_ctrl [NUM_QUEUES-1:0];
wire wr_0_req;
wire [`SRAM_ADDR_WIDTH-1:0] wr_0_addr;
wire [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
wire wr_0_ack;
wire rd_0_req;
wire [`SRAM_ADDR_WIDTH-1:0] rd_0_addr;
wire [DATA_WIDTH+CTRL_WIDTH-1:0] rd_0_data;
wire rd_0_vld;
wire rd_0_ack;
wire [`SRAM_ADDR_WIDTH-1:0] sram_addr;
wire [`CPCI_NF2_ADDR_WIDTH-1:0] cpci_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] cpci_reg_rd_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] cpci_reg_wr_data;
wire core_reg_req;
wire core_reg_rd_wr_L;
wire core_reg_ack;
wire [`CORE_REG_ADDR_WIDTH-1:0] core_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] core_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] core_reg_rd_data;
wire [3:0] core_4mb_reg_req;
wire [3:0] core_4mb_reg_rd_wr_L;
wire [3:0] core_4mb_reg_ack;
wire [4 * `BLOCK_SIZE_1M_REG_ADDR_WIDTH-1:0] core_4mb_reg_addr;
wire [4 * `CPCI_NF2_DATA_WIDTH-1:0] core_4mb_reg_wr_data;
wire [4 * `CPCI_NF2_DATA_WIDTH-1:0] core_4mb_reg_rd_data;
wire [15:0] core_256kb_0_reg_req;
wire [15:0] core_256kb_0_reg_rd_wr_L;
wire [15:0] core_256kb_0_reg_ack;
wire [16 * `BLOCK_SIZE_64k_REG_ADDR_WIDTH-1:0] core_256kb_0_reg_addr;
wire [16 * `CPCI_NF2_DATA_WIDTH-1:0] core_256kb_0_reg_wr_data;
wire [16 * `CPCI_NF2_DATA_WIDTH-1:0] core_256kb_0_reg_rd_data;
wire sram_reg_req;
wire sram_reg_rd_wr_L;
wire sram_reg_ack;
wire [`SRAM_REG_ADDR_WIDTH-1:0] sram_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] sram_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] sram_reg_rd_data;
wire udp_reg_req;
wire udp_reg_rd_wr_L;
wire udp_reg_ack;
wire [`UDP_REG_ADDR_WIDTH-1:0] udp_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] udp_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] udp_reg_rd_data;
wire dram_reg_req;
wire dram_reg_rd_wr_L;
wire dram_reg_ack;
wire [`DRAM_REG_ADDR_WIDTH-1:0] dram_reg_addr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] dram_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] dram_reg_rd_data;
wire [7:0] gmii_txd_int[(NUM_QUEUES / 2) - 1:0];
wire gmii_tx_en_int[(NUM_QUEUES / 2) - 1:0];
wire gmii_tx_er_int[(NUM_QUEUES / 2) - 1:0];
wire gmii_crs_int[(NUM_QUEUES / 2) - 1:0];
wire gmii_col_int[(NUM_QUEUES / 2) - 1:0];
wire [7:0] gmii_rxd_reg[(NUM_QUEUES / 2) - 1:0];
wire gmii_rx_dv_reg[(NUM_QUEUES / 2) - 1:0];
wire gmii_rx_er_reg[(NUM_QUEUES / 2) - 1:0];
wire eth_link_status[(NUM_QUEUES / 2) - 1:0];
wire [1:0] eth_clock_speed[(NUM_QUEUES / 2) - 1:0];
wire eth_duplex_status[(NUM_QUEUES / 2) - 1:0];
wire rx_rgmii_clk_int[(NUM_QUEUES / 2) - 1:0];
wire [`MAC_GRP_REG_ADDR_WIDTH-1:0] mac_grp_reg_addr[3:0];
wire [3:0] mac_grp_reg_req;
wire [3:0] mac_grp_reg_rd_wr_L;
wire [3:0] mac_grp_reg_ack;
wire [`CPCI_NF2_DATA_WIDTH-1:0] mac_grp_reg_wr_data[3:0];
wire [`CPCI_NF2_DATA_WIDTH-1:0] mac_grp_reg_rd_data[3:0];
wire [`CPU_QUEUE_REG_ADDR_WIDTH-1:0] cpu_queue_reg_addr[3:0];
wire [3:0] cpu_queue_reg_req;
wire [3:0] cpu_queue_reg_rd_wr_L;
wire [3:0] cpu_queue_reg_ack;
wire [`CPCI_NF2_DATA_WIDTH-1:0] cpu_queue_reg_wr_data[3:0];
wire [`CPCI_NF2_DATA_WIDTH-1:0] cpu_queue_reg_rd_data[3:0];
wire [3:0] cpu_q_dma_pkt_avail;
wire [3:0] cpu_q_dma_rd;
wire [`DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data [3:0];
wire [`DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl[3:0];
wire [3:0] cpu_q_dma_nearly_full;
wire [3:0] cpu_q_dma_wr;
wire [`DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data[3:0];
wire [`DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl[3:0];
wire [7:0] gmac_tx_data_out[(NUM_QUEUES / 2) - 1:0];
wire gmac_tx_dvld_out[(NUM_QUEUES / 2) - 1:0];
wire gmac_tx_ack_out[(NUM_QUEUES / 2) - 1:0];
wire [7:0] gmac_rx_data_in[(NUM_QUEUES / 2) - 1:0];
wire gmac_rx_dvld_in[(NUM_QUEUES / 2) - 1:0];
wire gmac_rx_frame_error_in[(NUM_QUEUES / 2) - 1:0];
wire end_of_packet[(NUM_QUEUES / 2) - 1:0];
wire start_of_packet[(NUM_QUEUES / 2) - 1:0];
wire tx_rgmii_clk_int;
wire jtag_rd_wr_L;
reg jtag_rd_wr_L_reg;
//reg control_port_waitrequest_reg;
reg [31:0] control_port_readdata_reg;
reg jtag_req_reg;
wire ready_out;
wire out_ack;
//---------------------------------------------
//
// MAC rx and tx queues
//
//---------------------------------------------
// Note: uses register block 8-11
generate
genvar i;
for(i=0; i<NUM_QUEUES/2; i=i+1) begin: mac_groups
nf2_mac_grp #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_HEADER(1),
.PORT_NUMBER(2 * i),
.STAGE_NUMBER(`IO_QUEUE_STAGE_NUM)
)
nf2_mac_grp
(// register interface
.mac_grp_reg_req (core_256kb_0_reg_req[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,1)]),
.mac_grp_reg_ack (core_256kb_0_reg_ack[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,1)]),
.mac_grp_reg_rd_wr_L (core_256kb_0_reg_rd_wr_L[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,1)]),
.mac_grp_reg_addr (core_256kb_0_reg_addr[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,
`BLOCK_SIZE_64k_REG_ADDR_WIDTH)]),
.mac_grp_reg_rd_data (core_256kb_0_reg_rd_data[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,
`CPCI_NF2_DATA_WIDTH)]),
.mac_grp_reg_wr_data (core_256kb_0_reg_wr_data[`WORD(`MAC_GRP_0_BLOCK_ADDR + i,
`CPCI_NF2_DATA_WIDTH)]),
// output to data path interface
.out_wr (in_wr[i*2]),
.out_rdy (in_rdy[i*2]),
.out_data (in_data[i*2]),
.out_ctrl (in_ctrl[i*2]),
// input from data path interface
.in_wr (out_wr[i*2]),
.in_rdy (out_rdy[i*2]),
.in_data (out_data[i*2]),
.in_ctrl (out_ctrl[i*2]),
.gmac_tx_data_out(gmac_tx_data_out[i]),
.gmac_tx_dvld_out(gmac_tx_dvld_out[i]),
.gmac_tx_ack_out(gmac_tx_ack_out[i]),
.end_of_packet(end_of_packet[i]),
.start_of_packet(start_of_packet[i]),
.gmac_rx_data_in(gmac_rx_data_in[i]),
.gmac_rx_dvld_in(gmac_rx_dvld_in[i]),
.gmac_rx_frame_error_in(gmac_rx_frame_error_in[i]),
// misc
.txgmiimiiclk (tx_rgmii_clk_int),
.rxgmiimiiclk (rx_rgmii_clk_int[i]),
.clk (core_clk_int),
.reset (reset)
);
end // block: mac_groups
endgenerate
// //---------------------------------------------
// //
// // JTAG interface
// //
// //---------------------------------------------
//
jtag_bus jtag_bus
(
.jtag_rd_wr_L(jtag_rd_wr_L),
.jtag_addr(control_port_address),
.jtag_wr_data(control_port_writedata),
.jtag_rd_data(control_port_readdata),
.jtag_req(jtag_req),
//.control_port_read_datavalid(control_port_read_datavalid),
.fifo_empty (cpci_reg_fifo_empty ),
.fifo_rd_en (cpci_reg_fifo_rd_en ),
.bus_rd_wr_L (cpci_reg_rd_wr_L),
.bus_addr (cpci_reg_addr),
.bus_wr_data (cpci_reg_wr_data),
.bus_rd_data (cpci_reg_rd_data),
.bus_rd_vld (cpci_reg_rd_vld),
.reset (reset),
.core_clk (core_clk_int)
);
always@(*) begin
if(control_port_read) begin
jtag_rd_wr_L_reg = 1'b1;
end
if(control_port_write) begin
jtag_rd_wr_L_reg = 1'b0;
end
end
always@(control_port_read,control_port_write) begin
if (reset)begin
jtag_req_reg = 1'b0;
end
else begin
if(control_port_read || control_port_write) begin
jtag_req_reg = 1'b1;
end
else
jtag_req_reg = 1'b0;
end
end
assign jtag_rd_wr_L = jtag_rd_wr_L_reg;
assign jtag_req = jtag_req_reg;
// assign control_port_readdata = control_port_readdata_reg;
//-------------------------------------------------
// User data path
//-------------------------------------------------
user_data_path
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_QUEUES),
.NUM_INPUT_QUEUES(NUM_QUEUES)) user_data_path
(.in_data_0 (in_data[0]),
.in_ctrl_0 (in_ctrl[0]),
.in_wr_0 (in_wr[0]),
.in_rdy_0 (in_rdy[0]),
.in_data_1 (in_data[1]),
.in_ctrl_1 (in_ctrl[1]),
.in_wr_1 (in_wr[1]),
.in_rdy_1 (in_rdy[1]),
.in_data_2 (in_data[2]),
.in_ctrl_2 (in_ctrl[2]),
.in_wr_2 (in_wr[2]),
.in_rdy_2 (in_rdy[2]),
.in_data_3 (in_data[3]),
.in_ctrl_3 (in_ctrl[3]),
.in_wr_3 (in_wr[3]),
.in_rdy_3 (in_rdy[3]),
.in_data_4 (in_data[4]),
.in_ctrl_4 (in_ctrl[4]),
.in_wr_4 (in_wr[4]),
.in_rdy_4 (in_rdy[4]),
.in_data_5 (in_data[5]),
.in_ctrl_5 (in_ctrl[5]),
.in_wr_5 (in_wr[5]),
.in_rdy_5 (in_rdy[5]),
.in_data_6 (in_data[6]),
.in_ctrl_6 (in_ctrl[6]),
.in_wr_6 (in_wr[6]),
.in_rdy_6 (in_rdy[6]),
.in_data_7 (in_data[7]),
.in_ctrl_7 (in_ctrl[7]),
.in_wr_7 (in_wr[7]),
.in_rdy_7 (in_rdy[7]),
// interface to MAC, CPU tx queues
.out_data_0 (out_data[0]),
.out_ctrl_0 (out_ctrl[0]),
.out_wr_0 (out_wr[0]),
.out_rdy_0 (out_rdy[0]),
.out_data_1 (out_data[1]),
.out_ctrl_1 (out_ctrl[1]),
.out_wr_1 (out_wr[1]),
.out_rdy_1 (out_rdy[1]),
.out_data_2 (out_data[2]),
.out_ctrl_2 (out_ctrl[2]),
.out_wr_2 (out_wr[2]),
.out_rdy_2 (out_rdy[2]),
.out_data_3 (out_data[3]),
.out_ctrl_3 (out_ctrl[3]),
.out_wr_3 (out_wr[3]),
.out_rdy_3 (out_rdy[3]),
.out_data_4 (out_data[4]),
.out_ctrl_4 (out_ctrl[4]),
.out_wr_4 (out_wr[4]),
.out_rdy_4 (out_rdy[4]),
.out_data_5 (out_data[5]),
.out_ctrl_5 (out_ctrl[5]),
.out_wr_5 (out_wr[5]),
.out_rdy_5 (out_rdy[5]),
.out_data_6 (out_data[6]),
.out_ctrl_6 (out_ctrl[6]),
.out_wr_6 (out_wr[6]),
.out_rdy_6 (out_rdy[6]),
.out_data_7 (out_data[7]),
.out_ctrl_7 (out_ctrl[7]),
.out_wr_7 (out_wr[7]),
.out_rdy_7 (out_rdy[7]),
// interface to SRAM
.wr_0_addr (wr_0_addr),
.wr_0_req (wr_0_req),
.wr_0_ack (wr_0_ack),
.wr_0_data (wr_0_data),
.rd_0_ack (rd_0_ack),
.rd_0_data (rd_0_data),
.rd_0_vld (rd_0_vld),
.rd_0_addr (rd_0_addr),
.rd_0_req (rd_0_req),
// interface to DRAM
/* TBD */
// register interface
.reg_req (udp_reg_req),
.reg_ack (udp_reg_ack),
.reg_rd_wr_L (udp_reg_rd_wr_L),
.reg_addr (udp_reg_addr),
.reg_rd_data (udp_reg_rd_data),
.reg_wr_data (udp_reg_wr_data),
// misc
.ready_out(ready_out),
.reset (reset),
.clk (core_clk_int));
sram sram_inst
(
.clock ( core_clk_int ),
.data ( wr_0_data ),
.rdaddress ( rd_0_addr ),
.rden ( rd_0_req ),
.wraddress ( wr_0_addr ),
.wren ( wr_0_req ),
.q ( rd_0_data )
);
parameter IDLE_WR_ACK =0, WRITE_WR_ACK = 1;
parameter IDLE_RD_ACK = 0, READ_RD_ACK = 1;
reg wr_0_ack_next,rd_0_ack_next,rd_0_vld_next;
reg wr_0_ack_reg,rd_0_ack_reg,rd_0_vld_reg;
reg [1:0] state_WR_ACK,state_WR_ACK_next;
reg [1:0] state_RD_ACK,state_RD_ACK_next;
always@(posedge core_clk_int) begin
if (reset) begin
wr_0_ack_reg <= 0;
state_WR_ACK <= IDLE_WR_ACK;
end
else begin
wr_0_ack_reg <= wr_0_ack_next;
state_WR_ACK <= state_WR_ACK_next;
end
end
always@(posedge core_clk_int) begin
if (reset) begin
rd_0_ack_reg <= 0;
rd_0_vld_reg <= 0;
state_RD_ACK <= IDLE_RD_ACK;
end
else begin
rd_0_ack_reg <= rd_0_ack_next;
rd_0_vld_reg <= rd_0_vld_next;
state_RD_ACK <= state_RD_ACK_next;
end
end
always@(*) begin
state_WR_ACK_next = state_WR_ACK;
wr_0_ack_next = wr_0_ack_reg;
case(state_WR_ACK)
IDLE_WR_ACK: begin
wr_0_ack_next <= 1'b0;
if(wr_0_req)begin
state_WR_ACK_next = WRITE_WR_ACK;
end
end
WRITE_WR_ACK: begin
wr_0_ack_next <= 1'b1;
if(rd_0_req)begin
state_WR_ACK_next = WRITE_WR_ACK;
end
else
state_WR_ACK_next = IDLE_WR_ACK;
end
default: begin
state_WR_ACK_next = IDLE_WR_ACK;
end
endcase
end
always@(*) begin
state_RD_ACK_next = state_RD_ACK;
rd_0_ack_next = rd_0_ack_reg;
rd_0_vld_next = rd_0_vld_reg;
case(state_RD_ACK)
IDLE_RD_ACK: begin
rd_0_ack_next <= 1'b0;
rd_0_vld_next <= 1'b0;
if(rd_0_req)begin
state_RD_ACK_next = READ_RD_ACK;
end
end
READ_RD_ACK: begin
rd_0_ack_next <= 1'b1;
rd_0_vld_next <= 1'b1;
if(rd_0_req)begin
state_RD_ACK_next = READ_RD_ACK;
end
else
state_RD_ACK_next = IDLE_RD_ACK;
end
default: begin
state_RD_ACK_next = IDLE_RD_ACK;
end
endcase
end
assign rd_0_ack = rd_0_ack_reg;
assign wr_0_ack = wr_0_ack_reg;
assign rd_0_vld = rd_0_vld_reg;
//-------------------------------------------------
//
// register address decoder, register bus mux and demux
//
//-----------------------------------------------
parameter IDLE_STATE_WAIT = 2'b00,WRITE_STATE_WAIT = 2'b01,WRITE_STATE_WAIT2 =2'b10,READ_STATE_WAIT =2'b11;
reg [1:0] state_wait,state_wait_next;
reg control_port_wait_reg,control_port_wait_reg_next;
reg rxm_port_readdata_valid_reg,rxm_port_readdata_valid_reg_next;
reg [31:0] rxm_port_readdata_reg;
reg [31:0] rxm_port_readdata_reg_next;
always@(posedge core_clk_int) begin
if (reset) begin
state_wait <= IDLE_STATE_WAIT;
control_port_wait_reg <= 1'b0;
rxm_port_readdata_valid_reg <= 1'b0;
rxm_port_readdata_reg <= 32'b0;
end
else begin
state_wait <= state_wait_next;
control_port_wait_reg <= control_port_wait_reg_next;
rxm_port_readdata_valid_reg <= rxm_port_readdata_valid_reg_next;
rxm_port_readdata_reg <= rxm_port_readdata_reg_next;
end
end
always@(*)begin
state_wait_next = state_wait;
control_port_wait_reg_next = control_port_wait_reg;
rxm_port_readdata_valid_reg_next = rxm_port_readdata_valid_reg;
rxm_port_readdata_reg_next = rxm_port_readdata_reg;
case (state_wait)
IDLE_STATE_WAIT: begin
rxm_port_readdata_valid_reg_next = 1'b0;
rxm_port_readdata_reg_next = 32'b0;
if(control_port_write) begin
control_port_wait_reg_next = 1'b1;
state_wait_next = WRITE_STATE_WAIT;
end
if(control_port_read) begin
control_port_wait_reg_next = 1'b1;
state_wait_next = READ_STATE_WAIT;
end
end
WRITE_STATE_WAIT: begin
if(out_ack) begin
control_port_wait_reg_next = 1'b1;
state_wait_next = WRITE_STATE_WAIT2;
end
end
WRITE_STATE_WAIT2: begin
if(!ready_out) begin
control_port_wait_reg_next = 1'b1;
end
else begin
control_port_wait_reg_next = 1'b0;
state_wait_next = IDLE_STATE_WAIT;
end
end
READ_STATE_WAIT: begin
if(cpci_reg_rd_vld) begin
control_port_wait_reg_next = 1'b0;
state_wait_next = IDLE_STATE_WAIT;
rxm_port_readdata_valid_reg_next = 1'b1;
rxm_port_readdata_reg_next = control_port_readdata;
end
end
endcase
end
assign control_port_waitrequest = control_port_wait_reg_next;
assign control_port_read_datavalid = rxm_port_readdata_valid_reg;
assign rxm_port_readdata = rxm_port_readdata_reg;
nf2_reg_grp nf2_reg_grp_u
(// interface to cpci_bus
.fifo_empty (cpci_reg_fifo_empty),
.fifo_rd_en (cpci_reg_fifo_rd_en),
.bus_rd_wr_L (cpci_reg_rd_wr_L),
.bus_addr (cpci_reg_addr),
.bus_wr_data (cpci_reg_wr_data),
.bus_rd_data (cpci_reg_rd_data),
.bus_rd_vld (cpci_reg_rd_vld),
.out_ack (out_ack),
// interface to core
.core_reg_req (core_reg_req),
.core_reg_rd_wr_L (core_reg_rd_wr_L),
.core_reg_addr (core_reg_addr),
.core_reg_wr_data (core_reg_wr_data),
.core_reg_rd_data (core_reg_rd_data),
.core_reg_ack (core_reg_ack),
// interface to SRAM
.sram_reg_req (sram_reg_req),
.sram_reg_rd_wr_L (sram_reg_rd_wr_L),
.sram_reg_addr (sram_reg_addr),
.sram_reg_wr_data (sram_reg_wr_data),
.sram_reg_rd_data (sram_reg_rd_data),
.sram_reg_ack (sram_reg_ack),
// interface to user data path
.udp_reg_req (udp_reg_req),
.udp_reg_rd_wr_L (udp_reg_rd_wr_L),
.udp_reg_addr (udp_reg_addr),
.udp_reg_wr_data (udp_reg_wr_data),
.udp_reg_rd_data (udp_reg_rd_data),
.udp_reg_ack (udp_reg_ack),
// interface to DRAM
.dram_reg_req (dram_reg_req),
.dram_reg_rd_wr_L (dram_reg_rd_wr_L),
.dram_reg_addr (dram_reg_addr),
.dram_reg_wr_data (dram_reg_wr_data),
.dram_reg_rd_data (dram_reg_rd_data),
.dram_reg_ack (dram_reg_ack),
// misc
.clk (core_clk_int),
.reset (reset)
);
reg_grp #(
.REG_ADDR_BITS(`CORE_REG_ADDR_WIDTH),
.NUM_OUTPUTS(4)
) core_4mb_reg_grp
(
// Upstream register interface
.reg_req (core_reg_req),
.reg_rd_wr_L (core_reg_rd_wr_L),
.reg_addr (core_reg_addr),
.reg_wr_data (core_reg_wr_data),
.reg_ack (core_reg_ack),
.reg_rd_data (core_reg_rd_data),
// Downstream register interface
.local_reg_req (core_4mb_reg_req),
.local_reg_rd_wr_L (core_4mb_reg_rd_wr_L),
.local_reg_addr (core_4mb_reg_addr),
.local_reg_wr_data (core_4mb_reg_wr_data),
.local_reg_ack (core_4mb_reg_ack),
.local_reg_rd_data (core_4mb_reg_rd_data),
//-- misc
.clk (core_clk_int),
.reset (reset)
);
reg_grp #(
.REG_ADDR_BITS(`CORE_REG_ADDR_WIDTH - 2),
.NUM_OUTPUTS(16)
) core_256kb_0_reg_grp
(
// Upstream register interface
.reg_req (core_4mb_reg_req[`WORD(1,1)]),
.reg_ack (core_4mb_reg_ack[`WORD(1,1)]),
.reg_rd_wr_L (core_4mb_reg_rd_wr_L[`WORD(1,1)]),
.reg_addr (core_4mb_reg_addr[`WORD(1, `BLOCK_SIZE_1M_REG_ADDR_WIDTH)]),
.reg_rd_data (core_4mb_reg_rd_data[`WORD(1, `CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_4mb_reg_wr_data[`WORD(1, `CPCI_NF2_DATA_WIDTH)]),
// Downstream register interface
.local_reg_req (core_256kb_0_reg_req),
.local_reg_rd_wr_L (core_256kb_0_reg_rd_wr_L),
.local_reg_addr (core_256kb_0_reg_addr),
.local_reg_wr_data (core_256kb_0_reg_wr_data),
.local_reg_ack (core_256kb_0_reg_ack),
.local_reg_rd_data (core_256kb_0_reg_rd_data),
//-- misc
.clk (core_clk_int),
.reset (reset)
);
//--------------------------------------------------
//
// --- Device ID register
//
// Provides a set of registers to uniquely identify the design
// - Design/Device ID
// - Revision
// - Description
//
//--------------------------------------------------
device_id_reg
`ifdef DEVICE_ID
#(
.DEVICE_ID(`DEVICE_ID),
.REVISION(`DEVICE_REVISION),
.DEVICE_STR(`DEVICE_STR)
)
`endif
device_id_reg (
// Register interface signals
.reg_req (core_256kb_0_reg_req[`WORD(`DEV_ID_BLOCK_ADDR,1)]),
.reg_ack (core_256kb_0_reg_ack[`WORD(`DEV_ID_BLOCK_ADDR,1)]),
.reg_rd_wr_L (core_256kb_0_reg_rd_wr_L[`WORD(`DEV_ID_BLOCK_ADDR,1)]),
.reg_addr (core_256kb_0_reg_addr[`WORD(`DEV_ID_BLOCK_ADDR,`DEV_ID_REG_ADDR_WIDTH)]),
.reg_rd_data (core_256kb_0_reg_rd_data[`WORD(`DEV_ID_BLOCK_ADDR,`CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_256kb_0_reg_wr_data[`WORD(`DEV_ID_BLOCK_ADDR,`CPCI_NF2_DATA_WIDTH)]),
//
.clk (core_clk_int),
.reset (reset)
);
// synthesis attribute keep_hierarchy of nf2_dma is false;
//--------------------------------------------------
//
// --- Unused register signals
//
//--------------------------------------------------
unused_reg #(
.REG_ADDR_WIDTH(`BLOCK_SIZE_1M_REG_ADDR_WIDTH)
) unused_reg_core_4mb_0 (
// Register interface signals
.reg_req (core_4mb_reg_req[`WORD(0,1)]),
.reg_ack (core_4mb_reg_ack[`WORD(0,1)]),
.reg_rd_wr_L (core_4mb_reg_rd_wr_L[`WORD(0,1)]),
.reg_addr (core_4mb_reg_addr[`WORD(0, `BLOCK_SIZE_1M_REG_ADDR_WIDTH)]),
.reg_rd_data (core_4mb_reg_rd_data[`WORD(0, `CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_4mb_reg_wr_data[`WORD(0, `CPCI_NF2_DATA_WIDTH)]),
//
.clk (core_clk_int),
.reset (reset)
);
unused_reg #(
.REG_ADDR_WIDTH(`BLOCK_SIZE_1M_REG_ADDR_WIDTH)
) unused_reg_core_4mb_2 (
// Register interface signals
.reg_req (core_4mb_reg_req[`WORD(2,1)]),
.reg_ack (core_4mb_reg_ack[`WORD(2,1)]),
.reg_rd_wr_L (core_4mb_reg_rd_wr_L[`WORD(2,1)]),
.reg_addr (core_4mb_reg_addr[`WORD(2, `BLOCK_SIZE_1M_REG_ADDR_WIDTH)]),
.reg_rd_data (core_4mb_reg_rd_data[`WORD(2, `CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_4mb_reg_wr_data[`WORD(2, `CPCI_NF2_DATA_WIDTH)]),
//
.clk (core_clk_int),
.reset (reset)
);
unused_reg #(
.REG_ADDR_WIDTH(`BLOCK_SIZE_1M_REG_ADDR_WIDTH)
) unused_reg_core_4mb_3 (
// Register interface signals
.reg_req (core_4mb_reg_req[`WORD(3,1)]),
.reg_ack (core_4mb_reg_ack[`WORD(3,1)]),
.reg_rd_wr_L (core_4mb_reg_rd_wr_L[`WORD(3,1)]),
.reg_addr (core_4mb_reg_addr[`WORD(3, `BLOCK_SIZE_1M_REG_ADDR_WIDTH)]),
.reg_rd_data (core_4mb_reg_rd_data[`WORD(3, `CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_4mb_reg_wr_data[`WORD(3, `CPCI_NF2_DATA_WIDTH)]),
//
.clk (core_clk_int),
.reset (reset)
);
generate
//genvar i;
for (i = 0; i < 16; i = i + 1) begin: unused_reg_core_256kb_0
if (!(i >= `MAC_GRP_0_BLOCK_ADDR &&
i < `MAC_GRP_0_BLOCK_ADDR + NUM_QUEUES/2) &&
!(i >= `CPU_QUEUE_0_BLOCK_ADDR &&
i < `CPU_QUEUE_0_BLOCK_ADDR + NUM_QUEUES/2) &&
i != `DEV_ID_BLOCK_ADDR &&
i != `DMA_BLOCK_ADDR &&
i != `MDIO_BLOCK_ADDR)
unused_reg #(
.REG_ADDR_WIDTH(`BLOCK_SIZE_64k_REG_ADDR_WIDTH)
) unused_reg_core_256kb_0_x (
// Register interface signals
.reg_req (core_256kb_0_reg_req[`WORD(i,1)]),
.reg_ack (core_256kb_0_reg_ack[`WORD(i,1)]),
.reg_rd_wr_L (core_256kb_0_reg_rd_wr_L[`WORD(i,1)]),
.reg_addr (core_256kb_0_reg_addr[`WORD(i, `BLOCK_SIZE_64k_REG_ADDR_WIDTH)]),
.reg_rd_data (core_256kb_0_reg_rd_data[`WORD(i, `CPCI_NF2_DATA_WIDTH)]),
.reg_wr_data (core_256kb_0_reg_wr_data[`WORD(i, `CPCI_NF2_DATA_WIDTH)]),
//
.clk (core_clk_int),
.reset (reset)
);
end
endgenerate
assign tx_rgmii_clk_int = core_clk_int;
assign rx_rgmii_0_clk_int = core_clk_int;
assign rx_rgmii_1_clk_int = core_clk_int;
assign rx_rgmii_2_clk_int = core_clk_int;
assign rx_rgmii_3_clk_int = core_clk_int;
//--------------------------------------------------
//
// --- MAC signal encapsulation/decapsulation
//
//--------------------------------------------------
// --- Mac 0
assign gmac_tx_data_0_out = gmac_tx_data_out[0];
assign gmac_tx_dvld_0_out = gmac_tx_dvld_out[0];
assign gmac_tx_ack_out[0] = gmac_tx_ack_0_out;
assign end_of_packet_0_out = end_of_packet[0];
assign start_of_packet_0_out = start_of_packet[0];
assign gmac_rx_data_in[0] = gmac_rx_data_0_in;
assign gmac_rx_dvld_in[0] = gmac_rx_dvld_0_in;
assign gmac_rx_frame_error_in[0] = gmac_rx_frame_error_0_in;
assign gmac_tx_data_1_out = gmac_tx_data_out[1];
assign gmac_tx_dvld_1_out = gmac_tx_dvld_out[1];
assign gmac_tx_ack_out[1] = gmac_tx_ack_1_out;
assign end_of_packet_1_out = end_of_packet[1];
assign start_of_packet_1_out = start_of_packet[1];
assign gmac_rx_data_in[1] = gmac_rx_data_1_in;
assign gmac_rx_dvld_in[1] = gmac_rx_dvld_1_in;
assign gmac_rx_frame_error_in[1] = gmac_rx_frame_error_1_in;
assign gmac_tx_data_2_out = gmac_tx_data_out[2];
assign gmac_tx_dvld_2_out = gmac_tx_dvld_out[2];
assign gmac_tx_ack_out[2] = gmac_tx_ack_2_out;
assign end_of_packet_2_out = end_of_packet[2];
assign start_of_packet_2_out = start_of_packet[2];
assign gmac_rx_data_in[2] = gmac_rx_data_2_in;
assign gmac_rx_dvld_in[2] = gmac_rx_dvld_2_in;
assign gmac_rx_frame_error_in[2] = gmac_rx_frame_error_2_in;
assign gmac_tx_data_3_out = gmac_tx_data_out[3];
assign gmac_tx_dvld_3_out = gmac_tx_dvld_out[3];
assign gmac_tx_ack_out[3] = gmac_tx_ack_3_out;
assign end_of_packet_3_out = end_of_packet[3];
assign start_of_packet_3_out = start_of_packet[3];
assign gmac_rx_data_in[3] = gmac_rx_data_3_in;
assign gmac_rx_dvld_in[3] = gmac_rx_dvld_3_in;
assign gmac_rx_frame_error_in[3] = gmac_rx_frame_error_3_in;
assign rx_rgmii_clk_int[0] = rx_rgmii_0_clk_int;
assign rx_rgmii_clk_int[1] = rx_rgmii_1_clk_int;
assign rx_rgmii_clk_int[2] = rx_rgmii_2_clk_int;
assign rx_rgmii_clk_int[3] = rx_rgmii_3_clk_int;
endmodule // nf2_core
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:31 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/ip_design_axi_gpio_1_0_sim_netlist.v
// Design : ip_design_axi_gpio_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_axi_gpio_1_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.3" *)
(* NotValidForBitStream *)
module ip_design_axi_gpio_1_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [4:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [7:0]gpio2_io_i;
wire [7:0]gpio2_io_i;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "8" *)
(* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
ip_design_axi_gpio_1_0_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[7:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[7:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[4:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[4:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module ip_design_axi_gpio_1_0_GPIO_Core
(reg3,
reg1,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ,
bus2ip_rnw_i_reg,
\Dual.gpio2_Data_In_reg[7]_0 ,
s_axi_aclk,
\Dual.gpio2_Data_In_reg[6]_0 ,
\Dual.gpio2_Data_In_reg[5]_0 ,
\Dual.gpio2_Data_In_reg[4]_0 ,
\Dual.gpio2_Data_In_reg[3]_0 ,
\Dual.gpio2_Data_In_reg[2]_0 ,
\Dual.gpio2_Data_In_reg[1]_0 ,
\Dual.gpio2_Data_In_reg[0]_0 ,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
D,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1,
bus2ip_rnw_i_reg_2);
output [7:0]reg3;
output [4:0]reg1;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
output [7:0]Q;
output [4:0]\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
input bus2ip_rnw_i_reg;
input \Dual.gpio2_Data_In_reg[7]_0 ;
input s_axi_aclk;
input \Dual.gpio2_Data_In_reg[6]_0 ;
input \Dual.gpio2_Data_In_reg[5]_0 ;
input \Dual.gpio2_Data_In_reg[4]_0 ;
input \Dual.gpio2_Data_In_reg[3]_0 ;
input \Dual.gpio2_Data_In_reg[2]_0 ;
input \Dual.gpio2_Data_In_reg[1]_0 ;
input \Dual.gpio2_Data_In_reg[0]_0 ;
input [0:4]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [4:0]gpio_io_i;
input [7:0]gpio2_io_i;
input [0:0]E;
input [7:0]D;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
input [0:0]bus2ip_rnw_i_reg_2;
wire [7:0]D;
wire [4:0]\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
wire \Dual.gpio2_Data_In_reg[0]_0 ;
wire \Dual.gpio2_Data_In_reg[1]_0 ;
wire \Dual.gpio2_Data_In_reg[2]_0 ;
wire \Dual.gpio2_Data_In_reg[3]_0 ;
wire \Dual.gpio2_Data_In_reg[4]_0 ;
wire \Dual.gpio2_Data_In_reg[5]_0 ;
wire \Dual.gpio2_Data_In_reg[6]_0 ;
wire \Dual.gpio2_Data_In_reg[7]_0 ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]Q;
wire [0:4]Read_Reg_In;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [0:0]bus2ip_rnw_i_reg_2;
wire [7:0]gpio2_io_i;
wire [0:7]gpio2_io_i_d2;
wire [7:0]gpio2_io_o;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_i;
wire [0:4]gpio_io_i_d2;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(reg1[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(reg1[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(reg1[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(reg1[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[4]),
.Q(reg1[0]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[0]_0 ),
.Q(reg3[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[1]_0 ),
.Q(reg3[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[2]_0 ),
.Q(reg3[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[3]_0 ),
.Q(reg3[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[4]_0 ),
.Q(reg3[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[5]_0 ),
.Q(reg3[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[6]_0 ),
.Q(reg3[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[7]_0 ),
.Q(reg3[0]),
.R(bus2ip_rnw_i_reg));
ip_design_axi_gpio_1_0_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4]}));
ip_design_axi_gpio_1_0_cdc_sync__parameterized0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3],gpio2_io_i_d2[4],gpio2_io_i_d2[5],gpio2_io_i_d2[6],gpio2_io_i_d2[7]}));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[7]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[6]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[5]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[4]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[4]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[5]),
.Q(Q[2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[6]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[7]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[7]),
.Q(gpio2_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[6]),
.Q(gpio2_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[5]),
.Q(gpio2_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[4]),
.Q(gpio2_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[7]),
.Q(gpio2_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[6]),
.Q(gpio2_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[5]),
.Q(gpio2_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[4]),
.Q(gpio2_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [4]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[7]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[6]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[5]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[4]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[3]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module ip_design_axi_gpio_1_0_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
\ip2bus_data_i_D1_reg[0] ,
Q,
s_axi_aclk,
s_axi_aresetn,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
gpio_xferAck_Reg,
GPIO_xferAck_i,
reg3,
reg1);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input Q;
input s_axi_aclk;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [7:0]s_axi_wdata;
input [2:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]reg3;
input [4:0]reg1;
wire Bus_RNW_reg;
wire Bus_RNW_reg_i_1_n_0;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire gpio_xferAck_Reg;
wire \ip2bus_data_i_D1[27]_i_2_n_0 ;
wire \ip2bus_data_i_D1[27]_i_3_n_0 ;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(Bus_RNW_reg),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00100000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [1]),
.O(\Dual.gpio2_Data_Out_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(\Dual.gpio2_OE_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000010))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00100000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(\Dual.gpio_OE_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arready),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(Q),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00040400))
\ip2bus_data_i_D1[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [8]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[24]_i_1
(.I0(reg3[7]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [7]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[25]_i_1
(.I0(reg3[6]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [6]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[26]_i_1
(.I0(reg3[5]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [5]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[27]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[4]),
.I3(reg3[4]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [4]));
LUT5 #(
.INIT(32'h00020000))
\ip2bus_data_i_D1[27]_i_2
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\ip2bus_data_i_D1[27]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00020000))
\ip2bus_data_i_D1[27]_i_3
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1[27]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[28]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[3]),
.I3(reg3[3]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [3]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[29]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[2]),
.I3(reg3[2]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [2]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[30]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[1]),
.I3(reg3[1]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [1]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[31]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[0]),
.I3(reg3[0]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "1" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "8" *) (* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module ip_design_axi_gpio_1_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [4:0]gpio_io_i;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
input [7:0]gpio2_io_i;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_24;
wire AXI_LITE_IPIF_I_n_25;
wire AXI_LITE_IPIF_I_n_26;
wire AXI_LITE_IPIF_I_n_27;
wire AXI_LITE_IPIF_I_n_28;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_30;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire GPIO_xferAck_i;
wire [0:4]Read_Reg_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:7]gpio2_Data_In;
wire [7:0]gpio2_io_i;
wire [7:0]gpio2_io_o;
wire [7:0]gpio2_io_t;
wire [0:4]gpio_Data_In;
wire gpio_core_1_n_16;
wire [4:0]gpio_io_i;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [0:31]ip2bus_data;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [4:0]p_0_out;
wire [27:31]reg1;
wire [24:31]reg3;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
ip_design_axi_gpio_1_0_axi_lite_ipif AXI_LITE_IPIF_I
(.D({p_0_out,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14}),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (AXI_LITE_IPIF_I_n_24),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (AXI_LITE_IPIF_I_n_32),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] (AXI_LITE_IPIF_I_n_31),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] (AXI_LITE_IPIF_I_n_30),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] (AXI_LITE_IPIF_I_n_29),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] (AXI_LITE_IPIF_I_n_28),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] (AXI_LITE_IPIF_I_n_27),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] (AXI_LITE_IPIF_I_n_26),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] (AXI_LITE_IPIF_I_n_25),
.\Dual.gpio2_Data_In_reg[0] ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_17),
.\Dual.gpio2_OE_reg[0] (AXI_LITE_IPIF_I_n_18),
.\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_16),
.E(AXI_LITE_IPIF_I_n_15),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.Read_Reg_In(Read_Reg_In),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] ({ip2bus_data[0],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1({reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [7:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[7:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
ip_design_axi_gpio_1_0_GPIO_Core gpio_core_1
(.D({p_0_out,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14}),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.\Dual.gpio2_Data_In_reg[0]_0 (AXI_LITE_IPIF_I_n_32),
.\Dual.gpio2_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_31),
.\Dual.gpio2_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_30),
.\Dual.gpio2_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_29),
.\Dual.gpio2_Data_In_reg[4]_0 (AXI_LITE_IPIF_I_n_28),
.\Dual.gpio2_Data_In_reg[5]_0 (AXI_LITE_IPIF_I_n_27),
.\Dual.gpio2_Data_In_reg[6]_0 (AXI_LITE_IPIF_I_n_26),
.\Dual.gpio2_Data_In_reg[7]_0 (AXI_LITE_IPIF_I_n_25),
.E(AXI_LITE_IPIF_I_n_15),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.Read_Reg_In(Read_Reg_In),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_24),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_16),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_17),
.bus2ip_rnw_i_reg_2(AXI_LITE_IPIF_I_n_18),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_16),
.reg1({reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_16),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module ip_design_axi_gpio_1_0_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
s_axi_rvalid,
s_axi_bvalid,
bus2ip_cs,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
Read_Reg_In,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
s_axi_rdata,
\ip2bus_data_i_D1_reg[0] ,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
Q,
gpio_io_t,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\Dual.gpio2_Data_In_reg[0] ,
gpio2_io_t,
\ip2bus_data_i_D1_reg[0]_0 ,
reg3,
reg1);
output bus2ip_reset;
output bus2ip_rnw;
output s_axi_rvalid;
output s_axi_bvalid;
output bus2ip_cs;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:4]Read_Reg_In;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
output [8:0]s_axi_rdata;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [7:0]s_axi_wdata;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input [4:0]Q;
input [4:0]gpio_io_t;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]\Dual.gpio2_Data_In_reg[0] ;
input [7:0]gpio2_io_t;
input [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
input [7:0]reg3;
input [4:0]reg1;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
wire [7:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [4:0]Q;
wire [0:4]Read_Reg_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [8:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
ip_design_axi_gpio_1_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (bus2ip_rnw),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 (\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ),
.\Dual.gpio2_Data_In_reg[0] (\Dual.gpio2_Data_In_reg[0] ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg_In(Read_Reg_In),
.SR(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1(reg1),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module ip_design_axi_gpio_1_0_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [4:0]scndry_vect_out;
input [4:0]gpio_io_i;
input s_axi_aclk;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire [4:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module ip_design_axi_gpio_1_0_cdc_sync__parameterized0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio2_io_i;
input s_axi_aclk;
wire [7:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module ip_design_axi_gpio_1_0_slave_attachment
(SR,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
s_axi_rvalid,
s_axi_bvalid,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
Read_Reg_In,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
s_axi_rdata,
\ip2bus_data_i_D1_reg[0] ,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
Q,
gpio_io_t,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\Dual.gpio2_Data_In_reg[0] ,
gpio2_io_t,
\ip2bus_data_i_D1_reg[0]_0 ,
reg3,
reg1);
output SR;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output s_axi_rvalid;
output s_axi_bvalid;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:4]Read_Reg_In;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
output [8:0]s_axi_rdata;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [7:0]s_axi_wdata;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input [4:0]Q;
input [4:0]gpio_io_t;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]\Dual.gpio2_Data_In_reg[0] ;
input [7:0]gpio2_io_t;
input [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
input [7:0]reg3;
input [4:0]reg1;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
wire [7:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [4:0]Q;
wire [0:4]Read_Reg_In;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire clear;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [3:0]plusOp;
wire [4:0]reg1;
wire [7:0]reg3;
wire rst_i_1_n_0;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [8:0]s_axi_rdata;
wire \s_axi_rdata_i[31]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_3_n_0 ;
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1[27]_i_1
(.I0(Q[4]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[4]),
.O(Read_Reg_In[0]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1[28]_i_1
(.I0(Q[3]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[3]),
.O(Read_Reg_In[1]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1[29]_i_1
(.I0(Q[2]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[2]),
.O(Read_Reg_In[2]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1[30]_i_1
(.I0(Q[1]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[1]),
.O(Read_Reg_In[3]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1[31]_i_1
(.I0(Q[0]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[0]),
.O(Read_Reg_In[4]));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [7]),
.I1(gpio2_io_t[7]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [6]),
.I1(gpio2_io_t[6]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [5]),
.I1(gpio2_io_t[5]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [4]),
.I1(gpio2_io_t[4]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [3]),
.I1(gpio2_io_t[3]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [2]),
.I1(gpio2_io_t[2]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [1]),
.I1(gpio2_io_t[1]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_2
(.I0(\Dual.gpio2_Data_In_reg[0] [0]),
.I1(gpio2_io_t[0]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
ip_design_axi_gpio_1_0_address_decoder I_DECODER
(.D(D),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(start2),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.reg1(reg1),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready));
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(s_axi_arvalid),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(rst_i_1_n_0));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rst_i_1_n_0),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [8]),
.Q(s_axi_rdata[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(\state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(\state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation "[ ]" := nil (format "[ ]") : list_scope.
Notation "[ x ]" := (cons x nil) : list_scope.
Notation "[ x ; y ; .. ; z ]" := (cons x (cons y .. (cons z nil) ..)) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Generic facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse : core.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H as H H0.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H as H H0; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes.
Hint Immediate app_eq_nil: datatypes.
Hint Resolve app_eq_unit app_inj_tail: datatypes.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. now injection H as ->.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(******************************************)
(** ** Counting occurrences of an element *)
(******************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
clear Hfinjective.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma ext_in_map :
forall (A B : Type)(f g:A->B) l, map f l = map g l -> forall a, In a l -> f a = g a.
Proof. induction l; intros [=] ? []; subst; auto. Qed.
Arguments ext_in_map [A B f g l].
Lemma map_ext_in_iff :
forall (A B : Type)(f g:A->B) l, map f l = map g l <-> forall a, In a l -> f a = g a.
Proof. split; [apply ext_in_map | apply map_ext_in]. Qed.
Arguments map_ext_in_iff [A B f g l].
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l'].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl : core.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl : core.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl : core.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl : core.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr : core.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons : core.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app : core.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn_comm : forall m n l,
firstn m (skipn n l) = skipn n (firstn (n + m) l).
Proof. now intros m; induction n; intros []; simpl; destruct m. Qed.
Lemma skipn_firstn_comm : forall m n l,
skipn m (firstn n l) = firstn (n - m) (skipn m l).
Proof. now induction m; intros [] []; simpl; rewrite ?firstn_nil. Qed.
Lemma skipn_O : forall l, skipn 0 l = l.
Proof. reflexivity. Qed.
Lemma skipn_nil : forall n, skipn n ([] : list A) = [].
Proof. now intros []. Qed.
Lemma skipn_cons n a l: skipn (S n) (a::l) = skipn n l.
Proof. reflexivity. Qed.
Lemma skipn_none : forall l, skipn (length l) l = [].
Proof. now induction l. Qed.
Lemma skipn_all2 n: forall l, length l <= n -> skipn n l = [].
Proof.
intros l L%Nat.sub_0_le; rewrite <-(firstn_all l) at 1.
now rewrite skipn_firstn_comm, L.
Qed.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma skipn_length n :
forall l, length (skipn n l) = length l - n.
Proof.
induction n.
- intros l; simpl; rewrite Nat.sub_0_r; reflexivity.
- destruct l; simpl; auto.
Qed.
Lemma skipn_all l: skipn (length l) l = nil.
Proof. now induction l. Qed.
Lemma skipn_app n : forall l1 l2,
skipn n (l1 ++ l2) = (skipn n l1) ++ (skipn (n - length l1) l2).
Proof. induction n; auto; intros [|]; simpl; auto. Qed.
Lemma firstn_skipn_rev: forall x l,
firstn x l = rev (skipn (length l - x) (rev l)).
Proof.
intros x l; rewrite <-(firstn_skipn x l) at 3.
rewrite rev_app_distr, skipn_app, rev_app_distr, rev_length,
skipn_length, Nat.sub_diag; simpl; rewrite rev_involutive.
rewrite <-app_nil_r at 1; f_equal; symmetry; apply length_zero_iff_nil.
repeat rewrite rev_length, skipn_length; apply Nat.sub_diag.
Qed.
Lemma firstn_rev: forall x l,
firstn x (rev l) = rev (skipn (length l - x) l).
Proof.
now intros x l; rewrite firstn_skipn_rev, rev_involutive, rev_length.
Qed.
Lemma skipn_rev: forall x l,
skipn x (rev l) = rev (firstn (length l - x) l).
Proof.
intros x l; rewrite firstn_skipn_rev, rev_involutive, <-rev_length.
destruct (Nat.le_ge_cases (length (rev l)) x) as [L | L].
- rewrite skipn_all2; [apply Nat.sub_0_le in L | trivial].
now rewrite L, Nat.sub_0_r, skipn_none.
- replace (length (rev l) - (length (rev l) - x))
with (length (rev l) + x - length (rev l)).
rewrite minus_plus. reflexivity.
rewrite <- (Nat.sub_add _ _ L) at 2.
now rewrite <-!(Nat.add_comm x), <-minus_plus_simpl_l_reverse.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
Lemma seq_app : forall len1 len2 start,
seq start (len1 + len2) = seq start len1 ++ seq (start + len1) len2.
Proof.
induction len1 as [|len1' IHlen]; intros; simpl in *.
- now rewrite Nat.add_0_r.
- now rewrite Nat.add_succ_r, IHlen.
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists : core.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. abstract now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. abstract now inversion 1.
Defined.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall : core.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. abstract now inversion 1.
+ right. abstract now inversion 1.
Defined.
End One_predicate.
Theorem Forall_inv_tail
: forall (P : A -> Prop) (x0 : A) (xs : list A), Forall P (x0 :: xs) -> Forall P xs.
Proof.
intros P x0 xs H.
apply Forall_forall with (l := xs).
assert (H0 : forall x : A, In x (x0 :: xs) -> P x).
apply Forall_forall with (P := P) (l := x0 :: xs).
exact H.
assert (H1 : forall (x : A) (H2 : In x xs), P x).
intros x H2.
apply (H0 x).
right.
exact H2.
intros x H2.
apply (H1 x H2).
Qed.
Theorem Exists_impl
: forall (P Q : A -> Prop), (forall x : A, P x -> Q x) -> forall xs : list A, Exists P xs -> Exists Q xs.
Proof.
intros P Q H xs H0.
induction H0.
apply (Exists_cons_hd Q x l (H x H0)).
apply (Exists_cons_tl x IHExists).
Qed.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma neg_Forall_Exists_neg (P:A->Prop) (l:list A) :
(forall x:A, {P x} + { ~ P x }) ->
~ Forall P l ->
Exists (fun x => ~ P x) l.
Proof.
intro Dec.
apply Exists_Forall_neg; intros.
destruct (Dec x); auto.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
now apply neg_Forall_Exists_neg.
Defined.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists : core.
Hint Constructors Forall : core.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2 : core.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2 : core.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs : core.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:49:21 05/11/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(
input [0:0] clka,
input [0:0] rst,
output [5:0] address,
output [31:0] Inst_code
);
wire [31:0] douta;
wire [5:0] addra;
reg [31:0] PC;
wire [31:0] PC_new;
ROM_B Inst_addr (
.clka(clka), // input clka
.addra(addra), // input [5 : 0] addra
.douta(douta) // output [31 : 0] douta
);
assign PC_new = PC + 4;
assign Inst_code = douta;
assign addra = PC[7:2];
assign address = PC[7:2];
always@(posedge clka or posedge rst)
begin
if(rst)
begin
PC[31:0]<=32'd0;
end
else
begin
PC<=PC_new;
end
end
endmodule
|
/*******************************************************************************
* Module: ramt_var_w_var_r
* Date:2015-05-29
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Does not use parity bits to increase total data width, width down to 1 are valid.
*
* Copyright (c) 2015 Elphel, Inc.
* ramt_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ramt_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ramt_var_w_var_r
#(
parameter integer REGISTERS_A = 0, // 1 - registered output
parameter integer REGISTERS_B = 0, // 1 - registered output
parameter integer LOG2WIDTH_A = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_B = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [14-LOG2WIDTH_A:0] addr_a, // address port A
input en_a, // enable port A (read and write)
input regen_a, // output register enable port A
input we_a, // write port enable port A
output [(1 << LOG2WIDTH_A)-1:0] data_out_a,// data out port A
input [(1 << LOG2WIDTH_A)-1:0] data_in_a, // data in port A
input clk_b, // clock for port BA
input [14-LOG2WIDTH_B:0] addr_b, // address port B
input en_b, // read enable port B
input regen_b, // output register enable port B
input we_b, // write port enable port B
output [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
input [(1 << LOG2WIDTH_B)-1:0] data_in_b // data in port B
);
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
localparam WIDTH_B = 1 << LOG2WIDTH_B;
wire [31:0] data_out32_a;
assign data_out_a=data_out32_a[WIDTH_A-1:0];
wire [31:0] data_out32_b;
assign data_out_b=data_out32_b[WIDTH_B-1:0];
wire [WIDTH_A+31:0] data_in_ext_a = {32'b0,data_in_a[WIDTH_A-1:0]};
wire [31:0] data_in32_a = data_in_ext_a[31:0];
wire [WIDTH_B+31:0] data_in_ext_b = {32'b0,data_in_b[WIDTH_B-1:0]};
wire [31:0] data_in32_b = data_in_ext_b[31:0];
RAMB36E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS_A), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
.DOB_REG (REGISTERS_B), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
.RAM_EXTENSION_A ("NONE"), // Cascading, valid: "NONE","UPPER", LOWER"
.RAM_EXTENSION_B ("NONE"), // Cascading, valid: "NONE","UPPER", LOWER"
.READ_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.READ_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.WRITE_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A (WRITE_MODE_A), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B (WRITE_MODE_B), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES"), // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out32_a), // Port A data/LSB data[31:0], output
.DOPADOP (), // Port A parity/LSB parity[3:0], output
.DIADI (data_in32_a), // Port A data/LSB data[31:0], input
.DIPADIP (4'b0), // Port A parity/LSB parity[3:0], input
.ADDRARDADDR ({1'b1,addr_a,{LOG2WIDTH_A{1'b1}}}), // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKARDCLK (clk_a), // Port A (read port in SDP) clock, input
.ENARDEN (en_a), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen_a), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA ({4{we_a}}), // Port A (read port in SDP) Write Enable[3:0], input
// Port B
.DOBDO (data_out32_b), // Port B data/MSB data[31:0], output
.DOPBDOP (), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in32_b), // Port B data/MSB data[31:0], input
.DIPBDIP (4'b0), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({1'b1,addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKBWRCLK (clk_b), // Port B (write port in SDP) clock, input
.ENBWREN (en_b), // Port B (write port in SDP) Enable, input
.REGCEB (regen_b), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE ({4'b0,{4{we_b}}}),// Port B (write port in SDP) Write Enable[7:0], input
// Error correction circuitry
.SBITERR (), // Single bit error status, output
.DBITERR (), // Double bit error status, output
.ECCPARITY (), // Genearted error correction parity [7:0], output
.RDADDRECC (), // ECC read address[8:0], output
.INJECTSBITERR (1'b0), // inject a single-bit error, input
.INJECTDBITERR (1'b0), // inject a double-bit error, input
// Cascade signals to create 64Kx1
.CASCADEOUTA (), // A-port cascade, output
.CASCADEOUTB (), // B-port cascade, output
.CASCADEINA (1'b0), // A-port cascade, input
.CASCADEINB (1'b0) // B-port cascade, input
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_SYMBOL_V
`define SKY130_FD_SC_HD__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_2_V
`define SKY130_FD_SC_LS__A41O_2_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41o_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41o_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
|
module TestFCounter();
reg clk, sig; //Clock and input RF signal whose frequency we must measure.
wire [13:0] f; //Calculated frequency.
integer fMeas;
integer fAct; //Actual frequency.
integer nSig;
integer testNum;
//Number of positive edges in sig before counter computes f. Note that in repeat blocks, inversions of sig are carried out so that two repetitions are needed to create one new positive edge.
parameter clk_units=10;
parameter m=8000;
parameter f_clk=40000; //Clock frequency in hundreds of Hz.
//Instantiate counter.
fcounter c(clk, sig, f);
//initial begin
// $dumpfile ("fcounterTestBench.vcd");
// $dumpvars;
//end
initial begin
$display("\t\ttime,\ttest#,\tf_actual [100's Hz],\tf_meas [100's Hz]");
//$monitor("%d\t%d\t%d\t%d",$time, testNum, fAct,f);
$monitor("%d\t%d\t%d\t%d",$time, testNum, fAct, f);
end
initial begin
#0
clk=1'b0;
sig=1'b0;
nSig=0; //Initialize signal edge counter.
testNum=0;
//counter listens for 50 positive edges of sig before making a measurement.
//Test 1: f_sig/f_clk = 1/10 => f_sig=4000 hundred Hz.
testNum=testNum+1;
fAct=f_clk/clk_units; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (8*m*clk_units) begin
#100 sig=~sig; //f_sig / f_clk = tau_c/tau_s => tau_s=tau_c * f_clk/f_sig = 10*10=100
nSig=nSig+1;
//function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
//Test 2: f_sig/f_clk = 1/100
testNum=testNum+1;
fAct=f_clk/100; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (4*m*clk_units) begin
#1000 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*100=1000
nSig=nSig+1;
// function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
//Test 3: f_sig/f_clk = 1/50
testNum=testNum+1;
fAct=f_clk/50; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (3*m*clk_units) begin
#500 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*50=500
nSig=nSig+1;
// function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
//Test 4: f_sig/f_clk=1/23
testNum=testNum+1;
fAct=f_clk/23; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (3*m*clk_units) begin
#230 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*23=230
nSig=nSig+1;
// function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
//Test 5: f_sig faster than f_clk: f_sig/f_clk=5
testNum=testNum+1;
fAct=f_clk*5; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (8*m*clk_units) begin
#2 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10/5=2
nSig=nSig+1;
// function int $cast( fMeas, f );
end
$display("Now make tests last for non-integer or half-integer numbers of M*sig posedges.");
//Test 6: f_sig/f_clk = 1/50
testNum=testNum+1;
fAct=f_clk/50; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (2*m*clk_units+3) begin
#500 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*50=500
nSig=nSig+1;
// function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
//Test 7: f_sig/f_clk=1/23
testNum=testNum+1;
fAct=f_clk/23; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
repeat (4*m*clk_units+7) begin
#230 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*23=230
nSig=nSig+1;
// function int $cast( fMeas, f );
end
nSig=0; //Restart nSig counter.
nSig=0; //Restart nSig counter.
//Test 8: f_sig/f_clk=1/100000
// testNum=testNum+1;
// fAct=f_clk/1000; //fActual = m_sig_counts / (#clock counts*tau_c) = m * f_clk/n
// repeat (2*m*clk_units+1) begin
// #10000 sig=~sig; //tau_s=tau_c * f_clk/f_sig = 10*100000=1000000
// nSig=nSig+1;
// end
// nSig=0; //Restart nSig counter.
#5 $finish; //Stop the simulation
end
always begin
//Choose larger number of cycles between clock edges to allow for
//different ratios of sig and clock frequencies.
#clk_units
clk=~clk; //Invert clock
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:33:44 09/17/2015
// Design Name: Key Encoder
// Module Name: KeyEncoderAJM
//////////////////////////////////////////////////////////////////////////////////
module KeyEncoderAJM(Columns, Rows, KeyNumber);
input [3:0] Columns;
input [3:0] Rows;
output reg [4:0] KeyNumber;
parameter NoKey = 0;
parameter key1 = 1;
parameter key2 = 2;
parameter key3 = 3;
parameter key4 = 4;
parameter key5 = 5;
parameter key6 = 6;
parameter key7 = 7;
parameter key8 = 8;
parameter key9 = 9;
parameter keyA = 10;
parameter keyB = 11;
parameter keyC = 12;
parameter keyD = 13;
parameter keyStar = 14;
parameter key0 = 15;
parameter keyPound = 16;
always@(Columns or Rows)
case ({ Columns, Rows })
8'b01110111: KeyNumber <= key1;
8'b10110111: KeyNumber <= key2;
8'b11010111: KeyNumber <= key3;
8'b01111011: KeyNumber <= key4;
8'b10111011: KeyNumber <= key5;
8'b11011011: KeyNumber <= key6;
8'b01111101: KeyNumber <= key7;
8'b10111101: KeyNumber <= key8;
8'b11011101: KeyNumber <= key9;
8'b11100111: KeyNumber <= keyA;
8'b11101011: KeyNumber <= keyB;
8'b11101101: KeyNumber <= keyC;
8'b11101110: KeyNumber <= keyD;
8'b01111110: KeyNumber <= keyStar;
8'b10111110: KeyNumber <= key0;
8'b11011110: KeyNumber <= keyPound;
default: KeyNumber <= NoKey;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_SYMBOL_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWLVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_PP_SYMBOL_V
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*########################################################################
AXI WRAPPER FOR ECFG BLOCK
########################################################################
*/
module axi_ecfg (/*AUTOARG*/
// Outputs
s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid,
esys_tx_enable, esys_tx_mmu_mode, esys_tx_gpio_mode,
esys_tx_ctrl_mode, esys_tx_clkdiv, esys_rx_enable,
esys_rx_mmu_mode, esys_rx_gpio_mode, esys_rx_loopback_mode,
esys_cclk_div, esys_cclk_pllcfg, esys_coreid, esys_dataout,
esys_irqsrc_read,
// Inputs
s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_rready, param_coreid, erx_irq_fifo_src, erx_irq_fifo_data,
erx_rdfifo_access, erx_rdfifo_wait, erx_wrfifo_access,
erx_wrfifo_wait, erx_wbfifo_access, erx_wbfifo_wait,
etx_rdfifo_access, etx_rdfifo_wait, etx_wrfifo_access,
etx_wrfifo_wait, etx_wbfifo_access, etx_wbfifo_wait
);
//Register file parameters
/*
#####################################################################
COMPILE TIME PARAMETERS
######################################################################
*/
parameter DW = 32; //elink monitor register width
parameter AW = 32; //mmu table address width
parameter SW = DW/8; //mmu table address width
parameter MAW = 6; //register file address width
parameter MDW = 32; //
parameter IDW = 12; //Elink ID (row,column coordinate)
/*****************************/
/*AXI SLAVE INTERFACE (LITE) */
/*****************************/
//Global signals
input s_axi_aclk; //clock source for axi slave interfaces
input s_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
input [AW-1:0] s_axi_awaddr; //write address
input [2:0] s_axi_awprot; //write protection type
input s_axi_awvalid; //write address valid
output s_axi_awready; //write address ready
//Write data channel
input [DW-1:0] s_axi_wdata; //write data
input [SW-1:0] s_axi_wstrb; //write strobes
input s_axi_wvalid; //write valid
output s_axi_wready; //write channel ready
//Buffered write response channel
input s_axi_bready; //write ready
output [1:0] s_axi_bresp; //write response
output s_axi_bvalid; //write response valid
//Read address channel
input [AW-1:0] s_axi_araddr; //read address
input [2:0] s_axi_arprot; //read protection type
input s_axi_arvalid; //read address valid
output s_axi_arready; //read address ready
//Read data channel
output [DW-1:0] s_axi_rdata; //read data
output [1:0] s_axi_rresp; //read response
output s_axi_rvalid; //read valid
input s_axi_rready; //read ready
/*****************************/
/*STATIC SIGNALS */
/*****************************/
input [IDW-1:0] param_coreid;
/*****************************/
/*ELINK DATAPATH INPUTS */
/*****************************/
input [11:0] erx_irq_fifo_src;
input [11:0] erx_irq_fifo_data;
input erx_rdfifo_access;
input erx_rdfifo_wait;
input erx_wrfifo_access;
input erx_wrfifo_wait;
input erx_wbfifo_access;
input erx_wbfifo_wait;
input etx_rdfifo_access;
input etx_rdfifo_wait;
input etx_wrfifo_access;
input etx_wrfifo_wait;
input etx_wbfifo_access;
input etx_wbfifo_wait;
/*****************************/
/*ECFG CONTROL OUTPUTS */
/*****************************/
//tx
output esys_tx_enable; //enable signal for TX
output esys_tx_mmu_mode; //enables MMU on transnmit path
output esys_tx_gpio_mode; //forces TX output pins to constants
output [3:0] esys_tx_ctrl_mode; //value for emesh ctrlmode tag
output [3:0] esys_tx_clkdiv; //transmit clock divider
//rx
output esys_rx_enable; //enable signal for rx
output esys_rx_mmu_mode; //enables MMU on rx path
output esys_rx_gpio_mode; //forces rx wait pins to constants
output esys_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//cclk
output [3:0] esys_cclk_div; //cclk divider setting
output [3:0] esys_cclk_pllcfg; //pll configuration
//coreid
output [11:0] esys_coreid; //core-id for fpga elink
//gpio
output [11:0] esys_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
//irq
output esys_irqsrc_read; //increments the irq fifo pointer
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
wire [11:0] ecfg_dataout; // From ecfg of ecfg.v
wire ecfg_rx_enable; // From ecfg of ecfg.v
wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
wire ecfg_rx_loopback_mode; // From ecfg of ecfg.v
wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
wire ecfg_tx_enable; // From ecfg of ecfg.v
wire ecfg_tx_gpio_mode; // From ecfg of ecfg.v
wire ecfg_tx_mmu_mode; // From ecfg of ecfg.v
wire mi_access; // From axi_memif of axi_memif.v
wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
wire [MDW-1:0] mi_data_in; // From axi_memif of axi_memif.v
wire [31:0] mi_data_out; // From ecfg of ecfg.v
wire mi_write; // From axi_memif of axi_memif.v
// End of automatics
axi_memif axi_memif(/*AUTOINST*/
// Outputs
.s_axi_awready (s_axi_awready),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata[DW-1:0]),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.mi_addr (mi_addr[MAW-1:0]),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_data_in (mi_data_in[MDW-1:0]),
// Inputs
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_wdata (s_axi_wdata[DW-1:0]),
.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr[AW-1:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_rready (s_axi_rready),
.mi_data_out (mi_data_out[MDW-1:0]));
ecfg ecfg(
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[31:0]),
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
.ecfg_rx_enable (ecfg_rx_enable),
.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
.ecfg_rx_loopback_mode (ecfg_rx_loopback_mode),
.ecfg_cclk_div (ecfg_cclk_div[3:0]),
.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
.ecfg_coreid (ecfg_coreid[11:0]),
.ecfg_dataout (ecfg_dataout[11:0]),
// Inputs
.param_coreid (param_coreid[IDW-1:0]),
.clk (clk),
.reset (reset),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[5:0]),
.mi_data_in (mi_data_in[31:0]));
endmodule // axi_ecfg
// Local Variables:
// verilog-library-directories:("." "../axi")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_1_V
`define SKY130_FD_SC_HS__A222OI_1_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// hart0_server_reset_response_get O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 16 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 16 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// mem_master_awvalid O 1
// mem_master_awid O 16 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1
// mem_master_arvalid O 1
// mem_master_arid O 16 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1
// dma_server_awready O 1 reg
// dma_server_wready O 1 reg
// dma_server_bvalid O 1 reg
// dma_server_bid O 16 reg
// dma_server_bresp O 2 reg
// dma_server_arready O 1 reg
// dma_server_rvalid O 1 reg
// dma_server_rid O 16 reg
// dma_server_rdata O 512 reg
// dma_server_rresp O 2 reg
// dma_server_rlast O 1 reg
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// hart0_server_reset_request_put I 1 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 16 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 16 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 16 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 16 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// dma_server_awvalid I 1
// dma_server_awid I 16 reg
// dma_server_awaddr I 64 reg
// dma_server_awlen I 8 reg
// dma_server_awsize I 3 reg
// dma_server_awburst I 2 reg
// dma_server_awlock I 1 reg
// dma_server_awcache I 4 reg
// dma_server_awprot I 3 reg
// dma_server_awqos I 4 reg
// dma_server_awregion I 4 reg
// dma_server_wvalid I 1
// dma_server_wdata I 512 reg
// dma_server_wstrb I 64 reg
// dma_server_wlast I 1 reg
// dma_server_bready I 1
// dma_server_arvalid I 1
// dma_server_arid I 16 reg
// dma_server_araddr I 64 reg
// dma_server_arlen I 8 reg
// dma_server_arsize I 3 reg
// dma_server_arburst I 2 reg
// dma_server_arlock I 1 reg
// dma_server_arcache I 4 reg
// dma_server_arprot I 3 reg
// dma_server_arqos I 4 reg
// dma_server_arregion I 4 reg
// dma_server_rready I 1
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_hart0_server_reset_request_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_hart0_server_reset_response_get I 1
//
// Combinational paths from inputs to outputs:
// (mem_master_awready, mem_master_wready) -> mem_master_bready
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCPU(CLK,
RST_N,
hart0_server_reset_request_put,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input hart0_server_reset_request_put;
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// actionvalue method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [15 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [15 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [15 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [15 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [15 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [15 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [15 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [15 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid,
dma_server_rid,
imem_master_arid,
imem_master_awid,
mem_master_arid,
mem_master_awid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] imem_master_arcache,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
hart0_server_reset_response_get,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_logdelay
reg [63 : 0] cfg_logdelay;
wire [63 : 0] cfg_logdelay$D_IN;
wire cfg_logdelay$EN;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register imem_rg_cache_addr
reg [63 : 0] imem_rg_cache_addr;
reg [63 : 0] imem_rg_cache_addr$D_IN;
wire imem_rg_cache_addr$EN;
// register imem_rg_cache_b16
reg [15 : 0] imem_rg_cache_b16;
wire [15 : 0] imem_rg_cache_b16$D_IN;
wire imem_rg_cache_b16$EN;
// register imem_rg_f3
reg [2 : 0] imem_rg_f3;
wire [2 : 0] imem_rg_f3$D_IN;
wire imem_rg_f3$EN;
// register imem_rg_mstatus_MXR
reg imem_rg_mstatus_MXR;
wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;
// register imem_rg_pc
reg [63 : 0] imem_rg_pc;
reg [63 : 0] imem_rg_pc$D_IN;
wire imem_rg_pc$EN;
// register imem_rg_priv
reg [1 : 0] imem_rg_priv;
wire [1 : 0] imem_rg_priv$D_IN;
wire imem_rg_priv$EN;
// register imem_rg_satp
reg [63 : 0] imem_rg_satp;
wire [63 : 0] imem_rg_satp$D_IN;
wire imem_rg_satp$EN;
// register imem_rg_sstatus_SUM
reg imem_rg_sstatus_SUM;
wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;
// register imem_rg_tval
reg [63 : 0] imem_rg_tval;
reg [63 : 0] imem_rg_tval$D_IN;
wire imem_rg_tval$EN;
// register rg_csr_pc
reg [63 : 0] rg_csr_pc;
wire [63 : 0] rg_csr_pc$D_IN;
wire rg_csr_pc$EN;
// register rg_csr_val1
reg [63 : 0] rg_csr_val1;
wire [63 : 0] rg_csr_val1$D_IN;
wire rg_csr_val1$EN;
// register rg_cur_priv
reg [1 : 0] rg_cur_priv;
reg [1 : 0] rg_cur_priv$D_IN;
wire rg_cur_priv$EN;
// register rg_epoch
reg [1 : 0] rg_epoch;
reg [1 : 0] rg_epoch$D_IN;
wire rg_epoch$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_next_pc
reg [63 : 0] rg_next_pc;
reg [63 : 0] rg_next_pc$D_IN;
wire rg_next_pc$EN;
// register rg_run_on_reset
reg rg_run_on_reset;
wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_start_CPI_cycles
reg [63 : 0] rg_start_CPI_cycles;
wire [63 : 0] rg_start_CPI_cycles$D_IN;
wire rg_start_CPI_cycles$EN;
// register rg_start_CPI_instrs
reg [63 : 0] rg_start_CPI_instrs;
wire [63 : 0] rg_start_CPI_instrs$D_IN;
wire rg_start_CPI_instrs$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_trap_info
reg [131 : 0] rg_trap_info;
reg [131 : 0] rg_trap_info$D_IN;
wire rg_trap_info$EN;
// register rg_trap_instr
reg [31 : 0] rg_trap_instr;
wire [31 : 0] rg_trap_instr$D_IN;
wire rg_trap_instr$EN;
// register rg_trap_interrupt
reg rg_trap_interrupt;
wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;
// register stage1_rg_full
reg stage1_rg_full;
reg stage1_rg_full$D_IN;
wire stage1_rg_full$EN;
// register stage1_rg_stage_input
reg [401 : 0] stage1_rg_stage_input;
wire [401 : 0] stage1_rg_stage_input$D_IN;
wire stage1_rg_stage_input$EN;
// register stage2_rg_full
reg stage2_rg_full;
reg stage2_rg_full$D_IN;
wire stage2_rg_full$EN;
// register stage2_rg_resetting
reg stage2_rg_resetting;
wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;
// register stage2_rg_stage2
reg [495 : 0] stage2_rg_stage2;
wire [495 : 0] stage2_rg_stage2$D_IN;
wire stage2_rg_stage2$EN;
// register stage3_rg_full
reg stage3_rg_full;
reg stage3_rg_full$D_IN;
wire stage3_rg_full$EN;
// register stage3_rg_stage3
reg [238 : 0] stage3_rg_stage3;
wire [238 : 0] stage3_rg_stage3$D_IN;
wire stage3_rg_stage3$EN;
// register stageD_rg_data
reg [233 : 0] stageD_rg_data;
wire [233 : 0] stageD_rg_data$D_IN;
wire stageD_rg_data$EN;
// register stageD_rg_full
reg stageD_rg_full;
reg stageD_rg_full$D_IN;
wire stageD_rg_full$EN;
// register stageF_rg_epoch
reg [1 : 0] stageF_rg_epoch;
reg [1 : 0] stageF_rg_epoch$D_IN;
wire stageF_rg_epoch$EN;
// register stageF_rg_full
reg stageF_rg_full;
reg stageF_rg_full$D_IN;
wire stageF_rg_full$EN;
// register stageF_rg_priv
reg [1 : 0] stageF_rg_priv;
wire [1 : 0] stageF_rg_priv$D_IN;
wire stageF_rg_priv$EN;
// ports of submodule csr_regfile
wire [193 : 0] csr_regfile$csr_trap_actions;
wire [129 : 0] csr_regfile$csr_ret_actions;
wire [64 : 0] csr_regfile$read_csr;
wire [63 : 0] csr_regfile$csr_trap_actions_pc,
csr_regfile$csr_trap_actions_xtval,
csr_regfile$mav_csr_write_word,
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
csr_regfile$read_mstatus,
csr_regfile$read_satp,
csr_regfile$read_sstatus;
wire [27 : 0] csr_regfile$read_misa;
wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
csr_regfile$access_permitted_2_csr_addr,
csr_regfile$csr_counter_read_fault_csr_addr,
csr_regfile$mav_csr_write_csr_addr,
csr_regfile$mav_read_csr_csr_addr,
csr_regfile$read_csr_csr_addr,
csr_regfile$read_csr_port2_csr_addr;
wire [4 : 0] csr_regfile$interrupt_pending,
csr_regfile$ma_update_fcsr_fflags_flags,
csr_regfile$mv_update_fcsr_fflags_flags;
wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
wire [2 : 0] csr_regfile$read_frm;
wire [1 : 0] csr_regfile$access_permitted_1_priv,
csr_regfile$access_permitted_2_priv,
csr_regfile$csr_counter_read_fault_priv,
csr_regfile$csr_ret_actions_from_priv,
csr_regfile$csr_trap_actions_from_priv,
csr_regfile$interrupt_pending_cur_priv,
csr_regfile$ma_update_mstatus_fs_fs,
csr_regfile$mv_update_mstatus_fs_fs;
wire csr_regfile$EN_csr_minstret_incr,
csr_regfile$EN_csr_ret_actions,
csr_regfile$EN_csr_trap_actions,
csr_regfile$EN_debug,
csr_regfile$EN_ma_update_fcsr_fflags,
csr_regfile$EN_ma_update_mstatus_fs,
csr_regfile$EN_mav_csr_write,
csr_regfile$EN_mav_read_csr,
csr_regfile$EN_server_reset_request_put,
csr_regfile$EN_server_reset_response_get,
csr_regfile$RDY_server_reset_request_put,
csr_regfile$RDY_server_reset_response_get,
csr_regfile$access_permitted_1,
csr_regfile$access_permitted_1_read_not_write,
csr_regfile$access_permitted_2,
csr_regfile$access_permitted_2_read_not_write,
csr_regfile$csr_trap_actions_interrupt,
csr_regfile$csr_trap_actions_nmi,
csr_regfile$m_external_interrupt_req_set_not_clear,
csr_regfile$nmi_pending,
csr_regfile$nmi_req_set_not_clear,
csr_regfile$s_external_interrupt_req_set_not_clear,
csr_regfile$software_interrupt_req_set_not_clear,
csr_regfile$timer_interrupt_req_set_not_clear,
csr_regfile$wfi_resume;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fpr_regfile
wire [63 : 0] fpr_regfile$read_rs1,
fpr_regfile$read_rs2,
fpr_regfile$read_rs3,
fpr_regfile$write_rd_rd_val;
wire [4 : 0] fpr_regfile$read_rs1_port2_rs1,
fpr_regfile$read_rs1_rs1,
fpr_regfile$read_rs2_rs2,
fpr_regfile$read_rs3_rs3,
fpr_regfile$write_rd_rd;
wire fpr_regfile$EN_server_reset_request_put,
fpr_regfile$EN_server_reset_response_get,
fpr_regfile$EN_write_rd,
fpr_regfile$RDY_server_reset_request_put,
fpr_regfile$RDY_server_reset_response_get;
// ports of submodule gpr_regfile
wire [63 : 0] gpr_regfile$read_rs1,
gpr_regfile$read_rs2,
gpr_regfile$write_rd_rd_val;
wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
gpr_regfile$read_rs1_rs1,
gpr_regfile$read_rs2_rs2,
gpr_regfile$write_rd_rd;
wire gpr_regfile$EN_server_reset_request_put,
gpr_regfile$EN_server_reset_response_get,
gpr_regfile$EN_write_rd,
gpr_regfile$RDY_server_reset_request_put,
gpr_regfile$RDY_server_reset_response_get;
// ports of submodule near_mem
reg [63 : 0] near_mem$dmem_req_store_value, near_mem$imem_req_addr;
wire [511 : 0] near_mem$dma_server_rdata, near_mem$dma_server_wdata;
wire [63 : 0] near_mem$dma_server_araddr,
near_mem$dma_server_awaddr,
near_mem$dma_server_wstrb,
near_mem$dmem_req_addr,
near_mem$dmem_req_satp,
near_mem$dmem_word64,
near_mem$imem_master_araddr,
near_mem$imem_master_awaddr,
near_mem$imem_master_rdata,
near_mem$imem_master_wdata,
near_mem$imem_pc,
near_mem$imem_req_satp,
near_mem$mem_master_araddr,
near_mem$mem_master_awaddr,
near_mem$mem_master_rdata,
near_mem$mem_master_wdata,
near_mem$mv_tohost_value,
near_mem$set_watch_tohost_tohost_addr;
wire [31 : 0] near_mem$imem_instr;
wire [15 : 0] near_mem$dma_server_arid,
near_mem$dma_server_awid,
near_mem$dma_server_bid,
near_mem$dma_server_rid,
near_mem$imem_master_arid,
near_mem$imem_master_awid,
near_mem$imem_master_bid,
near_mem$imem_master_rid,
near_mem$mem_master_arid,
near_mem$mem_master_awid,
near_mem$mem_master_bid,
near_mem$mem_master_rid;
wire [7 : 0] near_mem$dma_server_arlen,
near_mem$dma_server_awlen,
near_mem$imem_master_arlen,
near_mem$imem_master_awlen,
near_mem$imem_master_wstrb,
near_mem$mem_master_arlen,
near_mem$mem_master_awlen,
near_mem$mem_master_wstrb,
near_mem$mv_status,
near_mem$server_fence_request_put;
wire [6 : 0] near_mem$dmem_req_amo_funct7;
wire [3 : 0] near_mem$dma_server_arcache,
near_mem$dma_server_arqos,
near_mem$dma_server_arregion,
near_mem$dma_server_awcache,
near_mem$dma_server_awqos,
near_mem$dma_server_awregion,
near_mem$dmem_exc_code,
near_mem$imem_exc_code,
near_mem$imem_master_arcache,
near_mem$imem_master_arqos,
near_mem$imem_master_arregion,
near_mem$imem_master_awcache,
near_mem$imem_master_awqos,
near_mem$imem_master_awregion,
near_mem$mem_master_arcache,
near_mem$mem_master_arqos,
near_mem$mem_master_arregion,
near_mem$mem_master_awcache,
near_mem$mem_master_awqos,
near_mem$mem_master_awregion;
wire [2 : 0] near_mem$dma_server_arprot,
near_mem$dma_server_arsize,
near_mem$dma_server_awprot,
near_mem$dma_server_awsize,
near_mem$dmem_req_f3,
near_mem$imem_master_arprot,
near_mem$imem_master_arsize,
near_mem$imem_master_awprot,
near_mem$imem_master_awsize,
near_mem$imem_req_f3,
near_mem$mem_master_arprot,
near_mem$mem_master_arsize,
near_mem$mem_master_awprot,
near_mem$mem_master_awsize;
wire [1 : 0] near_mem$dma_server_arburst,
near_mem$dma_server_awburst,
near_mem$dma_server_bresp,
near_mem$dma_server_rresp,
near_mem$dmem_req_op,
near_mem$dmem_req_priv,
near_mem$imem_master_arburst,
near_mem$imem_master_awburst,
near_mem$imem_master_bresp,
near_mem$imem_master_rresp,
near_mem$imem_req_priv,
near_mem$mem_master_arburst,
near_mem$mem_master_awburst,
near_mem$mem_master_bresp,
near_mem$mem_master_rresp;
wire near_mem$EN_dmem_req,
near_mem$EN_imem_req,
near_mem$EN_ma_ddr4_ready,
near_mem$EN_server_fence_i_request_put,
near_mem$EN_server_fence_i_response_get,
near_mem$EN_server_fence_request_put,
near_mem$EN_server_fence_response_get,
near_mem$EN_server_reset_request_put,
near_mem$EN_server_reset_response_get,
near_mem$EN_set_watch_tohost,
near_mem$EN_sfence_vma_server_request_put,
near_mem$EN_sfence_vma_server_response_get,
near_mem$RDY_server_reset_request_put,
near_mem$RDY_server_reset_response_get,
near_mem$dma_server_arlock,
near_mem$dma_server_arready,
near_mem$dma_server_arvalid,
near_mem$dma_server_awlock,
near_mem$dma_server_awready,
near_mem$dma_server_awvalid,
near_mem$dma_server_bready,
near_mem$dma_server_bvalid,
near_mem$dma_server_rlast,
near_mem$dma_server_rready,
near_mem$dma_server_rvalid,
near_mem$dma_server_wlast,
near_mem$dma_server_wready,
near_mem$dma_server_wvalid,
near_mem$dmem_exc,
near_mem$dmem_req_mstatus_MXR,
near_mem$dmem_req_sstatus_SUM,
near_mem$dmem_valid,
near_mem$imem_exc,
near_mem$imem_is_i32_not_i16,
near_mem$imem_master_arlock,
near_mem$imem_master_arready,
near_mem$imem_master_arvalid,
near_mem$imem_master_awlock,
near_mem$imem_master_awready,
near_mem$imem_master_awvalid,
near_mem$imem_master_bready,
near_mem$imem_master_bvalid,
near_mem$imem_master_rlast,
near_mem$imem_master_rready,
near_mem$imem_master_rvalid,
near_mem$imem_master_wlast,
near_mem$imem_master_wready,
near_mem$imem_master_wvalid,
near_mem$imem_req_mstatus_MXR,
near_mem$imem_req_sstatus_SUM,
near_mem$imem_valid,
near_mem$mem_master_arlock,
near_mem$mem_master_arready,
near_mem$mem_master_arvalid,
near_mem$mem_master_awlock,
near_mem$mem_master_awready,
near_mem$mem_master_awvalid,
near_mem$mem_master_bready,
near_mem$mem_master_bvalid,
near_mem$mem_master_rlast,
near_mem$mem_master_rready,
near_mem$mem_master_rvalid,
near_mem$mem_master_wlast,
near_mem$mem_master_wready,
near_mem$mem_master_wvalid,
near_mem$set_watch_tohost_watch_tohost;
// ports of submodule stage1_f_reset_reqs
wire stage1_f_reset_reqs$CLR,
stage1_f_reset_reqs$DEQ,
stage1_f_reset_reqs$EMPTY_N,
stage1_f_reset_reqs$ENQ,
stage1_f_reset_reqs$FULL_N;
// ports of submodule stage1_f_reset_rsps
wire stage1_f_reset_rsps$CLR,
stage1_f_reset_rsps$DEQ,
stage1_f_reset_rsps$EMPTY_N,
stage1_f_reset_rsps$ENQ,
stage1_f_reset_rsps$FULL_N;
// ports of submodule stage2_f_reset_reqs
wire stage2_f_reset_reqs$CLR,
stage2_f_reset_reqs$DEQ,
stage2_f_reset_reqs$EMPTY_N,
stage2_f_reset_reqs$ENQ,
stage2_f_reset_reqs$FULL_N;
// ports of submodule stage2_f_reset_rsps
wire stage2_f_reset_rsps$CLR,
stage2_f_reset_rsps$DEQ,
stage2_f_reset_rsps$EMPTY_N,
stage2_f_reset_rsps$ENQ,
stage2_f_reset_rsps$FULL_N;
// ports of submodule stage2_fbox
wire [63 : 0] stage2_fbox$req_v1,
stage2_fbox$req_v2,
stage2_fbox$req_v3,
stage2_fbox$word_fst;
wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode;
wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd;
wire [2 : 0] stage2_fbox$req_rm;
wire stage2_fbox$EN_req,
stage2_fbox$EN_server_reset_request_put,
stage2_fbox$EN_server_reset_response_get,
stage2_fbox$RDY_server_reset_request_put,
stage2_fbox$RDY_server_reset_response_get,
stage2_fbox$valid;
// ports of submodule stage2_mbox
wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
wire [2 : 0] stage2_mbox$req_f3;
wire stage2_mbox$EN_req,
stage2_mbox$EN_req_reset,
stage2_mbox$EN_rsp_reset,
stage2_mbox$EN_set_verbosity,
stage2_mbox$req_is_OP_not_OP_32,
stage2_mbox$valid;
// ports of submodule stage3_f_reset_reqs
wire stage3_f_reset_reqs$CLR,
stage3_f_reset_reqs$DEQ,
stage3_f_reset_reqs$EMPTY_N,
stage3_f_reset_reqs$ENQ,
stage3_f_reset_reqs$FULL_N;
// ports of submodule stage3_f_reset_rsps
wire stage3_f_reset_rsps$CLR,
stage3_f_reset_rsps$DEQ,
stage3_f_reset_rsps$EMPTY_N,
stage3_f_reset_rsps$ENQ,
stage3_f_reset_rsps$FULL_N;
// ports of submodule stageD_f_reset_reqs
wire stageD_f_reset_reqs$CLR,
stageD_f_reset_reqs$DEQ,
stageD_f_reset_reqs$EMPTY_N,
stageD_f_reset_reqs$ENQ,
stageD_f_reset_reqs$FULL_N;
// ports of submodule stageD_f_reset_rsps
wire stageD_f_reset_rsps$CLR,
stageD_f_reset_rsps$DEQ,
stageD_f_reset_rsps$EMPTY_N,
stageD_f_reset_rsps$ENQ,
stageD_f_reset_rsps$FULL_N;
// ports of submodule stageF_branch_predictor
reg [63 : 0] stageF_branch_predictor$predict_req_pc;
wire [194 : 0] stageF_branch_predictor$bp_train_cf_info;
wire [63 : 0] stageF_branch_predictor$bp_train_pc,
stageF_branch_predictor$predict_rsp;
wire [31 : 0] stageF_branch_predictor$bp_train_instr,
stageF_branch_predictor$predict_rsp_instr;
wire stageF_branch_predictor$EN_bp_train,
stageF_branch_predictor$EN_predict_req,
stageF_branch_predictor$EN_reset,
stageF_branch_predictor$RDY_predict_req,
stageF_branch_predictor$bp_train_is_i32_not_i16,
stageF_branch_predictor$predict_rsp_is_i32_not_i16;
// ports of submodule stageF_f_reset_reqs
wire stageF_f_reset_reqs$CLR,
stageF_f_reset_reqs$DEQ,
stageF_f_reset_reqs$EMPTY_N,
stageF_f_reset_reqs$ENQ,
stageF_f_reset_reqs$FULL_N;
// ports of submodule stageF_f_reset_rsps
wire stageF_f_reset_rsps$CLR,
stageF_f_reset_rsps$DEQ,
stageF_f_reset_rsps$EMPTY_N,
stageF_f_reset_rsps$ENQ,
stageF_f_reset_rsps$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_imem_rl_assert_fail,
CAN_FIRE_RL_imem_rl_fetch_next_32b,
CAN_FIRE_RL_rl_WFI_resume,
CAN_FIRE_RL_rl_finish_FENCE,
CAN_FIRE_RL_rl_finish_FENCE_I,
CAN_FIRE_RL_rl_finish_SFENCE_VMA,
CAN_FIRE_RL_rl_pipe,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_reset_from_WFI,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_show_pipe,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
CAN_FIRE_RL_rl_stage1_CSRR_W,
CAN_FIRE_RL_rl_stage1_CSRR_W_2,
CAN_FIRE_RL_rl_stage1_FENCE,
CAN_FIRE_RL_rl_stage1_FENCE_I,
CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
CAN_FIRE_RL_rl_stage1_WFI,
CAN_FIRE_RL_rl_stage1_interrupt,
CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
CAN_FIRE_RL_rl_stage1_trap,
CAN_FIRE_RL_rl_stage1_xRET,
CAN_FIRE_RL_rl_stage2_nonpipe,
CAN_FIRE_RL_rl_trap,
CAN_FIRE_RL_rl_trap_fetch,
CAN_FIRE_RL_stage1_rl_reset,
CAN_FIRE_RL_stage2_rl_reset_begin,
CAN_FIRE_RL_stage2_rl_reset_end,
CAN_FIRE_RL_stage3_rl_reset,
CAN_FIRE_RL_stageD_rl_reset,
CAN_FIRE_RL_stageF_rl_reset,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_imem_rl_assert_fail,
WILL_FIRE_RL_imem_rl_fetch_next_32b,
WILL_FIRE_RL_rl_WFI_resume,
WILL_FIRE_RL_rl_finish_FENCE,
WILL_FIRE_RL_rl_finish_FENCE_I,
WILL_FIRE_RL_rl_finish_SFENCE_VMA,
WILL_FIRE_RL_rl_pipe,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_reset_from_WFI,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_show_pipe,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
WILL_FIRE_RL_rl_stage1_CSRR_W,
WILL_FIRE_RL_rl_stage1_CSRR_W_2,
WILL_FIRE_RL_rl_stage1_FENCE,
WILL_FIRE_RL_rl_stage1_FENCE_I,
WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
WILL_FIRE_RL_rl_stage1_WFI,
WILL_FIRE_RL_rl_stage1_interrupt,
WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
WILL_FIRE_RL_rl_stage1_trap,
WILL_FIRE_RL_rl_stage1_xRET,
WILL_FIRE_RL_rl_stage2_nonpipe,
WILL_FIRE_RL_rl_trap,
WILL_FIRE_RL_rl_trap_fetch,
WILL_FIRE_RL_stage1_rl_reset,
WILL_FIRE_RL_stage2_rl_reset_begin,
WILL_FIRE_RL_stage2_rl_reset_end,
WILL_FIRE_RL_stage3_rl_reset,
WILL_FIRE_RL_stageD_rl_reset,
WILL_FIRE_RL_stageF_rl_reset,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
wire [131 : 0] MUX_rg_trap_info$write_1__VAL_1,
MUX_rg_trap_info$write_1__VAL_2,
MUX_rg_trap_info$write_1__VAL_3,
MUX_rg_trap_info$write_1__VAL_4;
wire [63 : 0] MUX_imem_rg_cache_addr$write_1__VAL_1,
MUX_imem_rg_cache_addr$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_3,
MUX_imem_rg_tval$write_1__VAL_4,
MUX_near_mem$imem_req_2__VAL_2,
MUX_near_mem$imem_req_2__VAL_4;
wire [31 : 0] MUX_rg_trap_instr$write_1__VAL_1;
wire [3 : 0] MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_3,
MUX_rg_state$write_1__VAL_4;
wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
MUX_gpr_regfile$write_rd_1__SEL_2,
MUX_imem_rg_cache_addr$write_1__SEL_1,
MUX_imem_rg_cache_addr$write_1__SEL_2,
MUX_imem_rg_cache_b16$write_1__PSEL_1,
MUX_rg_next_pc$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_2,
MUX_rg_state$write_1__PSEL_1,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_8,
MUX_rg_state$write_1__SEL_9,
MUX_rg_trap_info$write_1__SEL_1,
MUX_rg_trap_instr$write_1__SEL_1,
MUX_rg_trap_interrupt$write_1__SEL_1,
MUX_stage1_rg_full$write_1__VAL_2,
MUX_stage2_rg_full$write_1__VAL_2,
MUX_stage3_rg_full$write_1__VAL_2,
MUX_stageD_rg_full$write_1__VAL_2,
MUX_stageF_rg_full$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2440;
reg [31 : 0] v__h2434;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530,
_theResult_____1_fst__h12333,
alu_outputs___1_val1__h10371,
rs1_val__h35054,
value__h8443,
value__h8657,
x_out_bypass_rd_val__h9045,
x_out_cf_info_taken_PC__h16066,
x_out_data_to_stage2_addr__h9893,
x_out_data_to_stage2_val1__h9894,
x_out_data_to_stage3_frd_val__h8118,
x_out_data_to_stage3_rd_val__h8114,
x_out_fbypass_rd_val__h9227;
reg [4 : 0] data_to_stage2_rd__h9875,
x_out_bypass_rd__h9044,
x_out_data_to_stage3_fpr_flags__h8117,
x_out_data_to_stage3_rd__h8113,
x_out_fbypass_rd__h9226;
reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q15,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16,
alu_outputs_exc_code__h11528,
x_out_trap_info_exc_code__h8553;
reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22;
reg [1 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23;
reg CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324;
wire [429 : 0] IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511;
wire [127 : 0] csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801;
wire [63 : 0] IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1532,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1541,
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_057___d1269,
_theResult_____1_fst__h12326,
_theResult_____1_fst__h12361,
_theResult____h33602,
_theResult___fst__h12497,
_theResult___fst__h12504,
_theResult___fst__h12585,
_theResult___snd_fst_rd_val__h9208,
_theResult___snd_snd__h16492,
_theResult___snd_snd_rd_val__h8063,
addr_of_b32___1__h32186,
addr_of_b32___1__h43719,
addr_of_b32__h32058,
addr_of_b32__h43591,
alu_outputs___1_addr__h10096,
alu_outputs___1_addr__h10470,
alu_outputs___1_fval1__h11500,
alu_outputs___1_fval2__h10474,
alu_outputs___1_fval3__h11502,
alu_outputs___1_val1__h10269,
alu_outputs___1_val1__h10314,
alu_outputs___1_val1__h10343,
alu_outputs___1_val1__h10756,
alu_outputs___1_val1__h10784,
alu_outputs_cf_info_taken_PC__h16058,
branch_target__h10074,
cpi__h33604,
cpifrac__h33605,
data_to_stage2_addr__h9876,
data_to_stage2_val2__h9878,
delta_CPI_cycles__h33600,
delta_CPI_instrs___1__h33646,
delta_CPI_instrs__h33601,
fall_through_pc__h9619,
next_pc___1__h13758,
next_pc__h10109,
next_pc__h10144,
next_pc__h13755,
next_pc__h9620,
output_stage2___1_data_to_stage3_frd_val__h7992,
rd_val___1__h12241,
rd_val___1__h12322,
rd_val___1__h12329,
rd_val___1__h12336,
rd_val___1__h12343,
rd_val___1__h12350,
rd_val___1__h16521,
rd_val___1__h16552,
rd_val___1__h16584,
rd_val___1__h16613,
rd_val___1__h16665,
rd_val___1__h16713,
rd_val___1__h16719,
rd_val___1__h16764,
rd_val__h10385,
rd_val__h10406,
rd_val__h16393,
rd_val__h16444,
rd_val__h16466,
rd_val__h9457,
rd_val__h9490,
rd_val__h9523,
rd_val__h9554,
rd_val__h9588,
rs1_val__h34220,
rs1_val_bypassed__h5370,
rs2_val_bypassed__h5376,
trap_info_tval__h14908,
val__h9459,
val__h9492,
value__h14978,
x__h33603,
x_out_cf_info_fallthru_PC__h16065,
x_out_data_to_stage2_fval1__h9896,
x_out_data_to_stage2_fval3__h9898,
x_out_data_to_stage2_val2__h9895,
x_out_next_pc__h9637,
y__h35332;
wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2099,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1940,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1941,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1942,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1943,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1944,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1945,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1946,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1948,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1950,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1952,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1954,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1955,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1956,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1958,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1959,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1960,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1962,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1964,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1965,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1967,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1968,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1969,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1970,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1971,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1972,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1973,
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1974,
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2100,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18,
_theResult____h5654,
d_instr__h25151,
instr___1__h17516,
instr__h17693,
instr__h17838,
instr__h18030,
instr__h18225,
instr__h18454,
instr__h18907,
instr__h19023,
instr__h19088,
instr__h19405,
instr__h19743,
instr__h19927,
instr__h20056,
instr__h20283,
instr__h20538,
instr__h20710,
instr__h20879,
instr__h21068,
instr__h21257,
instr__h21374,
instr__h21552,
instr__h21671,
instr__h21766,
instr__h21902,
instr__h22038,
instr__h22174,
instr__h22312,
instr__h22450,
instr__h22608,
instr__h22704,
instr__h22857,
instr__h23056,
instr__h23207,
instr__h23412,
instr__h24212,
instr__h24377,
instr__h24576,
instr__h24727,
instr_out___1__h25153,
instr_out___1__h25175,
rs1_val_bypassed370_BITS_31_TO_0_MINUS_rs2_val_ETC__q10,
rs1_val_bypassed370_BITS_31_TO_0_PLUS_rs2_val__ETC__q9,
rs1_val_bypassed370_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8,
rs1_val_bypassed370_BITS_31_TO_0__q7,
tmp__h16612,
v32__h10383,
x__h16555,
x__h16587,
x__h16722,
x__h16767,
x_out_data_to_stage1_instr__h17442;
wire [20 : 0] SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747,
decoded_instr_imm21_UJ__h30483,
stage1_rg_stage_input_BITS_30_TO_10__q2;
wire [19 : 0] imm20__h19795;
wire [12 : 0] SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772,
decoded_instr_imm13_SB__h30481,
stage1_rg_stage_input_BITS_63_TO_51__q1;
wire [11 : 0] decoded_instr_imm12_S__h30480,
imm12__h17694,
imm12__h18031,
imm12__h19667,
imm12__h20336,
imm12__h20551,
imm12__h20747,
imm12__h21084,
imm12__h22705,
imm12__h23057,
offset__h18401,
stage1_rg_stage_input_BITS_75_TO_64__q6,
stage1_rg_stage_input_BITS_87_TO_76__q17;
wire [9 : 0] decoded_instr_funct10__h30478,
nzimm10__h20334,
nzimm10__h20549;
wire [8 : 0] offset__h19032, offset__h22619;
wire [7 : 0] offset__h17566, offset__h22991;
wire [6 : 0] offset__h17973;
wire [5 : 0] imm6__h19665, shamt__h10256;
wire [4 : 0] offset_BITS_4_TO_0___h17962,
offset_BITS_4_TO_0___h18393,
offset_BITS_4_TO_0___h23332,
rd__h18033,
rs1__h18032,
x_out_data_to_stage2_rd__h9892;
wire [3 : 0] alu_outputs___1_exc_code__h10752,
cur_verbosity__h3719,
x_exc_code__h44015,
x_out_trap_info_exc_code__h14913;
wire [2 : 0] rm__h10057;
wire [1 : 0] new_epoch__h26600, sxl__h6710, uxl__h6711;
wire IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2322,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728,
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2344,
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402,
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2589,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347,
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339,
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2295,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2312,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2316,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2339,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2343,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2404,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2462,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2096,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2115,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122,
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1114,
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1136,
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1211,
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1655,
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d2758,
NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875,
NOT_rg_run_on_reset_257_258_OR_imem_rg_pc_BITS_ETC___d2265,
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1167,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1174,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479,
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1179,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d766,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1253,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1259,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1310,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1670,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1674,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2933,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2935,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984,
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753,
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1014,
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1029,
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1078,
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1139,
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d2884,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1229,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1307,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1345,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402,
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707,
_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2485,
csr_regfile_RDY_server_reset_request_put__229__ETC___d2241,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2938,
csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1757,
csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1763,
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573,
gpr_regfile_RDY_server_reset_request_put__226__ETC___d2244,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2119,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261,
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2127,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129,
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_076___d2077,
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2224,
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1134,
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1199,
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1213,
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1645,
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2922,
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2753,
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2779,
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2814,
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817,
rg_state_7_EQ_3_323_AND_stage3_rg_full_8_OR_st_ETC___d2335,
rg_state_7_EQ_5_926_AND_NOT_stageF_rg_full_104_ETC___d2927,
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_104_ETC___d2865,
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1000,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1008,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1327,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1385,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1411,
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2424,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d875,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d884,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d892,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d899,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d926,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d937,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d943,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1045,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1059,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d812,
stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1075,
stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1113,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1351,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d972,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1408,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1598,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2445,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d959,
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1106,
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2376,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1005,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1016,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1017,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1019,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1031,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1032,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1034,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1049,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1050,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1052,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1063,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1064,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1066,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1080,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1081,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1083,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1095,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1096,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1098,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1119,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1120,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1121,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1123,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1141,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1142,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1143,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1145,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1218,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1219,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1220,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1223,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1224,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1225,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1226,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1288,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1342,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1370,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1375,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1378,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1389,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1405,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1565,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2378,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2380,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2382,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2384,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2386,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2392,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296,
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2334,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415,
stageF_f_reset_rsps_i_notEmpty__251_AND_stageD_ETC___d2271,
stageF_rg_full_104_AND_near_mem_imem_valid_AND_ETC___d2136;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// actionvalue method hart0_server_reset_response_get
assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = near_mem$imem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = near_mem$imem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = near_mem$imem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = near_mem$imem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = near_mem$imem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = near_mem$imem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = near_mem$imem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = near_mem$imem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = near_mem$imem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = near_mem$imem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = near_mem$imem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = near_mem$imem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = near_mem$imem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = near_mem$imem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = near_mem$imem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = near_mem$imem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = near_mem$imem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = near_mem$imem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = near_mem$imem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = near_mem$imem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = near_mem$imem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = near_mem$imem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = near_mem$imem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = near_mem$imem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = near_mem$imem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = near_mem$imem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = near_mem$imem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = near_mem$imem_master_rready ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = near_mem$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = near_mem$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = near_mem$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = near_mem$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = near_mem$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = near_mem$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = near_mem$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = near_mem$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = near_mem$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = near_mem$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = near_mem$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = near_mem$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = near_mem$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = near_mem$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = near_mem$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = near_mem$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = near_mem$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = near_mem$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = near_mem$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = near_mem$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = near_mem$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = near_mem$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = near_mem$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = near_mem$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = near_mem$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = near_mem$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = near_mem$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = near_mem$mem_master_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = near_mem$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = near_mem$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = near_mem$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = near_mem$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = near_mem$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = near_mem$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = near_mem$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = near_mem$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = near_mem$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = near_mem$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = near_mem$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = near_mem$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = near_mem$mv_status ;
// submodule csr_regfile
mkCSR_RegFile csr_regfile(.CLK(CLK),
.RST_N(RST_N),
.access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
.access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
.access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
.access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
.access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
.access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
.csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
.csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
.csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
.csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
.csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
.csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
.csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
.csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
.csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
.interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
.m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
.ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags),
.ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs),
.mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
.mav_csr_write_word(csr_regfile$mav_csr_write_word),
.mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
.mv_update_fcsr_fflags_flags(csr_regfile$mv_update_fcsr_fflags_flags),
.mv_update_mstatus_fs_fs(csr_regfile$mv_update_mstatus_fs_fs),
.nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
.read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
.read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
.s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
.software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
.EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
.EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
.EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
.EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags),
.EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs),
.EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
.EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
.EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
.EN_debug(csr_regfile$EN_debug),
.RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
.read_csr(csr_regfile$read_csr),
.read_csr_port2(),
.mav_read_csr(),
.mav_csr_write(),
.read_frm(csr_regfile$read_frm),
.read_fflags(),
.mv_update_fcsr_fflags(),
.mv_update_mstatus_fs(),
.read_misa(csr_regfile$read_misa),
.read_mstatus(csr_regfile$read_mstatus),
.read_sstatus(csr_regfile$read_sstatus),
.read_ustatus(),
.read_satp(csr_regfile$read_satp),
.csr_trap_actions(csr_regfile$csr_trap_actions),
.RDY_csr_trap_actions(),
.csr_ret_actions(csr_regfile$csr_ret_actions),
.RDY_csr_ret_actions(),
.read_csr_minstret(csr_regfile$read_csr_minstret),
.read_csr_mcycle(csr_regfile$read_csr_mcycle),
.read_csr_mtime(),
.access_permitted_1(csr_regfile$access_permitted_1),
.access_permitted_2(csr_regfile$access_permitted_2),
.csr_counter_read_fault(),
.csr_mip_read(),
.interrupt_pending(csr_regfile$interrupt_pending),
.wfi_resume(csr_regfile$wfi_resume),
.nmi_pending(csr_regfile$nmi_pending),
.RDY_debug());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fpr_regfile
mkFPR_RegFile fpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(fpr_regfile$read_rs1_rs1),
.read_rs2_rs2(fpr_regfile$read_rs2_rs2),
.read_rs3_rs3(fpr_regfile$read_rs3_rs3),
.write_rd_rd(fpr_regfile$write_rd_rd),
.write_rd_rd_val(fpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get),
.EN_write_rd(fpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get),
.read_rs1(fpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(fpr_regfile$read_rs2),
.read_rs3(fpr_regfile$read_rs3));
// submodule gpr_regfile
mkGPR_RegFile gpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(gpr_regfile$read_rs1_rs1),
.read_rs2_rs2(gpr_regfile$read_rs2_rs2),
.write_rd_rd(gpr_regfile$write_rd_rd),
.write_rd_rd_val(gpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
.EN_write_rd(gpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
.read_rs1(gpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(gpr_regfile$read_rs2));
// submodule near_mem
mkNear_Mem near_mem(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(near_mem$dma_server_araddr),
.dma_server_arburst(near_mem$dma_server_arburst),
.dma_server_arcache(near_mem$dma_server_arcache),
.dma_server_arid(near_mem$dma_server_arid),
.dma_server_arlen(near_mem$dma_server_arlen),
.dma_server_arlock(near_mem$dma_server_arlock),
.dma_server_arprot(near_mem$dma_server_arprot),
.dma_server_arqos(near_mem$dma_server_arqos),
.dma_server_arregion(near_mem$dma_server_arregion),
.dma_server_arsize(near_mem$dma_server_arsize),
.dma_server_arvalid(near_mem$dma_server_arvalid),
.dma_server_awaddr(near_mem$dma_server_awaddr),
.dma_server_awburst(near_mem$dma_server_awburst),
.dma_server_awcache(near_mem$dma_server_awcache),
.dma_server_awid(near_mem$dma_server_awid),
.dma_server_awlen(near_mem$dma_server_awlen),
.dma_server_awlock(near_mem$dma_server_awlock),
.dma_server_awprot(near_mem$dma_server_awprot),
.dma_server_awqos(near_mem$dma_server_awqos),
.dma_server_awregion(near_mem$dma_server_awregion),
.dma_server_awsize(near_mem$dma_server_awsize),
.dma_server_awvalid(near_mem$dma_server_awvalid),
.dma_server_bready(near_mem$dma_server_bready),
.dma_server_rready(near_mem$dma_server_rready),
.dma_server_wdata(near_mem$dma_server_wdata),
.dma_server_wlast(near_mem$dma_server_wlast),
.dma_server_wstrb(near_mem$dma_server_wstrb),
.dma_server_wvalid(near_mem$dma_server_wvalid),
.dmem_req_addr(near_mem$dmem_req_addr),
.dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
.dmem_req_f3(near_mem$dmem_req_f3),
.dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
.dmem_req_op(near_mem$dmem_req_op),
.dmem_req_priv(near_mem$dmem_req_priv),
.dmem_req_satp(near_mem$dmem_req_satp),
.dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
.dmem_req_store_value(near_mem$dmem_req_store_value),
.imem_master_arready(near_mem$imem_master_arready),
.imem_master_awready(near_mem$imem_master_awready),
.imem_master_bid(near_mem$imem_master_bid),
.imem_master_bresp(near_mem$imem_master_bresp),
.imem_master_bvalid(near_mem$imem_master_bvalid),
.imem_master_rdata(near_mem$imem_master_rdata),
.imem_master_rid(near_mem$imem_master_rid),
.imem_master_rlast(near_mem$imem_master_rlast),
.imem_master_rresp(near_mem$imem_master_rresp),
.imem_master_rvalid(near_mem$imem_master_rvalid),
.imem_master_wready(near_mem$imem_master_wready),
.imem_req_addr(near_mem$imem_req_addr),
.imem_req_f3(near_mem$imem_req_f3),
.imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
.imem_req_priv(near_mem$imem_req_priv),
.imem_req_satp(near_mem$imem_req_satp),
.imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
.mem_master_arready(near_mem$mem_master_arready),
.mem_master_awready(near_mem$mem_master_awready),
.mem_master_bid(near_mem$mem_master_bid),
.mem_master_bresp(near_mem$mem_master_bresp),
.mem_master_bvalid(near_mem$mem_master_bvalid),
.mem_master_rdata(near_mem$mem_master_rdata),
.mem_master_rid(near_mem$mem_master_rid),
.mem_master_rlast(near_mem$mem_master_rlast),
.mem_master_rresp(near_mem$mem_master_rresp),
.mem_master_rvalid(near_mem$mem_master_rvalid),
.mem_master_wready(near_mem$mem_master_wready),
.server_fence_request_put(near_mem$server_fence_request_put),
.set_watch_tohost_tohost_addr(near_mem$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(near_mem$set_watch_tohost_watch_tohost),
.EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
.EN_imem_req(near_mem$EN_imem_req),
.EN_dmem_req(near_mem$EN_dmem_req),
.EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
.EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
.EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
.EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
.EN_sfence_vma_server_request_put(near_mem$EN_sfence_vma_server_request_put),
.EN_sfence_vma_server_response_get(near_mem$EN_sfence_vma_server_response_get),
.EN_set_watch_tohost(near_mem$EN_set_watch_tohost),
.EN_ma_ddr4_ready(near_mem$EN_ma_ddr4_ready),
.RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
.imem_valid(near_mem$imem_valid),
.imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
.imem_pc(near_mem$imem_pc),
.imem_instr(near_mem$imem_instr),
.imem_exc(near_mem$imem_exc),
.imem_exc_code(near_mem$imem_exc_code),
.imem_tval(),
.imem_master_awvalid(near_mem$imem_master_awvalid),
.imem_master_awid(near_mem$imem_master_awid),
.imem_master_awaddr(near_mem$imem_master_awaddr),
.imem_master_awlen(near_mem$imem_master_awlen),
.imem_master_awsize(near_mem$imem_master_awsize),
.imem_master_awburst(near_mem$imem_master_awburst),
.imem_master_awlock(near_mem$imem_master_awlock),
.imem_master_awcache(near_mem$imem_master_awcache),
.imem_master_awprot(near_mem$imem_master_awprot),
.imem_master_awqos(near_mem$imem_master_awqos),
.imem_master_awregion(near_mem$imem_master_awregion),
.imem_master_wvalid(near_mem$imem_master_wvalid),
.imem_master_wdata(near_mem$imem_master_wdata),
.imem_master_wstrb(near_mem$imem_master_wstrb),
.imem_master_wlast(near_mem$imem_master_wlast),
.imem_master_bready(near_mem$imem_master_bready),
.imem_master_arvalid(near_mem$imem_master_arvalid),
.imem_master_arid(near_mem$imem_master_arid),
.imem_master_araddr(near_mem$imem_master_araddr),
.imem_master_arlen(near_mem$imem_master_arlen),
.imem_master_arsize(near_mem$imem_master_arsize),
.imem_master_arburst(near_mem$imem_master_arburst),
.imem_master_arlock(near_mem$imem_master_arlock),
.imem_master_arcache(near_mem$imem_master_arcache),
.imem_master_arprot(near_mem$imem_master_arprot),
.imem_master_arqos(near_mem$imem_master_arqos),
.imem_master_arregion(near_mem$imem_master_arregion),
.imem_master_rready(near_mem$imem_master_rready),
.dmem_valid(near_mem$dmem_valid),
.dmem_word64(near_mem$dmem_word64),
.dmem_st_amo_val(),
.dmem_exc(near_mem$dmem_exc),
.dmem_exc_code(near_mem$dmem_exc_code),
.mem_master_awvalid(near_mem$mem_master_awvalid),
.mem_master_awid(near_mem$mem_master_awid),
.mem_master_awaddr(near_mem$mem_master_awaddr),
.mem_master_awlen(near_mem$mem_master_awlen),
.mem_master_awsize(near_mem$mem_master_awsize),
.mem_master_awburst(near_mem$mem_master_awburst),
.mem_master_awlock(near_mem$mem_master_awlock),
.mem_master_awcache(near_mem$mem_master_awcache),
.mem_master_awprot(near_mem$mem_master_awprot),
.mem_master_awqos(near_mem$mem_master_awqos),
.mem_master_awregion(near_mem$mem_master_awregion),
.mem_master_wvalid(near_mem$mem_master_wvalid),
.mem_master_wdata(near_mem$mem_master_wdata),
.mem_master_wstrb(near_mem$mem_master_wstrb),
.mem_master_wlast(near_mem$mem_master_wlast),
.mem_master_bready(near_mem$mem_master_bready),
.mem_master_arvalid(near_mem$mem_master_arvalid),
.mem_master_arid(near_mem$mem_master_arid),
.mem_master_araddr(near_mem$mem_master_araddr),
.mem_master_arlen(near_mem$mem_master_arlen),
.mem_master_arsize(near_mem$mem_master_arsize),
.mem_master_arburst(near_mem$mem_master_arburst),
.mem_master_arlock(near_mem$mem_master_arlock),
.mem_master_arcache(near_mem$mem_master_arcache),
.mem_master_arprot(near_mem$mem_master_arprot),
.mem_master_arqos(near_mem$mem_master_arqos),
.mem_master_arregion(near_mem$mem_master_arregion),
.mem_master_rready(near_mem$mem_master_rready),
.RDY_server_fence_i_request_put(),
.RDY_server_fence_i_response_get(),
.RDY_server_fence_request_put(),
.RDY_server_fence_response_get(),
.RDY_sfence_vma_server_request_put(),
.RDY_sfence_vma_server_response_get(),
.dma_server_awready(near_mem$dma_server_awready),
.dma_server_wready(near_mem$dma_server_wready),
.dma_server_bvalid(near_mem$dma_server_bvalid),
.dma_server_bid(near_mem$dma_server_bid),
.dma_server_bresp(near_mem$dma_server_bresp),
.dma_server_arready(near_mem$dma_server_arready),
.dma_server_rvalid(near_mem$dma_server_rvalid),
.dma_server_rid(near_mem$dma_server_rid),
.dma_server_rdata(near_mem$dma_server_rdata),
.dma_server_rresp(near_mem$dma_server_rresp),
.dma_server_rlast(near_mem$dma_server_rlast),
.RDY_set_watch_tohost(),
.mv_tohost_value(near_mem$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(near_mem$mv_status));
// submodule stage1_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage1_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_reqs$ENQ),
.DEQ(stage1_f_reset_reqs$DEQ),
.CLR(stage1_f_reset_reqs$CLR),
.FULL_N(stage1_f_reset_reqs$FULL_N),
.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));
// submodule stage1_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage1_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_rsps$ENQ),
.DEQ(stage1_f_reset_rsps$DEQ),
.CLR(stage1_f_reset_rsps$CLR),
.FULL_N(stage1_f_reset_rsps$FULL_N),
.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));
// submodule stage2_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage2_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_reqs$ENQ),
.DEQ(stage2_f_reset_reqs$DEQ),
.CLR(stage2_f_reset_reqs$CLR),
.FULL_N(stage2_f_reset_reqs$FULL_N),
.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));
// submodule stage2_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage2_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_rsps$ENQ),
.DEQ(stage2_f_reset_rsps$DEQ),
.CLR(stage2_f_reset_rsps$CLR),
.FULL_N(stage2_f_reset_rsps$FULL_N),
.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));
// submodule stage2_fbox
mkFBox_Top stage2_fbox(.verbosity(4'd0),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(stage2_fbox$req_f7),
.req_opcode(stage2_fbox$req_opcode),
.req_rm(stage2_fbox$req_rm),
.req_rs2(stage2_fbox$req_rs2),
.req_v1(stage2_fbox$req_v1),
.req_v2(stage2_fbox$req_v2),
.req_v3(stage2_fbox$req_v3),
.EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put),
.EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get),
.EN_req(stage2_fbox$EN_req),
.RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put),
.RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get),
.valid(stage2_fbox$valid),
.word_fst(stage2_fbox$word_fst),
.word_snd(stage2_fbox$word_snd));
// submodule stage2_mbox
mkRISCV_MBox stage2_mbox(.CLK(CLK),
.RST_N(RST_N),
.req_f3(stage2_mbox$req_f3),
.req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
.req_v1(stage2_mbox$req_v1),
.req_v2(stage2_mbox$req_v2),
.set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
.EN_set_verbosity(stage2_mbox$EN_set_verbosity),
.EN_req_reset(stage2_mbox$EN_req_reset),
.EN_rsp_reset(stage2_mbox$EN_rsp_reset),
.EN_req(stage2_mbox$EN_req),
.RDY_set_verbosity(),
.RDY_req_reset(),
.RDY_rsp_reset(),
.valid(stage2_mbox$valid),
.word(stage2_mbox$word));
// submodule stage3_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage3_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_reqs$ENQ),
.DEQ(stage3_f_reset_reqs$DEQ),
.CLR(stage3_f_reset_reqs$CLR),
.FULL_N(stage3_f_reset_reqs$FULL_N),
.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));
// submodule stage3_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage3_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_rsps$ENQ),
.DEQ(stage3_f_reset_rsps$DEQ),
.CLR(stage3_f_reset_rsps$CLR),
.FULL_N(stage3_f_reset_rsps$FULL_N),
.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));
// submodule stageD_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageD_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_reqs$ENQ),
.DEQ(stageD_f_reset_reqs$DEQ),
.CLR(stageD_f_reset_reqs$CLR),
.FULL_N(stageD_f_reset_reqs$FULL_N),
.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));
// submodule stageD_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageD_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_rsps$ENQ),
.DEQ(stageD_f_reset_rsps$DEQ),
.CLR(stageD_f_reset_rsps$CLR),
.FULL_N(stageD_f_reset_rsps$FULL_N),
.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));
// submodule stageF_branch_predictor
mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
.RST_N(RST_N),
.bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
.bp_train_instr(stageF_branch_predictor$bp_train_instr),
.bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
.bp_train_pc(stageF_branch_predictor$bp_train_pc),
.predict_req_pc(stageF_branch_predictor$predict_req_pc),
.predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
.predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
.EN_reset(stageF_branch_predictor$EN_reset),
.EN_predict_req(stageF_branch_predictor$EN_predict_req),
.EN_bp_train(stageF_branch_predictor$EN_bp_train),
.RDY_reset(),
.RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
.predict_rsp(stageF_branch_predictor$predict_rsp),
.RDY_bp_train());
// submodule stageF_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageF_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_reqs$ENQ),
.DEQ(stageF_f_reset_reqs$DEQ),
.CLR(stageF_f_reset_reqs$CLR),
.FULL_N(stageF_f_reset_reqs$FULL_N),
.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));
// submodule stageF_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageF_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_rsps$ENQ),
.DEQ(stageF_f_reset_rsps$DEQ),
.CLR(stageF_f_reset_rsps$CLR),
.FULL_N(stageF_f_reset_rsps$FULL_N),
.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));
// rule RL_rl_show_pipe
assign CAN_FIRE_RL_rl_show_pipe =
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
rg_state != 4'd0 &&
rg_state != 4'd1 &&
rg_state != 4'd12 ;
assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;
// rule RL_rl_stage2_nonpipe
assign CAN_FIRE_RL_rl_stage2_nonpipe =
rg_state == 4'd3 && !stage3_rg_full && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 ;
assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;
// rule RL_rl_stage1_trap
assign CAN_FIRE_RL_rl_stage1_trap =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2779 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;
// rule RL_rl_trap
assign CAN_FIRE_RL_rl_trap =
rg_state == 4'd4 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;
// rule RL_rl_stage1_CSRR_W
assign CAN_FIRE_RL_rl_stage1_CSRR_W =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1014 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W = CAN_FIRE_RL_rl_stage1_CSRR_W ;
// rule RL_rl_stage1_CSRR_W_2
assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
// rule RL_rl_stage1_CSRR_S_or_C
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1029 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C =
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C ;
// rule RL_rl_stage1_CSRR_S_or_C_2
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
// rule RL_rl_stage1_restart_after_csrrx
assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_104_ETC___d2865 ;
assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;
// rule RL_rl_stage1_xRET
assign CAN_FIRE_RL_rl_stage1_xRET =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340 &&
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;
// rule RL_rl_stage1_FENCE_I
assign CAN_FIRE_RL_rl_stage1_FENCE_I =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1059 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_FENCE_I = CAN_FIRE_RL_rl_stage1_FENCE_I ;
// rule RL_rl_finish_FENCE_I
assign CAN_FIRE_RL_rl_finish_FENCE_I =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;
// rule RL_rl_stage1_FENCE
assign CAN_FIRE_RL_rl_stage1_FENCE =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1045 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ;
// rule RL_rl_finish_FENCE
assign CAN_FIRE_RL_rl_finish_FENCE =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;
// rule RL_rl_stage1_SFENCE_VMA
assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1078 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA =
CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;
// rule RL_rl_finish_SFENCE_VMA
assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
// rule RL_rl_stage1_WFI
assign CAN_FIRE_RL_rl_stage1_WFI =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1139 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;
// rule RL_rl_WFI_resume
assign CAN_FIRE_RL_rl_WFI_resume =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2922 ;
assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_reset_from_WFI
assign CAN_FIRE_RL_rl_reset_from_WFI =
rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_from_WFI =
CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_trap_fetch
assign CAN_FIRE_RL_rl_trap_fetch =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_5_926_AND_NOT_stageF_rg_full_104_ETC___d2927 ;
assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;
// rule RL_rl_stage1_interrupt
assign CAN_FIRE_RL_rl_stage1_interrupt =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2938 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;
// rule RL_imem_rl_assert_fail
assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete =
gpr_regfile$RDY_server_reset_response_get &&
fpr_regfile$RDY_server_reset_response_get &&
near_mem$RDY_server_reset_response_get &&
csr_regfile$RDY_server_reset_response_get &&
stageF_f_reset_rsps_i_notEmpty__251_AND_stageD_ETC___d2271 &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_pipe
assign CAN_FIRE_RL_rl_pipe =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2322 &&
rg_state_7_EQ_3_323_AND_stage3_rg_full_8_OR_st_ETC___d2335 &&
(NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2343 ||
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2344 ||
stage2_rg_full ||
stage3_rg_full) ;
assign WILL_FIRE_RL_rl_pipe = MUX_rg_state$write_1__PSEL_1 ;
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start =
gpr_regfile_RDY_server_reset_request_put__226__ETC___d2244 &&
rg_state == 4'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_imem_rl_fetch_next_32b
assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
imem_rg_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
CAN_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_stage3_rl_reset
assign CAN_FIRE_RL_stage3_rl_reset =
stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;
// rule RL_stage2_rl_reset_end
assign CAN_FIRE_RL_stage2_rl_reset_end =
stage2_fbox$RDY_server_reset_response_get &&
stage2_f_reset_rsps$FULL_N &&
stage2_rg_resetting ;
assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;
// rule RL_stage2_rl_reset_begin
assign CAN_FIRE_RL_stage2_rl_reset_begin =
stage2_fbox$RDY_server_reset_request_put &&
stage2_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_stage2_rl_reset_begin =
CAN_FIRE_RL_stage2_rl_reset_begin ;
// rule RL_stage1_rl_reset
assign CAN_FIRE_RL_stage1_rl_reset =
stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;
// rule RL_stageD_rl_reset
assign CAN_FIRE_RL_stageD_rl_reset =
stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;
// rule RL_stageF_rl_reset
assign CAN_FIRE_RL_stageF_rl_reset =
stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ;
assign MUX_gpr_regfile$write_rd_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
assign MUX_imem_rg_cache_addr$write_1__SEL_1 =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
assign MUX_imem_rg_cache_addr$write_1__SEL_2 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ;
assign MUX_imem_rg_cache_b16$write_1__PSEL_1 =
WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign MUX_rg_next_pc$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ;
assign MUX_rg_next_pc$write_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign MUX_rg_state$write_1__PSEL_1 =
CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2316 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_complete &&
!WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_8 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
assign MUX_rg_state$write_1__SEL_9 =
WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
assign MUX_rg_trap_info$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_trap_instr$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ;
assign MUX_rg_trap_interrupt$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
always@(rg_trap_instr or
csr_regfile$read_csr or
y__h35332 or
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b110:
MUX_csr_regfile$mav_csr_write_2__VAL_2 =
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856;
default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
csr_regfile$read_csr[63:0] & y__h35332;
endcase
end
assign MUX_imem_rg_cache_addr$write_1__VAL_1 =
(near_mem$imem_valid && !near_mem$imem_exc) ?
near_mem$imem_pc :
64'h0000000000000001 ;
assign MUX_imem_rg_cache_addr$write_1__VAL_2 =
near_mem$imem_exc ? 64'h0000000000000001 : near_mem$imem_pc ;
assign MUX_imem_rg_tval$write_1__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32186 :
stageF_branch_predictor$predict_rsp ;
assign MUX_imem_rg_tval$write_1__VAL_3 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h43719 :
rg_next_pc ;
assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 64'd4 ;
assign MUX_near_mem$imem_req_2__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32186 :
addr_of_b32__h32058 ;
assign MUX_near_mem$imem_req_2__VAL_4 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h43719 :
addr_of_b32__h43591 ;
assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
assign MUX_rg_state$write_1__VAL_3 =
csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_4 =
csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
assign MUX_rg_trap_info$write_1__VAL_1 =
{ stage1_rg_stage_input[401:338],
4'd2,
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h14908 } ;
assign MUX_rg_trap_info$write_1__VAL_2 =
{ value__h8443,
near_mem$dmem_exc_code,
stage2_rg_stage2[389:326] } ;
assign MUX_rg_trap_info$write_1__VAL_3 =
{ stage1_rg_stage_input[401:338],
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:264] :
{ alu_outputs_exc_code__h11528, trap_info_tval__h14908 } } ;
assign MUX_rg_trap_info$write_1__VAL_4 =
{ stage1_rg_stage_input[401:338], x_exc_code__h44015, 64'd0 } ;
assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[263:232] ;
assign MUX_stage1_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 ;
assign MUX_stage2_rg_full$write_1__VAL_2 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full) :
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign MUX_stage3_rg_full$write_1__VAL_2 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) ;
assign MUX_stageD_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307 &&
stageD_rg_full ;
assign MUX_stageF_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ?
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307 &&
stageD_rg_full :
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307 &&
stageD_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122) &&
stageF_rg_full ;
// register cfg_logdelay
assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
assign cfg_logdelay$EN = EN_set_verbosity ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register imem_rg_cache_addr
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_cache_addr$write_1__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
near_mem$imem_pc or MUX_imem_rg_cache_b16$write_1__PSEL_1)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_cache_addr$D_IN = near_mem$imem_pc;
MUX_imem_rg_cache_b16$write_1__PSEL_1:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
default: imem_rg_cache_addr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_cache_addr$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_cache_b16
assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
assign imem_rg_cache_b16$EN =
MUX_imem_rg_cache_b16$write_1__PSEL_1 && near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
!near_mem$imem_exc ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_f3
assign imem_rg_f3$D_IN = 3'b010 ;
assign imem_rg_f3$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_mstatus_MXR
assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign imem_rg_mstatus_MXR$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_pc
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1: imem_rg_pc$D_IN = 64'd4096;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
MUX_imem_rg_cache_b16$write_1__PSEL_1: imem_rg_pc$D_IN = rg_next_pc;
default: imem_rg_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_pc$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_priv
assign imem_rg_priv$D_IN = rg_cur_priv ;
assign imem_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_satp
assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
assign imem_rg_satp$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_sstatus_SUM
assign imem_rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign imem_rg_sstatus_SUM$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_tval
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_tval$write_1__VAL_2 or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or
MUX_imem_rg_tval$write_1__VAL_3 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1: imem_rg_tval$D_IN = 64'd4096;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_2;
MUX_imem_rg_cache_b16$write_1__PSEL_1:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_3;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
default: imem_rg_tval$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_tval$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register rg_csr_pc
assign rg_csr_pc$D_IN = stage1_rg_stage_input[401:338] ;
assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_csr_val1
assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h9894 ;
assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_cur_priv
always@(WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or
csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_trap:
rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
WILL_FIRE_RL_rl_stage1_xRET:
rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64];
WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_cur_priv$EN =
WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_epoch
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26600 or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or
WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
rg_epoch$D_IN = new_epoch__h26600;
MUX_imem_rg_cache_b16$write_1__PSEL_1:
rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_next_pc
always@(MUX_rg_next_pc$write_1__SEL_1 or
x_out_next_pc__h9637 or
MUX_rg_next_pc$write_1__SEL_2 or
WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h9637;
MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h9637;
WILL_FIRE_RL_rl_trap:
rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130];
WILL_FIRE_RL_rl_stage1_xRET:
rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66];
default: rg_next_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_next_pc$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_xRET ;
// register rg_run_on_reset
assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_start_CPI_cycles
assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
assign rg_start_CPI_cycles$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_start_CPI_instrs
assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
assign rg_start_CPI_instrs$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_state
always@(WILL_FIRE_RL_rl_reset_complete or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_reset_from_WFI or
WILL_FIRE_RL_rl_reset_start or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or
MUX_rg_state$write_1__SEL_8 or
MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_9 or
WILL_FIRE_RL_rl_stage1_CSRR_W or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
WILL_FIRE_RL_rl_stage1_FENCE_I or
WILL_FIRE_RL_rl_stage1_FENCE or
WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_reset_complete:
rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_CSRR_W_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
MUX_imem_rg_cache_b16$write_1__PSEL_1: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
rg_state$D_IN = 4'd5;
WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2316 ||
WILL_FIRE_RL_rl_reset_complete ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
WILL_FIRE_RL_rl_reset_from_WFI ||
WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_stage1_WFI ;
// register rg_trap_info
always@(MUX_rg_trap_info$write_1__SEL_1 or
MUX_rg_trap_info$write_1__VAL_1 or
WILL_FIRE_RL_rl_stage2_nonpipe or
MUX_rg_trap_info$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_trap or
MUX_rg_trap_info$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_trap_info$write_1__SEL_1:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
WILL_FIRE_RL_rl_stage2_nonpipe:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_trap:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_interrupt:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
default: rg_trap_info$D_IN =
132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_trap_info$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register rg_trap_instr
assign rg_trap_instr$D_IN =
MUX_rg_trap_instr$write_1__SEL_1 ?
stage1_rg_stage_input[263:232] :
stage2_rg_stage2[429:398] ;
assign rg_trap_instr$EN =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
// register rg_trap_interrupt
assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
assign rg_trap_interrupt$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register stage1_rg_full
always@(WILL_FIRE_RL_stage1_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage1_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stage1_rg_full$D_IN = 1'd0;
default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage1_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage1_rl_reset ;
// register stage1_rg_stage_input
assign stage1_rg_stage_input$D_IN =
{ stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168],
stageD_rg_data[165:96],
_theResult____h5654,
stageD_rg_data[79:0],
_theResult____h5654[6:0],
_theResult____h5654[11:7],
_theResult____h5654[19:15],
_theResult____h5654[24:20],
_theResult____h5654[31:27],
_theResult____h5654[31:20],
_theResult____h5654[14:12],
_theResult____h5654[31:27],
_theResult____h5654[31:25],
decoded_instr_funct10__h30478,
_theResult____h5654[31:20],
decoded_instr_imm12_S__h30480,
decoded_instr_imm13_SB__h30481,
_theResult____h5654[31:12],
decoded_instr_imm21_UJ__h30483,
_theResult____h5654[27:20],
_theResult____h5654[26:25] } ;
assign stage1_rg_stage_input$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ;
// register stage2_rg_full
always@(WILL_FIRE_RL_stage2_rl_reset_begin or
WILL_FIRE_RL_rl_pipe or
MUX_stage2_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
stage2_rg_full$D_IN = 1'd0;
default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage2_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_resetting
assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_rg_resetting$EN =
WILL_FIRE_RL_stage2_rl_reset_end ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_stage2
assign stage2_rg_stage2$D_IN =
{ rg_cur_priv,
stage1_rg_stage_input[401:338],
IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 } ;
assign stage2_rg_stage2$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2404 ;
// register stage3_rg_full
always@(WILL_FIRE_RL_stage3_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage3_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage3_rg_full$D_IN = MUX_stage3_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage3_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stage3_rl_reset ;
// register stage3_rg_stage3
assign stage3_rg_stage3$D_IN =
{ stage2_rg_stage2[493:398],
stage2_rg_stage2[495:494],
1'd1,
x_out_data_to_stage3_rd__h8113,
x_out_data_to_stage3_rd_val__h8114,
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3,
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
x_out_data_to_stage3_fpr_flags__h8117,
x_out_data_to_stage3_frd_val__h8118 } ;
assign stage3_rg_stage3$EN =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) ;
// register stageD_rg_data
assign stageD_rg_data$D_IN =
{ imem_rg_pc,
stageF_rg_epoch,
stageF_rg_priv,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11,
near_mem$imem_exc,
near_mem$imem_exc_code,
imem_rg_tval,
d_instr__h25151,
stageF_branch_predictor$predict_rsp } ;
assign stageD_rg_data$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// register stageD_rg_full
always@(WILL_FIRE_RL_stageD_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageD_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stageD_rg_full$D_IN = 1'd0;
default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageD_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stageD_rl_reset ;
// register stageF_rg_epoch
always@(WILL_FIRE_RL_stageF_rl_reset or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_rg_epoch or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26600 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_rg_epoch$D_IN = stageF_rg_epoch;
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_finish_SFENCE_VMA:
stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h26600;
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_epoch$D_IN = new_epoch__h26600;
default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stageF_rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_stageF_rl_reset ;
// register stageF_rg_full
always@(WILL_FIRE_RL_stageF_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageF_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_full$D_IN = 1'd1;
default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageF_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stageF_rl_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register stageF_rg_priv
assign stageF_rg_priv$D_IN = rg_cur_priv ;
assign stageF_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// submodule csr_regfile
assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_2_read_not_write =
rs1_val__h35054 == 64'd0 ;
assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
assign csr_regfile$csr_ret_actions_from_priv =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d2884) ?
2'b11 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ?
2'b01 :
2'b0) ;
assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[67:64] ;
assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
assign csr_regfile$csr_trap_actions_interrupt =
rg_trap_interrupt && !csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_nmi =
rg_trap_interrupt && csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_pc = rg_trap_info[131:68] ;
assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[63:0] ;
assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
assign csr_regfile$m_external_interrupt_req_set_not_clear =
m_external_interrupt_req_set_not_clear ;
assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ;
assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ;
assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$mav_csr_write_word =
MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
rs1_val__h34220 :
MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
assign csr_regfile$mv_update_fcsr_fflags_flags = 5'h0 ;
assign csr_regfile$mv_update_mstatus_fs_fs = 2'h0 ;
assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
assign csr_regfile$s_external_interrupt_req_set_not_clear =
s_external_interrupt_req_set_not_clear ;
assign csr_regfile$software_interrupt_req_set_not_clear =
software_interrupt_req_set_not_clear ;
assign csr_regfile$timer_interrupt_req_set_not_clear =
timer_interrupt_req_set_not_clear ;
assign csr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign csr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign csr_regfile$EN_mav_read_csr = 1'b0 ;
assign csr_regfile$EN_mav_csr_write =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
rg_trap_instr[19:15] != 5'd0 ;
assign csr_regfile$EN_ma_update_fcsr_fflags =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[70] ;
assign csr_regfile$EN_ma_update_mstatus_fs =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
(stage3_rg_stage3[70] || stage3_rg_stage3[69]) ;
assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_csr_minstret_incr =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_debug = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ =
gpr_regfile_RDY_server_reset_request_put__226__ETC___d2244 &&
rg_state == 4'd0 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = rg_run_on_reset ;
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fpr_regfile
assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign fpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign fpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign fpr_regfile$read_rs3_rs3 = stage1_rg_stage_input[129:125] ;
assign fpr_regfile$write_rd_rd = stage3_rg_stage3[139:135] ;
assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ;
assign fpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign fpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign fpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[69] ;
// submodule gpr_regfile
assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign gpr_regfile$write_rd_rd =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
rg_trap_instr[11:7] :
stage3_rg_stage3[139:135] ;
assign gpr_regfile$write_rd_rd_val =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
csr_regfile$read_csr[63:0] :
stage3_rg_stage3[134:71] ;
assign gpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign gpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign gpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
!stage3_rg_stage3[69] ;
// submodule near_mem
assign near_mem$dma_server_araddr = dma_server_araddr ;
assign near_mem$dma_server_arburst = dma_server_arburst ;
assign near_mem$dma_server_arcache = dma_server_arcache ;
assign near_mem$dma_server_arid = dma_server_arid ;
assign near_mem$dma_server_arlen = dma_server_arlen ;
assign near_mem$dma_server_arlock = dma_server_arlock ;
assign near_mem$dma_server_arprot = dma_server_arprot ;
assign near_mem$dma_server_arqos = dma_server_arqos ;
assign near_mem$dma_server_arregion = dma_server_arregion ;
assign near_mem$dma_server_arsize = dma_server_arsize ;
assign near_mem$dma_server_arvalid = dma_server_arvalid ;
assign near_mem$dma_server_awaddr = dma_server_awaddr ;
assign near_mem$dma_server_awburst = dma_server_awburst ;
assign near_mem$dma_server_awcache = dma_server_awcache ;
assign near_mem$dma_server_awid = dma_server_awid ;
assign near_mem$dma_server_awlen = dma_server_awlen ;
assign near_mem$dma_server_awlock = dma_server_awlock ;
assign near_mem$dma_server_awprot = dma_server_awprot ;
assign near_mem$dma_server_awqos = dma_server_awqos ;
assign near_mem$dma_server_awregion = dma_server_awregion ;
assign near_mem$dma_server_awsize = dma_server_awsize ;
assign near_mem$dma_server_awvalid = dma_server_awvalid ;
assign near_mem$dma_server_bready = dma_server_bready ;
assign near_mem$dma_server_rready = dma_server_rready ;
assign near_mem$dma_server_wdata = dma_server_wdata ;
assign near_mem$dma_server_wlast = dma_server_wlast ;
assign near_mem$dma_server_wstrb = dma_server_wstrb ;
assign near_mem$dma_server_wvalid = dma_server_wvalid ;
assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h9893 ;
assign near_mem$dmem_req_amo_funct7 =
x_out_data_to_stage2_val1__h9894[6:0] ;
assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
assign near_mem$dmem_req_op =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111)) ?
2'd0 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111)) ?
2'd1 :
2'd2) ;
assign near_mem$dmem_req_priv =
csr_regfile$read_mstatus[17] ?
csr_regfile$read_mstatus[12:11] :
rg_cur_priv ;
assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ;
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1541 or
alu_outputs___1_fval2__h10474 or branch_target__h10074)
begin
case (stage1_rg_stage_input[151:145])
7'b0100111:
near_mem$dmem_req_store_value = alu_outputs___1_fval2__h10474;
7'b1100011: near_mem$dmem_req_store_value = branch_target__h10074;
default: near_mem$dmem_req_store_value =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1541;
endcase
end
assign near_mem$imem_master_arready = imem_master_arready ;
assign near_mem$imem_master_awready = imem_master_awready ;
assign near_mem$imem_master_bid = imem_master_bid ;
assign near_mem$imem_master_bresp = imem_master_bresp ;
assign near_mem$imem_master_bvalid = imem_master_bvalid ;
assign near_mem$imem_master_rdata = imem_master_rdata ;
assign near_mem$imem_master_rid = imem_master_rid ;
assign near_mem$imem_master_rlast = imem_master_rlast ;
assign near_mem$imem_master_rresp = imem_master_rresp ;
assign near_mem$imem_master_rvalid = imem_master_rvalid ;
assign near_mem$imem_master_wready = imem_master_wready ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_near_mem$imem_req_2__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4 or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or
MUX_near_mem$imem_req_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
near_mem$imem_req_addr = 64'd4096;
MUX_imem_rg_cache_addr$write_1__SEL_2:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
MUX_imem_rg_cache_b16$write_1__PSEL_1:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
default: near_mem$imem_req_addr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign near_mem$imem_req_f3 =
WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
assign near_mem$imem_req_mstatus_MXR =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_imem_rg_cache_b16$write_1__PSEL_1) ?
csr_regfile$read_mstatus[19] :
imem_rg_mstatus_MXR ;
assign near_mem$imem_req_priv =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_imem_rg_cache_b16$write_1__PSEL_1) ?
rg_cur_priv :
imem_rg_priv ;
assign near_mem$imem_req_satp =
WILL_FIRE_RL_imem_rl_fetch_next_32b ?
imem_rg_satp :
csr_regfile$read_satp ;
assign near_mem$imem_req_sstatus_SUM =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_imem_rg_cache_b16$write_1__PSEL_1) ?
csr_regfile$read_sstatus[18] :
imem_rg_sstatus_SUM ;
assign near_mem$mem_master_arready = mem_master_arready ;
assign near_mem$mem_master_awready = mem_master_awready ;
assign near_mem$mem_master_bid = mem_master_bid ;
assign near_mem$mem_master_bresp = mem_master_bresp ;
assign near_mem$mem_master_bvalid = mem_master_bvalid ;
assign near_mem$mem_master_rdata = mem_master_rdata ;
assign near_mem$mem_master_rid = mem_master_rid ;
assign near_mem$mem_master_rlast = mem_master_rlast ;
assign near_mem$mem_master_rresp = mem_master_rresp ;
assign near_mem$mem_master_rvalid = mem_master_rvalid ;
assign near_mem$mem_master_wready = mem_master_wready ;
assign near_mem$server_fence_request_put =
8'b10101010 /* unspecified value */ ;
assign near_mem$set_watch_tohost_tohost_addr =
set_watch_tohost_tohost_addr ;
assign near_mem$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign near_mem$EN_imem_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign near_mem$EN_dmem_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 ;
assign near_mem$EN_server_fence_i_request_put =
CAN_FIRE_RL_rl_stage1_FENCE_I ;
assign near_mem$EN_server_fence_i_response_get =
CAN_FIRE_RL_rl_finish_FENCE_I ;
assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ;
assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
assign near_mem$EN_sfence_vma_server_request_put =
CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign near_mem$EN_sfence_vma_server_response_get =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
assign near_mem$EN_set_watch_tohost = EN_set_watch_tohost ;
assign near_mem$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule stage1_f_reset_reqs
assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_reqs$CLR = 1'b0 ;
// submodule stage1_f_reset_rsps
assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage1_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_f_reset_reqs
assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_f_reset_reqs$CLR = 1'b0 ;
// submodule stage2_f_reset_rsps
assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage2_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_fbox
assign stage2_fbox$req_f7 = MUX_rg_trap_instr$write_1__VAL_1[31:25] ;
assign stage2_fbox$req_opcode = MUX_rg_trap_instr$write_1__VAL_1[6:0] ;
assign stage2_fbox$req_rm = rm__h10057 ;
assign stage2_fbox$req_rs2 = MUX_rg_trap_instr$write_1__VAL_1[24:20] ;
assign stage2_fbox$req_v1 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 ?
x_out_data_to_stage2_val1__h9894 :
x_out_data_to_stage2_fval1__h9896 ;
assign stage2_fbox$req_v2 = alu_outputs___1_fval2__h10474 ;
assign stage2_fbox$req_v3 = x_out_data_to_stage2_fval3__h9898 ;
assign stage2_fbox$EN_server_reset_request_put =
CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_fbox$EN_server_reset_response_get =
CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_fbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 ;
// submodule stage2_mbox
assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign stage2_mbox$req_is_OP_not_OP_32 =
!MUX_rg_trap_instr$write_1__VAL_1[3] ;
assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h9894 ;
assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h9895 ;
assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
assign stage2_mbox$EN_set_verbosity = 1'b0 ;
assign stage2_mbox$EN_req_reset = 1'b0 ;
assign stage2_mbox$EN_rsp_reset = 1'b0 ;
assign stage2_mbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 ;
// submodule stage3_f_reset_reqs
assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_reqs$CLR = 1'b0 ;
// submodule stage3_f_reset_rsps
assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage3_f_reset_rsps$CLR = 1'b0 ;
// submodule stageD_f_reset_reqs
assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_reqs$CLR = 1'b0 ;
// submodule stageD_f_reset_rsps
assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageD_f_reset_rsps$CLR = 1'b0 ;
// submodule stageF_branch_predictor
assign stageF_branch_predictor$bp_train_cf_info =
(stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) ?
{ CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
x_out_cf_info_fallthru_PC__h16065,
alu_outputs_cf_info_taken_PC__h16058 } :
195'h6AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign stageF_branch_predictor$bp_train_instr = d_instr__h25151 ;
assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_imem_rg_cache_b16$write_1__PSEL_1 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_branch_predictor$predict_req_pc = 64'd4096;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_branch_predictor$predict_req_pc =
stageF_branch_predictor$predict_rsp;
MUX_imem_rg_cache_b16$write_1__PSEL_1:
stageF_branch_predictor$predict_req_pc = rg_next_pc;
default: stageF_branch_predictor$predict_req_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign stageF_branch_predictor$predict_rsp_instr = d_instr__h25151 ;
assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$EN_reset = 1'b0 ;
assign stageF_branch_predictor$EN_predict_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign stageF_branch_predictor$EN_bp_train =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// submodule stageF_f_reset_reqs
assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_reqs$CLR = 1'b0 ;
// submodule stageF_f_reset_rsps
assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageF_f_reset_rsps$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 =
next_pc__h9620 == stage1_rg_stage_input[215:152] ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122) :
stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2307 &&
stageD_rg_full ||
!stageF_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2322 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 ||
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2316 ||
(imem_rg_pc[1:0] == 2'b0 || near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303 ?
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129 :
!stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 ||
!stageD_rg_full) &&
stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2344 :
stage1_rg_full ;
assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2099 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2096 ?
{ 16'b0,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ?
near_mem$imem_instr[31:16] :
imem_rg_cache_b16 } :
near_mem$imem_instr ;
assign IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2344 =
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122) ;
assign IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 =
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129 ;
assign IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2589 =
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 =
x_out_fbypass_rd__h9226 == stage1_rg_stage_input[139:135] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 =
x_out_fbypass_rd__h9226 == stage1_rg_stage_input[134:130] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 =
x_out_fbypass_rd__h9226 == stage1_rg_stage_input[129:125] ;
assign IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856 =
csr_regfile$read_csr[63:0] | rs1_val__h35054 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1940 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b001) ?
instr__h24576 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24727 :
32'h0) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1941 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24377 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1940 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1942 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b001 &&
csr_regfile$read_misa[3]) ?
instr__h24212 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1941 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1943 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b011 &&
csr_regfile$read_misa[5]) ?
instr__h23412 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1942 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1944 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h23207 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1943 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1945 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h23056 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1944 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1946 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h22857 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1945 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1948 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] == 5'd0 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h22608 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h22704 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1946) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1950 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22312 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22450 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1948) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1952 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22038 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22174 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1950) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1954 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b11) ?
instr__h21766 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b10) ?
instr__h21902 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1952) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1955 =
(csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1763 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21671 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1954 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1956 =
(csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1757 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21552 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1955 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1958 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b01 &&
imm6__h19665 != 6'd0) ?
instr__h21257 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b10) ?
instr__h21374 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1956) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1959 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b0 &&
imm6__h19665 != 6'd0) ?
instr__h21068 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1958 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1960 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19665 != 6'd0) ?
instr__h20879 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1959 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1962 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] == 5'd2 &&
nzimm10__h20334 != 10'd0) ?
instr__h20538 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b0 &&
nzimm10__h20549 != 10'd0) ?
instr__h20710 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1960) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1964 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19665 != 6'd0 ||
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] == 5'd0 &&
imm6__h19665 == 6'd0) ?
instr__h20056 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b001 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h20283 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1962) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1965 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[75:71] != 5'd2 &&
imm6__h19665 != 6'd0) ?
instr__h19927 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1964 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1967 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h19405 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b010 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h19743 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1965) ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1968 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h19088 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1967 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1969 =
(csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1763 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h19023 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1968 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1970 =
(csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1757 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h18907 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1969 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1971 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h18454 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1970 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1972 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h18225 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1971 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1973 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h18030 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1972 ;
assign IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1974 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h17838 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1973 ;
assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2100 =
(imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11) ?
instr_out___1__h25175 :
IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2099 ;
assign IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d2884 ||
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ;
assign IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1179 &&
(stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] == 12'b0 ||
stage1_rg_stage_input[87:76] == 12'b000000000001 ||
(rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d2758) :
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270 =
rs1_val_bypassed__h5370 +
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_057___d1269 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 =
rs1_val_bypassed__h5370 == rs2_val_bypassed__h5376 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423 =
(rs1_val_bypassed__h5370 ^ 64'h8000000000000000) <
(rs2_val_bypassed__h5376 ^ 64'h8000000000000000) ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 =
rs1_val_bypassed__h5370 < rs2_val_bypassed__h5376 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270[31:0] ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
alu_outputs___1_val1__h10269 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1532 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800) ?
rs1_val_bypassed__h5370 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1541 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800) ?
rs2_val_bypassed__h5376 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d766 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
(stage1_rg_stage_input[151:145] != 7'b1100111 ||
stage1_rg_stage_input[112:110] != 3'd0) ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d972 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 &&
stage1_rg_stage_input[112:110] == 3'd0 ;
assign IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 =
{ stage1_rg_stage_input[263:232],
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22,
data_to_stage2_rd__h9875,
data_to_stage2_addr__h9876,
x_out_data_to_stage2_val1__h9894,
data_to_stage2_val2__h9878,
alu_outputs___1_fval1__h11500,
alu_outputs___1_fval2__h10474,
alu_outputs___1_fval3__h11502,
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
(stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] != 7'b0100111 &&
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2462),
stage1_rg_stage_input[151:145] == 7'b0100111,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
rm__h10057 } ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 =
x_out_bypass_rd__h9044 == stage1_rg_stage_input[139:135] ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 =
x_out_bypass_rd__h9044 == stage1_rg_stage_input[134:130] ;
assign NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 =
cur_verbosity__h3719 > 4'd1 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2295 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2303 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2295 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 ||
!stage2_rg_full) &&
stage1_rg_full &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2312 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2316 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2312 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2339 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(!stage1_rg_full || stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2343 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2339 ||
(!stage1_rg_full ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2404 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111 ||
stage1_rg_stage_input[151:145] == 7'b0101111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2589 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1307 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1342 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2462 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857 &&
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2445 &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
stage1_rg_stage_input[104:98] != 7'h71 &&
stage1_rg_stage_input[104:98] != 7'h51 &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
stage1_rg_stage_input[104:98] != 7'h70 &&
stage1_rg_stage_input[104:98] != 7'h50 ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857 &&
(_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2485 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0) &&
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h78) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm != 3'b101 &&
csr_regfile$read_frm != 3'b110 &&
csr_regfile$read_frm != 3'b111 :
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 =
imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074 &&
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_076___d2077 &&
imem_rg_cache_b16[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2096 =
imem_rg_pc[1:0] != 2'b0 &&
(imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] != 2'b11 ||
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074 &&
imem_rg_cache_b16[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2115 =
!near_mem$imem_exc &&
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074 ||
!near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_076___d2077 ||
imem_rg_cache_b16[1:0] != 2'b11) &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122 =
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2115 &&
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2119 &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] == 2'b11) ;
assign NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1114 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1113 ;
assign NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1136 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1134 ;
assign NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1211 =
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[21]) &&
(rg_cur_priv != 2'b0 || !csr_regfile$read_misa[13]) ||
stage1_rg_stage_input[87:76] != 12'b000100000101 ;
assign NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1655 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b000000000001 ;
assign NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d2758 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1211 ;
assign NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 =
rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h43591 == near_mem$imem_pc ;
assign NOT_rg_run_on_reset_257_258_OR_imem_rg_pc_BITS_ETC___d2265 =
!rg_run_on_reset ||
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 =
(stage1_rg_stage_input[109:105] != 5'b00010 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
stage1_rg_stage_input[109:105] != 5'b00011 &&
stage1_rg_stage_input[109:105] != 5'b0 &&
stage1_rg_stage_input[109:105] != 5'b00001 &&
stage1_rg_stage_input[109:105] != 5'b01100 &&
stage1_rg_stage_input[109:105] != 5'b01000 &&
stage1_rg_stage_input[109:105] != 5'b00100 &&
stage1_rg_stage_input[109:105] != 5'b10000 &&
stage1_rg_stage_input[109:105] != 5'b11000 &&
stage1_rg_stage_input[109:105] != 5'b10100 &&
stage1_rg_stage_input[109:105] != 5'b11100 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1167 =
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[263:260] != 4'b0 &&
stage1_rg_stage_input[263:260] != 4'b1000 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1174 =
stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479 =
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) &&
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 ;
assign NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1179 =
stage1_rg_stage_input[144:140] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772) ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 =
stage1_rg_stage_input[151:145] != 7'b0111011 ||
stage1_rg_stage_input[104:98] != 7'b0000001 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d766 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
stage1_rg_stage_input[151:145] == 7'b1100011 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1253 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
(stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1259 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
stage1_rg_stage_input[151:145] == 7'b1101111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1310 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1307) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1670 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1674 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2933 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2935 =
(NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340) &&
stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2933 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982) ;
assign NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753 =
(stage1_rg_stage_input[99:98] != 2'b0 &&
stage1_rg_stage_input[99:98] != 2'b01 ||
stage1_rg_stage_input[151:145] != 7'b1000011 &&
stage1_rg_stage_input[151:145] != 7'b1000111 &&
stage1_rg_stage_input[151:145] != 7'b1001111 &&
stage1_rg_stage_input[151:145] != 7'b1001011) &&
(stage1_rg_stage_input[151:145] != 7'b1010011 ||
stage1_rg_stage_input[104:98] != 7'h0 &&
stage1_rg_stage_input[104:98] != 7'h04 &&
stage1_rg_stage_input[104:98] != 7'h08 &&
stage1_rg_stage_input[104:98] != 7'h0C &&
(stage1_rg_stage_input[104:98] != 7'h2C ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10057 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h14 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h14 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10057 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h78 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b0)) &&
(stage1_rg_stage_input[151:145] != 7'b1010011 ||
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00011)) &&
(stage1_rg_stage_input[151:145] != 7'b1010011 ||
stage1_rg_stage_input[104:98] != 7'b0000001 &&
stage1_rg_stage_input[104:98] != 7'h05 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[104:98] != 7'h0D &&
(stage1_rg_stage_input[104:98] != 7'h2D ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10057 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h15 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h15 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h20 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h21 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10057 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00001)) &&
(stage1_rg_stage_input[151:145] != 7'b1010011 ||
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h79 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10057 != 3'b0)) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1014 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1029 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011 ||
stage1_rg_stage_input[112:110] == 3'b111) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1078 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1075 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1139 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1136 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d2884 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1229 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1226 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1307 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
(stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011 ||
stage1_rg_stage_input[151:145] == 7'b0011011 ||
stage1_rg_stage_input[151:145] == 7'b0111011 ||
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111)) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1345 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1342 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 &&
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 =
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148 =
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 =
(stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2) &&
near_mem$dmem_valid &&
near_mem$dmem_exc ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177 =
(stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc) &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
!stage2_mbox$valid :
!stage2_rg_stage2[5] && !stage2_fbox$valid) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
!stage2_rg_stage2[5] && stage2_fbox$valid) ;
assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 =
stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h32058 == near_mem$imem_pc ;
assign SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_057___d1269 =
{ {52{stage1_rg_stage_input_BITS_87_TO_76__q17[11]}},
stage1_rg_stage_input_BITS_87_TO_76__q17 } ;
assign SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747 =
{ {9{offset__h18401[11]}}, offset__h18401 } ;
assign SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772 =
{ {4{offset__h19032[8]}}, offset__h19032 } ;
assign _0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2485 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d899 ||
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d943 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign _theResult_____1_fst__h12326 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) ?
rd_val___1__h12322 :
_theResult_____1_fst__h12333 ;
assign _theResult_____1_fst__h12361 =
rs1_val_bypassed__h5370 & _theResult___snd_snd__h16492 ;
assign _theResult____h33602 =
(delta_CPI_instrs__h33601 == 64'd0) ?
delta_CPI_instrs___1__h33646 :
delta_CPI_instrs__h33601 ;
assign _theResult____h5654 = x_out_data_to_stage1_instr__h17442 ;
assign _theResult___fst__h12497 =
(stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262]) ?
rd_val___1__h16552 :
_theResult___fst__h12504 ;
assign _theResult___fst__h12504 =
stage1_rg_stage_input[262] ?
rd_val___1__h16613 :
rd_val___1__h16584 ;
assign _theResult___fst__h12585 =
{ {32{rs1_val_bypassed370_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8[31]}},
rs1_val_bypassed370_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 } ;
assign _theResult___snd_fst_rd_val__h9208 =
stage2_rg_stage2[5] ?
stage2_fbox$word_fst :
stage2_rg_stage2[197:134] ;
assign _theResult___snd_snd__h16492 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_057___d1269 :
rs2_val_bypassed__h5376 ;
assign _theResult___snd_snd_rd_val__h8063 =
stage2_rg_stage2[5] ?
stage2_rg_stage2[325:262] :
stage2_fbox$word_fst ;
assign addr_of_b32___1__h32186 = addr_of_b32__h32058 + 64'd4 ;
assign addr_of_b32___1__h43719 = addr_of_b32__h43591 + 64'd4 ;
assign addr_of_b32__h32058 =
{ stageF_branch_predictor$predict_rsp[63:2], 2'd0 } ;
assign addr_of_b32__h43591 = { rg_next_pc[63:2], 2'd0 } ;
assign alu_outputs___1_addr__h10096 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 ?
branch_target__h10074 :
x_out_cf_info_fallthru_PC__h16065 ;
assign alu_outputs___1_addr__h10470 =
rs1_val_bypassed__h5370 +
{ {52{stage1_rg_stage_input_BITS_75_TO_64__q6[11]}},
stage1_rg_stage_input_BITS_75_TO_64__q6 } ;
assign alu_outputs___1_exc_code__h10752 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
(stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1075 ?
4'd2 :
((stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 :
4'd2)) :
4'd2 ;
assign alu_outputs___1_fval1__h11500 = x_out_data_to_stage2_fval1__h9896 ;
assign alu_outputs___1_fval2__h10474 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1565 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) ?
x_out_fbypass_rd_val__h9227 :
rd_val__h9554 ;
assign alu_outputs___1_fval3__h11502 = x_out_data_to_stage2_fval3__h9898 ;
assign alu_outputs___1_val1__h10269 =
(stage1_rg_stage_input[112:110] == 3'b001) ?
rd_val__h16393 :
(stage1_rg_stage_input[262] ?
rd_val__h16466 :
rd_val__h16444) ;
assign alu_outputs___1_val1__h10314 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262])) ?
rd_val___1__h12241 :
_theResult_____1_fst__h12326 ;
assign alu_outputs___1_val1__h10343 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
rd_val___1__h16521 :
_theResult___fst__h12497 ;
assign alu_outputs___1_val1__h10756 =
stage1_rg_stage_input[112] ?
{ 59'd0, stage1_rg_stage_input[139:135] } :
rs1_val_bypassed__h5370 ;
assign alu_outputs___1_val1__h10784 =
{ 57'd0, stage1_rg_stage_input[104:98] } ;
assign alu_outputs_cf_info_taken_PC__h16058 =
x_out_cf_info_taken_PC__h16066 ;
assign branch_target__h10074 =
stage1_rg_stage_input[401:338] +
{ {51{stage1_rg_stage_input_BITS_63_TO_51__q1[12]}},
stage1_rg_stage_input_BITS_63_TO_51__q1 } ;
assign cpi__h33604 = x__h33603 / 64'd10 ;
assign cpifrac__h33605 = x__h33603 % 64'd10 ;
assign csr_regfile_RDY_server_reset_request_put__229__ETC___d2241 =
csr_regfile$RDY_server_reset_request_put &&
f_reset_reqs$EMPTY_N &&
stageF_f_reset_reqs$FULL_N &&
stageD_f_reset_reqs$FULL_N &&
stage1_f_reset_reqs$FULL_N &&
stage2_f_reset_reqs$FULL_N &&
stage3_f_reset_reqs$FULL_N ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1667 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2938 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
rg_state == 4'd3 &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2935 &&
!stage2_rg_full &&
!stage3_rg_full ;
assign csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801 =
delta_CPI_cycles__h33600 * 64'd10 ;
assign csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1757 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1000 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_misa__6_BIT_2_682_AND_stageD__ETC___d1763 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm == 3'b101 ||
csr_regfile$read_frm == 3'b110 ||
csr_regfile$read_frm == 3'b111 :
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110) ;
assign cur_verbosity__h3719 =
(csr_regfile$read_csr_minstret < cfg_logdelay) ?
4'd0 :
cfg_verbosity ;
assign d_instr__h25151 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 ?
instr_out___1__h25153 :
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2100 ;
assign data_to_stage2_addr__h9876 = x_out_data_to_stage2_addr__h9893 ;
assign data_to_stage2_val2__h9878 = x_out_data_to_stage2_val2__h9895 ;
assign decoded_instr_funct10__h30478 =
{ _theResult____h5654[31:25], _theResult____h5654[14:12] } ;
assign decoded_instr_imm12_S__h30480 =
{ _theResult____h5654[31:25], _theResult____h5654[11:7] } ;
assign decoded_instr_imm13_SB__h30481 =
{ _theResult____h5654[31],
_theResult____h5654[7],
_theResult____h5654[30:25],
_theResult____h5654[11:8],
1'b0 } ;
assign decoded_instr_imm21_UJ__h30483 =
{ _theResult____h5654[31],
_theResult____h5654[19:12],
_theResult____h5654[20],
_theResult____h5654[30:21],
1'b0 } ;
assign delta_CPI_cycles__h33600 =
csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
assign delta_CPI_instrs___1__h33646 = delta_CPI_instrs__h33601 + 64'd1 ;
assign delta_CPI_instrs__h33601 =
csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
assign fall_through_pc__h9619 =
stage1_rg_stage_input[401:338] +
(stage1_rg_stage_input[333] ? 64'd4 : 64'd2) ;
assign gpr_regfile_RDY_server_reset_request_put__226__ETC___d2244 =
gpr_regfile$RDY_server_reset_request_put &&
fpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__229__ETC___d2241 ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2119 =
imem_rg_pc[1:0] == 2'b0 ||
(!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] == 2'b11) &&
(!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074 ||
imem_rg_cache_b16[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2261 =
imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2074 =
imem_rg_pc[63:2] == imem_rg_cache_addr[63:2] ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 =
imem_rg_pc[63:2] == near_mem$imem_pc[63:2] ;
assign imm12__h17694 = { 4'd0, offset__h17566 } ;
assign imm12__h18031 = { 5'd0, offset__h17973 } ;
assign imm12__h19667 = { {6{imm6__h19665[5]}}, imm6__h19665 } ;
assign imm12__h20336 = { {2{nzimm10__h20334[9]}}, nzimm10__h20334 } ;
assign imm12__h20551 = { 2'd0, nzimm10__h20549 } ;
assign imm12__h20747 = { 6'b0, imm6__h19665 } ;
assign imm12__h21084 = { 6'b010000, imm6__h19665 } ;
assign imm12__h22705 = { 3'd0, offset__h22619 } ;
assign imm12__h23057 = { 4'd0, offset__h22991 } ;
assign imm20__h19795 = { {14{imm6__h19665[5]}}, imm6__h19665 } ;
assign imm6__h19665 = { stageD_rg_data[76], stageD_rg_data[70:66] } ;
assign instr___1__h17516 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h17693 :
IF_csr_regfile_read_misa__6_BIT_2_682_AND_stag_ETC___d1974 ;
assign instr__h17693 =
{ imm12__h17694, 8'd18, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h17838 =
{ 4'd0,
stageD_rg_data[72:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd18,
offset_BITS_4_TO_0___h17962,
7'b0100011 } ;
assign instr__h18030 =
{ imm12__h18031, rs1__h18032, 3'b010, rd__h18033, 7'b0000011 } ;
assign instr__h18225 =
{ 5'd0,
stageD_rg_data[69],
stageD_rg_data[76],
rd__h18033,
rs1__h18032,
3'b010,
offset_BITS_4_TO_0___h18393,
7'b0100011 } ;
assign instr__h18454 =
{ SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747[20],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747[10:1],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747[11],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1747[19:12],
12'd111 } ;
assign instr__h18907 = { 12'd0, stageD_rg_data[75:71], 15'd103 } ;
assign instr__h19023 = { 12'd0, stageD_rg_data[75:71], 15'd231 } ;
assign instr__h19088 =
{ SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[12],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[10:5],
5'd0,
rs1__h18032,
3'b0,
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[4:1],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[11],
7'b1100011 } ;
assign instr__h19405 =
{ SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[12],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[10:5],
5'd0,
rs1__h18032,
3'b001,
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[4:1],
SEXT_stageD_rg_data_677_BIT_76_694_CONCAT_stag_ETC___d1772[11],
7'b1100011 } ;
assign instr__h19743 =
{ imm12__h19667, 8'd0, stageD_rg_data[75:71], 7'b0010011 } ;
assign instr__h19927 =
{ imm20__h19795, stageD_rg_data[75:71], 7'b0110111 } ;
assign instr__h20056 =
{ imm12__h19667,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20283 =
{ imm12__h19667,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0011011 } ;
assign instr__h20538 =
{ imm12__h20336,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20710 = { imm12__h20551, 8'd16, rd__h18033, 7'b0010011 } ;
assign instr__h20879 =
{ imm12__h20747,
stageD_rg_data[75:71],
3'b001,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h21068 =
{ imm12__h20747, rs1__h18032, 3'b101, rs1__h18032, 7'b0010011 } ;
assign instr__h21257 =
{ imm12__h21084, rs1__h18032, 3'b101, rs1__h18032, 7'b0010011 } ;
assign instr__h21374 =
{ imm12__h19667, rs1__h18032, 3'b111, rs1__h18032, 7'b0010011 } ;
assign instr__h21552 =
{ 7'b0,
stageD_rg_data[70:66],
8'd0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21671 =
{ 7'b0,
stageD_rg_data[70:66],
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21766 =
{ 7'b0,
rd__h18033,
rs1__h18032,
3'b111,
rs1__h18032,
7'b0110011 } ;
assign instr__h21902 =
{ 7'b0,
rd__h18033,
rs1__h18032,
3'b110,
rs1__h18032,
7'b0110011 } ;
assign instr__h22038 =
{ 7'b0,
rd__h18033,
rs1__h18032,
3'b100,
rs1__h18032,
7'b0110011 } ;
assign instr__h22174 =
{ 7'b0100000,
rd__h18033,
rs1__h18032,
3'b0,
rs1__h18032,
7'b0110011 } ;
assign instr__h22312 =
{ 7'b0,
rd__h18033,
rs1__h18032,
3'b0,
rs1__h18032,
7'b0111011 } ;
assign instr__h22450 =
{ 7'b0100000,
rd__h18033,
rs1__h18032,
3'b0,
rs1__h18032,
7'b0111011 } ;
assign instr__h22608 =
{ 12'b000000000001,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b1110011 } ;
assign instr__h22704 =
{ imm12__h22705, 8'd19, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h22857 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23332,
7'b0100011 } ;
assign instr__h23056 =
{ imm12__h23057, rs1__h18032, 3'b011, rd__h18033, 7'b0000011 } ;
assign instr__h23207 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18033,
rs1__h18032,
3'b011,
offset_BITS_4_TO_0___h23332,
7'b0100011 } ;
assign instr__h23412 =
{ imm12__h17694, 8'd18, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24212 =
{ imm12__h22705, 8'd19, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24377 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23332,
7'b0100111 } ;
assign instr__h24576 =
{ imm12__h23057, rs1__h18032, 3'b011, rd__h18033, 7'b0000111 } ;
assign instr__h24727 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18033,
rs1__h18032,
3'b011,
offset_BITS_4_TO_0___h23332,
7'b0100111 } ;
assign instr_out___1__h25153 =
{ near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
assign instr_out___1__h25175 = { 16'b0, near_mem$imem_instr[15:0] } ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2127 =
near_mem$imem_exc ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2082 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129 =
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2127 ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2096 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11 ;
assign near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_076___d2077 =
near_mem$imem_pc == imem_rg_pc + 64'd2 ;
assign near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2224 =
near_mem$imem_valid && near_mem$imem_exc &&
near_mem$imem_exc_code != 4'd0 &&
near_mem$imem_exc_code != 4'd1 &&
near_mem$imem_exc_code != 4'd2 &&
near_mem$imem_exc_code != 4'd3 &&
near_mem$imem_exc_code != 4'd4 &&
near_mem$imem_exc_code != 4'd5 &&
near_mem$imem_exc_code != 4'd6 &&
near_mem$imem_exc_code != 4'd7 &&
near_mem$imem_exc_code != 4'd8 &&
near_mem$imem_exc_code != 4'd9 &&
near_mem$imem_exc_code != 4'd11 &&
near_mem$imem_exc_code != 4'd12 &&
near_mem$imem_exc_code != 4'd13 &&
near_mem$imem_exc_code != 4'd15 ;
assign new_epoch__h26600 = rg_epoch + 2'd1 ;
assign next_pc___1__h13758 = stage1_rg_stage_input[401:338] + 64'd2 ;
assign next_pc__h10109 =
stage1_rg_stage_input[401:338] +
{ {43{stage1_rg_stage_input_BITS_30_TO_10__q2[20]}},
stage1_rg_stage_input_BITS_30_TO_10__q2 } ;
assign next_pc__h10144 =
{ IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270[63:1],
1'd0 } ;
assign next_pc__h13755 = stage1_rg_stage_input[401:338] + 64'd4 ;
assign next_pc__h9620 = x_out_next_pc__h9637 ;
assign nzimm10__h20334 =
{ stageD_rg_data[76],
stageD_rg_data[68:67],
stageD_rg_data[69],
stageD_rg_data[66],
stageD_rg_data[70],
4'b0 } ;
assign nzimm10__h20549 =
{ stageD_rg_data[74:71],
stageD_rg_data[76:75],
stageD_rg_data[69],
stageD_rg_data[70],
2'b0 } ;
assign offset_BITS_4_TO_0___h17962 = { stageD_rg_data[75:73], 2'b0 } ;
assign offset_BITS_4_TO_0___h18393 =
{ stageD_rg_data[75:74], stageD_rg_data[70], 2'b0 } ;
assign offset_BITS_4_TO_0___h23332 = { stageD_rg_data[75:74], 3'b0 } ;
assign offset__h17566 =
{ stageD_rg_data[67:66],
stageD_rg_data[76],
stageD_rg_data[70:68],
2'b0 } ;
assign offset__h17973 =
{ stageD_rg_data[69],
stageD_rg_data[76:74],
stageD_rg_data[70],
2'b0 } ;
assign offset__h18401 =
{ stageD_rg_data[76],
stageD_rg_data[72],
stageD_rg_data[74:73],
stageD_rg_data[70],
stageD_rg_data[71],
stageD_rg_data[66],
stageD_rg_data[75],
stageD_rg_data[69:67],
1'b0 } ;
assign offset__h19032 =
{ stageD_rg_data[76],
stageD_rg_data[70:69],
stageD_rg_data[66],
stageD_rg_data[75:74],
stageD_rg_data[68:67],
1'b0 } ;
assign offset__h22619 =
{ stageD_rg_data[68:66],
stageD_rg_data[76],
stageD_rg_data[70:69],
3'b0 } ;
assign offset__h22991 =
{ stageD_rg_data[70:69], stageD_rg_data[76:74], 3'b0 } ;
assign output_stage2___1_data_to_stage3_frd_val__h7992 =
stage2_rg_stage2[5] ?
((stage2_rg_stage2[412:410] == 3'b010) ?
{ 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } :
near_mem$dmem_word64) :
stage2_rg_stage2[197:134] ;
assign rd__h18033 = { 2'b01, stageD_rg_data[68:66] } ;
assign rd_val___1__h12241 =
rs1_val_bypassed__h5370 + _theResult___snd_snd__h16492 ;
assign rd_val___1__h12322 =
rs1_val_bypassed__h5370 - _theResult___snd_snd__h16492 ;
assign rd_val___1__h12329 =
((rs1_val_bypassed__h5370 ^ 64'h8000000000000000) <
(_theResult___snd_snd__h16492 ^ 64'h8000000000000000)) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12336 =
(rs1_val_bypassed__h5370 < _theResult___snd_snd__h16492) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12343 =
rs1_val_bypassed__h5370 ^ _theResult___snd_snd__h16492 ;
assign rd_val___1__h12350 =
rs1_val_bypassed__h5370 | _theResult___snd_snd__h16492 ;
assign rd_val___1__h16521 =
{ {32{IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18[31]}},
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 } ;
assign rd_val___1__h16552 = { {32{x__h16555[31]}}, x__h16555 } ;
assign rd_val___1__h16584 = { {32{x__h16587[31]}}, x__h16587 } ;
assign rd_val___1__h16613 = { {32{tmp__h16612[31]}}, tmp__h16612 } ;
assign rd_val___1__h16665 =
{ {32{rs1_val_bypassed370_BITS_31_TO_0_PLUS_rs2_val__ETC__q9[31]}},
rs1_val_bypassed370_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 } ;
assign rd_val___1__h16713 =
{ {32{rs1_val_bypassed370_BITS_31_TO_0_MINUS_rs2_val_ETC__q10[31]}},
rs1_val_bypassed370_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 } ;
assign rd_val___1__h16719 = { {32{x__h16722[31]}}, x__h16722 } ;
assign rd_val___1__h16764 = { {32{x__h16767[31]}}, x__h16767 } ;
assign rd_val__h10385 = { {32{v32__h10383[31]}}, v32__h10383 } ;
assign rd_val__h10406 = stage1_rg_stage_input[401:338] + rd_val__h10385 ;
assign rd_val__h16393 = rs1_val_bypassed__h5370 << shamt__h10256 ;
assign rd_val__h16444 = rs1_val_bypassed__h5370 >> shamt__h10256 ;
assign rd_val__h16466 =
rs1_val_bypassed__h5370 >> shamt__h10256 |
~(64'hFFFFFFFFFFFFFFFF >> shamt__h10256) &
{64{rs1_val_bypassed__h5370[63]}} ;
assign rd_val__h9457 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs1 ;
assign rd_val__h9490 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs2 ;
assign rd_val__h9523 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs1 ;
assign rd_val__h9554 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs2 ;
assign rd_val__h9588 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[139:135] == stage1_rg_stage_input[129:125]) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs3 ;
assign rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1134 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
stage1_rg_stage_input[87:76] == 12'b000100000101 ;
assign rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1199 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010 ;
assign rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1213 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1211 ;
assign rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1645 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 &&
stage1_rg_stage_input[87:76] != 12'b000000000001 ;
assign rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2922 =
rg_state == 4'd12 && csr_regfile$wfi_resume &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2753 =
rg_state == 4'd3 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 &&
!stage3_rg_full &&
!stage2_rg_full ;
assign rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2779 =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340 &&
(stage1_rg_stage_input[332] ||
((stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
((stage1_rg_stage_input[151:145] == 7'b1100111) ?
stage1_rg_stage_input[112:110] != 3'd0 :
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774))) ;
assign rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2814 =
rg_state == 4'd3 &&
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2817 =
rg_state_7_EQ_3_323_AND_NOT_csr_regfile_interr_ETC___d2814 &&
!stage3_rg_full &&
!stage2_rg_full &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340 ;
assign rg_state_7_EQ_3_323_AND_stage3_rg_full_8_OR_st_ETC___d2335 =
rg_state == 4'd3 &&
(stage3_rg_full || stage2_rg_full || stage1_rg_full ||
stageD_rg_full ||
stageF_rg_full) &&
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2334 ;
assign rg_state_7_EQ_5_926_AND_NOT_stageF_rg_full_104_ETC___d2927 =
rg_state == 4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_104_ETC___d2865 =
rg_state == 4'd8 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129) ;
assign rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797 =
rg_trap_info[131:68] == csr_regfile$csr_trap_actions[193:130] ;
assign rm__h10057 =
(stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm :
stage1_rg_stage_input[112:110] ;
assign rs1__h18032 = { 2'b01, stageD_rg_data[73:71] } ;
assign rs1_val__h34220 =
(rg_trap_instr[14:12] == 3'b001) ?
rg_csr_val1 :
{ 59'd0, rg_trap_instr[19:15] } ;
assign rs1_val_bypassed370_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 =
rs1_val_bypassed__h5370[31:0] - rs2_val_bypassed__h5376[31:0] ;
assign rs1_val_bypassed370_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 =
rs1_val_bypassed__h5370[31:0] + rs2_val_bypassed__h5376[31:0] ;
assign rs1_val_bypassed370_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 =
rs1_val_bypassed__h5370[31:0] >> rs2_val_bypassed__h5376[4:0] |
~(32'hFFFFFFFF >> rs2_val_bypassed__h5376[4:0]) &
{32{rs1_val_bypassed370_BITS_31_TO_0__q7[31]}} ;
assign rs1_val_bypassed370_BITS_31_TO_0__q7 =
rs1_val_bypassed__h5370[31:0] ;
assign rs1_val_bypassed__h5370 =
(stage1_rg_stage_input[139:135] == 5'd0) ? 64'd0 : val__h9459 ;
assign rs2_val_bypassed__h5376 =
(stage1_rg_stage_input[134:130] == 5'd0) ? 64'd0 : val__h9492 ;
assign shamt__h10256 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
stage1_rg_stage_input[81:76] :
rs2_val_bypassed__h5376[5:0] ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1000 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1008 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1005 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1327 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1385 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1411 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1408 ;
assign stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363 =
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349) ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2424 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d875 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10057 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d875 =
stage1_rg_stage_input[104:98] == 7'h0 ||
stage1_rg_stage_input[104:98] == 7'h04 ||
stage1_rg_stage_input[104:98] == 7'h08 ||
stage1_rg_stage_input[104:98] == 7'h0C ||
stage1_rg_stage_input[104:98] == 7'h2C &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h10 && rm__h10057 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h10 &&
(rm__h10057 == 3'b001 || rm__h10057 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10057 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d884 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d875 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10057 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d892 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d884 ||
stage1_rg_stage_input[104:98] == 7'h50 &&
(rm__h10057 == 3'b010 || rm__h10057 == 3'b001 ||
rm__h10057 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d899 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d892 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d926 =
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input[104:98] == 7'h05 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[104:98] == 7'h0D ||
stage1_rg_stage_input[104:98] == 7'h2D &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h11 && rm__h10057 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h11 &&
(rm__h10057 == 3'b001 || rm__h10057 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10057 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10057 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h20 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d937 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d926 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h51 && rm__h10057 == 3'b010 ||
stage1_rg_stage_input[104:98] == 7'h51 &&
(rm__h10057 == 3'b001 || rm__h10057 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d943 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d937 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1045 =
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(stage1_rg_stage_input[263:260] == 4'b0 ||
stage1_rg_stage_input[263:260] == 4'b1000) ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1059 =
stage1_rg_stage_input[112:110] == 3'b001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d812 =
stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) ||
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262] ||
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1075 =
stage1_rg_stage_input[144:140] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1113 =
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
stage1_rg_stage_input[87:76] == 12'b000100000010 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1351 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892 =
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_037_E_ETC___d1113 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800 =
stage1_rg_stage_input[151:145] == 7'b0111011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d972 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800 ||
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:258] == 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1408 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1389 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1370 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1405 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1598 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2340 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_86_OR_NOT_stage1_rg_s_ETC___d2402 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1389 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1370 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1405 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 =
stage1_rg_stage_input[335:334] == rg_epoch ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2445 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2424 ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d926 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0) ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d959 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d899 ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d943 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10057 == 3'b0) ;
assign stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1106 =
stage1_rg_stage_input[332] ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign stage1_rg_stage_input_BITS_30_TO_10__q2 =
stage1_rg_stage_input[30:10] ;
assign stage1_rg_stage_input_BITS_63_TO_51__q1 =
stage1_rg_stage_input[63:51] ;
assign stage1_rg_stage_input_BITS_75_TO_64__q6 =
stage1_rg_stage_input[75:64] ;
assign stage1_rg_stage_input_BITS_87_TO_76__q17 =
stage1_rg_stage_input[87:76] ;
assign stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2376 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1005 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1016 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1014 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1017 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1016 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1019 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1017 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1031 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1029 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1032 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1031 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1034 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1032 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1049 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1045 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1050 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1049 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1052 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1050 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1063 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1059 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1064 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1063 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1066 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1064 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1080 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1078 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1081 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1080 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1083 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1081 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1095 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1096 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1095 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1098 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1096 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1119 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1106) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1114 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1120 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1119 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1121 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1120 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1123 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1121 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1141 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1106) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_89_AND_ETC___d1139 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1142 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1141 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1143 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1142 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1145 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1143 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1218 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1199) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1213) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1219 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1218 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1220 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1179) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1219 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1223 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1167) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1174) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1220 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1224 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1223 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1225 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1224 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1226 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1225 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1288 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1342 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1370 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1375 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1370 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d995 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1378 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1351) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1375 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1389 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1351 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1405 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0101111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1565 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
stage2_fbox$valid ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2292 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d769 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d781 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1351) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1375 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 &&
(IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 ||
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 &&
(IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d982 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d975 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2378 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2380 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2382 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2384 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2386 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2392 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296) &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 =
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215 =
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244 =
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 =
stage2_rg_stage2[397:395] == 3'd2 ||
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
stage2_rg_stage2[5] || stage2_fbox$valid) ;
assign stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2334 =
(stage3_rg_full || !stage2_rg_full ||
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168) &&
(stage3_rg_full || stage2_rg_full || !stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2331) ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[139:135] ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[134:130] ;
assign stageF_f_reset_rsps_i_notEmpty__251_AND_stageD_ETC___d2271 =
stageF_f_reset_rsps$EMPTY_N && stageD_f_reset_rsps$EMPTY_N &&
stage1_f_reset_rsps$EMPTY_N &&
stage2_f_reset_rsps$EMPTY_N &&
stage3_f_reset_rsps$EMPTY_N &&
f_reset_rsps$FULL_N &&
NOT_rg_run_on_reset_257_258_OR_imem_rg_pc_BITS_ETC___d2265 ;
assign stageF_rg_full_104_AND_near_mem_imem_valid_AND_ETC___d2136 =
stageF_rg_full && near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129 &&
!near_mem$imem_exc ;
assign sxl__h6710 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[35:34] :
2'd0 ;
assign tmp__h16612 =
rs1_val_bypassed__h5370[31:0] >> stage1_rg_stage_input[80:76] |
~(32'hFFFFFFFF >> stage1_rg_stage_input[80:76]) &
{32{rs1_val_bypassed370_BITS_31_TO_0__q7[31]}} ;
assign trap_info_tval__h14908 =
(stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_069_OR_rg_cur_priv_8_EQ__ETC___d1645)) ?
(stage1_rg_stage_input[333] ?
{ 32'd0, stage1_rg_stage_input[263:232] } :
{ 48'd0, stage1_rg_stage_input[231:216] }) :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 ;
assign uxl__h6711 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[33:32] :
2'd0 ;
assign v32__h10383 = { stage1_rg_stage_input[50:31], 12'h0 } ;
assign val__h9459 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) ?
x_out_bypass_rd_val__h9045 :
rd_val__h9457 ;
assign val__h9492 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ?
x_out_bypass_rd_val__h9045 :
rd_val__h9490 ;
assign value__h14978 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h14908 ;
assign x__h16555 =
rs1_val_bypassed__h5370[31:0] << stage1_rg_stage_input[80:76] ;
assign x__h16587 =
rs1_val_bypassed__h5370[31:0] >> stage1_rg_stage_input[80:76] ;
assign x__h16722 =
rs1_val_bypassed__h5370[31:0] << rs2_val_bypassed__h5376[4:0] ;
assign x__h16767 =
rs1_val_bypassed__h5370[31:0] >> rs2_val_bypassed__h5376[4:0] ;
assign x__h33603 =
csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801[63:0] /
_theResult____h33602 ;
assign x_exc_code__h44015 =
(csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
csr_regfile$interrupt_pending[3:0] :
4'd0 ;
assign x_out_cf_info_fallthru_PC__h16065 =
stage1_rg_stage_input[333] ?
next_pc__h13755 :
next_pc___1__h13758 ;
assign x_out_data_to_stage1_instr__h17442 =
stageD_rg_data[165] ? stageD_rg_data[95:64] : instr___1__h17516 ;
assign x_out_data_to_stage2_fval1__h9896 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1565 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) ?
x_out_fbypass_rd_val__h9227 :
rd_val__h9523 ;
assign x_out_data_to_stage2_fval3__h9898 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1565 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ?
x_out_fbypass_rd_val__h9227 :
rd_val__h9588 ;
assign x_out_data_to_stage2_rd__h9892 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ?
data_to_stage2_rd__h9875 :
5'd0 ;
assign x_out_data_to_stage2_val2__h9895 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
branch_target__h10074 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1541 ;
assign x_out_next_pc__h9637 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d979 ?
data_to_stage2_addr__h9876 :
fall_through_pc__h9619 ;
assign x_out_trap_info_exc_code__h14913 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:328] :
alu_outputs_exc_code__h11528 ;
assign y__h35332 = ~rs1_val__h35054 ;
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8443 = stage2_rg_stage2[493:430];
default: value__h8443 = stage2_rg_stage2[493:430];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_exc_code)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
x_out_trap_info_exc_code__h8553 = near_mem$dmem_exc_code;
default: x_out_trap_info_exc_code__h8553 = 4'd2;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8657 = stage2_rg_stage2[389:326];
default: value__h8657 = 64'd0;
endcase
end
always@(stage2_rg_stage2 or stage2_fbox$word_snd)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
x_out_data_to_stage3_fpr_flags__h8117 = 5'd0;
default: x_out_data_to_stage3_fpr_flags__h8117 = stage2_fbox$word_snd;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_data_to_stage3_rd__h8113 = stage2_rg_stage2[394:390];
3'd2: x_out_data_to_stage3_rd__h8113 = 5'd0;
default: x_out_data_to_stage3_rd__h8113 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4: x_out_bypass_rd__h9044 = stage2_rg_stage2[394:390];
default: x_out_bypass_rd__h9044 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd__h9226 = stage2_rg_stage2[394:390];
default: x_out_fbypass_rd__h9226 = stage2_rg_stage2[394:390];
endcase
end
always@(rg_trap_instr or rg_csr_val1)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b011: rs1_val__h35054 = rg_csr_val1;
default: rs1_val__h35054 = { 59'd0, rg_trap_instr[19:15] };
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$word_fst or
output_stage2___1_data_to_stage3_frd_val__h7992)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2, 3'd3:
x_out_data_to_stage3_frd_val__h8118 = stage2_rg_stage2[197:134];
3'd1, 3'd4:
x_out_data_to_stage3_frd_val__h8118 =
output_stage2___1_data_to_stage3_frd_val__h7992;
default: x_out_data_to_stage3_frd_val__h8118 = stage2_fbox$word_fst;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8063 or
near_mem$dmem_word64 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2:
x_out_data_to_stage3_rd_val__h8114 = stage2_rg_stage2[325:262];
3'd1, 3'd4: x_out_data_to_stage3_rd_val__h8114 = near_mem$dmem_word64;
3'd3: x_out_data_to_stage3_rd_val__h8114 = stage2_mbox$word;
default: x_out_data_to_stage3_rd_val__h8114 =
_theResult___snd_snd_rd_val__h8063;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8063 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_bypass_rd_val__h9045 = stage2_rg_stage2[325:262];
3'd3: x_out_bypass_rd_val__h9045 = stage2_mbox$word;
default: x_out_bypass_rd_val__h9045 =
_theResult___snd_snd_rd_val__h8063;
endcase
end
always@(stage2_rg_stage2 or _theResult___snd_fst_rd_val__h9208)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd_val__h9227 = stage2_rg_stage2[197:134];
default: x_out_fbypass_rd_val__h9227 =
_theResult___snd_fst_rd_val__h9208;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0000111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100111,
7'b1101111:
data_to_stage2_rd__h9875 = stage1_rg_stage_input[144:140];
7'b1100011: data_to_stage2_rd__h9875 = 5'd0;
default: data_to_stage2_rd__h9875 = stage1_rg_stage_input[144:140];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
near_mem$dmem_valid;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!near_mem$dmem_valid;
3'd3:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_mbox$valid;
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
stage2_rg_stage2[397:395] == 3'd5 && !stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_rg_stage2[397:395] != 3'd5 || stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
!stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] != 3'd3 && stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
stage2_rg_stage2[397:395] != 3'd2 &&
(stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5]);
endcase
end
always@(stage2_rg_stage2 or
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289;
endcase
end
always@(stage2_rg_stage2 or
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296;
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5] ||
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
_theResult___fst__h12585 or
rd_val___1__h16665 or
rd_val___1__h16719 or rd_val___1__h16764 or rd_val___1__h16713)
begin
case (stage1_rg_stage_input[97:88])
10'b0: alu_outputs___1_val1__h10371 = rd_val___1__h16665;
10'b0000000001: alu_outputs___1_val1__h10371 = rd_val___1__h16719;
10'b0000000101: alu_outputs___1_val1__h10371 = rd_val___1__h16764;
10'b0100000000: alu_outputs___1_val1__h10371 = rd_val___1__h16713;
default: alu_outputs___1_val1__h10371 = _theResult___fst__h12585;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d775 =
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
stage1_rg_stage_input[112:110] == 3'b111 &&
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[112:110] != 3'b111 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[151:145] == 7'b0001111 ||
stage1_rg_stage_input[151:145] == 7'b1110011 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d756;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d764 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[112:110] == 3'b111 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0);
endcase
end
always@(stage1_rg_stage_input or
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857 or
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d959 or
csr_regfile$read_mstatus)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962 =
(stage1_rg_stage_input[109:105] == 5'b00010 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[109:105] == 5'b00011 ||
stage1_rg_stage_input[109:105] == 5'b0 ||
stage1_rg_stage_input[109:105] == 5'b00001 ||
stage1_rg_stage_input[109:105] == 5'b01100 ||
stage1_rg_stage_input[109:105] == 5'b01000 ||
stage1_rg_stage_input[109:105] == 5'b00100 ||
stage1_rg_stage_input[109:105] == 5'b10000 ||
stage1_rg_stage_input[109:105] == 5'b11000 ||
stage1_rg_stage_input[109:105] == 5'b10100 ||
stage1_rg_stage_input[109:105] == 5'b11100) &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d857 &&
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d959;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d962;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 or
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d812)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970 =
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d812;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[112:110] == 3'b101 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970 =
stage1_rg_stage_input[97:88] == 10'b0 ||
stage1_rg_stage_input[97:88] == 10'b0100000000 ||
stage1_rg_stage_input[97:88] == 10'b0000000001 ||
stage1_rg_stage_input[97:88] == 10'b0000000101 ||
stage1_rg_stage_input[97:88] == 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d970 =
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111 ||
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14;
endcase
end
always@(rg_cur_priv)
begin
case (rg_cur_priv)
2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd8;
2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd9;
default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd11;
endcase
end
always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q15)
begin
case (stage1_rg_stage_input[87:76])
12'b0:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 =
CASE_rg_cur_priv_0b0_8_0b1_9_11__q15;
12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd3;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h10752)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0001111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0100011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100011:
alu_outputs_exc_code__h11528 = 4'd2;
7'b1100111, 7'b1101111: alu_outputs_exc_code__h11528 = 4'd0;
7'b1110011:
alu_outputs_exc_code__h11528 = alu_outputs___1_exc_code__h10752;
default: alu_outputs_exc_code__h11528 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or
_theResult_____1_fst__h12361 or
rd_val___1__h12329 or
rd_val___1__h12336 or rd_val___1__h12343 or rd_val___1__h12350)
begin
case (stage1_rg_stage_input[112:110])
3'b010: _theResult_____1_fst__h12333 = rd_val___1__h12329;
3'b011: _theResult_____1_fst__h12333 = rd_val___1__h12336;
3'b100: _theResult_____1_fst__h12333 = rd_val___1__h12343;
3'b110: _theResult_____1_fst__h12333 = rd_val___1__h12350;
default: _theResult_____1_fst__h12333 = _theResult_____1_fst__h12361;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_addr__h10470 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270 or
rs1_val_bypassed__h5370 or
alu_outputs___1_addr__h10096 or next_pc__h10144 or next_pc__h10109)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
x_out_data_to_stage2_addr__h9893 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1270;
7'b0100011:
x_out_data_to_stage2_addr__h9893 = alu_outputs___1_addr__h10470;
7'b0101111: x_out_data_to_stage2_addr__h9893 = rs1_val_bypassed__h5370;
7'b1100011:
x_out_data_to_stage2_addr__h9893 = alu_outputs___1_addr__h10096;
7'b1100111: x_out_data_to_stage2_addr__h9893 = next_pc__h10144;
7'b1101111: x_out_data_to_stage2_addr__h9893 = next_pc__h10109;
default: x_out_data_to_stage2_addr__h9893 =
alu_outputs___1_addr__h10470;
endcase
end
always@(stage1_rg_stage_input or
next_pc__h10144 or branch_target__h10074 or next_pc__h10109)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011: x_out_cf_info_taken_PC__h16066 = branch_target__h10074;
7'b1101111: x_out_cf_info_taken_PC__h16066 = next_pc__h10109;
default: x_out_cf_info_taken_PC__h16066 = next_pc__h10144;
endcase
end
always@(stage1_rg_stage_input or rs2_val_bypassed__h5376)
begin
case (stage1_rg_stage_input[151:145])
7'b0100011, 7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5376;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5376;
endcase
end
always@(stage1_rg_stage_input or
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1655 or
data_to_stage2_addr__h9876)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
data_to_stage2_addr__h9876;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
(stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_069_101_AND_NOT_rg_c_ETC___d1655) ?
stage1_rg_stage_input[401:338] :
64'd0;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1174 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1167 or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 or
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0001111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1174 &&
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1167;
7'b0100011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d753;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768;
endcase
end
always@(stage1_rg_stage_input or
rs1_val_bypassed__h5370 or
alu_outputs___1_val1__h10314 or
rd_val__h10406 or
alu_outputs___1_val1__h10343 or
alu_outputs___1_val1__h10784 or
rd_val__h10385 or
alu_outputs___1_val1__h10371 or alu_outputs___1_val1__h10756)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
alu_outputs___1_val1__h10314;
7'b0010111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
rd_val__h10406;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
alu_outputs___1_val1__h10343;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
alu_outputs___1_val1__h10784;
7'b0110111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
rd_val__h10385;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
alu_outputs___1_val1__h10371;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
alu_outputs___1_val1__h10756;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1530 =
rs1_val_bypassed__h5370;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1532 or
x_out_cf_info_fallthru_PC__h16065)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
x_out_data_to_stage2_val1__h9894 =
x_out_cf_info_fallthru_PC__h16065;
default: x_out_data_to_stage2_val1__h9894 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1532;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd1;
7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd0;
7'b0100011, 7'b0100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd2;
7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd4;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd5;
endcase
end
always@(stage1_rg_stage_input or
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800 or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011, 7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd0;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d800) ?
3'd3 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd0;
7'b1100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd2;
7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd1;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'hFFFFFFFFFFFFFFFF;
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_logdelay$EN)
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (imem_rg_cache_addr$EN)
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
if (rg_cur_priv$EN)
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
if (rg_run_on_reset$EN)
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (stage1_rg_full$EN)
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
if (stage2_rg_full$EN)
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
if (stage2_rg_resetting$EN)
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
stage2_rg_resetting$D_IN;
if (stage3_rg_full$EN)
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
if (stageD_rg_full$EN)
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
if (stageF_rg_epoch$EN)
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
if (stageF_rg_full$EN)
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
end
if (imem_rg_cache_b16$EN)
imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
if (imem_rg_mstatus_MXR$EN)
imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
if (imem_rg_priv$EN)
imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
if (imem_rg_satp$EN)
imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
if (imem_rg_sstatus_SUM$EN)
imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
if (imem_rg_tval$EN)
imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_start_CPI_cycles$EN)
rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
if (rg_start_CPI_instrs$EN)
rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
if (rg_trap_info$EN)
rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
if (rg_trap_instr$EN)
rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
if (rg_trap_interrupt$EN)
rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
if (stage1_rg_stage_input$EN)
stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
stage1_rg_stage_input$D_IN;
if (stage2_rg_stage2$EN)
stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
if (stage3_rg_stage3$EN)
stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
if (stageD_rg_data$EN)
stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
if (stageF_rg_priv$EN)
stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
cfg_verbosity = 4'hA;
imem_rg_cache_addr = 64'hAAAAAAAAAAAAAAAA;
imem_rg_cache_b16 = 16'hAAAA;
imem_rg_f3 = 3'h2;
imem_rg_mstatus_MXR = 1'h0;
imem_rg_pc = 64'hAAAAAAAAAAAAAAAA;
imem_rg_priv = 2'h2;
imem_rg_satp = 64'hAAAAAAAAAAAAAAAA;
imem_rg_sstatus_SUM = 1'h0;
imem_rg_tval = 64'hAAAAAAAAAAAAAAAA;
rg_csr_pc = 64'hAAAAAAAAAAAAAAAA;
rg_csr_val1 = 64'hAAAAAAAAAAAAAAAA;
rg_cur_priv = 2'h2;
rg_epoch = 2'h2;
rg_mstatus_MXR = 1'h0;
rg_next_pc = 64'hAAAAAAAAAAAAAAAA;
rg_run_on_reset = 1'h0;
rg_sstatus_SUM = 1'h0;
rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_trap_info = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_trap_instr = 32'hAAAAAAAA;
rg_trap_interrupt = 1'h0;
stage1_rg_full = 1'h0;
stage1_rg_stage_input =
402'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage2_rg_full = 1'h0;
stage2_rg_resetting = 1'h0;
stage2_rg_stage2 =
496'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage3_rg_full = 1'h0;
stage3_rg_stage3 =
239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_data =
234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_full = 1'h0;
stageF_rg_epoch = 2'h2;
stageF_rg_full = 1'h0;
stageF_rg_priv = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x epoch:%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_cur_priv,
csr_regfile$read_mstatus,
rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write("MStatus{",
"sd:%0d",
csr_regfile$read_mstatus[14:13] == 2'h3 ||
csr_regfile$read_mstatus[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
$write(" sxl:%0d uxl:%0d", sxl__h6710, uxl__h6711);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tw:%0d", csr_regfile$read_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" sum:%0d", csr_regfile$read_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" spp:%0d", csr_regfile$read_mstatus[8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" pies:%0d_%0d%0d",
csr_regfile$read_mstatus[7],
csr_regfile$read_mstatus[5],
csr_regfile$read_mstatus[4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" ies:%0d_%0d%0d",
csr_regfile$read_mstatus[3],
csr_regfile$read_mstatus[1],
csr_regfile$read_mstatus[0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("Rd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("rd_val:%h", stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("FRd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("frd_val:%h", stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage2: pc 0x%08h instr 0x%08h priv %0d",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[493:430]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Output_Stage2", " NONPIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("Output_Stage2", " PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full)
$write("Output_Stage2", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8117);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8113,
x_out_data_to_stage3_frd_val__h8118);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8113,
x_out_data_to_stage3_rd_val__h8114);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8443);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8553);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8657, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8443);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8553);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8657, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279))
$write("Rd %0d ", x_out_bypass_rd__h9044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297))
$write("rd_val:%h", x_out_bypass_rd_val__h9045);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310)
$write("FRd %0d ", x_out_fbypass_rd__h9226);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324)
$write("frd_val:%h", x_out_fbypass_rd_val__h9227);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage1: pc 0x%08h instr 0x%08h priv %0d",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("Output_Stage1",
" BUSY pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("Output_Stage1",
" NONPIPE: pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("Output_Stage1");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
$write("Output_Stage1", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1000)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1008)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1019)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1034)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1052)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1066)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1083)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1098)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1123)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1145)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1229)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240)
$write("{", "CF_None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248)
$write("{", "BR ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1253)
$write("{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1259)
$write("JAL [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16066,
x_out_cf_info_fallthru_PC__h16065);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1288)
$write("JALR [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16066,
x_out_cf_info_fallthru_PC__h16065);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248)
if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432)
$write("taken ");
else
$write("fallthru ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1253)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1240)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1248)
$write("[%h->%h %h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_fallthru_PC__h16065,
x_out_cf_info_taken_PC__h16066);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1253)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1310)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1327)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1345)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1378)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1385)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1411)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h9892);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h9893,
x_out_data_to_stage2_val1__h9894,
x_out_data_to_stage2_val2__h9895);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h9896,
alu_outputs___1_fval2__h10474,
x_out_data_to_stage2_fval3__h9898);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1598)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1005)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1017)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1032)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1050)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1064)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1081)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1096)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1121)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1143)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1226)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("'h%h", stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("'h%h", x_out_trap_info_exc_code__h14913);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d784)
$write("'h%h", value__h14978, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d984)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1670)
$write("\n redirect next_pc:%h", x_out_next_pc__h9637);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1674)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
stageD_rg_data[233:170],
x_out_data_to_stage1_instr__h17442,
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
stageD_rg_data[165])
$write(" instr_C:%0h", stageD_rg_data[79:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
!stageD_rg_data[165])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write(" instr:%0h pred_pc:%0h",
x_out_data_to_stage1_instr__h17442,
stageD_rg_data[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] != 4'd0 &&
stageD_rg_data[163:160] != 4'd1 &&
stageD_rg_data[163:160] != 4'd2 &&
stageD_rg_data[163:160] != 4'd3 &&
stageD_rg_data[163:160] != 4'd4 &&
stageD_rg_data[163:160] != 4'd5 &&
stageD_rg_data[163:160] != 4'd6 &&
stageD_rg_data[163:160] != 4'd7 &&
stageD_rg_data[163:160] != 4'd8 &&
stageD_rg_data[163:160] != 4'd9 &&
stageD_rg_data[163:160] != 4'd11 &&
stageD_rg_data[163:160] != 4'd12 &&
stageD_rg_data[163:160] != 4'd13 &&
stageD_rg_data[163:160] != 4'd15)
$write("unknown trap Exc_Code %d", stageD_rg_data[163:160]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" tval %0h", stageD_rg_data[159:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
imem_rg_pc,
d_instr__h25151,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122))
$write(" BUSY: pc:%h", imem_rg_pc);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129)
$write("data_to_StageD {pc:%h priv:%0d epoch:%0d",
imem_rg_pc,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_104_AND_near_mem_imem_valid_AND_ETC___d2136)
$write(" instr:%h pred_pc:%h",
d_instr__h25151,
stageF_branch_predictor$predict_rsp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2224)
$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_104_AND_near_mem_imem_valid_AND_ETC___d2136)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2122))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2129)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage2_nonpipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage2_nonpipe -> CPU_TRAP",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_trap &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
csr_regfile$read_csr_mcycle,
csr_regfile$csr_trap_actions[193:130],
rg_trap_instr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display(" CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
cpi__h33604,
cpifrac__h33605,
delta_CPI_cycles__h33600,
_theResult____h33602);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_trap_info[131:68],
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3719 != 4'd0)
$display(" mcause:0x%0h epc 0x%0h tval:0x%0h next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
csr_regfile$csr_trap_actions[65:2],
rg_trap_info[131:68],
rg_trap_info[63:0],
csr_regfile$csr_trap_actions[193:130],
csr_regfile$csr_trap_actions[1:0],
csr_regfile$csr_trap_actions[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34220,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
!csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34220,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35054,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
!csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35054,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_restart_after_csrrx",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3719 != 4'd0)
$display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d",
csr_regfile$csr_ret_actions[129:66],
csr_regfile$csr_ret_actions[63:0],
csr_regfile$csr_ret_actions[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
(cur_verbosity__h3719 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU.rl_stage1_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_from_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_interrupt &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
if (WILL_FIRE_RL_imem_rl_assert_fail)
begin
v__h2440 = $stime;
#0;
end
v__h2434 = v__h2440 / 32'd10;
if (WILL_FIRE_RL_imem_rl_assert_fail)
$display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
v__h2434);
if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
csr_regfile$read_csr_mcycle,
64'd4096);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
64'd4096,
new_epoch__h26600,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
64'd4096,
rg_cur_priv,
rg_epoch,
new_epoch__h26600);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage3_rg_stage3[69])
$display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
!stage3_rg_stage3[69])
$display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373)
$write(" S3.enq: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2376)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2378)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2380)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8117);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2382)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2384)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8113,
x_out_data_to_stage3_frd_val__h8118);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2386)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8113,
x_out_data_to_stage3_rd_val__h8114);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2373)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2392)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2296 ||
!stage2_rg_full) &&
stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" rl_pipe: Discarding stage1 due to redirection");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2398 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2300 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h9892);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h9893,
x_out_data_to_stage2_val1__h9894,
x_out_data_to_stage2_val2__h9895);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h9896,
alu_outputs___1_fval2__h10474,
x_out_data_to_stage2_fval3__h9898);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_Stage1.enq: 0x%08h", stageD_rg_data[233:170]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_StageD.enq (Data_StageF_to_StageD)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
stageF_branch_predictor$predict_rsp,
stageF_rg_epoch,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$write("CPU: Bluespec RISC-V Flute v3.0");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("Copyright (c) 2016-2022 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
end
// synopsys translate_on
endmodule // mkCPU
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo_ctl.v
// Author : Chih-Tsun Huang
// E-mail : [email protected]
// Revision : 4
// Date : 2014/04/28
// Abstract :
// FIFO controller is mainly the finite state machine and its
// control signals to manage the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo_ctr (
// inputs
input wire clk,
input wire rst_n,
input wire push,
input wire pop,
// outputs
output reg empty,
output reg almost_empty,
output reg full,
output reg almost_full,
output reg error,
output reg cen,
output reg wen,
output reg oen,
output reg [4:0] addr
);
parameter numOfRam = 32;
// small delay of flip-flop outputs
parameter delay = 1.5;
// state encoding
parameter EMPTY = 2'b00;
parameter BETWEEN = 2'b01;
parameter READOUT = 2'b10;
parameter FULL = 2'b11;
// state vector
reg [1:0] state;
reg [1:0] state_next;
// pointers
reg [4:0] head;
reg [4:0] head_next;
reg [4:0] tail;
reg [4:0] tail_next;
reg head_plus;
reg tail_plus;
reg addr_head;
reg addr_tail;
wire do_idle;
wire do_pop;
wire do_push;
wire do_push_pop;
// sequential part
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
state <= EMPTY;
head <= 5'b0;
tail <= 5'b0;
end else begin
state <= #(delay) state_next;
head <= #(delay) head_next;
tail <= #(delay) tail_next;
end
end
// combinational parts
// Lab Note:
// Complete your design here
// Get do signal
always @(*) begin
do_idle = 1'b0;
do_pop = 1'b0;
do_push = 1'b0;
do_push_pop = 1'b0;
case ({push,pop})
2'b00: begin do_idle = 1'b1; end
2'b01: begin do_pop = 1'b1; end
2'b10: begin do_push = 1'b1; end
2'b11: begin do_push_pop = 1'b1; end
endcase
end
always @(*) begin
if (head_plus) begin
head_next = (head + 1'b1)%numOfRam;
end else begin
head_next = head;
end
if (tail_plus) begin
tail_next = (tail + 1'b1)%numOfRam;
end else begin
tail_next = tail;
end
end
always @(*) begin
if (tail == head - 1'b1) begin
almost_empty = 1'b1;
end else begin
almost_empty = 1'b0;
end
if (head == tail - 1'b1) begin
almost_full = 1'b1;
end else begin
almost_full = 1'b0;
end
oen = 1'b0;
end
// FSM
always @(*) begin
empty = 1'b0;
full = 1'b0;
error = 1'b0;
cen = 1'b0;
wen = 1'b0;
addr = 5'b0;
head_plus = 1'b0;
tail_plus = 1'b0;
addr_head = 1'b0;
addr_tail = 1'b0;
state_next = state;
case (state)
EMPTY: begin
if (do_idle || do_pop || do_push_pop) begin
error = (do_pop | do_push_pop);
state_next = EMPTY;
end else if (do_push) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end
end
BETWEEN: begin
if (do_push && !almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end else if (do_idle || do_push_pop) begin
error = do_push_pop;
state_next = BETWEEN;
end else if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_push && almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = FULL;
end
end
READOUT: begin
if (!almost_empty) begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = BETWEEN;
end else begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = EMPTY;
end
end
FULL: begin
if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_idle || do_push || do_push_pop) begin
error = (do_push | do_push_pop);
state_next = FULL;
end
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:10:13 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_RECURSIVE_EVEN1_left_N23,
Sgf_operation_RECURSIVE_EVEN1_left_N22,
Sgf_operation_RECURSIVE_EVEN1_left_N21,
Sgf_operation_RECURSIVE_EVEN1_left_N20,
Sgf_operation_RECURSIVE_EVEN1_left_N19,
Sgf_operation_RECURSIVE_EVEN1_left_N18,
Sgf_operation_RECURSIVE_EVEN1_left_N17,
Sgf_operation_RECURSIVE_EVEN1_left_N16,
Sgf_operation_RECURSIVE_EVEN1_left_N15,
Sgf_operation_RECURSIVE_EVEN1_left_N14,
Sgf_operation_RECURSIVE_EVEN1_left_N13,
Sgf_operation_RECURSIVE_EVEN1_left_N12,
Sgf_operation_RECURSIVE_EVEN1_left_N11,
Sgf_operation_RECURSIVE_EVEN1_left_N10,
Sgf_operation_RECURSIVE_EVEN1_left_N9,
Sgf_operation_RECURSIVE_EVEN1_left_N8,
Sgf_operation_RECURSIVE_EVEN1_left_N7,
Sgf_operation_RECURSIVE_EVEN1_left_N6,
Sgf_operation_RECURSIVE_EVEN1_left_N5,
Sgf_operation_RECURSIVE_EVEN1_left_N4,
Sgf_operation_RECURSIVE_EVEN1_left_N3,
Sgf_operation_RECURSIVE_EVEN1_left_N2,
Sgf_operation_RECURSIVE_EVEN1_left_N1,
Sgf_operation_RECURSIVE_EVEN1_left_N0,
Sgf_operation_RECURSIVE_EVEN1_middle_N25,
Sgf_operation_RECURSIVE_EVEN1_middle_N24,
Sgf_operation_RECURSIVE_EVEN1_middle_N23,
Sgf_operation_RECURSIVE_EVEN1_middle_N22,
Sgf_operation_RECURSIVE_EVEN1_middle_N21,
Sgf_operation_RECURSIVE_EVEN1_middle_N20,
Sgf_operation_RECURSIVE_EVEN1_middle_N19,
Sgf_operation_RECURSIVE_EVEN1_middle_N18,
Sgf_operation_RECURSIVE_EVEN1_middle_N17,
Sgf_operation_RECURSIVE_EVEN1_middle_N16,
Sgf_operation_RECURSIVE_EVEN1_middle_N15,
Sgf_operation_RECURSIVE_EVEN1_middle_N14,
Sgf_operation_RECURSIVE_EVEN1_middle_N13,
Sgf_operation_RECURSIVE_EVEN1_middle_N12,
Sgf_operation_RECURSIVE_EVEN1_middle_N11,
Sgf_operation_RECURSIVE_EVEN1_middle_N10,
Sgf_operation_RECURSIVE_EVEN1_middle_N9,
Sgf_operation_RECURSIVE_EVEN1_middle_N8,
Sgf_operation_RECURSIVE_EVEN1_middle_N7,
Sgf_operation_RECURSIVE_EVEN1_middle_N6,
Sgf_operation_RECURSIVE_EVEN1_middle_N5,
Sgf_operation_RECURSIVE_EVEN1_middle_N4,
Sgf_operation_RECURSIVE_EVEN1_middle_N3,
Sgf_operation_RECURSIVE_EVEN1_middle_N2,
Sgf_operation_RECURSIVE_EVEN1_middle_N1,
Sgf_operation_RECURSIVE_EVEN1_middle_N0,
Sgf_operation_RECURSIVE_EVEN1_right_N23,
Sgf_operation_RECURSIVE_EVEN1_right_N22,
Sgf_operation_RECURSIVE_EVEN1_right_N21,
Sgf_operation_RECURSIVE_EVEN1_right_N20,
Sgf_operation_RECURSIVE_EVEN1_right_N19,
Sgf_operation_RECURSIVE_EVEN1_right_N18,
Sgf_operation_RECURSIVE_EVEN1_right_N17,
Sgf_operation_RECURSIVE_EVEN1_right_N16,
Sgf_operation_RECURSIVE_EVEN1_right_N15,
Sgf_operation_RECURSIVE_EVEN1_right_N14,
Sgf_operation_RECURSIVE_EVEN1_right_N13,
Sgf_operation_RECURSIVE_EVEN1_right_N12,
Sgf_operation_RECURSIVE_EVEN1_right_N11,
Sgf_operation_RECURSIVE_EVEN1_right_N10,
Sgf_operation_RECURSIVE_EVEN1_right_N9,
Sgf_operation_RECURSIVE_EVEN1_right_N8,
Sgf_operation_RECURSIVE_EVEN1_right_N7,
Sgf_operation_RECURSIVE_EVEN1_right_N6,
Sgf_operation_RECURSIVE_EVEN1_right_N5,
Sgf_operation_RECURSIVE_EVEN1_right_N4,
Sgf_operation_RECURSIVE_EVEN1_right_N3,
Sgf_operation_RECURSIVE_EVEN1_right_N2,
Sgf_operation_RECURSIVE_EVEN1_right_N1, n167, n169, n170, n171, n172,
n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n310, n311, n312, n313, n314, n315, n316,
n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380,
DP_OP_36J22_124_9196_n22, DP_OP_36J22_124_9196_n21,
DP_OP_36J22_124_9196_n20, DP_OP_36J22_124_9196_n19,
DP_OP_36J22_124_9196_n18, DP_OP_36J22_124_9196_n17,
DP_OP_36J22_124_9196_n16, DP_OP_36J22_124_9196_n15,
DP_OP_36J22_124_9196_n9, DP_OP_36J22_124_9196_n8,
DP_OP_36J22_124_9196_n7, DP_OP_36J22_124_9196_n6,
DP_OP_36J22_124_9196_n5, DP_OP_36J22_124_9196_n4,
DP_OP_36J22_124_9196_n3, DP_OP_36J22_124_9196_n2,
DP_OP_36J22_124_9196_n1, DP_OP_111J22_123_4462_n727,
DP_OP_111J22_123_4462_n474, DP_OP_111J22_123_4462_n473,
DP_OP_111J22_123_4462_n472, DP_OP_111J22_123_4462_n471,
DP_OP_111J22_123_4462_n470, DP_OP_111J22_123_4462_n469,
DP_OP_111J22_123_4462_n468, DP_OP_111J22_123_4462_n467,
DP_OP_111J22_123_4462_n461, DP_OP_111J22_123_4462_n460,
DP_OP_111J22_123_4462_n459, DP_OP_111J22_123_4462_n458,
DP_OP_111J22_123_4462_n457, DP_OP_111J22_123_4462_n456,
DP_OP_111J22_123_4462_n455, DP_OP_111J22_123_4462_n454,
DP_OP_111J22_123_4462_n453, DP_OP_111J22_123_4462_n452,
DP_OP_111J22_123_4462_n448, DP_OP_111J22_123_4462_n447,
DP_OP_111J22_123_4462_n445, DP_OP_111J22_123_4462_n444,
DP_OP_111J22_123_4462_n443, DP_OP_111J22_123_4462_n442,
DP_OP_111J22_123_4462_n441, DP_OP_111J22_123_4462_n440,
DP_OP_111J22_123_4462_n439, DP_OP_111J22_123_4462_n438,
DP_OP_111J22_123_4462_n437, DP_OP_111J22_123_4462_n436,
DP_OP_111J22_123_4462_n435, DP_OP_111J22_123_4462_n431,
DP_OP_111J22_123_4462_n430, DP_OP_111J22_123_4462_n429,
DP_OP_111J22_123_4462_n428, DP_OP_111J22_123_4462_n427,
DP_OP_111J22_123_4462_n426, DP_OP_111J22_123_4462_n425,
DP_OP_111J22_123_4462_n424, DP_OP_111J22_123_4462_n423,
DP_OP_111J22_123_4462_n418, DP_OP_111J22_123_4462_n417,
DP_OP_111J22_123_4462_n415, DP_OP_111J22_123_4462_n414,
DP_OP_111J22_123_4462_n413, DP_OP_111J22_123_4462_n412,
DP_OP_111J22_123_4462_n411, DP_OP_111J22_123_4462_n410,
DP_OP_111J22_123_4462_n409, DP_OP_111J22_123_4462_n408,
DP_OP_111J22_123_4462_n407, DP_OP_111J22_123_4462_n406,
DP_OP_111J22_123_4462_n401, DP_OP_111J22_123_4462_n400,
DP_OP_111J22_123_4462_n399, DP_OP_111J22_123_4462_n398,
DP_OP_111J22_123_4462_n397, DP_OP_111J22_123_4462_n396,
DP_OP_111J22_123_4462_n395, DP_OP_111J22_123_4462_n394,
DP_OP_111J22_123_4462_n388, DP_OP_111J22_123_4462_n387,
DP_OP_111J22_123_4462_n385, DP_OP_111J22_123_4462_n384,
DP_OP_111J22_123_4462_n369, DP_OP_111J22_123_4462_n366,
DP_OP_111J22_123_4462_n365, DP_OP_111J22_123_4462_n364,
DP_OP_111J22_123_4462_n363, DP_OP_111J22_123_4462_n362,
DP_OP_111J22_123_4462_n361, DP_OP_111J22_123_4462_n360,
DP_OP_111J22_123_4462_n359, DP_OP_111J22_123_4462_n358,
DP_OP_111J22_123_4462_n356, DP_OP_111J22_123_4462_n355,
DP_OP_111J22_123_4462_n354, DP_OP_111J22_123_4462_n352,
DP_OP_111J22_123_4462_n351, DP_OP_111J22_123_4462_n350,
DP_OP_111J22_123_4462_n349, DP_OP_111J22_123_4462_n348,
DP_OP_111J22_123_4462_n347, DP_OP_111J22_123_4462_n346,
DP_OP_111J22_123_4462_n345, DP_OP_111J22_123_4462_n344,
DP_OP_111J22_123_4462_n343, DP_OP_111J22_123_4462_n342,
DP_OP_111J22_123_4462_n341, DP_OP_111J22_123_4462_n340,
DP_OP_111J22_123_4462_n339, DP_OP_111J22_123_4462_n338,
DP_OP_111J22_123_4462_n337, DP_OP_111J22_123_4462_n336,
DP_OP_111J22_123_4462_n335, DP_OP_111J22_123_4462_n334,
DP_OP_111J22_123_4462_n333, DP_OP_111J22_123_4462_n332,
DP_OP_111J22_123_4462_n330, DP_OP_111J22_123_4462_n329,
DP_OP_111J22_123_4462_n328, DP_OP_111J22_123_4462_n327,
DP_OP_111J22_123_4462_n326, DP_OP_111J22_123_4462_n325,
DP_OP_111J22_123_4462_n324, DP_OP_111J22_123_4462_n323,
DP_OP_111J22_123_4462_n322, DP_OP_111J22_123_4462_n321,
DP_OP_111J22_123_4462_n320, DP_OP_111J22_123_4462_n319,
DP_OP_111J22_123_4462_n318, DP_OP_111J22_123_4462_n317,
DP_OP_111J22_123_4462_n315, DP_OP_111J22_123_4462_n313,
DP_OP_111J22_123_4462_n312, DP_OP_111J22_123_4462_n311,
DP_OP_111J22_123_4462_n310, DP_OP_111J22_123_4462_n309,
DP_OP_111J22_123_4462_n308, DP_OP_111J22_123_4462_n305,
DP_OP_111J22_123_4462_n304, DP_OP_111J22_123_4462_n303,
DP_OP_111J22_123_4462_n302, DP_OP_111J22_123_4462_n301,
DP_OP_111J22_123_4462_n300, DP_OP_111J22_123_4462_n299,
DP_OP_111J22_123_4462_n298, DP_OP_111J22_123_4462_n297,
DP_OP_111J22_123_4462_n296, DP_OP_111J22_123_4462_n295,
DP_OP_111J22_123_4462_n294, DP_OP_111J22_123_4462_n293,
DP_OP_111J22_123_4462_n292, DP_OP_111J22_123_4462_n291,
DP_OP_111J22_123_4462_n290, DP_OP_111J22_123_4462_n289,
DP_OP_111J22_123_4462_n288, DP_OP_111J22_123_4462_n287,
DP_OP_111J22_123_4462_n286, DP_OP_111J22_123_4462_n285,
DP_OP_111J22_123_4462_n284, DP_OP_111J22_123_4462_n283,
DP_OP_111J22_123_4462_n282, DP_OP_111J22_123_4462_n281,
DP_OP_111J22_123_4462_n280, DP_OP_111J22_123_4462_n279,
DP_OP_111J22_123_4462_n278, DP_OP_111J22_123_4462_n277,
DP_OP_111J22_123_4462_n274, DP_OP_111J22_123_4462_n273,
DP_OP_111J22_123_4462_n272, DP_OP_111J22_123_4462_n271,
DP_OP_111J22_123_4462_n270, DP_OP_111J22_123_4462_n269,
DP_OP_111J22_123_4462_n268, DP_OP_111J22_123_4462_n267,
DP_OP_111J22_123_4462_n266, DP_OP_111J22_123_4462_n265,
DP_OP_111J22_123_4462_n264, DP_OP_111J22_123_4462_n263,
DP_OP_111J22_123_4462_n262, DP_OP_111J22_123_4462_n261,
DP_OP_111J22_123_4462_n260, DP_OP_111J22_123_4462_n259,
DP_OP_111J22_123_4462_n258, DP_OP_111J22_123_4462_n257,
mult_x_23_n355, mult_x_23_n351, mult_x_23_n350, mult_x_23_n343,
mult_x_23_n342, mult_x_23_n340, mult_x_23_n339, mult_x_23_n338,
mult_x_23_n337, mult_x_23_n336, mult_x_23_n335, mult_x_23_n334,
mult_x_23_n331, mult_x_23_n330, mult_x_23_n329, mult_x_23_n327,
mult_x_23_n326, mult_x_23_n325, mult_x_23_n323, mult_x_23_n322,
mult_x_23_n321, mult_x_23_n320, mult_x_23_n319, mult_x_23_n318,
mult_x_23_n317, mult_x_23_n315, mult_x_23_n314, mult_x_23_n313,
mult_x_23_n312, mult_x_23_n311, mult_x_23_n310, mult_x_23_n309,
mult_x_23_n308, mult_x_23_n306, mult_x_23_n303, mult_x_23_n302,
mult_x_23_n301, mult_x_23_n300, mult_x_23_n299, mult_x_23_n298,
mult_x_23_n297, mult_x_23_n296, mult_x_23_n295, mult_x_23_n294,
mult_x_23_n293, mult_x_23_n292, mult_x_23_n291, mult_x_23_n285,
mult_x_23_n284, mult_x_23_n281, mult_x_23_n280, mult_x_23_n265,
mult_x_23_n262, mult_x_23_n261, mult_x_23_n260, mult_x_23_n259,
mult_x_23_n258, mult_x_23_n257, mult_x_23_n256, mult_x_23_n255,
mult_x_23_n254, mult_x_23_n253, mult_x_23_n252, mult_x_23_n251,
mult_x_23_n250, mult_x_23_n249, mult_x_23_n248, mult_x_23_n247,
mult_x_23_n246, mult_x_23_n245, mult_x_23_n244, mult_x_23_n243,
mult_x_23_n242, mult_x_23_n241, mult_x_23_n240, mult_x_23_n239,
mult_x_23_n238, mult_x_23_n237, mult_x_23_n236, mult_x_23_n235,
mult_x_23_n234, mult_x_23_n233, mult_x_23_n232, mult_x_23_n231,
mult_x_23_n230, mult_x_23_n229, mult_x_23_n228, mult_x_23_n227,
mult_x_23_n226, mult_x_23_n225, mult_x_23_n224, mult_x_23_n223,
mult_x_23_n222, mult_x_23_n221, mult_x_23_n219, mult_x_23_n218,
mult_x_23_n217, mult_x_23_n216, mult_x_23_n215, mult_x_23_n214,
mult_x_23_n213, mult_x_23_n212, mult_x_23_n209, mult_x_23_n208,
mult_x_23_n207, mult_x_23_n206, mult_x_23_n205, mult_x_23_n204,
mult_x_23_n203, mult_x_23_n202, mult_x_23_n201, mult_x_23_n200,
mult_x_23_n199, mult_x_23_n198, mult_x_23_n197, mult_x_23_n196,
mult_x_23_n195, mult_x_23_n194, mult_x_23_n191, mult_x_23_n190,
mult_x_23_n189, mult_x_23_n188, mult_x_23_n187, mult_x_23_n186,
mult_x_23_n185, mult_x_23_n184, mult_x_23_n183, mult_x_23_n182,
mult_x_23_n181, mult_x_23_n180, mult_x_23_n177, mult_x_23_n176,
mult_x_23_n175, mult_x_23_n174, mult_x_23_n173, mult_x_23_n172,
mult_x_23_n171, mult_x_23_n170, mult_x_23_n169, mult_x_23_n168,
mult_x_23_n165, mult_x_23_n164, mult_x_23_n163, mult_x_23_n162,
mult_x_23_n161, mult_x_23_n160, mult_x_55_n363, mult_x_55_n361,
mult_x_55_n359, mult_x_55_n357, mult_x_55_n351, mult_x_55_n350,
mult_x_55_n348, mult_x_55_n347, mult_x_55_n346, mult_x_55_n345,
mult_x_55_n344, mult_x_55_n343, mult_x_55_n342, mult_x_55_n339,
mult_x_55_n338, mult_x_55_n337, mult_x_55_n335, mult_x_55_n334,
mult_x_55_n331, mult_x_55_n330, mult_x_55_n329, mult_x_55_n328,
mult_x_55_n327, mult_x_55_n326, mult_x_55_n323, mult_x_55_n322,
mult_x_55_n321, mult_x_55_n320, mult_x_55_n317, mult_x_55_n316,
mult_x_55_n314, mult_x_55_n311, mult_x_55_n307, mult_x_55_n306,
mult_x_55_n305, mult_x_55_n304, mult_x_55_n301, mult_x_55_n300,
mult_x_55_n299, mult_x_55_n298, mult_x_55_n297, mult_x_55_n296,
mult_x_55_n295, mult_x_55_n294, mult_x_55_n293, mult_x_55_n292,
mult_x_55_n291, mult_x_55_n290, mult_x_55_n289, mult_x_55_n288,
mult_x_55_n282, mult_x_55_n280, mult_x_55_n273, mult_x_55_n267,
mult_x_55_n264, mult_x_55_n263, mult_x_55_n262, mult_x_55_n261,
mult_x_55_n260, mult_x_55_n259, mult_x_55_n258, mult_x_55_n257,
mult_x_55_n256, mult_x_55_n255, mult_x_55_n254, mult_x_55_n253,
mult_x_55_n252, mult_x_55_n251, mult_x_55_n250, mult_x_55_n249,
mult_x_55_n248, mult_x_55_n247, mult_x_55_n246, mult_x_55_n245,
mult_x_55_n244, mult_x_55_n243, mult_x_55_n242, mult_x_55_n241,
mult_x_55_n240, mult_x_55_n239, mult_x_55_n238, mult_x_55_n237,
mult_x_55_n236, mult_x_55_n235, mult_x_55_n234, mult_x_55_n233,
mult_x_55_n232, mult_x_55_n231, mult_x_55_n230, mult_x_55_n229,
mult_x_55_n228, mult_x_55_n227, mult_x_55_n226, mult_x_55_n225,
mult_x_55_n224, mult_x_55_n223, mult_x_55_n221, mult_x_55_n220,
mult_x_55_n219, mult_x_55_n218, mult_x_55_n217, mult_x_55_n216,
mult_x_55_n215, mult_x_55_n214, mult_x_55_n211, mult_x_55_n210,
mult_x_55_n209, mult_x_55_n208, mult_x_55_n207, mult_x_55_n206,
mult_x_55_n205, mult_x_55_n204, mult_x_55_n203, mult_x_55_n202,
mult_x_55_n201, mult_x_55_n200, mult_x_55_n199, mult_x_55_n198,
mult_x_55_n197, mult_x_55_n196, mult_x_55_n195, mult_x_55_n194,
mult_x_55_n193, mult_x_55_n192, mult_x_55_n191, mult_x_55_n190,
mult_x_55_n189, mult_x_55_n188, mult_x_55_n187, mult_x_55_n186,
mult_x_55_n185, mult_x_55_n184, mult_x_55_n183, mult_x_55_n182,
mult_x_55_n179, mult_x_55_n178, mult_x_55_n177, mult_x_55_n176,
mult_x_55_n175, mult_x_55_n174, mult_x_55_n173, mult_x_55_n172,
mult_x_55_n171, mult_x_55_n170, mult_x_55_n169, mult_x_55_n168,
mult_x_55_n167, mult_x_55_n166, mult_x_55_n165, mult_x_55_n164,
mult_x_55_n163, mult_x_55_n162, n390, n391, n392, n393, n394, n395,
n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450,
n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
n495, n496, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:1] Sgf_operation_Result;
wire [25:0] Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] Sgf_operation_RECURSIVE_EVEN1_Q_left;
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_24_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_25_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n2406), .Q(Op_MY[31]) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[0]), .QN(n2390) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n2407), .Q(Op_MX[21]), .QN(n414) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n2407), .Q(Op_MX[19]), .QN(n420) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n2407), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n2408), .Q(Op_MX[12]), .QN(n589) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n2408), .Q(Op_MX[8]), .QN(n575) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n2409), .Q(Op_MX[1]), .QN(n576) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n2409), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n2411),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n2411), .Q(FSM_add_overflow_flag), .QN(n2395) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n2413), .Q(Op_MY[14]), .QN(n528) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n2413), .Q(Op_MY[13]), .QN(n588) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n2413), .Q(Op_MY[12]), .QN(n551) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n2414), .Q(Op_MY[7]), .QN(n413) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n2414), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n2414), .Q(Op_MY[2]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n2414), .Q(Op_MY[1]), .QN(n403) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n2415), .Q(Op_MY[0]), .QN(n566) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n2415), .Q(zero_flag), .QN(n2398) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n238), .CK(
clk), .RN(n2403), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n237), .CK(
clk), .RN(n2402), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(
clk), .RN(n2401), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(
clk), .RN(n2401), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(
clk), .RN(n2401), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(n2401), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(n2401), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(n2401), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[23]) );
CMPR32X2TS DP_OP_36J22_124_9196_U9 ( .A(DP_OP_36J22_124_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J22_124_9196_n9), .CO(
DP_OP_36J22_124_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J22_124_9196_U8 ( .A(DP_OP_36J22_124_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J22_124_9196_n8), .CO(
DP_OP_36J22_124_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J22_124_9196_U7 ( .A(DP_OP_36J22_124_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J22_124_9196_n7), .CO(
DP_OP_36J22_124_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J22_124_9196_U6 ( .A(DP_OP_36J22_124_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J22_124_9196_n6), .CO(
DP_OP_36J22_124_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J22_124_9196_U5 ( .A(DP_OP_36J22_124_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J22_124_9196_n5), .CO(
DP_OP_36J22_124_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J22_124_9196_U4 ( .A(DP_OP_36J22_124_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J22_124_9196_n4), .CO(
DP_OP_36J22_124_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J22_124_9196_U3 ( .A(DP_OP_36J22_124_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J22_124_9196_n3), .CO(
DP_OP_36J22_124_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J22_124_9196_U2 ( .A(n527), .B(S_Oper_A_exp[8]), .C(
DP_OP_36J22_124_9196_n2), .CO(DP_OP_36J22_124_9196_n1), .S(
Exp_module_Data_S[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n2419), .Q(final_result_ieee[31]), .QN(n2399) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[7]), .QN(n2397) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[10]), .QN(n2396) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[6]), .QN(n2393) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[4]), .QN(n2392) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[5]), .QN(n2389) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[9]), .QN(n2388) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[3]), .QN(n2387) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n2406), .Q(FSM_selector_A),
.QN(n2394) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[8]), .QN(n2384) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n2415), .Q(
FSM_selector_B[1]), .QN(n2382) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n2419), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n2420), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n2420), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n2420), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n2420), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n2420), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n2420), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n2420), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n2420), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n2420), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n2420), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n2421), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n2421), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n2421), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n2421), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n2421), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n2421), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n2421), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n2421), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n2421), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n2421), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n2422), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n2422), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n2419), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n2419), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n2419), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n2419), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n2419), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n2419), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n2419), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n2419), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n2416), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n2418),
.Q(underflow_flag), .QN(n2400) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[2]), .QN(n2383) );
CMPR42X1TS DP_OP_111J22_123_4462_U319 ( .A(DP_OP_111J22_123_4462_n447), .B(
DP_OP_111J22_123_4462_n363), .C(DP_OP_111J22_123_4462_n364), .D(
DP_OP_111J22_123_4462_n460), .ICI(DP_OP_111J22_123_4462_n473), .S(
DP_OP_111J22_123_4462_n361), .ICO(DP_OP_111J22_123_4462_n359), .CO(
DP_OP_111J22_123_4462_n360) );
CMPR42X1TS DP_OP_111J22_123_4462_U310 ( .A(DP_OP_111J22_123_4462_n417), .B(
DP_OP_111J22_123_4462_n340), .C(DP_OP_111J22_123_4462_n344), .D(
DP_OP_111J22_123_4462_n430), .ICI(DP_OP_111J22_123_4462_n443), .S(
DP_OP_111J22_123_4462_n338), .ICO(DP_OP_111J22_123_4462_n336), .CO(
DP_OP_111J22_123_4462_n337) );
CMPR42X2TS DP_OP_111J22_123_4462_U309 ( .A(DP_OP_111J22_123_4462_n456), .B(
DP_OP_111J22_123_4462_n469), .C(DP_OP_111J22_123_4462_n345), .D(
DP_OP_111J22_123_4462_n341), .ICI(DP_OP_111J22_123_4462_n338), .S(
DP_OP_111J22_123_4462_n335), .ICO(DP_OP_111J22_123_4462_n333), .CO(
DP_OP_111J22_123_4462_n334) );
CMPR42X1TS DP_OP_111J22_123_4462_U307 ( .A(DP_OP_111J22_123_4462_n339), .B(
DP_OP_111J22_123_4462_n332), .C(DP_OP_111J22_123_4462_n442), .D(
DP_OP_111J22_123_4462_n429), .ICI(DP_OP_111J22_123_4462_n455), .S(
DP_OP_111J22_123_4462_n330), .ICO(DP_OP_111J22_123_4462_n328), .CO(
DP_OP_111J22_123_4462_n329) );
CMPR42X2TS DP_OP_111J22_123_4462_U303 ( .A(DP_OP_111J22_123_4462_n441), .B(
DP_OP_111J22_123_4462_n454), .C(DP_OP_111J22_123_4462_n329), .D(
DP_OP_111J22_123_4462_n325), .ICI(DP_OP_111J22_123_4462_n322), .S(
DP_OP_111J22_123_4462_n319), .ICO(DP_OP_111J22_123_4462_n317), .CO(
DP_OP_111J22_123_4462_n318) );
CMPR42X2TS DP_OP_111J22_123_4462_U299 ( .A(DP_OP_111J22_123_4462_n453), .B(
DP_OP_111J22_123_4462_n440), .C(DP_OP_111J22_123_4462_n321), .D(
DP_OP_111J22_123_4462_n313), .ICI(DP_OP_111J22_123_4462_n317), .S(
DP_OP_111J22_123_4462_n310), .ICO(DP_OP_111J22_123_4462_n308), .CO(
DP_OP_111J22_123_4462_n309) );
CMPR42X2TS DP_OP_111J22_123_4462_U295 ( .A(DP_OP_111J22_123_4462_n426), .B(
DP_OP_111J22_123_4462_n439), .C(DP_OP_111J22_123_4462_n312), .D(
DP_OP_111J22_123_4462_n303), .ICI(DP_OP_111J22_123_4462_n308), .S(
DP_OP_111J22_123_4462_n300), .ICO(DP_OP_111J22_123_4462_n298), .CO(
DP_OP_111J22_123_4462_n299) );
CMPR42X1TS DP_OP_111J22_123_4462_U290 ( .A(DP_OP_111J22_123_4462_n388), .B(
DP_OP_111J22_123_4462_n290), .C(DP_OP_111J22_123_4462_n437), .D(
DP_OP_111J22_123_4462_n399), .ICI(DP_OP_111J22_123_4462_n294), .S(
DP_OP_111J22_123_4462_n288), .ICO(DP_OP_111J22_123_4462_n286), .CO(
DP_OP_111J22_123_4462_n287) );
CMPR42X2TS DP_OP_111J22_123_4462_U289 ( .A(DP_OP_111J22_123_4462_n411), .B(
DP_OP_111J22_123_4462_n424), .C(DP_OP_111J22_123_4462_n295), .D(
DP_OP_111J22_123_4462_n288), .ICI(DP_OP_111J22_123_4462_n291), .S(
DP_OP_111J22_123_4462_n285), .ICO(DP_OP_111J22_123_4462_n283), .CO(
DP_OP_111J22_123_4462_n284) );
CMPR42X1TS DP_OP_111J22_123_4462_U288 ( .A(DP_OP_111J22_123_4462_n436), .B(
DP_OP_111J22_123_4462_n289), .C(DP_OP_111J22_123_4462_n387), .D(
DP_OP_111J22_123_4462_n398), .ICI(DP_OP_111J22_123_4462_n423), .S(
DP_OP_111J22_123_4462_n282), .ICO(DP_OP_111J22_123_4462_n280), .CO(
DP_OP_111J22_123_4462_n281) );
CMPR42X2TS DP_OP_111J22_123_4462_U284 ( .A(DP_OP_111J22_123_4462_n397), .B(
DP_OP_111J22_123_4462_n409), .C(DP_OP_111J22_123_4462_n274), .D(
DP_OP_111J22_123_4462_n281), .ICI(DP_OP_111J22_123_4462_n277), .S(
DP_OP_111J22_123_4462_n272), .ICO(DP_OP_111J22_123_4462_n270), .CO(
DP_OP_111J22_123_4462_n271) );
CMPR42X2TS DP_OP_111J22_123_4462_U282 ( .A(DP_OP_111J22_123_4462_n408), .B(
DP_OP_111J22_123_4462_n269), .C(DP_OP_111J22_123_4462_n396), .D(
DP_OP_111J22_123_4462_n273), .ICI(DP_OP_111J22_123_4462_n270), .S(
DP_OP_111J22_123_4462_n267), .ICO(DP_OP_111J22_123_4462_n265), .CO(
DP_OP_111J22_123_4462_n266) );
CMPR42X1TS DP_OP_111J22_123_4462_U280 ( .A(DP_OP_111J22_123_4462_n264), .B(
DP_OP_111J22_123_4462_n385), .C(DP_OP_111J22_123_4462_n268), .D(
DP_OP_111J22_123_4462_n395), .ICI(DP_OP_111J22_123_4462_n265), .S(
DP_OP_111J22_123_4462_n262), .ICO(DP_OP_111J22_123_4462_n260), .CO(
DP_OP_111J22_123_4462_n261) );
CMPR42X2TS mult_x_23_U218 ( .A(mult_x_23_n342), .B(mult_x_23_n318), .C(
mult_x_23_n330), .D(mult_x_23_n259), .ICI(mult_x_23_n260), .S(
mult_x_23_n257), .ICO(mult_x_23_n255), .CO(mult_x_23_n256) );
CMPR42X2TS mult_x_23_U216 ( .A(mult_x_23_n329), .B(mult_x_23_n317), .C(
mult_x_23_n258), .D(mult_x_23_n255), .ICI(mult_x_23_n254), .S(
mult_x_23_n252), .ICO(mult_x_23_n250), .CO(mult_x_23_n251) );
CMPR42X2TS mult_x_23_U212 ( .A(mult_x_23_n291), .B(mult_x_23_n351), .C(
mult_x_23_n339), .D(mult_x_23_n327), .ICI(mult_x_23_n248), .S(
mult_x_23_n242), .ICO(mult_x_23_n240), .CO(mult_x_23_n241) );
CMPR42X2TS mult_x_23_U211 ( .A(mult_x_23_n315), .B(mult_x_23_n303), .C(
mult_x_23_n246), .D(mult_x_23_n243), .ICI(mult_x_23_n242), .S(
mult_x_23_n239), .ICO(mult_x_23_n237), .CO(mult_x_23_n238) );
CMPR42X2TS mult_x_23_U209 ( .A(mult_x_23_n350), .B(mult_x_23_n338), .C(
mult_x_23_n302), .D(mult_x_23_n236), .ICI(mult_x_23_n240), .S(
mult_x_23_n234), .ICO(mult_x_23_n232), .CO(mult_x_23_n233) );
CMPR42X1TS mult_x_23_U208 ( .A(mult_x_23_n326), .B(mult_x_23_n314), .C(
mult_x_23_n237), .D(mult_x_23_n241), .ICI(mult_x_23_n234), .S(
mult_x_23_n231), .ICO(mult_x_23_n229), .CO(mult_x_23_n230) );
CMPR42X2TS mult_x_23_U201 ( .A(mult_x_23_n227), .B(mult_x_23_n219), .C(
mult_x_23_n225), .D(mult_x_23_n217), .ICI(mult_x_23_n221), .S(
mult_x_23_n214), .ICO(mult_x_23_n212), .CO(mult_x_23_n213) );
CMPR42X1TS mult_x_23_U198 ( .A(mult_x_23_n311), .B(mult_x_23_n335), .C(
mult_x_23_n323), .D(mult_x_23_n209), .ICI(mult_x_23_n215), .S(
mult_x_23_n207), .ICO(mult_x_23_n205), .CO(mult_x_23_n206) );
CMPR42X1TS mult_x_23_U192 ( .A(n590), .B(mult_x_23_n285), .C(mult_x_23_n321),
.D(mult_x_23_n297), .ICI(mult_x_23_n309), .S(mult_x_23_n191), .ICO(
mult_x_23_n189), .CO(mult_x_23_n190) );
CMPR42X2TS mult_x_23_U191 ( .A(mult_x_23_n200), .B(mult_x_23_n197), .C(
mult_x_23_n191), .D(mult_x_23_n198), .ICI(mult_x_23_n194), .S(
mult_x_23_n188), .ICO(mult_x_23_n186), .CO(mult_x_23_n187) );
CMPR42X1TS mult_x_23_U190 ( .A(n398), .B(n442), .C(mult_x_23_n284), .D(
mult_x_23_n308), .ICI(mult_x_23_n296), .S(mult_x_23_n185), .ICO(
mult_x_23_n183), .CO(mult_x_23_n184) );
CMPR42X1TS mult_x_23_U189 ( .A(mult_x_23_n320), .B(mult_x_23_n189), .C(
mult_x_23_n190), .D(mult_x_23_n185), .ICI(mult_x_23_n186), .S(
mult_x_23_n182), .ICO(mult_x_23_n180), .CO(mult_x_23_n181) );
CMPR42X2TS mult_x_23_U186 ( .A(mult_x_23_n295), .B(mult_x_23_n183), .C(
mult_x_23_n177), .D(mult_x_23_n184), .ICI(mult_x_23_n180), .S(
mult_x_23_n175), .ICO(mult_x_23_n173), .CO(mult_x_23_n174) );
CMPR42X1TS mult_x_55_U222 ( .A(mult_x_55_n327), .B(mult_x_55_n339), .C(
mult_x_55_n351), .D(mult_x_55_n363), .ICI(mult_x_55_n267), .S(
mult_x_55_n264), .ICO(mult_x_55_n262), .CO(mult_x_55_n263) );
CMPR42X2TS mult_x_55_U220 ( .A(mult_x_55_n350), .B(mult_x_55_n326), .C(
mult_x_55_n338), .D(mult_x_55_n261), .ICI(mult_x_55_n262), .S(
mult_x_55_n259), .ICO(mult_x_55_n257), .CO(mult_x_55_n258) );
CMPR42X2TS mult_x_55_U215 ( .A(mult_x_55_n348), .B(mult_x_55_n251), .C(
mult_x_55_n255), .D(mult_x_55_n249), .ICI(mult_x_55_n252), .S(
mult_x_55_n247), .ICO(mult_x_55_n245), .CO(mult_x_55_n246) );
CMPR42X1TS mult_x_55_U214 ( .A(mult_x_55_n299), .B(mult_x_55_n323), .C(
mult_x_55_n347), .D(mult_x_55_n311), .ICI(mult_x_55_n248), .S(
mult_x_55_n244), .ICO(mult_x_55_n242), .CO(mult_x_55_n243) );
CMPR42X2TS mult_x_55_U211 ( .A(mult_x_55_n322), .B(mult_x_55_n334), .C(
mult_x_55_n273), .D(mult_x_55_n298), .ICI(mult_x_55_n239), .S(
mult_x_55_n236), .ICO(mult_x_55_n234), .CO(mult_x_55_n235) );
CMPR42X1TS mult_x_55_U210 ( .A(mult_x_55_n346), .B(mult_x_55_n238), .C(
mult_x_55_n242), .D(mult_x_55_n243), .ICI(mult_x_55_n236), .S(
mult_x_55_n233), .ICO(mult_x_55_n231), .CO(mult_x_55_n232) );
CMPR42X1TS mult_x_55_U208 ( .A(mult_x_55_n321), .B(mult_x_55_n345), .C(
mult_x_55_n297), .D(mult_x_55_n357), .ICI(mult_x_55_n230), .S(
mult_x_55_n228), .ICO(mult_x_55_n226), .CO(mult_x_55_n227) );
CMPR42X1TS mult_x_55_U204 ( .A(mult_x_55_n320), .B(mult_x_55_n344), .C(
mult_x_55_n296), .D(n403), .ICI(mult_x_55_n221), .S(mult_x_55_n219),
.ICO(mult_x_55_n217), .CO(mult_x_55_n218) );
CMPR42X2TS mult_x_55_U203 ( .A(mult_x_55_n226), .B(mult_x_55_n229), .C(
mult_x_55_n227), .D(mult_x_55_n223), .ICI(mult_x_55_n219), .S(
mult_x_55_n216), .ICO(mult_x_55_n214), .CO(mult_x_55_n215) );
CMPR42X1TS mult_x_55_U200 ( .A(mult_x_55_n307), .B(mult_x_55_n343), .C(
mult_x_55_n331), .D(mult_x_55_n295), .ICI(mult_x_55_n220), .S(
mult_x_55_n209), .ICO(mult_x_55_n207), .CO(mult_x_55_n208) );
CMPR42X2TS mult_x_55_U199 ( .A(mult_x_55_n211), .B(mult_x_55_n217), .C(
mult_x_55_n218), .D(mult_x_55_n209), .ICI(mult_x_55_n214), .S(
mult_x_55_n206), .ICO(mult_x_55_n204), .CO(mult_x_55_n205) );
CMPR42X2TS mult_x_55_U197 ( .A(mult_x_55_n306), .B(mult_x_55_n330), .C(
mult_x_55_n294), .D(mult_x_55_n342), .ICI(mult_x_55_n207), .S(
mult_x_55_n201), .ICO(mult_x_55_n199), .CO(mult_x_55_n200) );
CMPR42X2TS mult_x_55_U196 ( .A(mult_x_55_n210), .B(mult_x_55_n203), .C(
mult_x_55_n208), .D(mult_x_55_n201), .ICI(mult_x_55_n204), .S(
mult_x_55_n198), .ICO(mult_x_55_n196), .CO(mult_x_55_n197) );
CMPR42X1TS mult_x_55_U194 ( .A(mult_x_55_n195), .B(mult_x_55_n329), .C(
mult_x_55_n317), .D(mult_x_55_n305), .ICI(mult_x_55_n202), .S(
mult_x_55_n193), .ICO(mult_x_55_n191), .CO(mult_x_55_n192) );
CMPR42X1TS mult_x_55_U192 ( .A(mult_x_55_n194), .B(mult_x_55_n282), .C(
mult_x_55_n316), .D(mult_x_55_n304), .ICI(mult_x_55_n328), .S(
mult_x_55_n187), .ICO(mult_x_55_n185), .CO(mult_x_55_n186) );
CMPR42X1TS mult_x_55_U191 ( .A(mult_x_55_n292), .B(mult_x_55_n191), .C(
mult_x_55_n187), .D(mult_x_55_n192), .ICI(mult_x_55_n188), .S(
mult_x_55_n184), .ICO(mult_x_55_n182), .CO(mult_x_55_n183) );
CMPR42X2TS mult_x_23_U197 ( .A(mult_x_23_n299), .B(mult_x_23_n218), .C(
mult_x_23_n216), .D(mult_x_23_n207), .ICI(mult_x_23_n212), .S(
mult_x_23_n204), .ICO(mult_x_23_n202), .CO(mult_x_23_n203) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n2414), .Q(Op_MY[10]) );
CMPR42X2TS DP_OP_111J22_123_4462_U317 ( .A(DP_OP_111J22_123_4462_n362), .B(
DP_OP_111J22_123_4462_n358), .C(DP_OP_111J22_123_4462_n472), .D(
DP_OP_111J22_123_4462_n459), .ICI(DP_OP_111J22_123_4462_n359), .S(
DP_OP_111J22_123_4462_n356), .ICO(DP_OP_111J22_123_4462_n354), .CO(
DP_OP_111J22_123_4462_n355) );
CMPR42X2TS DP_OP_111J22_123_4462_U296 ( .A(DP_OP_111J22_123_4462_n452), .B(
DP_OP_111J22_123_4462_n401), .C(DP_OP_111J22_123_4462_n413), .D(
DP_OP_111J22_123_4462_n305), .ICI(DP_OP_111J22_123_4462_n311), .S(
DP_OP_111J22_123_4462_n303), .ICO(DP_OP_111J22_123_4462_n301), .CO(
DP_OP_111J22_123_4462_n302) );
CMPR42X2TS DP_OP_111J22_123_4462_U287 ( .A(DP_OP_111J22_123_4462_n410), .B(
DP_OP_111J22_123_4462_n286), .C(DP_OP_111J22_123_4462_n282), .D(
DP_OP_111J22_123_4462_n287), .ICI(DP_OP_111J22_123_4462_n283), .S(
DP_OP_111J22_123_4462_n279), .ICO(DP_OP_111J22_123_4462_n277), .CO(
DP_OP_111J22_123_4462_n278) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n2412), .Q(Op_MY[22]), .QN(n573) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n2413), .Q(Op_MY[18]), .QN(n574) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n2413), .Q(Op_MY[11]), .QN(DP_OP_111J22_123_4462_n727) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n2414), .Q(Op_MY[9]), .QN(n584) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n2414), .Q(Op_MY[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n2409), .Q(Op_MX[0]), .QN(n585) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n2415),
.Q(exp_oper_result[8]) );
MDFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_0_ ( .D0(n585), .D1(
1'b1), .S0(n455), .CK(clk), .Q(n2381) );
DFFRX1TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n2424), .Q(
FS_Module_state_reg[3]), .QN(n562) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n2413), .Q(Op_MY[20]), .QN(n592) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n2408), .Q(Op_MX[11]), .QN(n561) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n2406), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n2406), .Q(Op_MX[29]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n380), .CK(
clk), .RN(n2403), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n2412), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n2406), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n2412), .Q(Op_MY[27]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n1955),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n1955),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n2415),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n2415),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(clk), .RN(n2415),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n2412), .Q(Op_MY[23]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n236), .CK(
clk), .RN(n2402), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(n2402), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(
clk), .RN(n2403), .Q(P_Sgf[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n2406), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n2406), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n2406), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n2406), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n2407), .Q(Op_MX[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n2409),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n2409),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n2409),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(clk), .RN(n2409),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n2409),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n2410),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n2410),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n2410),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n2410),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n2410),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n2410),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n2410),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n2410),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n2410),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n2410),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n2411),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n2411),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n2411),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n2411),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n2411),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n2411),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .RN(n2411),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n2411),
.Q(Add_result[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n2412), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n2412), .Q(Op_MY[25]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n2415),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n2415),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n1955),
.Q(exp_oper_result[6]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n2412), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n2412), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n2412), .Q(Op_MY[24]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n261), .CK(
clk), .RN(n2424), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n260), .CK(
clk), .RN(n2405), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n259), .CK(
clk), .RN(n2405), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n258), .CK(
clk), .RN(n2405), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n257), .CK(
clk), .RN(n2405), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n256), .CK(
clk), .RN(n2405), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n255), .CK(
clk), .RN(n2405), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n254), .CK(
clk), .RN(n2405), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n253), .CK(
clk), .RN(n2405), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n252), .CK(
clk), .RN(n2405), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n251), .CK(
clk), .RN(n2405), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n250), .CK(
clk), .RN(n2404), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n249), .CK(
clk), .RN(n2404), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n248), .CK(
clk), .RN(n2404), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n247), .CK(
clk), .RN(n2404), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n246), .CK(
clk), .RN(n2404), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n245), .CK(
clk), .RN(n2404), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n244), .CK(
clk), .RN(n2404), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n243), .CK(
clk), .RN(n2404), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n242), .CK(
clk), .RN(n2404), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n241), .CK(
clk), .RN(n2404), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n240), .CK(
clk), .RN(n2403), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n239), .CK(
clk), .RN(n2403), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n235), .CK(
clk), .RN(n2402), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(
clk), .RN(n2402), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(
clk), .RN(n2403), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(n2402), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(
clk), .RN(n2402), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(
clk), .RN(n2403), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(n2402), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(
clk), .RN(n2402), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(n2402), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(n2401), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(n2401), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(n2401), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(
clk), .RN(n2401), .Q(P_Sgf[11]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n2407), .Q(Op_MX[15]), .QN(n421) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n2409), .Q(Op_MX[2]), .QN(n572) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n2407), .Q(Op_MX[17]), .QN(n419) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n2408), .Q(Op_MX[13]), .QN(n596) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n2413), .Q(n398), .QN(n590) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n2412), .Q(n399), .QN(n407) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n2408), .Q(n397), .QN(n579) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(clk), .Q(
Sgf_operation_Result[3]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(clk), .Q(
Sgf_operation_Result[4]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(clk), .Q(
Sgf_operation_Result[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n2407), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n2408), .Q(n400), .QN(n569) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n2408), .Q(Op_MX[6]), .QN(n393) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n2408), .Q(n401), .QN(n586) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n2408), .Q(Op_MX[4]), .QN(n394) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n1955), .Q(FSM_selector_C),
.QN(n2391) );
DFFSX1TS Sel_B_Q_reg_0_ ( .D(n2423), .CK(clk), .SN(n2415), .Q(n2386), .QN(
FSM_selector_B[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n2414), .Q(Op_MY[4]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n2409), .Q(Op_MX[3]), .QN(n577) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n2407), .Q(Op_MX[22]), .QN(n568) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n2407), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n2414), .Q(Op_MY[5]), .QN(n418) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n2407), .Q(Op_MX[20]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n2413), .Q(Op_MY[17]), .QN(n396) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n2413), .Q(Op_MY[15]), .QN(n392) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n2413), .Q(Op_MY[19]), .QN(n391) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(clk), .Q(
Sgf_operation_Result[5]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(clk), .Q(
Sgf_operation_Result[10]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(clk), .Q(
Sgf_operation_Result[6]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(clk), .Q(
Sgf_operation_Result[7]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(clk), .Q(
Sgf_operation_Result[9]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(clk), .Q(
Sgf_operation_Result[11]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(clk), .Q(
Sgf_operation_Result[1]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(clk), .Q(
Sgf_operation_Result[2]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n2408), .Q(Op_MX[10]), .QN(n581) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n2414), .Q(Op_MY[3]), .QN(n415) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[1]), .QN(n2385) );
CMPR42X1TS mult_x_55_U213 ( .A(mult_x_55_n335), .B(mult_x_55_n359), .C(
mult_x_55_n250), .D(mult_x_55_n245), .ICI(mult_x_55_n244), .S(
mult_x_55_n241), .ICO(mult_x_55_n239), .CO(mult_x_55_n240) );
CMPR32X2TS DP_OP_36J22_124_9196_U10 ( .A(S_Oper_A_exp[0]), .B(n1954), .C(
DP_OP_36J22_124_9196_n22), .CO(DP_OP_36J22_124_9196_n9), .S(
Exp_module_Data_S[0]) );
CMPR42X1TS mult_x_55_U193 ( .A(mult_x_55_n293), .B(mult_x_55_n199), .C(
mult_x_55_n200), .D(mult_x_55_n193), .ICI(mult_x_55_n196), .S(
mult_x_55_n190), .ICO(mult_x_55_n188), .CO(mult_x_55_n189) );
CMPR42X1TS mult_x_23_U205 ( .A(mult_x_23_n325), .B(mult_x_23_n228), .C(
mult_x_23_n233), .D(mult_x_23_n226), .ICI(mult_x_23_n229), .S(
mult_x_23_n223), .ICO(mult_x_23_n221), .CO(mult_x_23_n222) );
XOR2X1TS U405 ( .A(n861), .B(n860), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
BUFX3TS U406 ( .A(n2305), .Y(n2088) );
BUFX3TS U407 ( .A(n2305), .Y(n2225) );
INVX2TS U408 ( .A(n2375), .Y(n2374) );
NAND2X1TS U409 ( .A(n933), .B(n937), .Y(n934) );
AOI21X2TS U410 ( .A0(n1377), .A1(n1371), .B0(n1370), .Y(n1376) );
BUFX3TS U411 ( .A(n2305), .Y(n2337) );
OAI21X1TS U412 ( .A0(n939), .A1(n938), .B0(n937), .Y(n940) );
INVX2TS U413 ( .A(n982), .Y(n1005) );
NOR2X6TS U414 ( .A(n1999), .B(n1998), .Y(n1935) );
OR3X1TS U415 ( .A(underflow_flag), .B(overflow_flag), .C(n2378), .Y(n2375)
);
NAND2X2TS U416 ( .A(n1933), .B(n1953), .Y(n2305) );
AOI21X1TS U417 ( .A0(n2150), .A1(n2107), .B0(n2106), .Y(n2126) );
NAND2XLTS U418 ( .A(n1946), .B(FS_Module_state_reg[1]), .Y(n1933) );
NOR2X2TS U419 ( .A(n2390), .B(FS_Module_state_reg[1]), .Y(n2265) );
INVX2TS U420 ( .A(n2372), .Y(n2378) );
NAND2X2TS U421 ( .A(n1371), .B(n789), .Y(n790) );
OAI21X1TS U422 ( .A0(n1182), .A1(n1184), .B0(n1185), .Y(n841) );
NAND2X1TS U423 ( .A(DP_OP_111J22_123_4462_n285), .B(
DP_OP_111J22_123_4462_n292), .Y(n858) );
NAND2X2TS U424 ( .A(DP_OP_111J22_123_4462_n279), .B(
DP_OP_111J22_123_4462_n284), .Y(n922) );
NAND2X2TS U425 ( .A(DP_OP_111J22_123_4462_n293), .B(
DP_OP_111J22_123_4462_n299), .Y(n1373) );
NOR2X2TS U426 ( .A(DP_OP_111J22_123_4462_n279), .B(
DP_OP_111J22_123_4462_n284), .Y(n883) );
NAND2X1TS U427 ( .A(n984), .B(n642), .Y(n644) );
INVX2TS U428 ( .A(n1949), .Y(n2128) );
NAND2X2TS U429 ( .A(n899), .B(n563), .Y(n1570) );
CLKBUFX2TS U430 ( .A(n2370), .Y(n2372) );
OR2X2TS U431 ( .A(DP_OP_111J22_123_4462_n271), .B(DP_OP_111J22_123_4462_n267), .Y(n563) );
NOR2X2TS U432 ( .A(DP_OP_111J22_123_4462_n327), .B(
DP_OP_111J22_123_4462_n334), .Y(n1536) );
NOR2X4TS U433 ( .A(DP_OP_111J22_123_4462_n319), .B(
DP_OP_111J22_123_4462_n326), .Y(n1382) );
NOR2X1TS U434 ( .A(n1007), .B(n1106), .Y(n640) );
OAI21X2TS U435 ( .A0(n1222), .A1(n1227), .B0(n1223), .Y(n1208) );
OAI21X1TS U436 ( .A0(n985), .A1(n991), .B0(n986), .Y(n641) );
NAND2X1TS U437 ( .A(mult_x_23_n204), .B(mult_x_23_n213), .Y(n1223) );
NAND2X1TS U438 ( .A(mult_x_55_n216), .B(mult_x_55_n224), .Y(n1002) );
NOR2X2TS U439 ( .A(mult_x_23_n204), .B(mult_x_23_n213), .Y(n1222) );
NOR2X2TS U440 ( .A(mult_x_55_n206), .B(mult_x_55_n215), .Y(n997) );
NOR2X1TS U441 ( .A(n2385), .B(n2390), .Y(n1957) );
NOR2X2TS U442 ( .A(mult_x_23_n188), .B(mult_x_23_n195), .Y(n1210) );
NOR2X1TS U443 ( .A(n1967), .B(n2395), .Y(n1946) );
OAI21X2TS U444 ( .A0(n1035), .A1(n1032), .B0(n1033), .Y(n1021) );
OR2X2TS U445 ( .A(DP_OP_111J22_123_4462_n365), .B(DP_OP_111J22_123_4462_n361), .Y(n406) );
CMPR32X2TS U446 ( .A(n1604), .B(n1603), .C(n1602), .CO(
DP_OP_111J22_123_4462_n304), .S(DP_OP_111J22_123_4462_n305) );
CMPR32X2TS U447 ( .A(n1568), .B(n1567), .C(n1566), .CO(
DP_OP_111J22_123_4462_n268), .S(DP_OP_111J22_123_4462_n269) );
CMPR32X2TS U448 ( .A(n552), .B(n1282), .C(n1281), .CO(mult_x_23_n227), .S(
mult_x_23_n228) );
NAND2X1TS U449 ( .A(n773), .B(n772), .Y(n1411) );
NAND2X2TS U450 ( .A(DP_OP_111J22_123_4462_n361), .B(
DP_OP_111J22_123_4462_n365), .Y(n1404) );
CMPR32X2TS U451 ( .A(n1561), .B(n1560), .C(n1559), .CO(
DP_OP_111J22_123_4462_n350), .S(DP_OP_111J22_123_4462_n351) );
CMPR32X2TS U452 ( .A(Op_MY[14]), .B(n588), .C(n1278), .CO(mult_x_23_n208),
.S(mult_x_23_n209) );
CMPR32X2TS U453 ( .A(n1621), .B(n1620), .C(n1619), .CO(n1622), .S(
DP_OP_111J22_123_4462_n332) );
INVX2TS U454 ( .A(n408), .Y(n457) );
NOR2X2TS U455 ( .A(n627), .B(n626), .Y(n1038) );
AOI21X1TS U456 ( .A0(n1270), .A1(n570), .B0(n805), .Y(n1267) );
ADDHXLTS U457 ( .A(n1355), .B(n1354), .CO(mult_x_23_n258), .S(mult_x_23_n259) );
INVX2TS U458 ( .A(n408), .Y(n456) );
ADDHX1TS U459 ( .A(n1626), .B(n1625), .CO(DP_OP_111J22_123_4462_n369), .S(
n775) );
NOR2X1TS U460 ( .A(n2134), .B(n2136), .Y(n2107) );
NOR2X1TS U461 ( .A(n2166), .B(n2168), .Y(n1859) );
XNOR2X1TS U462 ( .A(n1504), .B(n473), .Y(n1598) );
INVX4TS U463 ( .A(n417), .Y(n449) );
NAND2X1TS U464 ( .A(n1923), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]),
.Y(n2084) );
NOR2X1TS U465 ( .A(n2383), .B(FS_Module_state_reg[0]), .Y(n1932) );
NOR2X1TS U466 ( .A(n1856), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2166) );
INVX2TS U467 ( .A(n395), .Y(n512) );
INVX2TS U468 ( .A(n693), .Y(n502) );
AOI21X1TS U469 ( .A0(n895), .A1(n1449), .B0(n1448), .Y(n1454) );
INVX2TS U470 ( .A(n1534), .Y(n542) );
NAND2XLTS U471 ( .A(n1449), .B(n1447), .Y(n692) );
NAND2X4TS U472 ( .A(n1146), .B(n602), .Y(n1148) );
INVX4TS U473 ( .A(n482), .Y(n483) );
NAND2X4TS U474 ( .A(n1074), .B(n511), .Y(n1154) );
INVX4TS U475 ( .A(n1335), .Y(n532) );
AND2X2TS U476 ( .A(n882), .B(n881), .Y(n1611) );
AOI21X1TS U477 ( .A0(n1439), .A1(n765), .B0(n764), .Y(n770) );
NAND2X2TS U478 ( .A(n888), .B(n554), .Y(n897) );
XOR2X1TS U479 ( .A(Op_MY[4]), .B(n450), .Y(n602) );
INVX4TS U480 ( .A(n390), .Y(n485) );
INVX4TS U481 ( .A(n465), .Y(n466) );
INVX4TS U482 ( .A(n465), .Y(n467) );
CLKINVX6TS U483 ( .A(n390), .Y(n484) );
INVX2TS U484 ( .A(n395), .Y(n511) );
INVX4TS U485 ( .A(n477), .Y(n478) );
AOI21X1TS U486 ( .A0(n1725), .A1(n1731), .B0(n1734), .Y(n1730) );
AND2X2TS U487 ( .A(n754), .B(n741), .Y(n1556) );
INVX2TS U488 ( .A(n1614), .Y(n1608) );
CLKINVX6TS U489 ( .A(n410), .Y(n515) );
INVX2TS U490 ( .A(n757), .Y(n477) );
INVX4TS U491 ( .A(n584), .Y(n468) );
AND2X4TS U492 ( .A(n800), .B(n486), .Y(n1335) );
NAND2X1TS U493 ( .A(n1902), .B(n1901), .Y(n1905) );
BUFX3TS U494 ( .A(Op_MY[1]), .Y(n1093) );
INVX2TS U495 ( .A(n1759), .Y(n1755) );
NAND2XLTS U496 ( .A(n704), .B(n703), .Y(n705) );
NAND2X1TS U497 ( .A(n1433), .B(n1432), .Y(n1434) );
INVX2TS U498 ( .A(n421), .Y(n505) );
NAND2X1TS U499 ( .A(Op_MY[15]), .B(Op_MY[3]), .Y(n729) );
NOR2X1TS U500 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n707) );
INVX2TS U501 ( .A(n586), .Y(n435) );
NOR2X1TS U502 ( .A(n1801), .B(n1803), .Y(n1646) );
NOR2X2TS U503 ( .A(n1717), .B(n1719), .Y(n1701) );
NOR2X1TS U504 ( .A(n1656), .B(n1655), .Y(n1774) );
NOR2X2TS U505 ( .A(n1699), .B(n1698), .Y(n1719) );
NOR2X2TS U506 ( .A(n1697), .B(n1696), .Y(n1717) );
ADDFX2TS U507 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]), .B(n1681),
.CI(n1680), .CO(n1688), .S(n1687) );
NOR2X2TS U508 ( .A(Op_MY[15]), .B(Op_MY[3]), .Y(n728) );
INVX4TS U509 ( .A(n412), .Y(n473) );
NAND2X1TS U510 ( .A(n1909), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]),
.Y(n1911) );
CLKINVX3TS U511 ( .A(n477), .Y(n479) );
AO21X2TS U512 ( .A0(n542), .A1(n432), .B0(n465), .Y(n1595) );
NOR2XLTS U513 ( .A(n471), .B(n577), .Y(n1120) );
INVX2TS U514 ( .A(n1556), .Y(n544) );
OAI22X1TS U515 ( .A0(n544), .A1(n1485), .B0(n741), .B1(n758), .Y(n1626) );
ADDHXLTS U516 ( .A(n1358), .B(n1357), .CO(mult_x_23_n235), .S(mult_x_23_n236) );
CLKINVX3TS U517 ( .A(n1427), .Y(n491) );
INVX2TS U518 ( .A(n416), .Y(n481) );
NOR2XLTS U519 ( .A(DP_OP_111J22_123_4462_n727), .B(n569), .Y(n1170) );
INVX2TS U520 ( .A(n502), .Y(n504) );
INVX4TS U521 ( .A(n462), .Y(n463) );
NOR2XLTS U522 ( .A(n1988), .B(n2389), .Y(n1990) );
OAI21X1TS U523 ( .A0(n1246), .A1(n1252), .B0(n1247), .Y(n829) );
NOR2X4TS U524 ( .A(DP_OP_111J22_123_4462_n300), .B(
DP_OP_111J22_123_4462_n309), .Y(n864) );
NOR2X6TS U525 ( .A(n2057), .B(n1928), .Y(n2048) );
CMPR42X1TS U526 ( .A(mult_x_23_n298), .B(mult_x_23_n334), .C(mult_x_23_n206),
.D(mult_x_23_n199), .ICI(mult_x_23_n202), .S(mult_x_23_n196), .ICO(
mult_x_23_n194), .CO(mult_x_23_n195) );
NAND2X1TS U527 ( .A(n1949), .B(n1994), .Y(n1947) );
OR2X1TS U528 ( .A(DP_OP_111J22_123_4462_n366), .B(n777), .Y(n597) );
OR2X1TS U529 ( .A(n823), .B(n822), .Y(n582) );
OAI21XLTS U530 ( .A0(n2258), .A1(n2254), .B0(n2255), .Y(n2246) );
OAI21XLTS U531 ( .A0(n2082), .A1(n2095), .B0(n2096), .Y(n2087) );
OR2X2TS U532 ( .A(DP_OP_111J22_123_4462_n343), .B(DP_OP_111J22_123_4462_n348), .Y(n405) );
BUFX3TS U533 ( .A(n1954), .Y(n527) );
OR2X1TS U534 ( .A(mult_x_55_n176), .B(mult_x_55_n172), .Y(n969) );
OR2X1TS U535 ( .A(mult_x_55_n247), .B(mult_x_55_n253), .Y(n580) );
OR2X1TS U536 ( .A(n909), .B(n908), .Y(n1575) );
CLKINVX3TS U537 ( .A(n392), .Y(n440) );
OAI21XLTS U538 ( .A0(n1255), .A1(n1251), .B0(n1252), .Y(n1250) );
INVX4TS U539 ( .A(n1181), .Y(n1206) );
CLKINVX3TS U540 ( .A(n561), .Y(n554) );
OAI21XLTS U541 ( .A0(n2383), .A1(n2266), .B0(FS_Module_state_reg[3]), .Y(
n1966) );
INVX2TS U542 ( .A(n2375), .Y(n2377) );
AND2X2TS U543 ( .A(n1956), .B(n1957), .Y(n2370) );
NAND2X1TS U544 ( .A(n1981), .B(n1957), .Y(n2368) );
OAI211XLTS U545 ( .A0(n2398), .A1(n2339), .B0(n2128), .C0(n1966), .Y(n379)
);
CLKXOR2X2TS U546 ( .A(n1428), .B(n1426), .Y(n390) );
CLKBUFX2TS U547 ( .A(Op_MX[19]), .Y(n1351) );
INVX2TS U548 ( .A(n419), .Y(n507) );
CLKXOR2X2TS U549 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n416) );
INVX2TS U550 ( .A(Op_MY[11]), .Y(n471) );
CLKXOR2X2TS U551 ( .A(Op_MY[6]), .B(Op_MY[5]), .Y(n395) );
CLKMX2X2TS U552 ( .A(P_Sgf[44]), .B(n1941), .S0(n2088), .Y(n259) );
XOR2X1TS U553 ( .A(n1376), .B(n1375), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
INVX2TS U554 ( .A(n1570), .Y(n901) );
XOR2X1TS U555 ( .A(n994), .B(n993), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N15) );
CLKMX2X2TS U556 ( .A(n1992), .B(Add_result[23]), .S0(n2240), .Y(n283) );
NAND2X1TS U557 ( .A(n563), .B(n919), .Y(n920) );
CLKMX2X2TS U558 ( .A(P_Sgf[19]), .B(n2310), .S0(n2326), .Y(n234) );
CLKMX2X2TS U559 ( .A(P_Sgf[17]), .B(n2277), .S0(n2340), .Y(n232) );
INVX2TS U560 ( .A(n2220), .Y(n2222) );
CLKMX2X2TS U561 ( .A(P_Sgf[16]), .B(n2287), .S0(n2340), .Y(n231) );
OAI21X1TS U562 ( .A0(n1210), .A1(n1216), .B0(n1211), .Y(n836) );
OR2X2TS U563 ( .A(n1589), .B(n1588), .Y(n1591) );
CLKMX2X2TS U564 ( .A(n2045), .B(Add_result[16]), .S0(n2261), .Y(n290) );
AO21X1TS U565 ( .A0(n544), .A1(n519), .B0(n1485), .Y(
DP_OP_111J22_123_4462_n436) );
CLKMX2X2TS U566 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n2338), .Y(n276) );
CLKMX2X2TS U567 ( .A(n2056), .B(Add_result[15]), .S0(n2035), .Y(n291) );
CLKMX2X2TS U568 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n2338), .Y(n277) );
CLKMX2X2TS U569 ( .A(n2070), .B(Add_result[14]), .S0(n2261), .Y(n292) );
OR2X2TS U570 ( .A(n658), .B(n657), .Y(n660) );
AO21X1TS U571 ( .A0(n464), .A1(n504), .B0(n1542), .Y(n1586) );
NAND2BX1TS U572 ( .AN(n1608), .B(n483), .Y(n1549) );
MX2X1TS U573 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n2338),
.Y(n279) );
CLKMX2X2TS U574 ( .A(n2081), .B(Add_result[13]), .S0(n2261), .Y(n293) );
MX2X1TS U575 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n2338),
.Y(n280) );
AO21X1TS U576 ( .A0(Sgf_normalized_result[23]), .A1(n2128), .B0(n1995), .Y(
n307) );
OAI31XLTS U577 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[2]),
.A2(n2385), .B0(n1971), .Y(n377) );
OR2X2TS U578 ( .A(n715), .B(n714), .Y(n571) );
OR2X2TS U579 ( .A(n804), .B(n803), .Y(n570) );
AO21X1TS U580 ( .A0(n541), .A1(n493), .B0(n584), .Y(mult_x_55_n300) );
INVX4TS U581 ( .A(n1983), .Y(n1982) );
INVX2TS U582 ( .A(n1760), .Y(n1762) );
INVX4TS U583 ( .A(n2044), .Y(n2261) );
AOI211X1TS U584 ( .A0(FSM_selector_B[0]), .A1(n1960), .B0(n2044), .C0(n2344),
.Y(n2423) );
INVX4TS U585 ( .A(n690), .Y(n1439) );
AND2X4TS U586 ( .A(n480), .B(n568), .Y(n417) );
INVX2TS U587 ( .A(n1803), .Y(n1805) );
BUFX3TS U588 ( .A(n1146), .Y(n470) );
INVX1TS U589 ( .A(n1953), .Y(n1945) );
INVX4TS U590 ( .A(n416), .Y(n480) );
OR2X2TS U591 ( .A(n1638), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n1641) );
INVX2TS U592 ( .A(n1440), .Y(n1442) );
OAI21X1TS U593 ( .A0(FSM_selector_B[0]), .A1(n1979), .B0(n567), .Y(n1980) );
NAND2BX1TS U594 ( .AN(n1152), .B(n450), .Y(n604) );
NAND2BX1TS U595 ( .AN(n1362), .B(n521), .Y(n1363) );
INVX4TS U596 ( .A(n471), .Y(n472) );
NAND2BX1TS U597 ( .AN(n1152), .B(Op_MY[7]), .Y(n1153) );
CLKMX2X2TS U598 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
CLKMX2X2TS U599 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U600 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
INVX4TS U601 ( .A(n419), .Y(n508) );
CLKMX2X2TS U602 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X2TS U603 ( .A(P_Sgf[47]), .B(n1938), .S0(n2340), .Y(n380) );
NAND2X4TS U604 ( .A(n1935), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]),
.Y(n1937) );
CLKMX2X2TS U605 ( .A(P_Sgf[43]), .B(n2014), .S0(n2088), .Y(n258) );
CLKMX2X2TS U606 ( .A(P_Sgf[42]), .B(n2022), .S0(n2088), .Y(n257) );
CLKMX2X2TS U607 ( .A(P_Sgf[41]), .B(n2030), .S0(n2088), .Y(n256) );
CLKMX2X2TS U608 ( .A(P_Sgf[40]), .B(n2039), .S0(n2088), .Y(n255) );
CLKMX2X2TS U609 ( .A(P_Sgf[39]), .B(n2051), .S0(n2088), .Y(n254) );
CLKMX2X2TS U610 ( .A(P_Sgf[37]), .B(n2076), .S0(n2088), .Y(n252) );
CLKMX2X2TS U611 ( .A(P_Sgf[35]), .B(n2100), .S0(n2225), .Y(n250) );
XOR2X1TS U612 ( .A(n1392), .B(n1391), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
XOR2X1TS U613 ( .A(n1540), .B(n1539), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
CLKMX2X2TS U614 ( .A(P_Sgf[33]), .B(n2127), .S0(n2225), .Y(n248) );
CLKMX2X2TS U615 ( .A(P_Sgf[32]), .B(n2141), .S0(n2225), .Y(n247) );
CLKMX2X2TS U616 ( .A(P_Sgf[31]), .B(n2151), .S0(n2225), .Y(n246) );
INVX3TS U617 ( .A(n2082), .Y(n2099) );
XOR2X2TS U618 ( .A(n662), .B(n661), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N23) );
XOR2X2TS U619 ( .A(n851), .B(n850), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N23) );
CLKMX2X2TS U620 ( .A(P_Sgf[29]), .B(n2183), .S0(n2225), .Y(n244) );
INVX6TS U621 ( .A(n2046), .Y(n2150) );
CLKMX2X2TS U622 ( .A(n2262), .B(FSM_add_overflow_flag), .S0(n2261), .Y(n282)
);
XOR2X1TS U623 ( .A(n955), .B(n954), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N21) );
CLKMX2X2TS U624 ( .A(P_Sgf[28]), .B(n2197), .S0(n2225), .Y(n243) );
XOR2X1TS U625 ( .A(n1219), .B(n1218), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N15) );
CLKMX2X2TS U626 ( .A(P_Sgf[27]), .B(n2207), .S0(n2225), .Y(n242) );
XOR2X1TS U627 ( .A(n1226), .B(n1225), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N14) );
OAI21X1TS U628 ( .A0(n994), .A1(n990), .B0(n991), .Y(n989) );
CLKMX2X2TS U629 ( .A(P_Sgf[26]), .B(n2226), .S0(n2225), .Y(n241) );
XOR2X1TS U630 ( .A(n1403), .B(n1402), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
XOR2X1TS U631 ( .A(n1001), .B(n1000), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N14) );
XOR2X1TS U632 ( .A(n1180), .B(n1179), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N21) );
CLKMX2X2TS U633 ( .A(P_Sgf[22]), .B(n2325), .S0(n2326), .Y(n237) );
CLKMX2X2TS U634 ( .A(P_Sgf[24]), .B(n2247), .S0(n2340), .Y(n239) );
CLKMX2X2TS U635 ( .A(n1997), .B(Add_result[22]), .S0(n2035), .Y(n284) );
CLKMX2X2TS U636 ( .A(P_Sgf[25]), .B(n2236), .S0(n2340), .Y(n240) );
INVX6TS U637 ( .A(n956), .Y(n981) );
NOR2X2TS U638 ( .A(n1382), .B(n1536), .Y(n788) );
CLKMX2X2TS U639 ( .A(P_Sgf[20]), .B(n2296), .S0(n2340), .Y(n235) );
OAI21X2TS U640 ( .A0(n1382), .A1(n1537), .B0(n1383), .Y(n787) );
NOR2X4TS U641 ( .A(n883), .B(n925), .Y(n1571) );
XOR2X1TS U642 ( .A(n1110), .B(n1109), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N11) );
CLKMX2X2TS U643 ( .A(n2005), .B(Add_result[21]), .S0(n2261), .Y(n285) );
CLKMX2X2TS U644 ( .A(P_Sgf[23]), .B(n2259), .S0(n2340), .Y(n238) );
XOR2X1TS U645 ( .A(n1241), .B(n1240), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N10) );
OAI21X1TS U646 ( .A0(n1110), .A1(n1106), .B0(n1107), .Y(n1011) );
CLKMX2X2TS U647 ( .A(P_Sgf[21]), .B(n2316), .S0(n2326), .Y(n236) );
OAI21X2TS U648 ( .A0(n857), .A1(n1373), .B0(n858), .Y(n694) );
NAND2X1TS U649 ( .A(n944), .B(n943), .Y(n945) );
XOR2X1TS U650 ( .A(n1329), .B(n1328), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N11) );
CLKMX2X2TS U651 ( .A(P_Sgf[18]), .B(n2306), .S0(n2326), .Y(n233) );
XOR2X1TS U652 ( .A(n1017), .B(n1016), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N10) );
OAI21X1TS U653 ( .A0(n2319), .A1(n2318), .B0(n2317), .Y(n2324) );
NOR2X4TS U654 ( .A(DP_OP_111J22_123_4462_n285), .B(
DP_OP_111J22_123_4462_n292), .Y(n857) );
CLKMX2X2TS U655 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n2338), .Y(n281) );
CLKMX2X2TS U656 ( .A(n2011), .B(Add_result[20]), .S0(n2035), .Y(n286) );
NOR2X4TS U657 ( .A(DP_OP_111J22_123_4462_n278), .B(
DP_OP_111J22_123_4462_n272), .Y(n925) );
CLKMX2X2TS U658 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n2338), .Y(n273) );
CLKMX2X2TS U659 ( .A(n2019), .B(Add_result[19]), .S0(n2261), .Y(n287) );
XOR2X1TS U660 ( .A(n1255), .B(n1254), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N7) );
NAND3BX1TS U661 ( .AN(Exp_module_Data_S[7]), .B(n2344), .C(n2343), .Y(n2345)
);
OR2X2TS U662 ( .A(DP_OP_111J22_123_4462_n349), .B(DP_OP_111J22_123_4462_n355), .Y(n782) );
INVX2TS U663 ( .A(n1190), .Y(n1191) );
CLKMX2X2TS U664 ( .A(n2027), .B(Add_result[18]), .S0(n2035), .Y(n288) );
OAI21X1TS U665 ( .A0(n2299), .A1(n2298), .B0(n2297), .Y(n2304) );
XOR2X1TS U666 ( .A(n1031), .B(n1030), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N7) );
NAND4BX1TS U667 ( .AN(n2342), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n2343) );
CLKMX2X2TS U668 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n2338), .Y(n274) );
CLKMX2X2TS U669 ( .A(n2036), .B(Add_result[17]), .S0(n2261), .Y(n289) );
XOR2X1TS U670 ( .A(n1260), .B(n1259), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N6) );
CLKMX2X2TS U671 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n2338), .Y(n275) );
NAND2X2TS U672 ( .A(mult_x_23_n196), .B(mult_x_23_n203), .Y(n1216) );
OR2X2TS U673 ( .A(n749), .B(n748), .Y(n598) );
OAI21X1TS U674 ( .A0(n1047), .A1(n1043), .B0(n1044), .Y(n1042) );
XOR2X1TS U675 ( .A(n1047), .B(n1046), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N4) );
XOR2X2TS U676 ( .A(n1730), .B(n1729), .Y(n1856) );
OR2X2TS U677 ( .A(mult_x_23_n174), .B(mult_x_23_n170), .Y(n1194) );
XOR2X1TS U678 ( .A(n1052), .B(n1051), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N3) );
OR2X2TS U679 ( .A(mult_x_23_n245), .B(mult_x_23_n251), .Y(n594) );
OR2X2TS U680 ( .A(mult_x_23_n161), .B(n843), .Y(n1173) );
OR2X1TS U681 ( .A(n847), .B(n846), .Y(n849) );
OR2X2TS U682 ( .A(mult_x_23_n239), .B(mult_x_23_n244), .Y(n595) );
OR2X2TS U683 ( .A(mult_x_55_n163), .B(n650), .Y(n948) );
NAND2BX1TS U684 ( .AN(n1608), .B(n479), .Y(n758) );
AO21X1TS U685 ( .A0(n549), .A1(n425), .B0(n1550), .Y(
DP_OP_111J22_123_4462_n407) );
OAI21X1TS U686 ( .A0(FS_Module_state_reg[1]), .A1(n2263), .B0(n1964), .Y(
n376) );
NAND2BX1TS U687 ( .AN(n1608), .B(n467), .Y(n723) );
OR2X2TS U688 ( .A(n1809), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(
n1808) );
XOR2X1TS U689 ( .A(n1275), .B(n1323), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N2) );
NAND2BX1TS U690 ( .AN(n1608), .B(n485), .Y(n1530) );
AO22X1TS U691 ( .A0(Sgf_normalized_result[8]), .A1(n2374), .B0(
final_result_ieee[8]), .B1(n2373), .Y(n182) );
NOR2X4TS U692 ( .A(n2337), .B(n2344), .Y(n2338) );
AO21X1TS U693 ( .A0(n539), .A1(n512), .B0(n413), .Y(mult_x_55_n314) );
AO22X1TS U694 ( .A0(Sgf_normalized_result[4]), .A1(n2374), .B0(
final_result_ieee[4]), .B1(n2373), .Y(n186) );
AO22X1TS U695 ( .A0(Sgf_normalized_result[5]), .A1(n2374), .B0(
final_result_ieee[5]), .B1(n2373), .Y(n185) );
AO22X1TS U696 ( .A0(Sgf_normalized_result[6]), .A1(n2374), .B0(
final_result_ieee[6]), .B1(n2373), .Y(n184) );
AO22X1TS U697 ( .A0(Sgf_normalized_result[7]), .A1(n2374), .B0(
final_result_ieee[7]), .B1(n2373), .Y(n183) );
OAI22X2TS U698 ( .A0(n449), .A1(n440), .B0(n481), .B1(n398), .Y(n1278) );
AO22X1TS U699 ( .A0(n1983), .A1(Data_MX[31]), .B0(n2369), .B1(Op_MX[31]),
.Y(n343) );
OAI21X1TS U700 ( .A0(Sgf_normalized_result[0]), .A1(n2240), .B0(n1959), .Y(
n306) );
OAI21X2TS U701 ( .A0(n1711), .A1(n1703), .B0(n1702), .Y(n1704) );
AO22X1TS U702 ( .A0(n1983), .A1(Data_MY[31]), .B0(n2369), .B1(Op_MY[31]),
.Y(n310) );
OR2X2TS U703 ( .A(FSM_selector_C), .B(n1947), .Y(n422) );
AO21X1TS U704 ( .A0(n534), .A1(n492), .B0(n420), .Y(mult_x_23_n306) );
AO21X1TS U705 ( .A0(n532), .A1(n487), .B0(n421), .Y(mult_x_23_n334) );
NOR2X4TS U706 ( .A(n1994), .B(n2391), .Y(n2006) );
INVX2TS U707 ( .A(n1983), .Y(n2369) );
OR2X2TS U708 ( .A(n1994), .B(FSM_selector_C), .Y(n2250) );
NAND2X2TS U709 ( .A(n1713), .B(n1701), .Y(n1703) );
AO21X1TS U710 ( .A0(n536), .A1(n496), .B0(n1364), .Y(mult_x_23_n292) );
AO21X1TS U711 ( .A0(n1345), .A1(n489), .B0(n419), .Y(mult_x_23_n320) );
INVX2TS U712 ( .A(n1776), .Y(n1778) );
OAI21X2TS U713 ( .A0(n1760), .A1(n1756), .B0(n1761), .Y(n1714) );
INVX2TS U714 ( .A(n1823), .Y(n1825) );
INVX2TS U715 ( .A(n1821), .Y(n1772) );
INVX2TS U716 ( .A(n1748), .Y(n1750) );
INVX2TS U717 ( .A(n1831), .Y(n1833) );
NAND2BX1TS U718 ( .AN(n1362), .B(n514), .Y(n1352) );
NAND3X1TS U719 ( .A(n1632), .B(n1631), .C(n1630), .Y(n1634) );
AND2X2TS U720 ( .A(n1944), .B(FS_Module_state_reg[1]), .Y(n1949) );
OR2X2TS U721 ( .A(n1878), .B(n1877), .Y(n1882) );
INVX1TS U722 ( .A(n1967), .Y(n1970) );
NAND2BX1TS U723 ( .AN(n1152), .B(n472), .Y(n1057) );
NOR2X1TS U724 ( .A(n2211), .B(Sgf_normalized_result[2]), .Y(n2212) );
OR2X2TS U725 ( .A(n1894), .B(n1893), .Y(n1898) );
NOR2X2TS U726 ( .A(n1687), .B(n1686), .Y(n1746) );
OR2X2TS U727 ( .A(n1909), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]),
.Y(n1913) );
AND2X4TS U728 ( .A(n2265), .B(n1981), .Y(n1983) );
AND2X4TS U729 ( .A(n1284), .B(n495), .Y(n1365) );
OR2X2TS U730 ( .A(n1728), .B(n1727), .Y(n583) );
NAND2X2TS U731 ( .A(n1981), .B(n1942), .Y(n1955) );
NAND3X1TS U732 ( .A(n2265), .B(P_Sgf[47]), .C(n1958), .Y(n1960) );
OR2X2TS U733 ( .A(n1740), .B(n1739), .Y(n1866) );
AND2X2TS U734 ( .A(n2265), .B(n1956), .Y(n2044) );
INVX4TS U735 ( .A(n411), .Y(n493) );
NAND2BX1TS U736 ( .AN(n1152), .B(n469), .Y(n614) );
NAND2X2TS U737 ( .A(n681), .B(n680), .Y(n871) );
OR2X2TS U738 ( .A(n1708), .B(n1707), .Y(n1731) );
NOR2X4TS U739 ( .A(n1953), .B(FS_Module_state_reg[1]), .Y(n1954) );
NAND2BX1TS U740 ( .AN(n1362), .B(n452), .Y(n796) );
NOR2X1TS U741 ( .A(n1988), .B(n2156), .Y(n1989) );
OAI21X2TS U742 ( .A0(n702), .A1(n706), .B0(n703), .Y(n695) );
INVX1TS U743 ( .A(n2263), .Y(n1958) );
NAND2BX1TS U744 ( .AN(n552), .B(n506), .Y(n802) );
NAND2BX1TS U745 ( .AN(n1362), .B(n508), .Y(n818) );
XOR2X2TS U746 ( .A(Op_MY[8]), .B(n509), .Y(n411) );
OR2X2TS U747 ( .A(Op_MY[12]), .B(Op_MY[0]), .Y(n587) );
AND2X2TS U748 ( .A(Op_MX[0]), .B(Op_MX[12]), .Y(n698) );
OR2X2TS U749 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
XOR2X1TS U750 ( .A(n929), .B(n928), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
AOI21X4TS U751 ( .A0(n1583), .A1(n924), .B0(n923), .Y(n929) );
XNOR2X2TS U752 ( .A(n1883), .B(n1879), .Y(n1917) );
XOR2X4TS U753 ( .A(n911), .B(n910), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
CMPR42X2TS U754 ( .A(DP_OP_111J22_123_4462_n297), .B(
DP_OP_111J22_123_4462_n412), .C(DP_OP_111J22_123_4462_n400), .D(
DP_OP_111J22_123_4462_n304), .ICI(DP_OP_111J22_123_4462_n301), .S(
DP_OP_111J22_123_4462_n296), .ICO(DP_OP_111J22_123_4462_n294), .CO(
DP_OP_111J22_123_4462_n295) );
NOR2X4TS U755 ( .A(DP_OP_111J22_123_4462_n293), .B(
DP_OP_111J22_123_4462_n299), .Y(n1372) );
AOI21X2TS U756 ( .A0(n635), .A1(n1021), .B0(n634), .Y(n1012) );
XOR2X4TS U757 ( .A(n918), .B(n917), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
AOI21X4TS U758 ( .A0(n1390), .A1(n1388), .B0(n784), .Y(n785) );
CMPR42X2TS U759 ( .A(DP_OP_111J22_123_4462_n336), .B(
DP_OP_111J22_123_4462_n468), .C(DP_OP_111J22_123_4462_n337), .D(
DP_OP_111J22_123_4462_n333), .ICI(DP_OP_111J22_123_4462_n330), .S(
DP_OP_111J22_123_4462_n327), .ICO(DP_OP_111J22_123_4462_n325), .CO(
DP_OP_111J22_123_4462_n326) );
NAND2X6TS U760 ( .A(n1294), .B(n491), .Y(n1353) );
OAI21X1TS U761 ( .A0(n1219), .A1(n1215), .B0(n1216), .Y(n1214) );
NAND2X6TS U762 ( .A(n2062), .B(n1926), .Y(n1928) );
NOR2X6TS U763 ( .A(n2071), .B(n2063), .Y(n1926) );
ADDFX2TS U764 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .B(n1675),
.CI(n1674), .CO(n1684), .S(n1683) );
OR2X2TS U765 ( .A(n1810), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(
n560) );
CMPR42X2TS U766 ( .A(DP_OP_111J22_123_4462_n315), .B(
DP_OP_111J22_123_4462_n427), .C(DP_OP_111J22_123_4462_n414), .D(
DP_OP_111J22_123_4462_n323), .ICI(DP_OP_111J22_123_4462_n320), .S(
DP_OP_111J22_123_4462_n313), .ICO(DP_OP_111J22_123_4462_n311), .CO(
DP_OP_111J22_123_4462_n312) );
NAND2X2TS U767 ( .A(n1916), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2147) );
OAI21X2TS U768 ( .A0(n2291), .A1(n2307), .B0(n2292), .Y(n2311) );
NOR2X2TS U769 ( .A(n977), .B(n972), .Y(n964) );
AOI21X2TS U770 ( .A0(n1377), .A1(n856), .B0(n855), .Y(n861) );
CMPR42X2TS U771 ( .A(DP_OP_111J22_123_4462_n445), .B(
DP_OP_111J22_123_4462_n458), .C(DP_OP_111J22_123_4462_n351), .D(
DP_OP_111J22_123_4462_n471), .ICI(DP_OP_111J22_123_4462_n354), .S(
DP_OP_111J22_123_4462_n349), .ICO(DP_OP_111J22_123_4462_n347), .CO(
DP_OP_111J22_123_4462_n348) );
OAI21X4TS U772 ( .A0(n922), .A1(n925), .B0(n926), .Y(n1582) );
OAI21X2TS U773 ( .A0(n1579), .A1(n1578), .B0(n1577), .Y(n1580) );
NOR2X4TS U774 ( .A(n938), .B(n942), .Y(n899) );
AOI21X2TS U775 ( .A0(n983), .A1(n642), .B0(n641), .Y(n643) );
OAI21X2TS U776 ( .A0(n997), .A1(n1002), .B0(n998), .Y(n983) );
XNOR2X4TS U777 ( .A(n1914), .B(n1910), .Y(n1923) );
CMPR42X2TS U778 ( .A(mult_x_55_n337), .B(mult_x_55_n361), .C(mult_x_55_n260),
.D(mult_x_55_n257), .ICI(mult_x_55_n256), .S(mult_x_55_n254), .ICO(
mult_x_55_n252), .CO(mult_x_55_n253) );
OAI21X2TS U779 ( .A0(n2075), .A1(n2071), .B0(n2072), .Y(n2064) );
OAI21X2TS U780 ( .A0(n1022), .A1(n1028), .B0(n1023), .Y(n634) );
OAI21X4TS U781 ( .A0(n1207), .A1(n839), .B0(n838), .Y(n1181) );
OAI21X2TS U782 ( .A0(n1272), .A1(n1323), .B0(n1273), .Y(n1270) );
AND2X4TS U783 ( .A(n1070), .B(n493), .Y(n1168) );
XOR2X2TS U784 ( .A(n868), .B(n867), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
NAND2X2TS U785 ( .A(DP_OP_111J22_123_4462_n349), .B(
DP_OP_111J22_123_4462_n355), .Y(n1396) );
XNOR2X2TS U786 ( .A(n752), .B(n736), .Y(n740) );
NOR2X8TS U787 ( .A(n2029), .B(n2028), .Y(n2021) );
NAND2X6TS U788 ( .A(n2038), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]),
.Y(n2029) );
NAND2X4TS U789 ( .A(n2048), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.Y(n1930) );
NAND2X4TS U790 ( .A(n2047), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.Y(n1929) );
XNOR2X2TS U791 ( .A(n1899), .B(n1895), .Y(n1919) );
NAND2X2TS U792 ( .A(n873), .B(n871), .Y(n682) );
XNOR2X4TS U793 ( .A(n873), .B(n871), .Y(n872) );
NOR2X2TS U794 ( .A(n936), .B(n938), .Y(n941) );
OAI21X1TS U795 ( .A0(n1540), .A1(n1536), .B0(n1537), .Y(n1386) );
AOI21X2TS U796 ( .A0(n1582), .A1(n563), .B0(n930), .Y(n939) );
OAI21X4TS U797 ( .A0(n781), .A1(n1399), .B0(n780), .Y(n1398) );
MX2X1TS U798 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U799 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
XOR2X1TS U800 ( .A(Op_MY[8]), .B(n468), .Y(n1070) );
NOR2X1TS U801 ( .A(n471), .B(n394), .Y(mult_x_55_n194) );
NOR2X1TS U802 ( .A(n1840), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.Y(n2289) );
OAI21X1TS U803 ( .A0(n2230), .A1(n2387), .B0(n1987), .Y(n2155) );
BUFX3TS U804 ( .A(n1095), .Y(n1163) );
AOI21X2TS U805 ( .A0(n830), .A1(n1245), .B0(n829), .Y(n1237) );
MX2X1TS U806 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
NOR2X1TS U807 ( .A(DP_OP_111J22_123_4462_n727), .B(n393), .Y(n1171) );
OAI22X1TS U808 ( .A0(n1464), .A1(n463), .B0(n1462), .B1(n503), .Y(
DP_OP_111J22_123_4462_n398) );
AND2X2TS U809 ( .A(n719), .B(n402), .Y(n1534) );
AO21XLTS U810 ( .A0(n1140), .A1(n429), .B0(n415), .Y(mult_x_55_n342) );
NOR2X2TS U811 ( .A(n1440), .B(n686), .Y(n688) );
AO21X1TS U812 ( .A0(n546), .A1(n516), .B0(n1562), .Y(n1568) );
NOR2X1TS U813 ( .A(n1850), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2218) );
NOR2X1TS U814 ( .A(n1916), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2134) );
AOI21X1TS U815 ( .A0(n1990), .A1(n2155), .B0(n1989), .Y(n2118) );
INVX2TS U816 ( .A(n1781), .Y(n1783) );
NAND2X1TS U817 ( .A(n2312), .B(n1845), .Y(n1847) );
NOR2X1TS U818 ( .A(n2318), .B(n2320), .Y(n1845) );
CMPR42X1TS U819 ( .A(mult_x_55_n291), .B(mult_x_55_n185), .C(mult_x_55_n179),
.D(mult_x_55_n186), .ICI(mult_x_55_n182), .S(mult_x_55_n177), .ICO(
mult_x_55_n175), .CO(mult_x_55_n176) );
NOR2X1TS U820 ( .A(mult_x_55_n216), .B(mult_x_55_n224), .Y(n995) );
CMPR42X1TS U821 ( .A(mult_x_23_n319), .B(mult_x_23_n355), .C(mult_x_23_n343),
.D(mult_x_23_n331), .ICI(mult_x_23_n265), .S(mult_x_23_n262), .ICO(
mult_x_23_n260), .CO(mult_x_23_n261) );
INVX2TS U822 ( .A(n2155), .Y(n2201) );
INVX2TS U823 ( .A(n2118), .Y(n2145) );
INVX2TS U824 ( .A(n2320), .Y(n2322) );
NAND4XLTS U825 ( .A(n2349), .B(n2348), .C(n2347), .D(n2346), .Y(n2366) );
NAND4XLTS U826 ( .A(n2362), .B(n2361), .C(n2360), .D(n2359), .Y(n2363) );
NOR2X1TS U827 ( .A(n958), .B(n959), .Y(n647) );
NAND2X1TS U828 ( .A(n964), .B(n969), .Y(n958) );
OAI21X2TS U829 ( .A0(n978), .A1(n972), .B0(n973), .Y(n965) );
OR2X1TS U830 ( .A(n616), .B(n615), .Y(n1054) );
NOR2X2TS U831 ( .A(DP_OP_111J22_123_4462_n258), .B(n902), .Y(n916) );
NAND2X1TS U832 ( .A(DP_OP_111J22_123_4462_n258), .B(n902), .Y(n1572) );
AOI21X2TS U833 ( .A0(n1416), .A1(n598), .B0(n750), .Y(n1413) );
NAND4XLTS U834 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n2342) );
INVX2TS U835 ( .A(n413), .Y(n509) );
XOR2X1TS U836 ( .A(Op_MX[10]), .B(Op_MX[22]), .Y(n679) );
INVX2TS U837 ( .A(n569), .Y(n436) );
XOR2X1TS U838 ( .A(n525), .B(Op_MX[20]), .Y(n876) );
INVX2TS U839 ( .A(n575), .Y(n525) );
INVX2TS U840 ( .A(n897), .Y(n453) );
XOR2X1TS U841 ( .A(Op_MX[6]), .B(Op_MX[18]), .Y(n1431) );
NOR2X2TS U842 ( .A(Op_MY[17]), .B(Op_MY[5]), .Y(n766) );
XOR2X1TS U843 ( .A(Op_MX[4]), .B(Op_MX[16]), .Y(n752) );
XOR2X1TS U844 ( .A(Op_MX[2]), .B(Op_MX[14]), .Y(n717) );
AOI21X2TS U845 ( .A0(n1770), .A1(n1664), .B0(n1663), .Y(n1665) );
NOR2X1TS U846 ( .A(n1829), .B(n1831), .Y(n1742) );
NOR2X1TS U847 ( .A(n471), .B(n576), .Y(n1121) );
NAND2BXLTS U848 ( .AN(n1152), .B(Op_MY[9]), .Y(n1112) );
NOR2X1TS U849 ( .A(n869), .B(n1450), .Y(n884) );
NOR2X2TS U850 ( .A(n439), .B(Op_MY[7]), .Y(n686) );
NOR2X2TS U851 ( .A(Op_MY[18]), .B(Op_MY[6]), .Y(n1440) );
OAI21X1TS U852 ( .A0(n686), .A1(n1441), .B0(n685), .Y(n687) );
NAND2X1TS U853 ( .A(n730), .B(n729), .Y(n731) );
NAND2X1TS U854 ( .A(n721), .B(n720), .Y(n737) );
INVX2TS U855 ( .A(n1283), .Y(n495) );
NAND2X1TS U856 ( .A(n1656), .B(n1655), .Y(n1796) );
INVX2TS U857 ( .A(n1769), .Y(n1799) );
NAND2X1TS U858 ( .A(n1660), .B(n1659), .Y(n1820) );
INVX2TS U859 ( .A(n1717), .Y(n1766) );
INVX2TS U860 ( .A(n1714), .Y(n1715) );
AOI21X1TS U861 ( .A0(n2163), .A1(n1859), .B0(n1858), .Y(n1860) );
NAND2X1TS U862 ( .A(n1642), .B(n1641), .Y(n1800) );
NAND2X1TS U863 ( .A(n1683), .B(n1682), .Y(n1828) );
AO21XLTS U864 ( .A0(n1148), .A1(n470), .B0(n418), .Y(mult_x_55_n328) );
INVX2TS U865 ( .A(n395), .Y(n513) );
BUFX3TS U866 ( .A(n601), .Y(n1146) );
NAND2BXLTS U867 ( .AN(n550), .B(Op_MY[3]), .Y(n610) );
NAND2X4TS U868 ( .A(n600), .B(n599), .Y(n1140) );
NAND2X1TS U869 ( .A(Op_MY[22]), .B(Op_MY[10]), .Y(n890) );
INVX2TS U870 ( .A(n919), .Y(n930) );
CMPR42X1TS U871 ( .A(DP_OP_111J22_123_4462_n467), .B(
DP_OP_111J22_123_4462_n415), .C(DP_OP_111J22_123_4462_n428), .D(
DP_OP_111J22_123_4462_n324), .ICI(DP_OP_111J22_123_4462_n328), .S(
DP_OP_111J22_123_4462_n322), .ICO(DP_OP_111J22_123_4462_n320), .CO(
DP_OP_111J22_123_4462_n321) );
CMPR42X1TS U872 ( .A(DP_OP_111J22_123_4462_n406), .B(
DP_OP_111J22_123_4462_n418), .C(DP_OP_111J22_123_4462_n431), .D(
DP_OP_111J22_123_4462_n352), .ICI(DP_OP_111J22_123_4462_n457), .S(
DP_OP_111J22_123_4462_n346), .ICO(DP_OP_111J22_123_4462_n344), .CO(
DP_OP_111J22_123_4462_n345) );
XNOR2X1TS U873 ( .A(n1502), .B(n467), .Y(n1505) );
OAI22X1TS U874 ( .A0(n546), .A1(n1562), .B0(n515), .B1(n1530), .Y(n1533) );
CMPR42X1TS U875 ( .A(mult_x_23_n310), .B(mult_x_23_n322), .C(mult_x_23_n208),
.D(mult_x_23_n201), .ICI(mult_x_23_n205), .S(mult_x_23_n199), .ICO(
mult_x_23_n197), .CO(mult_x_23_n198) );
CMPR42X1TS U876 ( .A(mult_x_23_n313), .B(mult_x_23_n337), .C(mult_x_23_n301),
.D(mult_x_23_n235), .ICI(mult_x_23_n232), .S(mult_x_23_n226), .ICO(
mult_x_23_n224), .CO(mult_x_23_n225) );
INVX2TS U877 ( .A(n1335), .Y(n531) );
NAND2X1TS U878 ( .A(n451), .B(n589), .Y(n1320) );
NOR2X1TS U879 ( .A(n2254), .B(n2242), .Y(n2214) );
NOR2X1TS U880 ( .A(n2192), .B(n2189), .Y(n2162) );
NAND2X1TS U881 ( .A(n1569), .B(n1575), .Y(n1578) );
NAND2X1TS U882 ( .A(n1571), .B(n563), .Y(n936) );
NOR2X2TS U883 ( .A(n1372), .B(n857), .Y(n789) );
CMPR42X1TS U884 ( .A(DP_OP_111J22_123_4462_n435), .B(
DP_OP_111J22_123_4462_n448), .C(DP_OP_111J22_123_4462_n461), .D(
DP_OP_111J22_123_4462_n369), .ICI(DP_OP_111J22_123_4462_n474), .S(
DP_OP_111J22_123_4462_n366), .ICO(DP_OP_111J22_123_4462_n364), .CO(
DP_OP_111J22_123_4462_n365) );
BUFX3TS U885 ( .A(n1320), .Y(n1361) );
INVX2TS U886 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .Y(n2063) );
NOR2X1TS U887 ( .A(n2118), .B(n1991), .Y(n2104) );
CLKAND2X2TS U888 ( .A(n449), .B(n481), .Y(n845) );
MX2X1TS U889 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
INVX2TS U890 ( .A(n1983), .Y(n2336) );
XOR3X1TS U891 ( .A(n656), .B(n655), .C(n654), .Y(n657) );
AO21XLTS U892 ( .A0(n457), .A1(n500), .B0(DP_OP_111J22_123_4462_n727), .Y(
n654) );
OAI21X2TS U893 ( .A0(n955), .A1(n951), .B0(n952), .Y(n950) );
CLKAND2X2TS U894 ( .A(n1571), .B(n1581), .Y(n565) );
NOR2X2TS U895 ( .A(DP_OP_111J22_123_4462_n259), .B(
DP_OP_111J22_123_4462_n261), .Y(n942) );
NAND2BXLTS U896 ( .AN(n1608), .B(n460), .Y(n713) );
OAI22X1TS U897 ( .A0(n1523), .A1(n553), .B0(n712), .B1(n476), .Y(n1527) );
MX2X1TS U898 ( .A(Data_MY[17]), .B(n442), .S0(n2369), .Y(n329) );
MX2X1TS U899 ( .A(Data_MX[9]), .B(n397), .S0(n1982), .Y(n353) );
MX2X1TS U900 ( .A(Data_MY[21]), .B(n438), .S0(n459), .Y(n333) );
MX2X1TS U901 ( .A(Data_MY[16]), .B(n441), .S0(n2336), .Y(n328) );
MX2X1TS U902 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n1985), .Y(n357) );
MX2X1TS U903 ( .A(Data_MY[15]), .B(n440), .S0(n2336), .Y(n327) );
MX2X1TS U904 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n1984), .Y(n361) );
MX2X1TS U905 ( .A(Data_MX[3]), .B(n434), .S0(n1982), .Y(n347) );
MX2X1TS U906 ( .A(Data_MX[10]), .B(n444), .S0(n1982), .Y(n354) );
MX2X1TS U907 ( .A(Data_MX[2]), .B(n433), .S0(n1982), .Y(n346) );
MX2X1TS U908 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n1984), .Y(n359) );
MX2X1TS U909 ( .A(P_Sgf[11]), .B(Sgf_operation_Result[11]), .S0(n2337), .Y(
n226) );
MX2X1TS U910 ( .A(P_Sgf[6]), .B(Sgf_operation_Result[6]), .S0(n2337), .Y(
n221) );
MX2X1TS U911 ( .A(P_Sgf[7]), .B(Sgf_operation_Result[7]), .S0(n2337), .Y(
n222) );
MX2X1TS U912 ( .A(P_Sgf[8]), .B(Sgf_operation_Result[8]), .S0(n2337), .Y(
n223) );
MX2X1TS U913 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n2326), .Y(
n219) );
MX2X1TS U914 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n2326), .Y(
n220) );
MX2X1TS U915 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n2326), .Y(
n218) );
MX2X1TS U916 ( .A(P_Sgf[15]), .B(n2281), .S0(n2340), .Y(n230) );
MX2X1TS U917 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n459), .Y(n316) );
MX2X1TS U918 ( .A(P_Sgf[30]), .B(n2173), .S0(n2225), .Y(n245) );
MX2X1TS U919 ( .A(P_Sgf[45]), .B(n2000), .S0(n2088), .Y(n260) );
MX2X1TS U920 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n2336), .Y(n336) );
MX2X1TS U921 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n2336), .Y(n340) );
MX2X1TS U922 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n1985), .Y(n338) );
MX2X1TS U923 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n2369), .Y(n337) );
MX2X1TS U924 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n2369), .Y(n341) );
MX2X1TS U925 ( .A(n2241), .B(Add_result[1]), .S0(n2035), .Y(n305) );
MX2X1TS U926 ( .A(n2231), .B(Add_result[2]), .S0(n2035), .Y(n304) );
MX2X1TS U927 ( .A(n2213), .B(Add_result[3]), .S0(n2240), .Y(n303) );
INVX2TS U928 ( .A(n2230), .Y(n2211) );
MX2X1TS U929 ( .A(n2202), .B(Add_result[4]), .S0(n2240), .Y(n302) );
MX2X1TS U930 ( .A(n2188), .B(Add_result[5]), .S0(n2240), .Y(n301) );
MX2X1TS U931 ( .A(n2178), .B(Add_result[6]), .S0(n2240), .Y(n300) );
MX2X1TS U932 ( .A(n2158), .B(Add_result[7]), .S0(n2240), .Y(n299) );
MX2X1TS U933 ( .A(n2146), .B(Add_result[8]), .S0(n2261), .Y(n298) );
MX2X1TS U934 ( .A(n2133), .B(Add_result[9]), .S0(n2035), .Y(n297) );
MX2X1TS U935 ( .A(n2121), .B(Add_result[10]), .S0(n2261), .Y(n296) );
MX2X1TS U936 ( .A(n2105), .B(Add_result[11]), .S0(n2261), .Y(n295) );
MX2X1TS U937 ( .A(n2094), .B(Add_result[12]), .S0(n2035), .Y(n294) );
MX2X1TS U938 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n458), .Y(n367) );
MX2X1TS U939 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n2369), .Y(n372) );
MX2X1TS U940 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n2336), .Y(n370) );
MX2X1TS U941 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n459), .Y(n374) );
MX2X1TS U942 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n1985), .Y(n369) );
MX2X1TS U943 ( .A(P_Sgf[13]), .B(n2273), .S0(n2340), .Y(n228) );
MX2X1TS U944 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n2326), .Y(
n216) );
MX2X1TS U945 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n2369), .Y(n335) );
MX2X1TS U946 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n2338),
.Y(n278) );
MX2X1TS U947 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n458), .Y(n339) );
MX2X1TS U948 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n2336), .Y(n368) );
MX2X1TS U949 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n2336), .Y(n342) );
MX2X1TS U950 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n2336), .Y(n373) );
MX2X1TS U951 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n459), .Y(n371) );
MX2X1TS U952 ( .A(Data_MX[11]), .B(n554), .S0(n2369), .Y(n355) );
MX2X1TS U953 ( .A(Data_MY[20]), .B(n555), .S0(n1985), .Y(n332) );
MX2X1TS U954 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n1985), .Y(n366) );
MX2X1TS U955 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n1982), .Y(n344) );
CLKAND2X2TS U956 ( .A(n1099), .B(n1098), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N1) );
MX2X1TS U957 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n458), .Y(n320) );
MX2X1TS U958 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n458), .Y(n321) );
MX2X1TS U959 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n458), .Y(n323) );
MX2X1TS U960 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n458), .Y(n330) );
MX2X1TS U961 ( .A(Data_MY[22]), .B(n1986), .S0(n458), .Y(n334) );
MX2X1TS U962 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n459), .Y(n331) );
MX2X1TS U963 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n1985), .Y(n322) );
OAI21XLTS U964 ( .A0(n1206), .A1(n1192), .B0(n1191), .Y(n1196) );
NOR2XLTS U965 ( .A(n1961), .B(underflow_flag), .Y(n1962) );
OAI21XLTS U966 ( .A0(n1206), .A1(n1183), .B0(n1182), .Y(n1188) );
MX2X1TS U967 ( .A(P_Sgf[0]), .B(n2327), .S0(n2326), .Y(n215) );
MX2X1TS U968 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n2326), .Y(
n217) );
MX2X1TS U969 ( .A(P_Sgf[9]), .B(Sgf_operation_Result[9]), .S0(n2337), .Y(
n224) );
MX2X1TS U970 ( .A(P_Sgf[10]), .B(Sgf_operation_Result[10]), .S0(n2337), .Y(
n225) );
MX2X1TS U971 ( .A(P_Sgf[12]), .B(n2335), .S0(n2337), .Y(n227) );
CLKAND2X2TS U972 ( .A(n2334), .B(n2333), .Y(n2335) );
OR2X1TS U973 ( .A(n2332), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(
n2334) );
MX2X1TS U974 ( .A(P_Sgf[14]), .B(n2331), .S0(n2337), .Y(n229) );
NAND4XLTS U975 ( .A(n2357), .B(n2356), .C(n2355), .D(n2354), .Y(n2364) );
NAND4XLTS U976 ( .A(n2353), .B(n2352), .C(n2351), .D(n2350), .Y(n2365) );
MX2X1TS U977 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n459), .Y(n312) );
MX2X1TS U978 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n459), .Y(n313) );
MX2X1TS U979 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n1984), .Y(n314) );
MX2X1TS U980 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n1985), .Y(n315) );
MX2X1TS U981 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n458), .Y(n317) );
MX2X1TS U982 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n458), .Y(n318) );
MX2X1TS U983 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n1985), .Y(n319) );
MX2X1TS U984 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n1984), .Y(n324) );
MX2X1TS U985 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n2336), .Y(n325) );
MX2X1TS U986 ( .A(Data_MY[14]), .B(n529), .S0(n2369), .Y(n326) );
MX2X1TS U987 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n1984), .Y(n345) );
MX2X1TS U988 ( .A(Data_MX[4]), .B(n443), .S0(n1982), .Y(n348) );
MX2X1TS U989 ( .A(Data_MX[5]), .B(n401), .S0(n1982), .Y(n349) );
MX2X1TS U990 ( .A(Data_MX[6]), .B(n2358), .S0(n1982), .Y(n350) );
MX2X1TS U991 ( .A(Data_MX[7]), .B(n400), .S0(n1982), .Y(n351) );
MX2X1TS U992 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n1982), .Y(n352) );
MX2X1TS U993 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n459), .Y(n356) );
MX2X1TS U994 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n459), .Y(n358) );
MX2X1TS U995 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n1984), .Y(n360) );
MX2X1TS U996 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n1984), .Y(n362) );
MX2X1TS U997 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n1984), .Y(n363) );
MX2X1TS U998 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n1984), .Y(n364) );
MX2X1TS U999 ( .A(Data_MX[21]), .B(n520), .S0(n1985), .Y(n365) );
NAND2BXLTS U1000 ( .AN(zero_flag), .B(n527), .Y(n2267) );
OAI21XLTS U1001 ( .A0(n981), .A1(n958), .B0(n957), .Y(n963) );
OAI21XLTS U1002 ( .A0(n981), .A1(n977), .B0(n978), .Y(n976) );
XOR2XLTS U1003 ( .A(n981), .B(n980), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N17) );
NOR2X1TS U1004 ( .A(n912), .B(n916), .Y(n904) );
XNOR2X1TS U1005 ( .A(n1583), .B(n793), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
AOI21X1TS U1006 ( .A0(n1377), .A1(n1379), .B0(n863), .Y(n868) );
INVX2TS U1007 ( .A(n1382), .Y(n1384) );
XOR2XLTS U1008 ( .A(n1414), .B(n1413), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
XOR2XLTS U1009 ( .A(n1422), .B(n1421), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
CLKAND2X2TS U1010 ( .A(n1529), .B(n1528), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
OR2X1TS U1011 ( .A(n1527), .B(n1526), .Y(n1529) );
OAI21XLTS U1012 ( .A0(n1206), .A1(n1202), .B0(n1203), .Y(n1201) );
XOR2XLTS U1013 ( .A(n1206), .B(n1205), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N17) );
OAI21XLTS U1014 ( .A0(n1329), .A1(n1325), .B0(n1326), .Y(n1236) );
CLKAND2X2TS U1015 ( .A(n1324), .B(n1323), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N1) );
OR2X1TS U1016 ( .A(n1322), .B(n1321), .Y(n1324) );
NAND2X2TS U1017 ( .A(n591), .B(n406), .Y(n781) );
CMPR42X2TS U1018 ( .A(DP_OP_111J22_123_4462_n438), .B(
DP_OP_111J22_123_4462_n425), .C(DP_OP_111J22_123_4462_n302), .D(
DP_OP_111J22_123_4462_n296), .ICI(DP_OP_111J22_123_4462_n298), .S(
DP_OP_111J22_123_4462_n293), .ICO(DP_OP_111J22_123_4462_n291), .CO(
DP_OP_111J22_123_4462_n292) );
AOI21X4TS U1019 ( .A0(n1181), .A1(n842), .B0(n841), .Y(n1180) );
XNOR2X4TS U1020 ( .A(n1435), .B(n1434), .Y(n410) );
XNOR2X2TS U1021 ( .A(n1431), .B(n1430), .Y(n1435) );
AND2X4TS U1022 ( .A(n1436), .B(n515), .Y(n1563) );
AOI21X2TS U1023 ( .A0(n1230), .A1(n1209), .B0(n1208), .Y(n1219) );
INVX4TS U1024 ( .A(n722), .Y(n465) );
INVX2TS U1025 ( .A(n409), .Y(n461) );
INVX2TS U1026 ( .A(n807), .Y(n488) );
INVX2TS U1027 ( .A(n794), .Y(n486) );
INVX2TS U1028 ( .A(n741), .Y(n517) );
INVX2TS U1029 ( .A(n699), .Y(n1525) );
CLKXOR2X2TS U1030 ( .A(n710), .B(n709), .Y(n402) );
CLKBUFX2TS U1031 ( .A(n1093), .Y(n469) );
OR2X1TS U1032 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .Y(n404) );
INVX4TS U1033 ( .A(n1168), .Y(n541) );
INVX2TS U1034 ( .A(n1168), .Y(n540) );
AND2X2TS U1035 ( .A(n649), .B(n648), .Y(n408) );
CLKXOR2X2TS U1036 ( .A(n683), .B(n682), .Y(n693) );
CLKXOR2X2TS U1037 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n794) );
CLKXOR2X2TS U1038 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1283) );
CLKXOR2X2TS U1039 ( .A(n708), .B(n698), .Y(n409) );
INVX2TS U1040 ( .A(n872), .Y(n482) );
CLKXOR2X2TS U1041 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1427) );
CLKXOR2X4TS U1042 ( .A(n888), .B(Op_MX[11]), .Y(n412) );
CLKXOR2X2TS U1043 ( .A(n740), .B(n739), .Y(n741) );
INVX2TS U1044 ( .A(n402), .Y(n430) );
INVX2TS U1045 ( .A(n1616), .Y(n462) );
NAND2X2TS U1046 ( .A(n684), .B(n693), .Y(n1616) );
INVX2TS U1047 ( .A(n599), .Y(n427) );
INVX2TS U1048 ( .A(n421), .Y(n506) );
OR2X1TS U1049 ( .A(P_Sgf[14]), .B(P_Sgf[12]), .Y(n423) );
NOR4X1TS U1050 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n424) );
INVX2TS U1051 ( .A(n1983), .Y(n1985) );
BUFX3TS U1052 ( .A(n881), .Y(n425) );
BUFX3TS U1053 ( .A(n881), .Y(n426) );
CLKXOR2X2TS U1054 ( .A(n880), .B(n879), .Y(n881) );
CLKXOR2X4TS U1055 ( .A(n1444), .B(n1443), .Y(n1519) );
AOI21X2TS U1056 ( .A0(n899), .A1(n930), .B0(n898), .Y(n1579) );
OAI21X2TS U1057 ( .A0(n937), .A1(n942), .B0(n943), .Y(n898) );
ADDFHX2TS U1058 ( .A(n1596), .B(n1595), .CI(n1594), .CO(
DP_OP_111J22_123_4462_n289), .S(DP_OP_111J22_123_4462_n297) );
CMPR42X2TS U1059 ( .A(DP_OP_111J22_123_4462_n444), .B(
DP_OP_111J22_123_4462_n350), .C(DP_OP_111J22_123_4462_n470), .D(
DP_OP_111J22_123_4462_n346), .ICI(DP_OP_111J22_123_4462_n347), .S(
DP_OP_111J22_123_4462_n343), .ICO(DP_OP_111J22_123_4462_n341), .CO(
DP_OP_111J22_123_4462_n342) );
AOI21X4TS U1060 ( .A0(n950), .A1(n948), .B0(n651), .Y(n662) );
BUFX3TS U1061 ( .A(n1148), .Y(n538) );
AOI21X2TS U1062 ( .A0(n629), .A1(n1037), .B0(n628), .Y(n1035) );
INVX2TS U1063 ( .A(n427), .Y(n428) );
INVX2TS U1064 ( .A(n427), .Y(n429) );
INVX2TS U1065 ( .A(n430), .Y(n431) );
INVX2TS U1066 ( .A(n430), .Y(n432) );
INVX2TS U1067 ( .A(n572), .Y(n433) );
INVX2TS U1068 ( .A(n577), .Y(n434) );
INVX2TS U1069 ( .A(n579), .Y(n437) );
INVX2TS U1070 ( .A(n407), .Y(n438) );
INVX2TS U1071 ( .A(n391), .Y(n439) );
INVX2TS U1072 ( .A(n590), .Y(n441) );
INVX2TS U1073 ( .A(n396), .Y(n442) );
INVX2TS U1074 ( .A(n394), .Y(n443) );
INVX2TS U1075 ( .A(n581), .Y(n444) );
INVX2TS U1076 ( .A(n2006), .Y(n445) );
INVX2TS U1077 ( .A(n445), .Y(n446) );
INVX2TS U1078 ( .A(n445), .Y(n447) );
INVX4TS U1079 ( .A(n417), .Y(n448) );
INVX2TS U1080 ( .A(n418), .Y(n450) );
INVX2TS U1081 ( .A(n596), .Y(n451) );
INVX2TS U1082 ( .A(n596), .Y(n452) );
INVX2TS U1083 ( .A(n897), .Y(n454) );
INVX2TS U1084 ( .A(Op_MY[0]), .Y(n455) );
INVX2TS U1085 ( .A(n1983), .Y(n458) );
INVX2TS U1086 ( .A(n1983), .Y(n459) );
INVX4TS U1087 ( .A(n409), .Y(n460) );
INVX2TS U1088 ( .A(n462), .Y(n464) );
XNOR2X2TS U1089 ( .A(n1093), .B(Op_MY[2]), .Y(n599) );
INVX2TS U1090 ( .A(n412), .Y(n474) );
INVX2TS U1091 ( .A(n412), .Y(n475) );
INVX2TS U1092 ( .A(n699), .Y(n476) );
INVX2TS U1093 ( .A(n794), .Y(n487) );
INVX2TS U1094 ( .A(n488), .Y(n489) );
INVX2TS U1095 ( .A(n488), .Y(n490) );
INVX2TS U1096 ( .A(n1427), .Y(n492) );
INVX2TS U1097 ( .A(n411), .Y(n494) );
INVX2TS U1098 ( .A(n1283), .Y(n496) );
INVX2TS U1099 ( .A(n415), .Y(n498) );
INVX2TS U1100 ( .A(n648), .Y(n499) );
INVX2TS U1101 ( .A(n499), .Y(n500) );
INVX2TS U1102 ( .A(n499), .Y(n501) );
INVX4TS U1103 ( .A(n502), .Y(n503) );
INVX2TS U1104 ( .A(n413), .Y(n510) );
INVX2TS U1105 ( .A(n420), .Y(n514) );
INVX2TS U1106 ( .A(n410), .Y(n516) );
INVX2TS U1107 ( .A(n517), .Y(n518) );
INVX2TS U1108 ( .A(n517), .Y(n519) );
INVX2TS U1109 ( .A(n414), .Y(n520) );
INVX2TS U1110 ( .A(n414), .Y(n521) );
NOR2XLTS U1111 ( .A(P_Sgf[47]), .B(n2263), .Y(n2264) );
CMPR42X1TS U1112 ( .A(mult_x_23_n340), .B(mult_x_23_n249), .C(mult_x_23_n253), .D(mult_x_23_n247), .ICI(mult_x_23_n250), .S(mult_x_23_n245), .ICO(
mult_x_23_n243), .CO(mult_x_23_n244) );
ADDHX1TS U1113 ( .A(n1367), .B(n1366), .CO(mult_x_23_n248), .S(
mult_x_23_n249) );
NOR2X2TS U1114 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1981) );
NOR4X1TS U1115 ( .A(n554), .B(n444), .C(n400), .D(Op_MX[0]), .Y(n2360) );
NOR4X1TS U1116 ( .A(Op_MY[11]), .B(Op_MY[0]), .C(Op_MY[13]), .D(Op_MY[9]),
.Y(n2351) );
NOR4X1TS U1117 ( .A(Op_MY[8]), .B(Op_MY[6]), .C(Op_MY[4]), .D(Op_MY[2]), .Y(
n2352) );
NAND2X1TS U1118 ( .A(n804), .B(n803), .Y(n1269) );
ADDHX1TS U1119 ( .A(n811), .B(n810), .CO(n812), .S(n804) );
INVX2TS U1120 ( .A(n422), .Y(n522) );
INVX2TS U1121 ( .A(n422), .Y(n523) );
INVX2TS U1122 ( .A(n422), .Y(n524) );
NOR2X2TS U1123 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n2230) );
INVX2TS U1124 ( .A(n576), .Y(n526) );
XNOR2X2TS U1125 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n708) );
INVX2TS U1126 ( .A(n528), .Y(n529) );
NOR2X2TS U1127 ( .A(Op_MY[14]), .B(Op_MY[2]), .Y(n726) );
BUFX3TS U1128 ( .A(n897), .Y(n530) );
OR2X1TS U1129 ( .A(n1587), .B(n530), .Y(n1588) );
CLKBUFX2TS U1130 ( .A(n1345), .Y(n533) );
CLKBUFX2TS U1131 ( .A(n1353), .Y(n534) );
INVX2TS U1132 ( .A(n1365), .Y(n535) );
INVX2TS U1133 ( .A(n1365), .Y(n536) );
CLKBUFX2TS U1134 ( .A(n1140), .Y(n537) );
BUFX3TS U1135 ( .A(n1154), .Y(n539) );
INVX2TS U1136 ( .A(n1534), .Y(n543) );
INVX2TS U1137 ( .A(n1556), .Y(n545) );
INVX4TS U1138 ( .A(n1563), .Y(n546) );
INVX2TS U1139 ( .A(n1563), .Y(n547) );
INVX4TS U1140 ( .A(n1611), .Y(n548) );
INVX2TS U1141 ( .A(n1611), .Y(n549) );
INVX2TS U1142 ( .A(n585), .Y(n550) );
BUFX3TS U1143 ( .A(Op_MX[0]), .Y(n1152) );
INVX2TS U1144 ( .A(n551), .Y(n552) );
BUFX3TS U1145 ( .A(Op_MY[12]), .Y(n1362) );
AOI21X1TS U1146 ( .A0(n1208), .A1(n837), .B0(n836), .Y(n838) );
NOR2XLTS U1147 ( .A(n404), .B(n423), .Y(n1627) );
OAI22X1TS U1148 ( .A0(n456), .A1(n1065), .B0(n501), .B1(n1064), .Y(
mult_x_55_n294) );
NOR4X1TS U1149 ( .A(P_Sgf[20]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[21]),
.Y(n1631) );
NOR4X1TS U1150 ( .A(Op_MX[22]), .B(Op_MX[19]), .C(Op_MX[17]), .D(Op_MX[15]),
.Y(n2355) );
NOR4X1TS U1151 ( .A(Op_MY[7]), .B(Op_MY[5]), .C(Op_MY[3]), .D(Op_MY[1]), .Y(
n2353) );
OAI22X2TS U1152 ( .A0(ack_FSM), .A1(n1963), .B0(beg_FSM), .B1(n2406), .Y(
n2266) );
INVX2TS U1153 ( .A(n1614), .Y(n553) );
NAND2X1TS U1154 ( .A(n587), .B(n706), .Y(n1614) );
NOR3XLTS U1155 ( .A(Op_MY[10]), .B(Op_MY[12]), .C(Op_MY[23]), .Y(n2350) );
NOR3XLTS U1156 ( .A(Op_MX[12]), .B(Op_MX[13]), .C(Op_MX[24]), .Y(n2359) );
INVX2TS U1157 ( .A(n592), .Y(n555) );
NAND2X1TS U1158 ( .A(Op_MY[20]), .B(Op_MY[8]), .Y(n1447) );
NOR2X1TS U1159 ( .A(Op_MY[20]), .B(Op_MY[8]), .Y(n869) );
BUFX3TS U1160 ( .A(n1948), .Y(n556) );
BUFX3TS U1161 ( .A(n1948), .Y(n2252) );
NOR2X2TS U1162 ( .A(n2391), .B(n1947), .Y(n1948) );
INVX2TS U1163 ( .A(n2250), .Y(n557) );
INVX2TS U1164 ( .A(n2250), .Y(n558) );
INVX2TS U1165 ( .A(n2250), .Y(n559) );
NAND2X1TS U1166 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n1987) );
AO21X1TS U1167 ( .A0(n1582), .A1(n1581), .B0(n1580), .Y(n564) );
OR2X2TS U1168 ( .A(FSM_selector_B[1]), .B(n2386), .Y(n567) );
BUFX3TS U1169 ( .A(Op_MY[22]), .Y(n1986) );
INVX2TS U1170 ( .A(n2381), .Y(n2327) );
BUFX3TS U1171 ( .A(Op_MY[18]), .Y(n1330) );
OR2X1TS U1172 ( .A(n1794), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]),
.Y(n578) );
INVX2TS U1173 ( .A(Op_MX[12]), .Y(n700) );
OR2X2TS U1174 ( .A(DP_OP_111J22_123_4462_n356), .B(
DP_OP_111J22_123_4462_n360), .Y(n591) );
AO21X1TS U1175 ( .A0(n889), .A1(n885), .B0(n870), .Y(n593) );
NAND2X1TS U1176 ( .A(Op_MY[18]), .B(Op_MY[6]), .Y(n1441) );
NAND2X1TS U1177 ( .A(n1771), .B(n1664), .Y(n1666) );
NOR2XLTS U1178 ( .A(n596), .B(n589), .Y(n1281) );
NAND2X4TS U1179 ( .A(n815), .B(n807), .Y(n1345) );
NOR2XLTS U1180 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1979) );
CMPR42X1TS U1181 ( .A(mult_x_23_n312), .B(mult_x_23_n336), .C(mult_x_23_n300), .D(n596), .ICI(mult_x_23_n224), .S(mult_x_23_n217), .ICO(mult_x_23_n215),
.CO(mult_x_23_n216) );
INVX2TS U1182 ( .A(n2136), .Y(n2138) );
INVX2TS U1183 ( .A(n2108), .Y(n2110) );
CMPR42X1TS U1184 ( .A(mult_x_55_n237), .B(mult_x_55_n234), .C(mult_x_55_n231), .D(mult_x_55_n235), .ICI(mult_x_55_n228), .S(mult_x_55_n225), .ICO(
mult_x_55_n223), .CO(mult_x_55_n224) );
INVX2TS U1185 ( .A(n2159), .Y(n2258) );
AOI21X1TS U1186 ( .A0(n965), .A1(n969), .B0(n645), .Y(n957) );
OAI21X2TS U1187 ( .A0(n638), .A1(n1012), .B0(n637), .Y(n1006) );
INVX2TS U1188 ( .A(n1418), .Y(n1420) );
OAI21XLTS U1189 ( .A0(n1031), .A1(n1027), .B0(n1028), .Y(n1026) );
OR2X1TS U1190 ( .A(n1097), .B(n1096), .Y(n1099) );
NAND2X1TS U1191 ( .A(n927), .B(n926), .Y(n928) );
OAI21X1TS U1192 ( .A0(n1421), .A1(n1418), .B0(n1419), .Y(n1416) );
AOI21X2TS U1193 ( .A0(n1263), .A1(n582), .B0(n824), .Y(n1259) );
NOR2X2TS U1195 ( .A(mult_x_55_n225), .B(mult_x_55_n232), .Y(n1007) );
NOR2X2TS U1196 ( .A(mult_x_55_n233), .B(mult_x_55_n240), .Y(n1106) );
OR2X2TS U1197 ( .A(mult_x_55_n241), .B(mult_x_55_n246), .Y(n1015) );
NAND2X1TS U1198 ( .A(n1015), .B(n580), .Y(n638) );
NOR2X2TS U1199 ( .A(mult_x_55_n254), .B(mult_x_55_n258), .Y(n1022) );
NOR2X2TS U1200 ( .A(mult_x_55_n259), .B(mult_x_55_n263), .Y(n1027) );
NOR2X1TS U1201 ( .A(n1022), .B(n1027), .Y(n635) );
XOR2X1TS U1202 ( .A(Op_MY[2]), .B(Op_MY[3]), .Y(n600) );
XNOR2X1TS U1203 ( .A(Op_MY[3]), .B(n433), .Y(n605) );
XNOR2X1TS U1204 ( .A(n498), .B(n434), .Y(n1092) );
OAI22X1TS U1205 ( .A0(n537), .A1(n605), .B0(n428), .B1(n1092), .Y(n632) );
XNOR2X1TS U1206 ( .A(Op_MY[4]), .B(Op_MY[3]), .Y(n601) );
XNOR2X1TS U1207 ( .A(n450), .B(n550), .Y(n603) );
XNOR2X1TS U1208 ( .A(Op_MY[5]), .B(Op_MX[1]), .Y(n1085) );
OAI22X1TS U1209 ( .A0(n538), .A1(n603), .B0(n1146), .B1(n1085), .Y(n631) );
OAI22X1TS U1210 ( .A0(n1148), .A1(n418), .B0(n1146), .B1(n604), .Y(n664) );
NAND2X2TS U1211 ( .A(n1093), .B(n455), .Y(n1095) );
XNOR2X1TS U1212 ( .A(n1093), .B(n443), .Y(n606) );
XNOR2X1TS U1213 ( .A(n1093), .B(n401), .Y(n1094) );
OAI22X1TS U1214 ( .A0(n1163), .A1(n606), .B0(n1094), .B1(n566), .Y(n663) );
NOR2BX1TS U1215 ( .AN(n550), .B(n1146), .Y(n609) );
XNOR2X1TS U1216 ( .A(Op_MY[3]), .B(Op_MX[1]), .Y(n611) );
OAI22X1TS U1217 ( .A0(n1140), .A1(n611), .B0(n599), .B1(n605), .Y(n608) );
XNOR2X1TS U1218 ( .A(n469), .B(n434), .Y(n620) );
OAI22X1TS U1219 ( .A0(n1163), .A1(n620), .B0(n606), .B1(n566), .Y(n607) );
CMPR32X2TS U1220 ( .A(n609), .B(n608), .C(n607), .CO(n626), .S(n625) );
OAI22X1TS U1221 ( .A0(n1140), .A1(n415), .B0(n428), .B1(n610), .Y(n619) );
XNOR2X1TS U1222 ( .A(Op_MY[3]), .B(n1152), .Y(n612) );
OAI22X1TS U1223 ( .A0(n1140), .A1(n612), .B0(n429), .B1(n611), .Y(n618) );
NOR2X2TS U1224 ( .A(n625), .B(n624), .Y(n1043) );
NOR2X1TS U1225 ( .A(n1038), .B(n1043), .Y(n629) );
XNOR2X1TS U1226 ( .A(n1093), .B(Op_MX[1]), .Y(n613) );
XNOR2X1TS U1227 ( .A(n1093), .B(n433), .Y(n621) );
OAI22X1TS U1228 ( .A0(n1095), .A1(n613), .B0(n621), .B1(n455), .Y(n616) );
NOR2BX1TS U1229 ( .AN(n1152), .B(n429), .Y(n615) );
OAI22X1TS U1230 ( .A0(n1163), .A1(n1152), .B0(n613), .B1(n455), .Y(n1097) );
NAND2X1TS U1231 ( .A(n614), .B(n1163), .Y(n1096) );
NAND2X1TS U1232 ( .A(n1097), .B(n1096), .Y(n1098) );
INVX2TS U1233 ( .A(n1098), .Y(n1055) );
NAND2X1TS U1234 ( .A(n616), .B(n615), .Y(n1053) );
INVX2TS U1235 ( .A(n1053), .Y(n617) );
AOI21X1TS U1236 ( .A0(n1054), .A1(n1055), .B0(n617), .Y(n1051) );
ADDHX1TS U1237 ( .A(n619), .B(n618), .CO(n624), .S(n623) );
OAI22X1TS U1238 ( .A0(n1163), .A1(n621), .B0(n620), .B1(n566), .Y(n622) );
NOR2X1TS U1239 ( .A(n623), .B(n622), .Y(n1048) );
NAND2X1TS U1240 ( .A(n623), .B(n622), .Y(n1049) );
OAI21X1TS U1241 ( .A0(n1051), .A1(n1048), .B0(n1049), .Y(n1037) );
NAND2X1TS U1242 ( .A(n625), .B(n624), .Y(n1044) );
NAND2X1TS U1243 ( .A(n627), .B(n626), .Y(n1039) );
OAI21X1TS U1244 ( .A0(n1038), .A1(n1044), .B0(n1039), .Y(n628) );
CMPR32X2TS U1245 ( .A(n632), .B(n631), .C(n630), .CO(n633), .S(n627) );
NOR2X1TS U1246 ( .A(mult_x_55_n264), .B(n633), .Y(n1032) );
NAND2X1TS U1247 ( .A(mult_x_55_n264), .B(n633), .Y(n1033) );
NAND2X1TS U1248 ( .A(mult_x_55_n259), .B(mult_x_55_n263), .Y(n1028) );
NAND2X1TS U1249 ( .A(mult_x_55_n254), .B(mult_x_55_n258), .Y(n1023) );
NAND2X1TS U1250 ( .A(mult_x_55_n247), .B(mult_x_55_n253), .Y(n1018) );
INVX2TS U1251 ( .A(n1018), .Y(n1013) );
NAND2X1TS U1252 ( .A(mult_x_55_n241), .B(mult_x_55_n246), .Y(n1014) );
INVX2TS U1253 ( .A(n1014), .Y(n636) );
AOI21X1TS U1254 ( .A0(n1015), .A1(n1013), .B0(n636), .Y(n637) );
NAND2X2TS U1255 ( .A(mult_x_55_n233), .B(mult_x_55_n240), .Y(n1107) );
NAND2X1TS U1256 ( .A(mult_x_55_n225), .B(mult_x_55_n232), .Y(n1008) );
OAI21X1TS U1257 ( .A0(n1007), .A1(n1107), .B0(n1008), .Y(n639) );
AOI21X4TS U1258 ( .A0(n640), .A1(n1006), .B0(n639), .Y(n982) );
NOR2X2TS U1259 ( .A(n997), .B(n995), .Y(n984) );
NOR2X2TS U1260 ( .A(mult_x_55_n198), .B(mult_x_55_n205), .Y(n990) );
NOR2X2TS U1261 ( .A(mult_x_55_n190), .B(mult_x_55_n197), .Y(n985) );
NOR2X2TS U1262 ( .A(n990), .B(n985), .Y(n642) );
NAND2X1TS U1263 ( .A(mult_x_55_n206), .B(mult_x_55_n215), .Y(n998) );
NAND2X1TS U1264 ( .A(mult_x_55_n198), .B(mult_x_55_n205), .Y(n991) );
NAND2X1TS U1265 ( .A(mult_x_55_n190), .B(mult_x_55_n197), .Y(n986) );
OAI21X4TS U1266 ( .A0(n982), .A1(n644), .B0(n643), .Y(n956) );
NOR2X2TS U1267 ( .A(mult_x_55_n184), .B(mult_x_55_n189), .Y(n977) );
NOR2X2TS U1268 ( .A(mult_x_55_n183), .B(mult_x_55_n177), .Y(n972) );
NOR2X2TS U1269 ( .A(mult_x_55_n171), .B(mult_x_55_n167), .Y(n959) );
NAND2X2TS U1270 ( .A(mult_x_55_n184), .B(mult_x_55_n189), .Y(n978) );
NAND2X1TS U1271 ( .A(mult_x_55_n183), .B(mult_x_55_n177), .Y(n973) );
NAND2X1TS U1272 ( .A(mult_x_55_n176), .B(mult_x_55_n172), .Y(n968) );
INVX2TS U1273 ( .A(n968), .Y(n645) );
NAND2X1TS U1274 ( .A(mult_x_55_n171), .B(mult_x_55_n167), .Y(n960) );
OAI21X1TS U1275 ( .A0(n957), .A1(n959), .B0(n960), .Y(n646) );
AOI21X4TS U1276 ( .A0(n956), .A1(n647), .B0(n646), .Y(n955) );
NOR2X1TS U1277 ( .A(mult_x_55_n166), .B(mult_x_55_n164), .Y(n951) );
NAND2X1TS U1278 ( .A(mult_x_55_n166), .B(mult_x_55_n164), .Y(n952) );
NOR2X1TS U1279 ( .A(n471), .B(n581), .Y(n656) );
INVX2TS U1280 ( .A(n656), .Y(n653) );
XOR2X1TS U1281 ( .A(Op_MY[10]), .B(Op_MY[11]), .Y(n649) );
XNOR2X1TS U1282 ( .A(Op_MY[10]), .B(Op_MY[9]), .Y(n648) );
XNOR2X1TS U1283 ( .A(n472), .B(n554), .Y(n1058) );
OAI22X1TS U1284 ( .A0(n457), .A1(n1058), .B0(n501), .B1(
DP_OP_111J22_123_4462_n727), .Y(n652) );
NAND2X1TS U1285 ( .A(mult_x_55_n163), .B(n650), .Y(n947) );
INVX2TS U1286 ( .A(n947), .Y(n651) );
CMPR32X2TS U1287 ( .A(n653), .B(n652), .C(mult_x_55_n162), .CO(n658), .S(
n650) );
NOR2X1TS U1288 ( .A(n471), .B(n561), .Y(n655) );
NAND2X1TS U1289 ( .A(n658), .B(n657), .Y(n659) );
NAND2X1TS U1290 ( .A(n660), .B(n659), .Y(n661) );
ADDHX1TS U1291 ( .A(n664), .B(n663), .CO(mult_x_55_n267), .S(n630) );
NOR2X2TS U1292 ( .A(Op_MY[13]), .B(Op_MY[1]), .Y(n702) );
NAND2X2TS U1293 ( .A(Op_MY[12]), .B(Op_MY[0]), .Y(n706) );
NAND2X1TS U1294 ( .A(Op_MY[13]), .B(Op_MY[1]), .Y(n703) );
NOR2X2TS U1295 ( .A(n726), .B(n728), .Y(n666) );
NAND2X2TS U1296 ( .A(Op_MY[14]), .B(Op_MY[2]), .Y(n725) );
OAI21X2TS U1297 ( .A0(n728), .A1(n725), .B0(n729), .Y(n665) );
AOI21X4TS U1298 ( .A0(n695), .A1(n666), .B0(n665), .Y(n690) );
NOR2X2TS U1299 ( .A(n441), .B(Op_MY[4]), .Y(n743) );
NOR2X2TS U1300 ( .A(n743), .B(n766), .Y(n1438) );
INVX2TS U1301 ( .A(n1438), .Y(n667) );
NOR2X1TS U1302 ( .A(n667), .B(n1440), .Y(n670) );
NAND2X2TS U1303 ( .A(n441), .B(Op_MY[4]), .Y(n763) );
NAND2X1TS U1304 ( .A(Op_MY[17]), .B(Op_MY[5]), .Y(n767) );
OAI21X4TS U1305 ( .A0(n766), .A1(n763), .B0(n767), .Y(n1437) );
INVX2TS U1306 ( .A(n1437), .Y(n668) );
OAI21X1TS U1307 ( .A0(n668), .A1(n1440), .B0(n1441), .Y(n669) );
AOI21X2TS U1308 ( .A0(n1439), .A1(n670), .B0(n669), .Y(n673) );
INVX2TS U1309 ( .A(n686), .Y(n671) );
NAND2X1TS U1310 ( .A(n439), .B(Op_MY[7]), .Y(n685) );
NAND2X1TS U1311 ( .A(n671), .B(n685), .Y(n672) );
CLKXOR2X4TS U1312 ( .A(n673), .B(n672), .Y(n1517) );
OAI21X1TS U1313 ( .A0(Op_MX[10]), .A1(Op_MX[22]), .B0(n437), .Y(n675) );
NAND2X1TS U1314 ( .A(Op_MX[10]), .B(Op_MX[22]), .Y(n674) );
NAND2X2TS U1315 ( .A(n675), .B(n674), .Y(n888) );
XNOR2X1TS U1316 ( .A(n1517), .B(n474), .Y(n1464) );
XOR2X1TS U1317 ( .A(Op_MX[21]), .B(Op_MX[10]), .Y(n676) );
NOR2X1TS U1318 ( .A(n676), .B(n679), .Y(n677) );
XOR2X1TS U1319 ( .A(n677), .B(n554), .Y(n684) );
NOR2X1TS U1320 ( .A(n437), .B(Op_MX[21]), .Y(n678) );
XNOR2X1TS U1321 ( .A(n679), .B(n678), .Y(n683) );
XNOR2X2TS U1322 ( .A(n437), .B(Op_MX[21]), .Y(n873) );
OAI21X1TS U1323 ( .A0(Op_MX[8]), .A1(Op_MX[20]), .B0(n436), .Y(n681) );
NAND2X1TS U1324 ( .A(Op_MX[8]), .B(Op_MX[20]), .Y(n680) );
NAND2X2TS U1325 ( .A(n1438), .B(n688), .Y(n691) );
AOI21X2TS U1326 ( .A0(n1437), .A1(n688), .B0(n687), .Y(n689) );
OAI21X4TS U1327 ( .A0(n691), .A1(n690), .B0(n689), .Y(n895) );
INVX2TS U1328 ( .A(n869), .Y(n1449) );
XNOR2X4TS U1329 ( .A(n895), .B(n692), .Y(n1515) );
XNOR2X1TS U1330 ( .A(n1515), .B(n475), .Y(n1462) );
NAND2X4TS U1331 ( .A(DP_OP_111J22_123_4462_n310), .B(
DP_OP_111J22_123_4462_n318), .Y(n1378) );
NAND2X2TS U1332 ( .A(DP_OP_111J22_123_4462_n300), .B(
DP_OP_111J22_123_4462_n309), .Y(n865) );
OAI21X4TS U1333 ( .A0(n864), .A1(n1378), .B0(n865), .Y(n1370) );
AOI21X4TS U1334 ( .A0(n1370), .A1(n789), .B0(n694), .Y(n792) );
INVX2TS U1335 ( .A(n695), .Y(n727) );
INVX2TS U1336 ( .A(n726), .Y(n696) );
NAND2X1TS U1337 ( .A(n696), .B(n725), .Y(n697) );
CLKXOR2X4TS U1338 ( .A(n727), .B(n697), .Y(n1609) );
XNOR2X1TS U1339 ( .A(n1609), .B(n460), .Y(n733) );
XOR2X1TS U1340 ( .A(Op_MX[0]), .B(Op_MX[12]), .Y(n699) );
XOR2X1TS U1341 ( .A(n700), .B(n708), .Y(n701) );
AND2X2TS U1342 ( .A(n701), .B(n476), .Y(n711) );
INVX2TS U1343 ( .A(n711), .Y(n1521) );
INVX2TS U1344 ( .A(n702), .Y(n704) );
CLKXOR2X4TS U1345 ( .A(n705), .B(n706), .Y(n1543) );
XNOR2X1TS U1346 ( .A(n1543), .B(n460), .Y(n712) );
OAI22X1TS U1347 ( .A0(n733), .A1(n476), .B0(n1521), .B1(n712), .Y(n715) );
XNOR2X1TS U1348 ( .A(n717), .B(n707), .Y(n710) );
NAND2X1TS U1349 ( .A(n708), .B(n698), .Y(n709) );
NOR2BX1TS U1350 ( .AN(n553), .B(n432), .Y(n714) );
INVX2TS U1351 ( .A(n711), .Y(n1523) );
NAND2X1TS U1352 ( .A(n713), .B(n1523), .Y(n1526) );
NAND2X1TS U1353 ( .A(n1527), .B(n1526), .Y(n1528) );
INVX2TS U1354 ( .A(n1528), .Y(n1424) );
NAND2X1TS U1355 ( .A(n715), .B(n714), .Y(n1423) );
INVX2TS U1356 ( .A(n1423), .Y(n716) );
AOI21X2TS U1357 ( .A0(n571), .A1(n1424), .B0(n716), .Y(n1421) );
NOR2X1TS U1358 ( .A(n794), .B(n717), .Y(n718) );
XNOR2X2TS U1359 ( .A(Op_MX[15]), .B(Op_MX[3]), .Y(n738) );
XOR2X1TS U1360 ( .A(n718), .B(n738), .Y(n719) );
OAI21X1TS U1361 ( .A0(Op_MX[2]), .A1(Op_MX[14]), .B0(n526), .Y(n721) );
NAND2X1TS U1362 ( .A(Op_MX[2]), .B(Op_MX[14]), .Y(n720) );
XNOR2X1TS U1363 ( .A(n738), .B(n737), .Y(n722) );
OAI22X1TS U1364 ( .A0(n542), .A1(n465), .B0(n432), .B1(n723), .Y(n747) );
XNOR2X1TS U1365 ( .A(n466), .B(n553), .Y(n724) );
XNOR2X1TS U1366 ( .A(n1543), .B(n466), .Y(n742) );
OAI22X1TS U1367 ( .A0(n542), .A1(n724), .B0(n742), .B1(n432), .Y(n746) );
OAI21X1TS U1368 ( .A0(n727), .A1(n726), .B0(n725), .Y(n732) );
INVX2TS U1369 ( .A(n728), .Y(n730) );
XNOR2X4TS U1370 ( .A(n732), .B(n731), .Y(n1597) );
XNOR2X1TS U1371 ( .A(n1597), .B(n460), .Y(n745) );
OAI22X1TS U1372 ( .A0(n745), .A1(n476), .B0(n733), .B1(n1523), .Y(n734) );
NOR2X1TS U1373 ( .A(n735), .B(n734), .Y(n1418) );
NAND2X1TS U1374 ( .A(n735), .B(n734), .Y(n1419) );
NOR2X1TS U1375 ( .A(Op_MX[15]), .B(Op_MX[3]), .Y(n736) );
NAND2X1TS U1376 ( .A(n738), .B(n737), .Y(n739) );
NOR2BX1TS U1377 ( .AN(n553), .B(n518), .Y(n762) );
XNOR2X1TS U1378 ( .A(n1609), .B(n466), .Y(n751) );
OAI22X1TS U1379 ( .A0(n751), .A1(n431), .B0(n542), .B1(n742), .Y(n761) );
INVX2TS U1380 ( .A(n743), .Y(n765) );
NAND2X2TS U1381 ( .A(n765), .B(n763), .Y(n744) );
XNOR2X4TS U1382 ( .A(n1439), .B(n744), .Y(n1504) );
XNOR2X1TS U1383 ( .A(n1504), .B(n460), .Y(n771) );
OAI22X1TS U1384 ( .A0(n771), .A1(n1525), .B0(n745), .B1(n1523), .Y(n760) );
ADDHX1TS U1385 ( .A(n747), .B(n746), .CO(n748), .S(n735) );
NAND2X1TS U1386 ( .A(n749), .B(n748), .Y(n1415) );
INVX2TS U1387 ( .A(n1415), .Y(n750) );
XNOR2X1TS U1388 ( .A(n1597), .B(n466), .Y(n1506) );
OAI22X1TS U1389 ( .A0(n1506), .A1(n432), .B0(n751), .B1(n543), .Y(n776) );
XOR2X1TS U1390 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n806) );
NOR2X1TS U1391 ( .A(n806), .B(n752), .Y(n753) );
XNOR2X2TS U1392 ( .A(Op_MX[17]), .B(n435), .Y(n1433) );
XOR2X1TS U1393 ( .A(n753), .B(n1433), .Y(n754) );
OAI21X1TS U1394 ( .A0(Op_MX[4]), .A1(Op_MX[16]), .B0(Op_MX[3]), .Y(n756) );
NAND2X1TS U1395 ( .A(Op_MX[4]), .B(Op_MX[16]), .Y(n755) );
NAND2X2TS U1396 ( .A(n756), .B(n755), .Y(n1432) );
XNOR2X1TS U1397 ( .A(n1433), .B(n1432), .Y(n757) );
INVX2TS U1398 ( .A(n478), .Y(n1485) );
XNOR2X1TS U1399 ( .A(n478), .B(n1608), .Y(n759) );
XNOR2X1TS U1400 ( .A(n1543), .B(n478), .Y(n1494) );
OAI22X1TS U1401 ( .A0(n544), .A1(n759), .B0(n1494), .B1(n518), .Y(n1625) );
CMPR32X2TS U1402 ( .A(n762), .B(n761), .C(n760), .CO(n774), .S(n749) );
INVX2TS U1403 ( .A(n763), .Y(n764) );
INVX2TS U1404 ( .A(n766), .Y(n768) );
NAND2X1TS U1405 ( .A(n768), .B(n767), .Y(n769) );
CLKXOR2X4TS U1406 ( .A(n770), .B(n769), .Y(n1502) );
XNOR2X1TS U1407 ( .A(n1502), .B(n461), .Y(n1524) );
OAI22X1TS U1408 ( .A0(n1524), .A1(n476), .B0(n771), .B1(n1521), .Y(n772) );
NOR2X2TS U1409 ( .A(n773), .B(n772), .Y(n1410) );
OAI21X4TS U1410 ( .A0(n1413), .A1(n1410), .B0(n1411), .Y(n1408) );
CMPR32X2TS U1411 ( .A(n776), .B(n775), .C(n774), .CO(n777), .S(n773) );
NAND2X1TS U1412 ( .A(DP_OP_111J22_123_4462_n366), .B(n777), .Y(n1407) );
INVX2TS U1413 ( .A(n1407), .Y(n778) );
AOI21X4TS U1414 ( .A0(n1408), .A1(n597), .B0(n778), .Y(n1399) );
INVX2TS U1415 ( .A(n1404), .Y(n1400) );
NAND2X2TS U1416 ( .A(DP_OP_111J22_123_4462_n356), .B(
DP_OP_111J22_123_4462_n360), .Y(n1401) );
INVX2TS U1417 ( .A(n1401), .Y(n779) );
AOI21X4TS U1418 ( .A0(n1400), .A1(n591), .B0(n779), .Y(n780) );
INVX2TS U1419 ( .A(n1396), .Y(n783) );
AOI21X4TS U1420 ( .A0(n1398), .A1(n782), .B0(n783), .Y(n1387) );
OR2X4TS U1421 ( .A(DP_OP_111J22_123_4462_n335), .B(
DP_OP_111J22_123_4462_n342), .Y(n1390) );
NAND2X2TS U1422 ( .A(n1390), .B(n405), .Y(n786) );
NAND2X2TS U1423 ( .A(DP_OP_111J22_123_4462_n343), .B(
DP_OP_111J22_123_4462_n348), .Y(n1393) );
INVX2TS U1424 ( .A(n1393), .Y(n1388) );
NAND2X2TS U1425 ( .A(DP_OP_111J22_123_4462_n335), .B(
DP_OP_111J22_123_4462_n342), .Y(n1389) );
INVX2TS U1426 ( .A(n1389), .Y(n784) );
OAI21X4TS U1427 ( .A0(n1387), .A1(n786), .B0(n785), .Y(n1381) );
NAND2X2TS U1428 ( .A(DP_OP_111J22_123_4462_n327), .B(
DP_OP_111J22_123_4462_n334), .Y(n1537) );
NAND2X2TS U1429 ( .A(DP_OP_111J22_123_4462_n319), .B(
DP_OP_111J22_123_4462_n326), .Y(n1383) );
AOI21X4TS U1430 ( .A0(n1381), .A1(n788), .B0(n787), .Y(n852) );
NOR2X4TS U1431 ( .A(DP_OP_111J22_123_4462_n310), .B(
DP_OP_111J22_123_4462_n318), .Y(n862) );
NOR2X4TS U1432 ( .A(n864), .B(n862), .Y(n1371) );
OR2X8TS U1433 ( .A(n852), .B(n790), .Y(n791) );
NAND2X8TS U1434 ( .A(n792), .B(n791), .Y(n1583) );
INVX2TS U1435 ( .A(n883), .Y(n924) );
NAND2X1TS U1436 ( .A(n924), .B(n922), .Y(n793) );
NOR2X2TS U1437 ( .A(mult_x_23_n223), .B(mult_x_23_n230), .Y(n1232) );
NOR2X2TS U1438 ( .A(mult_x_23_n231), .B(mult_x_23_n238), .Y(n1325) );
NOR2X2TS U1439 ( .A(n1232), .B(n1325), .Y(n835) );
NOR2X2TS U1440 ( .A(mult_x_23_n252), .B(mult_x_23_n256), .Y(n1246) );
NOR2X2TS U1441 ( .A(mult_x_23_n257), .B(mult_x_23_n261), .Y(n1251) );
NOR2X1TS U1442 ( .A(n1246), .B(n1251), .Y(n830) );
BUFX3TS U1443 ( .A(Op_MY[13]), .Y(n1356) );
XNOR2X1TS U1444 ( .A(n451), .B(n1356), .Y(n795) );
XNOR2X1TS U1445 ( .A(n451), .B(Op_MY[14]), .Y(n799) );
OAI22X1TS U1446 ( .A0(n1361), .A1(n795), .B0(n799), .B1(n589), .Y(n798) );
NOR2BX1TS U1447 ( .AN(n1362), .B(n486), .Y(n797) );
NOR2X1TS U1448 ( .A(n798), .B(n797), .Y(n1272) );
OAI22X1TS U1449 ( .A0(n1361), .A1(n1362), .B0(n795), .B1(n589), .Y(n1322) );
NAND2X1TS U1450 ( .A(n796), .B(n1361), .Y(n1321) );
NAND2X1TS U1451 ( .A(n1322), .B(n1321), .Y(n1323) );
NAND2X1TS U1452 ( .A(n798), .B(n797), .Y(n1273) );
XNOR2X1TS U1453 ( .A(n452), .B(n440), .Y(n808) );
OAI22X1TS U1454 ( .A0(n1361), .A1(n799), .B0(n808), .B1(n700), .Y(n811) );
XOR2X1TS U1455 ( .A(n505), .B(Op_MX[14]), .Y(n800) );
XNOR2X1TS U1456 ( .A(n506), .B(n1362), .Y(n801) );
XNOR2X1TS U1457 ( .A(n506), .B(n1356), .Y(n809) );
OAI22X1TS U1458 ( .A0(n531), .A1(n801), .B0(n809), .B1(n487), .Y(n810) );
OAI22X1TS U1459 ( .A0(n532), .A1(n421), .B0(n487), .B1(n802), .Y(n803) );
INVX2TS U1460 ( .A(n1269), .Y(n805) );
INVX2TS U1461 ( .A(n806), .Y(n807) );
NOR2BX1TS U1462 ( .AN(n552), .B(n489), .Y(n821) );
XNOR2X1TS U1463 ( .A(n452), .B(n441), .Y(n817) );
OAI22X1TS U1464 ( .A0(n1320), .A1(n808), .B0(n817), .B1(n589), .Y(n820) );
XNOR2X1TS U1465 ( .A(n506), .B(Op_MY[14]), .Y(n814) );
OAI22X1TS U1466 ( .A0(n532), .A1(n809), .B0(n814), .B1(n486), .Y(n819) );
NOR2X1TS U1467 ( .A(n813), .B(n812), .Y(n1264) );
NAND2X1TS U1468 ( .A(n813), .B(n812), .Y(n1265) );
OAI21X2TS U1469 ( .A0(n1267), .A1(n1264), .B0(n1265), .Y(n1263) );
XNOR2X1TS U1470 ( .A(n506), .B(n440), .Y(n1317) );
OAI22X1TS U1471 ( .A0(n532), .A1(n814), .B0(n1317), .B1(n486), .Y(n827) );
XOR2X1TS U1472 ( .A(n507), .B(Op_MX[16]), .Y(n815) );
XNOR2X1TS U1473 ( .A(n508), .B(n552), .Y(n816) );
XNOR2X1TS U1474 ( .A(n508), .B(n1356), .Y(n1311) );
OAI22X1TS U1475 ( .A0(n1345), .A1(n816), .B0(n1311), .B1(n490), .Y(n826) );
XNOR2X1TS U1476 ( .A(n452), .B(n442), .Y(n1319) );
OAI22X1TS U1477 ( .A0(n1361), .A1(n817), .B0(n1319), .B1(n589), .Y(n1369) );
OAI22X1TS U1478 ( .A0(n1345), .A1(n419), .B0(n489), .B1(n818), .Y(n1368) );
CMPR32X2TS U1479 ( .A(n821), .B(n820), .C(n819), .CO(n822), .S(n813) );
NAND2X1TS U1480 ( .A(n823), .B(n822), .Y(n1261) );
INVX2TS U1481 ( .A(n1261), .Y(n824) );
CMPR32X2TS U1482 ( .A(n827), .B(n826), .C(n825), .CO(n828), .S(n823) );
NOR2X1TS U1483 ( .A(mult_x_23_n262), .B(n828), .Y(n1256) );
NAND2X1TS U1484 ( .A(mult_x_23_n262), .B(n828), .Y(n1257) );
OAI21X4TS U1485 ( .A0(n1259), .A1(n1256), .B0(n1257), .Y(n1245) );
NAND2X1TS U1486 ( .A(mult_x_23_n257), .B(mult_x_23_n261), .Y(n1252) );
NAND2X1TS U1487 ( .A(mult_x_23_n252), .B(mult_x_23_n256), .Y(n1247) );
NAND2X1TS U1488 ( .A(n595), .B(n594), .Y(n833) );
NAND2X1TS U1489 ( .A(mult_x_23_n245), .B(mult_x_23_n251), .Y(n1242) );
INVX2TS U1490 ( .A(n1242), .Y(n1238) );
NAND2X1TS U1491 ( .A(mult_x_23_n239), .B(mult_x_23_n244), .Y(n1239) );
INVX2TS U1492 ( .A(n1239), .Y(n831) );
AOI21X1TS U1493 ( .A0(n595), .A1(n1238), .B0(n831), .Y(n832) );
OAI21X4TS U1494 ( .A0(n1237), .A1(n833), .B0(n832), .Y(n1231) );
NAND2X1TS U1495 ( .A(mult_x_23_n231), .B(mult_x_23_n238), .Y(n1326) );
NAND2X1TS U1496 ( .A(mult_x_23_n223), .B(mult_x_23_n230), .Y(n1233) );
OAI21X1TS U1497 ( .A0(n1232), .A1(n1326), .B0(n1233), .Y(n834) );
AOI21X4TS U1498 ( .A0(n835), .A1(n1231), .B0(n834), .Y(n1207) );
NOR2X1TS U1499 ( .A(mult_x_23_n214), .B(mult_x_23_n222), .Y(n1220) );
NOR2X2TS U1500 ( .A(n1220), .B(n1222), .Y(n1209) );
NOR2X2TS U1501 ( .A(mult_x_23_n196), .B(mult_x_23_n203), .Y(n1215) );
NOR2X2TS U1502 ( .A(n1215), .B(n1210), .Y(n837) );
NAND2X1TS U1503 ( .A(n1209), .B(n837), .Y(n839) );
NAND2X2TS U1504 ( .A(mult_x_23_n214), .B(mult_x_23_n222), .Y(n1227) );
NAND2X1TS U1505 ( .A(mult_x_23_n188), .B(mult_x_23_n195), .Y(n1211) );
NOR2X2TS U1506 ( .A(mult_x_23_n182), .B(mult_x_23_n187), .Y(n1202) );
NOR2X2TS U1507 ( .A(mult_x_23_n181), .B(mult_x_23_n175), .Y(n1197) );
NOR2X1TS U1508 ( .A(n1202), .B(n1197), .Y(n1189) );
NAND2X1TS U1509 ( .A(n1189), .B(n1194), .Y(n1183) );
NOR2X2TS U1510 ( .A(mult_x_23_n169), .B(mult_x_23_n165), .Y(n1184) );
NOR2X1TS U1511 ( .A(n1183), .B(n1184), .Y(n842) );
NAND2X1TS U1512 ( .A(mult_x_23_n182), .B(mult_x_23_n187), .Y(n1203) );
NAND2X1TS U1513 ( .A(mult_x_23_n181), .B(mult_x_23_n175), .Y(n1198) );
OAI21X2TS U1514 ( .A0(n1203), .A1(n1197), .B0(n1198), .Y(n1190) );
NAND2X1TS U1515 ( .A(mult_x_23_n174), .B(mult_x_23_n170), .Y(n1193) );
INVX2TS U1516 ( .A(n1193), .Y(n840) );
AOI21X1TS U1517 ( .A0(n1190), .A1(n1194), .B0(n840), .Y(n1182) );
NAND2X1TS U1518 ( .A(mult_x_23_n169), .B(mult_x_23_n165), .Y(n1185) );
NOR2X1TS U1519 ( .A(mult_x_23_n162), .B(mult_x_23_n164), .Y(n1176) );
NAND2X1TS U1520 ( .A(mult_x_23_n162), .B(mult_x_23_n164), .Y(n1177) );
OAI21X2TS U1521 ( .A0(n1180), .A1(n1176), .B0(n1177), .Y(n1175) );
NAND2X1TS U1522 ( .A(mult_x_23_n161), .B(n843), .Y(n1172) );
INVX2TS U1523 ( .A(n1172), .Y(n844) );
AOI21X4TS U1524 ( .A0(n1175), .A1(n1173), .B0(n844), .Y(n851) );
CMPR32X2TS U1525 ( .A(n573), .B(n416), .C(mult_x_23_n160), .CO(n847), .S(
n843) );
XNOR2X1TS U1526 ( .A(n845), .B(n1986), .Y(n846) );
NAND2X1TS U1527 ( .A(n847), .B(n846), .Y(n848) );
NAND2X1TS U1528 ( .A(n849), .B(n848), .Y(n850) );
INVX4TS U1529 ( .A(n852), .Y(n1377) );
INVX2TS U1530 ( .A(n1371), .Y(n853) );
NOR2X1TS U1531 ( .A(n853), .B(n1372), .Y(n856) );
INVX2TS U1532 ( .A(n1370), .Y(n854) );
OAI21X1TS U1533 ( .A0(n854), .A1(n1372), .B0(n1373), .Y(n855) );
INVX2TS U1534 ( .A(n857), .Y(n859) );
NAND2X1TS U1535 ( .A(n859), .B(n858), .Y(n860) );
INVX2TS U1536 ( .A(n862), .Y(n1379) );
INVX2TS U1537 ( .A(n1378), .Y(n863) );
INVX2TS U1538 ( .A(n864), .Y(n866) );
NAND2X1TS U1539 ( .A(n866), .B(n865), .Y(n867) );
NOR2X2TS U1540 ( .A(n438), .B(Op_MY[9]), .Y(n1450) );
NOR2X1TS U1541 ( .A(Op_MY[22]), .B(Op_MY[10]), .Y(n891) );
INVX2TS U1542 ( .A(n891), .Y(n885) );
AND2X4TS U1543 ( .A(n884), .B(n885), .Y(n894) );
NAND2X1TS U1544 ( .A(n438), .B(Op_MY[9]), .Y(n1451) );
OAI21X4TS U1545 ( .A0(n1450), .A1(n1447), .B0(n1451), .Y(n889) );
NAND2X1TS U1546 ( .A(n890), .B(DP_OP_111J22_123_4462_n727), .Y(n870) );
AOI21X4TS U1547 ( .A0(n895), .A1(n894), .B0(n593), .Y(n1587) );
INVX6TS U1548 ( .A(n1587), .Y(n1508) );
XNOR2X1TS U1549 ( .A(n1508), .B(n483), .Y(n1467) );
NOR2X1TS U1550 ( .A(n1283), .B(n876), .Y(n874) );
XOR2X1TS U1551 ( .A(n874), .B(n873), .Y(n882) );
NOR2X1TS U1552 ( .A(Op_MX[19]), .B(n436), .Y(n875) );
XNOR2X1TS U1553 ( .A(n876), .B(n875), .Y(n880) );
XNOR2X2TS U1554 ( .A(Op_MX[19]), .B(n436), .Y(n1428) );
OAI21X1TS U1555 ( .A0(Op_MX[6]), .A1(Op_MX[18]), .B0(n435), .Y(n878) );
NAND2X1TS U1556 ( .A(Op_MX[6]), .B(Op_MX[18]), .Y(n877) );
NAND2X2TS U1557 ( .A(n878), .B(n877), .Y(n1426) );
NAND2X1TS U1558 ( .A(n1428), .B(n1426), .Y(n879) );
INVX2TS U1559 ( .A(n483), .Y(n1550) );
OAI22X2TS U1560 ( .A0(n1467), .A1(n549), .B0(n426), .B1(n1550), .Y(
DP_OP_111J22_123_4462_n263) );
XNOR2X1TS U1561 ( .A(Op_MY[11]), .B(n443), .Y(n1065) );
XNOR2X1TS U1562 ( .A(n472), .B(n401), .Y(n1064) );
NOR2X4TS U1563 ( .A(DP_OP_111J22_123_4462_n266), .B(
DP_OP_111J22_123_4462_n262), .Y(n938) );
NAND2X2TS U1564 ( .A(n1571), .B(n901), .Y(n912) );
XNOR2X1TS U1565 ( .A(n1508), .B(n475), .Y(n1459) );
INVX2TS U1566 ( .A(n475), .Y(n1542) );
OAI22X1TS U1567 ( .A0(n1459), .A1(n464), .B0(n504), .B1(n1542), .Y(n1585) );
INVX2TS U1568 ( .A(n1585), .Y(n906) );
AOI21X1TS U1569 ( .A0(n895), .A1(n884), .B0(n889), .Y(n887) );
NAND2X1TS U1570 ( .A(n885), .B(n890), .Y(n886) );
CLKXOR2X4TS U1571 ( .A(n887), .B(n886), .Y(n1511) );
INVX2TS U1572 ( .A(n1511), .Y(n1455) );
INVX2TS U1573 ( .A(n889), .Y(n892) );
OAI21X1TS U1574 ( .A0(n892), .A1(n891), .B0(n890), .Y(n893) );
AOI21X2TS U1575 ( .A0(n895), .A1(n894), .B0(n893), .Y(n896) );
CLKXOR2X4TS U1576 ( .A(n896), .B(Op_MY[11]), .Y(n1509) );
INVX2TS U1577 ( .A(n1509), .Y(n907) );
OAI22X1TS U1578 ( .A0(n1455), .A1(n530), .B0(n907), .B1(n454), .Y(n905) );
NAND2X2TS U1579 ( .A(DP_OP_111J22_123_4462_n278), .B(
DP_OP_111J22_123_4462_n272), .Y(n926) );
NAND2X2TS U1580 ( .A(DP_OP_111J22_123_4462_n271), .B(
DP_OP_111J22_123_4462_n267), .Y(n919) );
NAND2X2TS U1581 ( .A(DP_OP_111J22_123_4462_n266), .B(
DP_OP_111J22_123_4462_n262), .Y(n937) );
NAND2X1TS U1582 ( .A(DP_OP_111J22_123_4462_n261), .B(
DP_OP_111J22_123_4462_n259), .Y(n943) );
INVX2TS U1583 ( .A(n1579), .Y(n900) );
AOI21X4TS U1584 ( .A0(n1582), .A1(n901), .B0(n900), .Y(n913) );
OAI21X2TS U1585 ( .A0(n913), .A1(n916), .B0(n1572), .Y(n903) );
AOI21X2TS U1586 ( .A0(n1583), .A1(n904), .B0(n903), .Y(n911) );
CMPR32X2TS U1587 ( .A(n906), .B(n905), .C(DP_OP_111J22_123_4462_n257), .CO(
n909), .S(n902) );
OAI22X1TS U1588 ( .A0(n907), .A1(n530), .B0(n454), .B1(n1587), .Y(n1584) );
NAND2X1TS U1589 ( .A(n909), .B(n908), .Y(n1573) );
NAND2X1TS U1590 ( .A(n1575), .B(n1573), .Y(n910) );
INVX2TS U1591 ( .A(n912), .Y(n915) );
INVX2TS U1592 ( .A(n913), .Y(n914) );
AOI21X2TS U1593 ( .A0(n1583), .A1(n915), .B0(n914), .Y(n918) );
INVX2TS U1594 ( .A(n916), .Y(n1569) );
NAND2X1TS U1595 ( .A(n1569), .B(n1572), .Y(n917) );
AOI21X2TS U1596 ( .A0(n1583), .A1(n1571), .B0(n1582), .Y(n921) );
XOR2X4TS U1597 ( .A(n921), .B(n920), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
INVX2TS U1598 ( .A(n922), .Y(n923) );
INVX2TS U1599 ( .A(n925), .Y(n927) );
INVX2TS U1600 ( .A(n936), .Y(n932) );
INVX2TS U1601 ( .A(n939), .Y(n931) );
AOI21X2TS U1602 ( .A0(n1583), .A1(n932), .B0(n931), .Y(n935) );
INVX2TS U1603 ( .A(n938), .Y(n933) );
XOR2X4TS U1604 ( .A(n935), .B(n934), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
AOI21X2TS U1605 ( .A0(n1583), .A1(n941), .B0(n940), .Y(n946) );
INVX2TS U1606 ( .A(n942), .Y(n944) );
XOR2X4TS U1607 ( .A(n946), .B(n945), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
NAND2X1TS U1608 ( .A(n948), .B(n947), .Y(n949) );
XNOR2X1TS U1609 ( .A(n950), .B(n949), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N22) );
INVX2TS U1610 ( .A(n951), .Y(n953) );
NAND2X1TS U1611 ( .A(n953), .B(n952), .Y(n954) );
INVX2TS U1612 ( .A(n959), .Y(n961) );
NAND2X1TS U1613 ( .A(n961), .B(n960), .Y(n962) );
XNOR2X1TS U1614 ( .A(n963), .B(n962), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N20) );
INVX2TS U1615 ( .A(n964), .Y(n967) );
INVX2TS U1616 ( .A(n965), .Y(n966) );
OAI21X1TS U1617 ( .A0(n981), .A1(n967), .B0(n966), .Y(n971) );
NAND2X1TS U1618 ( .A(n969), .B(n968), .Y(n970) );
XNOR2X1TS U1619 ( .A(n971), .B(n970), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N19) );
INVX2TS U1620 ( .A(n972), .Y(n974) );
NAND2X1TS U1621 ( .A(n974), .B(n973), .Y(n975) );
XNOR2X1TS U1622 ( .A(n976), .B(n975), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N18) );
INVX2TS U1623 ( .A(n977), .Y(n979) );
NAND2X1TS U1624 ( .A(n979), .B(n978), .Y(n980) );
AOI21X2TS U1625 ( .A0(n1005), .A1(n984), .B0(n983), .Y(n994) );
INVX2TS U1626 ( .A(n985), .Y(n987) );
NAND2X1TS U1627 ( .A(n987), .B(n986), .Y(n988) );
XNOR2X1TS U1628 ( .A(n989), .B(n988), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N16) );
INVX2TS U1629 ( .A(n990), .Y(n992) );
NAND2X1TS U1630 ( .A(n992), .B(n991), .Y(n993) );
INVX2TS U1631 ( .A(n995), .Y(n1003) );
INVX2TS U1632 ( .A(n1002), .Y(n996) );
AOI21X1TS U1633 ( .A0(n1005), .A1(n1003), .B0(n996), .Y(n1001) );
INVX2TS U1634 ( .A(n997), .Y(n999) );
NAND2X1TS U1635 ( .A(n999), .B(n998), .Y(n1000) );
NAND2X1TS U1636 ( .A(n1003), .B(n1002), .Y(n1004) );
XNOR2X1TS U1637 ( .A(n1005), .B(n1004), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N13) );
INVX2TS U1638 ( .A(n1006), .Y(n1110) );
INVX2TS U1639 ( .A(n1007), .Y(n1009) );
NAND2X1TS U1640 ( .A(n1009), .B(n1008), .Y(n1010) );
XNOR2X1TS U1641 ( .A(n1011), .B(n1010), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N12) );
INVX2TS U1642 ( .A(n1012), .Y(n1020) );
AOI21X1TS U1643 ( .A0(n1020), .A1(n580), .B0(n1013), .Y(n1017) );
NAND2X1TS U1644 ( .A(n1015), .B(n1014), .Y(n1016) );
NAND2X1TS U1645 ( .A(n580), .B(n1018), .Y(n1019) );
XNOR2X1TS U1646 ( .A(n1020), .B(n1019), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N9) );
INVX2TS U1647 ( .A(n1021), .Y(n1031) );
INVX2TS U1648 ( .A(n1022), .Y(n1024) );
NAND2X1TS U1649 ( .A(n1024), .B(n1023), .Y(n1025) );
XNOR2X1TS U1650 ( .A(n1026), .B(n1025), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N8) );
INVX2TS U1651 ( .A(n1027), .Y(n1029) );
NAND2X1TS U1652 ( .A(n1029), .B(n1028), .Y(n1030) );
INVX2TS U1653 ( .A(n1032), .Y(n1034) );
NAND2X1TS U1654 ( .A(n1034), .B(n1033), .Y(n1036) );
XOR2X1TS U1655 ( .A(n1036), .B(n1035), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N6) );
INVX2TS U1656 ( .A(n1037), .Y(n1047) );
INVX2TS U1657 ( .A(n1038), .Y(n1040) );
NAND2X1TS U1658 ( .A(n1040), .B(n1039), .Y(n1041) );
XNOR2X1TS U1659 ( .A(n1042), .B(n1041), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N5) );
INVX2TS U1660 ( .A(n1043), .Y(n1045) );
NAND2X1TS U1661 ( .A(n1045), .B(n1044), .Y(n1046) );
INVX2TS U1662 ( .A(n1048), .Y(n1050) );
NAND2X1TS U1663 ( .A(n1050), .B(n1049), .Y(n1052) );
NAND2X1TS U1664 ( .A(n1054), .B(n1053), .Y(n1056) );
XNOR2X1TS U1665 ( .A(n1056), .B(n1055), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N2) );
OAI22X1TS U1666 ( .A0(n456), .A1(DP_OP_111J22_123_4462_n727), .B0(n501),
.B1(n1057), .Y(mult_x_55_n273) );
XNOR2X1TS U1667 ( .A(n472), .B(n444), .Y(n1059) );
OAI22X1TS U1668 ( .A0(n457), .A1(n1059), .B0(n500), .B1(n1058), .Y(
mult_x_55_n288) );
XNOR2X1TS U1669 ( .A(n472), .B(n397), .Y(n1060) );
OAI22X1TS U1670 ( .A0(n457), .A1(n1060), .B0(n501), .B1(n1059), .Y(
mult_x_55_n289) );
XNOR2X1TS U1671 ( .A(n472), .B(Op_MX[8]), .Y(n1061) );
OAI22X1TS U1672 ( .A0(n457), .A1(n1061), .B0(n501), .B1(n1060), .Y(
mult_x_55_n290) );
XNOR2X1TS U1673 ( .A(n472), .B(n400), .Y(n1062) );
OAI22X1TS U1674 ( .A0(n457), .A1(n1062), .B0(n500), .B1(n1061), .Y(
mult_x_55_n291) );
BUFX3TS U1675 ( .A(Op_MX[6]), .Y(n2358) );
XNOR2X1TS U1676 ( .A(n472), .B(n2358), .Y(n1063) );
OAI22X1TS U1677 ( .A0(n457), .A1(n1063), .B0(n501), .B1(n1062), .Y(
mult_x_55_n292) );
OAI22X1TS U1678 ( .A0(n457), .A1(n1064), .B0(n500), .B1(n1063), .Y(
mult_x_55_n293) );
XNOR2X1TS U1679 ( .A(Op_MY[11]), .B(n434), .Y(n1066) );
OAI22X1TS U1680 ( .A0(n456), .A1(n1066), .B0(n501), .B1(n1065), .Y(
mult_x_55_n295) );
XNOR2X1TS U1681 ( .A(Op_MY[11]), .B(n433), .Y(n1067) );
OAI22X1TS U1682 ( .A0(n456), .A1(n1067), .B0(n501), .B1(n1066), .Y(
mult_x_55_n296) );
XNOR2X1TS U1683 ( .A(n472), .B(Op_MX[1]), .Y(n1068) );
OAI22X1TS U1684 ( .A0(n456), .A1(n1068), .B0(n500), .B1(n1067), .Y(
mult_x_55_n297) );
XNOR2X1TS U1685 ( .A(n472), .B(n550), .Y(n1069) );
OAI22X1TS U1686 ( .A0(n457), .A1(n1069), .B0(n500), .B1(n1068), .Y(
mult_x_55_n298) );
NOR2BX1TS U1687 ( .AN(n550), .B(n500), .Y(mult_x_55_n299) );
XNOR2X1TS U1688 ( .A(n468), .B(n554), .Y(n1166) );
OAI22X1TS U1689 ( .A0(n540), .A1(n1166), .B0(n494), .B1(n584), .Y(
mult_x_55_n301) );
XNOR2X1TS U1690 ( .A(n468), .B(Op_MX[8]), .Y(n1071) );
XNOR2X1TS U1691 ( .A(n468), .B(n397), .Y(n1131) );
OAI22X1TS U1692 ( .A0(n540), .A1(n1071), .B0(n493), .B1(n1131), .Y(
mult_x_55_n304) );
XNOR2X1TS U1693 ( .A(Op_MY[9]), .B(n400), .Y(n1072) );
OAI22X1TS U1694 ( .A0(n541), .A1(n1072), .B0(n494), .B1(n1071), .Y(
mult_x_55_n305) );
XNOR2X1TS U1695 ( .A(n468), .B(n2358), .Y(n1073) );
OAI22X1TS U1696 ( .A0(n541), .A1(n1073), .B0(n494), .B1(n1072), .Y(
mult_x_55_n306) );
XNOR2X1TS U1697 ( .A(n468), .B(n401), .Y(n1126) );
OAI22X1TS U1698 ( .A0(n540), .A1(n1126), .B0(n493), .B1(n1073), .Y(
mult_x_55_n307) );
XNOR2X1TS U1699 ( .A(Op_MY[9]), .B(Op_MX[1]), .Y(n1100) );
XNOR2X1TS U1700 ( .A(Op_MY[9]), .B(n433), .Y(n1160) );
OAI22X1TS U1701 ( .A0(n541), .A1(n1100), .B0(n493), .B1(n1160), .Y(
mult_x_55_n311) );
XOR2X1TS U1702 ( .A(Op_MY[6]), .B(n509), .Y(n1074) );
XNOR2X1TS U1703 ( .A(n510), .B(n444), .Y(n1075) );
XNOR2X1TS U1704 ( .A(n509), .B(n554), .Y(n1132) );
OAI22X1TS U1705 ( .A0(n1154), .A1(n1075), .B0(n511), .B1(n1132), .Y(
mult_x_55_n316) );
XNOR2X1TS U1706 ( .A(Op_MY[7]), .B(n397), .Y(n1118) );
OAI22X1TS U1707 ( .A0(n1154), .A1(n1118), .B0(n512), .B1(n1075), .Y(
mult_x_55_n317) );
XNOR2X1TS U1708 ( .A(n510), .B(n2358), .Y(n1076) );
XNOR2X1TS U1709 ( .A(n510), .B(n400), .Y(n1123) );
OAI22X1TS U1710 ( .A0(n1154), .A1(n1076), .B0(n513), .B1(n1123), .Y(
mult_x_55_n320) );
XNOR2X1TS U1711 ( .A(n510), .B(n401), .Y(n1077) );
OAI22X1TS U1712 ( .A0(n1154), .A1(n1077), .B0(n512), .B1(n1076), .Y(
mult_x_55_n321) );
XNOR2X1TS U1713 ( .A(n510), .B(n443), .Y(n1078) );
OAI22X1TS U1714 ( .A0(n1154), .A1(n1078), .B0(n513), .B1(n1077), .Y(
mult_x_55_n322) );
XNOR2X1TS U1715 ( .A(Op_MY[7]), .B(n434), .Y(n1111) );
OAI22X1TS U1716 ( .A0(n1154), .A1(n1111), .B0(n513), .B1(n1078), .Y(
mult_x_55_n323) );
XNOR2X1TS U1717 ( .A(n510), .B(n550), .Y(n1079) );
XNOR2X1TS U1718 ( .A(n510), .B(Op_MX[1]), .Y(n1137) );
OAI22X1TS U1719 ( .A0(n539), .A1(n1079), .B0(n513), .B1(n1137), .Y(
mult_x_55_n326) );
NOR2BX1TS U1720 ( .AN(n550), .B(n512), .Y(mult_x_55_n327) );
XNOR2X1TS U1721 ( .A(n450), .B(n554), .Y(n1080) );
OAI22X1TS U1722 ( .A0(n1148), .A1(n1080), .B0(n1146), .B1(n418), .Y(
mult_x_55_n329) );
XNOR2X1TS U1723 ( .A(Op_MY[5]), .B(n444), .Y(n1081) );
OAI22X1TS U1724 ( .A0(n1148), .A1(n1081), .B0(n1146), .B1(n1080), .Y(
mult_x_55_n330) );
XNOR2X1TS U1725 ( .A(Op_MY[5]), .B(n397), .Y(n1127) );
OAI22X1TS U1726 ( .A0(n1148), .A1(n1127), .B0(n1146), .B1(n1081), .Y(
mult_x_55_n331) );
XNOR2X1TS U1727 ( .A(n450), .B(n2358), .Y(n1082) );
XNOR2X1TS U1728 ( .A(Op_MY[5]), .B(n400), .Y(n1147) );
OAI22X1TS U1729 ( .A0(n1148), .A1(n1082), .B0(n470), .B1(n1147), .Y(
mult_x_55_n334) );
XNOR2X1TS U1730 ( .A(n450), .B(n401), .Y(n1113) );
OAI22X1TS U1731 ( .A0(n538), .A1(n1113), .B0(n470), .B1(n1082), .Y(
mult_x_55_n335) );
XNOR2X1TS U1732 ( .A(n450), .B(n434), .Y(n1083) );
XNOR2X1TS U1733 ( .A(n450), .B(n443), .Y(n1114) );
OAI22X1TS U1734 ( .A0(n538), .A1(n1083), .B0(n470), .B1(n1114), .Y(
mult_x_55_n337) );
XNOR2X1TS U1735 ( .A(n450), .B(n433), .Y(n1084) );
OAI22X1TS U1736 ( .A0(n538), .A1(n1084), .B0(n470), .B1(n1083), .Y(
mult_x_55_n338) );
OAI22X1TS U1737 ( .A0(n1148), .A1(n1085), .B0(n470), .B1(n1084), .Y(
mult_x_55_n339) );
XNOR2X1TS U1738 ( .A(n498), .B(n554), .Y(n1086) );
OAI22X1TS U1739 ( .A0(n1140), .A1(n1086), .B0(n428), .B1(n415), .Y(
mult_x_55_n343) );
XNOR2X1TS U1740 ( .A(n498), .B(n444), .Y(n1087) );
OAI22X1TS U1741 ( .A0(n1140), .A1(n1087), .B0(n429), .B1(n1086), .Y(
mult_x_55_n344) );
XNOR2X1TS U1742 ( .A(n498), .B(n397), .Y(n1088) );
OAI22X1TS U1743 ( .A0(n1140), .A1(n1088), .B0(n428), .B1(n1087), .Y(
mult_x_55_n345) );
XNOR2X1TS U1744 ( .A(n498), .B(Op_MX[8]), .Y(n1089) );
OAI22X1TS U1745 ( .A0(n537), .A1(n1089), .B0(n428), .B1(n1088), .Y(
mult_x_55_n346) );
XNOR2X1TS U1746 ( .A(n498), .B(n400), .Y(n1090) );
OAI22X1TS U1747 ( .A0(n1140), .A1(n1090), .B0(n429), .B1(n1089), .Y(
mult_x_55_n347) );
XNOR2X1TS U1748 ( .A(n498), .B(n2358), .Y(n1138) );
OAI22X1TS U1749 ( .A0(n537), .A1(n1138), .B0(n428), .B1(n1090), .Y(
mult_x_55_n348) );
XNOR2X1TS U1750 ( .A(n498), .B(n443), .Y(n1091) );
XNOR2X1TS U1751 ( .A(n498), .B(n401), .Y(n1139) );
OAI22X1TS U1752 ( .A0(n537), .A1(n1091), .B0(n429), .B1(n1139), .Y(
mult_x_55_n350) );
OAI22X1TS U1753 ( .A0(n537), .A1(n1092), .B0(n429), .B1(n1091), .Y(
mult_x_55_n351) );
XNOR2X1TS U1754 ( .A(n469), .B(n554), .Y(n1161) );
OAI22X1TS U1755 ( .A0(n1095), .A1(n1161), .B0(n566), .B1(n403), .Y(
mult_x_55_n357) );
XNOR2X1TS U1756 ( .A(n469), .B(n397), .Y(n1102) );
XNOR2X1TS U1757 ( .A(n469), .B(n444), .Y(n1162) );
OAI22X1TS U1758 ( .A0(n1163), .A1(n1102), .B0(n1162), .B1(n566), .Y(
mult_x_55_n359) );
XNOR2X1TS U1759 ( .A(n1093), .B(n400), .Y(n1155) );
XNOR2X1TS U1760 ( .A(n469), .B(Op_MX[8]), .Y(n1103) );
OAI22X1TS U1761 ( .A0(n1163), .A1(n1155), .B0(n1103), .B1(n566), .Y(
mult_x_55_n361) );
XNOR2X1TS U1762 ( .A(n1093), .B(n2358), .Y(n1156) );
OAI22X1TS U1763 ( .A0(n1095), .A1(n1094), .B0(n1156), .B1(n455), .Y(
mult_x_55_n363) );
XNOR2X1TS U1764 ( .A(n468), .B(n1152), .Y(n1101) );
OAI22X1TS U1765 ( .A0(n541), .A1(n1101), .B0(n494), .B1(n1100), .Y(n1105) );
OAI22X1TS U1766 ( .A0(n1163), .A1(n1103), .B0(n1102), .B1(n566), .Y(n1104)
);
ADDHX1TS U1767 ( .A(n1105), .B(n1104), .CO(mult_x_55_n250), .S(
mult_x_55_n251) );
NOR2X1TS U1768 ( .A(n471), .B(n586), .Y(mult_x_55_n282) );
INVX2TS U1769 ( .A(n1106), .Y(n1108) );
NAND2X1TS U1770 ( .A(n1108), .B(n1107), .Y(n1109) );
NOR2X1TS U1771 ( .A(DP_OP_111J22_123_4462_n727), .B(n579), .Y(mult_x_55_n280) );
INVX2TS U1772 ( .A(mult_x_55_n194), .Y(mult_x_55_n195) );
NOR2X1TS U1773 ( .A(DP_OP_111J22_123_4462_n727), .B(n575), .Y(mult_x_55_n168) );
INVX2TS U1774 ( .A(mult_x_55_n168), .Y(mult_x_55_n169) );
XNOR2X1TS U1775 ( .A(n510), .B(n433), .Y(n1136) );
OAI22X1TS U1776 ( .A0(n539), .A1(n1136), .B0(n513), .B1(n1111), .Y(n1117) );
OAI22X1TS U1777 ( .A0(n541), .A1(n584), .B0(n494), .B1(n1112), .Y(n1116) );
OAI22X1TS U1778 ( .A0(n538), .A1(n1114), .B0(n470), .B1(n1113), .Y(n1115) );
CMPR32X2TS U1779 ( .A(n1117), .B(n1116), .C(n1115), .CO(mult_x_55_n248), .S(
mult_x_55_n249) );
XNOR2X1TS U1780 ( .A(n510), .B(Op_MX[8]), .Y(n1122) );
OAI22X1TS U1781 ( .A0(n1154), .A1(n1122), .B0(n512), .B1(n1118), .Y(n1119)
);
CMPR32X2TS U1782 ( .A(n1121), .B(n1120), .C(n1119), .CO(mult_x_55_n202), .S(
mult_x_55_n203) );
NOR2X1TS U1783 ( .A(DP_OP_111J22_123_4462_n727), .B(n572), .Y(n1125) );
INVX2TS U1784 ( .A(n1121), .Y(n1130) );
OAI22X1TS U1785 ( .A0(n539), .A1(n1123), .B0(n512), .B1(n1122), .Y(n1124) );
CMPR32X2TS U1786 ( .A(n1125), .B(n1130), .C(n1124), .CO(mult_x_55_n210), .S(
mult_x_55_n211) );
XNOR2X1TS U1787 ( .A(n468), .B(n443), .Y(n1144) );
OAI22X1TS U1788 ( .A0(n540), .A1(n1144), .B0(n493), .B1(n1126), .Y(n1129) );
XNOR2X1TS U1789 ( .A(Op_MY[5]), .B(Op_MX[8]), .Y(n1145) );
OAI22X1TS U1790 ( .A0(n1148), .A1(n1145), .B0(n1146), .B1(n1127), .Y(n1128)
);
CMPR32X2TS U1791 ( .A(n1130), .B(n1129), .C(n1128), .CO(mult_x_55_n220), .S(
mult_x_55_n221) );
INVX2TS U1792 ( .A(n1171), .Y(n1135) );
XNOR2X1TS U1793 ( .A(n468), .B(n444), .Y(n1167) );
OAI22X1TS U1794 ( .A0(n541), .A1(n1131), .B0(n494), .B1(n1167), .Y(n1134) );
OAI22X1TS U1795 ( .A0(n539), .A1(n1132), .B0(n513), .B1(n413), .Y(n1133) );
CMPR32X2TS U1796 ( .A(n1135), .B(n1134), .C(n1133), .CO(mult_x_55_n178), .S(
mult_x_55_n179) );
NOR2BX1TS U1797 ( .AN(n550), .B(n494), .Y(n1143) );
OAI22X1TS U1798 ( .A0(n1154), .A1(n1137), .B0(n512), .B1(n1136), .Y(n1142)
);
OAI22X1TS U1799 ( .A0(n1140), .A1(n1139), .B0(n428), .B1(n1138), .Y(n1141)
);
CMPR32X2TS U1800 ( .A(n1143), .B(n1142), .C(n1141), .CO(mult_x_55_n255), .S(
mult_x_55_n256) );
NOR2BX1TS U1801 ( .AN(n1152), .B(n471), .Y(n1151) );
XNOR2X1TS U1802 ( .A(n468), .B(n434), .Y(n1159) );
OAI22X1TS U1803 ( .A0(n541), .A1(n1159), .B0(n494), .B1(n1144), .Y(n1150) );
OAI22X1TS U1804 ( .A0(n1148), .A1(n1147), .B0(n1146), .B1(n1145), .Y(n1149)
);
CMPR32X2TS U1805 ( .A(n1151), .B(n1150), .C(n1149), .CO(mult_x_55_n229), .S(
mult_x_55_n230) );
OAI22X1TS U1806 ( .A0(n1154), .A1(n413), .B0(n513), .B1(n1153), .Y(n1158) );
OAI22X1TS U1807 ( .A0(n1163), .A1(n1156), .B0(n1155), .B1(n566), .Y(n1157)
);
ADDHXLTS U1808 ( .A(n1158), .B(n1157), .CO(mult_x_55_n260), .S(
mult_x_55_n261) );
OAI22X1TS U1809 ( .A0(n541), .A1(n1160), .B0(n494), .B1(n1159), .Y(n1165) );
OAI22X1TS U1810 ( .A0(n1163), .A1(n1162), .B0(n1161), .B1(n566), .Y(n1164)
);
ADDHX1TS U1811 ( .A(n1165), .B(n1164), .CO(mult_x_55_n237), .S(
mult_x_55_n238) );
OAI22X1TS U1812 ( .A0(n541), .A1(n1167), .B0(n493), .B1(n1166), .Y(n1169) );
CMPR32X2TS U1813 ( .A(n1171), .B(n1170), .C(n1169), .CO(mult_x_55_n173), .S(
mult_x_55_n174) );
NAND2X1TS U1814 ( .A(n1173), .B(n1172), .Y(n1174) );
XNOR2X1TS U1815 ( .A(n1175), .B(n1174), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N22) );
INVX2TS U1816 ( .A(n1176), .Y(n1178) );
NAND2X1TS U1817 ( .A(n1178), .B(n1177), .Y(n1179) );
INVX2TS U1818 ( .A(n1184), .Y(n1186) );
NAND2X1TS U1819 ( .A(n1186), .B(n1185), .Y(n1187) );
XNOR2X1TS U1820 ( .A(n1188), .B(n1187), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N20) );
INVX2TS U1821 ( .A(n1189), .Y(n1192) );
NAND2X1TS U1822 ( .A(n1194), .B(n1193), .Y(n1195) );
XNOR2X1TS U1823 ( .A(n1196), .B(n1195), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N19) );
INVX2TS U1824 ( .A(n1197), .Y(n1199) );
NAND2X1TS U1825 ( .A(n1199), .B(n1198), .Y(n1200) );
XNOR2X1TS U1826 ( .A(n1201), .B(n1200), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N18) );
INVX2TS U1827 ( .A(n1202), .Y(n1204) );
NAND2X1TS U1828 ( .A(n1204), .B(n1203), .Y(n1205) );
INVX4TS U1829 ( .A(n1207), .Y(n1230) );
INVX2TS U1830 ( .A(n1210), .Y(n1212) );
NAND2X1TS U1831 ( .A(n1212), .B(n1211), .Y(n1213) );
XNOR2X1TS U1832 ( .A(n1214), .B(n1213), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N16) );
INVX2TS U1833 ( .A(n1215), .Y(n1217) );
NAND2X1TS U1834 ( .A(n1217), .B(n1216), .Y(n1218) );
INVX2TS U1835 ( .A(n1220), .Y(n1228) );
INVX2TS U1836 ( .A(n1227), .Y(n1221) );
AOI21X1TS U1837 ( .A0(n1230), .A1(n1228), .B0(n1221), .Y(n1226) );
INVX2TS U1838 ( .A(n1222), .Y(n1224) );
NAND2X1TS U1839 ( .A(n1224), .B(n1223), .Y(n1225) );
NAND2X1TS U1840 ( .A(n1228), .B(n1227), .Y(n1229) );
XNOR2X1TS U1841 ( .A(n1230), .B(n1229), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N13) );
INVX2TS U1842 ( .A(n1231), .Y(n1329) );
INVX2TS U1843 ( .A(n1232), .Y(n1234) );
NAND2X1TS U1844 ( .A(n1234), .B(n1233), .Y(n1235) );
XNOR2X1TS U1845 ( .A(n1236), .B(n1235), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N12) );
INVX2TS U1846 ( .A(n1237), .Y(n1244) );
AOI21X1TS U1847 ( .A0(n1244), .A1(n594), .B0(n1238), .Y(n1241) );
NAND2X1TS U1848 ( .A(n595), .B(n1239), .Y(n1240) );
NAND2X1TS U1849 ( .A(n594), .B(n1242), .Y(n1243) );
XNOR2X1TS U1850 ( .A(n1244), .B(n1243), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N9) );
INVX2TS U1851 ( .A(n1245), .Y(n1255) );
INVX2TS U1852 ( .A(n1246), .Y(n1248) );
NAND2X1TS U1853 ( .A(n1248), .B(n1247), .Y(n1249) );
XNOR2X1TS U1854 ( .A(n1250), .B(n1249), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N8) );
INVX2TS U1855 ( .A(n1251), .Y(n1253) );
NAND2X1TS U1856 ( .A(n1253), .B(n1252), .Y(n1254) );
INVX2TS U1857 ( .A(n1256), .Y(n1258) );
NAND2X1TS U1858 ( .A(n1258), .B(n1257), .Y(n1260) );
NAND2X1TS U1859 ( .A(n582), .B(n1261), .Y(n1262) );
XNOR2X1TS U1860 ( .A(n1263), .B(n1262), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N5) );
INVX2TS U1861 ( .A(n1264), .Y(n1266) );
NAND2X1TS U1862 ( .A(n1266), .B(n1265), .Y(n1268) );
XOR2X1TS U1863 ( .A(n1268), .B(n1267), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N4) );
NAND2X1TS U1864 ( .A(n570), .B(n1269), .Y(n1271) );
XNOR2X1TS U1865 ( .A(n1271), .B(n1270), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N3) );
INVX2TS U1866 ( .A(n1272), .Y(n1274) );
NAND2X1TS U1867 ( .A(n1274), .B(n1273), .Y(n1275) );
OAI22X1TS U1868 ( .A0(n449), .A1(n555), .B0(n481), .B1(n399), .Y(n1276) );
CMPR32X2TS U1869 ( .A(n1330), .B(Op_MY[19]), .C(n1276), .CO(mult_x_23_n171),
.S(mult_x_23_n172) );
OAI22X1TS U1870 ( .A0(n448), .A1(n398), .B0(n480), .B1(n442), .Y(n1277) );
CMPR32X2TS U1871 ( .A(n1356), .B(n440), .C(n1277), .CO(mult_x_23_n200), .S(
mult_x_23_n201) );
OAI22X1TS U1872 ( .A0(n449), .A1(Op_MY[14]), .B0(n481), .B1(n440), .Y(n1280)
);
XNOR2X1TS U1873 ( .A(n508), .B(n555), .Y(n1306) );
XNOR2X1TS U1874 ( .A(n507), .B(n399), .Y(n1305) );
OAI22X1TS U1875 ( .A0(n1345), .A1(n1306), .B0(n1305), .B1(n490), .Y(n1279)
);
CMPR32X2TS U1876 ( .A(n588), .B(n1280), .C(n1279), .CO(mult_x_23_n218), .S(
mult_x_23_n219) );
OAI22X1TS U1877 ( .A0(n449), .A1(n1356), .B0(n481), .B1(n529), .Y(n1282) );
OAI22X1TS U1878 ( .A0(n449), .A1(n438), .B0(n481), .B1(n1986), .Y(
mult_x_23_n281) );
OAI22X1TS U1879 ( .A0(n448), .A1(n1330), .B0(n480), .B1(Op_MY[19]), .Y(
mult_x_23_n284) );
OAI22X1TS U1880 ( .A0(n448), .A1(n442), .B0(n480), .B1(n1330), .Y(
mult_x_23_n285) );
NOR2BX1TS U1881 ( .AN(n1362), .B(n480), .Y(mult_x_23_n291) );
XOR2X1TS U1882 ( .A(n521), .B(Op_MX[20]), .Y(n1284) );
INVX2TS U1883 ( .A(n521), .Y(n1364) );
OAI22X1TS U1884 ( .A0(n536), .A1(n521), .B0(n495), .B1(n1364), .Y(
mult_x_23_n293) );
XNOR2X1TS U1885 ( .A(n520), .B(n1986), .Y(n1285) );
OAI22X1TS U1886 ( .A0(n536), .A1(n1285), .B0(n495), .B1(n520), .Y(
mult_x_23_n294) );
XNOR2X1TS U1887 ( .A(n520), .B(n399), .Y(n1286) );
OAI22X1TS U1888 ( .A0(n536), .A1(n1286), .B0(n1285), .B1(n495), .Y(
mult_x_23_n295) );
XNOR2X1TS U1889 ( .A(n520), .B(n555), .Y(n1287) );
OAI22X1TS U1890 ( .A0(n535), .A1(n1287), .B0(n1286), .B1(n495), .Y(
mult_x_23_n296) );
XNOR2X1TS U1891 ( .A(n521), .B(Op_MY[19]), .Y(n1288) );
OAI22X1TS U1892 ( .A0(n535), .A1(n1288), .B0(n1287), .B1(n496), .Y(
mult_x_23_n297) );
XNOR2X1TS U1893 ( .A(n521), .B(n1330), .Y(n1289) );
OAI22X1TS U1894 ( .A0(n536), .A1(n1289), .B0(n1288), .B1(n496), .Y(
mult_x_23_n298) );
XNOR2X1TS U1895 ( .A(n521), .B(n442), .Y(n1290) );
OAI22X1TS U1896 ( .A0(n536), .A1(n1290), .B0(n1289), .B1(n496), .Y(
mult_x_23_n299) );
XNOR2X1TS U1897 ( .A(n520), .B(n398), .Y(n1291) );
OAI22X1TS U1898 ( .A0(n535), .A1(n1291), .B0(n1290), .B1(n496), .Y(
mult_x_23_n300) );
XNOR2X1TS U1899 ( .A(n521), .B(n440), .Y(n1292) );
OAI22X1TS U1900 ( .A0(n536), .A1(n1292), .B0(n1291), .B1(n496), .Y(
mult_x_23_n301) );
XNOR2X1TS U1901 ( .A(n520), .B(Op_MY[14]), .Y(n1293) );
OAI22X1TS U1902 ( .A0(n536), .A1(n1293), .B0(n1292), .B1(n496), .Y(
mult_x_23_n302) );
XNOR2X1TS U1903 ( .A(n520), .B(n1356), .Y(n1341) );
OAI22X1TS U1904 ( .A0(n536), .A1(n1341), .B0(n1293), .B1(n496), .Y(
mult_x_23_n303) );
XOR2X1TS U1905 ( .A(Op_MX[19]), .B(Op_MX[18]), .Y(n1294) );
XNOR2X1TS U1906 ( .A(Op_MX[19]), .B(Op_MY[22]), .Y(n1295) );
OAI22X1TS U1907 ( .A0(n1353), .A1(n1295), .B0(n491), .B1(n514), .Y(
mult_x_23_n308) );
XNOR2X1TS U1908 ( .A(n514), .B(n438), .Y(n1296) );
OAI22X1TS U1909 ( .A0(n1353), .A1(n1296), .B0(n1295), .B1(n491), .Y(
mult_x_23_n309) );
XNOR2X1TS U1910 ( .A(Op_MX[19]), .B(Op_MY[20]), .Y(n1297) );
OAI22X1TS U1911 ( .A0(n1353), .A1(n1297), .B0(n1296), .B1(n492), .Y(
mult_x_23_n310) );
XNOR2X1TS U1912 ( .A(n514), .B(Op_MY[19]), .Y(n1298) );
OAI22X1TS U1913 ( .A0(n1353), .A1(n1298), .B0(n1297), .B1(n491), .Y(
mult_x_23_n311) );
XNOR2X1TS U1914 ( .A(n514), .B(n1330), .Y(n1299) );
OAI22X1TS U1915 ( .A0(n1353), .A1(n1299), .B0(n1298), .B1(n492), .Y(
mult_x_23_n312) );
XNOR2X1TS U1916 ( .A(n1351), .B(n442), .Y(n1300) );
OAI22X1TS U1917 ( .A0(n1353), .A1(n1300), .B0(n1299), .B1(n492), .Y(
mult_x_23_n313) );
XNOR2X1TS U1918 ( .A(n514), .B(n398), .Y(n1301) );
OAI22X1TS U1919 ( .A0(n534), .A1(n1301), .B0(n1300), .B1(n491), .Y(
mult_x_23_n314) );
XNOR2X1TS U1920 ( .A(n514), .B(n440), .Y(n1339) );
OAI22X1TS U1921 ( .A0(n1353), .A1(n1339), .B0(n1301), .B1(n492), .Y(
mult_x_23_n315) );
XNOR2X1TS U1922 ( .A(n1351), .B(n1356), .Y(n1302) );
XNOR2X1TS U1923 ( .A(n514), .B(Op_MY[14]), .Y(n1340) );
OAI22X1TS U1924 ( .A0(n534), .A1(n1302), .B0(n1340), .B1(n492), .Y(
mult_x_23_n317) );
XNOR2X1TS U1925 ( .A(n1351), .B(n552), .Y(n1303) );
OAI22X1TS U1926 ( .A0(n534), .A1(n1303), .B0(n1302), .B1(n491), .Y(
mult_x_23_n318) );
NOR2BX1TS U1927 ( .AN(n552), .B(n492), .Y(mult_x_23_n319) );
OAI22X1TS U1928 ( .A0(n1345), .A1(n508), .B0(n807), .B1(n419), .Y(
mult_x_23_n321) );
XNOR2X1TS U1929 ( .A(n507), .B(n1986), .Y(n1304) );
OAI22X1TS U1930 ( .A0(n1345), .A1(n1304), .B0(n490), .B1(n508), .Y(
mult_x_23_n322) );
OAI22X1TS U1931 ( .A0(n1345), .A1(n1305), .B0(n1304), .B1(n489), .Y(
mult_x_23_n323) );
XNOR2X1TS U1932 ( .A(n508), .B(Op_MY[19]), .Y(n1307) );
OAI22X1TS U1933 ( .A0(n533), .A1(n1307), .B0(n1306), .B1(n489), .Y(
mult_x_23_n325) );
XNOR2X1TS U1934 ( .A(n508), .B(n1330), .Y(n1308) );
OAI22X1TS U1935 ( .A0(n533), .A1(n1308), .B0(n1307), .B1(n489), .Y(
mult_x_23_n326) );
XNOR2X1TS U1936 ( .A(n507), .B(n442), .Y(n1343) );
OAI22X1TS U1937 ( .A0(n1345), .A1(n1343), .B0(n1308), .B1(n490), .Y(
mult_x_23_n327) );
XNOR2X1TS U1938 ( .A(n508), .B(n440), .Y(n1309) );
XNOR2X1TS U1939 ( .A(n507), .B(n398), .Y(n1344) );
OAI22X1TS U1940 ( .A0(n533), .A1(n1309), .B0(n1344), .B1(n489), .Y(
mult_x_23_n329) );
XNOR2X1TS U1941 ( .A(n508), .B(Op_MY[14]), .Y(n1310) );
OAI22X1TS U1942 ( .A0(n533), .A1(n1310), .B0(n1309), .B1(n490), .Y(
mult_x_23_n330) );
OAI22X1TS U1943 ( .A0(n533), .A1(n1311), .B0(n1310), .B1(n490), .Y(
mult_x_23_n331) );
OAI22X1TS U1944 ( .A0(n531), .A1(n506), .B0(n486), .B1(n421), .Y(
mult_x_23_n335) );
XNOR2X1TS U1945 ( .A(n505), .B(n1986), .Y(n1312) );
OAI22X1TS U1946 ( .A0(n531), .A1(n1312), .B0(n487), .B1(n506), .Y(
mult_x_23_n336) );
XNOR2X1TS U1947 ( .A(n506), .B(n399), .Y(n1313) );
OAI22X1TS U1948 ( .A0(n532), .A1(n1313), .B0(n1312), .B1(n486), .Y(
mult_x_23_n337) );
XNOR2X1TS U1949 ( .A(n505), .B(n555), .Y(n1314) );
OAI22X1TS U1950 ( .A0(n532), .A1(n1314), .B0(n1313), .B1(n487), .Y(
mult_x_23_n338) );
XNOR2X1TS U1951 ( .A(n505), .B(Op_MY[19]), .Y(n1315) );
OAI22X1TS U1952 ( .A0(n531), .A1(n1315), .B0(n1314), .B1(n487), .Y(
mult_x_23_n339) );
XNOR2X1TS U1953 ( .A(n505), .B(n1330), .Y(n1333) );
OAI22X1TS U1954 ( .A0(n532), .A1(n1333), .B0(n1315), .B1(n487), .Y(
mult_x_23_n340) );
XNOR2X1TS U1955 ( .A(n506), .B(n398), .Y(n1316) );
XNOR2X1TS U1956 ( .A(n505), .B(Op_MY[17]), .Y(n1334) );
OAI22X1TS U1957 ( .A0(n532), .A1(n1316), .B0(n1334), .B1(n486), .Y(
mult_x_23_n342) );
OAI22X1TS U1958 ( .A0(n532), .A1(n1317), .B0(n1316), .B1(n487), .Y(
mult_x_23_n343) );
XNOR2X1TS U1959 ( .A(n452), .B(n1986), .Y(n1318) );
OAI22X1TS U1960 ( .A0(n1361), .A1(n1318), .B0(n589), .B1(n452), .Y(
mult_x_23_n350) );
XNOR2X1TS U1961 ( .A(n452), .B(n438), .Y(n1359) );
OAI22X1TS U1962 ( .A0(n1361), .A1(n1359), .B0(n1318), .B1(n589), .Y(
mult_x_23_n351) );
XNOR2X1TS U1963 ( .A(n452), .B(n1330), .Y(n1350) );
OAI22X1TS U1964 ( .A0(n1320), .A1(n1319), .B0(n1350), .B1(n700), .Y(
mult_x_23_n355) );
NOR2BX1TS U1965 ( .AN(n552), .B(n700), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N0) );
INVX2TS U1966 ( .A(n1325), .Y(n1327) );
NAND2X1TS U1967 ( .A(n1327), .B(n1326), .Y(n1328) );
NOR2X1TS U1968 ( .A(n449), .B(n1986), .Y(mult_x_23_n280) );
OAI22X1TS U1969 ( .A0(n449), .A1(Op_MY[19]), .B0(n481), .B1(n555), .Y(n1332)
);
OAI22X1TS U1970 ( .A0(n534), .A1(n514), .B0(n491), .B1(n420), .Y(n1331) );
CMPR32X2TS U1971 ( .A(n574), .B(n1332), .C(n1331), .CO(mult_x_23_n176), .S(
mult_x_23_n177) );
NOR2BX1TS U1972 ( .AN(n1362), .B(n495), .Y(n1338) );
XNOR2X1TS U1973 ( .A(n451), .B(n439), .Y(n1349) );
XNOR2X1TS U1974 ( .A(n451), .B(Op_MY[20]), .Y(n1360) );
OAI22X1TS U1975 ( .A0(n1361), .A1(n1349), .B0(n1360), .B1(n589), .Y(n1337)
);
OAI22X1TS U1976 ( .A0(n531), .A1(n1334), .B0(n1333), .B1(n487), .Y(n1336) );
CMPR32X2TS U1977 ( .A(n1338), .B(n1337), .C(n1336), .CO(mult_x_23_n253), .S(
mult_x_23_n254) );
OAI22X1TS U1978 ( .A0(n1353), .A1(n1340), .B0(n1339), .B1(n492), .Y(n1348)
);
XNOR2X1TS U1979 ( .A(n520), .B(n1362), .Y(n1342) );
OAI22X1TS U1980 ( .A0(n535), .A1(n1342), .B0(n1341), .B1(n495), .Y(n1347) );
OAI22X1TS U1981 ( .A0(n1345), .A1(n1344), .B0(n1343), .B1(n490), .Y(n1346)
);
CMPR32X2TS U1982 ( .A(n1348), .B(n1347), .C(n1346), .CO(mult_x_23_n246), .S(
mult_x_23_n247) );
OAI22X1TS U1983 ( .A0(n1361), .A1(n1350), .B0(n1349), .B1(n589), .Y(n1355)
);
OAI22X1TS U1984 ( .A0(n1353), .A1(n420), .B0(n492), .B1(n1352), .Y(n1354) );
OAI21X1TS U1985 ( .A0(n481), .A1(n552), .B0(n448), .Y(n1358) );
OAI22X1TS U1986 ( .A0(n448), .A1(n552), .B0(n481), .B1(n1356), .Y(n1357) );
OAI22X1TS U1987 ( .A0(n1361), .A1(n1360), .B0(n1359), .B1(n700), .Y(n1367)
);
OAI22X1TS U1988 ( .A0(n535), .A1(n1364), .B0(n496), .B1(n1363), .Y(n1366) );
ADDHXLTS U1989 ( .A(n1369), .B(n1368), .CO(mult_x_23_n265), .S(n825) );
INVX2TS U1990 ( .A(n1372), .Y(n1374) );
NAND2X1TS U1991 ( .A(n1374), .B(n1373), .Y(n1375) );
NAND2X1TS U1992 ( .A(n1379), .B(n1378), .Y(n1380) );
XNOR2X1TS U1993 ( .A(n1377), .B(n1380), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
INVX2TS U1994 ( .A(n1381), .Y(n1540) );
NAND2X1TS U1995 ( .A(n1384), .B(n1383), .Y(n1385) );
XNOR2X1TS U1996 ( .A(n1386), .B(n1385), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
INVX2TS U1997 ( .A(n1387), .Y(n1395) );
AOI21X1TS U1998 ( .A0(n1395), .A1(n405), .B0(n1388), .Y(n1392) );
NAND2X1TS U1999 ( .A(n1390), .B(n1389), .Y(n1391) );
NAND2X1TS U2000 ( .A(n405), .B(n1393), .Y(n1394) );
XNOR2X1TS U2001 ( .A(n1395), .B(n1394), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
NAND2X1TS U2002 ( .A(n782), .B(n1396), .Y(n1397) );
XNOR2X1TS U2003 ( .A(n1398), .B(n1397), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
INVX2TS U2004 ( .A(n1399), .Y(n1405) );
AOI21X1TS U2005 ( .A0(n406), .A1(n1405), .B0(n1400), .Y(n1403) );
NAND2X1TS U2006 ( .A(n591), .B(n1401), .Y(n1402) );
NAND2X1TS U2007 ( .A(n1404), .B(n406), .Y(n1406) );
XNOR2X1TS U2008 ( .A(n1406), .B(n1405), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
NAND2X1TS U2009 ( .A(n597), .B(n1407), .Y(n1409) );
XNOR2X1TS U2010 ( .A(n1409), .B(n1408), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
INVX2TS U2011 ( .A(n1410), .Y(n1412) );
NAND2X1TS U2012 ( .A(n1412), .B(n1411), .Y(n1414) );
NAND2X1TS U2013 ( .A(n598), .B(n1415), .Y(n1417) );
XNOR2X1TS U2014 ( .A(n1417), .B(n1416), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
NAND2X1TS U2015 ( .A(n1420), .B(n1419), .Y(n1422) );
NAND2X1TS U2016 ( .A(n571), .B(n1423), .Y(n1425) );
XNOR2X1TS U2017 ( .A(n1425), .B(n1424), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
XNOR2X1TS U2018 ( .A(n1508), .B(n485), .Y(n1476) );
NOR2X1TS U2019 ( .A(n1427), .B(n1431), .Y(n1429) );
XOR2X1TS U2020 ( .A(n1429), .B(n1428), .Y(n1436) );
NOR2X1TS U2021 ( .A(Op_MX[17]), .B(n435), .Y(n1430) );
INVX2TS U2022 ( .A(n484), .Y(n1562) );
OAI22X1TS U2023 ( .A0(n1476), .A1(n547), .B0(n515), .B1(n1562), .Y(n1446) );
AOI21X1TS U2024 ( .A0(n1439), .A1(n1438), .B0(n1437), .Y(n1444) );
NAND2X1TS U2025 ( .A(n1442), .B(n1441), .Y(n1443) );
INVX2TS U2026 ( .A(n1519), .Y(n1457) );
INVX2TS U2027 ( .A(n1517), .Y(n1565) );
OAI22X1TS U2028 ( .A0(n1457), .A1(n530), .B0(n1565), .B1(n453), .Y(n1566) );
INVX2TS U2029 ( .A(n1566), .Y(n1445) );
CMPR32X2TS U2030 ( .A(n1446), .B(n1445), .C(DP_OP_111J22_123_4462_n280),
.CO(DP_OP_111J22_123_4462_n273), .S(DP_OP_111J22_123_4462_n274) );
INVX2TS U2031 ( .A(n1447), .Y(n1448) );
CLKINVX1TS U2032 ( .A(n1450), .Y(n1452) );
NAND2X1TS U2033 ( .A(n1452), .B(n1451), .Y(n1453) );
CLKXOR2X4TS U2034 ( .A(n1454), .B(n1453), .Y(n1513) );
INVX2TS U2035 ( .A(n1513), .Y(n1456) );
OAI22X1TS U2036 ( .A0(n1456), .A1(n530), .B0(n1455), .B1(n454), .Y(
DP_OP_111J22_123_4462_n384) );
INVX2TS U2037 ( .A(n1515), .Y(n1564) );
OAI22X1TS U2038 ( .A0(n1456), .A1(n454), .B0(n1564), .B1(n530), .Y(
DP_OP_111J22_123_4462_n385) );
INVX2TS U2039 ( .A(n1502), .Y(n1458) );
OAI22X1TS U2040 ( .A0(n1458), .A1(n530), .B0(n1457), .B1(n454), .Y(
DP_OP_111J22_123_4462_n387) );
INVX2TS U2041 ( .A(n1504), .Y(n1535) );
OAI22X1TS U2042 ( .A0(n1458), .A1(n454), .B0(n1535), .B1(n530), .Y(
DP_OP_111J22_123_4462_n388) );
XNOR2X1TS U2043 ( .A(n1509), .B(n474), .Y(n1460) );
OAI22X1TS U2044 ( .A0(n1460), .A1(n463), .B0(n1459), .B1(n504), .Y(
DP_OP_111J22_123_4462_n394) );
XNOR2X1TS U2045 ( .A(n1511), .B(n475), .Y(n1461) );
OAI22X1TS U2046 ( .A0(n1461), .A1(n463), .B0(n1460), .B1(n503), .Y(
DP_OP_111J22_123_4462_n395) );
XNOR2X1TS U2047 ( .A(n1513), .B(n474), .Y(n1463) );
OAI22X1TS U2048 ( .A0(n1463), .A1(n464), .B0(n1461), .B1(n504), .Y(
DP_OP_111J22_123_4462_n396) );
OAI22X1TS U2049 ( .A0(n1463), .A1(n503), .B0(n1462), .B1(n463), .Y(
DP_OP_111J22_123_4462_n397) );
XNOR2X1TS U2050 ( .A(n1519), .B(n474), .Y(n1465) );
OAI22X1TS U2051 ( .A0(n1465), .A1(n464), .B0(n1464), .B1(n504), .Y(
DP_OP_111J22_123_4462_n399) );
XNOR2X1TS U2052 ( .A(n1502), .B(n475), .Y(n1466) );
OAI22X1TS U2053 ( .A0(n1466), .A1(n464), .B0(n1465), .B1(n504), .Y(
DP_OP_111J22_123_4462_n400) );
OAI22X1TS U2054 ( .A0(n1466), .A1(n504), .B0(n1598), .B1(n463), .Y(
DP_OP_111J22_123_4462_n401) );
NOR2BX1TS U2055 ( .AN(n553), .B(n503), .Y(DP_OP_111J22_123_4462_n406) );
XNOR2X1TS U2056 ( .A(n1509), .B(n483), .Y(n1468) );
OAI22X1TS U2057 ( .A0(n1468), .A1(n549), .B0(n1467), .B1(n425), .Y(
DP_OP_111J22_123_4462_n408) );
XNOR2X1TS U2058 ( .A(n1511), .B(n483), .Y(n1469) );
OAI22X1TS U2059 ( .A0(n1469), .A1(n549), .B0(n1468), .B1(n426), .Y(
DP_OP_111J22_123_4462_n409) );
XNOR2X1TS U2060 ( .A(n1513), .B(n483), .Y(n1470) );
OAI22X1TS U2061 ( .A0(n1470), .A1(n549), .B0(n1469), .B1(n426), .Y(
DP_OP_111J22_123_4462_n410) );
XNOR2X1TS U2062 ( .A(n1515), .B(n483), .Y(n1471) );
OAI22X1TS U2063 ( .A0(n1470), .A1(n425), .B0(n1471), .B1(n549), .Y(
DP_OP_111J22_123_4462_n411) );
XNOR2X1TS U2064 ( .A(n1517), .B(n483), .Y(n1472) );
OAI22X1TS U2065 ( .A0(n1472), .A1(n548), .B0(n1471), .B1(n426), .Y(
DP_OP_111J22_123_4462_n412) );
XNOR2X1TS U2066 ( .A(n1519), .B(n483), .Y(n1473) );
OAI22X1TS U2067 ( .A0(n1473), .A1(n549), .B0(n1472), .B1(n425), .Y(
DP_OP_111J22_123_4462_n413) );
XNOR2X1TS U2068 ( .A(n1502), .B(n483), .Y(n1474) );
OAI22X1TS U2069 ( .A0(n1474), .A1(n549), .B0(n1473), .B1(n425), .Y(
DP_OP_111J22_123_4462_n414) );
XNOR2X1TS U2070 ( .A(n1504), .B(n872), .Y(n1613) );
OAI22X1TS U2071 ( .A0(n1474), .A1(n426), .B0(n1613), .B1(n549), .Y(
DP_OP_111J22_123_4462_n415) );
XNOR2X1TS U2072 ( .A(n1597), .B(n872), .Y(n1612) );
XNOR2X1TS U2073 ( .A(n1609), .B(n872), .Y(n1475) );
OAI22X1TS U2074 ( .A0(n1612), .A1(n425), .B0(n1475), .B1(n548), .Y(
DP_OP_111J22_123_4462_n417) );
XNOR2X1TS U2075 ( .A(n1543), .B(n872), .Y(n1547) );
OAI22X1TS U2076 ( .A0(n1475), .A1(n425), .B0(n548), .B1(n1547), .Y(
DP_OP_111J22_123_4462_n418) );
XNOR2X1TS U2077 ( .A(n1509), .B(n485), .Y(n1477) );
OAI22X1TS U2078 ( .A0(n1477), .A1(n547), .B0(n1476), .B1(n515), .Y(
DP_OP_111J22_123_4462_n423) );
XNOR2X1TS U2079 ( .A(n1511), .B(n485), .Y(n1478) );
OAI22X1TS U2080 ( .A0(n1478), .A1(n547), .B0(n1477), .B1(n516), .Y(
DP_OP_111J22_123_4462_n424) );
XNOR2X1TS U2081 ( .A(n1513), .B(n485), .Y(n1479) );
OAI22X1TS U2082 ( .A0(n1479), .A1(n547), .B0(n1478), .B1(n516), .Y(
DP_OP_111J22_123_4462_n425) );
XNOR2X1TS U2083 ( .A(n1515), .B(n485), .Y(n1480) );
OAI22X1TS U2084 ( .A0(n1479), .A1(n515), .B0(n1480), .B1(n547), .Y(
DP_OP_111J22_123_4462_n426) );
XNOR2X1TS U2085 ( .A(n1517), .B(n485), .Y(n1481) );
OAI22X1TS U2086 ( .A0(n1481), .A1(n547), .B0(n1480), .B1(n515), .Y(
DP_OP_111J22_123_4462_n427) );
XNOR2X1TS U2087 ( .A(n1519), .B(n485), .Y(n1482) );
OAI22X1TS U2088 ( .A0(n1482), .A1(n547), .B0(n1481), .B1(n516), .Y(
DP_OP_111J22_123_4462_n428) );
XNOR2X1TS U2089 ( .A(n1502), .B(n485), .Y(n1483) );
OAI22X1TS U2090 ( .A0(n1483), .A1(n547), .B0(n1482), .B1(n515), .Y(
DP_OP_111J22_123_4462_n429) );
XNOR2X1TS U2091 ( .A(n1504), .B(n484), .Y(n1484) );
OAI22X1TS U2092 ( .A0(n1483), .A1(n516), .B0(n1484), .B1(n547), .Y(
DP_OP_111J22_123_4462_n430) );
XNOR2X1TS U2093 ( .A(n1597), .B(n484), .Y(n1551) );
OAI22X1TS U2094 ( .A0(n1484), .A1(n516), .B0(n1551), .B1(n546), .Y(
DP_OP_111J22_123_4462_n431) );
NOR2BX1TS U2095 ( .AN(n553), .B(n516), .Y(DP_OP_111J22_123_4462_n435) );
XNOR2X1TS U2096 ( .A(n1508), .B(n479), .Y(n1486) );
OAI22X1TS U2097 ( .A0(n1486), .A1(n545), .B0(n519), .B1(n1485), .Y(
DP_OP_111J22_123_4462_n437) );
XNOR2X1TS U2098 ( .A(n1509), .B(n479), .Y(n1487) );
OAI22X1TS U2099 ( .A0(n1487), .A1(n545), .B0(n1486), .B1(n518), .Y(
DP_OP_111J22_123_4462_n438) );
XNOR2X1TS U2100 ( .A(n1511), .B(n479), .Y(n1488) );
OAI22X1TS U2101 ( .A0(n1488), .A1(n545), .B0(n1487), .B1(n519), .Y(
DP_OP_111J22_123_4462_n439) );
XNOR2X1TS U2102 ( .A(n1513), .B(n479), .Y(n1489) );
OAI22X1TS U2103 ( .A0(n1489), .A1(n545), .B0(n1488), .B1(n518), .Y(
DP_OP_111J22_123_4462_n440) );
XNOR2X1TS U2104 ( .A(n1515), .B(n479), .Y(n1490) );
OAI22X1TS U2105 ( .A0(n1489), .A1(n518), .B0(n1490), .B1(n545), .Y(
DP_OP_111J22_123_4462_n441) );
XNOR2X1TS U2106 ( .A(n1517), .B(n479), .Y(n1491) );
OAI22X1TS U2107 ( .A0(n1491), .A1(n545), .B0(n1490), .B1(n519), .Y(
DP_OP_111J22_123_4462_n442) );
XNOR2X1TS U2108 ( .A(n1519), .B(n479), .Y(n1492) );
OAI22X1TS U2109 ( .A0(n1492), .A1(n545), .B0(n1491), .B1(n519), .Y(
DP_OP_111J22_123_4462_n443) );
XNOR2X1TS U2110 ( .A(n1502), .B(n479), .Y(n1493) );
OAI22X1TS U2111 ( .A0(n1493), .A1(n545), .B0(n1492), .B1(n518), .Y(
DP_OP_111J22_123_4462_n444) );
XNOR2X1TS U2112 ( .A(n1504), .B(n478), .Y(n1558) );
OAI22X1TS U2113 ( .A0(n1493), .A1(n519), .B0(n1558), .B1(n545), .Y(
DP_OP_111J22_123_4462_n445) );
XNOR2X1TS U2114 ( .A(n1597), .B(n478), .Y(n1557) );
XNOR2X1TS U2115 ( .A(n1609), .B(n478), .Y(n1495) );
OAI22X1TS U2116 ( .A0(n1557), .A1(n519), .B0(n1495), .B1(n544), .Y(
DP_OP_111J22_123_4462_n447) );
OAI22X1TS U2117 ( .A0(n1495), .A1(n518), .B0(n544), .B1(n1494), .Y(
DP_OP_111J22_123_4462_n448) );
XNOR2X1TS U2118 ( .A(n1508), .B(n467), .Y(n1496) );
OAI22X1TS U2119 ( .A0(n1496), .A1(n543), .B0(n432), .B1(n465), .Y(
DP_OP_111J22_123_4462_n452) );
XNOR2X1TS U2120 ( .A(n1509), .B(n467), .Y(n1497) );
OAI22X1TS U2121 ( .A0(n1497), .A1(n543), .B0(n1496), .B1(n431), .Y(
DP_OP_111J22_123_4462_n453) );
XNOR2X1TS U2122 ( .A(n1511), .B(n467), .Y(n1498) );
OAI22X1TS U2123 ( .A0(n1498), .A1(n543), .B0(n1497), .B1(n432), .Y(
DP_OP_111J22_123_4462_n454) );
XNOR2X1TS U2124 ( .A(n1513), .B(n467), .Y(n1499) );
OAI22X1TS U2125 ( .A0(n1499), .A1(n543), .B0(n1498), .B1(n431), .Y(
DP_OP_111J22_123_4462_n455) );
XNOR2X1TS U2126 ( .A(n1515), .B(n467), .Y(n1500) );
OAI22X1TS U2127 ( .A0(n1499), .A1(n432), .B0(n1500), .B1(n543), .Y(
DP_OP_111J22_123_4462_n456) );
XNOR2X1TS U2128 ( .A(n1517), .B(n467), .Y(n1501) );
OAI22X1TS U2129 ( .A0(n1501), .A1(n543), .B0(n1500), .B1(n432), .Y(
DP_OP_111J22_123_4462_n457) );
XNOR2X1TS U2130 ( .A(n1519), .B(n467), .Y(n1503) );
OAI22X1TS U2131 ( .A0(n1503), .A1(n543), .B0(n1501), .B1(n431), .Y(
DP_OP_111J22_123_4462_n458) );
OAI22X1TS U2132 ( .A0(n1505), .A1(n543), .B0(n1503), .B1(n431), .Y(
DP_OP_111J22_123_4462_n459) );
XNOR2X1TS U2133 ( .A(n1504), .B(n466), .Y(n1507) );
OAI22X1TS U2134 ( .A0(n1505), .A1(n431), .B0(n1507), .B1(n542), .Y(
DP_OP_111J22_123_4462_n460) );
OAI22X1TS U2135 ( .A0(n1507), .A1(n431), .B0(n1506), .B1(n542), .Y(
DP_OP_111J22_123_4462_n461) );
XNOR2X1TS U2136 ( .A(n1508), .B(n461), .Y(n1510) );
OAI22X1TS U2137 ( .A0(n1510), .A1(n1523), .B0(n409), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n467) );
XNOR2X1TS U2138 ( .A(n1509), .B(n461), .Y(n1512) );
OAI22X1TS U2139 ( .A0(n1512), .A1(n1521), .B0(n1510), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n468) );
XNOR2X1TS U2140 ( .A(n1511), .B(n461), .Y(n1514) );
OAI22X1TS U2141 ( .A0(n1514), .A1(n1521), .B0(n1512), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n469) );
XNOR2X1TS U2142 ( .A(n1513), .B(n461), .Y(n1516) );
OAI22X1TS U2143 ( .A0(n1516), .A1(n1523), .B0(n1514), .B1(n476), .Y(
DP_OP_111J22_123_4462_n470) );
XNOR2X1TS U2144 ( .A(n1515), .B(n461), .Y(n1518) );
OAI22X1TS U2145 ( .A0(n1516), .A1(n1525), .B0(n1518), .B1(n1521), .Y(
DP_OP_111J22_123_4462_n471) );
XNOR2X1TS U2146 ( .A(n1517), .B(n461), .Y(n1520) );
OAI22X1TS U2147 ( .A0(n1520), .A1(n1523), .B0(n1518), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n472) );
XNOR2X1TS U2148 ( .A(n1519), .B(n461), .Y(n1522) );
OAI22X1TS U2149 ( .A0(n1522), .A1(n1521), .B0(n1520), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n473) );
OAI22X1TS U2150 ( .A0(n1524), .A1(n1523), .B0(n1522), .B1(n476), .Y(
DP_OP_111J22_123_4462_n474) );
NOR2BX1TS U2151 ( .AN(n553), .B(n1525), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
XNOR2X1TS U2152 ( .A(n484), .B(n1608), .Y(n1531) );
XNOR2X1TS U2153 ( .A(n1543), .B(n484), .Y(n1554) );
OAI22X1TS U2154 ( .A0(n546), .A1(n1531), .B0(n1554), .B1(n516), .Y(n1532) );
ADDHX1TS U2155 ( .A(n1533), .B(n1532), .CO(DP_OP_111J22_123_4462_n362), .S(
DP_OP_111J22_123_4462_n363) );
INVX2TS U2156 ( .A(DP_OP_111J22_123_4462_n263), .Y(
DP_OP_111J22_123_4462_n264) );
INVX2TS U2157 ( .A(n1609), .Y(n1599) );
INVX2TS U2158 ( .A(n1543), .Y(n1615) );
OAI22X2TS U2159 ( .A0(n1599), .A1(n453), .B0(n1615), .B1(n897), .Y(n1596) );
INVX2TS U2160 ( .A(n1597), .Y(n1600) );
OAI22X1TS U2161 ( .A0(n1535), .A1(n453), .B0(n1600), .B1(n897), .Y(n1594) );
INVX2TS U2162 ( .A(DP_OP_111J22_123_4462_n289), .Y(
DP_OP_111J22_123_4462_n290) );
INVX2TS U2163 ( .A(n1536), .Y(n1538) );
NAND2X1TS U2164 ( .A(n1538), .B(n1537), .Y(n1539) );
NAND2BX1TS U2165 ( .AN(n1608), .B(n474), .Y(n1541) );
OAI22X1TS U2166 ( .A0(n1616), .A1(n1542), .B0(n503), .B1(n1541), .Y(n1546)
);
XNOR2X1TS U2167 ( .A(n474), .B(n1608), .Y(n1544) );
XNOR2X1TS U2168 ( .A(n1543), .B(n473), .Y(n1610) );
OAI22X1TS U2169 ( .A0(n463), .A1(n1544), .B0(n1610), .B1(n503), .Y(n1545) );
ADDHX1TS U2170 ( .A(n1546), .B(n1545), .CO(DP_OP_111J22_123_4462_n339), .S(
DP_OP_111J22_123_4462_n340) );
XNOR2X1TS U2171 ( .A(n872), .B(n1608), .Y(n1548) );
OAI22X1TS U2172 ( .A0(n548), .A1(n1548), .B0(n1547), .B1(n426), .Y(n1553) );
OAI22X1TS U2173 ( .A0(n548), .A1(n1550), .B0(n425), .B1(n1549), .Y(n1552) );
XNOR2X1TS U2174 ( .A(n1609), .B(n484), .Y(n1555) );
OAI22X1TS U2175 ( .A0(n1551), .A1(n516), .B0(n1555), .B1(n546), .Y(n1561) );
ADDHX1TS U2176 ( .A(n1553), .B(n1552), .CO(DP_OP_111J22_123_4462_n352), .S(
n1560) );
NOR2BX1TS U2177 ( .AN(n553), .B(n425), .Y(n1607) );
OAI22X1TS U2178 ( .A0(n1555), .A1(n515), .B0(n546), .B1(n1554), .Y(n1606) );
OAI22X1TS U2179 ( .A0(n1558), .A1(n519), .B0(n1557), .B1(n544), .Y(n1605) );
OAI22X1TS U2180 ( .A0(n1565), .A1(n530), .B0(n1564), .B1(n454), .Y(n1567) );
NOR2X2TS U2181 ( .A(n1570), .B(n1578), .Y(n1581) );
INVX2TS U2182 ( .A(n1572), .Y(n1576) );
INVX2TS U2183 ( .A(n1573), .Y(n1574) );
AOI21X1TS U2184 ( .A0(n1576), .A1(n1575), .B0(n1574), .Y(n1577) );
AOI21X4TS U2185 ( .A0(n565), .A1(n1583), .B0(n564), .Y(n1593) );
CMPR32X2TS U2186 ( .A(n1586), .B(n1585), .C(n1584), .CO(n1589), .S(n908) );
NAND2X1TS U2187 ( .A(n1589), .B(n1588), .Y(n1590) );
NAND2X1TS U2188 ( .A(n1591), .B(n1590), .Y(n1592) );
XOR2X2TS U2189 ( .A(n1593), .B(n1592), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
INVX2TS U2190 ( .A(n1596), .Y(n1604) );
XNOR2X1TS U2191 ( .A(n1597), .B(n473), .Y(n1618) );
OAI22X2TS U2192 ( .A0(n1598), .A1(n504), .B0(n1618), .B1(n463), .Y(n1601) );
OAI22X1TS U2193 ( .A0(n1600), .A1(n454), .B0(n1599), .B1(n897), .Y(n1603) );
CMPR32X2TS U2194 ( .A(n1604), .B(n409), .C(n1601), .CO(n1602), .S(
DP_OP_111J22_123_4462_n315) );
CMPR32X2TS U2195 ( .A(n1607), .B(n1606), .C(n1605), .CO(n1559), .S(
DP_OP_111J22_123_4462_n358) );
NOR2BX1TS U2196 ( .AN(n553), .B(n453), .Y(n1621) );
XNOR2X1TS U2197 ( .A(n1609), .B(n473), .Y(n1617) );
OAI22X1TS U2198 ( .A0(n1617), .A1(n503), .B0(n1616), .B1(n1610), .Y(n1620)
);
OAI22X1TS U2199 ( .A0(n1613), .A1(n426), .B0(n1612), .B1(n548), .Y(n1619) );
OAI22X1TS U2200 ( .A0(n1615), .A1(n454), .B0(n530), .B1(n1614), .Y(n1624) );
OAI22X1TS U2201 ( .A0(n1618), .A1(n504), .B0(n1617), .B1(n464), .Y(n1623) );
CMPR32X2TS U2202 ( .A(n1624), .B(n1623), .C(n1622), .CO(
DP_OP_111J22_123_4462_n323), .S(DP_OP_111J22_123_4462_n324) );
NOR2X2TS U2203 ( .A(n562), .B(FS_Module_state_reg[2]), .Y(n1956) );
NAND2X2TS U2204 ( .A(n1956), .B(n2390), .Y(n1967) );
NOR4X1TS U2205 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n1632) );
NOR4X1TS U2206 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n1629) );
NOR3XLTS U2207 ( .A(P_Sgf[22]), .B(P_Sgf[2]), .C(P_Sgf[0]), .Y(n1628) );
AND4X1TS U2208 ( .A(n1629), .B(n1628), .C(n1627), .D(n424), .Y(n1630) );
XOR2X1TS U2209 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n1961) );
MXI2X1TS U2210 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1961), .Y(n1633)
);
OAI211X1TS U2211 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1634), .C0(
n1633), .Y(n1969) );
OAI31X1TS U2212 ( .A0(FS_Module_state_reg[1]), .A1(n1967), .A2(n1969), .B0(
n2391), .Y(n214) );
INVX2TS U2213 ( .A(Sgf_operation_Result[1]), .Y(n1638) );
XNOR2X1TS U2214 ( .A(n1638), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]),
.Y(n1637) );
INVX2TS U2215 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n1636) );
NOR2X2TS U2216 ( .A(n1637), .B(n1636), .Y(n1781) );
OR2X2TS U2217 ( .A(n2381), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]),
.Y(n1787) );
INVX2TS U2218 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n1788) );
NAND2X2TS U2219 ( .A(n2381), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]),
.Y(n1786) );
INVX2TS U2220 ( .A(n1786), .Y(n1635) );
AOI21X1TS U2221 ( .A0(n1787), .A1(n1788), .B0(n1635), .Y(n1784) );
NAND2X1TS U2222 ( .A(n1637), .B(n1636), .Y(n1782) );
OAI21X2TS U2223 ( .A0(n1781), .A1(n1784), .B0(n1782), .Y(n1791) );
INVX2TS U2224 ( .A(Sgf_operation_Result[2]), .Y(n1640) );
INVX2TS U2225 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n1639) );
NOR2X2TS U2226 ( .A(n1642), .B(n1641), .Y(n1801) );
INVX2TS U2227 ( .A(Sgf_operation_Result[3]), .Y(n1648) );
INVX2TS U2228 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n1647) );
CMPR32X2TS U2229 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .B(n1640),
.C(n1639), .CO(n1643), .S(n1642) );
NOR2X2TS U2230 ( .A(n1644), .B(n1643), .Y(n1803) );
NAND2X1TS U2231 ( .A(n1644), .B(n1643), .Y(n1804) );
OAI21X2TS U2232 ( .A0(n1803), .A1(n1800), .B0(n1804), .Y(n1645) );
AOI21X4TS U2233 ( .A0(n1791), .A1(n1646), .B0(n1645), .Y(n1769) );
INVX2TS U2234 ( .A(Sgf_operation_Result[4]), .Y(n1650) );
INVX2TS U2235 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n1649) );
CMPR32X2TS U2236 ( .A(n1648), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]),
.C(n1647), .CO(n1655), .S(n1644) );
INVX2TS U2237 ( .A(Sgf_operation_Result[5]), .Y(n1652) );
INVX2TS U2238 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n1651) );
CMPR32X2TS U2239 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .B(n1650),
.C(n1649), .CO(n1657), .S(n1656) );
NOR2X2TS U2240 ( .A(n1658), .B(n1657), .Y(n1776) );
NOR2X2TS U2241 ( .A(n1774), .B(n1776), .Y(n1771) );
INVX2TS U2242 ( .A(Sgf_operation_Result[6]), .Y(n1654) );
INVX2TS U2243 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n1653) );
CMPR32X2TS U2244 ( .A(n1652), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]),
.C(n1651), .CO(n1659), .S(n1658) );
NOR2X2TS U2245 ( .A(n1660), .B(n1659), .Y(n1821) );
INVX2TS U2246 ( .A(Sgf_operation_Result[7]), .Y(n1673) );
INVX2TS U2247 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n1672) );
CMPR32X2TS U2248 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .B(n1654),
.C(n1653), .CO(n1661), .S(n1660) );
NOR2X2TS U2249 ( .A(n1662), .B(n1661), .Y(n1823) );
NOR2X2TS U2250 ( .A(n1821), .B(n1823), .Y(n1664) );
NAND2X1TS U2251 ( .A(n1658), .B(n1657), .Y(n1777) );
OAI21X2TS U2252 ( .A0(n1776), .A1(n1796), .B0(n1777), .Y(n1770) );
NAND2X1TS U2253 ( .A(n1662), .B(n1661), .Y(n1824) );
OAI21X1TS U2254 ( .A0(n1823), .A1(n1820), .B0(n1824), .Y(n1663) );
OAI21X4TS U2255 ( .A0(n1769), .A1(n1666), .B0(n1665), .Y(n1710) );
INVX2TS U2256 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(n1668) );
INVX2TS U2257 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n1667) );
INVX2TS U2258 ( .A(Sgf_operation_Result[11]), .Y(n1679) );
INVX2TS U2259 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n1678) );
NOR2X2TS U2260 ( .A(n1693), .B(n1692), .Y(n1753) );
INVX2TS U2261 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n1670) );
INVX2TS U2262 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n1669) );
CMPR32X2TS U2263 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]), .B(n1668),
.C(n1667), .CO(n1694), .S(n1693) );
NOR2X2TS U2264 ( .A(n1695), .B(n1694), .Y(n1760) );
NOR2X2TS U2265 ( .A(n1753), .B(n1760), .Y(n1713) );
INVX2TS U2266 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n1671) );
CMPR32X2TS U2267 ( .A(n1670), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]),
.C(n1669), .CO(n1696), .S(n1695) );
INVX2TS U2268 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n2049) );
INVX2TS U2269 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n1706) );
CMPR32X2TS U2270 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]), .B(n2063),
.C(n1671), .CO(n1698), .S(n1697) );
INVX2TS U2271 ( .A(Sgf_operation_Result[8]), .Y(n1675) );
INVX2TS U2272 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n1674) );
CMPR32X2TS U2273 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .B(n1673),
.C(n1672), .CO(n1682), .S(n1662) );
NOR2X2TS U2274 ( .A(n1683), .B(n1682), .Y(n1829) );
INVX2TS U2275 ( .A(Sgf_operation_Result[9]), .Y(n1677) );
INVX2TS U2276 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n1676) );
NOR2X2TS U2277 ( .A(n1685), .B(n1684), .Y(n1831) );
INVX2TS U2278 ( .A(Sgf_operation_Result[10]), .Y(n1681) );
INVX2TS U2279 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n1680) );
CMPR32X2TS U2280 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .B(n1677),
.C(n1676), .CO(n1686), .S(n1685) );
CMPR32X2TS U2281 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]), .B(n1679),
.C(n1678), .CO(n1692), .S(n1689) );
NOR2X2TS U2282 ( .A(n1689), .B(n1688), .Y(n1748) );
NOR2X2TS U2283 ( .A(n1746), .B(n1748), .Y(n1691) );
NAND2X2TS U2284 ( .A(n1742), .B(n1691), .Y(n1712) );
NOR2X2TS U2285 ( .A(n1703), .B(n1712), .Y(n1705) );
NAND2X1TS U2286 ( .A(n1685), .B(n1684), .Y(n1832) );
OAI21X2TS U2287 ( .A0(n1831), .A1(n1828), .B0(n1832), .Y(n1743) );
NAND2X2TS U2288 ( .A(n1687), .B(n1686), .Y(n1836) );
NAND2X1TS U2289 ( .A(n1689), .B(n1688), .Y(n1749) );
OAI21X1TS U2290 ( .A0(n1748), .A1(n1836), .B0(n1749), .Y(n1690) );
AOI21X4TS U2291 ( .A0(n1743), .A1(n1691), .B0(n1690), .Y(n1711) );
NAND2X2TS U2292 ( .A(n1693), .B(n1692), .Y(n1756) );
NAND2X1TS U2293 ( .A(n1695), .B(n1694), .Y(n1761) );
NAND2X2TS U2294 ( .A(n1697), .B(n1696), .Y(n1765) );
NAND2X1TS U2295 ( .A(n1699), .B(n1698), .Y(n1720) );
OAI21X1TS U2296 ( .A0(n1719), .A1(n1765), .B0(n1720), .Y(n1700) );
AOI21X2TS U2297 ( .A0(n1714), .A1(n1701), .B0(n1700), .Y(n1702) );
AOI21X4TS U2298 ( .A0(n1710), .A1(n1705), .B0(n1704), .Y(n1737) );
INVX2TS U2299 ( .A(n1737), .Y(n1725) );
INVX2TS U2300 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(n2037) );
INVX2TS U2301 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n1726) );
CMPR32X2TS U2302 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]), .B(n2049),
.C(n1706), .CO(n1707), .S(n1699) );
NAND2X1TS U2303 ( .A(n1708), .B(n1707), .Y(n1724) );
NAND2X1TS U2304 ( .A(n1731), .B(n1724), .Y(n1709) );
XNOR2X1TS U2305 ( .A(n1725), .B(n1709), .Y(n1855) );
NOR2X2TS U2306 ( .A(n1855), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2192) );
INVX6TS U2307 ( .A(n1710), .Y(n1830) );
OAI21X4TS U2308 ( .A0(n1830), .A1(n1712), .B0(n1711), .Y(n1759) );
INVX2TS U2309 ( .A(n1713), .Y(n1716) );
OAI21X2TS U2310 ( .A0(n1755), .A1(n1716), .B0(n1715), .Y(n1768) );
INVX2TS U2311 ( .A(n1765), .Y(n1718) );
AOI21X2TS U2312 ( .A0(n1768), .A1(n1766), .B0(n1718), .Y(n1723) );
INVX2TS U2313 ( .A(n1719), .Y(n1721) );
NAND2X1TS U2314 ( .A(n1721), .B(n1720), .Y(n1722) );
CLKXOR2X2TS U2315 ( .A(n1723), .B(n1722), .Y(n1854) );
NOR2X2TS U2316 ( .A(n1854), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2189) );
INVX2TS U2317 ( .A(n1724), .Y(n1734) );
INVX2TS U2318 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(n2028) );
INVX2TS U2319 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n1738) );
CMPR32X2TS U2320 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]), .B(n2037),
.C(n1726), .CO(n1727), .S(n1708) );
NAND2X1TS U2321 ( .A(n1728), .B(n1727), .Y(n1732) );
NAND2X1TS U2322 ( .A(n583), .B(n1732), .Y(n1729) );
NAND2X1TS U2323 ( .A(n1731), .B(n583), .Y(n1736) );
INVX2TS U2324 ( .A(n1732), .Y(n1733) );
AOI21X1TS U2325 ( .A0(n583), .A1(n1734), .B0(n1733), .Y(n1735) );
OAI21X4TS U2326 ( .A0(n1737), .A1(n1736), .B0(n1735), .Y(n1867) );
INVX2TS U2327 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(n2020) );
INVX2TS U2328 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n1868) );
CMPR32X2TS U2329 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]), .B(n2028),
.C(n1738), .CO(n1739), .S(n1728) );
NAND2X1TS U2330 ( .A(n1740), .B(n1739), .Y(n1864) );
NAND2X1TS U2331 ( .A(n1866), .B(n1864), .Y(n1741) );
XNOR2X1TS U2332 ( .A(n1867), .B(n1741), .Y(n1857) );
NOR2X2TS U2333 ( .A(n1857), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2168) );
NAND2X2TS U2334 ( .A(n2162), .B(n1859), .Y(n1861) );
INVX2TS U2335 ( .A(n1742), .Y(n1745) );
INVX2TS U2336 ( .A(n1743), .Y(n1744) );
OAI21X2TS U2337 ( .A0(n1830), .A1(n1745), .B0(n1744), .Y(n1839) );
INVX2TS U2338 ( .A(n1746), .Y(n1837) );
INVX2TS U2339 ( .A(n1836), .Y(n1747) );
AOI21X1TS U2340 ( .A0(n1839), .A1(n1837), .B0(n1747), .Y(n1752) );
NAND2X1TS U2341 ( .A(n1750), .B(n1749), .Y(n1751) );
CLKXOR2X2TS U2342 ( .A(n1752), .B(n1751), .Y(n1848) );
NOR2X2TS U2343 ( .A(n1848), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]),
.Y(n2254) );
INVX2TS U2344 ( .A(n1753), .Y(n1758) );
NAND2X1TS U2345 ( .A(n1758), .B(n1756), .Y(n1754) );
XOR2X1TS U2346 ( .A(n1755), .B(n1754), .Y(n1849) );
NOR2X2TS U2347 ( .A(n1849), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2242) );
INVX2TS U2348 ( .A(n1756), .Y(n1757) );
AOI21X1TS U2349 ( .A0(n1759), .A1(n1758), .B0(n1757), .Y(n1764) );
NAND2X1TS U2350 ( .A(n1762), .B(n1761), .Y(n1763) );
XOR2X1TS U2351 ( .A(n1764), .B(n1763), .Y(n1850) );
NAND2X1TS U2352 ( .A(n1766), .B(n1765), .Y(n1767) );
XNOR2X1TS U2353 ( .A(n1768), .B(n1767), .Y(n1851) );
NOR2X2TS U2354 ( .A(n1851), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2220) );
NOR2X2TS U2355 ( .A(n2218), .B(n2220), .Y(n1853) );
NAND2X2TS U2356 ( .A(n2214), .B(n1853), .Y(n2161) );
NOR2X2TS U2357 ( .A(n1861), .B(n2161), .Y(n1863) );
AOI21X2TS U2358 ( .A0(n1799), .A1(n1771), .B0(n1770), .Y(n1822) );
NAND2X1TS U2359 ( .A(n1772), .B(n1820), .Y(n1773) );
XOR2X1TS U2360 ( .A(n1822), .B(n1773), .Y(n1815) );
NOR2X2TS U2361 ( .A(n1815), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.Y(n2300) );
INVX2TS U2362 ( .A(n1774), .Y(n1797) );
INVX2TS U2363 ( .A(n1796), .Y(n1775) );
AOI21X1TS U2364 ( .A0(n1799), .A1(n1797), .B0(n1775), .Y(n1780) );
NAND2X1TS U2365 ( .A(n1778), .B(n1777), .Y(n1779) );
XOR2X1TS U2366 ( .A(n1780), .B(n1779), .Y(n1814) );
NOR2X2TS U2367 ( .A(n1814), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.Y(n2298) );
NOR2X1TS U2368 ( .A(n2300), .B(n2298), .Y(n1817) );
NAND2X1TS U2369 ( .A(n1783), .B(n1782), .Y(n1785) );
XOR2X1TS U2370 ( .A(n1785), .B(n1784), .Y(n1790) );
NOR2X1TS U2371 ( .A(n1790), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.Y(n2269) );
NAND2X1TS U2372 ( .A(n1787), .B(n1786), .Y(n1789) );
XNOR2X1TS U2373 ( .A(n1789), .B(n1788), .Y(n2332) );
NAND2X1TS U2374 ( .A(n2332), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]),
.Y(n2333) );
NAND2X1TS U2375 ( .A(n1790), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.Y(n2270) );
OAI21X1TS U2376 ( .A0(n2269), .A1(n2333), .B0(n2270), .Y(n2329) );
INVX2TS U2377 ( .A(n1791), .Y(n1802) );
INVX2TS U2378 ( .A(n1801), .Y(n1792) );
NAND2X1TS U2379 ( .A(n1792), .B(n1800), .Y(n1793) );
XOR2X1TS U2380 ( .A(n1802), .B(n1793), .Y(n1794) );
NAND2X1TS U2381 ( .A(n1794), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]),
.Y(n2328) );
INVX2TS U2382 ( .A(n2328), .Y(n1795) );
AOI21X1TS U2383 ( .A0(n2329), .A1(n578), .B0(n1795), .Y(n2278) );
NAND2X1TS U2384 ( .A(n1797), .B(n1796), .Y(n1798) );
XNOR2X1TS U2385 ( .A(n1799), .B(n1798), .Y(n1810) );
OAI21X1TS U2386 ( .A0(n1802), .A1(n1801), .B0(n1800), .Y(n1807) );
NAND2X1TS U2387 ( .A(n1805), .B(n1804), .Y(n1806) );
XNOR2X1TS U2388 ( .A(n1807), .B(n1806), .Y(n1809) );
NAND2X1TS U2389 ( .A(n560), .B(n1808), .Y(n1813) );
NAND2X1TS U2390 ( .A(n1809), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]),
.Y(n2279) );
INVX2TS U2391 ( .A(n2279), .Y(n2282) );
NAND2X1TS U2392 ( .A(n1810), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]),
.Y(n2284) );
INVX2TS U2393 ( .A(n2284), .Y(n1811) );
AOI21X1TS U2394 ( .A0(n560), .A1(n2282), .B0(n1811), .Y(n1812) );
OAI21X1TS U2395 ( .A0(n2278), .A1(n1813), .B0(n1812), .Y(n2274) );
NAND2X1TS U2396 ( .A(n1814), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.Y(n2297) );
NAND2X1TS U2397 ( .A(n1815), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.Y(n2301) );
OAI21X1TS U2398 ( .A0(n2300), .A1(n2297), .B0(n2301), .Y(n1816) );
AOI21X2TS U2399 ( .A0(n1817), .A1(n2274), .B0(n1816), .Y(n2288) );
INVX2TS U2400 ( .A(n1829), .Y(n1818) );
NAND2X1TS U2401 ( .A(n1818), .B(n1828), .Y(n1819) );
XOR2X1TS U2402 ( .A(n1830), .B(n1819), .Y(n1841) );
NOR2X2TS U2403 ( .A(n1841), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.Y(n2291) );
OAI21X1TS U2404 ( .A0(n1822), .A1(n1821), .B0(n1820), .Y(n1827) );
NAND2X1TS U2405 ( .A(n1825), .B(n1824), .Y(n1826) );
XNOR2X1TS U2406 ( .A(n1827), .B(n1826), .Y(n1840) );
NOR2X2TS U2407 ( .A(n2291), .B(n2289), .Y(n2312) );
OAI21X1TS U2408 ( .A0(n1830), .A1(n1829), .B0(n1828), .Y(n1835) );
NAND2X1TS U2409 ( .A(n1833), .B(n1832), .Y(n1834) );
XNOR2X1TS U2410 ( .A(n1835), .B(n1834), .Y(n1842) );
NOR2X2TS U2411 ( .A(n1842), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]),
.Y(n2318) );
NAND2X1TS U2412 ( .A(n1837), .B(n1836), .Y(n1838) );
XNOR2X1TS U2413 ( .A(n1839), .B(n1838), .Y(n1843) );
NOR2X2TS U2414 ( .A(n1843), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]),
.Y(n2320) );
NAND2X2TS U2415 ( .A(n1840), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.Y(n2307) );
NAND2X1TS U2416 ( .A(n1841), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.Y(n2292) );
NAND2X1TS U2417 ( .A(n1842), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]),
.Y(n2317) );
NAND2X1TS U2418 ( .A(n1843), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]),
.Y(n2321) );
OAI21X1TS U2419 ( .A0(n2320), .A1(n2317), .B0(n2321), .Y(n1844) );
AOI21X1TS U2420 ( .A0(n2311), .A1(n1845), .B0(n1844), .Y(n1846) );
OAI21X4TS U2421 ( .A0(n2288), .A1(n1847), .B0(n1846), .Y(n2159) );
NAND2X2TS U2422 ( .A(n1848), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]),
.Y(n2255) );
NAND2X1TS U2423 ( .A(n1849), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]),
.Y(n2243) );
OAI21X1TS U2424 ( .A0(n2242), .A1(n2255), .B0(n2243), .Y(n2215) );
NAND2X1TS U2425 ( .A(n1850), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]),
.Y(n2232) );
NAND2X1TS U2426 ( .A(n1851), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]),
.Y(n2221) );
OAI21X1TS U2427 ( .A0(n2220), .A1(n2232), .B0(n2221), .Y(n1852) );
AOI21X2TS U2428 ( .A0(n2215), .A1(n1853), .B0(n1852), .Y(n2160) );
NAND2X4TS U2429 ( .A(n1854), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]),
.Y(n2203) );
NAND2X1TS U2430 ( .A(n1855), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]),
.Y(n2193) );
OAI21X1TS U2431 ( .A0(n2192), .A1(n2203), .B0(n2193), .Y(n2163) );
NAND2X1TS U2432 ( .A(n1856), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]),
.Y(n2179) );
NAND2X1TS U2433 ( .A(n1857), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]),
.Y(n2169) );
OAI21X1TS U2434 ( .A0(n2168), .A1(n2179), .B0(n2169), .Y(n1858) );
OAI21X2TS U2435 ( .A0(n1861), .A1(n2160), .B0(n1860), .Y(n1862) );
AOI21X4TS U2436 ( .A0(n1863), .A1(n2159), .B0(n1862), .Y(n2046) );
INVX2TS U2437 ( .A(n1864), .Y(n1865) );
AOI21X4TS U2438 ( .A0(n1867), .A1(n1866), .B0(n1865), .Y(n1875) );
INVX2TS U2439 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(n2012) );
INVX2TS U2440 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n1876) );
CMPR32X2TS U2441 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]), .B(n2020),
.C(n1868), .CO(n1869), .S(n1740) );
NOR2X1TS U2442 ( .A(n1870), .B(n1869), .Y(n1874) );
INVX2TS U2443 ( .A(n1874), .Y(n1871) );
NAND2X1TS U2444 ( .A(n1870), .B(n1869), .Y(n1873) );
NAND2X1TS U2445 ( .A(n1871), .B(n1873), .Y(n1872) );
XOR2X1TS U2446 ( .A(n1875), .B(n1872), .Y(n1916) );
OAI21X4TS U2447 ( .A0(n1875), .A1(n1874), .B0(n1873), .Y(n1883) );
INVX2TS U2448 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(n1939) );
INVX2TS U2449 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n1884) );
CMPR32X2TS U2450 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]), .B(n2012),
.C(n1876), .CO(n1877), .S(n1870) );
NAND2X1TS U2451 ( .A(n1878), .B(n1877), .Y(n1880) );
NAND2X1TS U2452 ( .A(n1882), .B(n1880), .Y(n1879) );
NOR2X2TS U2453 ( .A(n1917), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2136) );
INVX2TS U2454 ( .A(n1880), .Y(n1881) );
AOI21X4TS U2455 ( .A0(n1883), .A1(n1882), .B0(n1881), .Y(n1891) );
INVX2TS U2456 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(n1998) );
INVX2TS U2457 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n1892) );
CMPR32X2TS U2458 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]), .B(n1939),
.C(n1884), .CO(n1885), .S(n1878) );
NOR2X1TS U2459 ( .A(n1886), .B(n1885), .Y(n1890) );
INVX2TS U2460 ( .A(n1890), .Y(n1887) );
NAND2X1TS U2461 ( .A(n1886), .B(n1885), .Y(n1889) );
NAND2X1TS U2462 ( .A(n1887), .B(n1889), .Y(n1888) );
CLKXOR2X2TS U2463 ( .A(n1891), .B(n1888), .Y(n1918) );
NOR2X2TS U2464 ( .A(n1918), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2122) );
OAI21X4TS U2465 ( .A0(n1891), .A1(n1890), .B0(n1889), .Y(n1899) );
INVX2TS U2466 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(n1931) );
INVX2TS U2467 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n1900) );
CMPR32X2TS U2468 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]), .B(n1998),
.C(n1892), .CO(n1893), .S(n1886) );
NAND2X1TS U2469 ( .A(n1894), .B(n1893), .Y(n1896) );
NAND2X1TS U2470 ( .A(n1898), .B(n1896), .Y(n1895) );
NOR2X2TS U2471 ( .A(n1919), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]),
.Y(n2108) );
NOR2X2TS U2472 ( .A(n2122), .B(n2108), .Y(n1921) );
NAND2X2TS U2473 ( .A(n2107), .B(n1921), .Y(n2057) );
INVX2TS U2474 ( .A(n1896), .Y(n1897) );
AOI21X4TS U2475 ( .A0(n1899), .A1(n1898), .B0(n1897), .Y(n1907) );
INVX2TS U2476 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .Y(n1936) );
INVX2TS U2477 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n1908) );
CMPR32X2TS U2478 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]), .B(n1931),
.C(n1900), .CO(n1901), .S(n1894) );
NOR2X1TS U2479 ( .A(n1902), .B(n1901), .Y(n1906) );
INVX2TS U2480 ( .A(n1906), .Y(n1903) );
NAND2X1TS U2481 ( .A(n1903), .B(n1905), .Y(n1904) );
CLKXOR2X2TS U2482 ( .A(n1907), .B(n1904), .Y(n1922) );
NOR2X2TS U2483 ( .A(n1922), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]),
.Y(n2095) );
OAI21X4TS U2484 ( .A0(n1907), .A1(n1906), .B0(n1905), .Y(n1914) );
CMPR32X2TS U2485 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]), .B(n1936),
.C(n1908), .CO(n1909), .S(n1902) );
NAND2X1TS U2486 ( .A(n1913), .B(n1911), .Y(n1910) );
NOR2X4TS U2487 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .B(n1923),
.Y(n2083) );
NOR2X2TS U2488 ( .A(n2095), .B(n2083), .Y(n2062) );
INVX2TS U2489 ( .A(n1911), .Y(n1912) );
AOI21X2TS U2490 ( .A0(n1914), .A1(n1913), .B0(n1912), .Y(n1915) );
XOR2X4TS U2491 ( .A(n1915), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]),
.Y(n1924) );
NOR2X4TS U2492 ( .A(n1924), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]),
.Y(n2071) );
NAND2X1TS U2493 ( .A(n1917), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]),
.Y(n2137) );
OAI21X1TS U2494 ( .A0(n2136), .A1(n2147), .B0(n2137), .Y(n2106) );
NAND2X1TS U2495 ( .A(n1918), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]),
.Y(n2123) );
NAND2X1TS U2496 ( .A(n1919), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]),
.Y(n2109) );
OAI21X1TS U2497 ( .A0(n2108), .A1(n2123), .B0(n2109), .Y(n1920) );
AOI21X2TS U2498 ( .A0(n2106), .A1(n1921), .B0(n1920), .Y(n2058) );
NAND2X2TS U2499 ( .A(n1922), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]),
.Y(n2096) );
OAI21X2TS U2500 ( .A0(n2083), .A1(n2096), .B0(n2084), .Y(n2061) );
NAND2X2TS U2501 ( .A(n1924), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]),
.Y(n2072) );
NOR2X4TS U2502 ( .A(n2072), .B(n2063), .Y(n1925) );
AOI21X4TS U2503 ( .A0(n2061), .A1(n1926), .B0(n1925), .Y(n1927) );
OAI21X4TS U2504 ( .A0(n2058), .A1(n1928), .B0(n1927), .Y(n2047) );
OAI21X4TS U2505 ( .A0(n2046), .A1(n1930), .B0(n1929), .Y(n2038) );
NAND2X4TS U2506 ( .A(n2021), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]),
.Y(n2013) );
NOR2X8TS U2507 ( .A(n2013), .B(n2012), .Y(n1940) );
NAND2X8TS U2508 ( .A(n1940), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]),
.Y(n1999) );
XNOR2X4TS U2509 ( .A(n1935), .B(n1931), .Y(n1934) );
NAND2X2TS U2510 ( .A(n562), .B(n1932), .Y(n1953) );
CLKMX2X2TS U2511 ( .A(P_Sgf[46]), .B(n1934), .S0(n2337), .Y(n261) );
XOR2X4TS U2512 ( .A(n1937), .B(n1936), .Y(n1938) );
BUFX3TS U2513 ( .A(n2305), .Y(n2340) );
XNOR2X1TS U2514 ( .A(n1940), .B(n1939), .Y(n1941) );
INVX2TS U2515 ( .A(rst), .Y(n2424) );
BUFX3TS U2516 ( .A(n2424), .Y(n2404) );
BUFX3TS U2517 ( .A(n2424), .Y(n2402) );
BUFX3TS U2518 ( .A(n2424), .Y(n2401) );
NOR2XLTS U2519 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .Y(
n1942) );
BUFX3TS U2520 ( .A(n2416), .Y(n2420) );
CLKBUFX2TS U2521 ( .A(n1955), .Y(n1943) );
BUFX3TS U2522 ( .A(n2417), .Y(n2421) );
BUFX3TS U2523 ( .A(n2424), .Y(n2403) );
BUFX3TS U2524 ( .A(n2416), .Y(n2407) );
BUFX3TS U2525 ( .A(n1943), .Y(n2409) );
BUFX3TS U2526 ( .A(n1943), .Y(n2410) );
BUFX3TS U2527 ( .A(n2417), .Y(n2408) );
BUFX3TS U2528 ( .A(n2416), .Y(n2412) );
CLKBUFX2TS U2529 ( .A(n2417), .Y(n2422) );
BUFX3TS U2530 ( .A(n1943), .Y(n2414) );
BUFX3TS U2531 ( .A(n2417), .Y(n2415) );
BUFX3TS U2532 ( .A(n2424), .Y(n2405) );
BUFX3TS U2533 ( .A(n1955), .Y(n2406) );
NAND2X1TS U2534 ( .A(FS_Module_state_reg[2]), .B(n562), .Y(n2263) );
NAND2X1TS U2535 ( .A(n1967), .B(n2263), .Y(n1944) );
OAI21X2TS U2536 ( .A0(n1946), .A1(n1945), .B0(FS_Module_state_reg[1]), .Y(
n1994) );
BUFX3TS U2537 ( .A(n2128), .Y(n2114) );
AOI22X1TS U2538 ( .A0(n446), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n2114), .Y(n1950) );
OAI2BB1X1TS U2539 ( .A0N(n559), .A1N(P_Sgf[24]), .B0(n1950), .Y(n1951) );
AOI21X1TS U2540 ( .A0(n556), .A1(Add_result[0]), .B0(n1951), .Y(n1952) );
OAI2BB1X1TS U2541 ( .A0N(P_Sgf[23]), .A1N(n524), .B0(n1952), .Y(n191) );
BUFX3TS U2542 ( .A(n2375), .Y(n2371) );
INVX2TS U2543 ( .A(n2371), .Y(n2379) );
INVX2TS U2544 ( .A(n2372), .Y(n2376) );
AO22X1TS U2545 ( .A0(Sgf_normalized_result[22]), .A1(n2379), .B0(
final_result_ieee[22]), .B1(n2376), .Y(n167) );
AO22X1TS U2546 ( .A0(Sgf_normalized_result[20]), .A1(n2379), .B0(
final_result_ieee[20]), .B1(n2378), .Y(n170) );
BUFX3TS U2547 ( .A(n1955), .Y(n2417) );
BUFX3TS U2548 ( .A(n2422), .Y(n2419) );
BUFX3TS U2549 ( .A(n2422), .Y(n2418) );
BUFX3TS U2550 ( .A(n2422), .Y(n2411) );
BUFX3TS U2551 ( .A(n2422), .Y(n2413) );
BUFX3TS U2552 ( .A(n1955), .Y(n2416) );
INVX2TS U2553 ( .A(n2368), .Y(n2344) );
OAI31X1TS U2554 ( .A0(n2044), .A1(n2344), .A2(n2382), .B0(n1960), .Y(n308)
);
INVX2TS U2555 ( .A(n2044), .Y(n2240) );
NAND2X1TS U2556 ( .A(Add_result[0]), .B(n2240), .Y(n1959) );
OAI32X1TS U2557 ( .A0(n2378), .A1(n1962), .A2(overflow_flag), .B0(n2370),
.B1(n2399), .Y(n262) );
NAND2X1TS U2558 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1968) );
NOR3X1TS U2559 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1968), .Y(ready) );
INVX2TS U2560 ( .A(ready), .Y(n1963) );
AOI32X1TS U2561 ( .A0(FS_Module_state_reg[1]), .A1(n2383), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n2266), .Y(
n1964) );
INVX2TS U2562 ( .A(n527), .Y(n2339) );
AOI22X1TS U2563 ( .A0(n1970), .A1(n1969), .B0(n2265), .B1(n1968), .Y(n1971)
);
NOR3BX1TS U2564 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n1972) );
XOR2X1TS U2565 ( .A(n527), .B(n1972), .Y(DP_OP_36J22_124_9196_n15) );
OAI2BB1X1TS U2566 ( .A0N(Op_MY[29]), .A1N(n2382), .B0(n567), .Y(n1973) );
XOR2X1TS U2567 ( .A(n527), .B(n1973), .Y(DP_OP_36J22_124_9196_n16) );
OAI2BB1X1TS U2568 ( .A0N(Op_MY[28]), .A1N(n2382), .B0(n567), .Y(n1974) );
XOR2X1TS U2569 ( .A(n527), .B(n1974), .Y(DP_OP_36J22_124_9196_n17) );
OAI2BB1X1TS U2570 ( .A0N(Op_MY[27]), .A1N(n2382), .B0(n567), .Y(n1975) );
XOR2X1TS U2571 ( .A(n527), .B(n1975), .Y(DP_OP_36J22_124_9196_n18) );
OAI2BB1X1TS U2572 ( .A0N(Op_MY[26]), .A1N(n2382), .B0(n567), .Y(n1976) );
XOR2X1TS U2573 ( .A(n527), .B(n1976), .Y(DP_OP_36J22_124_9196_n19) );
OAI2BB1X1TS U2574 ( .A0N(Op_MY[25]), .A1N(n2382), .B0(n567), .Y(n1977) );
XOR2X1TS U2575 ( .A(n527), .B(n1977), .Y(DP_OP_36J22_124_9196_n20) );
OAI2BB1X1TS U2576 ( .A0N(Op_MY[24]), .A1N(n2382), .B0(n567), .Y(n1978) );
XOR2X1TS U2577 ( .A(n527), .B(n1978), .Y(DP_OP_36J22_124_9196_n21) );
XOR2X1TS U2578 ( .A(n1954), .B(n1980), .Y(DP_OP_36J22_124_9196_n22) );
INVX2TS U2579 ( .A(n1983), .Y(n1984) );
NAND2X1TS U2580 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n1988) );
NAND2X1TS U2581 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n2156) );
NOR2X1TS U2582 ( .A(n2384), .B(n2388), .Y(n2119) );
NAND2X1TS U2583 ( .A(n2119), .B(Sgf_normalized_result[10]), .Y(n1991) );
MXI2X1TS U2584 ( .A(P_Sgf[46]), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n1993) );
AOI21X1TS U2585 ( .A0(n1994), .A1(n1993), .B0(n2128), .Y(n1995) );
AHHCINX2TS U2586 ( .A(Sgf_normalized_result[22]), .CIN(n1996), .S(n1997),
.CO(n2260) );
INVX2TS U2587 ( .A(n2044), .Y(n2035) );
XOR2X1TS U2588 ( .A(n1999), .B(n1998), .Y(n2000) );
AOI22X1TS U2589 ( .A0(n447), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n2128), .Y(n2001) );
OAI2BB1X1TS U2590 ( .A0N(P_Sgf[46]), .A1N(n558), .B0(n2001), .Y(n2002) );
AOI21X1TS U2591 ( .A0(n2252), .A1(Add_result[22]), .B0(n2002), .Y(n2003) );
OAI2BB1X1TS U2592 ( .A0N(n522), .A1N(P_Sgf[45]), .B0(n2003), .Y(n213) );
AHHCONX2TS U2593 ( .A(Sgf_normalized_result[21]), .CI(n2004), .CON(n1996),
.S(n2005) );
AOI22X1TS U2594 ( .A0(n2006), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n2128), .Y(n2007) );
OAI2BB1X1TS U2595 ( .A0N(P_Sgf[45]), .A1N(n557), .B0(n2007), .Y(n2008) );
AOI21X1TS U2596 ( .A0(n556), .A1(Add_result[21]), .B0(n2008), .Y(n2009) );
OAI2BB1X1TS U2597 ( .A0N(n522), .A1N(P_Sgf[44]), .B0(n2009), .Y(n212) );
AHHCINX2TS U2598 ( .A(Sgf_normalized_result[20]), .CIN(n2010), .S(n2011),
.CO(n2004) );
XOR2X1TS U2599 ( .A(n2013), .B(n2012), .Y(n2014) );
AOI22X1TS U2600 ( .A0(n447), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n2128), .Y(n2015) );
OAI2BB1X1TS U2601 ( .A0N(n558), .A1N(P_Sgf[44]), .B0(n2015), .Y(n2016) );
AOI21X1TS U2602 ( .A0(n1948), .A1(Add_result[20]), .B0(n2016), .Y(n2017) );
OAI2BB1X1TS U2603 ( .A0N(n522), .A1N(P_Sgf[43]), .B0(n2017), .Y(n211) );
AHHCONX2TS U2604 ( .A(Sgf_normalized_result[19]), .CI(n2018), .CON(n2010),
.S(n2019) );
XNOR2X1TS U2605 ( .A(n2021), .B(n2020), .Y(n2022) );
AOI22X1TS U2606 ( .A0(n446), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n2114), .Y(n2023) );
OAI2BB1X1TS U2607 ( .A0N(n559), .A1N(P_Sgf[43]), .B0(n2023), .Y(n2024) );
AOI21X1TS U2608 ( .A0(n556), .A1(Add_result[19]), .B0(n2024), .Y(n2025) );
OAI2BB1X1TS U2609 ( .A0N(n522), .A1N(P_Sgf[42]), .B0(n2025), .Y(n210) );
AHHCINX2TS U2610 ( .A(Sgf_normalized_result[18]), .CIN(n2026), .S(n2027),
.CO(n2018) );
XOR2X1TS U2611 ( .A(n2029), .B(n2028), .Y(n2030) );
AOI22X1TS U2612 ( .A0(n447), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n2114), .Y(n2031) );
OAI2BB1X1TS U2613 ( .A0N(n559), .A1N(P_Sgf[42]), .B0(n2031), .Y(n2032) );
AOI21X1TS U2614 ( .A0(n1948), .A1(Add_result[18]), .B0(n2032), .Y(n2033) );
OAI2BB1X1TS U2615 ( .A0N(n522), .A1N(P_Sgf[41]), .B0(n2033), .Y(n209) );
AHHCONX2TS U2616 ( .A(Sgf_normalized_result[17]), .CI(n2034), .CON(n2026),
.S(n2036) );
XNOR2X1TS U2617 ( .A(n2038), .B(n2037), .Y(n2039) );
AOI22X1TS U2618 ( .A0(n2006), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n2114), .Y(n2040) );
OAI2BB1X1TS U2619 ( .A0N(n557), .A1N(P_Sgf[41]), .B0(n2040), .Y(n2041) );
AOI21X1TS U2620 ( .A0(n556), .A1(Add_result[17]), .B0(n2041), .Y(n2042) );
OAI2BB1X1TS U2621 ( .A0N(n522), .A1N(P_Sgf[40]), .B0(n2042), .Y(n208) );
AHHCINX2TS U2622 ( .A(Sgf_normalized_result[16]), .CIN(n2043), .S(n2045),
.CO(n2034) );
AOI21X1TS U2623 ( .A0(n2150), .A1(n2048), .B0(n2047), .Y(n2050) );
XOR2X1TS U2624 ( .A(n2050), .B(n2049), .Y(n2051) );
AOI22X1TS U2625 ( .A0(n446), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n2114), .Y(n2052) );
OAI2BB1X1TS U2626 ( .A0N(n557), .A1N(P_Sgf[40]), .B0(n2052), .Y(n2053) );
AOI21X1TS U2627 ( .A0(n556), .A1(Add_result[16]), .B0(n2053), .Y(n2054) );
OAI2BB1X1TS U2628 ( .A0N(n523), .A1N(P_Sgf[39]), .B0(n2054), .Y(n207) );
AHHCONX2TS U2629 ( .A(Sgf_normalized_result[15]), .CI(n2055), .CON(n2043),
.S(n2056) );
INVX2TS U2630 ( .A(n2057), .Y(n2060) );
INVX2TS U2631 ( .A(n2058), .Y(n2059) );
AOI21X4TS U2632 ( .A0(n2150), .A1(n2060), .B0(n2059), .Y(n2082) );
AOI21X2TS U2633 ( .A0(n2099), .A1(n2062), .B0(n2061), .Y(n2075) );
XNOR2X1TS U2634 ( .A(n2064), .B(n2063), .Y(n2065) );
CLKMX2X2TS U2635 ( .A(P_Sgf[38]), .B(n2065), .S0(n2088), .Y(n253) );
AOI22X1TS U2636 ( .A0(n2006), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n2114), .Y(n2066) );
OAI2BB1X1TS U2637 ( .A0N(n558), .A1N(P_Sgf[39]), .B0(n2066), .Y(n2067) );
AOI21X1TS U2638 ( .A0(n556), .A1(Add_result[15]), .B0(n2067), .Y(n2068) );
OAI2BB1X1TS U2639 ( .A0N(n524), .A1N(P_Sgf[38]), .B0(n2068), .Y(n206) );
AHHCINX2TS U2640 ( .A(Sgf_normalized_result[14]), .CIN(n2069), .S(n2070),
.CO(n2055) );
INVX2TS U2641 ( .A(n2071), .Y(n2073) );
NAND2X1TS U2642 ( .A(n2073), .B(n2072), .Y(n2074) );
XOR2X1TS U2643 ( .A(n2075), .B(n2074), .Y(n2076) );
AOI22X1TS U2644 ( .A0(n446), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n2114), .Y(n2077) );
OAI2BB1X1TS U2645 ( .A0N(n558), .A1N(P_Sgf[38]), .B0(n2077), .Y(n2078) );
AOI21X1TS U2646 ( .A0(n1948), .A1(Add_result[14]), .B0(n2078), .Y(n2079) );
OAI2BB1X1TS U2647 ( .A0N(n523), .A1N(P_Sgf[37]), .B0(n2079), .Y(n205) );
AHHCONX2TS U2648 ( .A(Sgf_normalized_result[13]), .CI(n2080), .CON(n2069),
.S(n2081) );
INVX2TS U2649 ( .A(n2083), .Y(n2085) );
NAND2X1TS U2650 ( .A(n2085), .B(n2084), .Y(n2086) );
XNOR2X1TS U2651 ( .A(n2087), .B(n2086), .Y(n2089) );
CLKMX2X2TS U2652 ( .A(P_Sgf[36]), .B(n2089), .S0(n2088), .Y(n251) );
AOI22X1TS U2653 ( .A0(n447), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n2114), .Y(n2090) );
OAI2BB1X1TS U2654 ( .A0N(n559), .A1N(P_Sgf[37]), .B0(n2090), .Y(n2091) );
AOI21X1TS U2655 ( .A0(n556), .A1(Add_result[13]), .B0(n2091), .Y(n2092) );
OAI2BB1X1TS U2656 ( .A0N(n524), .A1N(P_Sgf[36]), .B0(n2092), .Y(n204) );
AHHCINX2TS U2657 ( .A(Sgf_normalized_result[12]), .CIN(n2093), .S(n2094),
.CO(n2080) );
INVX2TS U2658 ( .A(n2095), .Y(n2097) );
NAND2X1TS U2659 ( .A(n2097), .B(n2096), .Y(n2098) );
XNOR2X1TS U2660 ( .A(n2099), .B(n2098), .Y(n2100) );
AOI22X1TS U2661 ( .A0(n447), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n2114), .Y(n2101) );
OAI2BB1X1TS U2662 ( .A0N(n559), .A1N(P_Sgf[36]), .B0(n2101), .Y(n2102) );
AOI21X1TS U2663 ( .A0(n556), .A1(Add_result[12]), .B0(n2102), .Y(n2103) );
OAI2BB1X1TS U2664 ( .A0N(n523), .A1N(P_Sgf[35]), .B0(n2103), .Y(n203) );
AHHCONX2TS U2665 ( .A(Sgf_normalized_result[11]), .CI(n2104), .CON(n2093),
.S(n2105) );
OAI21X1TS U2666 ( .A0(n2126), .A1(n2122), .B0(n2123), .Y(n2112) );
NAND2X1TS U2667 ( .A(n2110), .B(n2109), .Y(n2111) );
XNOR2X1TS U2668 ( .A(n2112), .B(n2111), .Y(n2113) );
CLKMX2X2TS U2669 ( .A(P_Sgf[34]), .B(n2113), .S0(n2225), .Y(n249) );
AOI22X1TS U2670 ( .A0(n2006), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n2114), .Y(n2115) );
OAI2BB1X1TS U2671 ( .A0N(n557), .A1N(P_Sgf[35]), .B0(n2115), .Y(n2116) );
AOI21X1TS U2672 ( .A0(n556), .A1(Add_result[11]), .B0(n2116), .Y(n2117) );
OAI2BB1X1TS U2673 ( .A0N(n524), .A1N(P_Sgf[34]), .B0(n2117), .Y(n202) );
NAND2X1TS U2674 ( .A(n2145), .B(n2119), .Y(n2120) );
XOR2X1TS U2675 ( .A(n2120), .B(n2396), .Y(n2121) );
INVX2TS U2676 ( .A(n2122), .Y(n2124) );
NAND2X1TS U2677 ( .A(n2124), .B(n2123), .Y(n2125) );
XOR2X1TS U2678 ( .A(n2126), .B(n2125), .Y(n2127) );
BUFX3TS U2679 ( .A(n2128), .Y(n2248) );
AOI22X1TS U2680 ( .A0(n446), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n2248), .Y(n2129) );
OAI2BB1X1TS U2681 ( .A0N(n557), .A1N(P_Sgf[34]), .B0(n2129), .Y(n2130) );
AOI21X1TS U2682 ( .A0(n2252), .A1(Add_result[10]), .B0(n2130), .Y(n2131) );
OAI2BB1X1TS U2683 ( .A0N(n523), .A1N(P_Sgf[33]), .B0(n2131), .Y(n201) );
NAND2X1TS U2684 ( .A(n2145), .B(Sgf_normalized_result[8]), .Y(n2132) );
XOR2X1TS U2685 ( .A(n2132), .B(n2388), .Y(n2133) );
INVX2TS U2686 ( .A(n2134), .Y(n2148) );
INVX2TS U2687 ( .A(n2147), .Y(n2135) );
AOI21X1TS U2688 ( .A0(n2150), .A1(n2148), .B0(n2135), .Y(n2140) );
NAND2X1TS U2689 ( .A(n2138), .B(n2137), .Y(n2139) );
XOR2X1TS U2690 ( .A(n2140), .B(n2139), .Y(n2141) );
AOI22X1TS U2691 ( .A0(n447), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n2248), .Y(n2142) );
OAI2BB1X1TS U2692 ( .A0N(n558), .A1N(P_Sgf[33]), .B0(n2142), .Y(n2143) );
AOI21X1TS U2693 ( .A0(n2252), .A1(Add_result[9]), .B0(n2143), .Y(n2144) );
OAI2BB1X1TS U2694 ( .A0N(n524), .A1N(P_Sgf[32]), .B0(n2144), .Y(n200) );
XNOR2X1TS U2695 ( .A(n2145), .B(n2384), .Y(n2146) );
NAND2X1TS U2696 ( .A(n2148), .B(n2147), .Y(n2149) );
XNOR2X1TS U2697 ( .A(n2150), .B(n2149), .Y(n2151) );
AOI22X1TS U2698 ( .A0(n447), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n2248), .Y(n2152) );
OAI2BB1X1TS U2699 ( .A0N(n559), .A1N(P_Sgf[32]), .B0(n2152), .Y(n2153) );
AOI21X1TS U2700 ( .A0(n2252), .A1(Add_result[8]), .B0(n2153), .Y(n2154) );
OAI2BB1X1TS U2701 ( .A0N(n523), .A1N(P_Sgf[31]), .B0(n2154), .Y(n199) );
OAI21X1TS U2702 ( .A0(n2201), .A1(n2389), .B0(n2156), .Y(n2177) );
NAND2X1TS U2703 ( .A(n2177), .B(Sgf_normalized_result[6]), .Y(n2157) );
XOR2X1TS U2704 ( .A(n2157), .B(n2397), .Y(n2158) );
OAI21X2TS U2705 ( .A0(n2258), .A1(n2161), .B0(n2160), .Y(n2191) );
INVX2TS U2706 ( .A(n2191), .Y(n2206) );
INVX2TS U2707 ( .A(n2162), .Y(n2165) );
INVX2TS U2708 ( .A(n2163), .Y(n2164) );
OAI21X2TS U2709 ( .A0(n2206), .A1(n2165), .B0(n2164), .Y(n2182) );
INVX2TS U2710 ( .A(n2166), .Y(n2180) );
INVX2TS U2711 ( .A(n2179), .Y(n2167) );
AOI21X1TS U2712 ( .A0(n2182), .A1(n2180), .B0(n2167), .Y(n2172) );
INVX2TS U2713 ( .A(n2168), .Y(n2170) );
NAND2X1TS U2714 ( .A(n2170), .B(n2169), .Y(n2171) );
XOR2X1TS U2715 ( .A(n2172), .B(n2171), .Y(n2173) );
AOI22X1TS U2716 ( .A0(n2006), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n2248), .Y(n2174) );
OAI2BB1X1TS U2717 ( .A0N(n557), .A1N(P_Sgf[31]), .B0(n2174), .Y(n2175) );
AOI21X1TS U2718 ( .A0(n2252), .A1(Add_result[7]), .B0(n2175), .Y(n2176) );
OAI2BB1X1TS U2719 ( .A0N(n524), .A1N(P_Sgf[30]), .B0(n2176), .Y(n198) );
XNOR2X1TS U2720 ( .A(n2177), .B(n2393), .Y(n2178) );
NAND2X1TS U2721 ( .A(n2180), .B(n2179), .Y(n2181) );
XNOR2X1TS U2722 ( .A(n2182), .B(n2181), .Y(n2183) );
AOI22X1TS U2723 ( .A0(n446), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n2248), .Y(n2184) );
OAI2BB1X1TS U2724 ( .A0N(n558), .A1N(P_Sgf[30]), .B0(n2184), .Y(n2185) );
AOI21X1TS U2725 ( .A0(n2252), .A1(Add_result[6]), .B0(n2185), .Y(n2186) );
OAI2BB1X1TS U2726 ( .A0N(n523), .A1N(P_Sgf[29]), .B0(n2186), .Y(n197) );
NAND2X1TS U2727 ( .A(n2201), .B(n2392), .Y(n2187) );
XNOR2X1TS U2728 ( .A(n2187), .B(n2389), .Y(n2188) );
INVX2TS U2729 ( .A(n2189), .Y(n2204) );
INVX2TS U2730 ( .A(n2203), .Y(n2190) );
AOI21X1TS U2731 ( .A0(n2191), .A1(n2204), .B0(n2190), .Y(n2196) );
INVX2TS U2732 ( .A(n2192), .Y(n2194) );
NAND2X1TS U2733 ( .A(n2194), .B(n2193), .Y(n2195) );
XOR2X1TS U2734 ( .A(n2196), .B(n2195), .Y(n2197) );
AOI22X1TS U2735 ( .A0(n446), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n2248), .Y(n2198) );
OAI2BB1X1TS U2736 ( .A0N(n559), .A1N(P_Sgf[29]), .B0(n2198), .Y(n2199) );
AOI21X1TS U2737 ( .A0(n2252), .A1(Add_result[5]), .B0(n2199), .Y(n2200) );
OAI2BB1X1TS U2738 ( .A0N(n524), .A1N(P_Sgf[28]), .B0(n2200), .Y(n196) );
XOR2X1TS U2739 ( .A(n2201), .B(Sgf_normalized_result[4]), .Y(n2202) );
NAND2X1TS U2740 ( .A(n2204), .B(n2203), .Y(n2205) );
XOR2X1TS U2741 ( .A(n2206), .B(n2205), .Y(n2207) );
AOI22X1TS U2742 ( .A0(n447), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n2248), .Y(n2208) );
OAI2BB1X1TS U2743 ( .A0N(n557), .A1N(P_Sgf[28]), .B0(n2208), .Y(n2209) );
AOI21X1TS U2744 ( .A0(n2252), .A1(Add_result[4]), .B0(n2209), .Y(n2210) );
OAI2BB1X1TS U2745 ( .A0N(n523), .A1N(P_Sgf[27]), .B0(n2210), .Y(n195) );
XOR2X1TS U2746 ( .A(n2212), .B(n2387), .Y(n2213) );
INVX2TS U2747 ( .A(n2214), .Y(n2217) );
INVX2TS U2748 ( .A(n2215), .Y(n2216) );
OAI21X1TS U2749 ( .A0(n2258), .A1(n2217), .B0(n2216), .Y(n2235) );
INVX2TS U2750 ( .A(n2218), .Y(n2233) );
INVX2TS U2751 ( .A(n2232), .Y(n2219) );
AOI21X1TS U2752 ( .A0(n2235), .A1(n2233), .B0(n2219), .Y(n2224) );
NAND2X1TS U2753 ( .A(n2222), .B(n2221), .Y(n2223) );
XOR2X1TS U2754 ( .A(n2224), .B(n2223), .Y(n2226) );
AOI22X1TS U2755 ( .A0(n446), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n2248), .Y(n2227) );
OAI2BB1X1TS U2756 ( .A0N(n558), .A1N(P_Sgf[27]), .B0(n2227), .Y(n2228) );
AOI21X1TS U2757 ( .A0(n2252), .A1(Add_result[3]), .B0(n2228), .Y(n2229) );
OAI2BB1X1TS U2758 ( .A0N(n524), .A1N(P_Sgf[26]), .B0(n2229), .Y(n194) );
XOR2X1TS U2759 ( .A(n2230), .B(Sgf_normalized_result[2]), .Y(n2231) );
NAND2X1TS U2760 ( .A(n2233), .B(n2232), .Y(n2234) );
XNOR2X1TS U2761 ( .A(n2235), .B(n2234), .Y(n2236) );
AOI22X1TS U2762 ( .A0(n446), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n2248), .Y(n2237) );
OAI2BB1X1TS U2763 ( .A0N(n557), .A1N(P_Sgf[26]), .B0(n2237), .Y(n2238) );
AOI21X1TS U2764 ( .A0(n2252), .A1(Add_result[2]), .B0(n2238), .Y(n2239) );
OAI2BB1X1TS U2765 ( .A0N(n522), .A1N(P_Sgf[25]), .B0(n2239), .Y(n193) );
XNOR2X1TS U2766 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n2241) );
INVX2TS U2767 ( .A(n2242), .Y(n2244) );
NAND2X1TS U2768 ( .A(n2244), .B(n2243), .Y(n2245) );
XNOR2X1TS U2769 ( .A(n2246), .B(n2245), .Y(n2247) );
AOI22X1TS U2770 ( .A0(n2006), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n2248), .Y(n2249) );
OAI2BB1X1TS U2771 ( .A0N(n558), .A1N(P_Sgf[25]), .B0(n2249), .Y(n2251) );
AOI21X1TS U2772 ( .A0(n556), .A1(Add_result[1]), .B0(n2251), .Y(n2253) );
OAI2BB1X1TS U2773 ( .A0N(n523), .A1N(P_Sgf[24]), .B0(n2253), .Y(n192) );
INVX2TS U2774 ( .A(n2254), .Y(n2256) );
NAND2X1TS U2775 ( .A(n2256), .B(n2255), .Y(n2257) );
XOR2X1TS U2776 ( .A(n2258), .B(n2257), .Y(n2259) );
ADDHXLTS U2777 ( .A(Sgf_normalized_result[23]), .B(n2260), .CO(n2262), .S(
n1992) );
AOI22X1TS U2778 ( .A0(n2265), .A1(n2264), .B0(n2390), .B1(n2383), .Y(n2268)
);
AOI21X1TS U2779 ( .A0(n2268), .A1(n2267), .B0(n2266), .Y(n378) );
INVX2TS U2780 ( .A(n2269), .Y(n2271) );
NAND2X1TS U2781 ( .A(n2271), .B(n2270), .Y(n2272) );
XOR2X1TS U2782 ( .A(n2272), .B(n2333), .Y(n2273) );
INVX2TS U2783 ( .A(n2274), .Y(n2299) );
INVX2TS U2784 ( .A(n2298), .Y(n2275) );
NAND2X1TS U2785 ( .A(n2275), .B(n2297), .Y(n2276) );
XOR2X1TS U2786 ( .A(n2299), .B(n2276), .Y(n2277) );
INVX2TS U2787 ( .A(n2278), .Y(n2283) );
NAND2X1TS U2788 ( .A(n1808), .B(n2279), .Y(n2280) );
XNOR2X1TS U2789 ( .A(n2283), .B(n2280), .Y(n2281) );
AOI21X1TS U2790 ( .A0(n2283), .A1(n1808), .B0(n2282), .Y(n2286) );
NAND2X1TS U2791 ( .A(n560), .B(n2284), .Y(n2285) );
XOR2X1TS U2792 ( .A(n2286), .B(n2285), .Y(n2287) );
INVX2TS U2793 ( .A(n2288), .Y(n2313) );
INVX2TS U2794 ( .A(n2289), .Y(n2308) );
INVX2TS U2795 ( .A(n2307), .Y(n2290) );
AOI21X1TS U2796 ( .A0(n2313), .A1(n2308), .B0(n2290), .Y(n2295) );
INVX2TS U2797 ( .A(n2291), .Y(n2293) );
NAND2X1TS U2798 ( .A(n2293), .B(n2292), .Y(n2294) );
XOR2X1TS U2799 ( .A(n2295), .B(n2294), .Y(n2296) );
INVX2TS U2800 ( .A(n2300), .Y(n2302) );
NAND2X1TS U2801 ( .A(n2302), .B(n2301), .Y(n2303) );
XNOR2X1TS U2802 ( .A(n2304), .B(n2303), .Y(n2306) );
BUFX3TS U2803 ( .A(n2305), .Y(n2326) );
NAND2X1TS U2804 ( .A(n2308), .B(n2307), .Y(n2309) );
XNOR2X1TS U2805 ( .A(n2313), .B(n2309), .Y(n2310) );
AOI21X1TS U2806 ( .A0(n2313), .A1(n2312), .B0(n2311), .Y(n2319) );
INVX2TS U2807 ( .A(n2318), .Y(n2314) );
NAND2X1TS U2808 ( .A(n2314), .B(n2317), .Y(n2315) );
XOR2X1TS U2809 ( .A(n2319), .B(n2315), .Y(n2316) );
NAND2X1TS U2810 ( .A(n2322), .B(n2321), .Y(n2323) );
XNOR2X1TS U2811 ( .A(n2324), .B(n2323), .Y(n2325) );
NAND2X1TS U2812 ( .A(n578), .B(n2328), .Y(n2330) );
XNOR2X1TS U2813 ( .A(n2330), .B(n2329), .Y(n2331) );
NAND2X1TS U2814 ( .A(n2368), .B(n2394), .Y(n375) );
NOR2BX1TS U2815 ( .AN(exp_oper_result[8]), .B(n2394), .Y(S_Oper_A_exp[8]) );
XNOR2X1TS U2816 ( .A(DP_OP_36J22_124_9196_n1), .B(n2339), .Y(n2341) );
CLKMX2X2TS U2817 ( .A(Exp_module_Overflow_flag_A), .B(n2341), .S0(n2340),
.Y(n271) );
OAI22X1TS U2818 ( .A0(Exp_module_Data_S[8]), .A1(n2345), .B0(n2344), .B1(
n2400), .Y(n272) );
AO22X1TS U2819 ( .A0(n2374), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n2378), .Y(n190) );
AO22X1TS U2820 ( .A0(n2374), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n2378), .Y(n189) );
AO22X1TS U2821 ( .A0(n2374), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n2378), .Y(n188) );
NOR4X1TS U2822 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n2349) );
NOR4X1TS U2823 ( .A(n555), .B(Op_MY[18]), .C(n440), .D(n398), .Y(n2348) );
NOR4X1TS U2824 ( .A(n438), .B(n442), .C(Op_MY[14]), .D(Op_MY[19]), .Y(n2347)
);
NOR4X1TS U2825 ( .A(Op_MY[22]), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]),
.Y(n2346) );
NOR4X1TS U2826 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n2357) );
NOR4X1TS U2827 ( .A(Op_MX[20]), .B(Op_MX[18]), .C(Op_MX[16]), .D(Op_MX[14]),
.Y(n2356) );
NOR4X1TS U2828 ( .A(Op_MX[21]), .B(Op_MX[30]), .C(Op_MX[29]), .D(Op_MX[28]),
.Y(n2354) );
NOR4X1TS U2829 ( .A(n397), .B(n401), .C(n434), .D(Op_MX[1]), .Y(n2362) );
NOR4X1TS U2830 ( .A(Op_MX[8]), .B(n2358), .C(n443), .D(n433), .Y(n2361) );
OA22X1TS U2831 ( .A0(n2366), .A1(n2365), .B0(n2364), .B1(n2363), .Y(n2367)
);
OAI2BB2XLTS U2832 ( .B0(n2368), .B1(n2367), .A0N(n2368), .A1N(zero_flag),
.Y(n311) );
OA22X1TS U2833 ( .A0(n2372), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n2371), .Y(n270) );
OA22X1TS U2834 ( .A0(n2372), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n2371), .Y(n269) );
OA22X1TS U2835 ( .A0(n2370), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n2371), .Y(n268) );
OA22X1TS U2836 ( .A0(n2370), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n2371), .Y(n267) );
OA22X1TS U2837 ( .A0(n2370), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n2371), .Y(n266) );
OA22X1TS U2838 ( .A0(n2370), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n2371), .Y(n265) );
OA22X1TS U2839 ( .A0(n2370), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n2371), .Y(n264) );
OA22X1TS U2840 ( .A0(n2372), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n2371), .Y(n263) );
AO22X1TS U2841 ( .A0(Sgf_normalized_result[3]), .A1(n2374), .B0(
final_result_ieee[3]), .B1(n2378), .Y(n187) );
INVX2TS U2842 ( .A(n2372), .Y(n2373) );
AO22X1TS U2843 ( .A0(Sgf_normalized_result[9]), .A1(n2374), .B0(
final_result_ieee[9]), .B1(n2376), .Y(n181) );
AO22X1TS U2844 ( .A0(Sgf_normalized_result[10]), .A1(n2377), .B0(
final_result_ieee[10]), .B1(n2376), .Y(n180) );
AO22X1TS U2845 ( .A0(Sgf_normalized_result[11]), .A1(n2377), .B0(
final_result_ieee[11]), .B1(n2376), .Y(n179) );
AO22X1TS U2846 ( .A0(Sgf_normalized_result[12]), .A1(n2377), .B0(
final_result_ieee[12]), .B1(n2376), .Y(n178) );
AO22X1TS U2847 ( .A0(Sgf_normalized_result[13]), .A1(n2377), .B0(
final_result_ieee[13]), .B1(n2376), .Y(n177) );
AO22X1TS U2848 ( .A0(Sgf_normalized_result[14]), .A1(n2377), .B0(
final_result_ieee[14]), .B1(n2376), .Y(n176) );
AO22X1TS U2849 ( .A0(Sgf_normalized_result[15]), .A1(n2377), .B0(
final_result_ieee[15]), .B1(n2376), .Y(n175) );
AO22X1TS U2850 ( .A0(Sgf_normalized_result[16]), .A1(n2377), .B0(
final_result_ieee[16]), .B1(n2376), .Y(n174) );
AO22X1TS U2851 ( .A0(Sgf_normalized_result[17]), .A1(n2377), .B0(
final_result_ieee[17]), .B1(n2376), .Y(n173) );
AO22X1TS U2852 ( .A0(Sgf_normalized_result[18]), .A1(n2377), .B0(
final_result_ieee[18]), .B1(n2378), .Y(n172) );
AO22X1TS U2853 ( .A0(Sgf_normalized_result[19]), .A1(n2377), .B0(
final_result_ieee[19]), .B1(n2378), .Y(n171) );
AO22X1TS U2854 ( .A0(Sgf_normalized_result[21]), .A1(n2379), .B0(
final_result_ieee[21]), .B1(n2378), .Y(n169) );
CMPR42X1TS U2855 ( .A(mult_x_55_n168), .B(mult_x_55_n280), .C(mult_x_55_n288), .D(mult_x_55_n300), .ICI(mult_x_55_n165), .S(mult_x_55_n164), .ICO(
mult_x_55_n162), .CO(mult_x_55_n163) );
CMPR42X1TS U2856 ( .A(mult_x_55_n169), .B(mult_x_55_n301), .C(mult_x_55_n289), .D(mult_x_55_n173), .ICI(mult_x_55_n170), .S(mult_x_55_n167), .ICO(
mult_x_55_n165), .CO(mult_x_55_n166) );
CMPR42X1TS U2857 ( .A(mult_x_55_n290), .B(mult_x_55_n314), .C(mult_x_55_n174), .D(mult_x_55_n178), .ICI(mult_x_55_n175), .S(mult_x_55_n172), .ICO(
mult_x_55_n170), .CO(mult_x_55_n171) );
CMPR42X1TS U2858 ( .A(n555), .B(n438), .C(mult_x_23_n280), .D(mult_x_23_n292), .ICI(mult_x_23_n163), .S(mult_x_23_n162), .ICO(mult_x_23_n160), .CO(
mult_x_23_n161) );
CMPR42X1TS U2859 ( .A(n592), .B(mult_x_23_n281), .C(mult_x_23_n293), .D(
mult_x_23_n171), .ICI(mult_x_23_n168), .S(mult_x_23_n165), .ICO(
mult_x_23_n163), .CO(mult_x_23_n164) );
CMPR42X1TS U2860 ( .A(mult_x_23_n294), .B(mult_x_23_n306), .C(mult_x_23_n172), .D(mult_x_23_n176), .ICI(mult_x_23_n173), .S(mult_x_23_n170), .ICO(
mult_x_23_n168), .CO(mult_x_23_n169) );
CMPR42X1TS U2861 ( .A(DP_OP_111J22_123_4462_n407), .B(
DP_OP_111J22_123_4462_n263), .C(DP_OP_111J22_123_4462_n384), .D(
DP_OP_111J22_123_4462_n394), .ICI(DP_OP_111J22_123_4462_n260), .S(
DP_OP_111J22_123_4462_n259), .ICO(DP_OP_111J22_123_4462_n257), .CO(
DP_OP_111J22_123_4462_n258) );
initial $sdf_annotate("FPU_Multiplication_Function_KOA_2STAGE_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_edb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_edb_e.v,v 1.1 2004/04/06 10:50:54 wig Exp $
// $Date: 2004/04/06 10:50:54 $
// $Log: inst_edb_e.v,v $
// Revision 1.1 2004/04/06 10:50:54 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_edb_e
//
// No `defines in this module
module inst_edb_e
//
// Generated module inst_edb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_edb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//
// Copyright (c) 2014 Colin Rothwell
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
// intermediary between Bluespec, which outputs an enable signal,
// and Megawizard's verilog, which doesn't have that input
module floatMulWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
input dummy_enable;
floatMul floatMul_component (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_TB_V
`define SKY130_FD_SC_HDLL__MUX2_TB_V
/**
* mux2: 2-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_hdll__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_TB_V
|
// --------------------------------------------------------------------
// Copyright (c) 2010 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: DE2_115 D5M+VGA 640*480 800*600 solution
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN Peli Li:| 22/07/2010:| Initial Revision
// --------------------------------------------------------------------
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
//to set the VGA solution
`include "VGA_Param.h"
module DE2_115_CAMERA(
//////////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
//////////// Sma //////////
SMA_CLKIN,
SMA_CLKOUT,
//////////// LED //////////
LEDG,
LEDR,
//////////// KEY //////////
KEY,
//////////// EJTAG //////////
EX_IO,
//////////// SW //////////
SW,
//////////// SEG7 //////////
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
//////////// LCD //////////
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
//////////// RS232 //////////
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
//////////// PS2 for Keyboard and Mouse //////////
PS2_CLK,
PS2_CLK2,
PS2_DAT,
PS2_DAT2,
//////////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
//////////// VGA //////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
//////////// Audio //////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
//////////// I2C for EEPROM //////////
EEP_I2C_SCLK,
EEP_I2C_SDAT,
//////////// I2C for Audio Tv-Decoder //////////
I2C_SCLK,
I2C_SDAT,
//////////// Ethernet 0 //////////
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_LINK100,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENETCLK_25,
//////////// Ethernet 1 //////////
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_LINK100,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
//////////// TV Decoder //////////
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
//////////// USB 2.0 OTG //////////
OTG_ADDR,
OTG_CS_N,
OTG_DACK_N,
OTG_DATA,
OTG_DREQ,
OTG_FSPEED,
OTG_INT,
OTG_LSPEED,
OTG_RD_N,
OTG_RST_N,
OTG_WE_N,
//////////// IR Receiver //////////
IRDA_RXD,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// SRAM //////////
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
//////////// Flash //////////
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
//////////// GPIO, GPIO connect to D5M - 5M Pixel Camera //////////
D5M_D,
D5M_FVAL,
D5M_LVAL,
D5M_PIXLCLK,
D5M_RESET_N,
D5M_SCLK,
D5M_SDATA,
D5M_STROBE,
D5M_TRIGGER,
D5M_XCLKIN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
//////////// Sma //////////
input SMA_CLKIN;
output SMA_CLKOUT;
//////////// LED //////////
output [8:0] LEDG;
output [17:0] LEDR;
//////////// KEY //////////
input [3:0] KEY;
//////////// EJTAG //////////
inout [6:0] EX_IO;
//////////// SW //////////
input [17:0] SW;
//////////// SEG7 //////////
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
//////////// LCD //////////
output LCD_BLON;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
//////////// RS232 //////////
output UART_CTS;
input UART_RTS;
input UART_RXD;
output UART_TXD;
//////////// PS2 for Keyboard and Mouse //////////
inout PS2_CLK;
inout PS2_CLK2;
inout PS2_DAT;
inout PS2_DAT2;
//////////// SDCARD //////////
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_N;
//////////// VGA //////////
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
//////////// Audio //////////
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
//////////// I2C for EEPROM //////////
output EEP_I2C_SCLK;
inout EEP_I2C_SDAT;
//////////// I2C for Audio Tv-Decoder //////////
output I2C_SCLK;
inout I2C_SDAT;
//////////// Ethernet 0 //////////
output ENET0_GTX_CLK;
input ENET0_INT_N;
input ENET0_LINK100;
output ENET0_MDC;
inout ENET0_MDIO;
output ENET0_RST_N;
input ENET0_RX_CLK;
input ENET0_RX_COL;
input ENET0_RX_CRS;
input [3:0] ENET0_RX_DATA;
input ENET0_RX_DV;
input ENET0_RX_ER;
input ENET0_TX_CLK;
output [3:0] ENET0_TX_DATA;
output ENET0_TX_EN;
output ENET0_TX_ER;
input ENETCLK_25;
//////////// Ethernet 1 //////////
output ENET1_GTX_CLK;
input ENET1_INT_N;
input ENET1_LINK100;
output ENET1_MDC;
inout ENET1_MDIO;
output ENET1_RST_N;
input ENET1_RX_CLK;
input ENET1_RX_COL;
input ENET1_RX_CRS;
input [3:0] ENET1_RX_DATA;
input ENET1_RX_DV;
input ENET1_RX_ER;
input ENET1_TX_CLK;
output [3:0] ENET1_TX_DATA;
output ENET1_TX_EN;
output ENET1_TX_ER;
//////////// TV Decoder //////////
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
//////////// USB 2.0 OTG //////////
output [1:0] OTG_ADDR;
output OTG_CS_N;
output [1:0] OTG_DACK_N;
inout [15:0] OTG_DATA;
input [1:0] OTG_DREQ;
inout OTG_FSPEED;
input [1:0] OTG_INT;
inout OTG_LSPEED;
output OTG_RD_N;
output OTG_RST_N;
output OTG_WE_N;
//////////// IR Receiver //////////
input IRDA_RXD;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [31:0] DRAM_DQ;
output [3:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// SRAM //////////
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
//////////// Flash //////////
output [22:0] FL_ADDR;
output FL_CE_N;
inout [7:0] FL_DQ;
output FL_OE_N;
output FL_RST_N;
input FL_RY;
output FL_WE_N;
output FL_WP_N;
//////////// GPIO, GPIO connect to D5M - 5M Pixel Camera //////////
input [11:0] D5M_D;
input D5M_FVAL;
input D5M_LVAL;
input D5M_PIXLCLK;
output D5M_RESET_N;
output D5M_SCLK;
inout D5M_SDATA;
input D5M_STROBE;
output D5M_TRIGGER;
output D5M_XCLKIN;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
wire [11:0] mCCD_DATA;
wire mCCD_DVAL;
wire mCCD_DVAL_d;
wire [15:0] X_Cont;
wire [15:0] Y_Cont;
wire [9:0] X_ADDR;
wire [31:0] Frame_Cont;
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
wire DLY_RST_3;
wire DLY_RST_4;
wire Read;
reg [11:0] rCCD_DATA;
reg rCCD_LVAL;
reg rCCD_FVAL;
wire [11:0] sCCD_R;
wire [11:0] sCCD_G;
wire [11:0] sCCD_B;
wire [31:0] w_HSV;
wire [31:0] i_HSV;
wire [9:0] G;
wire [9:0] P;
wire [11:0] H;
wire [11:0] S;
wire [11:0] V;
wire sCCD_DVAL;
wire sdram_ctrl_clk;
wire [9:0] oVGA_R; // VGA Red[9:0]
wire [9:0] oVGA_G; // VGA Green[9:0]
wire [9:0] oVGA_B; // VGA Blue[9:0]
//power on start
wire auto_start;
//=======================================================
// Structural coding
//=======================================================
// D5M
assign D5M_TRIGGER = 1'b1; // tRIGGER
assign D5M_RESET_N = DLY_RST_1;
assign VGA_CTRL_CLK = ~VGA_CLK;
assign LEDG = Y_Cont;
assign UART_TXD = UART_RXD;
//fetch the high 8 bits
assign VGA_R = oVGA_R[9:2];
assign VGA_G = oVGA_G[9:2];
assign VGA_B = oVGA_B[9:2];
//D5M read
always@(posedge D5M_PIXLCLK)
begin
rCCD_DATA <= D5M_D;
rCCD_LVAL <= D5M_LVAL;
rCCD_FVAL <= D5M_FVAL;
end
//auto start when power on
assign auto_start = ((KEY[0])&&(DLY_RST_3)&&(!DLY_RST_4))? 1'b1:1'b0;
//Reset module
Reset_Delay u2 ( .iCLK(CLOCK2_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2),
.oRST_3(DLY_RST_3),
.oRST_4(DLY_RST_4)
);
//D5M image capture
CCD_Capture u3 ( .oDATA(mCCD_DATA),
.oDVAL(mCCD_DVAL),
.oX_Cont(X_Cont),
.oY_Cont(Y_Cont),
.oFrame_Cont(Frame_Cont),
.iDATA(rCCD_DATA),
.iFVAL(rCCD_FVAL),
.iLVAL(rCCD_LVAL),
.iSTART(!KEY[3]|auto_start),
.iEND(!KEY[2]),
.iCLK(~D5M_PIXLCLK),
.iRST(DLY_RST_2),
.New_Frame(new_frame)
);
//D5M raw date convert to RGB data
`ifdef VGA_640x480p60
RAW2RGB u4 ( .iCLK(D5M_PIXLCLK),
.iRST(DLY_RST_1),
.iDATA(mCCD_DATA),
.iDVAL(mCCD_DVAL),
.oRed(sCCD_R),
.oGreen(sCCD_G),
.oBlue(sCCD_B),
.oDVAL(sCCD_DVAL),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont)
);
`else
RAW2RGB u4 ( .iCLK(D5M_PIXLCLK),
.iRST_n(DLY_RST_1),
.iData(mCCD_DATA),
.iDval(mCCD_DVAL),
.oRed(sCCD_R),
.oGreen(sCCD_G),
.oBlue(sCCD_B),
.oDval(sCCD_DVAL),
.iZoom(SW[16]),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont)
);
`endif
//Frame count display
SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG(position[31:0])
);
sdram_pll u6 (
.inclk0(CLOCK2_50),
.c0(sdram_ctrl_clk),
.c1(DRAM_CLK),
.c2(D5M_XCLKIN), //25M
`ifdef VGA_640x480p60
.c3(VGA_CLK) //25M
`else
.c4(VGA_CLK) //40M
`endif
);
//SDRam Read and Write as Frame Buffer
Sdram_Control u7 ( // HOST Side
.trigger(trigger),
.RESET_N(KEY[0]),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({1'b0,5'b00000,G}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
`ifdef VGA_640x480p60
.WR1_MAX_ADDR(640*480/2),
.WR1_LENGTH(8'h50),
`else
.WR1_MAX_ADDR(800*600/2),
.WR1_LENGTH(8'h80),
`endif
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(D5M_PIXLCLK),
// FIFO Write Side 2
.WR2_DATA({1'b0,5'b00000,P}),
.WR2(sCCD_DVAL),
.WR2_ADDR(23'h100000),
`ifdef VGA_640x480p60
.WR2_MAX_ADDR(23'h100000+640*480/2),
.WR2_LENGTH(8'h50),
`else
.WR2_MAX_ADDR(23'h100000+800*600/2),
.WR2_LENGTH(8'h80),
`endif
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(D5M_PIXLCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
`ifdef VGA_640x480p60
.RD1_MAX_ADDR(640*480/2),
.RD1_LENGTH(8'h50),
`else
.RD1_MAX_ADDR(800*600/2),
.RD1_LENGTH(8'h80),
`endif
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(23'h100000),
`ifdef VGA_640x480p60
.RD2_MAX_ADDR(23'h100000+640*480/2),
.RD2_LENGTH(8'h50),
`else
.RD2_MAX_ADDR(23'h100000+800*600/2),
.RD2_LENGTH(8'h80),
`endif
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(~VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM(DRAM_DQM)
);
//D5M I2C control
I2C_CCD_Config u8 ( // Host Side
.iCLK(CLOCK2_50),
.iRST_N(DLY_RST_2),
.iEXPOSURE_ADJ(KEY[1]),
.iEXPOSURE_DEC_p(SW[0]),
.iZOOM_MODE_SW(SW[16]),
// I2C Side
.I2C_SCLK(D5M_SCLK),
.I2C_SDAT(D5M_SDATA)
);
//VGA DISPLAY
VGA_Controller u1 ( // Host Side
.oRequest(Read),
.iRed(Read_DATA2[9:0]),
.iGreen({Read_DATA1[14:10],Read_DATA2[14:10]}),
.iBlue(Read_DATA1[9:0]),
// VGA Side
.oVGA_R(oVGA_R),
.oVGA_G(oVGA_G),
.oVGA_B(oVGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC_N),
.oVGA_BLANK(VGA_BLANK_N),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2),
.iZOOM_MODE_SW(SW[16])
);
wire trigger;
assign trigger = (Frame_Cont == 32'h00000100) ? 1'b1 : 1'b0;
rgb2hsv r2h(
.clk(D5M_PIXLCLK),
.clk_en(1'b1),
.rst(1'b0),
.RGB({sCCD_B[11:4],sCCD_G[11:4],sCCD_R[11:4],8'h00}),
//xxx,
.HSV(i_HSV)
);
cvinrange cir(
.HSV1(i_HSV),
.HSV2(i_HSV),
.outHSV(w_HSV)
);
/*
assign H = {w_HSV[31:24],2'b00};
assign S = {w_HSV[23:16],2'b00};
assign V = {w_HSV[15:8],2'b00};
*/
//Till this point I am sure that this P refers to pink and G refers to green
//but after those lines the connections to sdram and vga controllers are mixed
//but it doesn't matter
//because we use those for displaying only and the important is seeing a difference not
//seeing the true colors
assign P = {w_HSV[7:0],2'b00};
assign G = {w_HSV[15:8],2'b00};
assign LEDR = {new_frame,w_HSV[7:0],VGA_VS,position[31:24]};
wire new_frame;
//center_pos my_center (.x_row(X_Cont),.y_col(Y_Cont),.reset(new_frame),.clk (D5M_PIXLCLK),.center_x(position [31:16]),.center_y( position [15:0]),.valid(w_HSV));
GET_CENTER gc(.clk(D5M_PIXLCLK),.x_pos(X_Cont),.y_pos(Y_Cont),.rst(KEY[0]),.binary_pink(w_HSV[0]),.binary_green(w_HSV[8]),.new_frame(new_frame),.center(position));
wire [31:0] position ;
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
//
// This code instantiates a module that calls the various array querying
// functions.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
// Check the array sizing functions work correctly.
module array_test
#( parameter
LEFT = 5,
RIGHT = 55)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] a [LEFT:RIGHT];
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l == LEFT) && (r == RIGHT) && (s == (RIGHT - LEFT + 1))) begin
$write("*-* All Finished *-*\n");
end
$finish;
end
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:01:13 04/02/2016
// Design Name:
// Module Name: ALU_1bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_1bit
(
// Input
input a_in,
input b_in,
input carry_in,
input b_invert,
input less,
input [1:0] op,
// Output
output wire result,
output wire carry_out
);
// Internal Variables
reg b_invert_out;
reg mux_out;
wire fa_01_out;
wire and_out;
wire or_out;
//submodule
full_adder fa_01 (
.x_in ( a_in ),
.y_in ( b_invert_out ),
.c_in ( carry_in ),
.s_out ( fa_01_out ),
.c_out ( carry_out )
); // Full_Adder
// b_Inverter
always @ ( b_invert or b_in )
begin : Binvert
if ( !b_invert )
b_invert_out = b_in; // b
else
b_invert_out = ~ b_in; // b'
end
// Logical_operation
assign and_out = a_in & b_invert_out;
assign or_out = a_in | b_invert_out;
assign result = mux_out;
// op_Selection
always @ ( op or and_out or or_out or less or fa_01_out )
begin : Operation
if ( op == 0 ) // AND
mux_out = and_out;
else if ( op == 1) // OR
mux_out = or_out;
else if ( op == 2) // ADD/SUB
mux_out = fa_01_out;
else // SLT
mux_out = less;
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : adxl362.v
// Description : Top level for ADXL362 Model
// Author : Philip Tracton
// Created On : Wed Jun 22 21:28:54 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jun 22 21:28:54 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "adxl362_registers.vh"
module adxl362 (/*AUTOARG*/
// Outputs
MISO, INT1, INT2,
// Inputs
SCLK, MOSI, nCS
) ;
input wire SCLK;
input wire MOSI;
input wire nCS;
output wire MISO;
output reg INT1;
output reg INT2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] act_inact_ctrl; // From registers of adxl362_regs.v
wire [5:0] address; // From spi of adxl362_spi.v
wire clk; // From sys_con of adxl362_system_controller.v
wire clk_odr; // From sys_con of adxl362_system_controller.v
wire clk_sys; // From sys_con of adxl362_system_controller.v
wire data_fifo_write; // From spi of adxl362_spi.v
wire [7:0] data_write; // From spi of adxl362_spi.v
wire [3:0] fifo_ctrl; // From registers of adxl362_regs.v
wire [7:0] fifo_samples; // From registers of adxl362_regs.v
wire fifo_write; // From accelerometer of adxl362_accelerometer.v
wire [15:0] fifo_write_data; // From accelerometer of adxl362_accelerometer.v
wire [7:0] filter_ctrl; // From registers of adxl362_regs.v
wire [7:0] intmap1; // From registers of adxl362_regs.v
wire [7:0] intmap2; // From registers of adxl362_regs.v
wire [7:0] power_ctrl; // From registers of adxl362_regs.v
wire read_data_fifo; // From spi of adxl362_spi.v
wire reset; // From sys_con of adxl362_system_controller.v
wire rising_clk_odr; // From accelerometer of adxl362_accelerometer.v
wire rst; // From sys_con of adxl362_system_controller.v
wire self_test; // From registers of adxl362_regs.v
wire [10:0] threshold_active; // From registers of adxl362_regs.v
wire [10:0] threshold_inactive; // From registers of adxl362_regs.v
wire [7:0] time_active; // From registers of adxl362_regs.v
wire [15:0] time_inactive; // From registers of adxl362_regs.v
wire write; // From spi of adxl362_spi.v
// End of automatics
/*AUTOREG*/
reg soft_reset = 0;
wire [11:0] xdata;
wire [11:0] ydata;
wire [11:0] zdata;
wire [11:0] temperature;
wire [7:0] data_fifo;
wire [2:0] odr;
wire [1:0] fifo_mode;
wire fifo_enable;
wire fifo_temp;
wire fifo_empty;
wire [7:0] status;
reg data_ready = 0;
wire [15:0] data_fifo_read;
wire [7:0] data_read;
wire empty;
assign odr = filter_ctrl[2:0];
assign fifo_mode = fifo_ctrl[1:0];
assign fifo_enable = (fifo_ctrl[1:0] != 2'b00);
assign fifo_temp = fifo_ctrl[2];
assign status = {5'b0, ~empty, data_ready};
always @(posedge clk_sys)
if (rst) begin
INT1 <= 0;
end else begin
if (intmap1[0]) begin
if (intmap1[7]) begin
INT1 <= ~status[0];
end else begin
INT1 <= status[0];
end
end
if (intmap1[1]) begin
if (intmap1[7]) begin
INT1 <= ~status[1];
end else begin
INT1 <= status[1];
end
end
end // else: !if(rst)
always @(posedge clk_sys)
if (rst) begin
INT2 <= 0;
end else begin
if (intmap2[0]) begin
if (intmap2[7]) begin
INT2 <= ~status[0];
end else begin
INT2 <= status[0];
end
end
if (intmap2[1]) begin
if (intmap2[7]) begin
INT2 <= ~status[1];
end else begin
INT2 <= status[1];
end
end
end // else: !if(rst)
always @(posedge clk_sys) begin
//data_ready = fifo_enable & ~fifo_empty;
if (fifo_write || rising_clk_odr) begin
data_ready <= 1;
end
if (!write & ((address == `ADXL362_XDATA_LOW) |
(address == `ADXL362_YDATA_LOW) |
(address == `ADXL362_ZDATA_LOW) )
) begin
data_ready <= 0;
end
end
//
// System Controller
//
// This module generates the 51.2 KHz clock used in the sytem. This
// module is not synthesizable.
//
adxl362_system_controller sys_con (/*AUTOINST*/
// Outputs
.clk (clk),
.clk_sys (clk_sys),
.reset (reset),
.clk_odr (clk_odr),
.rst (rst),
// Inputs
.soft_reset (soft_reset),
.odr (odr[2:0]));
//
// SPI
//
// This module handles SPI communication with host CPU. Register bus interface
// is synched to the clk domain in this module!
//
adxl362_spi spi(/*AUTOINST*/
// Outputs
.MISO (MISO),
.address (address[5:0]),
.data_write (data_write[7:0]),
.data_fifo_write (data_fifo_write),
.write (write),
.read_data_fifo (read_data_fifo),
// Inputs
.SCLK (SCLK),
.MOSI (MOSI),
.nCS (nCS),
.clk_sys (clk_sys),
.data_read (data_read[7:0]),
.data_fifo_read (data_fifo_read[15:0]),
.rst (rst));
//
// Registers
//
// These are the firmware accessible registers
//
adxl362_regs registers(/*AUTOINST*/
// Outputs
.data_read (data_read[7:0]),
.threshold_active (threshold_active[10:0]),
.time_active (time_active[7:0]),
.threshold_inactive (threshold_inactive[10:0]),
.time_inactive (time_inactive[15:0]),
.act_inact_ctrl (act_inact_ctrl[7:0]),
.fifo_ctrl (fifo_ctrl[3:0]),
.fifo_samples (fifo_samples[7:0]),
.intmap1 (intmap1[7:0]),
.intmap2 (intmap2[7:0]),
.filter_ctrl (filter_ctrl[7:0]),
.power_ctrl (power_ctrl[7:0]),
.self_test (self_test),
// Inputs
.clk_sys (clk_sys),
.write (write),
.address (address[5:0]),
.data_write (data_write[7:0]),
.xdata (xdata[11:0]),
.ydata (ydata[11:0]),
.zdata (zdata[11:0]),
.temperature (temperature[11:0]),
.status (status[7:0]));
//
// Data FIFO
//
adxl362_fifo fifo(
// Outputs
.data_read (data_fifo_read[15:0]),
.full (full),
.empty (empty),
// Inputs
.data_write (fifo_write_data),
.clk (clk_sys),
.rst (rst),
.flush (1'b0),
.read (read_data_fifo),
.write (fifo_write));
//
// Accelerometer
//
adxl362_accelerometer accelerometer (/*AUTOINST*/
// Outputs
.rising_clk_odr (rising_clk_odr),
.fifo_write (fifo_write),
.fifo_write_data(fifo_write_data[15:0]),
.xdata (xdata[11:0]),
.ydata (ydata[11:0]),
.zdata (zdata[11:0]),
.temperature (temperature[11:0]),
// Inputs
.clk_sys (clk_sys),
.clk_odr (clk_odr),
.fifo_mode (fifo_mode[1:0]),
.fifo_temp (fifo_temp));
endmodule // adxl362
|
/*checksum available 6 cycles after all inputs asserted*/
module binary_adder_tree(A, B, C, D, E, F, G, H, I, clk, checksum_reg);
input [15:0] A, B, C, D, E, F, G, H, I;
input clk;
output reg [15:0] checksum_reg;
wire [15:0] checksum;
wire [16:0] sum_a_b, sum_c_d, sum_e_f, sum_g_h, sum_ab_cd, sum_ef_gh, sum_abcd_efgh, sum_i;
reg [16:0] sumreg_ab, sumreg_cd, sumreg_ef, sumreg_gh, sumreg_ab_cd, sumreg_ef_gh, sumreg_abcd_efgh, sumreg_i;
// Registers
always @ (posedge clk)
begin
//cycle 1
sumreg_ab <= sum_a_b;
sumreg_cd <= sum_c_d;
sumreg_ef <= sum_e_f;
sumreg_gh <= sum_g_h;
//cycle 2
sumreg_ab_cd <= sum_ab_cd;
sumreg_ef_gh <= sum_ef_gh;
//cycle 3
sumreg_abcd_efgh <= sum_abcd_efgh;
//cycle 4
sumreg_i <= sum_i;
//CYCLE 5
checksum_reg <= checksum;
end
// 2-bit additions
assign sum_a_b = A + B;
assign sum_c_d = C + D;
assign sum_e_f = E + F;
assign sum_g_h = G + H;
assign sum_ab_cd = sumreg_ab + sumreg_cd;
assign sum_ef_gh = sumreg_ef + sumreg_gh;
assign sum_abcd_efgh = sumreg_ab_cd + sumreg_ef_gh;
assign sum_i = sumreg_abcd_efgh+I;
assign checksum = ~((sumreg_i[16]==1'b1)?(sumreg_i[15:0]+1):sumreg_i[15:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_2_V
`define SKY130_FD_SC_HS__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_2_V
|
`include "constants.vh"
`include "rv32_opcodes.vh"
`include "alu_ops.vh"
`default_nettype none
module decoder(
input wire [31:0] inst,
output reg [`IMM_TYPE_WIDTH-1:0] imm_type,
output wire [`REG_SEL-1:0] rs1,
output wire [`REG_SEL-1:0] rs2,
output wire [`REG_SEL-1:0] rd,
output reg [`SRC_A_SEL_WIDTH-1:0] src_a_sel,
output reg [`SRC_B_SEL_WIDTH-1:0] src_b_sel,
output reg wr_reg,
output reg uses_rs1,
output reg uses_rs2,
output reg illegal_instruction,
output reg [`ALU_OP_WIDTH-1:0] alu_op,
output reg [`RS_ENT_SEL-1:0] rs_ent,
// output reg dmem_use,
// output reg dmem_write,
output wire [2:0] dmem_size,
output wire [`MEM_TYPE_WIDTH-1:0] dmem_type,
output reg [`MD_OP_WIDTH-1:0] md_req_op,
output reg md_req_in_1_signed,
output reg md_req_in_2_signed,
output reg [`MD_OUT_SEL_WIDTH-1:0] md_req_out_sel
);
wire [`ALU_OP_WIDTH-1:0] srl_or_sra;
wire [`ALU_OP_WIDTH-1:0] add_or_sub;
wire [`RS_ENT_SEL-1:0] rs_ent_md;
wire [6:0] opcode = inst[6:0];
wire [6:0] funct7 = inst[31:25];
wire [11:0] funct12 = inst[31:20];
wire [2:0] funct3 = inst[14:12];
// reg [`MD_OP_WIDTH-1:0] md_req_op;
reg [`ALU_OP_WIDTH-1:0] alu_op_arith;
assign rd = inst[11:7];
assign rs1 = inst[19:15];
assign rs2 = inst[24:20];
assign dmem_size = {1'b0,funct3[1:0]};
assign dmem_type = funct3;
always @ (*) begin
imm_type = `IMM_I;
src_a_sel = `SRC_A_RS1;
src_b_sel = `SRC_B_IMM;
wr_reg = 1'b0;
uses_rs1 = 1'b1;
uses_rs2 = 1'b0;
illegal_instruction = 1'b0;
// dmem_use = 1'b0;
// dmem_write = 1'b0;
rs_ent = `RS_ENT_ALU;
alu_op = `ALU_OP_ADD;
case (opcode)
`RV32_LOAD : begin
// dmem_use = 1'b1;
wr_reg = 1'b1;
rs_ent = `RS_ENT_LDST;
// wb_src_sel_DX = `WB_SRC_MEM;
end
`RV32_STORE : begin
uses_rs2 = 1'b1;
imm_type = `IMM_S;
// dmem_use = 1'b1;
// dmem_write = 1'b1;
rs_ent = `RS_ENT_LDST;
end
`RV32_BRANCH : begin
uses_rs2 = 1'b1;
//branch_taken_unkilled = cmp_true;
src_b_sel = `SRC_B_RS2;
case (funct3)
`RV32_FUNCT3_BEQ : alu_op = `ALU_OP_SEQ;
`RV32_FUNCT3_BNE : alu_op = `ALU_OP_SNE;
`RV32_FUNCT3_BLT : alu_op = `ALU_OP_SLT;
`RV32_FUNCT3_BLTU : alu_op = `ALU_OP_SLTU;
`RV32_FUNCT3_BGE : alu_op = `ALU_OP_SGE;
`RV32_FUNCT3_BGEU : alu_op = `ALU_OP_SGEU;
default : illegal_instruction = 1'b1;
endcase // case (funct3)
rs_ent = `RS_ENT_BRANCH;
end
`RV32_JAL : begin
// jal_unkilled = 1'b1;
uses_rs1 = 1'b0;
src_a_sel = `SRC_A_PC;
src_b_sel = `SRC_B_FOUR;
wr_reg = 1'b1;
rs_ent = `RS_ENT_JAL;
end
`RV32_JALR : begin
illegal_instruction = (funct3 != 0);
// jalr_unkilled = 1'b1;
src_a_sel = `SRC_A_PC;
src_b_sel = `SRC_B_FOUR;
wr_reg = 1'b1;
rs_ent = `RS_ENT_JALR;
end
/*
`RV32_MISC_MEM : begin
case (funct3)
`RV32_FUNCT3_FENCE : begin
if ((inst[31:28] == 0) && (rs1 == 0) && (reg_to_wr_DX == 0))
; // most fences are no-ops
else
illegal_instruction = 1'b1;
end
`RV32_FUNCT3_FENCE_I : begin
if ((inst[31:20] == 0) && (rs1 == 0) && (reg_to_wr_DX == 0))
fence_i = 1'b1;
else
illegal_instruction = 1'b1;
end
default : illegal_instruction = 1'b1;
endcase // case (funct3)
end
*/
`RV32_OP_IMM : begin
alu_op = alu_op_arith;
wr_reg = 1'b1;
end
`RV32_OP : begin
uses_rs2 = 1'b1;
src_b_sel = `SRC_B_RS2;
alu_op = alu_op_arith;
wr_reg = 1'b1;
if (funct7 == `RV32_FUNCT7_MUL_DIV) begin
// uses_md_unkilled = 1'b1;
rs_ent = rs_ent_md;
// wb_src_sel_DX = `WB_SRC_MD;
end
end
/*
`RV32_SYSTEM : begin
wb_src_sel_DX = `WB_SRC_CSR;
wr_reg = (funct3 != `RV32_FUNCT3_PRIV);
case (funct3)
`RV32_FUNCT3_PRIV : begin
if ((rs1 == 0) && (reg_to_wr_DX == 0)) begin
case (funct12)
`RV32_FUNCT12_ECALL : ecall = 1'b1;
`RV32_FUNCT12_EBREAK : ebreak = 1'b1;
`RV32_FUNCT12_ERET : begin
if (prv == 0)
illegal_instruction = 1'b1;
else
eret_unkilled = 1'b1;
end
default : illegal_instruction = 1'b1;
endcase // case (funct12)
end // if ((rs1 == 0) && (reg_to_wr_DX == 0))
end // case: `RV32_FUNCT3_PRIV
`RV32_FUNCT3_CSRRW : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_WRITE;
`RV32_FUNCT3_CSRRS : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_SET;
`RV32_FUNCT3_CSRRC : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_CLEAR;
`RV32_FUNCT3_CSRRWI : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_WRITE;
`RV32_FUNCT3_CSRRSI : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_SET;
`RV32_FUNCT3_CSRRCI : csr_cmd = (rs1 == 0) ? `CSR_READ : `CSR_CLEAR;
default : illegal_instruction = 1'b1;
endcase // case (funct3)
end
*/
`RV32_AUIPC : begin
uses_rs1 = 1'b0;
src_a_sel = `SRC_A_PC;
imm_type = `IMM_U;
wr_reg = 1'b1;
end
`RV32_LUI : begin
uses_rs1 = 1'b0;
src_a_sel = `SRC_A_ZERO;
imm_type = `IMM_U;
wr_reg = 1'b1;
end
default : begin
illegal_instruction = 1'b1;
end
endcase // case (opcode)
end // always @ (*)
assign add_or_sub = ((opcode == `RV32_OP) && (funct7[5])) ? `ALU_OP_SUB : `ALU_OP_ADD;
assign srl_or_sra = (funct7[5]) ? `ALU_OP_SRA : `ALU_OP_SRL;
always @(*) begin
case (funct3)
`RV32_FUNCT3_ADD_SUB : alu_op_arith = add_or_sub;
`RV32_FUNCT3_SLL : alu_op_arith = `ALU_OP_SLL;
`RV32_FUNCT3_SLT : alu_op_arith = `ALU_OP_SLT;
`RV32_FUNCT3_SLTU : alu_op_arith = `ALU_OP_SLTU;
`RV32_FUNCT3_XOR : alu_op_arith = `ALU_OP_XOR;
`RV32_FUNCT3_SRA_SRL : alu_op_arith = srl_or_sra;
`RV32_FUNCT3_OR : alu_op_arith = `ALU_OP_OR;
`RV32_FUNCT3_AND : alu_op_arith = `ALU_OP_AND;
default : alu_op_arith = `ALU_OP_ADD;
endcase // case (funct3)
end // always @ begin
//assign md_req_valid = uses_md;
assign rs_ent_md = (
(funct3 == `RV32_FUNCT3_MUL) ||
(funct3 == `RV32_FUNCT3_MULH) ||
(funct3 == `RV32_FUNCT3_MULHSU) ||
(funct3 == `RV32_FUNCT3_MULHU)
) ? `RS_ENT_MUL : `RS_ENT_DIV;
always @(*) begin
md_req_op = `MD_OP_MUL;
md_req_in_1_signed = 0;
md_req_in_2_signed = 0;
md_req_out_sel = `MD_OUT_LO;
case (funct3)
`RV32_FUNCT3_MUL : begin
end
`RV32_FUNCT3_MULH : begin
md_req_in_1_signed = 1;
md_req_in_2_signed = 1;
md_req_out_sel = `MD_OUT_HI;
end
`RV32_FUNCT3_MULHSU : begin
md_req_in_1_signed = 1;
md_req_out_sel = `MD_OUT_HI;
end
`RV32_FUNCT3_MULHU : begin
md_req_out_sel = `MD_OUT_HI;
end
`RV32_FUNCT3_DIV : begin
md_req_op = `MD_OP_DIV;
md_req_in_1_signed = 1;
md_req_in_2_signed = 1;
end
`RV32_FUNCT3_DIVU : begin
md_req_op = `MD_OP_DIV;
end
`RV32_FUNCT3_REM : begin
md_req_op = `MD_OP_REM;
md_req_in_1_signed = 1;
md_req_in_2_signed = 1;
md_req_out_sel = `MD_OUT_REM;
end
`RV32_FUNCT3_REMU : begin
md_req_op = `MD_OP_REM;
md_req_out_sel = `MD_OUT_REM;
end
endcase
end
endmodule // decoder
`default_nettype wire
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Ram.v when simulating
// the core, Ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Ram(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Ram.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//======================================================================
//
// fltfpga.v
// ---------
// Top level wrapper for the fltfpga design.
// The fltfpga (FairLight FPGA) is an attempt at implementing a
// demo system om the TerasIC C5G development board using the
// board HDMI and AC97 interfaces for graphics and sound.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fltfpga(
// Clock and reset.
input wire clk,
input wire reset_n,
// Board I2C interface.
output wire hdmi_i2c_clk,
input wire hdmi_i2c_data_in,
output wire hdmi_i2c_data_out,
// HDMI interface.
input wire hdmi_tx_int,
output wire [23 : 0] hdmi_tdx,
output wire hdmi_tx_clk,
output wire hdmi_tx_data_en,
output wire hdmi_tx_vsync,
output wire hdmi_tx_hsync,
output wire hdmi_tx_de,
// I2C interface
input wire scl_in,
output wire scl_out,
input wire sda_in,
output wire sda_out,
// AC97 interface.
// LED interface.
output wire [7 : 0] led,
// button interface.
input wire button0,
input wire button1,
// USB-UART interface.
input wire uart_rxd,
output wire uart_txd
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter AUDIO_I2C_ADDR = 8'h42;
parameter HDMI_I2C_ADDR = 8'h43;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
endmodule // fltfpga
//======================================================================
// EOF fltfpga.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_PP_SYMBOL_V
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
`ifndef INCLUDE_ISA
`include "ISA.v"
`endif
module WB (
input clk, // Clock
// pipeline in
input wire [`WIDTH - 1:0] IR_in,
input wire [`WIDTH - 3:0] PC_in,
input wire [`WIDTH - 1:0] Z_in,
// processor output
output reg Halt,
`ifdef TRACE_PIPELINE
// debug output
output wire [`WIDTH - 1:0] IR_out,
output wire [`WIDTH - 3:0] PC_out,
`endif
// reg
output reg [`REG_ADDR_LEN - 1:0] Addr,
output reg [`WIDTH - 1:0] Data,
output reg wr_en,
output reg [1:0] w_mode //w_mode: 0-word, 1-halfword, 2-byte
);
wire [5:0] OpCode;
wire [4:0] Rd;
assign OpCode = IR_in[31:26];
assign Rd = IR_in[25:21];
`ifdef TRACE_PIPELINE
assign IR_out = IR_in;
assign PC_out = PC_in;
`endif
always @(IR_in) begin
Halt = 0;
w_mode = 0;
wr_en = 0;
case(OpCode)
`LW: begin
//Addr = Rd;
//Data = Z_in;
WriteReg(Rd, Z_in, 0);
end
`LH: begin
//w_mode = 1;
//Addr = Rd;
//Data = Z_in;
WriteReg(Rd, Z_in, 1);
end
`LD: begin
//w_mode = 1;
//Addr = Rd;
//Data = Z_in;
WriteReg(Rd, Z_in, 1);
end
`R_TYPE, `I_TYPE: begin
//Addr = Rd;
//Data = Z_in;
WriteReg(Rd, Z_in, 0);
end
`JAL, `JALR: begin
//Addr = 31;
//Data = Z_in;
WriteReg(Rd, Z_in, 0);
end
//`HALT: Halt = 1;
endcase
end
always @(posedge clk) begin
if(OpCode == `HALT)
Halt = 1;
end
task WriteReg(input [`REG_ADDR_LEN - 1:0] Addr_in,
input [`WIDTH - 1:0] Data_in,
input [1:0] w_mode_in);
begin
w_mode = w_mode_in;
Data = Data_in;
Addr = Addr_in;
wr_en = 1;
end
endtask
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:33:03 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiS1_SThreadBusy O 1
// wsiS1_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wsiM1_MCmd O 3
// wsiM1_MReqLast O 1
// wsiM1_MBurstPrecise O 1
// wsiM1_MBurstLength O 12
// wsiM1_MData O 32 reg
// wsiM1_MByteEn O 4 reg
// wsiM1_MReqInfo O 8
// wsiM1_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS1_MCmd I 3
// wsiS1_MBurstLength I 12
// wsiS1_MData I 32
// wsiS1_MByteEn I 4
// wsiS1_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiS1_MReqLast I 1
// wsiS1_MBurstPrecise I 1
// wsiS1_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wsiM1_SThreadBusy I 1 reg
// wsiM1_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWsiSplitter2x24B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo,
wsiS1_SThreadBusy,
wsiS1_SReset_n,
wsiS1_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wsiM1_MCmd,
wsiM1_MReqLast,
wsiM1_MBurstPrecise,
wsiM1_MBurstLength,
wsiM1_MData,
wsiM1_MByteEn,
wsiM1_MReqInfo,
wsiM1_SThreadBusy,
wsiM1_MReset_n,
wsiM1_SReset_n);
parameter [31 : 0] ctrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// action method wsiS1_mCmd
input [2 : 0] wsiS1_MCmd;
// action method wsiS1_mReqLast
input wsiS1_MReqLast;
// action method wsiS1_mBurstPrecise
input wsiS1_MBurstPrecise;
// action method wsiS1_mBurstLength
input [11 : 0] wsiS1_MBurstLength;
// action method wsiS1_mData
input [31 : 0] wsiS1_MData;
// action method wsiS1_mByteEn
input [3 : 0] wsiS1_MByteEn;
// action method wsiS1_mReqInfo
input [7 : 0] wsiS1_MReqInfo;
// action method wsiS1_mDataInfo
// value method wsiS1_sThreadBusy
output wsiS1_SThreadBusy;
// value method wsiS1_sReset_n
output wsiS1_SReset_n;
// action method wsiS1_mReset_n
input wsiS1_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wsiM1_mCmd
output [2 : 0] wsiM1_MCmd;
// value method wsiM1_mReqLast
output wsiM1_MReqLast;
// value method wsiM1_mBurstPrecise
output wsiM1_MBurstPrecise;
// value method wsiM1_mBurstLength
output [11 : 0] wsiM1_MBurstLength;
// value method wsiM1_mData
output [31 : 0] wsiM1_MData;
// value method wsiM1_mByteEn
output [3 : 0] wsiM1_MByteEn;
// value method wsiM1_mReqInfo
output [7 : 0] wsiM1_MReqInfo;
// value method wsiM1_mDataInfo
// action method wsiM1_sThreadBusy
input wsiM1_SThreadBusy;
// value method wsiM1_mReset_n
output wsiM1_MReset_n;
// action method wsiM1_sReset_n
input wsiM1_SReset_n;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData, wsiM1_MData;
wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo;
wire [3 : 0] wsiM0_MByteEn, wsiM1_MByteEn;
wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
// inlined wires
wire [95 : 0] wsi_M0_extStatusW$wget,
wsi_M1_extStatusW$wget,
wsi_S0_extStatusW$wget,
wsi_S1_extStatusW$wget;
wire [71 : 0] wci_wciReq$wget;
wire [60 : 0] wsi_M0_reqFifo_x_wire$wget,
wsi_M1_reqFifo_x_wire$wget,
wsi_S0_wsiReq$wget,
wsi_S1_wsiReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mAddr_w$wget,
wci_Es_mData_w$wget,
wsi_Es0_mData_w$wget,
wsi_Es1_mData_w$wget;
wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget;
wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget,
wsi_Es0_mByteEn_w$wget,
wsi_Es1_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget,
wci_wEdge$wget,
wsi_Es0_mCmd_w$wget,
wsi_Es1_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsi_Es0_mBurstLength_w$whas,
wsi_Es0_mBurstPrecise_w$whas,
wsi_Es0_mByteEn_w$whas,
wsi_Es0_mCmd_w$whas,
wsi_Es0_mDataInfo_w$whas,
wsi_Es0_mData_w$whas,
wsi_Es0_mReqInfo_w$whas,
wsi_Es0_mReqLast_w$whas,
wsi_Es1_mBurstLength_w$whas,
wsi_Es1_mBurstPrecise_w$whas,
wsi_Es1_mByteEn_w$whas,
wsi_Es1_mCmd_w$whas,
wsi_Es1_mDataInfo_w$whas,
wsi_Es1_mData_w$whas,
wsi_Es1_mReqInfo_w$whas,
wsi_Es1_mReqLast_w$whas,
wsi_M0_operateD_1$wget,
wsi_M0_operateD_1$whas,
wsi_M0_peerIsReady_1$wget,
wsi_M0_peerIsReady_1$whas,
wsi_M0_reqFifo_dequeueing$whas,
wsi_M0_reqFifo_enqueueing$whas,
wsi_M0_reqFifo_x_wire$whas,
wsi_M0_sThreadBusy_pw$whas,
wsi_M1_operateD_1$wget,
wsi_M1_operateD_1$whas,
wsi_M1_peerIsReady_1$wget,
wsi_M1_peerIsReady_1$whas,
wsi_M1_reqFifo_dequeueing$whas,
wsi_M1_reqFifo_enqueueing$whas,
wsi_M1_reqFifo_x_wire$whas,
wsi_M1_sThreadBusy_pw$whas,
wsi_S0_operateD_1$wget,
wsi_S0_operateD_1$whas,
wsi_S0_peerIsReady_1$wget,
wsi_S0_peerIsReady_1$whas,
wsi_S0_reqFifo_doResetClr$whas,
wsi_S0_reqFifo_doResetDeq$whas,
wsi_S0_reqFifo_doResetEnq$whas,
wsi_S0_reqFifo_r_clr$whas,
wsi_S0_reqFifo_r_deq$whas,
wsi_S0_reqFifo_r_enq$whas,
wsi_S0_sThreadBusy_dw$wget,
wsi_S0_sThreadBusy_dw$whas,
wsi_S0_wsiReq$whas,
wsi_S1_operateD_1$wget,
wsi_S1_operateD_1$whas,
wsi_S1_peerIsReady_1$wget,
wsi_S1_peerIsReady_1$whas,
wsi_S1_reqFifo_doResetClr$whas,
wsi_S1_reqFifo_doResetDeq$whas,
wsi_S1_reqFifo_doResetEnq$whas,
wsi_S1_reqFifo_r_clr$whas,
wsi_S1_reqFifo_r_deq$whas,
wsi_S1_reqFifo_r_enq$whas,
wsi_S1_sThreadBusy_dw$wget,
wsi_S1_sThreadBusy_dw$whas,
wsi_S1_wsiReq$whas;
// register splitCtrl
reg [31 : 0] splitCtrl;
wire [31 : 0] splitCtrl$D_IN;
wire splitCtrl$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsi_M0_burstKind
reg [1 : 0] wsi_M0_burstKind;
wire [1 : 0] wsi_M0_burstKind$D_IN;
wire wsi_M0_burstKind$EN;
// register wsi_M0_errorSticky
reg wsi_M0_errorSticky;
wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN;
// register wsi_M0_iMesgCount
reg [31 : 0] wsi_M0_iMesgCount;
wire [31 : 0] wsi_M0_iMesgCount$D_IN;
wire wsi_M0_iMesgCount$EN;
// register wsi_M0_isReset_isInReset
reg wsi_M0_isReset_isInReset;
wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN;
// register wsi_M0_operateD
reg wsi_M0_operateD;
wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN;
// register wsi_M0_pMesgCount
reg [31 : 0] wsi_M0_pMesgCount;
wire [31 : 0] wsi_M0_pMesgCount$D_IN;
wire wsi_M0_pMesgCount$EN;
// register wsi_M0_peerIsReady
reg wsi_M0_peerIsReady;
wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN;
// register wsi_M0_reqFifo_c_r
reg [1 : 0] wsi_M0_reqFifo_c_r;
wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN;
wire wsi_M0_reqFifo_c_r$EN;
// register wsi_M0_reqFifo_q_0
reg [60 : 0] wsi_M0_reqFifo_q_0;
reg [60 : 0] wsi_M0_reqFifo_q_0$D_IN;
wire wsi_M0_reqFifo_q_0$EN;
// register wsi_M0_reqFifo_q_1
reg [60 : 0] wsi_M0_reqFifo_q_1;
reg [60 : 0] wsi_M0_reqFifo_q_1$D_IN;
wire wsi_M0_reqFifo_q_1$EN;
// register wsi_M0_sThreadBusy_d
reg wsi_M0_sThreadBusy_d;
wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN;
// register wsi_M0_statusR
reg [7 : 0] wsi_M0_statusR;
wire [7 : 0] wsi_M0_statusR$D_IN;
wire wsi_M0_statusR$EN;
// register wsi_M0_tBusyCount
reg [31 : 0] wsi_M0_tBusyCount;
wire [31 : 0] wsi_M0_tBusyCount$D_IN;
wire wsi_M0_tBusyCount$EN;
// register wsi_M0_trafficSticky
reg wsi_M0_trafficSticky;
wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN;
// register wsi_M1_burstKind
reg [1 : 0] wsi_M1_burstKind;
wire [1 : 0] wsi_M1_burstKind$D_IN;
wire wsi_M1_burstKind$EN;
// register wsi_M1_errorSticky
reg wsi_M1_errorSticky;
wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN;
// register wsi_M1_iMesgCount
reg [31 : 0] wsi_M1_iMesgCount;
wire [31 : 0] wsi_M1_iMesgCount$D_IN;
wire wsi_M1_iMesgCount$EN;
// register wsi_M1_isReset_isInReset
reg wsi_M1_isReset_isInReset;
wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN;
// register wsi_M1_operateD
reg wsi_M1_operateD;
wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN;
// register wsi_M1_pMesgCount
reg [31 : 0] wsi_M1_pMesgCount;
wire [31 : 0] wsi_M1_pMesgCount$D_IN;
wire wsi_M1_pMesgCount$EN;
// register wsi_M1_peerIsReady
reg wsi_M1_peerIsReady;
wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN;
// register wsi_M1_reqFifo_c_r
reg [1 : 0] wsi_M1_reqFifo_c_r;
wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN;
wire wsi_M1_reqFifo_c_r$EN;
// register wsi_M1_reqFifo_q_0
reg [60 : 0] wsi_M1_reqFifo_q_0;
reg [60 : 0] wsi_M1_reqFifo_q_0$D_IN;
wire wsi_M1_reqFifo_q_0$EN;
// register wsi_M1_reqFifo_q_1
reg [60 : 0] wsi_M1_reqFifo_q_1;
reg [60 : 0] wsi_M1_reqFifo_q_1$D_IN;
wire wsi_M1_reqFifo_q_1$EN;
// register wsi_M1_sThreadBusy_d
reg wsi_M1_sThreadBusy_d;
wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN;
// register wsi_M1_statusR
reg [7 : 0] wsi_M1_statusR;
wire [7 : 0] wsi_M1_statusR$D_IN;
wire wsi_M1_statusR$EN;
// register wsi_M1_tBusyCount
reg [31 : 0] wsi_M1_tBusyCount;
wire [31 : 0] wsi_M1_tBusyCount$D_IN;
wire wsi_M1_tBusyCount$EN;
// register wsi_M1_trafficSticky
reg wsi_M1_trafficSticky;
wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN;
// register wsi_S0_burstKind
reg [1 : 0] wsi_S0_burstKind;
wire [1 : 0] wsi_S0_burstKind$D_IN;
wire wsi_S0_burstKind$EN;
// register wsi_S0_errorSticky
reg wsi_S0_errorSticky;
wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN;
// register wsi_S0_iMesgCount
reg [31 : 0] wsi_S0_iMesgCount;
wire [31 : 0] wsi_S0_iMesgCount$D_IN;
wire wsi_S0_iMesgCount$EN;
// register wsi_S0_isReset_isInReset
reg wsi_S0_isReset_isInReset;
wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN;
// register wsi_S0_mesgWordLength
reg [11 : 0] wsi_S0_mesgWordLength;
wire [11 : 0] wsi_S0_mesgWordLength$D_IN;
wire wsi_S0_mesgWordLength$EN;
// register wsi_S0_operateD
reg wsi_S0_operateD;
wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN;
// register wsi_S0_pMesgCount
reg [31 : 0] wsi_S0_pMesgCount;
wire [31 : 0] wsi_S0_pMesgCount$D_IN;
wire wsi_S0_pMesgCount$EN;
// register wsi_S0_peerIsReady
reg wsi_S0_peerIsReady;
wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN;
// register wsi_S0_reqFifo_countReg
reg [1 : 0] wsi_S0_reqFifo_countReg;
wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN;
wire wsi_S0_reqFifo_countReg$EN;
// register wsi_S0_reqFifo_levelsValid
reg wsi_S0_reqFifo_levelsValid;
wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN;
// register wsi_S0_statusR
reg [7 : 0] wsi_S0_statusR;
wire [7 : 0] wsi_S0_statusR$D_IN;
wire wsi_S0_statusR$EN;
// register wsi_S0_tBusyCount
reg [31 : 0] wsi_S0_tBusyCount;
wire [31 : 0] wsi_S0_tBusyCount$D_IN;
wire wsi_S0_tBusyCount$EN;
// register wsi_S0_trafficSticky
reg wsi_S0_trafficSticky;
wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN;
// register wsi_S0_wordCount
reg [11 : 0] wsi_S0_wordCount;
wire [11 : 0] wsi_S0_wordCount$D_IN;
wire wsi_S0_wordCount$EN;
// register wsi_S1_burstKind
reg [1 : 0] wsi_S1_burstKind;
wire [1 : 0] wsi_S1_burstKind$D_IN;
wire wsi_S1_burstKind$EN;
// register wsi_S1_errorSticky
reg wsi_S1_errorSticky;
wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN;
// register wsi_S1_iMesgCount
reg [31 : 0] wsi_S1_iMesgCount;
wire [31 : 0] wsi_S1_iMesgCount$D_IN;
wire wsi_S1_iMesgCount$EN;
// register wsi_S1_isReset_isInReset
reg wsi_S1_isReset_isInReset;
wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN;
// register wsi_S1_mesgWordLength
reg [11 : 0] wsi_S1_mesgWordLength;
wire [11 : 0] wsi_S1_mesgWordLength$D_IN;
wire wsi_S1_mesgWordLength$EN;
// register wsi_S1_operateD
reg wsi_S1_operateD;
wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN;
// register wsi_S1_pMesgCount
reg [31 : 0] wsi_S1_pMesgCount;
wire [31 : 0] wsi_S1_pMesgCount$D_IN;
wire wsi_S1_pMesgCount$EN;
// register wsi_S1_peerIsReady
reg wsi_S1_peerIsReady;
wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN;
// register wsi_S1_reqFifo_countReg
reg [1 : 0] wsi_S1_reqFifo_countReg;
wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN;
wire wsi_S1_reqFifo_countReg$EN;
// register wsi_S1_reqFifo_levelsValid
reg wsi_S1_reqFifo_levelsValid;
wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN;
// register wsi_S1_statusR
reg [7 : 0] wsi_S1_statusR;
wire [7 : 0] wsi_S1_statusR$D_IN;
wire wsi_S1_statusR$EN;
// register wsi_S1_tBusyCount
reg [31 : 0] wsi_S1_tBusyCount;
wire [31 : 0] wsi_S1_tBusyCount$D_IN;
wire wsi_S1_tBusyCount$EN;
// register wsi_S1_trafficSticky
reg wsi_S1_trafficSticky;
wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN;
// register wsi_S1_wordCount
reg [11 : 0] wsi_S1_wordCount;
wire [11 : 0] wsi_S1_wordCount$D_IN;
wire wsi_S1_wordCount$EN;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsi_S0_reqFifo
wire [60 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT;
wire wsi_S0_reqFifo$CLR,
wsi_S0_reqFifo$DEQ,
wsi_S0_reqFifo$EMPTY_N,
wsi_S0_reqFifo$ENQ,
wsi_S0_reqFifo$FULL_N;
// ports of submodule wsi_S1_reqFifo
wire [60 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT;
wire wsi_S1_reqFifo$CLR,
wsi_S1_reqFifo$DEQ,
wsi_S1_reqFifo$EMPTY_N,
wsi_S1_reqFifo$ENQ,
wsi_S1_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_doMessageConsume_S0,
WILL_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_both,
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_deq,
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_both,
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_deq,
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr,
WILL_FIRE_RL_wsi_S0_reqFifo_enq,
WILL_FIRE_RL_wsi_S0_reqFifo_reset,
WILL_FIRE_RL_wsi_S1_reqFifo_enq,
WILL_FIRE_RL_wsi_S1_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [60 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__VAL_1,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017;
reg [31 : 0] _theResult____h16428;
wire [31 : 0] rdat__h16512,
rdat__h16701,
rdat__h16715,
rdat__h16723,
rdat__h16737,
rdat__h16745,
rdat__h16759,
rdat__h16767,
rdat__h16781;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd =
wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise =
!wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsi_M0_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo =
wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ;
// value method wsiM1_mCmd
assign wsiM1_MCmd =
wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[60:58] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[57] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise =
!wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[56] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[55:44] ;
// value method wsiM1_mData
assign wsiM1_MData = wsi_M1_reqFifo_q_0[43:12] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[11:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo =
wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ;
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsi_S0_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S0_reqFifo$D_IN),
.ENQ(wsi_S0_reqFifo$ENQ),
.DEQ(wsi_S0_reqFifo$DEQ),
.CLR(wsi_S0_reqFifo$CLR),
.D_OUT(wsi_S0_reqFifo$D_OUT),
.FULL_N(wsi_S0_reqFifo$FULL_N),
.EMPTY_N(wsi_S0_reqFifo$EMPTY_N));
// submodule wsi_S1_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S1_reqFifo$D_IN),
.ENQ(wsi_S1_reqFifo$ENQ),
.DEQ(wsi_S1_reqFifo$DEQ),
.CLR(wsi_S1_reqFifo$CLR),
.D_OUT(wsi_S1_reqFifo$D_OUT),
.FULL_N(wsi_S1_reqFifo$FULL_N),
.EMPTY_N(wsi_S1_reqFifo$EMPTY_N));
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_doMessageConsume_S0
assign WILL_FIRE_RL_doMessageConsume_S0 =
wsi_S0_reqFifo$EMPTY_N &&
(splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
// rule RL_doMessageConsume_S1
assign CAN_FIRE_RL_doMessageConsume_S1 =
wsi_S1_reqFifo$EMPTY_N &&
(!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_doMessageConsume_S1 =
CAN_FIRE_RL_doMessageConsume_S1 &&
!WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wsi_M0_reqFifo_deq
assign WILL_FIRE_RL_wsi_M0_reqFifo_deq =
wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ;
// rule RL_wsi_M0_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr =
((wsi_M0_reqFifo_c_r == 2'd0) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd1 ||
wsi_M0_reqFifo_enqueueing$whas) &&
wsi_M0_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
// rule RL_wsi_M0_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
!wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wsi_M0_reqFifo_both
assign WILL_FIRE_RL_wsi_M0_reqFifo_both =
((wsi_M0_reqFifo_c_r == 2'd1) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd2 ||
wsi_M0_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_deq
assign WILL_FIRE_RL_wsi_M1_reqFifo_deq =
wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ;
// rule RL_wsi_M1_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr =
((wsi_M1_reqFifo_c_r == 2'd0) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd1 ||
wsi_M1_reqFifo_enqueueing$whas) &&
wsi_M1_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
// rule RL_wsi_M1_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
!wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_both
assign WILL_FIRE_RL_wsi_M1_reqFifo_both =
((wsi_M1_reqFifo_c_r == 2'd1) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd2 ||
wsi_M1_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_S0_reqFifo_enq
assign WILL_FIRE_RL_wsi_S0_reqFifo_enq =
wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady &&
wsi_S0_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_wsi_S0_reqFifo_reset
assign WILL_FIRE_RL_wsi_S0_reqFifo_reset =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wsi_S1_reqFifo_enq
assign WILL_FIRE_RL_wsi_S1_reqFifo_enq =
wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady &&
wsi_S1_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_wsi_S1_reqFifo_reset
assign WILL_FIRE_RL_wsi_S1_reqFifo_reset =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S1 ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ;
assign MUX_wci_illegalEdge$write_1__VAL_1 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd1) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
wsi_M0_reqFifo_q_1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd2) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd1) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
wsi_M1_reqFifo_q_1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd2) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsi_S0_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsi_S0_wsiReq$whas = 1'd1 ;
assign wsi_S0_operateD_1$wget = 1'd1 ;
assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S0_peerIsReady_1$wget = 1'd1 ;
assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ;
assign wsi_S0_sThreadBusy_dw$whas =
wsi_S0_reqFifo_levelsValid && wsi_S0_operateD &&
wsi_S0_peerIsReady ;
assign wsi_S1_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsi_S1_wsiReq$whas = 1'd1 ;
assign wsi_S1_operateD_1$wget = 1'd1 ;
assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S1_peerIsReady_1$wget = 1'd1 ;
assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ;
assign wsi_S1_sThreadBusy_dw$whas =
wsi_S1_reqFifo_levelsValid && wsi_S1_operateD &&
wsi_S1_peerIsReady ;
assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ;
assign wsi_M0_operateD_1$wget = 1'd1 ;
assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M0_peerIsReady_1$wget = 1'd1 ;
assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ;
assign wsi_M1_operateD_1$wget = 1'd1 ;
assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M1_peerIsReady_1$wget = 1'd1 ;
assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es0_mCmd_w$whas = 1'd1 ;
assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es0_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es0_mData_w$wget = wsiS0_MData ;
assign wsi_Es0_mData_w$whas = 1'd1 ;
assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es0_mByteEn_w$whas = 1'd1 ;
assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es0_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es1_mCmd_w$whas = 1'd1 ;
assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es1_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es1_mData_w$wget = wsiS1_MData ;
assign wsi_Es1_mData_w$whas = 1'd1 ;
assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es1_mByteEn_w$whas = 1'd1 ;
assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es1_mReqInfo_w$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_M0_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] &&
!splitCtrl[7] ;
assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_M1_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] &&
!splitCtrl[15] ;
assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es0_mDataInfo_w$whas = 1'd1 ;
assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es1_mDataInfo_w$whas = 1'd1 ;
assign wsi_S0_extStatusW$wget =
{ wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ;
assign wsi_S1_extStatusW$wget =
{ wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ;
assign wsi_M0_extStatusW$wget =
{ wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ;
assign wsi_M1_extStatusW$wget =
{ wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ;
// register splitCtrl
assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign splitCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_1 ;
assign wci_illegalEdge$EN =
MUX_wci_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset$D_IN = 1'd0 ;
assign wci_isReset_isInReset$EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN =
(wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_incCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_0
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_burstKind
assign wsi_M0_burstKind$D_IN =
(wsi_M0_burstKind == 2'd0) ?
(wsi_M0_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M0_burstKind$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[60:58] == 3'd1 &&
(wsi_M0_burstKind == 2'd0 ||
(wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) &&
wsi_M0_reqFifo_q_0[57]) ;
// register wsi_M0_errorSticky
assign wsi_M0_errorSticky$D_IN = 1'b0 ;
assign wsi_M0_errorSticky$EN = 1'b0 ;
// register wsi_M0_iMesgCount
assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ;
assign wsi_M0_iMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[60:58] == 3'd1 &&
wsi_M0_burstKind == 2'd2 &&
wsi_M0_reqFifo_q_0[57] ;
// register wsi_M0_isReset_isInReset
assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ;
// register wsi_M0_operateD
assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M0_operateD$EN = 1'd1 ;
// register wsi_M0_pMesgCount
assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ;
assign wsi_M0_pMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[60:58] == 3'd1 &&
wsi_M0_burstKind == 2'd1 &&
wsi_M0_reqFifo_q_0[57] ;
// register wsi_M0_peerIsReady
assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsi_M0_peerIsReady$EN = 1'd1 ;
// register wsi_M0_reqFifo_c_r
assign wsi_M0_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ?
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M0_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1;
default: wsi_M0_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsi_M0_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_sThreadBusy_d
assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsi_M0_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_statusR
assign wsi_M0_statusR$D_IN =
{ wsi_M0_isReset_isInReset,
!wsi_M0_peerIsReady,
!wsi_M0_operateD,
wsi_M0_errorSticky,
wsi_M0_burstKind != 2'd0,
wsi_M0_sThreadBusy_d,
1'd0,
wsi_M0_trafficSticky } ;
assign wsi_M0_statusR$EN = 1'd1 ;
// register wsi_M0_tBusyCount
assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ;
assign wsi_M0_tBusyCount$EN =
wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ;
// register wsi_M0_trafficSticky
assign wsi_M0_trafficSticky$D_IN = 1'd1 ;
assign wsi_M0_trafficSticky$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[60:58] == 3'd1 ;
// register wsi_M1_burstKind
assign wsi_M1_burstKind$D_IN =
(wsi_M1_burstKind == 2'd0) ?
(wsi_M1_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M1_burstKind$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[60:58] == 3'd1 &&
(wsi_M1_burstKind == 2'd0 ||
(wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) &&
wsi_M1_reqFifo_q_0[57]) ;
// register wsi_M1_errorSticky
assign wsi_M1_errorSticky$D_IN = 1'b0 ;
assign wsi_M1_errorSticky$EN = 1'b0 ;
// register wsi_M1_iMesgCount
assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ;
assign wsi_M1_iMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[60:58] == 3'd1 &&
wsi_M1_burstKind == 2'd2 &&
wsi_M1_reqFifo_q_0[57] ;
// register wsi_M1_isReset_isInReset
assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ;
// register wsi_M1_operateD
assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M1_operateD$EN = 1'd1 ;
// register wsi_M1_pMesgCount
assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ;
assign wsi_M1_pMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[60:58] == 3'd1 &&
wsi_M1_burstKind == 2'd1 &&
wsi_M1_reqFifo_q_0[57] ;
// register wsi_M1_peerIsReady
assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsi_M1_peerIsReady$EN = 1'd1 ;
// register wsi_M1_reqFifo_c_r
assign wsi_M1_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ?
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M1_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1;
default: wsi_M1_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsi_M1_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_sThreadBusy_d
assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsi_M1_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M1_statusR
assign wsi_M1_statusR$D_IN =
{ wsi_M1_isReset_isInReset,
!wsi_M1_peerIsReady,
!wsi_M1_operateD,
wsi_M1_errorSticky,
wsi_M1_burstKind != 2'd0,
wsi_M1_sThreadBusy_d,
1'd0,
wsi_M1_trafficSticky } ;
assign wsi_M1_statusR$EN = 1'd1 ;
// register wsi_M1_tBusyCount
assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ;
assign wsi_M1_tBusyCount$EN =
wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ;
// register wsi_M1_trafficSticky
assign wsi_M1_trafficSticky$D_IN = 1'd1 ;
assign wsi_M1_trafficSticky$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[60:58] == 3'd1 ;
// register wsi_S0_burstKind
assign wsi_S0_burstKind$D_IN =
(wsi_S0_burstKind == 2'd0) ?
(wsi_S0_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S0_burstKind$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq &&
(wsi_S0_burstKind == 2'd0 ||
(wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) &&
wsi_S0_wsiReq$wget[57]) ;
// register wsi_S0_errorSticky
assign wsi_S0_errorSticky$D_IN = 1'b0 ;
assign wsi_S0_errorSticky$EN = 1'b0 ;
// register wsi_S0_iMesgCount
assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ;
assign wsi_S0_iMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 &&
wsi_S0_wsiReq$wget[57] ;
// register wsi_S0_isReset_isInReset
assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ;
// register wsi_S0_mesgWordLength
assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ;
assign wsi_S0_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[57] ;
// register wsi_S0_operateD
assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S0_operateD$EN = 1'd1 ;
// register wsi_S0_pMesgCount
assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ;
assign wsi_S0_pMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 &&
wsi_S0_wsiReq$wget[57] ;
// register wsi_S0_peerIsReady
assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsi_S0_peerIsReady$EN = 1'd1 ;
// register wsi_S0_reqFifo_countReg
assign wsi_S0_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ?
wsi_S0_reqFifo_countReg + 2'd1 :
wsi_S0_reqFifo_countReg - 2'd1 ;
assign wsi_S0_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S0 ;
// register wsi_S0_reqFifo_levelsValid
assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
assign wsi_S0_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S0 ||
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
// register wsi_S0_statusR
assign wsi_S0_statusR$D_IN =
{ wsi_S0_isReset_isInReset,
!wsi_S0_peerIsReady,
!wsi_S0_operateD,
wsi_S0_errorSticky,
wsi_S0_burstKind != 2'd0,
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget,
1'd0,
wsi_S0_trafficSticky } ;
assign wsi_S0_statusR$EN = 1'd1 ;
// register wsi_S0_tBusyCount
assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ;
assign wsi_S0_tBusyCount$EN =
wsi_S0_operateD && wsi_S0_peerIsReady &&
(!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ;
// register wsi_S0_trafficSticky
assign wsi_S0_trafficSticky$D_IN = 1'd1 ;
assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S0_wordCount
assign wsi_S0_wordCount$D_IN =
wsi_S0_wsiReq$wget[57] ? 12'd1 : wsi_S0_wordCount + 12'd1 ;
assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S1_burstKind
assign wsi_S1_burstKind$D_IN =
(wsi_S1_burstKind == 2'd0) ?
(wsi_S1_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S1_burstKind$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq &&
(wsi_S1_burstKind == 2'd0 ||
(wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) &&
wsi_S1_wsiReq$wget[57]) ;
// register wsi_S1_errorSticky
assign wsi_S1_errorSticky$D_IN = 1'b0 ;
assign wsi_S1_errorSticky$EN = 1'b0 ;
// register wsi_S1_iMesgCount
assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ;
assign wsi_S1_iMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 &&
wsi_S1_wsiReq$wget[57] ;
// register wsi_S1_isReset_isInReset
assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ;
// register wsi_S1_mesgWordLength
assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ;
assign wsi_S1_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[57] ;
// register wsi_S1_operateD
assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S1_operateD$EN = 1'd1 ;
// register wsi_S1_pMesgCount
assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ;
assign wsi_S1_pMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 &&
wsi_S1_wsiReq$wget[57] ;
// register wsi_S1_peerIsReady
assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsi_S1_peerIsReady$EN = 1'd1 ;
// register wsi_S1_reqFifo_countReg
assign wsi_S1_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ?
wsi_S1_reqFifo_countReg + 2'd1 :
wsi_S1_reqFifo_countReg - 2'd1 ;
assign wsi_S1_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S1 ;
// register wsi_S1_reqFifo_levelsValid
assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
assign wsi_S1_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S1 ||
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
// register wsi_S1_statusR
assign wsi_S1_statusR$D_IN =
{ wsi_S1_isReset_isInReset,
!wsi_S1_peerIsReady,
!wsi_S1_operateD,
wsi_S1_errorSticky,
wsi_S1_burstKind != 2'd0,
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget,
1'd0,
wsi_S1_trafficSticky } ;
assign wsi_S1_statusR$EN = 1'd1 ;
// register wsi_S1_tBusyCount
assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ;
assign wsi_S1_tBusyCount$EN =
wsi_S1_operateD && wsi_S1_peerIsReady &&
(!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ;
// register wsi_S1_trafficSticky
assign wsi_S1_trafficSticky$D_IN = 1'd1 ;
assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// register wsi_S1_wordCount
assign wsi_S1_wordCount$D_IN =
wsi_S1_wsiReq$wget[57] ? 12'd1 : wsi_S1_wordCount + 12'd1 ;
assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsi_S0_reqFifo
assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ;
assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo$CLR = 1'b0 ;
// submodule wsi_S1_reqFifo
assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ;
assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign rdat__h16512 =
hasDebugLogic ?
{ wsi_S0_statusR,
wsi_S1_statusR,
wsi_M0_statusR,
wsi_M1_statusR } :
32'd0 ;
assign rdat__h16701 =
hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16715 =
hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16723 =
hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16737 =
hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16745 =
hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16759 =
hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16767 =
hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16781 =
hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ;
always@(wci_reqF$D_OUT or
splitCtrl or
rdat__h16512 or
rdat__h16701 or
rdat__h16715 or
rdat__h16723 or
rdat__h16737 or
rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781)
begin
case (wci_reqF$D_OUT[39:32])
8'h04: _theResult____h16428 = splitCtrl;
8'h1C: _theResult____h16428 = rdat__h16512;
8'h20: _theResult____h16428 = rdat__h16701;
8'h24: _theResult____h16428 = rdat__h16715;
8'h28: _theResult____h16428 = rdat__h16723;
8'h2C: _theResult____h16428 = rdat__h16737;
8'h30: _theResult____h16428 = rdat__h16745;
8'h34: _theResult____h16428 = rdat__h16759;
8'h38: _theResult____h16428 = rdat__h16767;
8'h3C: _theResult____h16428 = rdat__h16781;
default: _theResult____h16428 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsi_M0_burstKind$EN)
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN;
if (wsi_M0_errorSticky$EN)
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN;
if (wsi_M0_iMesgCount$EN)
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN;
if (wsi_M0_operateD$EN)
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN;
if (wsi_M0_pMesgCount$EN)
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN;
if (wsi_M0_peerIsReady$EN)
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN;
if (wsi_M0_reqFifo_c_r$EN)
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN;
if (wsi_M0_reqFifo_q_0$EN)
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN;
if (wsi_M0_reqFifo_q_1$EN)
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN;
if (wsi_M0_sThreadBusy_d$EN)
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M0_sThreadBusy_d$D_IN;
if (wsi_M0_tBusyCount$EN)
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN;
if (wsi_M0_trafficSticky$EN)
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M0_trafficSticky$D_IN;
if (wsi_M1_burstKind$EN)
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN;
if (wsi_M1_errorSticky$EN)
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN;
if (wsi_M1_iMesgCount$EN)
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN;
if (wsi_M1_operateD$EN)
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN;
if (wsi_M1_pMesgCount$EN)
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN;
if (wsi_M1_peerIsReady$EN)
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN;
if (wsi_M1_reqFifo_c_r$EN)
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN;
if (wsi_M1_reqFifo_q_0$EN)
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN;
if (wsi_M1_reqFifo_q_1$EN)
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN;
if (wsi_M1_sThreadBusy_d$EN)
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M1_sThreadBusy_d$D_IN;
if (wsi_M1_tBusyCount$EN)
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN;
if (wsi_M1_trafficSticky$EN)
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M1_trafficSticky$D_IN;
if (wsi_S0_burstKind$EN)
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN;
if (wsi_S0_errorSticky$EN)
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN;
if (wsi_S0_iMesgCount$EN)
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN;
if (wsi_S0_operateD$EN)
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN;
if (wsi_S0_pMesgCount$EN)
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN;
if (wsi_S0_peerIsReady$EN)
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN;
if (wsi_S0_reqFifo_countReg$EN)
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_countReg$D_IN;
if (wsi_S0_reqFifo_levelsValid$EN)
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_levelsValid$D_IN;
if (wsi_S0_tBusyCount$EN)
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN;
if (wsi_S0_trafficSticky$EN)
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S0_trafficSticky$D_IN;
if (wsi_S0_wordCount$EN)
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN;
if (wsi_S1_burstKind$EN)
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN;
if (wsi_S1_errorSticky$EN)
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN;
if (wsi_S1_iMesgCount$EN)
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN;
if (wsi_S1_operateD$EN)
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN;
if (wsi_S1_pMesgCount$EN)
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN;
if (wsi_S1_peerIsReady$EN)
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN;
if (wsi_S1_reqFifo_countReg$EN)
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_countReg$D_IN;
if (wsi_S1_reqFifo_levelsValid$EN)
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_levelsValid$D_IN;
if (wsi_S1_tBusyCount$EN)
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN;
if (wsi_S1_trafficSticky$EN)
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S1_trafficSticky$D_IN;
if (wsi_S1_wordCount$EN)
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN;
end
if (wsi_M0_statusR$EN)
wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN;
if (wsi_M1_statusR$EN)
wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN;
if (wsi_S0_mesgWordLength$EN)
wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S0_mesgWordLength$D_IN;
if (wsi_S0_statusR$EN)
wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN;
if (wsi_S1_mesgWordLength$EN)
wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S1_mesgWordLength$D_IN;
if (wsi_S1_statusR$EN)
wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset$EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset$D_IN;
if (wsi_M0_isReset_isInReset$EN)
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M0_isReset_isInReset$D_IN;
if (wsi_M1_isReset_isInReset$EN)
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M1_isReset_isInReset$D_IN;
if (wsi_S0_isReset_isInReset$EN)
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S0_isReset_isInReset$D_IN;
if (wsi_S1_isReset_isInReset$EN)
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S1_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
splitCtrl = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsi_M0_burstKind = 2'h2;
wsi_M0_errorSticky = 1'h0;
wsi_M0_iMesgCount = 32'hAAAAAAAA;
wsi_M0_isReset_isInReset = 1'h0;
wsi_M0_operateD = 1'h0;
wsi_M0_pMesgCount = 32'hAAAAAAAA;
wsi_M0_peerIsReady = 1'h0;
wsi_M0_reqFifo_c_r = 2'h2;
wsi_M0_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsi_M0_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsi_M0_sThreadBusy_d = 1'h0;
wsi_M0_statusR = 8'hAA;
wsi_M0_tBusyCount = 32'hAAAAAAAA;
wsi_M0_trafficSticky = 1'h0;
wsi_M1_burstKind = 2'h2;
wsi_M1_errorSticky = 1'h0;
wsi_M1_iMesgCount = 32'hAAAAAAAA;
wsi_M1_isReset_isInReset = 1'h0;
wsi_M1_operateD = 1'h0;
wsi_M1_pMesgCount = 32'hAAAAAAAA;
wsi_M1_peerIsReady = 1'h0;
wsi_M1_reqFifo_c_r = 2'h2;
wsi_M1_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsi_M1_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsi_M1_sThreadBusy_d = 1'h0;
wsi_M1_statusR = 8'hAA;
wsi_M1_tBusyCount = 32'hAAAAAAAA;
wsi_M1_trafficSticky = 1'h0;
wsi_S0_burstKind = 2'h2;
wsi_S0_errorSticky = 1'h0;
wsi_S0_iMesgCount = 32'hAAAAAAAA;
wsi_S0_isReset_isInReset = 1'h0;
wsi_S0_mesgWordLength = 12'hAAA;
wsi_S0_operateD = 1'h0;
wsi_S0_pMesgCount = 32'hAAAAAAAA;
wsi_S0_peerIsReady = 1'h0;
wsi_S0_reqFifo_countReg = 2'h2;
wsi_S0_reqFifo_levelsValid = 1'h0;
wsi_S0_statusR = 8'hAA;
wsi_S0_tBusyCount = 32'hAAAAAAAA;
wsi_S0_trafficSticky = 1'h0;
wsi_S0_wordCount = 12'hAAA;
wsi_S1_burstKind = 2'h2;
wsi_S1_errorSticky = 1'h0;
wsi_S1_iMesgCount = 32'hAAAAAAAA;
wsi_S1_isReset_isInReset = 1'h0;
wsi_S1_mesgWordLength = 12'hAAA;
wsi_S1_operateD = 1'h0;
wsi_S1_pMesgCount = 32'hAAAAAAAA;
wsi_S1_peerIsReady = 1'h0;
wsi_S1_reqFifo_countReg = 2'h2;
wsi_S1_reqFifo_levelsValid = 1'h0;
wsi_S1_statusR = 8'hAA;
wsi_S1_tBusyCount = 32'hAAAAAAAA;
wsi_S1_trafficSticky = 1'h0;
wsi_S1_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3698 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3698,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h16289 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h16289,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
wci_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h4017 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4017,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h3873 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3873,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h16444 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h16444,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
_theResult____h16428);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkWsiSplitter2x24B
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: async_fifo_512x36_to_72_progfull_500.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module async_fifo_512x36_to_72_progfull_500 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [71:0] q;
output rdempty;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "36"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "72"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: STEUERUNG.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// STEUERUNG The control logic of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module STEUERUNG( BCLK, BRESET, DC_ACC_DONE, ACB_ZERO, DONE, INT_N, NMI_N, DC_ABORT, IC_INIT, DC_INIT, SAVE_PC, CFG,
IACC_STAT, PROT_ERROR, IC_DIN, PC_NEW, PSR, STRING, TRAPS, IC_READ, DATA_HOLD, LD_DIN, LD_IMME,
WREN, WR_REG, GENSTAT, ILO, COP_OP, IC_USER, ACC_FELD, DISP, IC_TEX, IMME_Q, INFO_AU, LD_OUT,
DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, WRADR, RWVAL, Y_INIT,
ENA_HK, STOP_CINV );
input BCLK;
input BRESET;
input DC_ACC_DONE;
input ACB_ZERO;
input DONE;
input INT_N;
input NMI_N;
input DC_ABORT;
input IC_INIT;
input DC_INIT;
input SAVE_PC;
input Y_INIT;
input [8:0] CFG;
input [3:0] IACC_STAT;
input PROT_ERROR;
input [31:0] IC_DIN;
input [31:0] PC_NEW;
input [11:0] PSR;
input [4:0] STRING;
input [5:0] TRAPS;
input STOP_CINV;
output IC_READ;
output DATA_HOLD;
output LD_DIN;
output LD_IMME;
output WREN;
output WR_REG;
output [2:0] GENSTAT;
output IC_USER;
output [14:0] ACC_FELD;
output [31:0] DISP;
output [2:0] IC_TEX;
output [31:0] IMME_Q;
output [6:0] INFO_AU;
output [1:0] LD_OUT;
output [12:0] DETOIP;
output [1:0] MMU_UPDATE;
output [10:0] OPER;
output [31:0] PC_ARCHI;
output [31:0] PC_ICACHE;
output [7:0] RDAA;
output [7:0] RDAB;
output [1:0] START;
output [1:0] WMASKE;
output [5:0] WRADR;
output [2:0] RWVAL;
output ENA_HK;
output ILO;
output [23:0] COP_OP;
wire [55:0] OPREG;
wire IC_ABORT;
wire INIT_DONE;
wire UNDEF;
wire ILLEGAL;
wire [2:0] ANZ_VAL;
wire [31:0] PC_SAVE;
wire NEW;
wire RESTART;
wire STOP_IC;
wire [1:0] ALSB;
wire [2:0] USED;
wire NEXT_ADR;
wire NEW_PC;
wire NEXT_PCA;
wire LOAD_PC;
wire [31:0] DISP_BR;
DECODER BEFEHLS_DEC(
.BCLK(BCLK),
.BRESET(BRESET),
.ACC_DONE(DC_ACC_DONE),
.ACB_ZERO(ACB_ZERO),
.DONE(DONE),
.NMI_N(NMI_N),
.INT_N(INT_N),
.DC_ABORT(DC_ABORT),
.IC_ABORT(IC_ABORT),
.INIT_DONE(INIT_DONE),
.UNDEF(UNDEF),
.ILL(ILLEGAL),
.IC_READ(IC_READ),
.ANZ_VAL(ANZ_VAL),
.CFG(CFG),
.OPREG(OPREG),
.PC_SAVE(PC_SAVE),
.PSR(PSR),
.STRING(STRING),
.TRAPS(TRAPS),
.NEW(NEW),
.WREN(WREN),
.LD_DIN(LD_DIN),
.LD_IMME(LD_IMME),
.NEXT_PCA(NEXT_PCA),
.WR_REG(WR_REG),
.LOAD_PC(LOAD_PC),
.GENSTAT(GENSTAT),
.RESTART(RESTART),
.STOP_IC(STOP_IC),
.ACC_FELD(ACC_FELD),
.DISP(DISP),
.DISP_BR(DISP_BR),
.IMME_Q(IMME_Q),
.INFO_AU(INFO_AU),
.LD_OUT(LD_OUT),
.DETOIP(DETOIP),
.MMU_UPDATE(MMU_UPDATE),
.OPER(OPER),
.RDAA(RDAA),
.RDAB(RDAB),
.START(START),
.USED(USED),
.WMASKE(WMASKE),
.WRADR(WRADR),
.RWVAL(RWVAL),
.ENA_HK(ENA_HK),
.ILO(ILO),
.COP_OP(COP_OP),
.STOP_CINV(STOP_CINV) );
ILL_UNDEF CHECKER(
.USER(PSR[8]),
.ANZ_VAL(ANZ_VAL),
.CFG(CFG[3:1]),
.OPREG(OPREG[23:0]),
.ILL(ILLEGAL),
.UNDEF(UNDEF));
OPDEC_REG OPC_REG(
.BCLK(BCLK),
.BRESET(BRESET),
.NEW(NEW),
.DC_INIT(DC_INIT),
.IC_INIT(IC_INIT),
.Y_INIT(Y_INIT),
.RESTART(RESTART),
.STOP_IC(STOP_IC),
.ACC_STAT(IACC_STAT),
.PROT_ERROR(PROT_ERROR),
.ALSB(ALSB),
.IC_DIN(IC_DIN),
.USED(USED),
.IC_READ(IC_READ),
.NEXT_ADR(NEXT_ADR),
.DATA_HOLD(DATA_HOLD),
.NEW_PC(NEW_PC),
.ABORT(IC_ABORT),
.INIT_DONE(INIT_DONE),
.ANZ_VAL(ANZ_VAL),
.IC_TEX(IC_TEX),
.OPREG(OPREG));
PROG_COUNTER PCS(
.BCLK(BCLK),
.BRESET(BRESET),
.NEXT_ADR(NEXT_ADR),
.NEW_PC(NEW_PC),
.NEXT_PCA(NEXT_PCA),
.NEW(NEW),
.LOAD_PC(LOAD_PC),
.USER(PSR[8]),
.SAVE_PC(SAVE_PC),
.FPU_TRAP(TRAPS[0]),
.ADIVAR(INFO_AU[3]),
.DISP(DISP_BR),
.PC_NEW(PC_NEW),
.USED(USED),
.IC_USER(IC_USER),
.ALSB(ALSB),
.PC_ARCHI(PC_ARCHI),
.PC_ICACHE(PC_ICACHE),
.PC_SAVE(PC_SAVE));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 12:45:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_xlconstant_0_3 -prefix
// system_xlconstant_0_3_ system_xlconstant_0_3_stub.v
// Design : system_xlconstant_0_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_3(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[9:0]" */;
output [9:0]dout;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_SWITCH.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:41 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_SWITCH (
input IN_0,
input IN_1,
input SW ,
output OUT
);
assign OUT=SW?IN_1:IN_0;
endmodule
|
// Debounces a button. The "changed" output is true for the first clock
// of the new value of "debounced_button". Takes 42 ms to settle.
module Debouncer #(parameter DEFAULT_VALUE=1'b0)
(
input wire clock,
input wire reset_n,
input wire button,
output reg debounced_button,
output reg changed
);
// 2**21 * 20 ns = 42 ms.
localparam N = 21;
reg [N-1:0] counter;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
debounced_button <= DEFAULT_VALUE;
counter <= 1'b0;
changed <= 1'b0;
end else begin
changed <= 1'b0;
if (button == debounced_button) begin
// Keep resetting our counter.
counter <= {N{1'b1}};
end else begin
if (counter == 0) begin
// We've made it through the wait period, change
// our value.
debounced_button <= button;
counter <= {N{1'b1}};
changed <= 1'b1;
end else begin
// Count down.
counter <= counter - 1'b1;
end
end
end
end
endmodule
|
`timescale 1 ns / 100 ps
module ringbuffer_tb ();
reg write_clock_enable;
reg read_clock_enable;
reg clock;
reg reset;
reg [1:0] write_data;
wire [1:0] read_data;
wire empty;
wire overflow;
ringbuffer #(.AW(2), .DW(2))
RINGBUFFER (
.reset(reset),
.clock(clock),
.read_data(read_data),
.read_clock_enable(read_clock_enable),
.write_data(write_data),
.write_clock_enable(write_clock_enable),
.empty(empty),
.overflow(overflow));
always
#1 clock = ~clock;
initial begin
$dumpfile ("ringbuffer_tb.vcd");
$dumpvars (0, ringbuffer_tb);
clock = 0;
write_clock_enable = 0;
read_clock_enable = 0;
reset = 0;
write_data = 2'b11;
#6;
reset = 1;
#6
if (read_data != 0) begin
$display("After reset read_data != 0");
$stop;
end
if (~empty) begin
$display("Ringbuffer is not empty after reset");
$stop;
end
if (overflow) begin
$display("Ringbuffer is overflowed after reset");
$stop;
end
// try to read even if the buffer is empty
#1;
read_clock_enable = 1;
#2;
read_clock_enable = 0;
#1;
if (read_data != 0) begin
$display("read_data increase even the ringbuffer is empty and a malicious read_clock_enable was triggered");
$stop;
end
// check write, read, write, write, write,read, read, write, read, read
#1;
write_clock_enable = 1;
#2;
write_clock_enable = 0;
#1;
if (empty || overflow) begin
$display("buffer should not empty nor overflowed");
$stop;
end
#2;
read_clock_enable = 1;
#2;
if (~empty) begin
$display("buffer is empty, but not signaling emptyness");
$stop;
end
if (read_data != 2'b11) begin
$display("read_data doesn\'t increase after read");
$stop;
end
#2;
read_clock_enable = 0;
#2;
// ringbuffer is now empty again, read_data & write_data should show = 1
#2;
write_clock_enable = 1;
#2;
write_clock_enable = 0;
#2;
write_clock_enable = 1;
#2;
write_clock_enable = 0;
#2;
// buffer should be full
write_clock_enable = 1;
#2;
write_clock_enable = 0;
if (~overflow) begin
$display("overflow not signaled even it\'s full");
$stop;
end
#2;
read_clock_enable = 1;
#2;
read_clock_enable = 0;
if (overflow) begin
$display("overflow should *NOT* signaled anymore");
$stop;
end
#2;
read_clock_enable = 1;
#2;
read_clock_enable = 0;
#2;
read_clock_enable = 1;
#2;
read_clock_enable = 0;
#2;
read_clock_enable = 1;
#2;
read_clock_enable = 0;
if (~empty) begin
$display("buffer should empty, but it doesn\'t signaling this");
$stop;
end
#2;
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// readWriteSDBlock.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or
//// READ_SD_BLOCK, then write or read a 512 byte block
//// of SD memory
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
module readWriteSDBlock (blockAddr, checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, readError, readWriteSDBlockRdy, readWriteSDBlockReq, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, rxFifoData, rxFifoWen, sendCmdRdy, sendCmdReq, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen, txFifoData, txFifoRen, writeError);
parameter SDCARD_CLOCK = 16000000;
input [31:0]blockAddr;
input clk;
input [1:0]readWriteSDBlockReq;
input [7:0]respByte;
input respTout;
input rst;
input [7:0]rxDataIn;
input rxDataRdy;
input sendCmdRdy;
input txDataEmpty;
input txDataFull;
input [7:0]txFifoData;
output [7:0]checkSumByte;
output [7:0]cmdByte;
output [7:0]dataByte1;
output [7:0]dataByte2;
output [7:0]dataByte3;
output [7:0]dataByte4;
output [1:0]readError;
output readWriteSDBlockRdy;
output rxDataRdyClr;
output [7:0]rxFifoData;
output rxFifoWen;
output sendCmdReq;
output spiCS_n;
output [7:0]txDataOut;
output txDataWen;
output txFifoRen;
output [1:0]writeError;
wire [31:0]blockAddr;
reg [7:0]checkSumByte, next_checkSumByte;
wire clk;
reg [7:0]cmdByte, next_cmdByte;
reg [7:0]dataByte1, next_dataByte1;
reg [7:0]dataByte2, next_dataByte2;
reg [7:0]dataByte3, next_dataByte3;
reg [7:0]dataByte4, next_dataByte4;
reg [1:0]readError, next_readError;
reg readWriteSDBlockRdy, next_readWriteSDBlockRdy;
wire [1:0]readWriteSDBlockReq;
wire [7:0]respByte;
wire respTout;
wire rst;
wire [7:0]rxDataIn;
wire rxDataRdy;
reg rxDataRdyClr, next_rxDataRdyClr;
reg [7:0]rxFifoData, next_rxFifoData;
reg rxFifoWen, next_rxFifoWen;
wire sendCmdRdy;
reg sendCmdReq, next_sendCmdReq;
reg spiCS_n, next_spiCS_n;
wire txDataEmpty;
wire txDataFull;
reg [7:0]txDataOut, next_txDataOut;
reg txDataWen, next_txDataWen;
wire [7:0]txFifoData;
reg txFifoRen, next_txFifoRen;
reg [1:0]writeError, next_writeError;
// diagram signals declarations
reg [7:0]delCnt1, next_delCnt1;
reg [7:0]delCnt2, next_delCnt2;
reg [7:0]locRespByte, next_locRespByte;
reg [8:0]loopCnt, next_loopCnt;
reg [11:0]timeOutCnt, next_timeOutCnt;
// BINARY ENCODED state machine: rwBlkSt
// State codes definitions:
`define ST_RW_SD 6'b000000
`define WR_CMD_SEND_CMD 6'b000001
`define WR_CMD_WT_FIN 6'b000010
`define WR_CMD_DEL 6'b000011
`define WT_REQ 6'b000100
`define WR_TOKEN_FF1_FIN 6'b000101
`define WR_TOKEN_FF1_ST 6'b000110
`define WR_TOKEN_FF2_FIN 6'b000111
`define WR_TOKEN_FF2_ST 6'b001000
`define WR_TOKEN_FE_FIN 6'b001001
`define WR_TOKEN_FE_ST 6'b001010
`define WR_DATA_D_FIN 6'b001011
`define WR_DATA_D_ST 6'b001100
`define WR_DATA_RD_FIFO1 6'b001101
`define WR_DATA_RD_FIFO2 6'b001110
`define WR_DATA_LOOP_INIT 6'b001111
`define WR_DATA_CS_ST1 6'b010000
`define WR_DATA_CS_FIN1 6'b010001
`define WR_DATA_CS_FIN2 6'b010010
`define WR_DATA_CS_ST2 6'b010011
`define WR_DATA_CHK_RESP 6'b010100
`define WR_DATA_REQ_RESP_ST 6'b010101
`define WR_DATA_REQ_RESP_FIN 6'b010110
`define RD_CMD_SEND_CMD 6'b010111
`define RD_CMD_WT_FIN 6'b011000
`define RD_CMD_DEL 6'b011001
`define RD_TOKEN_CHK_LOOP 6'b011010
`define RD_TOKEN_WT_FIN 6'b011011
`define RD_TOKEN_SEND_CMD 6'b011100
`define RD_TOKEN_DEL2 6'b011101
`define RD_TOKEN_INIT_LOOP 6'b011110
`define RD_TOKEN_DEL1 6'b011111
`define RD_DATA_ST_LOOP 6'b100000
`define RD_DATA_WT_DATA 6'b100001
`define RD_DATA_CHK_LOOP 6'b100010
`define RD_DATA_CLR_RX 6'b100011
`define RD_DATA_CS_FIN2 6'b100100
`define RD_DATA_CS_FIN1 6'b100101
`define RD_DATA_CS_ST1 6'b100110
`define RD_DATA_CS_ST2 6'b100111
`define WR_BUSY_CHK_FIN 6'b101000
`define WR_BUSY_WT_FIN1 6'b101001
`define WR_BUSY_DEL1 6'b101010
`define WR_BUSY_SEND_CMD1 6'b101011
`define WR_BUSY_DEL2 6'b101100
`define WR_BUSY_INIT_LOOP 6'b101101
`define RD_TOKEN_DEL3 6'b101110
`define WR_DATA_DEL 6'b101111
reg [5:0]CurrState_rwBlkSt, NextState_rwBlkSt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: rwBlkSt
// NextState logic (combinatorial)
always @ (blockAddr or sendCmdRdy or respTout or respByte or readWriteSDBlockReq or txDataFull or loopCnt or txFifoData or txDataEmpty or timeOutCnt or locRespByte or rxDataRdy or rxDataIn or delCnt1 or delCnt2 or readWriteSDBlockRdy or spiCS_n or readError or writeError or txDataOut or txDataWen or rxDataRdyClr or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or txFifoRen or rxFifoWen or rxFifoData or CurrState_rwBlkSt)
begin
NextState_rwBlkSt <= CurrState_rwBlkSt;
// Set default values for outputs and signals
next_readWriteSDBlockRdy <= readWriteSDBlockRdy;
next_spiCS_n <= spiCS_n;
next_readError <= readError;
next_writeError <= writeError;
next_txDataOut <= txDataOut;
next_txDataWen <= txDataWen;
next_rxDataRdyClr <= rxDataRdyClr;
next_cmdByte <= cmdByte;
next_dataByte1 <= dataByte1;
next_dataByte2 <= dataByte2;
next_dataByte3 <= dataByte3;
next_dataByte4 <= dataByte4;
next_checkSumByte <= checkSumByte;
next_sendCmdReq <= sendCmdReq;
next_loopCnt <= loopCnt;
next_delCnt1 <= delCnt1;
next_delCnt2 <= delCnt2;
next_txFifoRen <= txFifoRen;
next_rxFifoWen <= rxFifoWen;
next_rxFifoData <= rxFifoData;
next_timeOutCnt <= timeOutCnt;
next_locRespByte <= locRespByte;
case (CurrState_rwBlkSt) // synopsys parallel_case full_case
`ST_RW_SD:
begin
next_readWriteSDBlockRdy <= 1'b0;
next_spiCS_n <= 1'b1;
next_readError <= 1'b0;
next_writeError <= 1'b0;
next_txDataOut <= 8'h00;
next_txDataWen <= 1'b0;
next_rxDataRdyClr <= 1'b0;
next_cmdByte <= 8'h00;
next_dataByte1 <= 8'h00;
next_dataByte2 <= 8'h00;
next_dataByte3 <= 8'h00;
next_dataByte4 <= 8'h00;
next_checkSumByte <= 8'h00;
next_sendCmdReq <= 1'b0;
next_loopCnt <= 8'h00;
next_delCnt1 <= 8'h00;
next_delCnt2 <= 8'h00;
next_readError <= `READ_NO_ERROR;
next_writeError <= `WRITE_NO_ERROR;
next_txFifoRen <= 1'b0;
next_rxFifoWen <= 1'b0;
next_rxFifoData <= 8'h00;
next_timeOutCnt <= 12'h000;
next_locRespByte <= 8'h00;
NextState_rwBlkSt <= `WT_REQ;
end
`WT_REQ:
begin
next_spiCS_n <= 1'b1;
next_readWriteSDBlockRdy <= 1'b1;
next_cmdByte <= 8'h00;
next_dataByte1 <= 8'h00;
next_dataByte2 <= 8'h00;
next_dataByte3 <= 8'h00;
next_dataByte4 <= 8'h00;
next_checkSumByte <= 8'h00;
if (readWriteSDBlockReq == `READ_SD_BLOCK)
begin
NextState_rwBlkSt <= `RD_CMD_SEND_CMD;
next_spiCS_n <= 1'b0;
next_readWriteSDBlockRdy <= 1'b0;
next_readError <= `READ_NO_ERROR;
end
else if (readWriteSDBlockReq == `WRITE_SD_BLOCK)
begin
NextState_rwBlkSt <= `WR_CMD_SEND_CMD;
next_spiCS_n <= 1'b0;
next_readWriteSDBlockRdy <= 1'b0;
next_writeError <= `WRITE_NO_ERROR;
end
end
`WR_CMD_SEND_CMD:
begin
next_cmdByte <= 8'h58;
//CMD24 Block Write
next_dataByte1 <= blockAddr[31:24];
next_dataByte2 <= blockAddr[23:16];
next_dataByte3 <= blockAddr[15:8];
next_dataByte4 <= blockAddr[7:0];
next_checkSumByte <= 8'hff;
next_sendCmdReq <= 1'b1;
NextState_rwBlkSt <= `WR_CMD_DEL;
end
`WR_CMD_WT_FIN:
begin
if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00))
begin
NextState_rwBlkSt <= `WT_REQ;
next_writeError <= `WRITE_CMD_ERROR;
end
else if (sendCmdRdy == 1'b1)
begin
NextState_rwBlkSt <= `WR_TOKEN_FF1_ST;
end
end
`WR_CMD_DEL:
begin
next_sendCmdReq <= 1'b0;
NextState_rwBlkSt <= `WR_CMD_WT_FIN;
end
`WR_TOKEN_FF1_FIN:
begin
next_txDataWen <= 1'b0;
NextState_rwBlkSt <= `WR_TOKEN_FF2_ST;
end
`WR_TOKEN_FF1_ST:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_TOKEN_FF1_FIN;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`WR_TOKEN_FF2_FIN:
begin
next_txDataWen <= 1'b0;
NextState_rwBlkSt <= `WR_TOKEN_FE_ST;
end
`WR_TOKEN_FF2_ST:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_TOKEN_FF2_FIN;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`WR_TOKEN_FE_FIN:
begin
next_txDataWen <= 1'b0;
NextState_rwBlkSt <= `WR_DATA_LOOP_INIT;
end
`WR_TOKEN_FE_ST:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_TOKEN_FE_FIN;
next_txDataOut <= 8'hfe;
next_txDataWen <= 1'b1;
end
end
`WR_BUSY_CHK_FIN:
begin
if (locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS)
begin
NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
next_timeOutCnt <= timeOutCnt + 1'b1;
end
else if (timeOutCnt == `TWO_FIFTY_MS)
begin
NextState_rwBlkSt <= `WT_REQ;
next_writeError <= `WRITE_BUSY_ERROR;
end
else
begin
NextState_rwBlkSt <= `WT_REQ;
end
end
`WR_BUSY_WT_FIN1:
begin
if (rxDataRdy == 1'b1)
begin
NextState_rwBlkSt <= `WR_BUSY_CHK_FIN;
next_locRespByte <= rxDataIn;
end
end
`WR_BUSY_DEL1:
begin
next_txDataWen <= 1'b0;
next_rxDataRdyClr <= 1'b0;
next_delCnt1 <= delCnt1 + 1'b1;
next_delCnt2 <= 8'h00;
if (delCnt1 == `MAX_8_BIT)
begin
NextState_rwBlkSt <= `WR_BUSY_WT_FIN1;
end
else
begin
NextState_rwBlkSt <= `WR_BUSY_DEL2;
end
end
`WR_BUSY_SEND_CMD1:
begin
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
next_rxDataRdyClr <= 1'b1;
next_delCnt1 <= 8'h00;
NextState_rwBlkSt <= `WR_BUSY_DEL1;
end
`WR_BUSY_DEL2:
begin
next_delCnt2 <= delCnt2 + 1'b1;
if (delCnt2 == 8'hff)
begin
NextState_rwBlkSt <= `WR_BUSY_DEL1;
end
end
`WR_BUSY_INIT_LOOP:
begin
next_timeOutCnt <= 12'h000;
NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
end
`RD_CMD_SEND_CMD:
begin
next_cmdByte <= 8'h51;
//CMD17 Block Read
next_dataByte1 <= blockAddr[31:24];
next_dataByte2 <= blockAddr[23:16];
next_dataByte3 <= blockAddr[15:8];
next_dataByte4 <= blockAddr[7:0];
next_checkSumByte <= 8'hff;
next_sendCmdReq <= 1'b1;
NextState_rwBlkSt <= `RD_CMD_DEL;
end
`RD_CMD_WT_FIN:
begin
if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00))
begin
NextState_rwBlkSt <= `WT_REQ;
next_readError <= `READ_CMD_ERROR;
end
else if (sendCmdRdy == 1'b1)
begin
NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP;
end
end
`RD_CMD_DEL:
begin
next_sendCmdReq <= 1'b0;
NextState_rwBlkSt <= `RD_CMD_WT_FIN;
end
`RD_TOKEN_CHK_LOOP:
begin
if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS)
begin
NextState_rwBlkSt <= `RD_TOKEN_DEL2;
next_timeOutCnt <= timeOutCnt + 1'b1;
next_delCnt1 <= 8'h00;
end
else if (timeOutCnt == `ONE_HUNDRED_MS)
begin
NextState_rwBlkSt <= `WT_REQ;
next_readError <= `READ_TOKEN_ERROR;
end
else
begin
NextState_rwBlkSt <= `RD_DATA_CLR_RX;
next_rxDataRdyClr <= 1'b1;
end
end
`RD_TOKEN_WT_FIN:
begin
if (rxDataRdy == 1'b1)
begin
NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP;
next_locRespByte <= rxDataIn;
end
end
`RD_TOKEN_SEND_CMD:
begin
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
next_rxDataRdyClr <= 1'b1;
NextState_rwBlkSt <= `RD_TOKEN_DEL1;
end
`RD_TOKEN_DEL2:
begin
next_delCnt1 <= delCnt1 + 1'b1;
next_delCnt2 <= 8'h00;
if (delCnt1 == `MAX_8_BIT)
begin
NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
end
else
begin
NextState_rwBlkSt <= `RD_TOKEN_DEL3;
end
end
`RD_TOKEN_INIT_LOOP:
begin
next_timeOutCnt <= 12'h000;
NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
end
`RD_TOKEN_DEL1:
begin
next_txDataWen <= 1'b0;
next_rxDataRdyClr <= 1'b0;
NextState_rwBlkSt <= `RD_TOKEN_WT_FIN;
end
`RD_TOKEN_DEL3:
begin
next_delCnt2 <= delCnt2 + 1'b1;
if (delCnt2 == 8'hff)
begin
NextState_rwBlkSt <= `RD_TOKEN_DEL2;
end
end
`RD_DATA_ST_LOOP:
begin
next_txDataWen <= 1'b1;
next_txDataOut <= 8'hff;
next_loopCnt <= loopCnt + 1'b1;
NextState_rwBlkSt <= `RD_DATA_WT_DATA;
end
`RD_DATA_WT_DATA:
begin
next_txDataWen <= 1'b0;
if (rxDataRdy == 1'b1)
begin
NextState_rwBlkSt <= `RD_DATA_CHK_LOOP;
next_rxFifoWen <= 1'b1;
next_rxDataRdyClr <= 1'b1;
next_rxFifoData <= rxDataIn;
end
end
`RD_DATA_CHK_LOOP:
begin
if (loopCnt == 9'b000000000)
begin
NextState_rwBlkSt <= `RD_DATA_CS_ST1;
next_rxDataRdyClr <= 1'b0;
next_rxFifoWen <= 1'b0;
end
else
begin
NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
next_rxDataRdyClr <= 1'b0;
next_rxFifoWen <= 1'b0;
end
end
`RD_DATA_CLR_RX:
begin
NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
next_rxDataRdyClr <= 1'b0;
next_loopCnt <= 9'b000000000;
end
`RD_DATA_CS_FIN2:
begin
next_txDataWen <= 1'b0;
if (txDataEmpty == 1'b1)
begin
NextState_rwBlkSt <= `WT_REQ;
end
end
`RD_DATA_CS_FIN1:
begin
next_txDataWen <= 1'b0;
NextState_rwBlkSt <= `RD_DATA_CS_ST2;
end
`RD_DATA_CS_ST1:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `RD_DATA_CS_FIN1;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`RD_DATA_CS_ST2:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `RD_DATA_CS_FIN2;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`WR_DATA_D_FIN:
begin
next_txDataWen <= 1'b0;
if (loopCnt == 9'b000000000)
begin
NextState_rwBlkSt <= `WR_DATA_CS_ST1;
end
else
begin
NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
end
end
`WR_DATA_D_ST:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_DATA_D_FIN;
next_txDataOut <= txFifoData;
next_txDataWen <= 1'b1;
end
end
`WR_DATA_RD_FIFO1:
begin
next_txFifoRen <= 1'b1;
next_loopCnt <= loopCnt + 1'b1;
NextState_rwBlkSt <= `WR_DATA_RD_FIFO2;
end
`WR_DATA_RD_FIFO2:
begin
next_txFifoRen <= 1'b0;
NextState_rwBlkSt <= `WR_DATA_D_ST;
end
`WR_DATA_LOOP_INIT:
begin
next_loopCnt <= 9'b000000000;
NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
end
`WR_DATA_CS_ST1:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_DATA_CS_FIN1;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`WR_DATA_CS_FIN1:
begin
next_txDataWen <= 1'b0;
NextState_rwBlkSt <= `WR_DATA_CS_ST2;
end
`WR_DATA_CS_FIN2:
begin
next_txDataWen <= 1'b0;
next_timeOutCnt <= 12'h000;
if (txDataEmpty == 1'b1)
begin
NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
end
end
`WR_DATA_CS_ST2:
begin
if (txDataFull == 1'b0)
begin
NextState_rwBlkSt <= `WR_DATA_CS_FIN2;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
end
end
`WR_DATA_CHK_RESP:
begin
if (timeOutCnt == `WR_RESP_TOUT)
begin
NextState_rwBlkSt <= `WT_REQ;
next_writeError <= `WRITE_DATA_ERROR;
end
else if (locRespByte[4:0] == 5'h5)
begin
NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP;
end
else
begin
NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
end
end
`WR_DATA_REQ_RESP_ST:
begin
NextState_rwBlkSt <= `WR_DATA_DEL;
next_txDataOut <= 8'hff;
next_txDataWen <= 1'b1;
next_timeOutCnt <= timeOutCnt + 1'b1;
next_rxDataRdyClr <= 1'b1;
end
`WR_DATA_REQ_RESP_FIN:
begin
if (rxDataRdy == 1'b1)
begin
NextState_rwBlkSt <= `WR_DATA_CHK_RESP;
next_locRespByte <= rxDataIn;
end
end
`WR_DATA_DEL:
begin
NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN;
next_txDataWen <= 1'b0;
next_rxDataRdyClr <= 1'b0;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_rwBlkSt <= `ST_RW_SD;
else
CurrState_rwBlkSt <= NextState_rwBlkSt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
readWriteSDBlockRdy <= 1'b0;
spiCS_n <= 1'b1;
readError <= 1'b0;
writeError <= 1'b0;
txDataOut <= 8'h00;
txDataWen <= 1'b0;
rxDataRdyClr <= 1'b0;
cmdByte <= 8'h00;
dataByte1 <= 8'h00;
dataByte2 <= 8'h00;
dataByte3 <= 8'h00;
dataByte4 <= 8'h00;
checkSumByte <= 8'h00;
sendCmdReq <= 1'b0;
txFifoRen <= 1'b0;
rxFifoWen <= 1'b0;
rxFifoData <= 8'h00;
loopCnt <= 8'h00;
delCnt1 <= 8'h00;
delCnt2 <= 8'h00;
timeOutCnt <= 12'h000;
locRespByte <= 8'h00;
end
else
begin
readWriteSDBlockRdy <= next_readWriteSDBlockRdy;
spiCS_n <= next_spiCS_n;
readError <= next_readError;
writeError <= next_writeError;
txDataOut <= next_txDataOut;
txDataWen <= next_txDataWen;
rxDataRdyClr <= next_rxDataRdyClr;
cmdByte <= next_cmdByte;
dataByte1 <= next_dataByte1;
dataByte2 <= next_dataByte2;
dataByte3 <= next_dataByte3;
dataByte4 <= next_dataByte4;
checkSumByte <= next_checkSumByte;
sendCmdReq <= next_sendCmdReq;
txFifoRen <= next_txFifoRen;
rxFifoWen <= next_rxFifoWen;
rxFifoData <= next_rxFifoData;
loopCnt <= next_loopCnt;
delCnt1 <= next_delCnt1;
delCnt2 <= next_delCnt2;
timeOutCnt <= next_timeOutCnt;
locRespByte <= next_locRespByte;
end
end
endmodule
|
// Based on http://opencores.org/project,spi
module wb_regmap(
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_cti_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
debug_out
);
// Wishbone slave signals
input wb_clk_i;
input wb_rst_i;
input [4:0] wb_adr_i;
input [15:0] wb_dat_i;
output [15:0] wb_dat_o;
input [1:0] wb_sel_i;
input [2:0] wb_cti_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output wb_err_o;
output wb_int_o;
output [15:0] debug_out;
assign debug_out = {fifo_dout};
// This is used to force addressing errors on poor handshake implementation
wire [4:0] int_addr;
assign int_addr = (wb_cyc_i) ? wb_adr_i : 5'h1F;
// End of Transfer
wire eot;
assign eot = ((wb_cti_i == 3'b000) & wb_ack_o) | (wb_cti_i == 3'b111);
// Handshake - synchronous due to nature of block RAM
reg wb_ack_o;
always @(posedge wb_clk_i) begin
// Set by STB and itself, cleared by EOT or RST
wb_ack_o <= (wb_stb_i | wb_ack_o) & ~(eot | wb_rst_i);
end
// Interrupt and Error
reg wb_int_o;
reg wb_err_o;
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wb_int_o <= 1'b0;
wb_err_o <= 1'b0;
end
end
// Register map
reg [4:0] rm_addr_in;
reg [15:0] reg_map [31:0];
reg [15:0] rm_data_in;
reg [15:0] rm_data_out;
// Latch data out on a read request
reg [15:0] rm_dat_o;
always @(posedge wb_clk_i) begin
if (~wb_we_i) begin
rm_dat_o <= rm_data_out;
end
end
// Latch data in on a write request
always @(posedge wb_clk_i) begin
if (wb_we_i) begin
reg_map[int_addr] <= rm_data_in;
end
end
// Write to registers multiplex
always @(int_addr or wb_dat_i) begin
case (int_addr)
0: rm_data_in <= wb_dat_i;
1: rm_data_in <= wb_dat_i;
2: rm_data_in <= wb_dat_i;
3: rm_data_in <= wb_dat_i;
4: rm_data_in <= wb_dat_i;
5: rm_data_in <= wb_dat_i;
6: rm_data_in <= wb_dat_i;
7: rm_data_in <= wb_dat_i;
//16: fifo_din <= wb_dat_i;
default: rm_data_in <= 16'hAAAA;
endcase
end
// Read from registers multiplex
always @(int_addr or reg_map) begin
case (int_addr)
0: rm_data_out <= reg_map[int_addr];
1: rm_data_out <= reg_map[int_addr];
2: rm_data_out <= reg_map[int_addr];
3: rm_data_out <= reg_map[int_addr];
4: rm_data_out <= reg_map[int_addr];
5: rm_data_out <= reg_map[int_addr];
6: rm_data_out <= reg_map[int_addr];
7: rm_data_out <= reg_map[int_addr];
8: rm_data_out <= reg_map[int_addr];
default: rm_data_out <= 16'd12346;
endcase
end
// Loop-back FIFO for testing
wire fifo_rd;
wire fifo_wr;
assign fifo_rd = ~(wb_cti_i == 3'b000) & (int_addr == 5'h10) & wb_stb_i & wb_ack_o & ~wb_we_i;
assign fifo_wr = ~(wb_cti_i == 3'b000) & (int_addr == 5'h11) & wb_stb_i & wb_ack_o & wb_we_i;
// FIFO read access cannot rely on data switch as it needs to look ahead
assign fifo_rd_addr_incr = (wb_cti_i == 3'b001) & (int_addr == 5'h10) & wb_stb_i;
wire [15:0] fifo_din;
wire [15:0] fifo_dout;
reg [9:0] fifo_wr_addr;
reg [9:0] fifo_rd_addr;
// Bypass register map when accessing the FIFO
assign wb_dat_o = (fifo_rd) ? fifo_dout : rm_dat_o;
assign fifo_din = (fifo_wr) ? wb_dat_i : 16'd0;
// Auto-incremenet
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
fifo_wr_addr <= 9'd0;
fifo_rd_addr <= 9'd0;
end else begin
if (fifo_wr)
fifo_wr_addr <= fifo_wr_addr + 9'd1;
else
fifo_wr_addr <= fifo_wr_addr;
if (fifo_rd_addr_incr)
fifo_rd_addr <= fifo_rd_addr + 9'd1;
else
fifo_rd_addr <= fifo_rd_addr;
end
end
// Instantiate a generic dual port RAM module
dp_ram rm_fifo(
// Write port
.a_clk(wb_clk_i), .a_wr(fifo_wr), .a_addr(fifo_wr_addr),
.a_din(fifo_din), .a_dout(),
// Read port
.b_clk(wb_clk_i), .b_wr(1'b0), .b_addr(fifo_rd_addr),
.b_din(16'b0), .b_dout(fifo_dout)
);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../onchip_memory2.hex";
output [ 31: 0] readdata;
input [ 9: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 10;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "onchip_memory2.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 1024,
// the_altsyncram.numwords_a = 1024,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 10;
//
//synthesis read_comments_as_HDL off
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : pcie_brams_s6.v
// Description: BlockRAM module for Spartan-6 PCIe Block
//
// Arranges and connects brams
// Implements address decoding, datapath muxing and
// pipeline stages
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_brams_s6 #(
// the number of BRAMs to use
// supported values are:
// 1,2,4,9
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input wen,
input [11:0] waddr,
input [35:0] wdata,
input ren,
input rce,
input [11:0] raddr,
output [35:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 36 :
(NUM_BRAMS == 2) ? 18 :
(NUM_BRAMS == 4) ? 9 :
4
);
localparam TCQ = 1;
//synthesis translate_off
initial begin
case (NUM_BRAMS)
1,2,4,9:;
default: begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [11:0] waddr_int;
wire [35:0] wdata_int;
generate
if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [11:0] waddr_dly;
reg [35:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 12'b0;
wdata_dly <= #TCQ 36'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [11:0] raddr_int;
wire [35:0] rdata_int;
generate
if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [11:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 12'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate
if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [35:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 36'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_s6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
endgenerate
endmodule // pcie_brams_s6
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_TB_V
`define SKY130_FD_SC_MS__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_FUNCTIONAL_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: five_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module five_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/five_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/five_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/five_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module DataMem (
input clk, rst,
input MemWrite, MemRead,
input rx,
input [31:0] addr, wdata,
input [7:0] switch,
output tx,
output reg [31:0] rdata,
output reg [7:0] led,
output reg [11:0] digi,
output irq
);
parameter RAM_SIZE = 256;
parameter RAM_BIT = 8; // 2^8 = 256
reg [31:0] DATA[RAM_SIZE-1:0];
reg [31:0] TH, TL;
reg [2:0] TCON;
reg [7:0] UART_RXD, UART_TXD;
reg [1:0] UART_CON;
reg enable; // UART enable
wire rx_s, tx_s; // UART status
wire [7:0] rx_d; // receive data
integer i;
assign irq = TCON[2];
// read
always @ (*) begin
if(MemRead) begin
case (addr)
32'h4000_0000: rdata <= TH;
32'h4000_0004: rdata <= TL;
32'h4000_0008: rdata <= {29'b0, TCON};
32'h4000_000c: rdata <= {24'b0, led};
32'h4000_0010: rdata <= {24'b0, switch};
32'h4000_0014: rdata <= {20'b0, digi};
32'h4000_0018: rdata <= {24'b0, UART_TXD};
32'h4000_001c: rdata <= {24'b0, UART_RXD};
32'h4000_0020: rdata <= {28'b0, UART_CON, 2'b0};
default: begin
rdata <= ( (addr[RAM_BIT+1:2]<RAM_SIZE) && ~addr[30] ) ?
DATA[ addr[RAM_BIT+1:2] ] : 32'b0;
end
endcase
end else
rdata <= 32'b0;
end
// write
always @ (posedge clk or posedge rst) begin
if (rst) begin // posedge rst
for(i=0;i<256;i=i+1) DATA[i]<=32'b0;
TH <= 32'b0;
TL <= 32'b0;
TCON <= 3'b0; // all disable
led <= 8'b0;
digi <= 12'b0;
end else begin
if(TCON[0]) begin // TIM enable
if(TL==32'hffff_ffff) begin
TL <= TH;
TCON[2] <= TCON[1] ? 1'b1 : 1'b0;
end else begin
TL <= TL + 1'b1;
end
end
if(MemWrite)
case (addr)
32'h4000_0000: TH <= wdata;
32'h4000_0004: TL <= wdata;
32'h4000_0008: TCON <= wdata[2:0];
32'h4000_000C: led <= wdata[7:0];
32'h4000_0014: digi <= wdata[11:0];
default: if ( (addr[RAM_BIT+1:2]<RAM_SIZE) && ~addr[30] )
DATA[ addr[RAM_BIT+1:2] ] <= wdata;
endcase
end
end
// UART control
UART_RX uartrx(
.clk(clk), .rst(rst),
.RX(rx),
.DATA(rx_d),
.STATUS(rx_s)
);
UART_TX uarttx(
.clk(clk), .rst(rst),
.DATA(UART_TXD),
.EN(enable),
.TX(tx),
.STATUS(),
.END(tx_s)
);
always @ (posedge clk or posedge rst) begin
if(rst) begin
UART_CON <= 2'b0;
UART_TXD <= 8'b0;
UART_RXD <= 8'b0;
enable <= 1'b0;
end else begin
if(MemWrite)
case (addr)
32'h4000_0018: begin
UART_TXD <= wdata[7:0];
enable <= 1'b1;
end
32'h4000_0020: UART_CON <= wdata[3:2];
default: ;
endcase
if(MemRead)
case (addr)
32'h4000_0018: UART_CON[0] <= 1'b0;
32'h4000_001c: UART_CON[1] <= 1'b0;
default: ;
endcase
if(rx_s) begin
UART_RXD <= rx_d;
UART_CON[1] <= 1'b1;
end
if(tx_s) begin
UART_CON[0] <= 1'b1;
enable <= 1'b0;
end
end
end
endmodule
|
module cosrom (
input c, // clock
input [9:0] a0, a1, // angle
output [34:0] d0, d1);
wire [35:0] o0, o1;
assign d0 = o0[34:0];
assign d1 = o1[34:0];
RAMB36E1 #(
.DOA_REG(1),.DOB_REG(1),
.INIT_A(36'h000000000), .INIT_B(36'h000000000),
.RAM_MODE("TDP"),
.READ_WIDTH_A(36), .READ_WIDTH_B(36),
.WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36),
.INIT_00(256'hFFE1A04AFFE9A040FFF08037FFF6002CFFFA6023FFFD6018FFFF400FFFFFE005),
.INIT_01(256'hFF752099FF87008FFF97A085FFA7007BFFB54072FFC24068FFCDE05DFFD86054),
.INIT_02(256'hFEB9A0E8FED560DEFEEFE0D4FF0920CAFF2140C1FF3800B6FF4DA0ADFF6200A3),
.INIT_03(256'hFDAF4137FDD4C12CFDF94124FE1C6119FE3E410FFE5F0106FE7E60FBFE9CA0F2),
.INIT_04(256'hFC55E185FC85617CFCB3A172FCE0A168FD0C615EFD370155FD60414AFD886141),
.INIT_05(256'hFAADE1D5FAE721CAFB1F41C1FB5621B7FB8BC1ADFBC021A3FBF34199FC254190),
.INIT_06(256'hF8B70223F8FA2219F93C2210F97CC205F9BC41FCF9FA81F2FA3781E8FA7341DE),
.INIT_07(256'hF6718272F6BE8268F70A425EF754C254F79E224BF7E62240F82D0237F872A22D),
.INIT_08(256'hF3DD62C0F43442B7F489C2ACF4DE22A3F5314299F583228FF5D3E286F623427B),
.INIT_09(256'hF0FAE30FF15B6304F1BAE2FCF21902F1F275E2E7F2D1A2DEF32C22D4F38562CA),
.INIT_0A(256'hEDC9E35DEE344353EE9D834AEF05633FEF6C2336EFD1A32CF035E322F0990319),
.INIT_0B(256'hEA4AA3ABEABEE3A2EB31C397EBA3838EEC140384EC83637BECF16370ED5E4367),
.INIT_0C(256'hE67D63FAE6FB43EFE77803E6E7F383DCE86DC3D2E8E6C3C8E95EA3BFE9D543B5),
.INIT_0D(256'hE2620447E2E9A43DE3702434E3F5642AE4796420E4FC4417E57DC40CE5FE2403),
.INIT_0E(256'hDDF8E495DE8A448BDF1A8482DFA96477E037246EE0C3C465E14F045AE1D92451),
.INIT_0F(256'hD94224E2D9DD44D9DA7724CFDB0FC4C5DBA744BCDC3D84B2DCD284A8DD66449E),
.INIT_10(256'hD43DE530D4E2A526D586451DD6288512D6C9A509D769A500D80864F6D8A5E4EC),
.INIT_11(256'hCEEC657DCF9AC573D048056AD0F40560D19EC556D248654DD2F0C543D397E539),
.INIT_12(256'hC94DE5CACA05E5C0CABCC5B7CB7265ADCC26C5A3CCDA059ACD8C0590CE3CC586),
.INIT_13(256'hC3628617C424260DC4E48603C5A3C5FAC661C5F0C71EA5E7C7DA45DDC894A5D3),
.INIT_14(256'hBD2A6663BDF5A65ABEBFA650BF886646C050063DC1166633C1DBA62AC29FA620),
.INIT_15(256'hB6A606AFB77AC6A6B84E469CB920A693B9F1C689BAC1C680BB908676BC5E066C),
.INIT_16(256'hAFD586FBB0B3C6F2B190C6E8B26CA6DFB34746D5B420C6CCB4F906C2B5D026B9),
.INIT_17(256'hA8B92747A9A0C73DAA874734AB6CA72BAC50C721AD33C718AE15870EAEF62705),
.INIT_18(256'hA1512793A2424789A332277FA420E776A50E876DA5FAE763A6E6275AA7D04751),
.INIT_19(256'h999DC7DD9A9867D59B91A7CA9C89E7C29D80E7B89E76A7AE9F6B67A6A05EC79B),
.INIT_1A(256'h919F882892A3681F93A6281694A7A80C95A8080396A747FA97A547F098A227E7),
.INIT_1B(256'h895688738A63C86A8B6FC8608C7AA8578D84684E8E8CE8448F94483B909A8832),
.INIT_1C(256'h80C328BD81D9A8B482EEE8AA840328A2851628988627E88E8738A8868848287C),
.INIT_1D(256'h77E5A907790568FE7A2408F57B4168EB7C5DA8E27D78C8D97E92A8CF7FAB88C7),
.INIT_1E(256'h6EBE89506FE78948710F493E7235E935735B492B747FA92375A2C91976C4C910),
.INIT_1F(256'h654E09996680299167B1098768E0C97E6A0F69756B3CE96C6C6949636D94895A),
.INIT_20(256'h5B9489E25CCFC9DA5E09C9D05F42A9C7607A69BE61B109B562E689AC641AE9A3),
.INIT_21(256'h51928A2B52D6AA215419CA19555BCA10569C8A0657DC49FE591AE9F55A5849EB),
.INIT_22(256'h47482A7348956A6A49E16A604B2C6A584C764A4F4DBF0A464F06AA3D504D2A34),
.INIT_23(256'h3CB5EABA3E0C2AB23F612AA840B52AA042080A974359AA8D44AA4A8545F9CA7C),
.INIT_24(256'h31DC6B02333B6AF834996AF035F64AE737520ADE38ACAAD53A064ACD3B5EAAC3),
.INIT_25(256'h26BBCB492823AB3F298A8B372AF04B2E2C54EB252DB86B1C2F1AEB14307C2B0A),
.INIT_26(256'h1B548B8E1CC54B861E34EB7D1FA38B752110EB6B227D4B6323E88B5A2552AB51),
.INIT_27(256'h0FA74BD51120CBCC12992BC314106BBA1586ABB216FBCBA9186FCBA019E2CB98),
.INIT_28(256'h03B42C1A05366C1206B78C0908378C0009B66BF70B344BEF0CB10BE60E2CABDD),
.INIT_29(256'hF77BEC5FF906CC57FA908C4EFC192C45FDA0AC3CFF272C3400ACAC2C0230EC22),
.INIT_2A(256'hEAFEECA3EC924C9BEE24AC93EFB5EC8AF1460C81F2D52C79F4632C70F5F00C67),
.INIT_2B(256'hDE3DACE7DFD98CDFE1746CD7E30E2CCEE4A6CCC5E63E6CBDE7D50CB5E96A8CAC),
.INIT_2C(256'hD138AD2BD2DCED22D4802D1AD6226D12D7C38D09D963AD01DB02CCF9DCA0CCF0),
.INIT_2D(256'hC3F04D6EC59CED65C748AD5EC8F34D55CA9CCD4CCC454D44CDECCD3CCF934D34),
.INIT_2E(256'hB6652DB1B81A2DA8B9CE2DA0BB812D98BD330D8FBEE3ED87C093CD7FC2428D76),
.INIT_2F(256'hA897CDF3AA550DEAAC114DE2ADCC8DDAAF86ADD1B13FEDCAB2F80DC1B4AF0DB8),
.INIT_30(256'h9A88AE349C4E2E2C9E128E239FD60E1CA1986E13A359CE0BA51A2E03A6D96DFA),
.INIT_31(256'h8C386E758E060E6D8FD28E64919E2E5D9368AE5495322E4C96FAAE4498C22E3C),
.INIT_32(256'h7DA78EB57F7D2EAD8151CEA583256E9D84F80E9586C9AE8D889A4E858A69CE7C),
.INIT_33(256'h6ED6AEF570B42EEC7290CEE5746C6EDD76470ED57820AECD79F94EC57BD0EEBD),
.INIT_34(256'h5FC62F3461ABAF2C63902F246573CF1D67564F146937CF0C6B186F056CF80EFD),
.INIT_35(256'h5076CF7252642F6B54508F63563BEF5B58264F535A0FCF4C5BF82F435DDFAF3C),
.INIT_36(256'h40E92FB042DE4FA944D26FA146C58F9948B7CF924AA8EF894C994F834E888F7A),
.INIT_37(256'h311DCFEE331A8FE635166FDF37114FD7390B2FCF3B040FC73CFC0FC03EF32FB9),
.INIT_38(256'h2115502B2319B023251D301C271F90132921300D2B21B0042D216FFE2F200FF5),
.INIT_39(256'h10D0506712DC305F14E7305816F1305018FA50491B0270411D09B03A1F0FF032),
.INIT_3A(256'h004F70A20262D09B047550940686D08C089750840AA6F07D0CB5B0760EC3706E),
.INIT_3B(256'hEF9370DDF1AE10D5F3C7F0CFF5E0D0C7F7F8D0C0FA0FD0B8FC25F0B1FE3B30AA),
.INIT_3C(256'hDE9CB117E0BEB110E2DFD109E5001102E71F50FAE93DB0F3EB5B30ECED77D0E5),
.INIT_3D(256'hCD6C3151CF955149D1BDB143D3E5113BD60BB135D831512DDA55F125DC79D11F),
.INIT_3E(256'hBC02518ABE329182C062117CC290B175C4BE516DC6EB1166C9171160CB421158),
.INIT_3F(256'hAA5FD1C2AC9731BBAECDB1B4B10351ADB33811A6B56BF19FB79EF198B9D11191),
.INIT_40(256'h988571F99AC3D1F39D0151EC9F3DD1E4A17991DEA3B471D7A5EE71D0A82791C9),
.INIT_41(256'h8673D23088B9122A8AFD72238D40F21C8F83921591C5520E9406320796465201),
.INIT_42(256'h742BB2667677B26078C2D2597B0D12527D56924C7F9F324581E6F23E842DD237),
.INIT_43(256'h61ADD29C640072956652528F68A352886AF372816D42D27B6F91527471DEF26D),
.INIT_44(256'h4EFAB2D15153F2CA53AC72C4560412BD585AD2B65AB0D2B05D05F2A95F5A52A3),
.INIT_45(256'h3C1333043E7312FF40D1F2F7433032F2458D72EA47EA12E54A45B2DD4CA092D7),
.INIT_46(256'h28F813372B5E53322DC3B32B30285325328C131E34EF13183751531239B2B30B),
.INIT_47(256'h15AA136A181693641A82535E1CED53581F57735121C0D34B242953442691333F),
.INIT_48(256'h0229D39C049C9396070E9390097FD38A0BF033830E5FD37D10CEB377133CD371),
.INIT_49(256'hEE7833CDF0F113C7F36933C1F5E093BBF85733B5FACCF3AEFD4213A9FFB653A2),
.INIT_4A(256'hDA95D3FDDD14D3F8DF92F3F1E21053EBE48D13E6E708F3DFE98413D9EBFE93D4),
.INIT_4B(256'hC683942DC9087427CB8C9421CE10141CD092B415D314940FD595B409D8163404),
.INIT_4C(256'hB242345BB4CCF456B756F450B9E0344ABC68D445BEF0943EC177B439C3FDF432),
.INIT_4D(256'h9DD2948AA062F483A2F2B47EA581D479A8101472AA9DB46DAD2A9467AFB6D462),
.INIT_4E(256'h893534B68BCB54B18E60D4AC90F574A5938994A1961CD49A98AF74959B41548F),
.INIT_4F(256'h746B34E37706D4DD79A1D4D87C3C34D37ED5B4CC816EB4C88406D4C1869E74BD),
.INIT_50(256'h5F75350F6216550964B6B503675694FF69F594F86C9414F46F31B4ED71CED4E9),
.INIT_51(256'h4A53F5394CFA75344FA0552F5245752954E9F524578DB51E5A30D5195CD35514),
.INIT_52(256'h3508756337B4355E3A5F55593D09B5533FB3754E425C95494505154447ACD53E),
.INIT_53(256'h1F93758C2244558724F4958227A4157C2A5315782D0175732FAF156D325C1568),
.INIT_54(256'h09F5B5B40CAB95AF0F60D5AA121595A614C995A0177CF59B1A2FD5971CE1F591),
.INIT_55(256'hF43015DCF6EAF5D7F9A535D2FC5ED5CDFF17D5C801D035C30487F5BE073F35BA),
.INIT_56(256'hDE437602E10335FEE3C235F8E680B5F4E93E95EFEBFBD5EAEEB895E6F17495E0),
.INIT_57(256'hC830B628CAF51623CDB8F61FD07C1619D33ED616D600D610D8C2560CDB833607),
.INIT_58(256'hB1F8964DB4C19648B78A1644BA51F63FBD19363ABFDFF636C2A61631C56BB62D),
.INIT_59(256'h9B9BF6719E69766CA1367668A402D663A6CEB65FA99A165BAC64D656AF2EF651),
.INIT_5A(256'h851BB69487EDB6908ABF168B8D8FF68790603682932FF67E95FF367A98CDD675),
.INIT_5B(256'h6E78D6B6714F16B27424B6AD76F9F6AA79CE96A57CA2B6A17F76369C82493698),
.INIT_5C(256'h57B3F6D75A8E76D45D6856CF6041B6CB631A96C765F2F6C368CAB6BE6BA216BB),
.INIT_5D(256'h40CE36F843ACB6F4468AB6F0496836EC4C4536E84F2196E351FD96E054D916DC),
.INIT_5E(256'h29C857182CAAB7132F8CB710326E370C354F3708382FB7043B0FB7003DEF36FC),
.INIT_5F(256'h12A3373715897732186F572F1B54B72B1E399727211DF7232401D71F26E5571C),
.INIT_60(256'hFB5FB754FE49B7500133574D041C77490705374609ED57410CD5173E0FBC573A),
.INIT_61(256'hE3FED771E6EC776DE9D9B76AECC69767EFB2D762F29ED760F58A375BF8753758),
.INIT_62(256'hCC81778DCF729789D2635786D553B783D843977FDB33177CDE221778E110B775),
.INIT_63(256'hB4E857A8B7DCF7A5BAD137A2BDC4F79EC0B8579BC3AB3797C69DB794C98FD791),
.INIT_64(256'h9D3497C2A02C97C0A323F7BBA61B17B9A911D7B6AC0817B2AEFDF7AFB1F357AB),
.INIT_65(256'h856717DC886237D98B5CD7D58E5717D29150F7CF944A77CC974397C99A3C57C6),
.INIT_66(256'h6D80B7F5707ED7F1737C97EE7679F7EB7976F7E87C7397E57F6FB7E1826B97DF),
.INIT_67(256'h5582380B588358095B8418065E847803618457FF6483F7FD678337FA6A8217F7),
.INIT_68(256'h3D6CD8224070B81F4374581D46777819497A58174C7CD8144F7F18125280D80E),
.INIT_69(256'h254158382847F8352B4E38322E5438303159B82C345F182B3763F8273A689825),
.INIT_6A(256'h0D00984C1009D84A1312B847161B5845192398421C2B783F1F33183D223A583A),
.INIT_6B(256'hF4AB9860F7B7585EFAC2B85BFDCDD85900D8985603E3185406ED385109F7184F),
.INIT_6C(256'hDC435872DF517871E25F386EE56CB86CE879D869EB86B867EE935865F19F9862),
.INIT_6D(256'hC3C8D885C6D91882C9E91880CCF8D87ED008587CD3177879D6267878D9351875),
.INIT_6E(256'hAB3CB895AE4F3894B1615891B473388FB784D88DBA96388BBDA75889C0B83887),
.INIT_6F(256'h92A038A595B4B8A498C8D8A19BDCD8A09EF0789DA203F89CA5171899A82A1898),
.INIT_70(256'h79F438B47D0A98B3802098B0833678AF864C18AD896178AB8C76B8AA8F8B98A7),
.INIT_71(256'h613998C26451B8C1676998BF6A8138BD6D98B8BC70AFF8BA73C6F8B876DDB8B6),
.INIT_72(256'h487178D04B8B38CE4EA4B8CC51BE18CB54D738C957F018C75B08D8C65E2158C4),
.INIT_73(256'h2F9C98DC32B7D8DA35D2F8D938EDD8D73C0878D53F2318D5423D58D2455778D1),
.INIT_74(256'h16BBF8E719D898E51CF538E5201178E2232DB8E22649B8E0296578DE2C8118DD),
.INIT_75(256'hFDD098F100EE98F0040C78EF072A18ED0A4798EC0D64F8EB108218E9139F18E8),
.INIT_76(256'hE4DB98FBE7FAB8F9EB19B8F8EE3898F7F15738F5F475D8F5F79438F3FAB278F2),
.INIT_77(256'hCBDD9902CEFDD902D21DD900D53DD900D85D98FEDB7D58FEDE9CD8FCE1BC38FB),
.INIT_78(256'hB2D7D90AB5F8F909B919F908BC3AD907BF5B9906C27C5906C59CD904C8BD5904),
.INIT_79(256'h99CB19109CED1910A00ED90EA330990EA652390DA973D90DAC95390BAFB6990B),
.INIT_7A(256'h80B8791583DB191586FDB9158A2019138D4279139064D9139386F91196A91911),
.INIT_7B(256'h67A0F91A6AC419196DE73919710A5919742D3917775039187A7319177D95D916),
.INIT_7C(256'h4E85591D51A8F91D54CC991D57F0191C5B13991C5E36F91B615A591B647DB91B),
.INIT_7D(256'h3566B920388AB9203BAE991F3ED2791F41F6591F451A391F483DF91E4B61B91E),
.INIT_7E(256'h1C4619211F6A3921228E592125B2792128D699212BFAB9212F1EB9203242B920),
.INIT_7F(256'h0324592206489922096CD9220C9119220FB5592212D9792115FDB9221921F922),
.INITP_00(256'h7777777777777777777777777777777777777777777777777777777777777777),
.INITP_01(256'h7777777777777777777777777777777777777777777777777777777777777777),
.INITP_02(256'h7777777777777777777777777777777777777777777777777777777777777777),
.INITP_03(256'h7777777777777777777777777777777777777777777777777777777777777777),
.INITP_04(256'h7777777777777777777777777777777777777777777777777777777777777777),
.INITP_05(256'h6666666666666666666666666666666666666666666666666666667777777777),
.INITP_06(256'h6666666666666666666666666666666666666666666666666666666666666666),
.INITP_07(256'h5555555555555555555555555555555555555555666666666666666666666666),
.INITP_08(256'h5555555555555555555555555555555555555555555555555555555555555555),
.INITP_09(256'h4444444444444444444444444444444444444444444444444444444455555555),
.INITP_0A(256'h3333333333333333333334444444444444444444444444444444444444444444),
.INITP_0B(256'h3333333333333333333333333333333333333333333333333333333333333333),
.INITP_0C(256'h2222222222222222222222222222222222222222222222222222222222333333),
.INITP_0D(256'h1111111111111111111111111111111111112222222222222222222222222222),
.INITP_0E(256'h0000000000000000011111111111111111111111111111111111111111111111),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.SIM_DEVICE("7SERIES"))
RAMB36E1_inst (
.CASCADEOUTA(), .CASCADEOUTB(),
.DBITERR(), .ECCPARITY(), .RDADDRECC(), .SBITERR(),
.DOADO(o0[31:0]),
.DOPADOP(o0[35:32]),
.DOBDO(o1[31:0]),
.DOPBDOP(o1[35:32]),
.CASCADEINA(1'b0), .CASCADEINB(1'b0),
.INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0),
.ADDRARDADDR({1'b0,a0,5'd0}),
.CLKARDCLK(c),
.ENARDEN(1'b1),
.REGCEAREGCE(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTREGARSTREG(1'b0),
.WEA(4'b0),
.DIADI(32'h0),
.DIPADIP(4'h0),
.ADDRBWRADDR({1'b0,a1,5'd0}),
.CLKBWRCLK(c),
.ENBWREN(1'b1),
.REGCEB(1'b1),
.RSTRAMB(1'b0),
.RSTREGB(1'b0),
.WEBWE(8'b0),
.DIBDI(32'h0),
.DIPBDIP(4'h0));
endmodule
|
//`#start header` -- edit after this line, do not edit this line
// Copyright (C) 2013 Michael McMaster <[email protected]>
//
// This file is part of SCSI2SD.
//
// SCSI2SD is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// SCSI2SD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 10/15/2013 at 22:01
// Component: OddParityGen
module OddParityGen (
output DBP,
input [7:0] DBx,
input EN
);
//`#start body` -- edit after this line, do not edit this line
// For some reason the "simple" implementation uses up about 34% of all
// PLD resources on a PSoC 5LP
// 1 ^ DBx[0] ^ DBx[1] ^ DBx[2] ^ DBx[3] ^ DBx[4] ^ DBx[5] ^ DBx[6] ^ DBx[7]
// Breaking the expression up into parts seems to use much less resources.
wire tmp = 1 ^ DBx[0];
wire tmpa = DBx[1] ^ DBx[2];
wire tmpb = DBx[3] ^ DBx[4];
wire tmpc = DBx[5] ^ DBx[6] ^ DBx[7];
assign DBP = EN ? tmp ^ tmpa ^ tmpb ^ tmpc : 0;
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* XY routing
*
* Routing Function
* ================
*
* Simple XY routing
* - Function updates flit with the output port required at next router
* and modifies displacement fields as head flit gets closer to
* destination.
*
* More complex routing algorithms may be implemented by making edits here
* and to the flit's control field defn.
*
* Valid Turn?
* ===========
*
* LAG_route_valid_turn(from, to)
*
* This function is associated with the routing algorithm and is used to
* optimize the synthesis of the implementation by indicating impossible
* turns - hence superfluous logic.
*
* Valid Input PL
* ==============
*
* Does a particular input PL exist. e.g. Tile input port may only contain
* one PL buffer.
*
*/
//router_radix defined in parameters.v
function automatic bit LAG_route_valid_input_pl;
input integer port;
input integer pl;
bit valid;
begin
valid=1'b1;
if (port==`TILE) begin
if (pl>=router_num_pls_on_entry) valid=1'b0;
end
LAG_route_valid_input_pl=valid;
end
endfunction // automatic
function automatic bit LAG_route_valid_turn;
input output_port_t from;
input output_port_t to;
bit valid;
begin
valid=1'b1;
// flits don't leave on the same port as they entered
if (from==to) valid=1'b0;
`ifdef OPT_MESHXYTURNS
// Optimise turns for XY routing in a mesh
if (((from==`NORTH)||(from==`SOUTH))&&((to==`EAST)||(to==`WEST))) valid=1'b0;
`endif
LAG_route_valid_turn=valid;
end
endfunction // bit
module LAG_route (flit_in, flit_out, clk, rst_n);
input flit_t flit_in;
output flit_t flit_out;
input clk, rst_n;
function flit_t next_route;
input flit_t flit_in;
logic [4:0] route;
flit_t new_flit;
x_displ_t x_disp;
y_displ_t y_disp;
begin
new_flit = flit_in;
x_disp = x_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS : router_radix]);
y_disp = y_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1]);
// Simple XY Routing
if (x_disp!=0) begin
if (x_disp>0) begin
route = `port5id_east;
x_disp--;
end else begin
route = `port5id_west;
x_disp++;
end
end else begin
if (y_disp==0) begin
route=`port5id_tile;
end else if (y_disp>0) begin
route=`port5id_south;
y_disp--;
end else begin
route=`port5id_north;
y_disp++;
end
end
new_flit.data[router_radix - 1 : 0] = route;
new_flit.data[router_radix + `X_ADDR_BITS : router_radix] = x_displ_t ' (x_disp);
new_flit.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1] = y_displ_t ' (y_disp);
next_route = new_flit;
end
endfunction // flit_t
assign flit_out=next_route(flit_in);
endmodule // route
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
|
module scaler_core # (
parameter integer C_S_WIDTH = 12,
parameter integer C_M_WIDTH = 12,
parameter integer C_S_BMP = 0 ,
parameter integer C_S_BID = 0 ,
parameter integer C_S_IDX = 0 , /// C_S_WIDTH or 0
parameter integer C_TEST = 0
) (
input wire clk,
input wire resetn,
input [C_S_WIDTH-1:0] s_nbr,
input [C_M_WIDTH-1:0] m_nbr,
input wire enable ,
output wire o_valid ,
output wire s_advance ,
output wire s_last ,
output wire [C_S_WIDTH + C_M_WIDTH :0] s_c ,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] s_bmp_bid_idx0,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] s_bmp_bid_idx1,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] s_bmp_bid_idx2,
output wire m_advance ,
output wire m_first ,
output wire m_last ,
output wire [C_S_WIDTH + C_M_WIDTH :0] m_c ,
output wire a_last ,
output wire d_valid
);
localparam integer C_A_WIDTH = C_S_WIDTH + C_M_WIDTH;
reg [C_A_WIDTH :0] s0_c;
reg s0_last;
reg [C_A_WIDTH :0] s1_c;
reg [C_S_WIDTH-1:0] s1_idx_evn;
reg s1_last;
reg su_c;
reg [C_A_WIDTH :0] m0_c;
reg m0_first;
reg m0_last;
reg m1_valid;
reg [C_A_WIDTH :0] m1_c;
reg m1_last;
reg [C_A_WIDTH :0] m2_c;
reg [C_M_WIDTH-1:0] m2_idx_evn;
reg m2_last;
reg mu_c;
reg s_v; /// (s_c >= m_c) or (s_last & ~m_last)
reg s_vlast; /// last valid
reg sm_last;
reg sm_valid;
assign s_c = s0_c;
assign s_advance = su_c;
assign s_last = s0_last;
assign m_c = m0_c;
assign m_advance = mu_c;
assign m_first = m0_first;
assign m_last = m0_last;
assign d_valid = s_v;
assign a_last = sm_last;
assign o_valid = sm_valid;
wire aux_v01; assign aux_v01 = (s0_c >= m1_c);
wire aux_v10; assign aux_v10 = (s1_c >= m0_c);
wire aux_v11; assign aux_v11 = (s1_c >= m1_c);
wire aux_v12; assign aux_v12 = (s1_c >= m2_c);
wire aux_v02r; assign aux_v02r = (s0_c < m2_c);
wire aux_v11r; assign aux_v11r = (s1_c < m1_c);
wire aux_v12r; assign aux_v12r = (s1_c < m2_c);
wire aux_v10r; assign aux_v10r = (s1_c < m0_c);
wire aux_v01r; assign aux_v01r = (s0_c < m1_c);
wire [1:0] smu; assign smu = {su_c, mu_c};
localparam integer UP_B = 2'b11;
localparam integer UP_S = 2'b10;
localparam integer UP_M = 2'b01;
localparam integer UP_N = 2'b00;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s0_c <= 0;
s0_last <= 1;
end
else if (enable) begin
if (su_c) begin
s0_c <= s1_c;
s0_last <= s1_last;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s1_c <= m_nbr;
s1_idx_evn <= s_nbr;
s1_last <= (s_nbr == 1);
end
else if (enable) begin
if (su_c) begin
if (s1_last) begin
s1_idx_evn <= s_nbr;
s1_last <= (s_nbr == 1);
s1_c <= m_nbr;
end
else begin
s1_idx_evn <= s1_idx_evn - 1;
s1_last <= (s1_idx_evn == 2);
s1_c <= s1_c + m_nbr * 2;
end
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m0_c <= 0;
m0_last <= 0;
m1_valid <= 0;
m1_c <= 0;
m1_last <= 1;
end
else if (enable) begin
if (mu_c) begin
m0_c <= m1_c;
m0_last <= m1_last;
m0_first <= m0_last;
m1_valid <= 1;
m1_c <= m2_c;
m1_last <= m2_last;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m2_c <= s_nbr;
m2_idx_evn <= m_nbr;
m2_last <= (m_nbr == 1);
end
else if (enable) begin
if (mu_c) begin
if (m2_last) begin
m2_c <= s_nbr;
m2_idx_evn <= m_nbr;
m2_last <= (m_nbr == 1);
end
else begin
m2_c <= m2_c + s_nbr * 2;
m2_idx_evn <= m2_idx_evn - 1;
m2_last <= (m2_idx_evn == 2);
end
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0)
su_c <= 0;
else if (enable) begin
case (smu)
UP_B: begin
if (m1_last) su_c <= 1;
else if (s1_last) su_c <= 0;
else su_c <= aux_v12r;
end
UP_S: begin
if (m0_last) su_c <= 1;
else if (s1_last) su_c <= 0;
else su_c <= aux_v11r;
end
UP_M: begin
if (m1_last) su_c <= 1;
else if (s0_last) su_c <= 0;
else su_c <= aux_v02r;
end
default: begin
su_c <= 0;
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 1'b0)
mu_c <= 1;
else if (enable) begin
case (smu)
UP_B: begin
if (s1_last) mu_c <= 1;
else if (m1_last) mu_c <= 0;
else mu_c <= aux_v11;
end
UP_S: begin
if (s1_last) mu_c <= 1;
else if (m0_last) mu_c <= 0;
else mu_c <= aux_v10;
end
UP_M: begin
if (s0_last) mu_c <= 1;
else if (m1_last) mu_c <= 0;
else mu_c <= aux_v01;
end
default: begin
mu_c <= 0;
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_v <= 0;
s_vlast <= 0;
sm_last <= 0;
end
else if (enable) begin
case (smu)
UP_B: begin
if ((s1_last || aux_v11) && m1_last)
s_vlast <= 1;
else
s_vlast <= 0;
if (s1_last || aux_v11)
s_v <= 1;
else
s_v <= 0;
sm_last <= (s1_last && m1_last);
end
UP_S: begin
if ((s1_last || aux_v10) && m0_last)
s_vlast <= 1;
if ((s1_last || aux_v10) && ~s_vlast)
s_v <= 1;
else
s_v <= 0;
sm_last <= (s1_last && m0_last);
end
UP_M: begin
if ((s0_last || aux_v01) && m1_last)
s_vlast <= 1;
if (s0_last || aux_v01)
s_v <= m1_valid;
else
s_v <= 0;
sm_last <= (s0_last && m1_last);
end
default: begin
s_vlast <= 0;
s_v <= 0;
sm_last <= 0;
end
endcase
end
end
`define NEXT_SBMP(_r) \
_r[C_S_BMP-1:0] <= {_r[C_S_BMP-2:0], _r[C_S_BMP-1]}
`define NEXT_SBID(_r) \
_r[C_S_BID-1:0] <= (_r[C_S_BID-1:0] + 1)
`define NEXT_SIDX(_r) \
_r <= (s1_last ? 0 : (_r+1))
generate
if (C_S_BMP > 0) begin
reg [C_S_BMP-1:0] s_bmp[2:0];
assign s_bmp_bid_idx0[C_S_BMP+C_S_BID+C_S_IDX-1:C_S_BID+C_S_IDX] = s_bmp[0];
assign s_bmp_bid_idx1[C_S_BMP+C_S_BID+C_S_IDX-1:C_S_BID+C_S_IDX] = s_bmp[1];
assign s_bmp_bid_idx2[C_S_BMP+C_S_BID+C_S_IDX-1:C_S_BID+C_S_IDX] = s_bmp[2];
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_bmp[0] <= 0;
s_bmp[1] <= 0;
s_bmp[2] <= 1;
end
else if (enable) begin
case (smu)
UP_B: begin
if ((s1_last && aux_v11r) || sm_last)
s_bmp[0] <= s_bmp[2];
else
s_bmp[0] <= s_bmp[1];
s_bmp[1] <= s_bmp[2];
`NEXT_SBMP(s_bmp[2]);
end
UP_S: begin
if (s1_last && aux_v10r)
s_bmp[0] <= s_bmp[2];
else
s_bmp[0] <= s_bmp[1];
s_bmp[1] <= s_bmp[2];
`NEXT_SBMP(s_bmp[2]);
end
UP_M: begin
if (s0_last && aux_v01r)
s_bmp[0] <= s_bmp[1];
end
default: begin
s_bmp[0] <= 0;
s_bmp[1] <= 0;
s_bmp[2] <= 1;
end
endcase
end
end
end
if (C_S_BID > 0) begin
reg [C_S_BID-1:0] s_bid[2:0];
assign s_bmp_bid_idx0[C_S_BID+C_S_IDX-1:C_S_IDX] = s_bid[0];
assign s_bmp_bid_idx1[C_S_BID+C_S_IDX-1:C_S_IDX] = s_bid[1];
assign s_bmp_bid_idx2[C_S_BID+C_S_IDX-1:C_S_IDX] = s_bid[2];
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_bid[0] <= 0;
s_bid[1] <= 0;
s_bid[2] <= 0; /// 0 is the first
end
else if (enable) begin
case (smu)
UP_B: begin
if ((s1_last && aux_v11r) || sm_last)
s_bid[0] <= s_bid[2];
else
s_bid[0] <= s_bid[1];
s_bid[1] <= s_bid[2];
`NEXT_SBID(s_bid[2]);
end
UP_S: begin
if (s1_last && aux_v10r)
s_bid[0] <= s_bid[2];
else
s_bid[0] <= s_bid[1];
s_bid[1] <= s_bid[2];
`NEXT_SBID(s_bid[2]);
end
UP_M: begin
if (s0_last && aux_v01r)
s_bid[0] <= s_bid[1];
end
default: begin
s_bid[0] <= 0;
s_bid[1] <= 0;
s_bid[2] <= 0;
end
endcase
end
end
end
if (C_S_IDX > 0) begin
reg [C_S_WIDTH-1:0] s_idx[2:0];
assign s_bmp_bid_idx0[C_S_IDX-1:0] = s_idx[0];
assign s_bmp_bid_idx1[C_S_IDX-1:0] = s_idx[1];
assign s_bmp_bid_idx2[C_S_IDX-1:0] = s_idx[2];
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_idx[0] <= 0;
s_idx[1] <= 0;
s_idx[2] <= 0;
end
else if (enable) begin
case (smu)
UP_B: begin
if ((s1_last && aux_v11r) || sm_last)
s_idx[0] <= s_idx[2];
else
s_idx[0] <= s_idx[1];
s_idx[1] <= s_idx[2];
`NEXT_SIDX(s_idx[2]);
end
UP_S: begin
if (s1_last && aux_v10r)
s_idx[0] <= s_idx[2];
else
s_idx[0] <= s_idx[1];
s_idx[1] <= s_idx[2];
`NEXT_SIDX(s_idx[2]);
end
UP_M: begin
if (s0_last && aux_v01r)
s_idx[0] <= s_idx[1];
end
default: begin
s_idx[0] <= 0;
s_idx[1] <= 0;
s_idx[2] <= 0;
end
endcase
end
end
end
endgenerate
always @ (posedge clk) begin
if (resetn == 1'b0)
sm_valid <= 0;
else if (enable) begin
if (su_c && mu_c)
sm_valid <= 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_SYMBOL_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_4_V
`define SKY130_FD_SC_LS__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_4_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file digit.v when simulating
// the core, digit. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module digit(
clka,
addra,
douta
);
input clka;
input [13 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("digit.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(10240),
.C_READ_DEPTH_B(10240),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(10240),
.C_WRITE_DEPTH_B(10240),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pipe_wrapper.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
// pipe_wrapper.v
// pipe_clock.v
// pipe_reset.v or gtp_pipe_reset.v
// qpll_reset.v
// * Generate GTXE2_CHANNEL for every lane.
// pipe_user.v
// pipe_rate.v or gtp_pipe_rate.v
// pipe_sync.v
// pipe_drp.v or gtp_pipe_drp.v
// pipe_eq.v
// rxeq_scan.v
// gt_wrapper.v
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
// * Generate GTXE2_COMMON for every quad.
// qpll_drp.v
// qpll_wrapper.v
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
// : "TRUE" = Simulation only
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
// PCIE_GT_DEVICE : "GTX" (default)
// : "GTH"
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
// : "LPM" for Gen3 only (default) (GTX, GTH)
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
// : "TRUE" = Use external clock module
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
// : "TRUE" = Enable PLL power saving (default)
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
// : "TRUE" = Asynchronous mode.
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
// : "TRUE" = RX buffer use for Gen3 only (default)
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
// : 1 = Auto TX sync (GTH)
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
// : 1 = Auto RX sync (GTH)
// PCIE_CHAN_BOND : 0 = One-Hop (default)
// : 1 = Daisy-Chain
// : 2 = Binary-Tree
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
// PCIE_LANE : 1 (default), 2, 4, or 8
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
// : 2 = PCIe Gen1/Gen2 Mode (default)
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
// : 1 = 125 MHz
// : 2 = 250 MHz
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
// : 1 = Return TX preset #5
// PCIE_OOBCLK_MODE : 0 = Reference clock
// : 1 = 62.50 MHz (default)
// : 2 = 50.00 MHz (requires 1 BUFG)
// PCIE_JTAG_MODE : 0 = Normal operation (default)
// : 1 = JTAG mode (for debug only)
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
// : 1 = Debug mode (for debug only)
//------------------------------------------------------------------------------
//---------- Notes -------------------------------------------------------------
// Notes within the PIPE Wrapper RTL files are for internal use only.
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
// In Gen3 mode, all 32-bits are used.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Wrapper ------------------------------------------------------
module PCIEBus_pipe_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
//--------------------------------------
( // Gen1/Gen2 | Gen3
//--------------------------------------
//---------- PIPE Clock & Reset Ports ------------------
input PIPE_CLK, // Reference clock that drives MMCM
input PIPE_RESET_N, // PCLK | PCLK
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
// Drives TXUSRCLK in Gen3
// Drives RXUSRCLK in Gen3 async mode only
//---------- PIPE TX Data Ports ------------------------
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
//---------- PIPE RX Data Ports ------------------------
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
//---------- PIPE Command Ports ------------------------
input PIPE_TXDETECTRX, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
input [ 1:0] PIPE_RATE, // PCLK | PCLK
//---------- PIPE Electrical Command Ports -------------
input [ 2:0] PIPE_TXMARGIN, // Async | Async
input PIPE_TXSWING, // Async | Async
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
// output [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE, // PCLK | PCLK
//---------- PIPE Status Ports -------------------------
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
output PIPE_PCLK_LOCK, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
output PIPE_USERCLK1, // Optional user clock
output PIPE_USERCLK2, // Optional user clock
output PIPE_RXUSRCLK, // RXUSRCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
//---------- PRBS/Loopback Ports -----------------------
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
//---------- FSM Ports ---------------------------------
output [10:0] PIPE_RST_FSM, // PCLK | PCLK
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
output [(PCIE_LANE*31)-1:0]PIPE_RATE_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
output PIPE_RST_IDLE, // PCLK | PCLK
output PIPE_QRST_IDLE, // PCLK | PCLK
output PIPE_RATE_IDLE, // PCLK | PCLK
//---------- JTAG Ports --------------------------------
input PIPE_JTAG_EN, // DCLK | DCLK
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
//---------- Debug Ports -------------------------------
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
output [31:0] PIPE_DEBUG, // Async | Async
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
//---------- PIPE Clock Module Output ------------------
wire clk_pclk;
wire clk_rxusrclk;
wire [PCIE_LANE-1:0] clk_rxoutclk;
wire clk_dclk;
wire clk_oobclk;
wire clk_mmcm_lock;
//---------- PIPE Reset Module Output ------------------
wire rst_cpllreset;
wire rst_cpllpd;
wire rst_rxusrclk_reset;
wire rst_dclk_reset;
wire rst_gtreset;
wire rst_drp_start;
wire rst_drp_x16x20_mode;
wire rst_drp_x16;
wire rst_userrdy;
wire rst_txsync_start;
wire rst_idle;
wire [ 4:0] rst_fsm;
//------------------------------------------------------
wire gtp_rst_qpllreset; // GTP
wire gtp_rst_qpllpd; // GTP
//------------------------------------------------------
wire [(PCIE_LANE-1)>>2:0]qpllreset;
wire qpllpd;
//---------- QPLL Reset Module Output ------------------
wire qrst_ovrd;
wire qrst_drp_start;
wire qrst_qpllreset;
wire qrst_qpllpd;
wire qrst_idle;
wire [ 3:0] qrst_fsm;
//---------- PIPE_JTAG Master Module Output ------------
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
//---------- PIPE User Module Output -------------------
wire [PCIE_LANE-1:0] user_oobclk;
wire [PCIE_LANE-1:0] user_resetovrd;
wire [PCIE_LANE-1:0] user_txpmareset;
wire [PCIE_LANE-1:0] user_rxpmareset;
wire [PCIE_LANE-1:0] user_rxcdrreset;
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
wire [PCIE_LANE-1:0] user_eyescanreset;
wire [PCIE_LANE-1:0] user_txpcsreset;
wire [PCIE_LANE-1:0] user_rxpcsreset;
wire [PCIE_LANE-1:0] user_rxbufreset;
wire [PCIE_LANE-1:0] user_resetovrd_done;
wire [PCIE_LANE-1:0] user_active_lane;
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
wire [PCIE_LANE-1:0] user_rxcdrlock;
wire [PCIE_LANE-1:0] user_rx_converge;
//---------- PIPE Rate Module Output -------------------
wire [PCIE_LANE-1:0] rate_cpllpd;
wire [PCIE_LANE-1:0] rate_qpllpd;
wire [PCIE_LANE-1:0] rate_cpllreset;
wire [PCIE_LANE-1:0] rate_qpllreset;
wire [PCIE_LANE-1:0] rate_txpmareset;
wire [PCIE_LANE-1:0] rate_rxpmareset;
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
wire [PCIE_LANE-1:0] rate_pclk_sel;
wire [PCIE_LANE-1:0] rate_drp_start;
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
wire [PCIE_LANE-1:0] rate_drp_x16;
wire [PCIE_LANE-1:0] rate_gen3;
wire [(PCIE_LANE*3)-1:0] rate_rate;
wire [PCIE_LANE-1:0] rate_resetovrd_start;
wire [PCIE_LANE-1:0] rate_txsync_start;
wire [PCIE_LANE-1:0] rate_done;
wire [PCIE_LANE-1:0] rate_rxsync_start;
wire [PCIE_LANE-1:0] rate_rxsync;
wire [PCIE_LANE-1:0] rate_idle;
wire [(PCIE_LANE*5)-1:0]rate_fsm;
//---------- PIPE Sync Module Output -------------------
wire [PCIE_LANE-1:0] sync_txphdlyreset;
wire [PCIE_LANE-1:0] sync_txphalign;
wire [PCIE_LANE-1:0] sync_txphalignen;
wire [PCIE_LANE-1:0] sync_txphinit;
wire [PCIE_LANE-1:0] sync_txdlybypass;
wire [PCIE_LANE-1:0] sync_txdlysreset;
wire [PCIE_LANE-1:0] sync_txdlyen;
wire [PCIE_LANE-1:0] sync_txsync_done;
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
wire [PCIE_LANE-1:0] sync_rxphalign;
wire [PCIE_LANE-1:0] sync_rxphalignen;
wire [PCIE_LANE-1:0] sync_rxdlybypass;
wire [PCIE_LANE-1:0] sync_rxdlysreset;
wire [PCIE_LANE-1:0] sync_rxdlyen;
wire [PCIE_LANE-1:0] sync_rxddien;
wire [PCIE_LANE-1:0] sync_rxsync_done;
wire [PCIE_LANE-1:0] sync_rxsync_donem;
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
wire [PCIE_LANE-1:0] txdlysresetdone;
wire [PCIE_LANE-1:0] txphaligndone;
wire [PCIE_LANE-1:0] rxdlysresetdone;
wire [PCIE_LANE-1:0] rxphaligndone_s;
wire txsyncallin; // GTH
wire rxsyncallin; // GTH
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE*9)-1:0] drp_addr;
wire [PCIE_LANE-1:0] drp_en;
wire [(PCIE_LANE*16)-1:0]drp_di;
wire [PCIE_LANE-1:0] drp_we;
wire [PCIE_LANE-1:0] drp_done;
wire [(PCIE_LANE*3)-1:0] drp_fsm;
//---------- PIPE JTAG Slave Module Output--------------
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
wire [PCIE_LANE-1:0] jtag_sl_den;
wire [PCIE_LANE-1:0] jtag_sl_en;
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
wire [PCIE_LANE-1:0] jtag_sl_we;
//---------- PIPE DRP MUX Output -----------------------
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
wire [PCIE_LANE-1:0] drp_mux_en;
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
wire [PCIE_LANE-1:0] drp_mux_we;
//---------- PIPE EQ Module Output ---------------------
wire [PCIE_LANE-1:0] eq_txeq_deemph;
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
//---------- PIPE DRP Module Output --------------------
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
//---------- QPLL Wrapper Output -----------------------
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
//---------- GTX Wrapper Output ------------------------
wire [PCIE_LANE-1:0] gt_txoutclk;
wire [PCIE_LANE-1:0] gt_rxoutclk;
wire [PCIE_LANE-1:0] gt_cplllock;
wire [PCIE_LANE-1:0] gt_rxcdrlock;
wire [PCIE_LANE-1:0] gt_txresetdone;
wire [PCIE_LANE-1:0] gt_rxresetdone;
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
wire [PCIE_LANE-1:0] gt_rxvalid;
wire [PCIE_LANE-1:0] gt_phystatus;
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
wire [PCIE_LANE-1:0] gt_rxelecidle;
wire [PCIE_LANE-1:0] gt_txratedone;
wire [PCIE_LANE-1:0] gt_rxratedone;
wire [(PCIE_LANE*16)-1:0]gt_do;
wire [PCIE_LANE-1:0] gt_rdy;
wire [PCIE_LANE-1:0] gt_txphinitdone;
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
wire [PCIE_LANE-1:0] gt_txphaligndone;
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxcommadet;
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
wire [PCIE_LANE-1:0] gt_rxbyterealign;
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
wire [PCIE_LANE-1:0] rxchbonden;
wire [PCIE_LANE-1:0] rxchbondmaster;
wire [PCIE_LANE-1:0] rxchbondslave;
wire [PCIE_LANE-1:0] oobclk;
//---------- TX EQ -------------------------------------
localparam TXEQ_FS = 6'd40; // TX equalization full swing
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
//---------- Select JTAG Slave Type ----------------------------------------
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Assignments -------------------------------------------------------
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
//---------- Reset Synchronizer ------------------------------------------------
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
begin
if (!PIPE_RESET_N)
begin
reset_n_reg1 <= 1'd0;
reset_n_reg2 <= 1'd0;
end
else
begin
reset_n_reg1 <= 1'd1;
reset_n_reg2 <= reset_n_reg1;
end
end
//---------- PIPE Clock Module -------------------------------------------------
generate
if (PCIE_EXT_CLK == "FALSE")
begin : pipe_clock_int
PCIEBus_pipe_clock #
(
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
//.CLK_RST_N (1'b1),
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_GEN3 (rate_gen3[0]),
//---------- Output ------------------------------------
.CLK_PCLK (clk_pclk),
.CLK_RXUSRCLK (clk_rxusrclk),
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
.CLK_DCLK (clk_dclk),
.CLK_USERCLK1 (PIPE_USERCLK1),
.CLK_USERCLK2 (PIPE_USERCLK2),
.CLK_OOBCLK (clk_oobclk),
.CLK_MMCM_LOCK (clk_mmcm_lock)
);
end
else
//---------- PIPE Clock External ---------------------------------------
begin : pipe_clock_int_disable
assign clk_pclk = PIPE_PCLK_IN;
assign clk_rxusrclk = PIPE_RXUSRCLK_IN;
assign clk_rxoutclk = PIPE_RXOUTCLK_IN;
assign clk_dclk = PIPE_DCLK_IN;
assign PIPE_USERCLK1 = PIPE_USERCLK1_IN;
assign PIPE_USERCLK2 = PIPE_USERCLK2_IN;
assign clk_oobclk = PIPE_OOBCLK_IN;
assign clk_mmcm_lock = PIPE_MMCM_LOCK_IN;
end
endgenerate
//---------- PIPE Reset Module -------------------------------------------------
generate
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_reset
//---------- GTP PIPE Reset Module -------------------------------------
PCIEBus_gtp_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
gtp_pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_PLLLOCK (&qpll_qplllock),
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm)
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = rst_cpllreset;
assign gtp_rst_qpllpd = rst_cpllpd;
end
else
begin : pipe_reset
//---------- PIPE Reset Module -----------------------------------------
PCIEBus_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_CPLLLOCK (gt_cplllock),
.RST_QPLL_IDLE (qrst_idle),
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm[4:0])
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = 1'd0;
assign gtp_rst_qpllpd = 1'd0;
end
endgenerate
//---------- QPLL Reset Module -------------------------------------------------
generate
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
begin : qpll_reset
PCIEBus_qpll_reset #
(
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
qpll_reset_i
(
//---------- Input ---------------------------------
.QRST_CLK (clk_pclk),
.QRST_RST_N (reset_n_reg2),
.QRST_MMCM_LOCK (clk_mmcm_lock),
.QRST_CPLLLOCK (gt_cplllock),
.QRST_DRP_DONE (qdrp_done),
.QRST_QPLLLOCK (qpll_qplllock),
.QRST_RATE (PIPE_RATE),
.QRST_QPLLRESET_IN (rate_qpllreset),
.QRST_QPLLPD_IN (rate_qpllpd),
//---------- Output --------------------------------
.QRST_OVRD (qrst_ovrd),
.QRST_DRP_START (qrst_drp_start),
.QRST_QPLLRESET_OUT (qrst_qpllreset),
.QRST_QPLLPD_OUT (qrst_qpllpd),
.QRST_IDLE (qrst_idle),
.QRST_FSM (qrst_fsm)
);
end
else
//---------- QPLL Reset Defaults ---------------------------------------
begin : qpll_reset_disable
assign qrst_ovrd = 1'd0;
assign qrst_drp_start = 1'd0;
assign qrst_qpllreset = 1'd0;
assign qrst_qpllpd = 1'd0;
assign qrst_idle = 1'd0;
assign qrst_fsm = 4'd1;
end
endgenerate
//---------- Generate PIPE JTAG Master -----------------------------------------
generate
if (PCIE_JTAG_MODE == 1)
begin : pipe_jtag_m
//-------------PIPE JTAG Master Module ---------------------------------
pipe_jtag_m #
(
.PCIE_LANE (PCIE_LANE)
)
pipe_jtag_m_i
(
//---------- Connect to JTAG Slave -------------
.JTAG_SL_IPORT (jtag_sl_iport), //
.JTAG_SL_OPORT (jtag_sl_oport),
//---------- Input -----------------------------
.JTAG_M_CLK (clk_dclk)
);
end
else
begin : pipe_jtag_m_disable
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
end
endgenerate
//---------- Generate PIPE Lane ------------------------------------------------
generate for (i=0; i<PCIE_LANE; i=i+1)
begin : pipe_lane
//---------- PIPE User Module ----------------------------------------------
PCIEBus_pipe_user #
(
.PCIE_USE_MODE (PCIE_USE_MODE),
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
)
pipe_user_i
(
//---------- Input ---------------------------------
.USER_TXUSRCLK (clk_pclk),
.USER_RXUSRCLK (clk_rxusrclk),
.USER_OOBCLK_IN (clk_oobclk),
.USER_RST_N (!rst_cpllreset),
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
.USER_PCLK_SEL (rate_pclk_sel[i]),
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
.USER_TXRESETDONE (gt_txresetdone[i]),
.USER_RXRESETDONE (gt_rxresetdone[i]),
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
.USER_RXVALID_IN (gt_rxvalid[i]),
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
.USER_PHYSTATUS_IN (gt_phystatus[i]),
.USER_RATE_DONE (rate_done[i]),
.USER_RST_IDLE (rst_idle),
.USER_RATE_RXSYNC (rate_rxsync[i]),
.USER_RATE_IDLE (rate_idle[i]),
.USER_RATE_GEN3 (rate_gen3[i]),
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
//---------- Output --------------------------------
.USER_OOBCLK (user_oobclk[i]),
.USER_RESETOVRD (user_resetovrd[i]),
.USER_TXPMARESET (user_txpmareset[i]),
.USER_RXPMARESET (user_rxpmareset[i]),
.USER_RXCDRRESET (user_rxcdrreset[i]),
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
.USER_EYESCANRESET (user_eyescanreset[i]),
.USER_TXPCSRESET (user_txpcsreset[i]),
.USER_RXPCSRESET (user_rxpcsreset[i]),
.USER_RXBUFRESET (user_rxbufreset[i]),
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
.USER_RESETDONE (user_resetdone[i]),
.USER_ACTIVE_LANE (user_active_lane[i]),
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
.USER_RX_CONVERGE (user_rx_converge[i])
);
//---------- GTP PIPE Rate Module ------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_rate
PCIEBus_gtp_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
)
gtp_pipe_rate_i
(
//---------- Input -----------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
//.RATE_RST_IDLE (rst_idle), // removed for GTP
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
.RATE_RATE_IN (PIPE_RATE),
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
//---------- Output ----------------------------
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
//---------- Default for GTP -----------------------
assign rate_cpllpd[i] = 1'd0;
assign rate_qpllpd[i] = 1'd0;
assign rate_cpllreset[i] = 1'd0;
assign rate_qpllreset[i] = 1'd0;
assign rate_txpmareset[i] = 1'd0;
assign rate_rxpmareset[i] = 1'd0;
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
assign rate_gen3[i] = 1'd0;
assign rate_resetovrd_start[i] = 1'd0;
assign rate_rxsync_start[i] = 1'd0;
assign rate_rxsync[i] = 1'd0;
end
else
begin : pipe_rate
//---------- PIPE Rate Module ----------------------------------------------
PCIEBus_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
)
pipe_rate_i
(
//---------- Input ---------------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
.RATE_RST_IDLE (rst_idle),
.RATE_ACTIVE_LANE (user_active_lane[i]),
.RATE_RATE_IN (PIPE_RATE),
.RATE_CPLLLOCK (gt_cplllock[i]),
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
.RATE_MMCM_LOCK (clk_mmcm_lock),
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
.RATE_TXRESETDONE (gt_txresetdone[i]),
.RATE_RXRESETDONE (gt_rxresetdone[i]),
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
//---------- Output --------------------------------
.RATE_CPLLPD (rate_cpllpd[i]),
.RATE_QPLLPD (rate_qpllpd[i]),
.RATE_CPLLRESET (rate_cpllreset[i]),
.RATE_QPLLRESET (rate_qpllreset[i]),
.RATE_TXPMARESET (rate_txpmareset[i]),
.RATE_RXPMARESET (rate_rxpmareset[i]),
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
.RATE_GEN3 (rate_gen3[i]),
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
.RATE_RXSYNC_START (rate_rxsync_start[i]),
.RATE_RXSYNC (rate_rxsync[i]),
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
end
//---------- PIPE Sync Module ----------------------------------------------
PCIEBus_pipe_sync #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_LANE (PCIE_LANE), // PCIe lane
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
)
pipe_sync_i
(
//---------- Input ---------------------------------
.SYNC_CLK (clk_pclk),
.SYNC_RST_N (!rst_cpllreset),
.SYNC_SLAVE (i > 0),
.SYNC_GEN3 (rate_gen3[i]),
.SYNC_RATE_IDLE (rate_idle[i]),
.SYNC_MMCM_LOCK (clk_mmcm_lock),
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
.SYNC_ACTIVE_LANE (user_active_lane[i]),
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- Output --------------------------------
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
.SYNC_TXPHALIGN (sync_txphalign[i]),
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
.SYNC_TXPHINIT (sync_txphinit[i]),
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
.SYNC_TXDLYEN (sync_txdlyen[i]),
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
.SYNC_RXPHALIGN (sync_rxphalign[i]),
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
.SYNC_RXDLYEN (sync_rxdlyen[i]),
.SYNC_RXDDIEN (sync_rxddien[i]),
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
);
//---------- PIPE Sync Assignments -----------------------------------------
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
//---------- GTP PIPE DRP Module -------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_drp
//---------- GTP PIPE DRP Module ---------------------------------------
PCIEBus_gtp_pipe_drp
//(
//.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // removed for GTP
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // removed for GTP
//.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // removed for GTP
//.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // removed for GTP
//)
gtp_pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
//.DRP_GTXRESET (rst_gtreset), // removed for GTP
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
//.DRP_RATE (PIPE_RATE), // removed for GTP
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
else
begin : pipe_drp
//---------- PIPE DRP Module -------------------------------------------
PCIEBus_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
)
pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_GTXRESET (rst_gtreset),
.DRP_RATE (PIPE_RATE),
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
//---------- Generate PIPE JTAG Slave --------------------------------------
if (PCIE_JTAG_MODE == 1)
begin : pipe_jtag_s
//-------------PIPE JTAG Slave Module ----------------------------------
pipe_jtag_s #
(
.GC_XSDB_SLAVE_TYPE (GC_XSDB_SLAVE_TYPE)
)
pipe_jtag_s_i
(
//---------- Connect to JTAG Master ------------
.JTAG_SL_I_PORT (jtag_sl_iport[((i+1)*37)-1 : (i*37)]),
.JTAG_SL_O_PORT (jtag_sl_oport[((i+1)*17)-1 : (i*17)]),
//---------- Input -----------------------------
.JTAG_SL_DRDY (gt_rdy[i]),
.JTAG_SL_DO (gt_do[(16*i)+15:(16*i)]),
//---------- Output ----------------------------
.JTAG_SL_DCLK (),
.JTAG_SL_ADDR (jtag_sl_addr[(17*i)+16:(17*i)]),
.JTAG_SL_DEN (jtag_sl_den[i]),
.JTAG_SL_DI (jtag_sl_di[(16*i)+15:(16*i)]),
.JTAG_SL_DWE (jtag_sl_we[i])
);
end
else
//---------- PIPE JTAG Slave Default ----------------------------------
begin : pipe_jtag_s_disable
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
assign jtag_sl_den[i] = 1'd0;
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
assign jtag_sl_we[i] = 1'd0;
end
//---------- Generate DRP MUX ----------------------------------------------
assign PIPE_JTAG_RDY[i] = drp_fsm[3*i];
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
assign drp_mux_addr[(9*i)+8:(9*i)] = PIPE_JTAG_EN ? jtag_sl_addr[(17*i)+8:(17*i)] : drp_addr[(9*i)+8:(9*i)];
assign drp_mux_en[i] = PIPE_JTAG_EN ? jtag_sl_en[i] : drp_en[i];
assign drp_mux_di[(16*i)+15:(16*i)] = PIPE_JTAG_EN ? jtag_sl_di[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
assign drp_mux_we[i] = PIPE_JTAG_EN ? jtag_sl_we[i] : drp_we[i];
//---------- Generate PIPE EQ ----------------------------------------------
if (PCIE_LINK_SPEED == 3)
begin : pipe_eq
//---------- PIPE EQ Module --------------------------------------------
PCIEBus_pipe_eq #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
)
pipe_eq_i
(
//---------- Input -----------------------------
.EQ_CLK (clk_pclk),
.EQ_RST_N (!rst_cpllreset),
.EQ_GEN3 (rate_gen3[i]),
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
//---------- Output ----------------------------
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
);
end
else
//---------- PIPE EQ Defaults ------------------------------------------
begin : pipe_eq_disable
assign eq_txeq_deemph[i] = 1'd0;
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_rxeq_adapt_done[i] = 1'd0;
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_TXEQ_DONE[i] = 1'd0;
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
assign PIPE_RXEQ_DONE[i] = 1'd0;
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
end
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
if ((i%4)==0)
begin : pipe_quad
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
begin : pipe_common
//---------- QPLL DRP Module ---------------------------------------
PCIEBus_qpll_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_drp_i
(
//---------- Input -------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_OVRD (qrst_ovrd),
.DRP_GEN3 (&rate_gen3),
.DRP_QPLLLOCK (qpll_qplllock[i>>2]),
.DRP_START (qrst_drp_start),
.DRP_DO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
.DRP_RDY (qpll_rdy[i>>2]),
//---------- Output ------------------------
.DRP_ADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
.DRP_EN (qdrp_en[i>>2]),
.DRP_DI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
.DRP_WE (qdrp_we[i>>2]),
.DRP_DONE (qdrp_done[i>>2]),
.DRP_QPLLRESET (qdrp_qpllreset[i>>2]),
.DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
.DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))])
);
//---------- QPLL Wrapper ------------------------------------------
PCIEBus_qpll_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_wrapper_i
(
//---------- QPLL Clock Ports --------------
.QPLL_GTGREFCLK (PIPE_CLK),
.QPLL_QPLLLOCKDETCLK (1'd0),
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
.QPLL_QPLLLOCK (qpll_qplllock[i>>2]),
//---------- QPLL Reset Ports --------------
.QPLL_QPLLPD (qpllpd),
.QPLL_QPLLRESET (qpllreset[i>>2]),
//---------- QPLL DRP Ports ----------------
.QPLL_DRPCLK (clk_dclk),
.QPLL_DRPADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
.QPLL_DRPEN (qdrp_en[i>>2]),
.QPLL_DRPDI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
.QPLL_DRPWE (qdrp_we[i>>2]),
.QPLL_DRPDO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
.QPLL_DRPRDY (qpll_rdy[i>>2])
);
end
else
//---------- PIPE Common Defaults ----------------------------------
begin : pipe_common_disable
assign qdrp_addr[(8*(i>>2))+7:(8*(i>>2))] = 8'd0;
assign qdrp_en[i>>2] = 1'd0;
assign qdrp_di[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
assign qdrp_we[i>>2] = 1'd0;
assign qdrp_done[i>>2] = 1'd0;
assign qdrp_qpllreset[i>>2] = 1'd0;
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 7'd0;
assign qpll_qplloutclk[i>>2] = 1'd0;
assign qpll_qplloutrefclk[i>>2] = 1'd0;
assign qpll_qplllock[i>>2] = 1'd0;
assign qpll_do[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
assign qpll_rdy[i>>2] = 1'd0;
end
//---------- Generate QPLL Powerdown and Reset -------------------------
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
end
//---------- GT Wrapper ----------------------------------------------------
PCIEBus_gt_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
gt_wrapper_i
(
//---------- GT User Ports -------------------------
.GT_MASTER (i == 0),
.GT_GEN3 (rate_gen3[i]),
.GT_RX_CONVERGE (&user_rx_converge),
//---------- GT Clock Ports ------------------------
.GT_GTREFCLK0 (PIPE_CLK),
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
.GT_TXUSRCLK (clk_pclk),
.GT_RXUSRCLK (clk_rxusrclk),
.GT_TXUSRCLK2 (clk_pclk),
.GT_RXUSRCLK2 (clk_rxusrclk),
.GT_OOBCLK (oobclk[i]),
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_TXOUTCLK (gt_txoutclk[i]),
.GT_RXOUTCLK (gt_rxoutclk[i]),
.GT_CPLLLOCK (gt_cplllock[i]),
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
//---------- GT Reset Ports ------------------------
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
.GT_TXUSERRDY (rst_userrdy),
.GT_RXUSERRDY (rst_userrdy),
.GT_RESETOVRD (user_resetovrd[i]),
.GT_GTTXRESET (rst_gtreset),
.GT_GTRXRESET (rst_gtreset),
.GT_TXPMARESET (user_txpmareset[i] || rate_txpmareset[i]),
.GT_RXPMARESET (user_rxpmareset[i] || rate_rxpmareset[i]),
.GT_RXCDRRESET (user_rxcdrreset[i]),
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
.GT_EYESCANRESET (user_eyescanreset[i]),
.GT_TXPCSRESET (user_txpcsreset[i]),
.GT_RXPCSRESET (user_rxpcsreset[i]),
.GT_RXBUFRESET (user_rxbufreset[i]),
.GT_TXRESETDONE (gt_txresetdone[i]),
.GT_RXRESETDONE (gt_rxresetdone[i]),
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//---------- GT TX Data Ports ----------------------
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
.GT_TXP (PIPE_TXP[i]),
.GT_TXN (PIPE_TXN[i]),
//---------- GT RX Data Ports ----------------------
.GT_RXP (PIPE_RXP[i]),
.GT_RXN (PIPE_RXN[i]),
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
//---------- GT Command Ports ----------------------
.GT_TXDETECTRX (PIPE_TXDETECTRX),
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
//---------- GT Electrical Command Ports -----------
.GT_TXMARGIN (PIPE_TXMARGIN),
.GT_TXSWING (PIPE_TXSWING),
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
//---------- GT Status Ports -----------------------
.GT_RXVALID (gt_rxvalid[i]),
.GT_PHYSTATUS (gt_phystatus[i]),
.GT_RXELECIDLE (gt_rxelecidle[i]),
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
.GT_TXRATEDONE (gt_txratedone[i]),
.GT_RXRATEDONE (gt_rxratedone[i]),
//---------- GT DRP Ports --------------------------
.GT_DRPCLK (clk_dclk),
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
.GT_DRPEN (drp_mux_en[i]),
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
.GT_DRPWE (drp_mux_we[i]),
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
.GT_DRPRDY (gt_rdy[i]),
//---------- GT TX Sync Ports ----------------------
.GT_TXPHALIGN (sync_txphalign[i]),
.GT_TXPHALIGNEN (sync_txphalignen[i]),
.GT_TXPHINIT (sync_txphinit[i]),
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
.GT_TXDLYSRESET (sync_txdlysreset[i]),
.GT_TXDLYEN (sync_txdlyen[i]),
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
.GT_TXPHINITDONE (gt_txphinitdone[i]),
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
.GT_TXSYNCMODE (i == 0), // GTH, GTP
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
//---------- GT RX Sync Ports ----------------------
.GT_RXPHALIGN (sync_rxphalign[i]),
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
.GT_RXDLYEN (sync_rxdlyen[i]),
.GT_RXDDIEN (sync_rxddien[i]),
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
.GT_RXSYNCMODE (i == 0), // GTH
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
.GT_RXSYNCALLIN (rxsyncallin), // GTH
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- GT Comma Alignment Ports --------------
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
.GT_RXCOMMADET (gt_rxcommadet[i]),
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
//---------- GT Channel Bonding Ports --------------
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
.GT_RXCHBONDEN (rxchbonden[i]),
.GT_RXCHBONDI (gt_rxchbondi[i]),
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
//---------- GT PRBS/Loopback Ports ----------------
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
.GT_LOOPBACK (PIPE_LOOPBACK),
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
//---------- GT Debug Port -------------------------
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
);
//---------- GT Wrapper Assignments ----------------------------------------
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
//---------- Channel Bonding Master Slave Enable ---------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_ms_disable
assign rxchbonden[i] = 1'd0;
assign rxchbondmaster[i] = 1'd0;
assign rxchbondslave[i] = 1'd0;
end
else
begin : channel_bonding_ms_enable
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
end
//---------- Channel Bonding Input Connection ------------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_in_disable
assign gt_rxchbondi[i] = 5'd0;
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
else
begin : channel_bonding_in_enable
//---------- Channel Bonding (2: Binary-Tree) --------------------------
if (PCIE_CHAN_BOND == 2)
begin : channel_bonding_a
case (i)
//---------- Lane 0 --------------------------------
0 :
begin
assign gt_rxchbondi[0] = gt_rxchbondo[0];
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
(PCIE_LANE > 4'd5) ? 3'd3 :
(PCIE_LANE > 4'd3) ? 3'd2 :
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
end
//---------- Lane 1 --------------------------------
1 :
begin
assign gt_rxchbondi[1] = gt_rxchbondo[1];
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 2 --------------------------------
2 :
begin
assign gt_rxchbondi[2] = gt_rxchbondo[1];
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 3 --------------------------------
3 :
begin
assign gt_rxchbondi[3] = gt_rxchbondo[3];
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 4 --------------------------------
4 :
begin
assign gt_rxchbondi[4] = gt_rxchbondo[3];
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 5 --------------------------------
5 :
begin
assign gt_rxchbondi[5] = gt_rxchbondo[5];
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 6 --------------------------------
6 :
begin
assign gt_rxchbondi[6] = gt_rxchbondo[5];
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 7 --------------------------------
7 :
begin
assign gt_rxchbondi[7] = gt_rxchbondo[7];
assign gt_rxchbondlevel[23:21] = 3'd0;
end
//---------- Default -------------------------------
default :
begin
assign gt_rxchbondi[i] = gt_rxchbondo[7];
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
endcase
end
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
else
begin : channel_bonding_b
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
end
end
end
endgenerate
//---------- PIPE Wrapper Output -----------------------------------------------
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
assign PIPE_RXELECIDLE = gt_rxelecidle;
assign PIPE_RXSTATUS = gt_rxstatus;
assign PIPE_RXBUFSTATUS = 0;//gt_rxbufstatus;
assign PIPE_CPLL_LOCK = gt_cplllock;
assign PIPE_QPLL_LOCK = 0;//qpll_qplllock;
assign PIPE_PCLK = clk_pclk;
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
assign PIPE_GEN3_OUT = rate_gen3[0];
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
assign PIPE_RST_FSM = 0;//rst_fsm;
assign PIPE_QRST_FSM = 0;//qrst_fsm;
assign PIPE_RATE_FSM = 0;//rate_fsm;
assign PIPE_SYNC_FSM_TX = 0;//sync_fsm_tx;
assign PIPE_SYNC_FSM_RX = 0;//sync_fsm_rx;
assign PIPE_DRP_FSM = 0;//drp_fsm;
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
assign PIPE_RST_IDLE = 0;//&rst_idle;
assign PIPE_QRST_IDLE = 0;//&qrst_idle;
assign PIPE_RATE_IDLE = 0;//&rate_idle;
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
assign PIPE_DEBUG[31:6] = 26'd0;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spiCtrl.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Controls access to the 3 types of SPI access
//// Direct SPI access, SD initialisation, and SD block read/write
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
module spiCtrl (clk, readWriteSDBlockRdy, readWriteSDBlockReq, rst, rxDataRdy, rxDataRdyClr, SDInitReq, spiCS_n, spiTransCtrl, spiTransSts, spiTransType, txDataWen);
input clk;
input readWriteSDBlockRdy;
input rst;
input rxDataRdy;
input spiTransCtrl;
input [1:0]spiTransType;
output [1:0]readWriteSDBlockReq;
output rxDataRdyClr;
output SDInitReq;
output spiCS_n;
output spiTransSts;
output txDataWen;
wire clk;
wire readWriteSDBlockRdy;
reg [1:0]readWriteSDBlockReq, next_readWriteSDBlockReq;
wire rst;
wire rxDataRdy;
reg rxDataRdyClr, next_rxDataRdyClr;
reg SDInitReq, next_SDInitReq;
reg spiCS_n, next_spiCS_n;
wire spiTransCtrl;
reg spiTransSts, next_spiTransSts;
wire [1:0]spiTransType;
reg txDataWen, next_txDataWen;
// BINARY ENCODED state machine: spiCtrlSt
// State codes definitions:
`define ST_S_CTRL 3'b000
`define WT_S_CTRL_REQ 3'b001
`define WT_FIN1 3'b010
`define DIR_ACC 3'b011
`define INIT 3'b100
`define WT_FIN2 3'b101
`define RW 3'b110
`define WT_FIN3 3'b111
reg [2:0]CurrState_spiCtrlSt, NextState_spiCtrlSt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: spiCtrlSt
// NextState logic (combinatorial)
always @ (spiTransCtrl or rxDataRdy or spiTransType or readWriteSDBlockRdy or readWriteSDBlockReq or txDataWen or SDInitReq or rxDataRdyClr or spiTransSts or spiCS_n or CurrState_spiCtrlSt)
begin
NextState_spiCtrlSt <= CurrState_spiCtrlSt;
// Set default values for outputs and signals
next_readWriteSDBlockReq <= readWriteSDBlockReq;
next_txDataWen <= txDataWen;
next_SDInitReq <= SDInitReq;
next_rxDataRdyClr <= rxDataRdyClr;
next_spiTransSts <= spiTransSts;
next_spiCS_n <= spiCS_n;
case (CurrState_spiCtrlSt) // synopsys parallel_case full_case
`ST_S_CTRL:
begin
next_readWriteSDBlockReq <= `NO_BLOCK_REQ;
next_txDataWen <= 1'b0;
next_SDInitReq <= 1'b0;
next_rxDataRdyClr <= 1'b0;
next_spiTransSts <= `TRANS_NOT_BUSY;
next_spiCS_n <= 1'b1;
NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
end
`WT_S_CTRL_REQ:
begin
next_rxDataRdyClr <= 1'b0;
next_spiTransSts <= `TRANS_NOT_BUSY;
if ((spiTransCtrl == `TRANS_START) && (spiTransType == `INIT_SD))
begin
NextState_spiCtrlSt <= `INIT;
next_spiTransSts <= `TRANS_BUSY;
next_SDInitReq <= 1'b1;
next_txDataWen <= 1'b1;
next_spiCS_n <= 1'b0;
end
else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_WRITE_SD_BLOCK))
begin
NextState_spiCtrlSt <= `RW;
next_spiTransSts <= `TRANS_BUSY;
next_readWriteSDBlockReq <= `WRITE_SD_BLOCK;
end
else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_READ_SD_BLOCK))
begin
NextState_spiCtrlSt <= `RW;
next_spiTransSts <= `TRANS_BUSY;
next_readWriteSDBlockReq <= `READ_SD_BLOCK;
end
else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `DIRECT_ACCESS))
begin
NextState_spiCtrlSt <= `DIR_ACC;
next_spiTransSts <= `TRANS_BUSY;
next_txDataWen <= 1'b1;
next_spiCS_n <= 1'b0;
end
end
`WT_FIN1:
begin
if (rxDataRdy == 1'b1)
begin
NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
next_rxDataRdyClr <= 1'b1;
next_spiCS_n <= 1'b1;
end
end
`DIR_ACC:
begin
next_txDataWen <= 1'b0;
NextState_spiCtrlSt <= `WT_FIN1;
end
`INIT:
begin
next_txDataWen <= 1'b0;
NextState_spiCtrlSt <= `WT_FIN2;
end
`WT_FIN2:
begin
if (rxDataRdy == 1'b1)
begin
next_SDInitReq <= 1'b0;
NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
next_rxDataRdyClr <= 1'b1;
end
end
`RW:
begin
next_readWriteSDBlockReq <= `NO_BLOCK_REQ;
NextState_spiCtrlSt <= `WT_FIN3;
end
`WT_FIN3:
begin
if (readWriteSDBlockRdy == 1'b1)
begin
NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
end
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_spiCtrlSt <= `ST_S_CTRL;
else
CurrState_spiCtrlSt <= NextState_spiCtrlSt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
readWriteSDBlockReq <= `NO_BLOCK_REQ;
txDataWen <= 1'b0;
SDInitReq <= 1'b0;
rxDataRdyClr <= 1'b0;
spiTransSts <= `TRANS_NOT_BUSY;
spiCS_n <= 1'b1;
end
else
begin
readWriteSDBlockReq <= next_readWriteSDBlockReq;
txDataWen <= next_txDataWen;
SDInitReq <= next_SDInitReq;
rxDataRdyClr <= next_rxDataRdyClr;
spiTransSts <= next_spiTransSts;
spiCS_n <= next_spiCS_n;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
|
//wb_gpio.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
8/31/2012
-Changed some of the naming for clarity
10/29/2011
-added an 'else' statement that so either the
reset HDL will be executed or the actual code
not both
10/23/2011
-fixed the wbs_ack_i to o_wbs_ack
-added the default entries for read and write
to illustrate the method of communication
-added license
9/10/2011
-removed the duplicate wbs_dat_i
-added the wbs_sel_i port
*/
/*
Use this to tell sycamore how to populate the Device ROM table
so that users can interact with your slave
META DATA
identification of your device 0 - 65536
DRT_ID: 1
flags (read drt.txt in the slave/device_rom_table directory 1 means
a standard device
DRT_FLAGS: 1
number of registers this should be equal to the nubmer of ???
parameters
DRT_SIZE: 5
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
*/
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_mask;
reg [31:0] interrupt_edge;
reg clear_interrupts;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "functions.vh"
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9671_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_valid,
adc_data_a,
adc_or_a,
adc_data_b,
adc_or_b,
adc_data_c,
adc_or_c,
adc_data_d,
adc_or_d,
adc_data_e,
adc_or_e,
adc_data_f,
adc_or_f,
adc_data_g,
adc_or_g,
adc_data_h,
adc_or_h,
adc_start_code,
adc_sync_in,
adc_sync_out,
adc_sync,
adc_sync_status,
adc_status,
adc_raddr_in,
adc_raddr_out);
// parameters
parameter PCORE_4L_2L_N = 1;
parameter PCORE_ID = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input rx_sof;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output adc_valid;
output [ 15:0] adc_data_a;
output adc_or_a;
output [ 15:0] adc_data_b;
output adc_or_b;
output [ 15:0] adc_data_c;
output adc_or_c;
output [ 15:0] adc_data_d;
output adc_or_d;
output [ 15:0] adc_data_e;
output adc_or_e;
output [ 15:0] adc_data_f;
output adc_or_f;
output [ 15:0] adc_data_g;
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
input [ 31:0] adc_start_code;
input adc_sync_in;
output adc_sync_out;
input adc_sync;
output adc_sync_status;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// internal wires
wire [127:0] adc_wdata;
wire [127:0] adc_rdata;
wire [ 15:0] adc_data_a_s;
wire [ 15:0] adc_data_b_s;
wire [ 15:0] adc_data_c_s;
wire [ 15:0] adc_data_d_s;
wire [ 15:0] adc_data_e_s;
wire [ 15:0] adc_data_f_s;
wire [ 15:0] adc_data_g_s;
wire [ 15:0] adc_data_h_s;
wire [ 3:0] adc_raddr_s;
wire adc_sync_s;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_sync_status = 'd0;
reg rx_sof_d = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
reg [ 15:0] adc_data_a;
reg [ 15:0] adc_data_b;
reg [ 15:0] adc_data_c;
reg [ 15:0] adc_data_d;
reg [ 15:0] adc_data_e;
reg [ 15:0] adc_data_f;
reg [ 15:0] adc_data_g;
reg [ 15:0] adc_data_h;
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid;
assign adc_sync_out = adc_sync;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
assign adc_or_c = 'd0;
assign adc_or_d = 'd0;
assign adc_or_e = 'd0;
assign adc_or_f = 'd0;
assign adc_or_g = 'd0;
assign adc_or_h = 'd0;
assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
always @(posedge rx_clk) begin
adc_data_a <= adc_rdata[ 15: 0];
adc_data_b <= adc_rdata[ 31: 16];
adc_data_c <= adc_rdata[ 47: 32];
adc_data_d <= adc_rdata[ 63: 48];
adc_data_e <= adc_rdata[ 79: 64];
adc_data_f <= adc_rdata[ 95: 80];
adc_data_g <= adc_rdata[111: 96];
adc_data_h <= adc_rdata[127:112];
end
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_sync_status <= 1'b0;
end else begin
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1;
end
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
end
end
end
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
int_valid <= 1'b1;
int_data <= rx_data;
end else begin
rx_sof_d <= rx_sof;
int_valid <= rx_sof_d;
int_data[63:0] <= {rx_data[31:0], int_data[63:32]};
int_data[127:64] <= {rx_data[63:32], int_data[127:96]};
end
end
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(128)) i_mem (
.clka(rx_clk),
.wea(int_valid),
.addra(adc_waddr),
.dina(adc_wdata),
.clkb(rx_clk),
.addrb(adc_raddr_s),
.doutb(adc_rdata));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
input [0 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(142),
.C_FCLK_CLK2_FREQ(50),
.C_FCLK_CLK3_FREQ(50),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
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