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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_4_V
`define SKY130_FD_SC_HD__O21A_4_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_4_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dirrep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dirrep(/*AUTOARG*/
// Outputs
dirrep_dir_wr_par_c4, dir_vld_c4_l, dc_rd_en_c4, dc_wr_en_c4,
inval_mask_dcd_c4, dc_rdwr_row_en_c4, dc_rdwr_panel_dec_c4,
dc_lkup_row_dec_c4, dc_lkup_panel_dec_c4, wr_dc_dir_entry_c4,
dc_dir_clear_c4, ic_rd_en_c4, ic_wr_en_c4, inval_mask_icd_c4,
ic_rdwr_row_en_c4, ic_rdwr_panel_dec_c4, ic_lkup_row_dec_c4,
ic_lkup_panel_dec_c4, wr_ic_dir_entry_c4, ic_dir_clear_c4,
lkup_addr8_c4, dir_error_c8, so, tagdp_lkup_addr11_c5,
// Inputs
ic_parity_out, dc_parity_out, arbdp_dir_wr_par_c3,
arbctl_dir_vld_c3_l, arbctl_ic_rd_en_c3, arbctl_dc_rd_en_c3,
arbctl_ic_wr_en_c3, arbctl_dc_wr_en_c3, arbctl_dir_panel_dcd_c3,
arbctl_dir_panel_icd_c3, arbctl_lkup_bank_ena_dcd_c3,
arbctl_lkup_bank_ena_icd_c3, arbctl_inval_mask_dcd_c3,
arbctl_inval_mask_icd_c3, arbctl_wr_dc_dir_entry_c3,
arbctl_wr_ic_dir_entry_c3, lkup_row_addr_dcd_c3,
lkup_row_addr_icd_c3, oneshot_dir_clear_c3, tagdp_lkup_addr11_c4,
sehold, rclk, si, se
);
output dirrep_dir_wr_par_c4;
output dir_vld_c4_l;
// D$ directory ( Left Bottom )
output dc_rd_en_c4, dc_wr_en_c4 ;
output [7:0] inval_mask_dcd_c4;
// Read and write addresses require a rd_en/wr_en qualification
output [3:0] dc_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 )
output [3:0] dc_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 );
// Lkup addresses do not require a qualification as the
// _lkup_row_dec_c4 is actually a qualified vector.
output [3:0] dc_lkup_row_dec_c4 ;
output [3:0] dc_lkup_panel_dec_c4 ;// use lkup_row_addr_dcd[2:1] dec
output [5:0] wr_dc_dir_entry_c4 ; // lsb is arbctl_dir_panel_dcd[2]
output dc_dir_clear_c4; // Bottom left
// ie bit 8 of the address.
// I$ directory ( Left TOp )
output ic_rd_en_c4, ic_wr_en_c4 ;
output [7:0] inval_mask_icd_c4;
// Read and write addresses require a rd_en/wr_en qualification
output [3:0] ic_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 )
output [3:0] ic_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 );
// Lkup addresses do not require a qualification as the
// _lkup_row_dec_c4 is actually a qualified vector.
output [3:0] ic_lkup_row_dec_c4 ; // use lkup_row_addr_dcd[2:1] dec
output [3:0] ic_lkup_panel_dec_c4 ;
output [5:0] wr_ic_dir_entry_c4 ; // lsb is arbctl_dir_panel_icd[2]
// ie bit 8 of the address.
output ic_dir_clear_c4; // Top left
output lkup_addr8_c4; // Left
output dir_error_c8; // Right
output so;
input [3:0] ic_parity_out; // LeftTop ( C7 signal.)
input [3:0] dc_parity_out; // LeftBottom ( C7 signal.)
// Use same pin positions as before.
input arbdp_dir_wr_par_c3;
input arbctl_dir_vld_c3_l;
input arbctl_ic_rd_en_c3, arbctl_dc_rd_en_c3;
input arbctl_ic_wr_en_c3, arbctl_dc_wr_en_c3;
input [4:0] arbctl_dir_panel_dcd_c3, arbctl_dir_panel_icd_c3 ;
input [3:0] arbctl_lkup_bank_ena_dcd_c3, arbctl_lkup_bank_ena_icd_c3 ; // translates to a row_en
input [7:0] arbctl_inval_mask_dcd_c3,arbctl_inval_mask_icd_c3;
input [4:0] arbctl_wr_dc_dir_entry_c3, arbctl_wr_ic_dir_entry_c3;
input [2:0] lkup_row_addr_dcd_c3, lkup_row_addr_icd_c3 ; // translates to a panel enable.
// comes from tagdp
input oneshot_dir_clear_c3;
input tagdp_lkup_addr11_c4; // Added POST_4.2
input sehold; // Added POST_4.2
output tagdp_lkup_addr11_c5; // Added POST_4.2
input rclk;
input si, se;
wire dir_error_c7;
wire [4:0] dir_panel_dcd_c4, dir_panel_icd_c4 ;
wire [2:0] lkup_row_addr_dcd_c4, lkup_row_addr_icd_c4;
// ------\/ Addition for directory macrotest \/------------
dffe_s #(1) ff_tagdp_lkup_addr11_c5
(.q (tagdp_lkup_addr11_c5),
.din (tagdp_lkup_addr11_c4),
.clk (rclk),
.en(~sehold),
.se(se), .si (), .so ()
) ;
// ------\/ Addition for directory macrotest \/------------
assign dir_error_c7 = (|(ic_parity_out)) | (|(dc_parity_out)) ;
dff_s #(1) ff_dir_error_c8
(.q (dir_error_c8),
.din (dir_error_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_wr_par_c4
(.q (dirrep_dir_wr_par_c4),
.din (arbdp_dir_wr_par_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dir_vld_dcd_c4_l
(.q (dir_vld_c4_l),
.din (arbctl_dir_vld_c3_l),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dc_rd_en_c4
(.q (dc_rd_en_c4),
.din (arbctl_dc_rd_en_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_ic_rd_en_c4
(.q (ic_rd_en_c4),
.din (arbctl_ic_rd_en_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dc_wr_en_c4
(.q (dc_wr_en_c4),
.din (arbctl_dc_wr_en_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_ic_wr_en_c4
(.q (ic_wr_en_c4),
.din (arbctl_ic_wr_en_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(8) ff_inval_mask_dcd_c4
(.q (inval_mask_dcd_c4[7:0]),
.din (arbctl_inval_mask_dcd_c3[7:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(8) ff_inval_mask_icd_c4
(.q (inval_mask_icd_c4[7:0]),
.din (arbctl_inval_mask_icd_c3[7:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
///////////////////////////////////////////////////////////
// RD Write row and panel enables.
// Row is dtermined by the lower order bits of the
// address.
// ie bits 5,4 for the I$
// ie bits 5,11 for the D$.
// Panel is determined by address bits 10,9
///////////////////////////////////////////////////////////
dff_s #(4) ff_dir_panel_dcd_c4
(.q ({dir_panel_dcd_c4[4:3], dir_panel_dcd_c4[1:0]}),
.din ({arbctl_dir_panel_dcd_c3[4:3],arbctl_dir_panel_dcd_c3[1:0]}),
.clk (rclk),
.se(se), .si (), .so ()
) ;
//assign dc_rdwr_panel_dec_c4[0] = ( dir_panel_dcd_c4[4:3] == 2'd0 );
//assign dc_rdwr_panel_dec_c4[1] = ( dir_panel_dcd_c4[4:3] == 2'd1 );
//assign dc_rdwr_panel_dec_c4[2] = ( dir_panel_dcd_c4[4:3] == 2'd2 );
//assign dc_rdwr_panel_dec_c4[3] = ( dir_panel_dcd_c4[4:3] == 2'd3 );
assign dc_rdwr_panel_dec_c4[0] = ~dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ;
assign dc_rdwr_panel_dec_c4[1] = ~dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ;
assign dc_rdwr_panel_dec_c4[2] = dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ;
assign dc_rdwr_panel_dec_c4[3] = dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ;
assign dc_rdwr_row_en_c4[0] = (dir_panel_dcd_c4[1:0] == 2'd0 );
assign dc_rdwr_row_en_c4[1] = (dir_panel_dcd_c4[1:0] == 2'd1 );
assign dc_rdwr_row_en_c4[2] = (dir_panel_dcd_c4[1:0] == 2'd2 );
assign dc_rdwr_row_en_c4[3] = (dir_panel_dcd_c4[1:0] == 2'd3 );
dff_s #(4) ff_dir_panel_icd_c4
(.q ({dir_panel_icd_c4[4:3],dir_panel_icd_c4[1:0]}),
.din ({arbctl_dir_panel_icd_c3[4:3],arbctl_dir_panel_icd_c3[1:0]}),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign ic_rdwr_panel_dec_c4[0] = ( dir_panel_icd_c4[4:3] == 2'd0 );
assign ic_rdwr_panel_dec_c4[1] = ( dir_panel_icd_c4[4:3] == 2'd1 );
assign ic_rdwr_panel_dec_c4[2] = ( dir_panel_icd_c4[4:3] == 2'd2 );
assign ic_rdwr_panel_dec_c4[3] = ( dir_panel_icd_c4[4:3] == 2'd3 );
assign ic_rdwr_row_en_c4[0] = (dir_panel_icd_c4[1:0] == 2'd0 );
assign ic_rdwr_row_en_c4[1] = (dir_panel_icd_c4[1:0] == 2'd1 );
assign ic_rdwr_row_en_c4[2] = (dir_panel_icd_c4[1:0] == 2'd2 );
assign ic_rdwr_row_en_c4[3] = (dir_panel_icd_c4[1:0] == 2'd3 );
///////////////////////////////////////////////////////////
// lkup row and panel enables.
// Lkup row coming from tagdp corresponds to
// address bits <10:8> of the lkup address.
// The bits <10:9> actually go into determining
// the panel id within the directory.
///////////////////////////////////////////////////////////
dff_s #(3) ff_lkup_row_addr_dcd_c4
(.q (lkup_row_addr_dcd_c4[2:0]),
.din (lkup_row_addr_dcd_c3[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign dc_lkup_panel_dec_c4[0] = ( lkup_row_addr_dcd_c4[2:1] == 2'd0 );
assign dc_lkup_panel_dec_c4[1] = ( lkup_row_addr_dcd_c4[2:1] == 2'd1 );
assign dc_lkup_panel_dec_c4[2] = ( lkup_row_addr_dcd_c4[2:1] == 2'd2 );
assign dc_lkup_panel_dec_c4[3] = ( lkup_row_addr_dcd_c4[2:1] == 2'd3 );
dff_s #(4) ff_lkup_bank_ena_dcd_c4
(.q (dc_lkup_row_dec_c4[3:0]),
.din (arbctl_lkup_bank_ena_dcd_c3[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(3) ff_lkup_row_addr_icd_c4
(.q (lkup_row_addr_icd_c4[2:0]),
.din (lkup_row_addr_icd_c3[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign lkup_addr8_c4 = lkup_row_addr_icd_c4[0];
assign ic_lkup_panel_dec_c4[0] = ( lkup_row_addr_icd_c4[2:1] == 2'd0 );
assign ic_lkup_panel_dec_c4[1] = ( lkup_row_addr_icd_c4[2:1] == 2'd1 );
assign ic_lkup_panel_dec_c4[2] = ( lkup_row_addr_icd_c4[2:1] == 2'd2 );
assign ic_lkup_panel_dec_c4[3] = ( lkup_row_addr_icd_c4[2:1] == 2'd3 );
dff_s #(4) ff_lkup_bank_ena_icd_c4
(.q (ic_lkup_row_dec_c4[3:0]),
.din (arbctl_lkup_bank_ena_icd_c3[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
///////////////////////////////////////////////////////////
// Wr or Rd entry.
// the LSB of the entry is address bit 2 of
// the panel id from arbctl.
// This translates to address<8> for both the I$ and D$.
///////////////////////////////////////////////////////////
dff_s #(6) ff_wr_dc_dir_entry_c4
(.q (wr_dc_dir_entry_c4[5:0]),
.din ({arbctl_wr_dc_dir_entry_c3[4:0],arbctl_dir_panel_dcd_c3[2]}),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(6) ff_wr_ic_dir_entry_c4
(.q (wr_ic_dir_entry_c4[5:0]),
.din ({arbctl_wr_ic_dir_entry_c3[4:0],arbctl_dir_panel_icd_c3[2]}),
.clk (rclk),
.se(se), .si (), .so ()
) ;
///////////////////////////////////////////////////////////
// Dir clear bits.
///////////////////////////////////////////////////////////
dff_s #(1) ff_ic_dir_clear_c4
(.q (ic_dir_clear_c4),
.din (oneshot_dir_clear_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dc_dir_clear_c4
(.q (dc_dir_clear_c4),
.din (oneshot_dir_clear_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_gtp_pipe_rate.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
module pcie_7x_v1_11_0_gtp_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input [ 1:0] RATE_RATE_IN,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_TXSYNC_DONE,
input RATE_PHYSTATUS,
//---------- Output ------------------------------------
output RATE_PCLK_SEL,
output RATE_DRP_START,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
//---------- Internal Signals --------------------------
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
//---------- Output FF or Buffer -----------------------
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg [ 3:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_TXDATA_WAIT = 1;
localparam FSM_PCLK_SEL = 2;
localparam FSM_DRP_X16_START = 3;
localparam FSM_DRP_X16_DONE = 4;
localparam FSM_RATE_SEL = 5;
localparam FSM_RXPMARESETDONE = 6;
localparam FSM_DRP_X20_START = 7;
localparam FSM_DRP_X20_DONE = 8;
localparam FSM_RATE_DONE = 9;
localparam FSM_TXSYNC_START = 10;
localparam FSM_TXSYNC_DONE = 11;
localparam FSM_DONE = 12; // Must sync value to pipe_user.v
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rate_in_reg1 <= 2'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rate_in_reg2 <= 2'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rate_in_reg1 <= RATE_RATE_IN;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rate_in_reg2 <= rate_in_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Select Rate -------------------------------------------------------
// Gen1 : div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : div 1 using [TX/RX]RATE = 3'd1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_IDLE;
pclk_sel <= 1'd0;
rate_out <= 3'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= FSM_TXDATA_WAIT;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
else
begin
fsm <= FSM_IDLE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;
pclk_sel <= (rate_in_reg2 == 2'd1);
rate_out <= rate_out;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
pclk_sel <= pclk_sel;
rate_out <= rate; // Update [TX/RX]RATE
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone)
fsm <= FSM_TXSYNC_START;
else
fsm <= FSM_RATE_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= FSM_IDLE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
pclk_sel <= 1'd0;
rate_out <= 3'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_RATE_OUT = rate_out;
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = {1'd0, fsm};
endmodule
|
(***********************************************************************
* ____ __ _ _ ____ __ * Still Another Math library ! *
* / ___) / _\ ( \/ )( _ \( ) *-------------------------------------*
* \___ \/ \/ \/ \ ) __// (_/\ * (c) Chauvin Barnabé *
* (____/\_/\_/\_)(_/(__) \____/ * This file is distributed under the *
* * terms of the GPL License Version 2 *
***********************************************************************)
Require Export SAMPL.functions.
Global Generalizable All Variables.
(**
* Definitions
*)
(**
** Vector-space and vector-subspace structures
We call a vector-space over $$\mathbb{K}$$ is an abelian group $$E$$ with two operations (a classical
addition (of the $$E$$ structure usually) and a scalar multiplication, that satisfy the
eight following axioms :
- Associativiy of addition : $$\forall u ,v, w \in E, u + (v + w) = (u + v) + w$$
- Commutativity of addition : $$\forall u, v \in E, u + v = v + u$$
- Identify element of addition : $$\exists 0_E \in E$$, \forall v \in E, v + 0_E = v$$.
We call this element the zero vector.
- Inverse elements of addition : $$\forall v \in E, \exists -v \in E, v + (-v) = 0_E$$.
We call this element the additive inverse.
- Compatibility of scalar multiplication with field multiplication :
$$\forall a, b \in \mathbb{K}, \forall v \in E, a(b\cdot v) = (ab)v$$
- Identify element of scalar multiplication :
$$\exists 1_\mathbb{K} \in \mathbb{K}, \forall v \in E, 1_\mathbb{K} v = v$$. We call this
element the multiplicative identify.
- Distributivity of scalar multiplication with respect to vector addition :
$$\forall a \in \mathbb{K}, \forall u, v \in E, a(u + v) = au + av$$
- Distributivity of scalar multiplication with respect to field addition :
$$\forall a, b \in \mathbb{K}, \forall v \in E, (a + b)v = av + bv$$
*)
Section vector_space_def.
(**
We first define the scalar multiplication.
The addition is already defined : we use [Plus] of a semiring.
*)
Class ScalarMult K E := scalar_mult : K -> E -> E.
Context K {Ke : Equiv K} {Kplus : Plus K} {Kmult : Mult K} {Kzero : Zero K} {Kone : One K}
{Knegate : Negate K} {Kap : Apart K} {Krecip : Recip K} {Kf : Field K}.
Context E {Ee : Equiv E} {Eplus : Plus E} {Ezero : MonUnit E} {Eopp : Negate E} {Eg : AbGroup E}.
Context {SV_Mult_H : ScalarMult K E}.
(**
We must define the 4 last axioms, and then we can define the structure itself :
*)
Class ScalarMultCompatibility : Prop :=
scalar_mult_comp : forall (a b : K)(v : E), scalar_mult a (scalar_mult b v) = scalar_mult (a [*] b) v.
Class ScalarMultDistr_Vector : Prop := scalar_mult_distr_vector :
forall (a : K)(u v : E), scalar_mult a (sg_op u v) = sg_op (scalar_mult a u) (scalar_mult a v).
Class ScalarMultDistr_Field : Prop := scalar_mult_distr_field :
forall (a b : K)(v : E), scalar_mult (a [+] b) v = sg_op (scalar_mult a v) (scalar_mult b v).
Class VectorSpace : Prop := {
vs_add_ass : Associative Eplus ;
vs_add_comm : Commutative Eplus ;
vs_add_id : LeftIdentity Eplus Ezero ;
vs_add_inv : Negate E ;
vs_scalar_mult_comp : ScalarMultCompatibility ;
vs_scalar_mult_id : LeftIdentity scalar_mult one ;
vs_scalar_mult_distr_vector : ScalarMultDistr_Vector ;
vs_scalar_mult_distr_field : ScalarMultDistr_Field
}.
End vector_space_def.
Infix "[x]" := scalar_mult (at level 40).
(**
We now define three properties that allow to define a lot of vector spaces :
- Let $$\mathbb{L}$$ be a field, such that $$\mathbb{K} \subset \mathbb{L}$$ (So $$1_\mathbb{K} = 1_\mathbb{L}$$).
Then $$\mathbb{L}$$ is a vector space over $$\mathbb{K}$$.
-
*)
Section vector_space_charac_1.
Variable L : Set.
Context {Le : Equiv L} {Lplus : Plus L} {Lmult : Mult L} {LmultAssoc :Associative Lmult} {Lzero : Zero L} {Lone : One L}
{Lnegate : Negate L} {Lap : Apart L} {Lrecip : Recip L} {Lf : Field L}.
Variable Kprop : L->Prop.
Let K := sig Kprop.
Let inj := sig_injection L Kprop.
Hypothesis Hplus_closed : ClosedOp L Kprop plus.
Hypothesis Hmult_closed : ClosedOp L Kprop mult.
Hypothesis Hone : Kprop Lone.
Instance L_scalarMult : ScalarMult K L := (fun x y => Lmult (inj x) y).
Instance Kone : One K := Fone L Kprop Hone.
Context {Kzero : Zero K} {Knegate : Negate K} {Kap : Apart K} {Krecip : Recip K}
{Ksf : (@SubField L Kprop Le Lplus Hplus_closed Lmult Hmult_closed Kone Knegate Kap Kzero Krecip)}.
(*
Context {H:Fone}.
Lemma test : VectorSpace K L.
Proof.
(* The first 4 axioms of the additions (It is the internal addition of [L], so it does not change) *)
split. apply _. apply _. apply _. apply _.
(* We unfold the definitions, and then we use functional extensionality *)
(* TODO : do it with classes features ! *)
unfold ScalarMultCompatibility ; unfold scalar_mult ; intros ; unfold L_scalarMult.
repeat rewrite spec_mult_restr ; unfold Associative in LmultAssoc ; unfold HeteroAssociative in LmultAssoc.
rewrite LmultAssoc. (* TODO *) admit.
unfold LeftIdentity. unfold scalar_mult. unfold L_scalarMult. intros. unfold one.
*)
End vector_space_charac_1.
(**
We define a vector subspace (also called a linear subspace).
Let $$E$$ be a vector space over $$\mathbb{K}$$, and $$F \subset E$$. $$F$$ is a vector subspace
of $$E$$ if :
- $$F$$ is closed under addition : $$\forall x, y \in F, x + y \in F$$
- $$F$$ is closed under scalar multiplication :
$$\forall \lambda \in \mathbb{K}, \forall x \in F, \lambda x \in F$$
- The restriction of the addition of $$E$$ to $$\mathbb{K} \times E$$ let $$F$$ be a vector space
over $$\mathbb{K}$$ (i.e. $$F$$ satisfy the vector space axioms)
We define the subset $$F$$ with the same way we did in sets.v (i.e a predicate [E->Prop]).
*)
Section vector_definitions.
Context (K:Set) {Ke : Equiv K} {Kplus : Plus K} {Kmult : Mult K} {Kzero : Zero K} {Kone : One K}
{Knegate : Negate K} {Kap : Apart K} {Krecip : Recip K} {Kf : Field K}.
Context (E:Set) {Ee : Equiv E} {Eadd : Plus E} {Ezero : Zero E} {Eneg : Negate E} {Eg : AbGroup E}
{Emult : ScalarMult K E} {Eh : VectorSpace K E}.
Section vector_subspace_def.
Variable Fprop : E -> Prop.
Let F := sig Fprop.
Let inj_F_E := @proj1_sig E Fprop.
(**
We first define the "closed operation" propositions :
*)
Class ClosedIntOp : Prop := closed_internal_op : forall (x y : F), Fprop (Eadd (inj_F_E x) (inj_F_E y)).
Class ClosedExtOp : Prop := closed_external_op : forall (l : K)(x : F), Fprop (Emult l (inj_F_E x)).
Context `{VectorSpace K F}.
Class VectorSubspace : Prop := {
vss_add_closed : ClosedIntOp ;
vss_mult_closed : ClosedExtOp ;
vss_add (x y : F) := exist Fprop (Eadd (proj1_sig x) (proj1_sig y)) (closed_internal_op x y) ;
vss_mult (l:K)(x:F) := exist Fprop (Emult l (proj1_sig x)) (closed_external_op l x) ;
(* Axioms of a vector space *)
vss_axioms : VectorSpace K F
}.
(**
We define two characterizations (or "useful criteria") to prove that a subset [F] is a vector subspace :
(These criterias consist in a fewer list of axioms)
- Criteria 1 :
- ($$F \subset E$$. This is obvious with our definition of $$F$$, wo we don't define it.)
- $$F \neq \emptyset$$ (We usually prove that the zero vector is included in $$F$$)
- $$\forall x, y \in F, x + y \in F$$
- $$\forall x \in F, \forall \lambda \in \mathbb{K}, \lambda x \in F$$
- Criteria 2 : (It only concises the two last axioms of the latter criteria)
- $$\forall x, y \in F, \forall \lambda \in \mathbb{K}, \lambda x + y \in F$$
*)
(* TODO *)
End vector_subspace_def.
(**
** Examples
In this section, we give several example of vector-spaces and vector-subspaces
We'll deal with the following vector-spaces :
- Geometrical vectors : $$\mathbb{R}^2$$ and $$\mathbb{R}^3$$ over $$\mathbb{R}$$ (denoted by [Ev2] and [Ev3])
- $$\mathcal{F}(\mathbb{R}, \mathbb{R})$$ over $$\mathbb{R}$$ (denoted by [Ef])
We first prove they are actual vector-spaces, and then we use them to define vector-subspaces.
*)
(* TODO *)
Section vector_line.
(**
The vector-line directed by $$u \in E$$ is $$\{ \lambda u \mid \lamdba \in \mathbb{K} \}$$.
(It is a subset of [E]).
*)
Definition vector_line (u : E)(x : E) := exists (l : K), x [=] (l [x] u).
Variable u:E.
Let lineProp := vector_line u.
Let line := sig lineProp.
(**
A vector-line is always a sub-vector-space of [E].
*)
Instance line_plus_closed : ClosedOp E lineProp plus.
(*repeat red. intros.
destruct x ; unfold lineProp in l ; unfold vector_line in l ; destruct l.
destruct y ; unfold lineProp in l ; unfold vector_line in l ; destruct l.
exists (x0 [+] x2).
(* TODO *) *)
Admitted.
Instance line_plus : Plus line := Fplus E lineProp.
Lemma zero_in_line : lineProp Ezero.
Proof.
(* TODO *)
Admitted.
Instance line_zero : Zero line := Fzero E lineProp zero_in_line.
Instance line_scalar_mult : ScalarMult K line.
(* TODO : restriction of EScalarMult *)
Admitted.
Instance vector_line_svs : VectorSubspace lineProp.
(* TODO *)
Admitted.
End vector_line.
Variable Fprop Gprop : E -> Prop.
Let F := sig Fprop.
Let G := sig Gprop.
(**
The intersection of two sub-vector-space is still a sub-vector-space of [E].
*)
Section svs_inter.
Definition svs_inter_prop := inter _ Fprop Gprop.
Let svs_inter := sig svs_inter_prop.
Instance svs_inter_closed : ClosedOp E svs_inter_prop plus.
(* TODO *)
Admitted.
Instance svs_inter_plus : Plus svs_inter := Fplus E svs_inter_prop.
Lemma zero_in_svs_inter : svs_inter_prop Ezero.
Proof.
(* TODO *)
Admitted.
Instance svs_inter_zero : Zero svs_inter := Fzero E svs_inter_prop zero_in_svs_inter.
Instance svs_inter_scalar_mult : ScalarMult K svs_inter.
(* TODO *)
Admitted.
Instance svs_inter_svs : VectorSubspace svs_inter_prop.
(* TODO *)
Admitted.
End svs_inter.
(**
The sum of two sub-vector-spaces [F] and [G] is :
$$F + G = \{x + y \mid x \in F \land y \in G \}$$.
*)
Section svs_sum.
Definition svs_sum_prop := fun z => exists (x y : E)(Hx : Fprop x)(Hy : Fprop y), z [=] (x [+] y).
Let svs_sum := sig svs_sum_prop.
Instance svs_sum_closed : ClosedOp E svs_sum_prop plus.
(* TODO *)
Admitted.
Instance svs_sum_plus : Plus svs_sum := Fplus E svs_sum_prop.
Lemma zero_in_svs_sum : svs_sum_prop Ezero.
Proof.
(* TODO *)
Admitted.
Instance svs_sum_zero : Zero svs_sum := Fzero E svs_sum_prop zero_in_svs_sum.
Instance svs_sum_scalar_mult : ScalarMult K svs_sum.
(* TODO *)
Admitted.
Instance svs_sum_svs : VectorSubspace svs_sum_prop.
(* TODO *)
Admitted.
(**
$$F + G$$ is the smallest vector subspace of [E] containing $$F \cup G$$ :
- $$F + G$$ is a sub-vector-space of [E] (Already proved)
- $$F \cup G \subset F + G$$
- If $$H$$ is a sub-vector space of [E] such that $$F \cup G \subset H$$, then $$F + G \subset H$$.
*)
Definition svs_union_prop := union _ Fprop Gprop.
Let svs_union := sig svs_union_prop.
Lemma svs_union_subset_sum : subset _ svs_union_prop svs_sum_prop.
Proof.
(* TODO *)
Admitted.
Variable Hprop:E->Prop.
Context `{Hsvs : VectorSubspace Hprop}.
Lemma svs_union_smallest_subset : subset _ svs_union_prop Hprop
-> subset _ svs_sum_prop Hprop.
Proof.
(* TODO *)
Admitted.
(**
The sum is direct if
$$\forall w \in E, \exists ! (u, v) \in F \times G, w = u + v$$.
We then note $$F \oplus G$$ instead of $$F + G$$.
*)
Definition svs_direct_sum := forall (w : E), exists ! (x y : E)
(Hx : Fprop x)(Hy : Fprop y), w [=] (x [+] y).
(**
$$F$$ and $$G$$ are direct sum if and only if $$F \cap G = \{0\}$$.
*)
Theorem svs_direct_sum_charac : iff (svs_direct_sum) (forall (x:E), svs_sum_prop x
-> x [=] Ezero).
Proof.
(* TODO *)
Admitted.
End svs_sum.
Section vector_plane.
(**
We define a vector plan as the direct sum of two vector line :
*)
Definition vector_plane_prop (H : svs_direct_sum)(x : E) := svs_sum_prop x.
End vector_plane.
Section additional_svs.
(**
[F] and [G] are additional if : $$F \oplus G = E$$.
(The inclusion $$F \oplus G \subset E$$ is obvious, we only specify $$E \subset F \oplus G$$).
*)
Definition svs_additional := svs_direct_sum /\ (forall (x:E), svs_sum_prop x).
(**
[F] and [G] are additional in [E] if and only if
$$\forall v \in E, \exists !(f, g) \in F \times G, v = f+g$$.
*)
Theorem svs_additional_charac : iff (svs_additional) (forall (v:E), exists! (f g : E),
Fprop f -> Gprop g -> v [=] (f [+] g)).
Proof.
(* TODO *)
Admitted.
End additional_svs.
End vector_definitions.
Open Scope nat_scope.
(**
* Vector set
In this section, [S] will be a set of vector (i.e. $$S = (e_1, ... e_n) \in E^n$$).
*)
Section vector_set.
Context (K:Set) {Ke : Equiv K} {Kplus : Plus K} {Kmult : Mult K} {Kzero : Zero K} {Kone : One K}
{Knegate : Negate K} {Kap : Apart K} {Krecip : Recip K} {Kf : Field K}.
Context (E:Set) {Ee : Equiv E} {Eadd : Plus E} {Ezero : Zero E} {Eneg : Negate E} {Eg : AbGroup E}
{Emult : ScalarMult K E} {Eh : VectorSpace K E}.
Variable n : nat.
Variable S : nat -> E.
Hypothesis S_finite : forall (k:nat), k>n -> (S k) [=] [0].
Section vector_basis.
Section vector_span.
(**
A vector span is a subset of [E] defined as follows :
$$\mathrm{span}(S) = \left\{ \sum\limits_{i = 1}^k \lambda_i e_i \mid k \in \mathbb{N}, \lambda_i \in \mathbb{K} \right\}$$.
(It is the set of all finite combinations of elements of [S]).
We note this subset $$\mathrm{span}(S)$$.
*)
Definition vector_span_prop (x:E) := exists (l : nat->K), x [=] sum E n (fun i => (l i) [x] (S i)).
(**
$$\mathrm{span}(S)$$ is a vector-subspace of [E].
*)
Let vector_span := sig vector_span_prop.
Instance span_closed : ClosedOp E vector_span_prop plus.
(* TODO *)
Admitted.
Instance span_plus : Plus vector_span := Fplus E vector_span_prop.
Lemma zero_in_span : vector_span_prop Ezero.
Proof.
(* TODO *)
Admitted.
Instance span_zero : Zero vector_span := Fzero E vector_span_prop zero_in_span.
Instance span_scalar_mult : ScalarMult K svs_sum.
(* TODO *)
Admitted.
Instance span_svs : VectorSubspace K E vector_span_prop.
(* TODO *)
Admitted.
(**
A span is a generating set if $$\mathrm{span}(S) = E$$.
*)
Definition generating_span := forall (v:E), vector_span_prop v.
End vector_span.
(**
A set of vectors is linearly independent if
$$\forall (\lambda_1, ... \lambda_n) \in \mathbb{K}^n, \sum\limits_{i = 1}^n \lambda_i e_i = 0$$,
then $$\lambda_1 = ... = \lambda_n = 0_{\mathbb{K}}$$.
*)
Definition linearly_independent := forall (l : nat -> K), sum E n (fun i => (l i) [x] (S i)) [=] [0]
-> (forall (i:nat), (l i) [=] [0]).
(**
A set of vectors [S] is a basis of [E] if [S] is linearly indepedent and if
[S] spans [E] (i.e. if [S] is a generating set of [E]).
*)
Definition basis := linearly_independent /\ generating_span.
(**
With our previous definitions, we can define the following equivalences :
- [S] is linearly independent $$\Leftrightarrow$$ there is unicity of
$(\lambda_1, ... \lambda_n) \in \mathbb{K}^n$$ such that forall $$v \in E$$,
$$v = \lambda_1 e_1 + ... + \lambda_n e_n$$.
- [S] is a generating set of [E] $$\Leftrightarrow $$ there exists
$(\lambda_1, ... \lambda_n) \in \mathbb{K}^n$$ such that forall $$v \in E$$,
$$v = \lambda_1 e_1 + ... + \lambda_n e_n$$.
- [S] is a basis $$\Leftrightarrow \forall v\ in E, \exists ! (\lambda_1, ... \lambda_n) \in \mathbb{K}^n,
v = \lambda_1 e_1 + ... + \lambda_n e_n$$.
*)
Lemma linearly_independence_charac : iff linearly_independent
(uniqueness (fun l => forall (v:E), v [=] sum E n (fun i => (l i) [x] (S i)))).
Proof.
(* TODO *)
Admitted.
Lemma generating_charac : iff generating_span
(exists (l : nat->K), forall (v:E), v [=] sum E n (fun i => (l i) [x] (S i))).
Proof.
(* TODO *)
Admitted.
Lemma basis_charac : iff basis (exists! (l : nat->K), forall (v:E), v [=] sum E n (fun i => (l i) [x] (S i))).
Proof.
iff_reasoning ; intros.
(* First implication*)
unfold basis in H ; unfold linearly_independent, generating_span in H ; destruct H.
admit. (* TODO *)
(* Second imlication *)
unfold basis ; unfold linearly_independent, generating_span ; split ; intros.
admit. admit. (* TODO *)
Qed.
End vector_basis.
End vector_set.
Section linearly_dependent.
Context (K:Set) {Ke : Equiv K} {Kplus : Plus K} {Kmult : Mult K} {Kzero : Zero K} {Kone : One K}
{Knegate : Negate K} {Kap : Apart K} {Krecip : Recip K} {Kf : Field K}.
Context (E:Set) {Ee : Equiv E} {Eadd : Plus E} {Ezero : Zero E} {Eneg : Negate E} {Eg : AbGroup E}
{Emult : ScalarMult K E} {Eh : VectorSpace K E}.
Variable n : nat.
Variable S : nat -> E.
Hypothesis S_finite : forall (k:nat), k>n -> (S k) [=] [0].
(**
A vector set is linearly dependent if and only if
$$\exists i \in [[1,n]], e_i \in \mathrm{span}(e_1, ... e_{i-1}, e_{i+1}, e_n)$$.
We first define the set $$(e_1, ... e_{i-1}, e_{i+1}, e_n)$$.
*)
Parameter vector_set' : nat -> nat -> E.
Parameter vector_set'_spec1 : forall (i : nat), vector_set' i i [=] [0].
Parameter vector_set'_spec2 : forall (i k : nat), i <> k -> (vector_set' i k) [=] (S k).
Lemma linearly_dependence_charac : iff (~ linearly_independent K E n S)
(exists (i:nat), i <= n -> (vector_span_prop K E n (vector_set' i)) (S i)).
Proof.
(* TODO *)
Admitted.
End linearly_dependent.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V
|
/*
ROM128X1: 128-Deep by 1-Wide ROM
ROM256X1: 256-Deep by 1-Wide ROM
ROM32X1: 32-Deep by 1-Wide ROM
ROM64X1: 64-Deep by 1-Wide ROM
*/
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("XXX"))
ram_RAMB18E1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/*
Site RAMB18_X0Y42
Pushed it outside the pblock
lets extend pblock
*/
module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
RAMB18E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
RAMB36E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_even_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_EVEN_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_even_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_even_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_even_parity_psl_logic.v"
`else
`endmodule // ovl_even_parity
`endif
|
module sm ();
localparam STATES = 7;
localparam /* synopsys enum states */
IDLE = 0, // '001
READ = 1, // '002
THINK = 2, // '004
SEND = 3, // '008
WAIT = 4, // '040
GET_ACK = 5, // '080
WAIT_REGBUS = 6; // '100
reg [STATES-1:0] /*synopsys enum states*/
state_i, state_r; /* synopsys state_vector state_r */
/*AUTOASCIIENUM("state_r","state_onehot,ascii_r","","onehot")*/
// Beginning of automatic ASCII enum decoding
reg [87:0] state_onehot,ascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
(7'b1<<IDLE): state_onehot,ascii_r = "idle ";
(7'b1<<READ): state_onehot,ascii_r = "read ";
(7'b1<<THINK): state_onehot,ascii_r = "think ";
(7'b1<<SEND): state_onehot,ascii_r = "send ";
(7'b1<<WAIT): state_onehot,ascii_r = "wait ";
(7'b1<<GET_ACK): state_onehot,ascii_r = "get_ack ";
(7'b1<<WAIT_REGBUS): state_onehot,ascii_r = "wait_regbus";
default: state_onehot,ascii_r = "%Error ";
endcase
end
// End of automatics
/*AUTOASCIIENUM("state_r","state_notonehot_ascii_r")*/
// Beginning of automatic ASCII enum decoding
reg [87:0] state_notonehot_ascii_r;// Decode of state_r
always @(state_r) begin
case ({state_r})
IDLE: state_notonehot_ascii_r = "idle ";
READ: state_notonehot_ascii_r = "read ";
THINK: state_notonehot_ascii_r = "think ";
SEND: state_notonehot_ascii_r = "send ";
WAIT: state_notonehot_ascii_r = "wait ";
GET_ACK: state_notonehot_ascii_r = "get_ack ";
WAIT_REGBUS: state_notonehot_ascii_r = "wait_regbus";
default: state_notonehot_ascii_r = "%Error ";
endcase
end
// End of automatics
endmodule
|
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-27 18:38:13
// Last Modified : 2016-11-19 17:55:11
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-25 17:59:05
// Last Modified : 2016-09-27 18:36:46
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-25 12:25:16
// Last Modified : 2016-09-25 12:25:16
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-24 01:24:56
// Last Modified : 2016-09-24 01:24:56
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
`timescale 1ns/1ps
module tb_FPU_PIPELINED_FPADDSUB2_vector_testing (); /* this is automatically generated */
localparam PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR=26;
parameter EWR = 5; //Single Precision */
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MODULE SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg beg_OP;
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
wire busy;
wire overflow_flag;
wire underflow_flag;
wire zero_flag;
wire [W-1:0] final_result_ieee;
reg [SW-1:0] final_result_ieee_mantissa;
reg [EW-1:0] final_result_ieee_exponent;
reg final_result_ieee_sign;
wire ready;
//Temps for the testbench and verification
reg [SW-1:0] Data_X_mant;
reg [SW-1:0] Data_Y_mant;
reg [EW-1:0] Data_X_exp;
reg [EW-1:0] Data_Y_exp;
reg Data_X_sign;
reg Data_Y_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS VARIABLES
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// reg [W-1:0] formatted_number_W;
//reg overflow_flag_t, underflow_flag_t;
//reg [EWR-1:0] LZD_raw_val_EWR;
reg [W-1:0] Theoretical_result;
reg [SW-1:0] Theoretical_result_mantissa;
reg [EW-1:0] Theoretical_result_exponent;
reg Theoretical_result_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// STIMULI SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_3 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer FileSaveDataDEC;
integer logVectorReference;
integer Cont_CLK;
// integer Recept;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// END OF DECLARATIONS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
FPU_PIPELINED_FPADDSUB #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_uut (
.clk (clk),
.rst (rst),
.beg_OP (beg_OP),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
always begin
#1;
final_result_ieee_mantissa = final_result_ieee[SW-1:0];
final_result_ieee_exponent = final_result_ieee[W-2:SW];
final_result_ieee_sign = final_result_ieee[W-1];
Data_X_mant = Data_X[SW-1:0];
Data_Y_mant = Data_Y[SW-1:0];
Data_X_exp = Data_X[W-2:SW];
Data_Y_exp = Data_Y[W-2:SW];
Data_X_sign = Data_X[W-1];
Data_Y_sign = Data_Y[W-1];
Theoretical_result_mantissa = Theoretical_result[SW-1:0];
Theoretical_result_exponent = Theoretical_result[W-2:SW];
Theoretical_result_sign = Theoretical_result[W-1];
end
// function [EWR-1:0] LZD_raw; // function definition starts here
// input [SWR-1:0] ADD_SUB_RAW;
// integer k;
// begin
// LZD_raw = 0;
// k=SWR-1;
// while(ADD_SUB_RAW[k] == 0) begin
// k = k-1;
// LZD_raw = LZD_raw + 1;
// $display("This is the bit analized %d\n", k);
// $display("This is the bit analized %d\n", ADD_SUB_RAW[k]);
// $display("Number of 0s %d\n", LZD_raw);
// end
// end
// endfunction
initial begin
`ifdef ACAIN16Q4
FileSaveData = $fopen("ResultadoXilinxACAIN16Q4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxACAIN16Q4FLMDEC.txt","w");
`elsif ETAIIN16Q4
FileSaveData = $fopen("ResultadoXilinxETAIIN16Q4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxETAIIN16Q4FLMDEC.txt","w");
`elsif ETAIIN16Q8
FileSaveData = $fopen("ResultadoXilinxETAIIN16Q8FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxETAIIN16Q8FLMDEC.txt","w");
`elsif ACAIIN16Q4
FileSaveData = $fopen("ResultadoXilinxACAIIN16Q4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxACAIIN16Q4FLMDEC.txt","w");
`elsif ACAIIN16Q8
FileSaveData = $fopen("ResultadoXilinxACAIIN16Q8FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxACAIIN16Q8FLMDEC.txt","w");
`elsif GDAN16M4P4
FileSaveData = $fopen("ResultadoXilinxGDAN16M4P4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxGDAN16M4P4FLMDEC.txt","w");
`elsif GDAN16M4P8
FileSaveData = $fopen("ResultadoXilinxGDAN16M4P8FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxGDAN16M4P8FLMDEC.txt","w");
`elsif GeArN16R2P4
FileSaveData = $fopen("ResultadoXilinxGeArN16R2P4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxGeArN16R2P4FLMDEC.txt","w");
`elsif GeArN16R4P4
FileSaveData = $fopen("ResultadoXilinxGeArN16R4P4FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxGeArN16R4P4FLMDEC.txt","w");
`elsif GeArN16R4P8
FileSaveData = $fopen("ResultadoXilinxGeArN16R4P8FLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxGeArN16R4P8FLMDEC.txt","w");
`elsif LOA
FileSaveData = $fopen("ResultadoXilinxLOAFLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxLOAFLMDEC.txt","w");
`else
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
FileSaveDataDEC = $fopen("ResultadoXilinxFLMDEC.txt","w");
`endif
logVectorReference = $fopen("output_log.txt","w");
rst = 1;
`ifdef SUB_OPER
add_subt = 1; //Se realiza la operacion de resta
`else
add_subt = 0; //Se realiza la operacion de suma
`endif
beg_OP = 0;
Data_Y = 0;
Data_X = 0;
Data_X_mant = 0;
Data_Y_mant = 0;
Data_X_exp = 0;
Data_Y_exp = 0;
Data_X_sign = 0;
Data_Y_sign = 0;
//Theoretical_result = 32'hbe1abef8;
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
#98 rst = 0;
//FPADD_FPSUB(0, Array_IN[3], Array_IN_2[3], formatted_number_W, overflow_flag_t, underflow_flag_t);
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$vcdpluson; //ESTO ES PARA LA OBTENCION DE LA POTENCIA DINAMICA, para esto necesitamos el .vcd
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
$readmemh("Hexadecimal_R.txt", Array_IN_3);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if (contador == (2**PERIOD+6)) begin
$fclose(FileSaveData);
$fclose(FileSaveDataDEC);
$fclose(logVectorReference);
$finish;
$vcdplusclose;
end else if(ready) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
`ifdef SINGLE
$fwrite(FileSaveDataDEC,"%f\n",$bitstoshortreal(final_result_ieee));
`endif
`ifdef DOUBLE
$fwrite(FileSaveDataDEC,"%f\n",$bitstoreal(final_result_ieee));
`endif
end
end
always @(negedge clk) begin
#(PERIOD/5);
if(~busy & ~rst) begin
beg_OP = 1;
end
end
always @(posedge clk) begin
#(PERIOD/5);
if(rst) begin
contador = 0;
end
else if(~busy & ~rst) begin
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
repeat(3) @(posedge clk);
end
end
// clock
initial begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_logic
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_logic.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_logic.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_logic
//
// No user `defines in this module
module avfb_logic
//
// Generated module i_avfb_logic
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top_rs
avfb_top_rs i_avfb_top_rs (
);
// End of Generated Instance Port Map for i_avfb_top_rs
endmodule
//
// End of Generated Module rtl of avfb_logic
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:12:44 04/03/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(Address, RW, CS, clk, Reset, AB, AN, dig
);
parameter SIZE = 5;
parameter LEDSIZE = 8;
input clk, Reset;
input [SIZE-1:0] Address;
input RW, AB;
input [1:0] CS;
output reg [7:0] dig;
output wire [3:0] AN;
reg [31:0] W_Data;
wire [31:0] R_Data_A, R_Data_B, LED_Data;
wire [63:0] Seg;
assign LED_Data = AB ? R_Data_A : R_Data_B;
clock CL (
.clock(clk),
.AN(AN),
.rst(Reset)
);
register instance_name (
.clk(clk),
.Reset(Reset),
.R_Addr_A(Address),
.R_Addr_B(Address),
.W_Addr(Address),
.W_Data(W_Data),
.Write_Reg(RW),
.R_Data_A(R_Data_A),
.R_Data_B(R_Data_B)
);
DIGITAL D1 (
.Data(LED_Data[3:0]),
.Seg(Seg[7:0])
);
DIGITAL D2 (
.Data(LED_Data[7:4]),
.Seg(Seg[15:8])
);
DIGITAL D3 (
.Data(LED_Data[11:8]),
.Seg(Seg[23:16])
);
DIGITAL D4 (
.Data(LED_Data[15:12]),
.Seg(Seg[31:24])
);
DIGITAL D5 (
.Data(LED_Data[19:16]),
.Seg(Seg[39:32])
);
DIGITAL D6 (
.Data(LED_Data[23:20]),
.Seg(Seg[47:40])
);
DIGITAL D7 (
.Data(LED_Data[27:24]),
.Seg(Seg[55:48])
);
DIGITAL D8 (
.Data(LED_Data[31:28]),
.Seg(Seg[63:56])
);
always @(*)
begin
W_Data=32'h0000_0000;
dig <= 8'b01110001;
if(RW)
begin
case(CS)
2'b00: W_Data= 32'h1234_5678;
2'b01: W_Data= 32'h89AB_CDEF;
2'b10: W_Data= 32'h7FFF_FFFF;
2'b11: W_Data= 32'hFFFF_FFFF;
endcase
end
else
begin
if (CS==2'b00)
begin
case(AN)
4'b0111:dig[7:0] <= Seg[7:0];
4'b1011:dig[7:0] <= Seg[15:8];
4'b1101:dig[7:0] <= Seg[23:16];
4'b1110:dig[7:0] <= Seg[31:24];
default: dig[7:0] <= Seg[7:0];
endcase
end
else
begin
case(AN)
4'b0111:dig[7:0] <= Seg[39:32];
4'b1011:dig[7:0] <= Seg[47:40];
4'b1101:dig[7:0] <= Seg[55:48];
4'b1110:dig[7:0] <= Seg[63:56];
default: dig[7:0] <= Seg[7:0];
endcase
end
end
end
endmodule
module register(clk, Reset, R_Addr_A, R_Addr_B, W_Addr, W_Data, Write_Reg, R_Data_A, R_Data_B
);
input clk;
input Reset;
input Write_Reg;
input [4:0] R_Addr_A, R_Addr_B, W_Addr;
input [31:0] W_Data;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0] REGISTERS[0:31];
integer i;
assign R_Data_A = REGISTERS[R_Addr_A];
assign R_Data_B = REGISTERS[R_Addr_B];
always @(posedge clk or posedge Reset)
begin
if(Reset)
begin
for(i=0; i<=31; i=i+1)
begin
REGISTERS[i]<=32'h0000_0000;
end
end
else
begin
if(Write_Reg)
begin
REGISTERS[W_Addr]<=W_Data;
end
end
end
endmodule
module DIGITAL(Data, Seg);
input [3:0] Data;
output reg [7:0] Seg;
always @(*)
begin
case (Data)
'd0: Seg[7:0] <= 8'b00000011;
'd1: Seg[7:0] <= 8'b10011111;
'd2: Seg[7:0] <= 8'b00100101;
'd3: Seg[7:0] <= 8'b00001101;
'd4: Seg[7:0] <= 8'b10011001;
'd5: Seg[7:0] <= 8'b01001001;
'd6: Seg[7:0] <= 8'b01000001;
'd7: Seg[7:0] <= 8'b00011111;
'd8: Seg[7:0] <= 8'b00000001;
'd9: Seg[7:0] <= 8'b00001001;
'd10: Seg[7:0] <= 8'b00010001;
'd11: Seg[7:0] <= 8'b11000001;
'd12: Seg[7:0] <= 8'b01100011;
'd13: Seg[7:0] <= 8'b10000101;
'd14: Seg[7:0] <= 8'b01100001;
'd15: Seg[7:0] <= 8'b01110001;
default: Seg[7:0] <= 8'b11111111;
endcase
end
endmodule
module clock(clock, AN, rst);
input clock;
input rst;
output reg [3:0] AN;
reg [1:0] Bit_Sel;
reg [17:0] count;
always@(posedge clock or posedge rst)
begin
if(rst)
begin
Bit_Sel <= 2'b00;
count <= 18'd0;
end
else
begin
if (count == 18'd260000)
begin
Bit_Sel <= Bit_Sel + 1'b1;
count <=18'd0;
end
else
begin
count <= count + 1'b1;
end
end
end
always @(*)
begin
case (Bit_Sel)
2'b00: AN <= 4'b0111;
2'b01: AN <= 4'b1011;
2'b10: AN <= 4'b1101;
2'b11: AN <= 4'b1110;
default: AN <= 4'b0000;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
|
// part of NeoGS project
//
// (c) NedoPC 2007-2009
//
// SD-card dma controller
//
// includes dma address regs, dma control reg
/*
Read from sd-card modes:
1. Full burst: first all 512 bytes are read into 512b buffer, then dma-bursted into main memory.
Not as fast in latency, but steals minimum of CPU cycles, though stops cpu for 1024+ clocks (if no other DMAs are active)
2. As soon as possible: initiates DMA as soon as new byte is arrived into 512b buffer.
Makes bursts of 2-3 bytes, when applicable (more bytes arriven since beginning of dma_req up to acknowledge in dma_ack)
Write to sd-card modes:
1. Full burst: all 512 bytes are read in one burst, transmission starts as soon as first byte arrives to the buffer.
Uses minimum of CPU cycles (1024+) but in one chunk.
2. DMA initiated as soon as spi is again ready to initiate new transfer (kind a throttling). Probably DMA pulls 2 or 4 bytes at once.
Structure:
- FIFO based on mem512b and two pointers
- SD controller - FSM which either reads or writes SD-card SPI iface
- DMA controller - FSM which either reads or writes DMA iface
- overall control - Controls operation of everything above, controls muxing of data to the
SD write port and FIFO write port, tracks operation end, maintains DMA_ADDRESS registers.
*/
module dma_sd(
input wire clk,
input wire rst_n,
// control to spi module of SD-card
//
output reg sd_start,
input wire sd_rdy,
input wire [7:0] sd_receiveddata,
output wire [7:0] sd_datatosend,
//
output reg sd_override, // when 1, override sd_start and sd_datatosend to the sd spi module
// signals for ports.v
//
input wire [7:0] din, // input and output from ports.v
output reg [7:0] dout,
//
input wire module_select, // =1 - module selected for read-write operations from ports.v
input wire write_strobe, // one-cycle positive write strobe - writes to the selected registers from din
//
input wire [1:0] regsel, // 2'b00 - high address, 2'b01 - middle address, 2'b10 - low address, 2'b11 - control register
// signals for DMA controller/DMA sequencer
//
output reg [20:0] dma_addr,
output wire [7:0] dma_wd, // data written to DMA
input wire [7:0] dma_rd, // data read from DMA
output reg dma_rnw,
//
output wire dma_req,
input wire dma_ack,
input wire dma_end
);
localparam _HAD = 2'b00; // high address
localparam _MAD = 2'b01; // mid address
localparam _LAD = 2'b10; // low address
localparam _CST = 2'b11; // control and status
reg dma_snr; // Send-NotReceive. Send to SDcard (==1) or Receive (==0) from it.
reg dma_burst; // whether burst transfers are on
// control dout bus
always @*
case( regsel[1:0] )
_HAD: dout = { 3'b000, dma_addr[20:16] };
_MAD: dout = dma_addr[15:8];
_LAD: dout = dma_addr[7:0];
_CST: dout = { dma_on, 5'bXXXXX, dma_burst, dma_snr};
endcase
// ports.v write access & dma_addr control
always @(posedge clk, negedge rst_n)
if( !rst_n ) // async reset
begin
dma_on <= 1'b0;
dma_snr <= 1'b0; // receive is less dangerous since it won't destroy SDcard info
dma_burst <= 1'b0;
end
else // posedge clk
begin
// dma_on control
if( module_select && write_strobe && (regsel==_CST) )
begin
dma_on <= din[7];
dma_burst <= din[1];
dma_snr <= din[0];
end
else if( dma_finish )
begin
dma_on <= 1'b0;
end
// dma_addr control
if( dma_ack && dma_on )
dma_addr <= dma_addr + 21'd1; // increment on beginning of DMA transfer
else if( module_select && write_strobe )
begin
if( regsel==_HAD )
dma_addr[20:16] <= din[4:0];
else if( regsel==_MAD )
dma_addr[15:8] <= din[7:0];
else if( regsel==_LAD )
dma_addr[7:0] <= din[7:0];
end
end
// fifo,dma,sd control FSMs/etc.
reg init;
wire wr_stb,rd_stb;
wire wdone,rdone,empty;
wire [7:0] fifo_wd; // data for FIFO to be written
wire [7:0] fido_rd; // data read from FIFO
// MUX data to FIFO
assign fifo_wd = dma_snr ? dma_rd : sd_receiveddata;
// MUX data to SDcard
assign sd_datatosend = dma_snr ? fifo_rd : 8'hFF;
// connect dma in to fifo out without muxing
assign dma_wd = fifo_rd;
fifo512_oneshot fifo512_oneshot ( .clk(clk),
.rst_n(rst_n),
.init(init),
.wr_stb(wr_stb),
.rd_stb(rd_stb),
.wdone(wdone),
.rdone(rdone),
.empty(empty),
.wd(fifo_wd),
.rd(fifo_rd)
);
// fifo control
reg sd_wr_stb,sd_rd_stb; // set in SD FSM
reg dma_wr_stb,dma_rd_stb; // set in DMA FSM
//
assign wr_stb = sd_wr_stb | dma_wr_stb;
assign rd_stb = sd_rd_stb | dma_rd_stb;
// dma control
wire dma_put_req;
wire dma_get_req;
assign dma_req = dma_put_req | dma_get_req;
reg sd_go; // start strobe for SD FSM
reg sd_idle; // whether SD FSM is idle
reg dma_go;
reg dma_idle;
// SD-card controlling FSM
reg [2:0] sd_state, sd_next_state;
localparam SD_IDLE = 3'b000;
localparam SD_READ1 = 3'b100;
localparam SD_READ2 = 3'b101;
localparam SD_WRITE1 = 3'b110;
localparam SD_WRITE2 = 3'b111;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
sd_state = SD_IDLE;
end
else // posedge clk
begin
sd_state <= sd_next_state;
end
end
always @*
begin
case( sd_state )
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_IDLE:begin
if( sd_go )
begin
if( sd_snr ) // send to SD
begin
sd_next_state = SD_WRITE1;
end
else // !sd_snr: read from SD
begin
sd_next_state = SD_READ1;
end
end
else
begin
sd_next_state = SD_IDLE;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_READ1:begin
if( wdone )
begin
sd_next_state = SD_IDLE;
end
else // !wdone - can still send bytes to the fifo
begin
if( !sd_rdy ) // not ready with previous byte - wait here
begin
sd_next_state = SD_READ1;
end
else // sd_rdy - can proceed further
begin
sd_next_state = SD_READ2;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_READ2:begin
sd_next_state = SD_READ1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_WRITE1:begin
if( rdone )
begin
sd_next_state = SD_IDLE;
end
else
begin
if( sd_rdy && !empty ) // whether sd ready and we can take next byte from fifo
begin
sd_next_state = SD_WRITE2;
end
else // can't start next byte: wait
begin
sd_next_state = SD_WRITE1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_WRITE2:begin
sd_next_state = SD_WRITE1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
default:begin
sd_next_state = SD_IDLE;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
sd_wr_stb = 1'b0;
sd_rd_stb = 1'b0;
sd_start = 1'b0;
sd_override = 1'b0;
sd_idle = 1'b0;
end
else // posedge clk
begin
case( sd_next_state )
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_IDLE:begin
sd_wr_stb <= 1'b0;
sd_rd_stb <= 1'b0;
sd_start <= 1'b0;
sd_override <= 1'b0;
sd_idle <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_READ1:begin
sd_override <= 1'b1; // takeover SD card SPI iface
sd_start <= 1'b0;
sd_wr_stb <= 1'b0;
sd_idle <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_READ2:begin
sd_start <= 1'b1; // trigger new SPI exchange
sd_wr_stb <= 1'b1; // trigger FIFO write
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_WRITE1:begin
sd_override <= 1'b1;
sd_start <= 1'b0;
sd_rd_str <= 1'b0;
sd_idle <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SD_WRITE2:begin
sd_start <= 1'b1;
sd_rd_stb <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
// DMA-controlling FSM
reg [3:0] dma_state, dma_next_state
localparam DMA_IDLE
localparam DMA_PUT_WAIT
localparam DMA_PUT_RUN
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
dma_state = DMA_IDLE;
end
else // posedge clk
begin
dma_state <= dma_next_state;
end
end
always @*
begin
case( dma_state )
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
DMA_IDLE:begin
if( dma_go )
begin
if( dma_snr )
begin
........dma_state = DMA_GET_WAIT;
end
else // !dma_snr
begin
dma_next_state = DMA_PUT_WAIT;
end
end
else
begin
dma_next_state = DMA_IDLE;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
DMA_PUT_WAIT:begin
if( rdone )
begin
dma_next_state = DMA_IDLE;
end
else // !rdone
begin
if( !empty ) // fifo is not empty
begin
dma_next_state = DMA_PUT_RUN;
end
else // fifo empty
begin
dma_next_state = DMA_PUT_WAIT;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
DMA_PUT_RUN:begin
if( rdone )
begin
dma_next_state = DMA_IDLE;
end
else
begin
if( empty )
begin
dma_next_state = DMA_PUT_WAIT;
end
else // !empty
begin
dma_next_state = DMA_PUT_RUN;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
end
else // posedge clk
begin
case( dma_next_state )
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
endmodule
// this is "one-shot" fifo: after each 512 bytes both written and read back, it must be initialized by means of 'init'
//
module fifo512_oneshot(
input wire clk,
input wire rst_n,
input wire init, // initializes fifo: wptr=rptr=0
input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr
input wire rd_stb, // read strobe: increments rptr
output wire wdone, // write done - all 512 bytes are written (end of write operation)
output wire rdone, // read done - all 512 bytes are read (end of read operation)
output wire empty, // fifo empty: when wptr==rptr (rd_stb must not be issued when empty is active, otherwise everytrhing desyncs)
input wire [7:0] wd, // data to be written
output wire [7:0] rd // data just read from rptr address
);
reg [9:0] wptr;
reg [9:0] rptr;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
wptr = 10'd0;
rptr = 10'd0;
end
else
begin // posedge clk
if( init )
begin
wptr <= 10'd0;
end
else if( wr_stb )
begin
wptr <= wptr + 10'd1;
end
if( init )
begin
rptr <= 10'd0;
end
else if( rd_stb )
begin
rptr <= rptr + 10'd1;
end
end
end
assign wdone = wptr[9];
assign rdone = rptr[9];
assign empty = ( wptr==rptr );
mem512b fifo512_oneshot_mem512b( .clk(clk),
.rdaddr(rptr[8:0]),
.dataout(rd),
.wraddr(wptr[8:0]),
.datain(wd),
.we(wr_stb)
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The module to implement the core's debug control and relevant CSRs
//
// ===========================================================================
`include "e203_defines.v"
module sirv_debug_csr
#(
parameter PC_SIZE = 32
)(
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
input clk,
input rst_n
);
// Implement DPC reg
wire dpc_ena = wr_dpc_ena | cmt_dpc_ena;
wire [PC_SIZE-1:0] dpc_nxt;
assign dpc_nxt[PC_SIZE-1:1] =
cmt_dpc_ena ? cmt_dpc[PC_SIZE-1:1]
: wr_csr_nxt[PC_SIZE-1:1];
assign dpc_nxt[0] = 1'b0;
sirv_gnrl_dfflr #(PC_SIZE) dpc_dfflr (dpc_ena, dpc_nxt, dpc_r, clk, rst_n);
// Implement Dbg Scratch reg
wire dscratch_ena = wr_dscratch_ena;
wire [32-1:0] dscratch_nxt;
assign dscratch_nxt = wr_csr_nxt;
sirv_gnrl_dfflr #(32) dscratch_dfflr (dscratch_ena, dscratch_nxt, dscratch_r, clk, rst_n);
// We dont support the HW Trigger Module yet now
// Implement dcsr reg
//
// The ndreset field
wire ndreset_ena = wr_dcsr_ena & wr_csr_nxt[29];
wire ndreset_nxt;
wire ndreset_r;
assign ndreset_nxt = wr_csr_nxt[29];
sirv_gnrl_dfflr #(1) ndreset_dfflr (ndreset_ena, ndreset_nxt, ndreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The fullreset field
wire fullreset_ena = wr_dcsr_ena & wr_csr_nxt[28];
wire fullreset_nxt;
wire fullreset_r;
assign fullreset_nxt = wr_csr_nxt[28];
sirv_gnrl_dfflr #(1) fullreset_dfflr (fullreset_ena, fullreset_nxt, fullreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The cause field
wire dcause_ena = cmt_dcause_ena;
wire [3-1:0] dcause_r;
wire [3-1:0] dcause_nxt = cmt_dcause;
sirv_gnrl_dfflr #(3) dcause_dfflr (dcause_ena, dcause_nxt, dcause_r, clk, rst_n);
//
// The halt field
wire halt_ena = wr_dcsr_ena;
wire halt_nxt;
wire halt_r;
assign halt_nxt = wr_csr_nxt[3];
sirv_gnrl_dfflr #(1) halt_dfflr (halt_ena, halt_nxt, halt_r, clk, rst_n);
//
// The step field
wire step_ena = wr_dcsr_ena;
wire step_nxt;
wire step_r;
assign step_nxt = wr_csr_nxt[2];
sirv_gnrl_dfflr #(1) step_dfflr (step_ena, step_nxt, step_r, clk, rst_n);
//
// The ebreakm field
wire ebreakm_ena = wr_dcsr_ena;
wire ebreakm_nxt;
wire ebreakm_r;
assign ebreakm_nxt = wr_csr_nxt[15];
sirv_gnrl_dfflr #(1) ebreakm_dfflr (ebreakm_ena, ebreakm_nxt, ebreakm_r, clk, rst_n);
//
// // The stopcycle field
//wire stopcycle_ena = wr_dcsr_ena;
//wire stopcycle_nxt;
//wire stopcycle_r;
//assign stopcycle_nxt = wr_csr_nxt[10];
//sirv_gnrl_dfflr #(1) stopcycle_dfflr (stopcycle_ena, stopcycle_nxt, stopcycle_r, clk, rst_n);
// //
// // The stoptime field
//wire stoptime_ena = wr_dcsr_ena;
//wire stoptime_nxt;
//wire stoptime_r;
//assign stoptime_nxt = wr_csr_nxt[9];
//sirv_gnrl_dfflr #(1) stoptime_dfflr (stoptime_ena, stoptime_nxt, stoptime_r, clk, rst_n);
assign dbg_stopcycle = 1'b1;
assign dcsr_r [31:30] = 2'd1;
assign dcsr_r [29:16] = 14'b0;
assign dcsr_r [15:12] = {4{ebreakm_r}};// we replicated the ebreakm for all ebreakh/s/u
assign dcsr_r [11] = 1'b0;
assign dcsr_r [10] = dbg_stopcycle;// Not writeable this bit is constant
assign dcsr_r [9] = 1'b0;//stoptime_r; Not use this bit same as rocket implmementation
assign dcsr_r [8:6] = dcause_r;
assign dcsr_r [5] = dbg_irq_r;
assign dcsr_r [4] = 1'b0;
assign dcsr_r [3] = halt_r;
assign dcsr_r [2] = step_r;
assign dcsr_r [1:0] = 2'b11;
assign dbg_mode = ~(dcause_r == 3'b0);
assign dbg_halt_r = halt_r;
assign dbg_step_r = step_r;
assign dbg_ebreakm_r = ebreakm_r;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.06.2017 16:47:20
// Design Name:
// Module Name: parte_7_2_lab
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module parte_7_2_lab(
input CLK100MHZ,
//input [15:0]SW,
input PS2_CLK,
input PS2_DATA,
input CPU_RESETN,
output VGA_HS,
output VGA_VS,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B
);
localparam CUADRILLA_XI = 212;
localparam CUADRILLA_XF = 812;
localparam CUADRILLA_YI = 184;
localparam CUADRILLA_YF = 584;
wire [10:0]vc_visible,hc_visible;
wire CLK82MHZ;
clk_wiz_0 inst(
// Clock out ports
.clk_out1(CLK82MHZ),
// Status and control signals
.reset(1'b0),
//.locked(locked),
// Clock in ports
.clk_in1(CLK100MHZ)
);
//driver_vga_640x480 m_driver(CLK82MHZ, VGA_HS, VGA_VS,hc_visible,vc_visible);
driver_vga_1024x768 m_driver(CLK82MHZ, VGA_HS, VGA_VS, hc_visible, vc_visible);
kbd_ms m_kd(CLK82MHZ, 1'b0, PS2_DATA, PS2_CLK, data, data_type, kbs_tot, parity_error);
wire kbs_tot;
wire [7:0] data;
wire [2:0] data_type;
wire parity_error;
wire [10:0]hc_template, vc_template;
wire [2:0]matrix_x;
wire [1:0]matrix_y;
wire lines;
// template_6x4_600x400 template_1(CLK82MHZ, hc_visible, vc_visible, matrix_x, matrix_y, lines);
reg [11:0]VGA_COLOR;
wire in_sq, dr;
hello_world_text_square m_hw(CLK82MHZ, 1'b0, hc_visible, vc_visible, in_sq, dr);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
wire in_sq_mas_1,in_sq_mas_2,in_sq_mas_3,in_sq_mas_4,in_sq_fecha,in_sq_hello;
wire in_ch_mas_1,in_ch_mas_2,in_ch_mas_3,in_ch_mas_4,in_ch_fecha,in_ch_hello;
show_one_char
#( .MENU_X_LOCATION (11'd1),
.MENU_Y_LOCATION (11'd1)
) show_mas_1
(
.clk(CLK82MHZ),
.rst(1'b0),
.hc_visible(hc_visible),
.vc_visible(vc_visible),
.the_char(8'd201),
.in_square(in_sq_mas_1),
.in_character(in_ch_mas_2)
);
// show_one_char
// #( .MENU_X_LOCATION (11'd824),
// .MENU_Y_LOCATION (11'd1)
// ) show_mas_2
// (
// .clk(CLK82MHZ),
// .rst(1'b0),
// .hc_visible(hc_visible),
// .vc_visible(vc_visible),
// .the_char(8'd20),
// .in_square(in_sq_mas_2),
// .in_character(in_ch_mas_2)
// );
show_one_char
#( .MENU_X_LOCATION (11'd1),
.MENU_Y_LOCATION (11'd668)
) show_mas_3
(
.clk(CLK82MHZ),
.rst(1'b0),
.hc_visible(hc_visible),
.vc_visible(vc_visible),
.the_char(8'd20),
.in_square(in_sq_mas_3),
.in_character(in_ch_mas_3)
);
show_one_char
#( .MENU_X_LOCATION (11'd824),
.MENU_Y_LOCATION (11'd668)
) show_mas_4
(
.clk(CLK82MHZ),
.rst(1'b0),
.hc_visible(hc_visible),
.vc_visible(vc_visible),
.the_char(8'd20),
.in_square(in_sq_mas_4),
.in_character(in_ch_mas_4)
);
show_one_line
#(.MENU_X_LOCATION (11'd252),
.MENU_Y_LOCATION (11'd12)
) schow_fecha
(
.clk(CLK82MHZ),
.rst(1'b0),
.hc_visible(hc_visible),
.vc_visible(vc_visible),
.the_line({"27 06 2017"}),
.in_square(in_fecha),
.in_character(in_ch_fecha)
);
hello_world_text_square hello
(
.clk(CLK82MHZ),
.rst(1'b0),
.hc_visible(hc_visible),
.vc_visible(vc_visible),
.in_square(in_sq_hello),
.in_character(in_ch_hello)
);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
wire [5:0] cuadros;
wire [5:0] letras;
assign cuadros = {in_sq_mas_1,in_sq_mas_2,in_sq_mas_3,in_sq_mas_4,in_fecha,in_sq_hello};
assign letras = {in_ch_mas_1,in_ch_mas_2,in_ch_mas_3,in_ch_mas_4,in_ch_fecha,in_ch_hello};
always @(*) begin
if((hc_visible != 0) && (vc_visible != 0)) begin
if(letras != 6'b0)
VGA_COLOR=12'hFFF;
else if(cuadros != 6'b0)
VGA_COLOR=12'hABC;
else
VGA_COLOR=12'h6FA;
end
else begin
VGA_COLOR=12'h000;
end
end
assign {VGA_R, VGA_G, VGA_B} = VGA_COLOR;
endmodule
|
/*
* Copyright (C) 2014-2016 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
* Xilinx internal configuration access port
*
* 100 MHz max
*/
`timescale 1ns / 1ps
module icap(input c, w, input [31:0] i);
wire [31:0] swapped;
genvar j;
generate
for(j=0; j<32; j=j+1)
begin : swap
assign swapped[j] = i[31-j];
end
endgenerate
// Write and CE are active low, I is bit swapped
ICAPE2 #(.ICAP_WIDTH("X32")) ICAP_i
(.O(),
.CLK(c),
.CSIB(~w),
.I({swapped[7:0], swapped[15:8], swapped[23:16], swapped[31:24]}),
.RDWRB(1'b0));
endmodule
|
// file: Clock70MHz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____70.000______0.000______50.0______485.714____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock70MHz,clk_wiz_v3_6,{component_name=Clock70MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock70MHz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (7),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : TC Top Level
// File : de3d_tc_top.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module de3d_tc_top
#(parameter BYTES = 4)
(
// DE SIGNALS
input de_clk, // Clock for Drawing Engine
input de_rstn, // Reset for Drawing Engine
input pc_busy, // Pixel cache busy.
input push_uv, // Push UV.
input [31:0] tex_2, // texture control register.
//
input current_clip_g1, // When high, return a de_ack
input [8:0] current_bit_mask_x_g1, // Mask for X size of bitmap
input [8:0] current_bit_mask_y_g1, // Mask for Y size of bitmap
input [3:0] current_mipmap_g1, // mipmap we are currently on
input current_exact_g1, // only fetch one texel at ul_x,ul_y
input [10:0] current_u_g1, // Upper left texel (U)
input [10:0] current_v_g1, // Upper left texel (V)
//
input [209:0] lod_2, // LOD origin.
input pal_load, // Load palette
input tc_inv, // Invalidate texel cache
// 000001 1bpt 0565
// 000010 1bpt 4444
// 000011 1bpt 8888
// 000100 2bpt 1555
// 000101 2bpt 0565
// 000110 2bpt 4444
// 000111 2bpt 8888
// 001000 4bpt 1555
// 001001 4bpt 0565
// 001010 4bpt 4444
// 001011 4bpt 8888
// 001100 8bpt 1232
// 001101 8bpt 0332
// 001110 8bpt 1555
// 001111 8bpt 0565
// 011100 8bpt 4444
// 011101 8bpt 8888 (exact)
// 111110 8bpt 8888 (16-4444)
// 111111 8bpt 8888 (16-0565)
// 011110 8bpt 8332
// 010000 16bpt 4444
// 010001 16bpt 1555
// 010010 16bpt 0565
// 010011 16bpt 8332
// 010100 32bpt 8888
// 011000 1bpt 8332
// 011001 2bpt 8332
// 011010 4bpt 8332
// OpenGL modes 100000 Alpha4
// 100001 Alpha8
// 100100 Luminance4
// 100101 Luminance8
// 101000 Luminance4_alpha4
// 101001 Luminance6_alpha2
// 101010 Luminance8_alpha8
// 101100 Intensity4
// 101101 Intensity8
// 110000 RGBA2
input [11:0] tptch, // Texture pitch to be sent to DEM
// input [31:0] torg, // Texture pitch to be sent to DEM
input [31:0] boarder_color, // boarder color (3rd pipe stage)
// DE SIGNALS
output [7:0] usedw_tc,
output full_tc,
output tc_ack, // load input values into lvl 2 register
output tc_ready, // Texture cache ack's uv load
output tc_ready_e, // Texture cache ack's uv load
output tc_busy, // Texel cache is busyto DE during load
output [31:0] ul_tex, // Upper left texel
output [31:0] ll_tex, // Lower left texel
output [31:0] ur_tex, // Upper right texel
output [31:0] lr_tex, // Lower right texel
// MC Input
input mclock, // Memory controller clock.
input mc_tc_push,
input mc_tc_ack,
input [(BYTES<<3)-1:0] mc_tc_data, // for level 2 cache
input mc_pal_ack,
input mc_pal_push,
// MC Outputs.
output mc_tc_req, // Texture memory request.
output [5:0] mc_tc_page, // Number of Pages.
output [31:0] mc_tc_address, // Memory Address.
output mc_pal_req,
output mc_pal_half
);
`include "define_3d.h"
assign mc_tc_page = 6'b0001;
//////////////////////////////////////////////////////////////////////////
wire tex_en; // Texture Mode Enable
wire [5:0] tsize; // Texture map format: 000000 1bpt 1555
wire clamp_u; // clamp u
wire clamp_v; // clamp v
wire ccs; // clamp color selector (3rd pipe stage)
assign tex_en = tex_2`T_TM;
assign tsize = tex_2`T_SIZE;
assign clamp_u = tex_2`T_TCU;
assign clamp_v = tex_2`T_TCV;
assign ccs = tex_2`T_CCS;
wire exact_out;
wire [31:0] ul_tex_i;
wire [31:0] ll_tex_i;
wire [31:0] ur_tex_i;
wire [31:0] lr_tex_i;
wire [8:0] ul_x;
wire [8:0] ul_y;
wire [8:0] ll_x;
wire [8:0] ll_y;
wire [8:0] ur_x;
wire [8:0] ur_y;
wire [8:0] lr_x;
wire [8:0] lr_y;
wire [26:0] ul_tag;
wire [26:0] ll_tag;
wire [26:0] ur_tag;
wire [26:0] lr_tag;
wire [8:0] ul_store_x;
wire [8:0] ul_store_y;
wire [8:0] ll_store_x;
wire [8:0] ll_store_y;
wire [8:0] ur_store_x;
wire [8:0] ur_store_y;
wire [8:0] lr_store_x;
wire [8:0] lr_store_y;
wire [31:0] do0, do1,
do2, do3,
do4, do5,
do6, do7; /* Data out from RAM cells */
wire load_tag;
wire [7:0] ram_addr;
wire ld_push_count;
wire [3:0] push_count;
wire [3:0] tc_op; /* TC operations to preform: */
/* 0000:Loaded */
/* 0001:Load lr */
/* 0010:Load ur */
/* 0011:Load ur, lr */
/* 0100:Load ll */
/* 0101:Load ll, lr */
/* 0110:Load ll, ur */
/* 0111:Load ll, ur, lr */
/* 1000:Load ul */
/* 1001:Load ul, lr */
/* 1010:Load ul, ur */
/* 1011:Load ul, ur, lr */
/* 1100:Load ul, ll */
/* 1101:Load ul, ll, lr */
/* 1110:Load ul, ll, ur */
/* 1111:Load ul, ll, ur, lr */
wire clamp_ur; /* clamp data out of the cache */
wire clamp_ul; /* clamp data out of the cache */
wire clamp_lr; /* clamp data out of the cache */
wire clamp_ll; /* clamp data out of the cache */
wire clamp_ul_r; /* one cycle delayed clamp_ovd; */
wire clamp_ur_r; /* one cycle delayed clamp_ovd; */
wire clamp_ll_r; /* one cycle delayed clamp_ovd; */
wire clamp_lr_r; /* one cycle delayed clamp_ovd; */
wire invalidate; /* signal to invalidate the tags */
wire [2:0] bpt_r; /* bits per texel 1 cycle delay */
/* 1 =2 */
/* 2 =4 */
/* 3 =8 */
/* 4 =16 */
/* 5 =32 */
wire [4:0] tfmt_r; /* format of texture 1 cycle delay */
wire pal_mode_r;
wire [4:0] tfmt; /* format of texture: 0 =1555 */
/* 1 =0565 */
/* 2 =4444 */
/* 3 =8888 */
/* 4 =8332 */
/* 5 =1232 */
/* 6 =0332 */
/* See below for OPENGL formats */
wire ram_sel;
wire [3:0] tc_op_store;
wire [3:0] mipmap_store; /* Pipelined mipmap number */
wire [7:0] adr0_i, adr1_i, /* Addresses to memory RAMS */
adr2_i, adr3_i,
adr4_i, adr5_i,
adr6_i, adr7_i;
wire exception;
wire [3:0] set_sel; /* Set to be updated. */
wire [3:0] set_read; /* Set to be read. */
wire [7:0] hit_bus; /* Hits. */
wire ram_wen_lo;
wire ram_wen_hi;
wire [11:0] tex_ptch;
wire [20:0] tex_org;
wire [31:0] tex_address;
wire tc_fifo_empty;
wire tex_req;
wire [7:0] tex_fifo_wrused;
wire [1:0] req_count;
wire exact_r;
wire tag_ads;
wire done;
wire tc_fetch;
wire [4:0] ee_tag_adr_rd;
wire [4:0] eo_tag_adr_rd;
wire [4:0] oe_tag_adr_rd;
wire [4:0] oo_tag_adr_rd;
wire pop_uv; // Pop The UV fifo.
wire tc_fetch_n;
wire [2:0] bpt_d;
wire [4:0] tfmt_d;
wire pal_mode_d;
wire [2:0] bpt_dd;
wire [4:0] tfmt_dd;
wire pal_mode_dd;
wire push_uv_dd;
wire current_clip_dd;
wire current_exact_dd;
wire [3:0] current_mipmap_dd;
wire tc_clip_in;
wire [3:0] tc_mipmap;
wire tc_exact;
wire [8:0] tc_ul_x;
wire [8:0] tc_ul_y;
wire [8:0] tc_ur_x;
wire [8:0] tc_ur_y;
wire [8:0] tc_ll_x;
wire [8:0] tc_ll_y;
wire [8:0] tc_lr_x;
wire [8:0] tc_lr_y;
wire tc_clamp_ul;
wire tc_clamp_ur;
wire tc_clamp_ll;
wire tc_clamp_lr;
wire [2:0] tc_bpt;
wire [4:0] tc_tfmt;
wire tc_pal_mode;
wire [4:0] tc_ee_tag_adr_rd;
wire [4:0] tc_eo_tag_adr_rd;
wire [4:0] tc_oe_tag_adr_rd;
wire [4:0] tc_oo_tag_adr_rd;
// Palette RAM signals
wire [127:0] pal_mux;
wire pal_we;
wire [7:0] pal_addr_0;
wire [7:0] pal_addr_1;
wire [7:0] pal_addr_2;
wire [7:0] pal_addr_3;
reg [31:0] pal_ram0[255:0];
reg [31:0] pal_ram1[255:0];
reg [31:0] pal_ram2[255:0];
reg [31:0] pal_ram3[255:0];
reg [31:0] pal_lookup[3:0];
wire [7:0] pal_rdaddr_0;
wire [7:0] pal_rdaddr_1;
wire [7:0] pal_rdaddr_2;
wire [7:0] pal_rdaddr_3;
/* Instantiations */
// The fog table generator has 3 pipeline stages. This corresponds to the three stages
// in the texel cache. The texel cache stages are:
// 1) generate the opcodes and store them, plus RAM addresses
// REGISTER - pc_busy
// 2) get texel value and swizzle to 32 bit texels
// REGISTER - busy2
// 3) lookup palette entry
// REGISTER - busy3
// 4) format data and output to renderer
//
//
assign tc_fetch = ~tc_fetch_n & tex_en & ~pc_busy;
de3d_tc_fmt u_de3d_tc_fmt
(
.de_clk (de_clk),
.tsize (tsize),
.bpt (bpt_d),
.tfmt (tfmt_d),
.pal_mode (pal_mode_d)
);
de3d_tc_addr_in u_de3d_tc_addr_in
(
// Inputs.
.de_clk (de_clk),
.bpt_d (bpt_d),
.tfmt_d (tfmt_d),
.pal_mode_d (pal_mode_d),
.push_uv (push_uv & tex_en),
.current_clip (current_clip_g1),
.bitmask_x (current_bit_mask_x_g1),
.bitmask_y (current_bit_mask_y_g1),
.current_mipmap (current_mipmap_g1),
.current_exact (current_exact_g1),
.ul_u (current_u_g1),
.ul_v (current_v_g1),
.clamp_x (clamp_u), // clamp u
.clamp_y (clamp_v), // clamp v
// Outputs.
.push_uv_dd (push_uv_dd),
.current_clip_dd (current_clip_dd),
.current_mipmap_dd (current_mipmap_dd),
.current_exact_dd (current_exact_dd),
.ul_x (ul_x),
.ul_y (ul_y),
.ur_x (ur_x),
.ur_y (ur_y),
.ll_x (ll_x),
.ll_y (ll_y),
.lr_x (lr_x),
.lr_y (lr_y),
.clamp_ul (clamp_ul),
.clamp_ur (clamp_ur),
.clamp_ll (clamp_ll),
.clamp_lr (clamp_lr),
.bpt_dd (bpt_dd),
.tfmt_dd (tfmt_dd),
.pal_mode_dd (pal_mode_dd),
.ee_tag_adr_rd (ee_tag_adr_rd),
.eo_tag_adr_rd (eo_tag_adr_rd),
.oe_tag_adr_rd (oe_tag_adr_rd),
.oo_tag_adr_rd (oo_tag_adr_rd)
);
// Current UV for Texture Cache..
// This needs to be a look ahead fifo.
sfifo_112x256_la u_sfifo_112x256_uv_tc
(
.aclr (~de_rstn),
.clock (de_clk),
.data ({
1'b0, // Spare bits.
pal_mode_dd,
current_clip_dd, // 1 bit
current_mipmap_dd, // 4 bits
current_exact_dd, // 1 bit
ul_x, // 9 bits
ul_y, // 9 bits
ur_x, // 9 bits
ur_y, // 9 bits
ll_x, // 9 bits
ll_y, // 9 bits
lr_x, // 9 bits
lr_y, // 9 bits
clamp_ul, // 1 bit
clamp_ur, // 1 bit
clamp_ll, // 1 bit
clamp_lr, // 1 bit
bpt_dd, // 3 bits
tfmt_dd, // 5 bits
ee_tag_adr_rd, // 5 bits
eo_tag_adr_rd, // 5 bits
oe_tag_adr_rd, // 5 bits
oo_tag_adr_rd // 5 bits
}),
.wrreq (push_uv_dd & tex_en),
.rdreq (pop_uv), // tc_ready), // tc_ack),
.q ({
tc_pal_mode, // 1 bit
tc_clip_in, // 1 bit.
tc_mipmap, // 4 bits.
tc_exact, // 1 bit.
tc_ul_x, // 9 bits
tc_ul_y, // 9 bits
tc_ur_x, // 9 bits
tc_ur_y, // 9 bits
tc_ll_x, // 9 bits
tc_ll_y, // 9 bits
tc_lr_x, // 9 bits
tc_lr_y, // 9 bits
tc_clamp_ul, // 1 bits
tc_clamp_ur, // 1 bits
tc_clamp_ll, // 1 bits
tc_clamp_lr, // 1 bits
tc_bpt, // 3 bits
tc_tfmt, // 5 bits
tc_ee_tag_adr_rd, // 5 bits
tc_eo_tag_adr_rd, // 5 bits
tc_oe_tag_adr_rd, // 5 bits
tc_oo_tag_adr_rd // 5 bits
}),
.empty (tc_fetch_n),
.usedw (usedw_tc),
.full (),
.almost_full (full_tc)
);
de3d_tc_tag u_de3d_tc_tag
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_tag (load_tag),
.tag_ads (tag_ads),
.bpt (tc_bpt),
.tc_op_store (tc_op_store),
.ee_tag_adr_rd (tc_ee_tag_adr_rd),
.eo_tag_adr_rd (tc_eo_tag_adr_rd),
.oe_tag_adr_rd (tc_oe_tag_adr_rd),
.oo_tag_adr_rd (tc_oo_tag_adr_rd),
.ul_tag_adr_rd ({tc_ul_x[8:3], tc_ul_y}),
.ll_tag_adr_rd ({tc_ll_x[8:3], tc_ll_y}),
.ur_tag_adr_rd ({tc_ur_x[8:3], tc_ur_y}),
.lr_tag_adr_rd ({tc_lr_x[8:3], tc_lr_y}),
.ul_tag_adr_wr ({ul_store_x[8:3],ul_store_y[8:0]}),
.ll_tag_adr_wr ({ll_store_x[8:3],ll_store_y[8:0]}),
.ur_tag_adr_wr ({ur_store_x[8:3],ur_store_y[8:0]}),
.lr_tag_adr_wr ({lr_store_x[8:3],lr_store_y[8:0]}),
.invalidate (invalidate),
.cur_mipmap (mipmap_store),
.set_sel (set_sel),
.hit_bus (hit_bus),
.tc_fetch (tc_fetch),
// Outputs
.ul_tag (ul_tag),
.ll_tag (ll_tag),
.ur_tag (ur_tag),
.lr_tag (lr_tag),
.exception (exception)
);
de3d_tc_store u_de3d_tc_store
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.tc_ack (tc_ack),
.mipmap (tc_mipmap),
.lod_2 (lod_2),
.ul ({tc_ul_x, tc_ul_y}),
.ur ({tc_ur_x, tc_ur_y}),
.ll ({tc_ll_x, tc_ll_y}),
.lr ({tc_lr_x, tc_lr_y}),
.clamp_ur (tc_clamp_ur),
.clamp_ul (tc_clamp_ul),
.clamp_lr (tc_clamp_lr),
.clamp_ll (tc_clamp_ll),
.bpt (tc_bpt),
.tfmt (tc_tfmt),
.pal_mode (tc_pal_mode),
.tc_op (tc_op),
.tptch (tptch),
.exact (tc_exact),
// Outputs.
.mipmap_store (mipmap_store),
.clamp_ul_r (clamp_ul_r),
.clamp_ll_r (clamp_ll_r),
.clamp_ur_r (clamp_ur_r),
.clamp_lr_r (clamp_lr_r),
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bpt_r (bpt_r),
.tfmt_r (tfmt_r),
.pal_mode_r (pal_mode_r),
.exact_r (exact_r),
.tc_op_store (tc_op_store),
.tex_org (tex_org),
.tex_ptch (tex_ptch)
);
de3d_tc_compare u_de3d_tc_compare
(
// Inputs.
.de_clk (de_clk),
.de_rstn (de_rstn),
.tc_ack (tc_ack),
.ur ({tc_ur_x, tc_ur_y}),
.ul ({tc_ul_x, tc_ul_y}),
.lr ({tc_lr_x, tc_lr_y}),
.ll ({tc_ll_x, tc_ll_y}),
.mipmap_in (tc_mipmap),
.ul_tag (ul_tag),
.ll_tag (ll_tag),
.ur_tag (ur_tag),
.lr_tag (lr_tag),
.exception (exception),
.bpt (tc_bpt),
.tc_exact (tc_exact),
.clip (tc_clip_in),
// Outputs.
.tc_op (tc_op),
.set_sel (set_sel),
.set_read (set_read),
.hit_bus (hit_bus)
);
de3d_tc_sm u_de3d_tc_sm
(
// Inputs.
.de_clk (de_clk),
.mc_clk (mclock),
.de_rstn (de_rstn),
.tc_op (tc_op),
.tc_fetch (tc_fetch),
.clip_in (1'b0),
.pc_busy (pc_busy),
.pal_load (pal_load),
.tc_inv (tc_inv),
.done (done),
.tex_fifo_wrused (tex_fifo_wrused),
.tex_en (tex_en),
.pal_ack (mc_pal_ack),
.mc_pal_push (mc_pal_push),
.mc_data (mc_tc_data),
// Outputs.
.invalidate (invalidate),
.tc_busy (tc_busy),
.load_tag (load_tag),
.tag_ads (tag_ads),
.tex_req (tex_req),
.pal_req (mc_pal_req),
.pal_half (mc_pal_half),
.tc_ack (tc_ack),
.tc_ready (tc_ready),
.tc_ready_e (tc_ready_e),
.ld_push_count (ld_push_count),
.push_count (push_count),
.req_count (req_count),
.pop_uv (pop_uv),
.pal_mux (pal_mux),
.pal_we (pal_we),
.pal_addr_0 (pal_addr_0),
.pal_addr_1 (pal_addr_1),
.pal_addr_2 (pal_addr_2),
.pal_addr_3 (pal_addr_3)
);
// infer 4 32x256 simple dual port RAMs
always @(posedge mclock) begin
if (pal_we) pal_ram0[pal_addr_0] <= pal_mux[31:0];
if (pal_we) pal_ram1[pal_addr_1] <= pal_mux[63:32];
if (pal_we) pal_ram2[pal_addr_2] <= pal_mux[95:64];
if (pal_we) pal_ram3[pal_addr_3] <= pal_mux[127:96];
end
always @(posedge de_clk) begin
pal_lookup[0] <= pal_ram0[pal_rdaddr_0];
pal_lookup[1] <= pal_ram1[pal_rdaddr_1];
pal_lookup[2] <= pal_ram2[pal_rdaddr_2];
pal_lookup[3] <= pal_ram3[pal_rdaddr_3];
end
de3d_tc_load_gen
#(.BYTES (BYTES))
u_de3d_tc_load_gen
(
// Inputs.
.de_clk (de_clk),
.tex_org (tex_org),
.tptch (tex_ptch),
.tc_op_store (tc_op_store),
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bpt (bpt_r),
.req_count (req_count),
// Outputs.
.tex_address (tex_address)
);
de3d_tc_mc_sigs u_de3d_tc_mc_sigs
(
// Inputs.
.de_clk (de_clk),
.de_rstn (de_rstn),
.ld_push_count (ld_push_count),
.push_count (push_count),
.mclock (mclock),
.tex_push_en (mc_tc_push),
.tc_op_store (tc_op_store),
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bpt (bpt_r),
.set_read (set_read),
// Outputs
.done (done),
.ram_sel (ram_sel),
.ram_addr (ram_addr)
);
/* generate address for RAMs *****************************************/
de3d_tc_mem_if_addr u0_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h0),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr0_i)
);
de3d_tc_mem_if_addr u1_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h1),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr1_i)
);
de3d_tc_mem_if_addr u2_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h2),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr2_i)
);
de3d_tc_mem_if_addr u3_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h3),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr3_i)
);
de3d_tc_mem_if_addr u4_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h4),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr4_i)
);
de3d_tc_mem_if_addr u5_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h5),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr5_i)
);
de3d_tc_mem_if_addr u6_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h6),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr6_i)
);
de3d_tc_mem_if_addr u7_de3d_tc_mem_if_addr
(
.ul_store_x (ul_store_x),
.ul_store_y (ul_store_y),
.ll_store_x (ll_store_x),
.ll_store_y (ll_store_y),
.ur_store_x (ur_store_x),
.ur_store_y (ur_store_y),
.lr_store_x (lr_store_x),
.lr_store_y (lr_store_y),
.bank (3'h7),
.bpt (bpt_r),
.tc_ready (1'b1), // tc_ready),
.set_read (set_read),
// Output.
.addr_out (adr7_i)
);
/* RAM write enable generators. ****************************************/
de3d_tc_mc_we u_de3d_tc_mc_we
(
.mclock (mclock),
.rstn (de_rstn),
.tex_push_en (mc_tc_push),
.ram_sel (ram_sel),
.ram_wen_lo (ram_wen_lo),
.ram_wen_hi (ram_wen_hi)
);
// RAM Instantiations - 256x32 RAMS
dpram_256x32 u0_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_lo),
.wraddress (ram_addr),
.data (mc_tc_data[31:0]),
.rdclock (de_clk),
.rdaddress (adr0_i),
.q (do0)
);
dpram_256x32 u1_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_lo),
.wraddress (ram_addr),
.data (mc_tc_data[63:32]),
.rdclock (de_clk),
.rdaddress (adr1_i),
.q (do1)
);
dpram_256x32 u2_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_lo),
.wraddress (ram_addr),
.data (mc_tc_data[95:64]),
.rdclock (de_clk),
.rdaddress (adr2_i),
.q (do2)
);
dpram_256x32 u3_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_lo),
.wraddress (ram_addr),
.data (mc_tc_data[127:96]),
.rdclock (de_clk),
.rdaddress (adr3_i),
.q (do3)
);
dpram_256x32 u4_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_hi),
.wraddress (ram_addr),
.data (mc_tc_data[31:0]),
.rdclock (de_clk),
.rdaddress (adr4_i),
.q (do4)
);
dpram_256x32 u5_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_hi),
.wraddress (ram_addr),
.data (mc_tc_data[63:32]),
.rdclock (de_clk),
.rdaddress (adr5_i),
.q (do5)
);
dpram_256x32 u6_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_hi),
.wraddress (ram_addr),
.data (mc_tc_data[95:64]),
.rdclock (de_clk),
.rdaddress (adr6_i),
.q (do6)
);
dpram_256x32 u7_dpram_256x32
(
.wrclock (mclock),
.wren (ram_wen_hi),
.wraddress (ram_addr),
.data (mc_tc_data[127:96]),
.rdclock (de_clk),
.rdaddress (adr7_i),
.q (do7)
);
/* Mux data to outputs ***********************************************/
de3d_tc_mem_if_out ul_de3d_tc_mem_if_out
(
.de_clk (de_clk),
.store_x (ul_store_x),
.store_y (ul_store_y),
.din0 (do0),
.din1 (do1),
.din2 (do2),
.din3 (do3),
.din4 (do4),
.din5 (do5),
.din6 (do6),
.din7 (do7),
.pal_lookup (pal_lookup[0]),
.bpt (bpt_r),
.tfmt (tfmt_r),
.pal_mode (pal_mode_r),
.exact (exact_r),
.clamp_ovd (clamp_ul_r),
.ccs_dd (ccs),
.boarder_color_dd (boarder_color),
.tex_en (tex_en),
.exact_out (exact_out),
.dout (ul_tex_i),
.pal_addr (pal_rdaddr_0)
);
de3d_tc_mem_if_out ll_de3d_tc_mem_if_out
(
.de_clk (de_clk),
.store_x (ll_store_x),
.store_y (ll_store_y),
.din0 (do0),
.din1 (do1),
.din2 (do2),
.din3 (do3),
.din4 (do4),
.din5 (do5),
.din6 (do6),
.din7 (do7),
.pal_lookup (pal_lookup[1]),
.bpt (bpt_r),
.tfmt (tfmt_r),
.pal_mode (pal_mode_r),
.exact (exact_r),
.clamp_ovd (clamp_ll_r),
.ccs_dd (ccs),
.boarder_color_dd (boarder_color),
.tex_en (tex_en),
.exact_out (),
.dout (ll_tex_i),
.pal_addr (pal_rdaddr_1)
);
de3d_tc_mem_if_out ur_de3d_tc_mem_if_out
(
.de_clk (de_clk),
.store_x (ur_store_x),
.store_y (ur_store_y),
.din0 (do0),
.din1 (do1),
.din2 (do2),
.din3 (do3),
.din4 (do4),
.din5 (do5),
.din6 (do6),
.din7 (do7),
.pal_lookup (pal_lookup[2]),
.bpt (bpt_r),
.tfmt (tfmt_r),
.pal_mode (pal_mode_r),
.exact (exact_r),
.clamp_ovd (clamp_ur_r),
.ccs_dd (ccs),
.boarder_color_dd (boarder_color),
.tex_en (tex_en),
.exact_out (),
.dout (ur_tex_i),
.pal_addr (pal_rdaddr_2)
);
de3d_tc_mem_if_out lr_de3d_tc_mem_if_out
(
.de_clk (de_clk),
.store_x (lr_store_x),
.store_y (lr_store_y),
.din0 (do0),
.din1 (do1),
.din2 (do2),
.din3 (do3),
.din4 (do4),
.din5 (do5),
.din6 (do6),
.din7 (do7),
.pal_lookup (pal_lookup[3]),
.bpt (bpt_r),
.tfmt (tfmt_r),
.pal_mode (pal_mode_r),
.exact (exact_r),
.clamp_ovd (clamp_lr_r),
.ccs_dd (ccs),
.boarder_color_dd (boarder_color),
.tex_en (tex_en),
.exact_out (),
.dout (lr_tex_i),
.pal_addr (pal_rdaddr_3)
);
afifo_32x256 u_tex_req_fifo
(
.aclr (~de_rstn),
.wrclk (de_clk),
.wrreq (tex_req),
.data (tex_address),
.rdclk (mclock),
.rdreq (mc_tc_ack),
.q (mc_tc_address),
.rdempty (tc_fifo_empty),
.wrfull (),
.wrusedw (tex_fifo_wrused)
);
assign mc_tc_req = ~tc_fifo_empty;
// Outputs based on palette or non
assign ul_tex = (exact_out) ? ul_tex_i : ul_tex_i;
assign ll_tex = (exact_out) ? ul_tex_i : ll_tex_i;
assign ur_tex = (exact_out) ? ul_tex_i : ur_tex_i;
assign lr_tex = (exact_out) ? ul_tex_i : lr_tex_i;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_add_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_add_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_63,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_63,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
inq_rnd_mode,
inq_id,
inq_fcc,
inq_add,
add_dest_rdy,
a1stg_in2_neq_in1_frac,
a1stg_in2_gt_in1_frac,
a1stg_in2_eq_in1_exp,
a1stg_expadd1,
a2stg_expadd,
a2stg_frac2hi_neq_0,
a2stg_frac2lo_neq_0,
a2stg_exp,
a3stg_fsdtoix_nx,
a3stg_fsdtoi_nx,
a2stg_frac2_63,
a4stg_exp,
add_of_out_cout,
a4stg_frac_neq_0,
a4stg_shl_data_neq_0,
a4stg_frac_dbl_nx,
a4stg_frac_sng_nx,
a1stg_expadd2,
a1stg_expadd4_inv,
a3stg_denorm,
a3stg_denorm_inv,
a4stg_denorm_inv,
a3stg_exp,
a4stg_round,
a3stg_lead0,
a4stg_rnd_frac_40,
a4stg_rnd_frac_39,
a4stg_rnd_frac_11,
a4stg_rnd_frac_10,
a4stg_frac_38_0_nx,
a4stg_frac_9_0_nx,
arst_l,
grst_l,
rclk,
add_pipe_active,
a1stg_denorm_sng_in1,
a1stg_denorm_dbl_in1,
a1stg_denorm_sng_in2,
a1stg_denorm_dbl_in2,
a1stg_norm_sng_in1,
a1stg_norm_dbl_in1,
a1stg_norm_sng_in2,
a1stg_norm_dbl_in2,
a1stg_step,
a1stg_stepa,
a1stg_sngop,
a1stg_intlngop,
a1stg_fsdtoix,
a1stg_fstod,
a1stg_fstoi,
a1stg_fstox,
a1stg_fdtoi,
a1stg_fdtox,
a1stg_faddsubs,
a1stg_faddsubd,
a1stg_fdtos,
a2stg_faddsubop,
a2stg_fsdtoix_fdtos,
a2stg_fitos,
a2stg_fitod,
a2stg_fxtos,
a2stg_fxtod,
a3stg_faddsubop,
a3stg_faddsubopa,
a4stg_dblop,
a6stg_fadd_in,
add_id_out_in,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
a6stg_fcmpop,
a6stg_step,
a3stg_sub_in,
add_sign_out,
add_cc_out,
a4stg_in_of,
add_exc_out,
a2stg_frac1_in_frac1,
a2stg_frac1_in_frac2,
a1stg_2nan_in_inv,
a1stg_faddsubop_inv,
a2stg_frac1_in_qnan,
a2stg_frac1_in_nv,
a2stg_frac1_in_nv_dbl,
a2stg_frac2_in_frac1,
a2stg_frac2_in_qnan,
a2stg_shr_cnt_in,
a2stg_shr_cnt_5_inv_in,
a2stg_shr_frac2_shr_int,
a2stg_shr_frac2_shr_dbl,
a2stg_shr_frac2_shr_sng,
a2stg_shr_frac2_max,
a2stg_sub_step,
a2stg_fracadd_frac2_inv_in,
a2stg_fracadd_frac2_inv_shr1_in,
a2stg_fracadd_frac2,
a2stg_fracadd_cin_in,
a3stg_exp_7ff,
a3stg_exp_ff,
a3stg_exp_add,
a2stg_expdec_neq_0,
a3stg_exp10_0_eq0,
a3stg_exp10_1_eq0,
a3stg_fdtos_inv,
a4stg_fixtos_fxtod_inv,
a4stg_rnd_frac_add_inv,
a4stg_shl_cnt_in,
a4stg_rnd_sng,
a4stg_rnd_dbl,
add_frac_out_rndadd,
add_frac_out_rnd_frac,
add_frac_out_shl,
a4stg_to_0,
add_exp_out_expinc,
add_exp_out_exp,
add_exp_out_exp1,
add_exp_out_expadd,
a4stg_to_0_inv,
se,
si,
so
);
parameter
FADDS= 8'h41,
FADDD= 8'h42,
FSUBS= 8'h45,
FSUBD= 8'h46,
FCMPS= 8'h51,
FCMPD= 8'h52,
FCMPES= 8'h55,
FCMPED= 8'h56,
FSTOX= 8'h81,
FDTOX= 8'h82,
FSTOI= 8'hd1,
FDTOI= 8'hd2,
FSTOD= 8'hc9,
FDTOS= 8'hc6,
FXTOS= 8'h84,
FXTOD= 8'h88,
FITOS= 8'hc4,
FITOD= 8'hc8;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_63; // request operand 1[63]
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_63; // request operand 2[63]
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input [1:0] inq_fcc; // request cc ID to op pipes
input inq_add; // add pipe request
input add_dest_rdy; // add result req accepted for CPX
input a1stg_in2_neq_in1_frac; // operand 2 fraction != oprnd 1 frac
input a1stg_in2_gt_in1_frac; // operand 2 fraction > oprnd 1 frac
input a1stg_in2_eq_in1_exp; // operand 2 exponent == oprnd 1 exp
input [11:0] a1stg_expadd1; // exponent adder 1 output- add 1 stage
input [11:0] a2stg_expadd; // exponent adder- add 2 stage
input a2stg_frac2hi_neq_0; // fraction 2[62:32]in add 2 stage != 0
input a2stg_frac2lo_neq_0; // fraction 2[31:11] in add 2 stage != 0
input [11:0] a2stg_exp; // exponent- add 2 stage
input a3stg_fsdtoix_nx; // inexact result for flt -> ints
input a3stg_fsdtoi_nx; // inexact result for flt -> 32b ints
input a2stg_frac2_63; // fraction 2 bit[63]- add 2 stage
input [11:0] a4stg_exp; // exponent- add 4 stage
input add_of_out_cout; // fraction rounding adder carry out
input a4stg_frac_neq_0; // fraction != 0- add 4 stage
input a4stg_shl_data_neq_0; // left shift result != 0- add 4 stage
input a4stg_frac_dbl_nx; // inexact double precision result
input a4stg_frac_sng_nx; // inexact single precision result
input [5:0] a1stg_expadd2; // exponent adder 2 output- add 1 stage
input [10:0] a1stg_expadd4_inv; // exponent adder 4 output- add 1 stage
input a3stg_denorm; // denorm output- add 3 stage
input a3stg_denorm_inv; // result is not a denorm- add 3 stage
input a4stg_denorm_inv; // 0 the exponent
input [10:0] a3stg_exp; // exponent- add 3 stage
input a4stg_round; // round the result- add 4 stage
input [5:0] a3stg_lead0; // leading 0's count- add 3 stage
input a4stg_rnd_frac_40; // rounded fraction[40]- add 4 stage
input a4stg_rnd_frac_39; // rounded fraction[39]- add 4 stage
input a4stg_rnd_frac_11; // rounded fraction[11]- add 4 stage
input a4stg_rnd_frac_10; // rounded fraction[10]- add 4 stage
input a4stg_frac_38_0_nx; // inexact single precision result
input a4stg_frac_9_0_nx; // inexact double precision result
input arst_l; // global asynchronous reset- asserted low
input grst_l; // global synchronous reset- asserted low
input rclk; // global clock
output add_pipe_active; // add pipe is executing a valid instr
output a1stg_denorm_sng_in1; // select line to normalized fraction 1
output a1stg_denorm_dbl_in1; // select line to normalized fraction 1
output a1stg_denorm_sng_in2; // select line to normalized fraction 2
output a1stg_denorm_dbl_in2; // select line to normalized fraction 2
output a1stg_norm_sng_in1; // select line to normalized fraction 1
output a1stg_norm_dbl_in1; // select line to normalized fraction 1
output a1stg_norm_sng_in2; // select line to normalized fraction 2
output a1stg_norm_dbl_in2; // select line to normalized fraction 2
output a1stg_step; // add pipe load
output a1stg_stepa; // add pipe load- copy
output a1stg_sngop; // single precision operation- add 1 stg
output a1stg_intlngop; // integer/long input- add 1 stage
output a1stg_fsdtoix; // float to integer convert- add 1 stg
output a1stg_fstod; // fstod- add 1 stage
output a1stg_fstoi; // fstoi- add 1 stage
output a1stg_fstox; // fstox- add 1 stage
output a1stg_fdtoi; // fdtoi- add 1 stage
output a1stg_fdtox; // fdtox- add 1 stage
output a1stg_faddsubs; // add/subtract single- add 1 stg
output a1stg_faddsubd; // add/subtract double- add 1 stg
output a1stg_fdtos; // fdtos- add 1 stage
output a2stg_faddsubop; // float add or subtract- add 2 stage
output a2stg_fsdtoix_fdtos; // float to integer convert- add 2 stg
output a2stg_fitos; // fitos- add 2 stage
output a2stg_fitod; // fitod- add 2 stage
output a2stg_fxtos; // fxtos- add 2 stage
output a2stg_fxtod; // fxtod- add 2 stage
output a3stg_faddsubop; // denorm compare lead0[10] input select
output [1:0] a3stg_faddsubopa; // denorm compare lead0[10] input select
output a4stg_dblop; // double precision operation- add 4 stg
output a6stg_fadd_in; // add pipe output request next cycle
output [9:0] add_id_out_in; // add pipe output ID next cycle
output [1:0] add_fcc_out; // add pipe input fcc passed through
output a6stg_dbl_dst; // float double result- add 6 stage
output a6stg_sng_dst; // float single result- add 6 stage
output a6stg_long_dst; // 64bit integer result- add 6 stage
output a6stg_int_dst; // 32bit integer result- add 6 stage
output a6stg_fcmpop; // compare- add 6 stage
output a6stg_step; // advance the add pipe
output a3stg_sub_in; // subtract in main adder- add 3 stage
output add_sign_out; // add sign output
output [1:0] add_cc_out; // add pipe result- condition
output a4stg_in_of; // add overflow- select exp out
output [4:0] add_exc_out; // add pipe result- exception flags
output a2stg_frac1_in_frac1; // select line to a2stg_frac1
output a2stg_frac1_in_frac2; // select line to a2stg_frac1
output a1stg_2nan_in_inv; // 2 NaN inputs- a1 stage
output a1stg_faddsubop_inv; // add/subtract- a1 stage
output a2stg_frac1_in_qnan; // make fraction 1 a QNaN
output a2stg_frac1_in_nv; // NV- make a new QNaN
output a2stg_frac1_in_nv_dbl; // NV- make a new double prec QNaN
output a2stg_frac2_in_frac1; // select line to a2stg_frac2
output a2stg_frac2_in_qnan; // make fraction 2 a QNaN
output [5:0] a2stg_shr_cnt_in; // right shift count input- add 1 stage
output a2stg_shr_cnt_5_inv_in; // right shift count input[5]- add 1 stg
output a2stg_shr_frac2_shr_int; // select line to a3stg_frac2
output a2stg_shr_frac2_shr_dbl; // select line to a3stg_frac2
output a2stg_shr_frac2_shr_sng; // select line to a3stg_frac2
output a2stg_shr_frac2_max; // select line to a3stg_frac2
output a2stg_sub_step; // select line to a3stg_frac2
output a2stg_fracadd_frac2_inv_in; // sel line to main adder input 2
output a2stg_fracadd_frac2_inv_shr1_in; // sel line to main adder in 2
output a2stg_fracadd_frac2; // select line to main adder input 2
output a2stg_fracadd_cin_in; // carry in to main adder- add 1 stage
output a3stg_exp_7ff; // select line to a3stg_exp
output a3stg_exp_ff; // select line to a3stg_exp
output a3stg_exp_add; // select line to a3stg_exp
output a2stg_expdec_neq_0; // exponent will be < 54
output a3stg_exp10_0_eq0; // exponent[10:0]==0- add 3 stage
output a3stg_exp10_1_eq0; // exponent[10:1]==0- add 3 stage
output a3stg_fdtos_inv; // double to single convert- add 3 stg
output a4stg_fixtos_fxtod_inv; // int to single/double cvt- add 4 stg
output a4stg_rnd_frac_add_inv; // select line to a4stg_rnd_frac
output [9:0] a4stg_shl_cnt_in; // postnorm shift left count- add 3 stg
output a4stg_rnd_sng; // round to single precision- add 4 stg
output a4stg_rnd_dbl; // round to double precision- add 4 stg
output add_frac_out_rndadd; // select line to add_frac_out
output add_frac_out_rnd_frac; // select line to add_frac_out
output add_frac_out_shl; // select line to add_frac_out
output a4stg_to_0; // result to max finite on overflow
output add_exp_out_expinc; // select line to add_exp_out
output add_exp_out_exp; // select line to add_exp_out
output add_exp_out_exp1; // select line to add_exp_out
output add_exp_out_expadd; // select line to add_exp_out
output a4stg_to_0_inv; // result to infinity on overflow
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire a1stg_in1_51;
wire a1stg_in1_54;
wire a1stg_in1_63;
wire a1stg_in1_50_0_neq_0;
wire a1stg_in1_53_32_neq_0;
wire a1stg_in1_exp_eq_0;
wire a1stg_in1_exp_neq_ffs;
wire a1stg_in2_51;
wire a1stg_in2_54;
wire a1stg_in2_63;
wire a1stg_in2_50_0_neq_0;
wire a1stg_in2_53_32_neq_0;
wire a1stg_in2_exp_eq_0;
wire a1stg_in2_exp_neq_ffs;
wire a1stg_denorm_sng_in1;
wire a1stg_denorm_dbl_in1;
wire a1stg_denorm_sng_in2;
wire a1stg_denorm_dbl_in2;
wire a1stg_norm_sng_in1;
wire a1stg_norm_dbl_in1;
wire a1stg_norm_sng_in2;
wire a1stg_norm_dbl_in2;
wire a1stg_snan_sng_in1;
wire a1stg_snan_dbl_in1;
wire a1stg_snan_sng_in2;
wire a1stg_snan_dbl_in2;
wire a1stg_qnan_sng_in1;
wire a1stg_qnan_dbl_in1;
wire a1stg_qnan_sng_in2;
wire a1stg_qnan_dbl_in2;
wire a1stg_snan_in1;
wire a1stg_snan_in2;
wire a1stg_qnan_in1;
wire a1stg_qnan_in2;
wire a1stg_nan_sng_in1;
wire a1stg_nan_dbl_in1;
wire a1stg_nan_sng_in2;
wire a1stg_nan_dbl_in2;
wire a1stg_nan_in1;
wire a1stg_nan_in2;
wire a1stg_nan_in;
wire a1stg_2nan_in;
wire a1stg_inf_sng_in1;
wire a1stg_inf_dbl_in1;
wire a1stg_inf_sng_in2;
wire a1stg_inf_dbl_in2;
wire a1stg_inf_in1;
wire a1stg_inf_in2;
wire a1stg_2inf_in;
wire a1stg_infnan_sng_in1;
wire a1stg_infnan_dbl_in1;
wire a1stg_infnan_sng_in2;
wire a1stg_infnan_dbl_in2;
wire a1stg_infnan_in1;
wire a1stg_infnan_in2;
wire a1stg_infnan_in;
wire a1stg_2zero_in;
wire a1stg_step;
wire a1stg_stepa;
wire [7:0] a1stg_op_in;
wire [7:0] a1stg_op;
wire a1stg_sngop;
wire [3:0] a1stg_sngopa;
wire a1stg_dblop;
wire [3:0] a1stg_dblopa;
wire [1:0] a1stg_rnd_mode;
wire [4:0] a1stg_id;
wire [1:0] a1stg_fcc;
wire a1stg_fadd;
wire a1stg_dbl_dst;
wire a1stg_sng_dst;
wire a1stg_long_dst;
wire a1stg_int_dst;
wire a1stg_intlngop;
wire a1stg_faddsubop;
wire a1stg_fsubop;
wire a1stg_fsdtox;
wire a1stg_fcmpesd;
wire a1stg_fcmpsd;
wire a1stg_faddsub_dtosop;
wire a1stg_fdtoix;
wire a1stg_fstoix;
wire a1stg_fsdtoix;
wire a1stg_fixtosd;
wire a1stg_fstod;
wire a1stg_fstoi;
wire a1stg_fstox;
wire a1stg_fdtoi;
wire a1stg_fdtox;
wire a1stg_fsdtoix_fdtos;
wire a1stg_fitos;
wire a1stg_fitod;
wire a1stg_fxtos;
wire a1stg_fcmpop;
wire a1stg_f4cycop;
wire a1stg_fixtos_fxtod;
wire a1stg_faddsubs_fdtos;
wire a1stg_faddsubs;
wire a1stg_faddsubd;
wire a1stg_fdtos;
wire a1stg_fistod;
wire a1stg_fixtos;
wire a1stg_fxtod;
wire a1stg_opdec_36;
wire [34:28] a1stg_opdec;
wire [3:0] a1stg_opdec_24_21;
wire [8:0] a1stg_opdec_19_11;
wire [9:0] a1stg_opdec_9_0;
wire fixtosd_hold;
wire [30:0] a2stg_opdec_in;
wire a2stg_opdec_36;
wire [34:28] a2stg_opdec;
wire [3:0] a2stg_opdec_24_21;
wire [8:0] a2stg_opdec_19_11;
wire [9:0] a2stg_opdec_9_0;
wire [1:0] a2stg_rnd_mode;
wire [4:0] a2stg_id;
wire [1:0] a2stg_fcc;
wire a2stg_fadd;
wire a2stg_long_dst;
wire a2stg_faddsubop;
wire a2stg_fsubop;
wire a2stg_faddsub_dtosop;
wire a2stg_fdtoix;
wire a2stg_fstoix;
wire a2stg_fsdtoix;
wire a2stg_fstod;
wire a2stg_fstoi;
wire a2stg_fstox;
wire a2stg_fdtoi;
wire a2stg_fdtox;
wire a2stg_fsdtoix_fdtos;
wire a2stg_fitos;
wire a2stg_fitod;
wire a2stg_fxtos;
wire a2stg_fcmpop;
wire a2stg_fixtos_fxtod;
wire a2stg_fdtos;
wire a2stg_fxtod;
wire a3stg_opdec_36;
wire [34:29] a3stg_opdec;
wire a3stg_opdec_24;
wire a3stg_opdec_21;
wire [9:0] a3stg_opdec_9_0;
wire [1:0] a3stg_rnd_mode;
wire [4:0] a3stg_id;
wire [1:0] a3stg_fcc;
wire a3stg_fadd;
wire a3stg_int_dst;
wire a3stg_faddsubop;
wire [1:0] a3stg_faddsubopa;
wire a3stg_fsdtoix;
wire a3stg_f4cycop;
wire a3stg_fixtos_fxtod;
wire a3stg_fdtos;
wire a4stg_opdec_36;
wire [34:29] a4stg_opdec;
wire a4stg_opdec_24;
wire a4stg_opdec_21;
wire a4stg_opdec_9;
wire [7:0] a4stg_opdec_7_0;
wire [1:0] a4stg_rnd_mode_in;
wire [1:0] a4stg_rnd_mode;
wire [1:0] a4stg_rnd_mode2;
wire [9:0] a4stg_id_in;
wire [9:0] a4stg_id;
wire [1:0] a4stg_fcc;
wire a4stg_dblop;
wire a4stg_fadd;
wire a4stg_faddsubop;
wire a4stg_faddsub_dtosop;
wire a4stg_fsdtoix;
wire a4stg_fcmpop;
wire a4stg_fixtos_fxtod;
wire a4stg_faddsubs_fdtos;
wire a4stg_faddsubs;
wire a4stg_faddsubd;
wire a4stg_fdtos;
wire a4stg_fistod;
wire [34:30] a5stg_opdec;
wire a5stg_opdec_9;
wire a5stg_opdec_7;
wire a5stg_opdec_1;
wire a5stg_opdec_0;
wire [9:0] a5stg_id;
wire a5stg_fadd;
wire a5stg_fixtos_fxtod;
wire a5stg_fixtos;
wire a5stg_fxtod;
wire [34:30] a6stg_opdec_in;
wire a6stg_opdec_in_9;
wire a6stg_fadd_in;
wire [34:30] a6stg_opdec;
wire a6stg_opdec_9;
wire [9:0] add_id_out_in;
wire [9:0] add_id_out;
wire [1:0] add_fcc_out_in;
wire [1:0] add_fcc_out;
wire a6stg_fadd;
wire a6stg_dbl_dst;
wire a6stg_sng_dst;
wire a6stg_long_dst;
wire a6stg_int_dst;
wire a6stg_fcmpop;
wire a6stg_hold;
wire a6stg_step;
wire a1stg_sub;
wire a2stg_sign1;
wire a2stg_sign2;
wire a2stg_sub;
wire a2stg_in2_neq_in1_frac;
wire a2stg_in2_gt_in1_frac;
wire a2stg_in2_eq_in1_exp;
wire a2stg_in2_gt_in1_exp;
wire a2stg_nan_in;
wire a2stg_nan_in2;
wire a2stg_snan_in2;
wire a2stg_qnan_in2;
wire a2stg_snan_in1;
wire a2stg_qnan_in1;
wire a2stg_2zero_in;
wire a2stg_2inf_in;
wire a2stg_in2_eq_in1;
wire a2stg_in2_gt_in1;
wire a3stg_sub_in;
wire a2stg_faddsub_sign;
wire a3stg_sign_in;
wire a3stg_sign;
wire a2stg_cc_1;
wire a2stg_cc_0;
wire [1:0] a2stg_cc;
wire [1:0] a3stg_cc;
wire a4stg_sign_in;
wire a4stg_sign;
wire a4stg_sign2;
wire [1:0] a4stg_cc;
wire add_sign_out;
wire [1:0] add_cc_out_in;
wire [1:0] add_cc_out;
wire a1stg_nv;
wire a2stg_nv;
wire a1stg_of_mask;
wire a2stg_of_mask;
wire a3stg_nv_in;
wire a3stg_nv;
wire a3stg_of_mask;
wire a2stg_nx_tmp1;
wire a2stg_nx_tmp2;
wire a2stg_nx_tmp3;
wire a3stg_a2_expadd_11;
wire a3stg_nx_tmp1;
wire a3stg_nx_tmp2;
wire a3stg_nx_tmp3;
wire a3stg_nx;
wire a4stg_nv_in;
wire a4stg_nv;
wire a4stg_nv2;
wire a4stg_of_mask_in;
wire a4stg_of_mask;
wire a4stg_of_mask2;
wire a4stg_nx_in;
wire a4stg_nx;
wire a4stg_nx2;
wire add_nv_out;
wire a4stg_in_of;
wire add_of_out_tmp1_in;
wire add_of_out_tmp1;
wire add_of_out_tmp2;
wire add_of_out;
wire a4stg_uf;
wire add_uf_out;
wire add_nx_out_in;
wire add_nx_out;
wire [4:0] add_exc_out;
wire a2stg_frac1_in_frac1;
wire a2stg_frac1_in_frac2;
wire a1stg_2nan_in_inv;
wire a1stg_faddsubop_inv;
wire a2stg_frac1_in_qnan;
wire a2stg_frac1_in_nv;
wire a2stg_frac1_in_nv_dbl;
wire a2stg_frac2_in_frac1;
wire a2stg_frac2_in_qnan;
wire a1stg_exp_diff_add1;
wire a1stg_exp_diff_add2;
wire a1stg_exp_diff_5;
wire [10:0] a1stg_exp_diff;
wire [5:0] a1stg_clamp63;
wire [5:0] a2stg_shr_cnt_in;
wire a2stg_shr_cnt_5_inv_in;
wire a2stg_shr_frac2_shr_int;
wire a2stg_shr_frac2_shr_dbl;
wire a2stg_shr_frac2_shr_sng;
wire a2stg_shr_frac2_max;
wire a2stg_sub_step;
wire a1stg_faddsub_clamp63_0;
wire a2stg_fracadd_frac2_inv_in;
wire a2stg_fracadd_frac2_inv_shr1_in;
wire a2stg_fracadd_frac2_in;
wire a2stg_fracadd_frac2;
wire a2stg_fracadd_cin_in;
wire a3stg_exp_7ff;
wire a3stg_exp_ff;
wire a3stg_exp_add;
wire a2stg_expdec_neq_0;
wire a3stg_exp10_0_eq0;
wire a3stg_exp10_1_eq0;
wire a3stg_fdtos_inv;
wire a4stg_fixtos_fxtod_inv;
wire a4stg_rnd_frac_add_inv;
wire [9:0] a4stg_shl_cnt_in;
wire a4stg_rnd_sng;
wire a4stg_rnd_dbl;
wire a4stg_rndup_sng;
wire a4stg_rndup_dbl;
wire a4stg_rndup;
wire a5stg_rndup;
wire add_frac_out_rndadd;
wire add_frac_out_rnd_frac;
wire add_frac_out_shl;
wire a4stg_to_0;
wire add_exp_out_expinc;
wire add_exp_out_exp;
wire add_exp_out_exp1;
wire add_exp_out_expadd;
wire a4stg_to_0_inv;
wire add_pipe_active_in;
wire add_pipe_active;
dffrl_async #(1) dffrl_add_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (add_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!add_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_a1stg_in1_51 (
.din (inq_in1_51),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_54 (
.din (inq_in1_54),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_63 (
.din (inq_in1_63),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_63),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_51 (
.din (inq_in2_51),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_54 (
.din (inq_in2_54),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_63 (
.din (inq_in2_63),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_63),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_denorm_sng_in1= a1stg_in1_exp_eq_0 && a1stg_sngopa[0];
assign a1stg_denorm_dbl_in1= a1stg_in1_exp_eq_0 && a1stg_dblopa[0];
assign a1stg_denorm_sng_in2= a1stg_in2_exp_eq_0 && a1stg_sngopa[0];
assign a1stg_denorm_dbl_in2= a1stg_in2_exp_eq_0 && a1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_norm_sng_in1= (!a1stg_in1_exp_eq_0) && a1stg_sngopa[0];
assign a1stg_norm_dbl_in1= (!a1stg_in1_exp_eq_0) && a1stg_dblopa[0];
assign a1stg_norm_sng_in2= (!a1stg_in2_exp_eq_0) && a1stg_sngopa[0];
assign a1stg_norm_dbl_in2= (!a1stg_in2_exp_eq_0) && a1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Nan add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_snan_sng_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_54)
&& a1stg_in1_53_32_neq_0 && a1stg_sngopa[1];
assign a1stg_snan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_51)
&& a1stg_in1_50_0_neq_0 && a1stg_dblopa[1];
assign a1stg_snan_sng_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_54)
&& a1stg_in2_53_32_neq_0 && a1stg_sngopa[1];
assign a1stg_snan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_51)
&& a1stg_in2_50_0_neq_0 && a1stg_dblopa[1];
assign a1stg_qnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_54
&& a1stg_sngopa[1];
assign a1stg_qnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_51
&& a1stg_dblopa[1];
assign a1stg_qnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_54
&& a1stg_sngopa[1];
assign a1stg_qnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_51
&& a1stg_dblopa[1];
assign a1stg_snan_in1= a1stg_snan_sng_in1 || a1stg_snan_dbl_in1;
assign a1stg_snan_in2= a1stg_snan_sng_in2 || a1stg_snan_dbl_in2;
assign a1stg_qnan_in1= a1stg_qnan_sng_in1 || a1stg_qnan_dbl_in1;
assign a1stg_qnan_in2= a1stg_qnan_sng_in2 || a1stg_qnan_dbl_in2;
assign a1stg_nan_sng_in1= (!a1stg_in1_exp_neq_ffs)
&& (a1stg_in1_54 || a1stg_in1_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_nan_dbl_in1= (!a1stg_in1_exp_neq_ffs)
&& (a1stg_in1_51 || a1stg_in1_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_nan_sng_in2= (!a1stg_in2_exp_neq_ffs)
&& (a1stg_in2_54 || a1stg_in2_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_nan_dbl_in2= (!a1stg_in2_exp_neq_ffs)
&& (a1stg_in2_51 || a1stg_in2_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_nan_in1= a1stg_nan_sng_in1 || a1stg_nan_dbl_in1;
assign a1stg_nan_in2= a1stg_nan_sng_in2 || a1stg_nan_dbl_in2;
assign a1stg_nan_in= a1stg_nan_in1 || a1stg_nan_in2;
assign a1stg_2nan_in= a1stg_nan_in1 && a1stg_nan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Infinity add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_inf_sng_in1= (!a1stg_in1_exp_neq_ffs)
&& (!a1stg_in1_54) && (!a1stg_in1_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_inf_dbl_in1= (!a1stg_in1_exp_neq_ffs)
&& (!a1stg_in1_51) && (!a1stg_in1_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_inf_sng_in2= (!a1stg_in2_exp_neq_ffs)
&& (!a1stg_in2_54) && (!a1stg_in2_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_inf_dbl_in2= (!a1stg_in2_exp_neq_ffs)
&& (!a1stg_in2_51) && (!a1stg_in2_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_inf_in1= a1stg_inf_sng_in1 || a1stg_inf_dbl_in1;
assign a1stg_inf_in2= a1stg_inf_sng_in2 || a1stg_inf_dbl_in2;
assign a1stg_2inf_in= a1stg_inf_in1 && a1stg_inf_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_infnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_sngopa[3];
assign a1stg_infnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_dblopa[3];
assign a1stg_infnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_sngopa[3];
assign a1stg_infnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_dblopa[3];
assign a1stg_infnan_in1= a1stg_infnan_sng_in1 || a1stg_infnan_dbl_in1;
assign a1stg_infnan_in2= a1stg_infnan_sng_in2 || a1stg_infnan_dbl_in2;
assign a1stg_infnan_in= a1stg_infnan_in1 || a1stg_infnan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Zero inputs.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// correctly detect case where both single precision operands are zero
// assign a1stg_2zero_in= a1stg_in1_exp_eq_0 && (!a1stg_in1_51)
// && (!a1stg_in1_50_0_neq_0)
// && a1stg_in2_exp_eq_0 && (!a1stg_in2_51)
// && (!a1stg_in2_50_0_neq_0);
assign a1stg_2zero_in =
a1stg_in1_exp_eq_0 &&
(!a1stg_in1_54 || a1stg_dblopa[3]) && // (!bit54 ) || dp
(!a1stg_in1_53_32_neq_0 || a1stg_dblopa[3]) && // (!bit53 && !bit52) || dp
(!a1stg_in1_51) &&
(!a1stg_in1_50_0_neq_0) &&
a1stg_in2_exp_eq_0 &&
(!a1stg_in2_54 || a1stg_dblopa[3]) && // (!bit54 ) || dp
(!a1stg_in2_53_32_neq_0 || a1stg_dblopa[3]) && // (!bit53 && !bit52) || dp
(!a1stg_in2_51) &&
(!a1stg_in2_50_0_neq_0);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point add control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add input stage.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_step= (!fixtosd_hold) && (!a6stg_hold);
assign a1stg_stepa= a1stg_step;
assign a1stg_op_in[7:0]= ({8{inq_add}}
& inq_op[7:0]);
dffre_s #(8) i_a1stg_op (
.din (a1stg_op_in[7:0]),
.en (a1stg_step),
.rst (reset),
.clk (rclk),
.q (a1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_sngop (
.din (inq_op[0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_sngop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_a1stg_sngopa (
.din ({4{inq_op[0]}}),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_sngopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a1stg_dblop (
.din (inq_op[1]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_a1stg_dblopa (
.din ({4{inq_op[1]}}),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_dblopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_a1stg_id (
.din (inq_id[4:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a1stg_fcc (
.din (inq_fcc[1:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_fadd= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED)
|| (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
|| (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
|| (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD)
|| (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
|| (a1stg_op[7:0]==FSTOD) || (a1stg_op[7:0]==FDTOS);
assign a1stg_dbl_dst= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FXTOD)
|| (a1stg_op[7:0]==FSTOD);
assign a1stg_sng_dst= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
|| (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_long_dst= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
assign a1stg_int_dst= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FDTOI);
assign a1stg_intlngop= (!(a1stg_sngopa[3] || a1stg_dblop));
assign a1stg_faddsubop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fsubop= (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fsdtox= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fcmpesd= (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
assign a1stg_fcmpsd= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD);
assign a1stg_faddsub_dtosop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_fdtoix= (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fstoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX);
assign a1stg_fsdtoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fixtosd= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
|| (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD);
assign a1stg_fstod= (a1stg_op[7:0]==FSTOD);
assign a1stg_fstoi= (a1stg_op[7:0]==FSTOI);
assign a1stg_fstox= (a1stg_op[7:0]==FSTOX);
assign a1stg_fdtoi= (a1stg_op[7:0]==FDTOI);
assign a1stg_fdtox= (a1stg_op[7:0]==FDTOX);
assign a1stg_fsdtoix_fdtos= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_fitos= (a1stg_op[7:0]==FITOS);
assign a1stg_fitod= (a1stg_op[7:0]==FITOD);
assign a1stg_fxtos= (a1stg_op[7:0]==FXTOS);
assign a1stg_fcmpop= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
|| (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
assign a1stg_f4cycop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FDTOS) || (a1stg_op[7:0]==FSTOD)
|| (a1stg_op[7:0]==FITOD);
assign a1stg_fixtos_fxtod= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
|| (a1stg_op[7:0]==FXTOD);
assign a1stg_faddsubs_fdtos= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_faddsubs= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS);
assign a1stg_faddsubd= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fdtos= (a1stg_op[7:0]==FDTOS);
assign a1stg_fistod= (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FSTOD);
assign a1stg_fixtos= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS);
assign a1stg_fxtod= (a1stg_op[7:0]==FXTOD);
assign a1stg_opdec_36 = a1stg_dblop;
assign a1stg_opdec[34:28] =
{a1stg_fadd,
a1stg_dbl_dst,
a1stg_sng_dst,
a1stg_long_dst,
a1stg_int_dst,
a1stg_faddsubop,
a1stg_fsubop};
assign a1stg_opdec_24_21[3:0] =
{a1stg_faddsub_dtosop,
a1stg_fdtoix,
a1stg_fstoix,
a1stg_fsdtoix};
assign a1stg_opdec_19_11[8:0] =
{a1stg_fstod,
a1stg_fstoi,
a1stg_fstox,
a1stg_fdtoi,
a1stg_fdtox,
a1stg_fsdtoix_fdtos,
a1stg_fitos,
a1stg_fitod,
a1stg_fxtos};
assign a1stg_opdec_9_0[9:0] =
{a1stg_fcmpop,
a1stg_f4cycop,
a1stg_fixtos_fxtod,
a1stg_faddsubs_fdtos,
a1stg_faddsubs,
a1stg_faddsubd,
a1stg_fdtos,
a1stg_fistod,
a1stg_fixtos,
a1stg_fxtod};
assign fixtosd_hold= a2stg_fixtos_fxtod
&& (!(a1stg_op[7] && (!a1stg_op[1]) && (!a1stg_op[0])
&& (a1stg_op[2] || (!a1stg_op[6]))));
assign a2stg_opdec_in[30:0]= {31{(!fixtosd_hold)}}
& {a1stg_opdec_36, a1stg_opdec[34:28],
a1stg_opdec_24_21[3:0], a1stg_opdec_19_11[8:0],
a1stg_opdec_9_0[9:0]};
dffre_s #(31) i_a2stg_opdec (
.din (a2stg_opdec_in[30:0]),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a2stg_opdec_36, a2stg_opdec[34:28], a2stg_opdec_24_21[3:0],
a2stg_opdec_19_11[8:0], a2stg_opdec_9_0[9:0]}),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a2stg_rnd_mode (
.din (a1stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_a2stg_id (
.din (a1stg_id[4:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a2stg_fcc (
.din (a1stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_fadd= a2stg_opdec[34];
assign a2stg_long_dst= a2stg_opdec[31];
assign a2stg_faddsubop= a2stg_opdec[29];
assign a2stg_fsubop= a2stg_opdec[28];
assign a2stg_faddsub_dtosop= a2stg_opdec_24_21[3];
assign a2stg_fdtoix= a2stg_opdec_24_21[2];
assign a2stg_fstoix= a2stg_opdec_24_21[1];
assign a2stg_fsdtoix= a2stg_opdec_24_21[0];
assign a2stg_fstod= a2stg_opdec_19_11[8];
assign a2stg_fstoi= a2stg_opdec_19_11[7];
assign a2stg_fstox= a2stg_opdec_19_11[6];
assign a2stg_fdtoi= a2stg_opdec_19_11[5];
assign a2stg_fdtox= a2stg_opdec_19_11[4];
assign a2stg_fsdtoix_fdtos= a2stg_opdec_19_11[3];
assign a2stg_fitos= a2stg_opdec_19_11[2];
assign a2stg_fitod= a2stg_opdec_19_11[1];
assign a2stg_fxtos= a2stg_opdec_19_11[0];
assign a2stg_fcmpop= a2stg_opdec_9_0[9];
assign a2stg_fixtos_fxtod= a2stg_opdec_9_0[7];
assign a2stg_fdtos= a2stg_opdec_9_0[3];
assign a2stg_fxtod= a2stg_opdec_9_0[0];
dffre_s #(19) i_a3stg_opdec (
.din ({a2stg_opdec_36, a2stg_opdec[34:29], a2stg_opdec_24_21[3],
a2stg_opdec_24_21[0], a2stg_opdec_9_0[9:0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
a3stg_opdec_21, a3stg_opdec_9_0[9:0]}),
.se (se),
.si (),
.so ()
);
dffre_s #(2) i_a3stg_faddsubopa (
.din ({2{a2stg_faddsubop}}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q (a3stg_faddsubopa[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a3stg_rnd_mode (
.din (a2stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_a3stg_id (
.din (a2stg_id[4:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a3stg_fcc (
.din (a2stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_fadd= a3stg_opdec[34];
assign a3stg_int_dst= a3stg_opdec[30];
assign a3stg_faddsubop= a3stg_opdec[29];
assign a3stg_fsdtoix= a3stg_opdec_21;
assign a3stg_f4cycop= a3stg_opdec_9_0[8];
assign a3stg_fixtos_fxtod= a3stg_opdec_9_0[7];
assign a3stg_fdtos= a3stg_opdec_9_0[3];
dffre_s #(18) i_a4stg_opdec (
.din ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
a3stg_opdec_21, a3stg_opdec_9_0[9], a3stg_opdec_9_0[7:0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a4stg_opdec_36, a4stg_opdec[34:29], a4stg_opdec_24,
a4stg_opdec_21, a4stg_opdec_9, a4stg_opdec_7_0[7:0]}),
.se (se),
.si (),
.so ()
);
assign a4stg_rnd_mode_in[1:0]= ({2{a3stg_f4cycop}}
& a3stg_rnd_mode[1:0])
| ({2{(!a3stg_f4cycop)}}
& a4stg_rnd_mode2[1:0]);
dffe_s #(2) i_a4stg_rnd_mode (
.din (a4stg_rnd_mode_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a4stg_rnd_mode2 (
.din (a3stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_rnd_mode2[1:0]),
.se (se),
.si (),
.so ()
);
assign a4stg_id_in[9:0]= {(a3stg_id[4:2]==3'o7),
(a3stg_id[4:2]==3'o6),
(a3stg_id[4:2]==3'o5),
(a3stg_id[4:2]==3'o4),
(a3stg_id[4:2]==3'o3),
(a3stg_id[4:2]==3'o2),
(a3stg_id[4:2]==3'o1),
(a3stg_id[4:2]==3'o0),
a3stg_id[1:0]};
dffe_s #(10) i_a4stg_id (
.din (a4stg_id_in[9:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_id[9:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a4stg_fcc (
.din (a3stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stages 4 and 5.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_dblop= a4stg_opdec_36;
assign a4stg_fadd= a4stg_opdec[34];
assign a4stg_faddsubop= a4stg_opdec[29];
assign a4stg_faddsub_dtosop= a4stg_opdec_24;
assign a4stg_fsdtoix= a4stg_opdec_21;
assign a4stg_fcmpop= a4stg_opdec_9;
assign a4stg_fixtos_fxtod= a4stg_opdec_7_0[7];
assign a4stg_faddsubs_fdtos= a4stg_opdec_7_0[6];
assign a4stg_faddsubs= a4stg_opdec_7_0[5];
assign a4stg_faddsubd= a4stg_opdec_7_0[4];
assign a4stg_fdtos= a4stg_opdec_7_0[3];
assign a4stg_fistod= a4stg_opdec_7_0[2];
dffre_s #(9) i_a5stg_opdec (
.din ({a4stg_opdec[34:30], a4stg_opdec_9, a4stg_opdec_7_0[7],
a4stg_opdec_7_0[1], a4stg_opdec_7_0[0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a5stg_opdec[34:30], a5stg_opdec_9, a5stg_opdec_7,
a5stg_opdec_1, a5stg_opdec_0}),
.se (se),
.si (),
.so ()
);
dffe_s #(10) i_a5stg_id (
.din (a4stg_id[9:0]),
.en (a6stg_step),
.clk (rclk),
.q (a5stg_id[9:0]),
.se (se),
.si (),
.so ()
);
assign a5stg_fadd= a5stg_opdec[34];
assign a5stg_fixtos_fxtod= a5stg_opdec_7;
assign a5stg_fixtos= a5stg_opdec_1;
assign a5stg_fxtod= a5stg_opdec_0;
assign a6stg_opdec_in[34:30] = ({5{a5stg_fixtos_fxtod}}
& a5stg_opdec[34:30])
| ({5{((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))}}
& a4stg_opdec[34:30]);
assign a6stg_opdec_in_9 = (a5stg_fixtos_fxtod
& a5stg_opdec_9)
| (((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))
& a4stg_opdec_9);
assign a6stg_fadd_in= (a5stg_fixtos_fxtod && a6stg_step && (!reset)
&& a5stg_fadd)
|| ((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod)
&& a6stg_step && (!reset) && a4stg_fadd)
|| ((!a6stg_step) && (!reset) && a6stg_fadd);
dffre_s #(6) i_a6stg_opdec (
.din ({a6stg_opdec_in[34:30], a6stg_opdec_in_9}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a6stg_opdec[34:30], a6stg_opdec_9}),
.se (se),
.si (),
.so ()
);
assign add_id_out_in[9:0]= ({10{((!a5stg_fixtos_fxtod) && a6stg_step)}}
& a4stg_id[9:0])
| ({10{(a5stg_fixtos_fxtod && a6stg_step)}}
& a5stg_id[9:0])
| ({10{(!a6stg_step)}}
& add_id_out[9:0]);
dff_s #(10) i_add_id_out (
.din (add_id_out_in[9:0]),
.clk (rclk),
.q (add_id_out[9:0]),
.se (se),
.si (),
.so ()
);
assign add_fcc_out_in[1:0]= ({2{a4stg_fcmpop}}
& a4stg_fcc);
dffe_s #(2) i_add_fcc_out (
.din (add_fcc_out_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (add_fcc_out[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign a6stg_fadd= a6stg_opdec[34];
assign a6stg_dbl_dst= a6stg_opdec[33];
assign a6stg_sng_dst= a6stg_opdec[32];
assign a6stg_long_dst= a6stg_opdec[31];
assign a6stg_int_dst= a6stg_opdec[30];
assign a6stg_fcmpop= a6stg_opdec_9;
assign a6stg_hold= a6stg_fadd && (!add_dest_rdy);
assign a6stg_step= (!a6stg_hold);
// Austin update
// Power management update
assign add_pipe_active_in = // add pipe is executing a valid instr
a1stg_fadd || a2stg_fadd || a3stg_fadd || a4stg_fadd || a5stg_fadd || a6stg_fadd;
dffre_s #(1) i_add_pipe_active (
.din (add_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (add_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign and exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_sub= (a1stg_fsubop ^ (a1stg_in1_63 ^ a1stg_in2_63))
&& (!a1stg_fdtos)
&& (!(a1stg_faddsubop && a1stg_nan_in));
dffe_s #(1) i_a2stg_sign1 (
.din (a1stg_in1_63),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sign1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_sign2 (
.din (a1stg_in2_63),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sign2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_sub (
.din (a1stg_sub),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sub),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_in2_neq_in1_frac (
.din (a1stg_in2_neq_in1_frac),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_neq_in1_frac),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_in2_gt_in1_frac (
.din (a1stg_in2_gt_in1_frac),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_gt_in1_frac),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_in2_eq_in1_exp (
.din (a1stg_in2_eq_in1_exp),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_eq_in1_exp),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_in2_gt_in1_exp (
.din (a1stg_expadd1[11]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_gt_in1_exp),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_nan_in (
.din (a1stg_nan_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nan_in),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_nan_in2 (
.din (a1stg_nan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nan_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_snan_in2 (
.din (a1stg_snan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_qnan_in2 (
.din (a1stg_qnan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_snan_in1 (
.din (a1stg_snan_in1),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_qnan_in1 (
.din (a1stg_qnan_in1),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_2zero_in (
.din (a1stg_2zero_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_2zero_in),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a2stg_2inf_in (
.din (a1stg_2inf_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_2inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_in2_eq_in1= a2stg_in2_eq_in1_exp && (!a2stg_in2_neq_in1_frac);
assign a2stg_in2_gt_in1= a2stg_in2_gt_in1_exp
|| (a2stg_in2_eq_in1_exp && a2stg_in2_neq_in1_frac
&& a2stg_in2_gt_in1_frac);
assign a3stg_sub_in= a2stg_sub
&& (!a2stg_nan_in)
&& (!(a2stg_fsdtoix && (!a2stg_expadd[11])));
assign a2stg_faddsub_sign= (a2stg_sign1
&& (!a2stg_nan_in)
&& (a2stg_sign2 ^ a2stg_fsubop)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| (a2stg_sign1
&& (!a2stg_nan_in)
&& (!a2stg_in2_eq_in1)
&& (!a2stg_in2_gt_in1)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| ((!a2stg_in2_eq_in1)
&& a2stg_in2_gt_in1
&& (!a2stg_nan_in)
&& (a2stg_sign2 ^ a2stg_fsubop)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| (a2stg_sign2
&& (a2stg_snan_in2
|| (a2stg_qnan_in2 && (!a2stg_snan_in1))))
|| (a2stg_sign1
&& ((a2stg_snan_in1 && (!a2stg_snan_in2))
|| (a2stg_qnan_in1 && (!a2stg_nan_in2))))
|| ((a2stg_rnd_mode[1:0]==2'b11)
&& a2stg_in2_eq_in1
&& (a2stg_sign1 ^ (a2stg_sign2 ^ a2stg_fsubop))
&& (!a2stg_nan_in)
&& (!a2stg_2inf_in));
assign a3stg_sign_in= (a2stg_faddsubop && a2stg_faddsub_sign)
|| ((!a2stg_faddsubop) && a2stg_sign2);
dffe_s #(1) i_a3stg_sign (
.din (a3stg_sign_in),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_sign),
.se (se),
.si (),
.so ()
);
assign a2stg_cc_1= ((a2stg_sign2 && (!a2stg_2zero_in) && a2stg_sub)
|| ((!a2stg_in2_eq_in1) && (!a2stg_sub)
&& (a2stg_in2_gt_in1 ^ (!a2stg_sign2)))
|| a2stg_nan_in)
&& a2stg_fcmpop;
assign a2stg_cc_0= (((!a2stg_sign2) && (!a2stg_2zero_in) && a2stg_sub)
|| ((!a2stg_in2_eq_in1) && (!a2stg_sub)
&& (a2stg_in2_gt_in1 ^ a2stg_sign2))
|| a2stg_nan_in)
&& a2stg_fcmpop;
assign a2stg_cc[1:0]= {a2stg_cc_1, a2stg_cc_0};
dffe_s #(2) i_a3stg_cc (
.din (a2stg_cc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_cc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_sign_in= (a3stg_f4cycop && a3stg_sign)
|| ((!a3stg_f4cycop) && a4stg_sign2);
dffe_s #(1) i_a4stg_sign (
.din (a4stg_sign_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a4stg_sign2 (
.din (a3stg_sign),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_sign2),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_a4stg_cc (
.din (a3stg_cc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_cc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_add_sign_out (
.din (a4stg_sign),
.en (a6stg_step),
.clk (rclk),
.q (add_sign_out),
.se (se),
.si (),
.so ()
);
assign add_cc_out_in[1:0]= ({2{a4stg_fcmpop}}
& a4stg_cc[1:0]);
dffe_s #(2) i_add_cc_out (
.din (add_cc_out_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (add_cc_out[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_nv= (a1stg_faddsubop
&& ((a1stg_2inf_in && a1stg_sub)
|| a1stg_snan_in1
|| a1stg_snan_in2))
|| (a1stg_fstod && a1stg_snan_in2)
|| (a1stg_fdtos && a1stg_snan_in2)
|| (a1stg_fcmpesd && a1stg_nan_in)
|| (a1stg_fcmpsd
&& (a1stg_snan_in1 || a1stg_snan_in2));
dffe_s #(1) i_a2stg_nv (
.din (a1stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nv),
.se (se),
.si (),
.so ()
);
assign a1stg_of_mask= (!(a1stg_faddsub_dtosop && a1stg_infnan_in));
dffe_s #(1) i_a2stg_of_mask (
.din (a1stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_nv_in= ((!a2stg_expadd[11])
&& a2stg_fsdtoix
&& ((!a2stg_sign2)
|| (|a2stg_expadd[10:0])
|| a2stg_frac2hi_neq_0
|| (a2stg_long_dst && a2stg_frac2lo_neq_0)))
|| a2stg_nv;
dffe_s #(1) i_a3stg_nv (
.din (a3stg_nv_in),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a3stg_of_mask (
.din (a2stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_of_mask),
.se (se),
.si (),
.so ()
);
assign a2stg_nx_tmp1= (a2stg_fdtoix && (|a2stg_exp[11:10]))
|| (a2stg_fstoix && (|a2stg_exp[11:7]));
assign a2stg_nx_tmp2= ((a2stg_fdtoix && (!(|a2stg_exp[11:10])))
|| (a2stg_fstoix && (!(|a2stg_exp[11:7]))))
&& ((|a2stg_exp[10:1])
|| a2stg_frac2hi_neq_0
|| a2stg_frac2lo_neq_0
|| a2stg_frac2_63);
assign a2stg_nx_tmp3= (a2stg_exp[11:0]==12'h41f)
&& a2stg_sign2
&& (!a2stg_frac2hi_neq_0)
&& a2stg_frac2lo_neq_0
&& a2stg_fdtoi;
dffe_s #(1) i_a3stg_a2_expadd_11 (
.din (a2stg_expadd[11]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_a2_expadd_11),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a3stg_nx_tmp1 (
.din (a2stg_nx_tmp1),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a3stg_nx_tmp2 (
.din (a2stg_nx_tmp2),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a3stg_nx_tmp3 (
.din (a2stg_nx_tmp3),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp3),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_nx= (a3stg_a2_expadd_11
&& ((a3stg_nx_tmp1
&& ((a3stg_fsdtoi_nx && a3stg_int_dst)
|| a3stg_fsdtoix_nx))
|| a3stg_nx_tmp2))
|| a3stg_nx_tmp3;
assign a4stg_nv_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_nv)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_nv2);
dffe_s #(1) i_a4stg_nv (
.din (a4stg_nv_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a4stg_nv2 (
.din (a3stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nv2),
.se (se),
.si (),
.so ()
);
assign a4stg_of_mask_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_of_mask)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_of_mask2);
dffe_s #(1) i_a4stg_of_mask (
.din (a4stg_of_mask_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_of_mask),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a4stg_of_mask2 (
.din (a3stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_of_mask2),
.se (se),
.si (),
.so ()
);
assign a4stg_nx_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_nx)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_nx2);
dffe_s #(1) i_a4stg_nx (
.din (a4stg_nx_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nx),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_a4stg_nx2 (
.din (a3stg_nx),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nx2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_add_nv_out (
.din (a4stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (add_nv_out),
.se (se),
.si (),
.so ()
);
assign a4stg_in_of= ((a4stg_exp[11] || (&a4stg_exp[10:0]))
&& a4stg_faddsubd
&& a4stg_of_mask)
|| (((|a4stg_exp[11:8]) || (&a4stg_exp[7:0]))
&& a4stg_faddsubs_fdtos
&& a4stg_of_mask);
assign add_of_out_tmp1_in= ((&a4stg_exp[10:1]) && a4stg_rndup && a4stg_round
&& a4stg_faddsubd
&& a4stg_of_mask)
|| ((&a4stg_exp[7:1]) && a4stg_rndup
&& (a4stg_round || a4stg_fdtos)
&& a4stg_faddsubs_fdtos
&& a4stg_of_mask);
dffe_s #(1) i_add_of_out_tmp1 (
.din (add_of_out_tmp1_in),
.en (a6stg_step),
.clk (rclk),
.q (add_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_add_of_out_tmp2 (
.din (a4stg_in_of),
.en (a6stg_step),
.clk (rclk),
.q (add_of_out_tmp2),
.se (se),
.si (),
.so ()
);
assign add_of_out= add_of_out_tmp2
|| (add_of_out_tmp1 && add_of_out_cout);
assign a4stg_uf= ((!(|a4stg_exp[10:0]))
&& a4stg_frac_neq_0
&& (a4stg_round || a4stg_fdtos)
&& a4stg_faddsub_dtosop)
|| (a4stg_faddsubop
&& (!(a4stg_round || a4stg_fdtos))
&& (!a4stg_denorm_inv)
&& a4stg_shl_data_neq_0);
dffe_s #(1) i_add_uf_out (
.din (a4stg_uf),
.en (a6stg_step),
.clk (rclk),
.q (add_uf_out),
.se (se),
.si (),
.so ()
);
assign add_nx_out_in= (a4stg_of_mask
&& a4stg_frac_dbl_nx
&& (a4stg_faddsubd || a5stg_fxtod)
&& ((!a4stg_faddsubd) || a4stg_round))
|| (a4stg_of_mask
&& a4stg_frac_sng_nx
&& (a4stg_faddsubs_fdtos || a5stg_fixtos)
&& ((!a4stg_faddsubs) || a4stg_round))
|| a4stg_nx;
dffe_s #(1) i_add_nx_out (
.din (add_nx_out_in),
.en (a6stg_step),
.clk (rclk),
.q (add_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign add_exc_out[4:0]= {add_nv_out, add_of_out, add_uf_out, 1'b0, add_nx_out};
assign add_exc_out[4:0] =
{add_nv_out,
add_of_out,
add_uf_out,
1'b0,
(add_nx_out || add_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add normalization and special input injection.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_frac1_in_frac1= a1stg_snan_in2
|| (a1stg_qnan_in2 && (!a1stg_snan_in1));
assign a2stg_frac1_in_frac2= a1stg_faddsubop
&& ((!a1stg_2nan_in)
|| a1stg_snan_in2
|| (a1stg_qnan_in2 && (!a1stg_snan_in1)));
assign a1stg_2nan_in_inv= (!a1stg_2nan_in);
assign a1stg_faddsubop_inv= (!a1stg_faddsubop);
assign a2stg_frac1_in_qnan= (a1stg_nan_in
|| (a1stg_2inf_in && a1stg_sub))
&& a1stg_faddsubop;
assign a2stg_frac1_in_nv= a1stg_2inf_in && a1stg_sub && a1stg_faddsubop;
assign a2stg_frac1_in_nv_dbl= a1stg_2inf_in && a1stg_sub && a1stg_faddsubd;
assign a2stg_frac2_in_frac1= a1stg_faddsubop && (!a1stg_infnan_in);
assign a2stg_frac2_in_qnan= a1stg_snan_in2 && (!a1stg_faddsubop);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe right shift count
// count calculation.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_exp_diff_add1= a1stg_faddsub_dtosop && (!a1stg_expadd1[11]);
assign a1stg_exp_diff_add2= a1stg_faddsubop && a1stg_expadd1[11];
assign a1stg_exp_diff_5= (!a1stg_expadd2[5]) && a1stg_fsdtox;
assign a1stg_exp_diff[10:0]= ({11{a1stg_exp_diff_add1}}
& a1stg_expadd1[10:0])
| ({11{a1stg_exp_diff_add2}}
& (~a1stg_expadd4_inv[10:0]))
| ({11{a1stg_fsdtoix}}
& {5'b0, a1stg_exp_diff_5, (~a1stg_expadd2[4:0])});
assign a1stg_clamp63[5:0]= a1stg_exp_diff[5:0] | {6{(|a1stg_exp_diff[10:6])}};
assign a2stg_shr_cnt_in[5:0]= a1stg_clamp63[5:0];
assign a2stg_shr_cnt_5_inv_in= (!a1stg_clamp63[5]);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe right shift.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_shr_frac2_shr_int= a2stg_faddsub_dtosop && a6stg_step;
assign a2stg_shr_frac2_shr_dbl= ((a2stg_fdtox && (|a2stg_exp[11:10]))
|| (a2stg_fstox && (|a2stg_exp[11:7])))
&& a6stg_step;
assign a2stg_shr_frac2_shr_sng= ((a2stg_fdtoi && (|a2stg_exp[11:10]))
|| (a2stg_fstoi && (|a2stg_exp[11:7])))
&& a6stg_step;
assign a2stg_shr_frac2_max= a2stg_fsdtoix && a6stg_step;
assign a2stg_sub_step= a2stg_sub && a6stg_step;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe adder.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_faddsub_clamp63_0= (|(({6{a1stg_expadd1[11]}}
& (~{a1stg_expadd4_inv[10:6],
a1stg_expadd4_inv[0]}))
| ({6{(!a1stg_expadd1[11])}}
& {a1stg_expadd1[10:6], a1stg_expadd1[0]})));
assign a2stg_fracadd_frac2_inv_in= (a1stg_fixtosd && a1stg_in2_63)
|| (a1stg_faddsubop && a1stg_sub
&& (!a1stg_faddsub_clamp63_0));
assign a2stg_fracadd_frac2_inv_shr1_in= a1stg_faddsubop && a1stg_sub
&& a1stg_faddsub_clamp63_0;
assign a2stg_fracadd_frac2_in= (a1stg_fixtosd && (!a1stg_in2_63))
|| a1stg_fstod
|| (a1stg_faddsubop && (!a1stg_sub));
dffe_s #(1) i_a2stg_fracadd_frac2 (
.din (a2stg_fracadd_frac2_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_fracadd_frac2),
.se (se),
.si (),
.so ()
);
assign a2stg_fracadd_cin_in= (a1stg_fixtosd && a1stg_in2_63)
|| (a1stg_faddsubop && a1stg_sub);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe exponent adjustment.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_exp_7ff= a2stg_fstod && (&a2stg_exp[7:0]);
assign a3stg_exp_ff= a2stg_fdtos && (&a2stg_exp[10:0]);
assign a3stg_exp_add= (a2stg_fstod && (!(&a2stg_exp[7:0])))
|| (a2stg_fdtos && (!(&a2stg_exp[10:0])));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe exponent decode- used to identify denorm results.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_expdec_neq_0= a2stg_faddsubop && (a2stg_exp[10:0]<11'h36);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic
// - add pipe main adder
// - add pipe exponent increment/decrement adjustment
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_exp10_0_eq0= (a3stg_exp[10:0]==11'b0);
assign a3stg_exp10_1_eq0= (a3stg_exp[10:1]==10'b0);
assign a3stg_fdtos_inv= (!a3stg_fdtos);
assign a4stg_fixtos_fxtod_inv= (!a4stg_fixtos_fxtod);
assign a4stg_rnd_frac_add_inv= (!(a3stg_fsdtoix
|| (a3stg_faddsubop && a3stg_exp10_0_eq0)));
///////////////////////////////////////////////////////////////////////////////
//
// Control logic- add pipe left shift count.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_shl_cnt_in[9:0]= ({10{a3stg_denorm}}
& {(a3stg_exp[5:4]==2'b11),
(a3stg_exp[5:4]==2'b10),
(a3stg_exp[5:4]==2'b01),
(a3stg_exp[5:4]==2'b00),
a3stg_exp[5:0]})
| ({10{a3stg_denorm_inv}}
& {(a3stg_lead0[5:4]==2'b11),
(a3stg_lead0[5:4]==2'b10),
(a3stg_lead0[5:4]==2'b01),
(a3stg_lead0[5:4]==2'b00),
a3stg_lead0[5:0]});
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe rounding adder.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_rnd_sng= a5stg_fixtos || a4stg_faddsubs_fdtos;
assign a4stg_rnd_dbl= a5stg_fxtod || a4stg_faddsubd;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe fraction output.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_rndup_sng= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
&& a4stg_frac_sng_nx)
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign
&& a4stg_frac_sng_nx)
|| ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_39
&& (a4stg_frac_38_0_nx || a4stg_rnd_frac_40));
assign a4stg_rndup_dbl= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
&& a4stg_frac_dbl_nx)
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign
&& a4stg_frac_dbl_nx)
|| ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_10
&& (a4stg_frac_9_0_nx || a4stg_rnd_frac_11));
assign a4stg_rndup= (a4stg_faddsubd && a4stg_rndup_dbl)
|| (a4stg_faddsubs && a4stg_rndup_sng)
|| (a4stg_fdtos && a4stg_rndup_sng && a4stg_of_mask);
assign a5stg_rndup= (a5stg_fxtod && a4stg_rndup_dbl)
|| (a5stg_fixtos && a4stg_rndup_sng);
assign add_frac_out_rndadd= (a4stg_faddsubop && a4stg_round && a4stg_rndup
&& (!a4stg_in_of))
|| (a4stg_fdtos && a4stg_rndup && (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && a5stg_rndup);
assign add_frac_out_rnd_frac= (a4stg_faddsubop && a4stg_round && (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a4stg_fdtos && (!a4stg_rndup) && (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && (!a5stg_rndup))
|| a4stg_fsdtoix;
assign add_frac_out_shl= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
|| a4stg_fistod;
assign a4stg_to_0= (!((a4stg_rnd_mode==2'b00)
|| ((a4stg_rnd_mode==2'b10) && (!a4stg_sign))
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign)));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe exponent output.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign add_exp_out_expinc= (a4stg_faddsubop && a4stg_round && a4stg_rndup
&& (!a4stg_in_of))
|| (a4stg_fdtos && a4stg_rndup
&& (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && a5stg_rndup);
assign add_exp_out_exp= (a4stg_faddsubop && a4stg_round
&& (!a4stg_in_of))
|| (a4stg_fdtos
&& (!a4stg_in_of))
|| a5stg_fixtos_fxtod;
assign add_exp_out_exp1= (a4stg_faddsubop && a4stg_round
&& (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a4stg_fdtos
&& (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a5stg_fixtos_fxtod
&& (!a5stg_rndup));
assign add_exp_out_expadd= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
|| a4stg_fistod;
assign a4stg_to_0_inv= (!a4stg_to_0);
endmodule
|
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
(*
* Copyright © 2013 http://io7m.com
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*)
(** Virtual paths. *)
Require Coq.Lists.List.
Require Coq.Strings.String.
Require ListAux.
Require ListMapWeak.
Require ListSetWeak.
Require MapWeak.
Require Names.
Require SetWeak.
Import ListAux.Notations.
Open Scope string_scope.
Open Scope list_scope.
(** A virtual path represents a path in the virtual filesystem.
Virtual paths are always absolute.
The concrete syntax of virtual paths is given by the following EBNF
grammar (where [name] indicates a string representing a
valid [Names.name]):
<<
path = "/" , [ name , ("/" , name)* ] ;
>>
A virtual path is conceptually a list of [Names.name],
with the empty list representing the root directory. *)
Definition t := list Names.t.
Definition root : t := nil.
(** Some example virtual paths include: [/bin], and
[/usr/bin/ps]. *)
Example bin : t := Names.bin :: nil.
Example usr_bin_ps : t := Names.usr :: Names.bin :: Names.ps :: nil.
(** Because equality of [Names.name] is decidable, equality
of [t] is too. *)
Theorem eq_decidable : forall (p0 p1 : t),
{p0 = p1}+{~p0 = p1}.
Proof.
apply List.list_eq_dec.
apply Names.eq_decidable.
Qed.
(** The property of [p0] being an ancestor of [p1]. [p0] is an ancestor
of [p1] iff:
- [p0] is not equal to [p1], and
- [p0] is a prefix of [p1]
*)
Definition is_ancestor_of (p0 p1 : t) : Prop :=
(p0 <> p1) /\ (ListAux.is_prefix p0 p1).
(** The property of [p0] being the parent of [p1]. [p0] is the parent
of [p1] iff:
- [p0] is an ancestor of [p1], and
- There exists some [x] such that [p0 @@ x = p1]
*)
Definition is_parent_of (p0 p1 : t) : Prop :=
(is_ancestor_of p0 p1) /\ (exists x, p0 @@ x = p1).
(** The [root] path is an ancestor of any non-[root] path. *)
Theorem is_ancestor_of_root : forall (p : t),
p <> root -> is_ancestor_of root p.
Proof.
unfold is_ancestor_of.
intros p Hn.
split.
apply not_eq_sym.
assumption.
induction p as [|px pr].
contradict Hn; reflexivity.
exact I.
Qed.
(** The [root] path has no ancestors. *)
Theorem is_ancestor_of_root_false : forall (p : t),
~is_ancestor_of p root.
Proof.
unfold is_ancestor_of.
induction p; intuition.
Qed.
(** The [root] path has no parent. *)
Theorem is_parent_of_root_false : forall (p : t),
~is_parent_of p root.
Proof.
unfold root.
unfold is_parent_of.
induction p; intuition.
inversion H1.
contradict H. apply ListAux.append_element_not_equal.
inversion H0.
contradict H3.
Qed.
(** Iff a path has a single element, then its parent is the [root]. *)
Theorem is_parent_of_root_single : forall (x : Names.t),
is_parent_of root (x :: nil).
Proof.
unfold root.
unfold is_parent_of.
unfold is_ancestor_of.
intro x.
split.
split.
discriminate.
exact I.
exists x; reflexivity.
Qed.
(** Being an ancestor is decidable. *)
Theorem is_ancestor_of_decidable : forall (p0 p1 : t),
{is_ancestor_of p0 p1}+{~is_ancestor_of p0 p1}.
Proof.
unfold is_ancestor_of.
intros p0 p1.
destruct (eq_decidable p0 p1).
right; rewrite e; intuition.
destruct (ListAux.is_prefix_decidable Names.eq_decidable p0 p1).
left; intuition.
right; intuition.
Qed.
(** Being a parent is decidable. *)
Theorem is_parent_of_decidable : forall (p0 p1 : t),
{is_parent_of p0 p1}+{~is_parent_of p0 p1}.
Proof.
intros p0 p1.
unfold is_parent_of in *.
unfold is_ancestor_of in *.
destruct (is_ancestor_of_decidable p0 p1).
destruct i.
destruct (ListAux.append_element_decidable Names.eq_decidable p0 p1).
left; intuition.
right; intuition.
unfold is_parent_of in *.
unfold is_ancestor_of in *.
right; intuition.
Qed.
(** Being an ancestor is transitive. *)
Theorem is_ancestor_of_transitive : forall (p0 p1 p2 : t),
is_ancestor_of p0 p1 -> is_ancestor_of p1 p2 -> is_ancestor_of p0 p2.
Proof.
Admitted.
(** The property of [p0] containing [p1]. The path [p0] is said to
contain [p1] iff:
- [p0 = p1], or
- [p0] is an ancestor of [p1] *)
Definition contains (p0 p1 : t) :=
(p0 = p1) \/ (is_ancestor_of p0 p1).
(** [contains] is decidable. *)
Theorem contains_decidable : forall (p0 p1 : t),
{contains p0 p1}+{~contains p0 p1}.
Proof.
unfold contains.
intros p0 p1.
destruct (eq_decidable p0 p1).
destruct (is_ancestor_of_decidable p0 p1).
left; left; assumption.
left; left; assumption.
destruct (is_ancestor_of_decidable p0 p1).
left; right; assumption.
right; tauto.
Qed.
(** All paths contain themselves. *)
Theorem contains_self : forall (p : t),
contains p p.
Proof.
left; reflexivity.
Qed.
(** If [p] is contained by [root], then [p = root]. *)
Theorem contains_is_root : forall (p : t),
contains p root -> p = root.
Proof.
unfold contains.
unfold is_ancestor_of.
intros p Hc.
induction p as [|ph pr].
reflexivity.
destruct Hc as [HL|HR].
assumption.
destruct HR as [HRL HRR].
inversion HRR.
Qed.
(** Containment is transitive. *)
Theorem contains_trans : forall (p q r : t),
contains p q -> contains q r -> contains p r.
Proof.
intros p q r Hpq Hqr.
unfold contains in *.
unfold is_ancestor_of in *.
destruct Hpq as [HpqL|HpqR].
destruct Hqr as [HqrL|HqrR].
left; apply (eq_trans HpqL HqrL).
rewrite HpqL.
right; assumption.
destruct Hqr as [HqrL|HqrR].
rewrite <- HqrL.
right; assumption.
Admitted.
(** Paths can be "subtracted" to remove common prefixes. This
is useful for calculating the paths of files inside archives mounted
into a filesystem. As an example, if an archive [A] is mounted at
[/usr] and [A] contains the path [/bin/ps], then
[subtract /usr/bin/ps /usr = /bin/ps].
So, if [contains p1 p0], then subtraction removes the first
[length p1] elements of [p0]. *)
Definition subtract (p0 p1 : t) : t :=
match contains_decidable p1 p0 with
| left _ => List.skipn (length p1) p0
| right _ => p0
end.
(** As stated, [subtract /usr/bin/ps /usr = /bin/ps]. *)
Example subtract_usr : subtract usr_bin_ps (Names.usr :: nil) = Names.bin :: Names.ps :: nil.
Proof.
compute.
destruct contains_decidable as [Hc|Hnc].
reflexivity.
contradict Hnc.
right; compute; intuition.
inversion H.
Qed.
(** Attempting to subtract [p1] from [p0] when [p1] does not contain [p0]
does nothing. *)
Theorem contains_subtract_false : forall (p0 p1 : t),
~contains p1 p0 -> subtract p0 p1 = p0.
Proof.
intros p0 p1 Hna.
unfold subtract.
destruct (contains_decidable p1 p0).
contradiction.
reflexivity.
Qed.
(** If [p1] contains [p0], then subtracting [p1] from [p0] reduces
the length of [p0] by [length p1]. *)
Theorem contains_subtract_length : forall (p0 p1 : t),
contains p1 p0 -> length (subtract p0 p1) = length p0 - length p1.
Proof.
intros p0 p1.
unfold subtract.
destruct (contains_decidable p1 p0).
intros; apply ListAux.skipn_length.
intros; contradiction.
Qed.
(** If [p0 = p1], then [subtract p0 p1 = root]. *)
Theorem contains_subtract_is_root : forall (p0 p1 : t),
p0 = p1 -> subtract p0 p1 = root.
Proof.
intros p0 p1 H_eq.
unfold subtract.
rewrite H_eq.
destruct (contains_decidable p1 p1) as [Hc|Hnc].
apply ListAux.skipn_0.
contradict Hnc.
left; reflexivity.
Qed.
(** Subtracting anything from [root] results in [root]. *)
Theorem subtract_root : forall (p : t),
subtract root p = root.
Proof.
intros p.
unfold subtract.
destruct (contains_decidable p root).
destruct p; reflexivity.
reflexivity.
Qed.
(** Subtracting anything from [root] results in [root]. *)
Theorem subtract_from_root : forall (p : t),
subtract root p = root.
Proof.
intros p.
unfold subtract.
destruct (contains_decidable p root).
destruct p; reflexivity.
reflexivity.
Qed.
(** Subtracting [root] from [p] results in [p]. *)
Theorem subtract_root_from : forall p,
subtract p root = p.
Proof.
intros p.
unfold subtract.
destruct (contains_decidable root p); reflexivity.
Qed.
(** Subtracting [p] from itself results in [root]. *)
Theorem subtract_self : forall p,
subtract p p = root.
Proof.
intros p.
unfold subtract.
destruct (contains_decidable p p) as [Hc|Hnc].
induction p.
reflexivity.
apply IHp.
left; reflexivity.
contradict Hnc.
left; reflexivity.
Qed.
Theorem contains_subtract_id : forall (p0 p1 : t),
contains p0 p1 -> p0 ++ (subtract p1 p0) = p1.
Proof.
unfold contains.
unfold is_ancestor_of.
induction p0 as [|p0h p0r].
destruct p1 as [|p1h p1r].
intros; simpl. apply subtract_from_root.
intros; simpl. apply subtract_root_from.
intros p1 H.
destruct H as [HL|HR].
rewrite HL.
rewrite subtract_self.
unfold root.
auto with *.
destruct p1 as [|p1h p1r].
destruct HR as [HRL HRR].
contradict HRR.
destruct HR as [HRL HRR].
destruct HRR as [HRRL HRRR].
simpl in *.
rewrite HRRL.
Admitted.
(** The sequential enumeration of the ancestors of [p] is
a list of the ancestors of [p] starting with the most distant
ancestor first.
As an example, given a path [/usr/bin/ps], a sequential
enumeration of the ancestors would result in a list
[/ :: /usr :: /usr/bin :: nil].
The [Enumeration] module provides a function to calculate the
enumeration. *)
Module Type EnumerationSignature.
Parameter enumeration : t -> list t.
(** The [enumeration] of the [root] is empty. *)
Parameter enumeration_root : enumeration root = nil.
(** Therefore, if the enumeration of [p] is empty, then [p = root]. *)
Parameter enumeration_is_root : forall (p : t),
enumeration p = nil -> p = root.
(** All paths returned by [enumeration] are ancestors of the original non-empty path. *)
Parameter enumeration_ancestors : forall (p q : t),
p <> root -> (List.In q (enumeration p) <-> is_ancestor_of q p).
End EnumerationSignature.
(** The actual implementation of the [enumeration] function. *)
Module Enumeration <: EnumerationSignature.
Definition enumeration (e : t) :=
match e with
| nil => nil
| _ :: _ => ListAux.prefixes e
end.
(** The [enumeration] of the [root] is empty. *)
Theorem enumeration_root :
enumeration nil = nil.
Proof.
reflexivity.
Qed.
(** Therefore, if the enumeration of [p] is empty, then [p = root]. *)
Theorem enumeration_is_root : forall (p : t),
enumeration p = nil -> p = root.
Proof.
induction p as [|ph pr].
auto.
intros.
simpl in H.
inversion H.
Qed.
(** All paths returned by [enumeration] are ancestors of the original non-empty path. *)
Theorem enumeration_ancestors : forall (p q : t),
p <> root -> (List.In q (enumeration p) <-> is_ancestor_of q p).
Proof.
intros p q H.
destruct p.
contradict H; reflexivity.
unfold enumeration.
unfold is_ancestor_of.
apply ListAux.prefixes_correct.
Qed.
End Enumeration.
(** As stated, [enumeration /usr/bin/ps = [/, /usr, /usr/bin]]. *)
Theorem enum_example : Enumeration.enumeration usr_bin_ps =
nil :: (Names.usr :: nil) :: (Names.usr :: Names.bin :: nil) :: nil.
Proof.
compute.
reflexivity.
Qed.
(** A map with virtual paths as keys. *)
Module PathVirtualMapsKey : MapWeak.Parameters with Definition key := t.
Definition key := t.
Definition key_eq_decidable := eq_decidable.
End PathVirtualMapsKey.
Module Maps := ListMapWeak.Make(PathVirtualMapsKey).
(** A finite set of virtual paths. *)
Module PathVirtualSetParameters : SetWeak.Parameters with Definition t := t.
Definition t := t.
Definition t_eq_decidable := eq_decidable.
End PathVirtualSetParameters.
Module Sets := ListSetWeak.Make(PathVirtualSetParameters).
|
Require Import Typing.
Require Export ContextualCausality.
Require Import Tactics.
Require Import Utils.
Require Import Environments.
Require Import Causality.
Require Import Templates.
Import ListNotations.
(* A type system with time-indexed types. This system subsumes both
the type system and the contextual causality system. *)
Open Scope Z.
(* Timed types *)
Inductive TiTy := TimedType (ty : Ty) (ti : TimeB).
Infix "@" := TimedType (at level 50).
(* Selector functions to extract the time and the type of a timed
type. *)
Definition time (t : TiTy) := match t with TimedType _ ti => ti end.
Definition type (t : TiTy) := match t with TimedType ty _ => ty end.
(* Convenience function to add time to a timed type. *)
Definition add_time d (t : TiTy) := match t with TimedType ty ti => TimedType ty (tadd' d ti) end.
Definition sub_time d (t : TiTy) := match t with TimedType ty ti => TimedType ty (tsub' d ti) end.
(* A time timed time environment maps variables to timed types. *)
Definition TiTyEnv := Env' TiTy.
Open Scope time.
(* Definition of the timed type inference rules for variables,
operators, expressions and contracts. *)
Inductive TiTyV : TiTyEnv -> TiTy -> Var -> Prop :=
| causal_V1 t t' g : type t = type t' -> time t <= time t' -> TiTyV (t :: g) t' V1
| causal_VS g v t t' : TiTyV g t v -> TiTyV (t' :: g) t (VS v).
Definition TiTyOp (op : Op) (ts : list TiTy) (t:TiTy) : Prop
:= (all (fun t' => time t' = time t) ts) /\ TypeOp op (map type ts) (type t).
Lemma TiTyOp_TypeOp op ts t ty tys :
TypeOp op tys ty ->
(all (fun t' => time t' = time t) ts) ->
tys = map type ts -> ty = type t ->
TiTyOp op ts t.
Proof.
intros. subst. firstorder.
Qed.
Inductive TiTyE : TiTyEnv -> TiTy -> Exp -> Prop:=
| causal_op t ts ts' op args : TiTyOp op ts' t -> all2 (TiTyE ts) ts' args -> TiTyE ts t (OpE op args)
| causal_obs l t' t ts : Time t' <= time t -> |-O l ∶ type t -> TiTyE ts t (Obs l t')
| causal_var t ts v : TiTyV ts t v -> TiTyE ts t (VarE v)
| causal_acc t ts e1 e2 n : TiTyE (map (add_time n) ts) (add_time n t) e2
-> TiTyE (type t @ TimeBot :: ts) t e1
-> TiTyE ts t (Acc e1 n e2)
.
Inductive TiTyC : TiTyEnv -> TimeB -> Contr -> Prop :=
| causal_zero ts t : TiTyC ts t Zero
| causal_translate ts t d c : TiTyC (map (sub_time d) ts) (tsub' d t) c
-> TiTyC ts t (Translate (Tnum d) c)
| causal_let ts t t' e c : TiTyE ts t' e -> TiTyC (t' :: ts) t c -> TiTyC ts t (Let e c)
| causal_scale ts ti ti' e c : ti' <= ti -> TiTyE ts (REAL @ ti) e -> TiTyC ts ti c -> TiTyC ts ti' (Scale e c)
| causal_both ts t c1 c2 : TiTyC ts t c1 -> TiTyC ts t c2 -> TiTyC ts t (Both c1 c2)
| causal_transfer t ts p1 p2 a : t <= Time 0 -> TiTyC ts t (Transfer p1 p2 a)
| causal_if ts t d e c1 c2 : TiTyE ts (BOOL @ Time 0) e -> TiTyC ts t c1
-> TiTyC (map (sub_time d) ts) (tsub' d t) c2
-> TiTyC ts t (If e (Tnum d) c1 c2)
.
Hint Constructors TiTyV TiTyE TiTyC.
(* We now show that timed typing implies both well-typing and
contextual causality. *)
Lemma TiTyV_type ts t v : TiTyV ts t v -> map type ts |-X v ∶ type t.
Proof.
intro T. induction T;simpl in *; try rewrite H; auto.
Qed.
Lemma type_add_time d t : type (add_time d t) = type t.
Proof.
destruct t. reflexivity.
Qed.
Lemma type_sub_time d t : type (sub_time d t) = type t.
Proof.
destruct t. reflexivity.
Qed.
(* Timed typing on expressions implies well-typing. *)
Lemma TiTyE_type ts t e : TiTyE ts t e -> map type ts |-E e ∶ type t.
Proof.
intros T. generalize dependent ts. generalize dependent t.
induction e using Exp_ind';intros;inversion T;simpl in T; subst.
- unfold TiTyOp in *. destruct H4. econstructor;eauto. clear H1. clear T.
generalize dependent t.
induction H5;intros; simpl in *; constructor;inversion H;inversion H1;subst; auto.
eapply IHall2;eauto.
- auto.
- constructor. apply TiTyV_type. assumption.
- constructor.
+ apply IHe1 in H5. simpl in *. assumption.
+ apply IHe2 in H3. rewrite map_map in *. rewrite type_add_time in *.
erewrite map_ext. eassumption. intros. simpl. rewrite type_add_time. reflexivity.
Qed.
Hint Resolve TiTyE_type.
(* Timed typing implies well-typing. *)
Theorem TiTyC_type ts t e : TiTyC ts t e -> map type ts |-C e.
Proof.
intros T. induction T; econstructor;simpl in *;eauto.
- rewrite map_map in IHT. erewrite map_ext. eassumption. intro. simpl.
rewrite type_sub_time. reflexivity.
- apply TiTyE_type in H0. simpl in H0. apply H0.
- apply TiTyE_type in H. simpl in H. apply H.
- rewrite map_map in IHT2. erewrite map_ext. eassumption. intro. simpl.
rewrite type_sub_time. reflexivity.
Qed.
Lemma TiTyV_time ts t v : TiTyV ts t v -> CausalV (map time ts) (time t) v.
Proof.
intro T. induction T;simpl in *; try rewrite H; auto.
Qed.
Lemma time_add_time d t : time (add_time d t) = tadd' d (time t).
Proof.
destruct t. reflexivity.
Qed.
Lemma time_sub_time d t : time (sub_time d t) = tsub' d (time t).
Proof.
destruct t. reflexivity.
Qed.
(* Timed typing on expressions implies contextual causality. *)
Lemma TiTyE_time ts t e : TiTyE ts t e -> CausalE (map time ts) (time t) e.
Proof.
intros T. generalize dependent ts. generalize dependent t.
induction e using Exp_ind';intros;inversion T;simpl in T; subst.
- unfold TiTyOp in *. destruct H4. econstructor;eauto. clear H1. clear T.
generalize dependent t.
induction H5;intros; simpl in *; constructor;inversion H;inversion H1;subst; auto.
rewrite <- H9. auto.
- auto.
- constructor. apply TiTyV_time. assumption.
- econstructor.
+ apply IHe2 in H3. rewrite map_map in *. rewrite time_add_time in *.
erewrite map_ext. eassumption. intros. simpl. rewrite time_add_time. reflexivity.
+ apply IHe1 in H5. simpl in *. eassumption.
Qed.
Hint Resolve TiTyE_type.
(* Timed typing implies contextual causality. *)
Theorem TiTyC_time ts t c : TiTyC ts t c -> CausalC (map time ts) t c.
Proof.
intros T. induction T; econstructor;simpl in *;eauto.
- rewrite map_map in *. erewrite map_ext. eassumption. intro. simpl.
rewrite time_sub_time. reflexivity.
- apply TiTyE_time in H. simpl in H. apply H.
- apply TiTyE_time in H0. simpl in H0. apply H0.
- apply TiTyE_time in H. simpl in H. apply H.
- rewrite map_map in *. erewrite map_ext. eassumption. intro. simpl.
rewrite time_sub_time. reflexivity.
Qed.
Corollary TiTyC_causal t c tenv : TiTyC [] t c -> causal c tenv.
Proof.
intros T. apply TiTyC_time in T. simpl in *. eauto using CausalC_sound.
Qed.
(* Below we show that the conjunction of well typing and contextual
causality implies timed typing. *)
Infix "@@" := (zipWith TimedType) (at level 1).
Fixpoint repeat {A} (n : nat) (x : A) : list A :=
match n with
| O => nil
| S m => x :: repeat m x
end.
Lemma map_type tys tis : length tys = length tis -> map type tys @@ tis = tys.
Proof.
generalize dependent tis. induction tys;intros. reflexivity.
destruct tis;tryfalse. simpl. f_equal. auto.
Qed.
Lemma map_time tys tis : length tys = length tis -> map time tys @@ tis = tis.
Proof.
generalize dependent tys. induction tis;intros. destruct tys; reflexivity.
destruct tys;tryfalse. simpl. f_equal. auto.
Qed.
Lemma map_type_time ts : (map type ts) @@ (map time ts) = ts.
Proof.
induction ts;simpl;f_equal;try destruct a;eauto.
Qed.
Lemma map_type_repeat tys t : map type tys @@ (repeat (length tys) t) = tys.
Proof.
induction tys. reflexivity. simpl. f_equal. auto.
Qed.
Lemma map_add_time n tys tis : map (add_time n) tys @@ tis = tys @@ (map (tadd' n) tis).
Proof.
generalize dependent tis. induction tys;intros. reflexivity.
destruct tis. reflexivity.
simpl. rewrite IHtys. reflexivity.
Qed.
Lemma map_sub_time n tys tis : map (sub_time n) tys @@ tis = tys @@ (map (tsub' n) tis).
Proof.
generalize dependent tis. induction tys;intros. reflexivity.
destruct tis. reflexivity.
simpl. rewrite IHtys. reflexivity.
Qed.
Lemma type_TiTyE tis tys ti ty e : tys |-E e ∶ ty -> CausalE tis ti e -> TiTyE tys@@tis (ty@ti) e.
Proof.
intros Ty Ti. generalize dependent tis. generalize dependent ti.
induction Ty using TypeExp_ind';intros;inversion Ti;subst;clear Ti.
- apply causal_op with (ts' := ts @@ (repeat (length ts) ti)). unfold TiTyOp. split.
clear H. clear H0. clear H1. induction ts;simpl; constructor. reflexivity. apply IHts.
rewrite map_type_repeat. simpl. assumption.
clear H. induction H0;simpl;constructor;inversion H1;inversion H5;subst;auto.
- eauto.
- econstructor. generalize dependent tis. generalize dependent ti.
induction H;intros;inversion H3; clear H3;subst;simpl; econstructor; eauto.
- apply causal_acc. simpl. rewrite map_add_time. eauto.
specialize (IHTy1 ti (TimeBot :: tis)). eauto.
Qed.
Theorem type_TiTyC tis tys ti c : tys |-C c -> CausalC tis ti c -> TiTyC tys@@tis ti c.
Proof.
intros Ty Ti. generalize dependent tis. generalize dependent ti.
induction Ty;intros;inversion Ti;subst;clear Ti;eauto using type_TiTyE.
- specialize (IHTy ti (t' :: tis)). eauto using type_TiTyE.
- econstructor. rewrite map_sub_time. eauto.
- econstructor; eauto using type_TiTyE. rewrite map_sub_time. eauto.
Qed.
Theorem TiTyE_decompose ts t e : TiTyE ts t e <-> map type ts |-E e ∶ type t /\ CausalE (map time ts) (time t) e.
Proof.
split; intros. split; eauto using TiTyE_type, TiTyE_time. destruct H.
eapply type_TiTyE in H;eauto. rewrite map_type_time in H. destruct t;simpl in H. assumption.
Qed.
Theorem TiTyC_decompose ts ti c : TiTyC ts ti c <-> map type ts |-C c /\ CausalC (map time ts) ti c.
Proof.
split; intros. split; eauto using TiTyC_type, TiTyC_time. destruct H.
eapply type_TiTyC in H;eauto. rewrite map_type_time in H. assumption.
Qed.
Theorem TiTyC_decompose' tis tys ti c : length tys = length tis ->
(TiTyC tys@@tis ti c <-> tys |-C c /\ CausalC tis ti c).
Proof.
intro L. split; intros. split. apply TiTyC_type in H. rewrite map_type in H;auto.
apply TiTyC_time in H. rewrite map_time in H; auto. destruct H. apply type_TiTyC;auto.
Qed.
Definition subtype (t1 t2 : TiTy) := type t1 = type t2 /\ time t1 <= time t2.
Infix "<|" := subtype (at level 1).
Hint Unfold subtype.
Lemma subtype_type t1 t2 : t1 <| t2 -> type t1 = type t2.
Proof.
intros. unfold subtype in *. tauto.
Qed.
Lemma subtype_time t1 t2 : t1 <| t2 -> time t1 <= time t2.
Proof.
intros. unfold subtype in *. tauto.
Qed.
Hint Resolve subtype_time subtype_type.
Lemma all_subtype_type ts1 ts2 : all2 subtype ts1 ts2 -> map type ts1 = map type ts2.
Proof.
intro H. induction H; simpl; f_equal; eauto.
Qed.
Lemma all_subtype_time ts1 ts2 : all2 subtype ts1 ts2 -> all2 tle (map time ts1) (map time ts2).
Proof.
intro H. induction H; simpl; f_equal; eauto.
Qed.
Hint Resolve all_subtype_time all_subtype_type.
Lemma TiTyE_open t t' ts ts' (e : Exp) : all2 subtype ts' ts -> t <| t' -> TiTyE ts t e -> TiTyE ts' t' e.
Proof.
intros Ss S T. rewrite TiTyE_decompose in *. destruct T. destruct S as [S1 S2].
split. rewrite <- S1. erewrite all_subtype_type by eassumption. assumption.
eapply CausalE_open;eauto.
Qed.
Lemma TiTyC_open t t' ts ts' c : all2 subtype ts' ts -> t' <= t -> TiTyC ts t c -> TiTyC ts' t' c.
Proof.
intros Ss S T. rewrite TiTyC_decompose in *. destruct T.
split. erewrite all_subtype_type by eassumption. assumption.
eapply CausalC_open;eauto.
Qed.
Lemma subtype_refl t : t <| t.
Proof. destruct t. auto. Qed.
Hint Immediate subtype_refl.
Lemma all_subtype_refl ts : all2 subtype ts ts.
Proof.
induction ts; eauto.
Qed.
(* Special case of [TiTyE_open] where the type environment stays the same. *)
Corollary TiTyE_open' t t' ts (e : Exp) : t <| t' -> TiTyE ts t e -> TiTyE ts t' e.
Proof. eauto using TiTyE_open, all_subtype_refl. Qed.
Lemma TiTyC_open' t t' ts c : t' <= t -> TiTyC ts t c -> TiTyC ts t' c.
Proof. eauto using TiTyC_open, all_subtype_refl. Qed.
Definition inferObs (l : ObsLabel) : Ty :=
match l with
| LabR _ => REAL
| LabB _ => BOOL
end.
Lemma inferObs_sound l : |-O l ∶ inferObs l.
Proof.
destruct l; auto.
Qed.
Definition tyeqb (t1 t2 : Ty) : bool :=
match t1, t2 with
| REAL, REAL => true
| BOOL, BOOL => true
| _,_ => false
end.
Lemma tyeqb_iff t1 t2 : tyeqb t1 t2 = true <-> t1 = t2.
Proof.
destruct t1;destruct t2; split;intro;simpl in *; congruence.
Qed.
Definition inferOp (op : Op) (args : list Ty) : option Ty :=
match op with
| Add => match args with [REAL;REAL] => Some REAL | _ => None end
| Sub => match args with [REAL;REAL] => Some REAL | _ => None end
| Mult => match args with [REAL;REAL] => Some REAL | _ => None end
| Div => match args with [REAL;REAL] => Some REAL | _ => None end
| And => match args with [BOOL;BOOL] => Some BOOL | _ => None end
| Or => match args with [BOOL;BOOL] => Some BOOL | _ => None end
| Less => match args with [REAL;REAL] => Some BOOL | _ => None end
| Leq => match args with [REAL;REAL] => Some BOOL | _ => None end
| Equal => match args with [REAL;REAL] => Some BOOL | _ => None end
| Not => match args with [BOOL] => Some BOOL | _ => None end
| Neg => match args with [REAL] => Some REAL | _ => None end
| BLit _ => match args with [] => Some BOOL | _ => None end
| RLit _ => match args with [] => Some REAL | _ => None end
| Cond => match args with [BOOL;t1;t2] => if tyeqb t1 t2 then Some t1 else None | _ => None end
end.
Lemma inferOp_TypeOp op args ty : inferOp op args = Some ty <-> |-Op op ∶ args => ty.
Proof.
destruct op; split; intro H; repeat (destruct args;try destruct t; simpl in *; try solve [inversion H;eauto]).
Qed.
Definition tmax (t1 t2 : TimeB) : TimeB :=
match t1,t2 with
| TimeBot, _ => t2
| _, TimeBot => t1
| Time t1', Time t2' => Time (Z.max t1' t2')
end.
Lemma tmax_tle_iff t t1 t2 : t <= tmax t1 t2 <-> t <= t1 \/ t <= t2.
Proof.
destruct t;split;firstorder; destruct t1, t2; inversion H; try rewrite -> Z.max_le_iff in H2; firstorder;
constructor; rewrite -> Z.max_le_iff; tauto.
Qed.
Lemma tmax_lub_iff t t1 t2 : tmax t1 t2 <= t <-> t1 <= t /\ t2 <= t.
Proof.
destruct t;split;firstorder destruct t1, t2; simpl in H; inversion_clear H;
try constructor; try rewrite -> Z.max_lub_iff in H0; firstorder.
rewrite -> Z.max_lub_iff. inversion H0. tauto. inversion H0. tauto.
Qed.
(* Define as left fold instead (and then prove that it is equal to the right fold). *)
Definition tmaxs (ts : list TimeB) : TimeB :=fold_right tmax TimeBot ts.
Lemma tmaxs_cons x xs : tmaxs (x :: xs) = tmax x (tmaxs xs).
Proof.
unfold tmaxs. fold ([x] ++ xs). rewrite fold_right_app. reflexivity.
Qed.
Fixpoint inferE (env : TiTyEnv) (e:Exp) : option TiTy :=
match e with
| OpE op args => sequence (map (inferE env) args) >>=
(fun args' => liftM (fun ty => ty @ tmaxs (map time args'))
(inferOp op (map type args')))
| VarE v => lookupEnv v env
| Obs l i => Some (inferObs l @ Time i)
| Acc f d z => inferE (map (add_time d) env) z >>=
(fun t => inferE (type t @ TimeBot :: env) f >>=
(fun t' => if tyeqb (type t) (type t')
then Some (type t @ tmax (tsub' d (time t)) (time t'))
else None))
end.
(* Time intervals *)
Open Scope Z.
Definition ole (lo hi : option Z) := forall l h, lo = Some l -> hi = Some h -> l <= h.
Hint Unfold ole.
(* Time intervals are always non-empty. *)
Inductive TimeI := Time' (t : TimeB) | TimeTop.
Definition iadd d t := match t with
| TimeTop => TimeTop
| Time' t' => Time' (tadd' d t')
end.
Definition tileb l t := match t with
| TimeTop => true
| Time' t' => tleb l t'
end.
Definition ileb t1 t2 := match t1,t2 with
| _,TimeTop => true
| Time' s1, Time' s2 => tleb s1 s2
| _, _ => false
end.
Definition imin t1 t2 := if ileb t1 t2 then t1 else t2.
Open Scope time.
Fixpoint inferC (env : TiTyEnv) (tenv : TEnv) (c:Contr) : option TimeI :=
match c with
| Zero => Some TimeTop
| Transfer p1 p2 a => Some (Time' (Time 0))
| Translate d c' => liftM (iadd (TexprSem d tenv)) (inferC (map (sub_time (TexprSem d tenv)) env) tenv c')
| Scale e c' => inferE env e >>= fun ty =>
inferC env tenv c' >>= fun t => if tyeqb (type ty) REAL && tileb (time ty) t
then Some t
else None
| Both c1 c2 => liftM2 imin (inferC env tenv c1) (inferC env tenv c2)
| Let e c' => inferE env e >>= fun t => inferC (t :: env) tenv c'
| If e d c1 c2 => inferE env e >>= fun t =>
if tyeqb (type t) BOOL && tleb (time t) (Time 0)
then liftM2 imin (inferC env tenv c1) (liftM (iadd (TexprSem d tenv))
(inferC (map (sub_time (TexprSem d tenv)) env) tenv c2))
else None
end.
Lemma all_type_tle args ts env m :
all2 (TiTyE env) ts args
-> tmaxs (map time ts) <= m
-> all2 (TiTyE env) (map (fun t => type t @ m) ts) args.
Proof.
intros T M. rewrite <- map_id. apply all2_map'. generalize dependent m. induction T;intros m M;constructor.
- simpl. eapply TiTyE_open' with (t:=x);auto. constructor. reflexivity.
simpl in *. rewrite tmax_lub_iff in M. tauto.
- apply IHT. simpl in M. rewrite tmax_lub_iff in M. tauto.
Qed.
Corollary all_type_max args ts env :
all2 (TiTyE env) ts args
-> all2 (TiTyE env) (map (fun t => type t @ tmaxs (map time ts)) ts) args.
Proof.
intros. apply all_type_tle;auto.
Qed.
Theorem inferE_sound env e t :
inferE env e = Some t -> TiTyE env t e.
Proof.
intros I. generalize dependent env. generalize dependent t.
induction e using Exp_ind'; intros; simpl in *;option_inv_auto.
- assert (all2 (TiTyE env) x args) as T
by (clear H3; generalize dependent x; induction H; simpl in *;
intros; option_inv_auto; eauto using TiTyE_open').
apply all_type_max in T. remember (map (fun t => type t @ tmaxs (map time x)) x) as x'.
rewrite inferOp_TypeOp in *. apply causal_op with (ts':= x').
constructor. simpl. subst. apply all_map_forall. auto. simpl.
assert (map type x = map type x') as Tx.
subst. induction x;simpl;f_equal. rewrite map_map. simpl. reflexivity.
rewrite <- Tx. assumption. assumption.
- destruct l;eauto.
- generalize dependent t. generalize dependent env.
induction v;constructor; destruct env; simpl in I; inversion I; auto.
apply IHv in I. inversion I. auto.
- destruct x; destruct x0; simpl in H3. cases (tyeqb ty ty0) as E;tryfalse. apply tyeqb_iff in E.
inversion_clear H3. subst. eapply IHe1 in H2. eapply IHe2 in H0.
econstructor;simpl in *;
[eapply TiTyE_open' with (t:=ty0 @ ti)|eapply TiTyE_open' with (t:=ty0 @ ti0)]; try assumption;
constructor; try reflexivity; simpl; destruct ti,ti0;auto;
simpl; autounfold;constructor; try omega.
+ rewrite <- Z.add_max_distr_r. rewrite Z.max_le_iff. left. omega.
+ rewrite Z.max_le_iff. right. omega.
Qed.
Lemma inferObs_complete l t : |-O l ∶ t -> inferObs l = t.
Proof.
intros T. destruct T; reflexivity.
Qed.
Open Scope time.
Lemma tadd_tsub_tle d x y : x <= tadd d y -> tsub d x <= y.
Proof.
intros T.
destruct x, y; simpl in *;eauto;inversion T; constructor. omega.
Qed.
Lemma tyeqb_refl x : tyeqb x x = true.
Proof. rewrite tyeqb_iff. reflexivity. Qed.
Lemma all_tmaxs ts' s :
all (fun t' : TiTy => time t' = time s) ts' -> tmaxs (map time ts') <= time s.
Proof.
intros A. induction A. constructor. simpl.
rewrite tmax_lub_iff. rewrite H. auto using tle_refl.
Qed.
Theorem inferE_complete env e s :
TiTyE env s e -> exists t, inferE env e = Some t /\ t <| s.
Proof.
intros T. generalize dependent env. generalize dependent s.
induction e using Exp_ind'; intros; inversion T;clear T;subst;simpl in *;option_inv_auto.
- assert (exists ts,sequence (map (inferE env) args) = Some ts /\ map type ts = map type ts'
/\ tmaxs (map time ts) <= tmaxs (map time ts')) as Q.
clear H4. induction H5;simpl. eauto. inversion H. subst. eapply IHall2 in H4.
decompose [ex and] H4. apply H3 in H0. decompose [ex and] H0. eexists. split.
repeat rewr_assumption. simpl. autounfold. reflexivity. simpl. split.
apply subtype_type in H9. repeat rewr_assumption. reflexivity.
inversion H9. rewrite tmax_lub_iff. split.
rewrite tmax_tle_iff. auto. rewrite tmax_tle_iff. auto.
decompose [ex and] Q. inversion H4. rewrite <- inferOp_TypeOp in *.
repeat (rewr_assumption; simpl). autounfold. eexists. split.
reflexivity. split. reflexivity. simpl.
assert (tmaxs (map time ts') <= time s). apply all_tmaxs. eauto.
eauto using tle_trans.
- eexists. split. erewrite inferObs_complete by eassumption. reflexivity. eauto.
- induction H2;try decompose [ex and] IHTiTyV;eexists;split; simpl;eauto.
- apply IHe1 in H5. apply IHe2 in H3. decompose [ex and] H5. decompose [ex and] H3.
eexists. split.
assert (type x0 = type s) as E by (inversion H4; rewrite type_add_time in *; assumption).
repeat (rewr_assumption;simpl).
assert (type x = type s) as E2 by auto using subtype_type.
rewr_assumption. rewrite tyeqb_refl. reflexivity.
constructor. reflexivity. simpl. inversion H4. inversion H1.
destruct s, x, x0. simpl in *. rewrite tmax_lub_iff.
unfold tadd', tsub'. split; auto using tadd_tsub_tle.
Qed.
Open Scope Z.
Inductive tile : TimeB -> TimeI -> Prop :=
| tile_top t : tile t TimeTop
| tile_time s t : tle s t -> tile s (Time' t).
Hint Constructors tile.
Lemma tileb_tile s t : tileb s t = true <-> tile s t.
Proof.
split;intros A.
- destruct t;auto. simpl in *. rewrite tleb_tle in A. auto.
- destruct t; simpl;auto. inversion A. subst.
rewrite <- tleb_tle in *. auto.
Qed.
Lemma tile_tsub_iadd t n x : tile t (iadd n x) -> tile (tsub' n t) x.
Proof.
intro L. destruct x. inversion L. subst. unfold tsub', tadd' in *.
constructor. auto using tadd_tsub_tle. constructor.
Qed.
Lemma tile_imin_l t x y : tile t (imin x y) -> tile t x.
Proof.
intro T. unfold imin in *.
cases (ileb x y) as L. assumption. destruct x, y;simpl in *;eauto.
rewrite tleb_tgt in L. inversion T. subst. constructor. eauto using tle_trans, tle_tlt.
inversion L.
Qed.
Lemma tile_imin_r t x y : tile t (imin x y) -> tile t y.
Proof.
intro T. unfold imin in *.
cases (ileb x y) as L; try assumption. destruct x, y;simpl in *;eauto.
rewrite tleb_tle in L. inversion T. subst. constructor. eauto using tle_trans.
inversion L.
Qed.
Lemma tile_imin_iadd s t x n : tile t (imin x (iadd n s)) -> tile (tsub' n t) s.
Proof.
intros T. eauto using tile_imin_r, tile_tsub_iadd.
Qed.
Theorem inferC_sound env c i tenv :
inferC env tenv c = Some i -> IsClosedCT c -> forall t, tile t i -> TiTyC env t c.
Proof.
generalize dependent env. generalize dependent i.
induction c; intros i env I C t0 E;simpl in *; option_inv_auto; inversion C;
try solve [eauto using inferE_sound |inversion E;auto].
- cases (tyeqb (type x) REAL && tileb (time x) x0) as TE;tryfalse.
rewrite Bool.andb_true_iff in TE.
destruct TE as [TE1 TE2]. rewrite tyeqb_iff in TE1.
rewrite tileb_tile in TE2.
destruct x. simpl in *. subst. inversion H3. subst.
apply inferE_sound in H0.
cases (tleb t0 ti) as TL. rewrite tleb_tle in TL.
eapply IHc in H2;try eassumption.
econstructor;eauto.
rewrite tleb_tgt in TL.
eapply IHc in H2; try apply E.
eapply causal_scale in H2. eassumption.
apply tle_refl. apply TiTyE_open' with (t:=REAL@ti);eauto.
constructor. reflexivity. simpl. auto using tle_tlt. inversion C. auto.
- subst; eapply IHc in H0; eauto using tile_tsub_iadd.
- constructor; eauto using tile_imin_l, tile_imin_r.
- cases (tyeqb (type x) BOOL && tleb (time x) (Time 0)) as B;tryfalse.
rewrite Bool.andb_true_iff in B. destruct B as [B1 B2].
rewrite tleb_tle, tyeqb_iff in *.
option_inv_auto.
constructor. eapply TiTyE_open' with (t:=x);eauto using inferE_sound.
eapply IHc1; eauto using tile_imin_l.
eapply IHc2; eauto using tile_imin_iadd.
Qed.
Lemma tile_iadd_tsub t n x : tile (tsub' n t) x -> tile t (iadd n x).
Proof.
intro L. destruct x. inversion L. subst. unfold tsub', tadd' in *.
constructor. unfold tadd'. auto using tsub_tadd_tle. constructor.
Qed.
Lemma tile_imin t x y : tile t x -> tile t y -> tile t (imin x y).
Proof.
intros X Y. unfold imin. cases (ileb x y) as L;assumption.
Qed.
Lemma imin_top_l t : imin TimeTop t = t.
Proof. unfold imin. destruct t;reflexivity. Qed.
Lemma imin_top_r t : imin t TimeTop = t.
Proof. unfold imin. destruct t;reflexivity. Qed.
Theorem inferC_complete env c t tenv: TiTyC env t c -> exists i, inferC env tenv c = Some i /\ tile t i.
Proof.
generalize dependent env. generalize dependent t.
induction c; intros t0 env T;simpl in *; option_inv_auto;inversion T;subst;eauto.
- apply inferE_complete in H3. decompose [ex and] H3. subst.
eapply TiTyC_open in H4.
apply IHc in H4. decompose [ex and] H4.
eexists. split.
repeat (rewr_assumption;simpl). reflexivity. eassumption.
eauto using all_subtype_refl. apply tle_refl.
- apply IHc in H5. decompose [ex and] H5.
apply inferE_complete in H4. decompose [ex and] H4.
repeat (rewr_assumption;simpl). inversion H6. simpl in *.
rewrite H. rewrite tyeqb_refl.
assert (tile (time x0) x) as E by (inversion H2;eauto).
subst. rewrite <- tileb_tile in E. rewrite E.
simpl. eexists. split. reflexivity.
inversion H2;eauto.
- apply IHc in H2. decompose [ex and] H2. simpl. rewr_assumption. simpl. autounfold.
eexists. split. reflexivity. auto using tile_iadd_tsub.
- apply IHc1 in H3. decompose [ex and] H3. apply IHc2 in H4. decompose [ex and] H4.
repeat rewr_assumption. simpl. autounfold.
eexists. split. reflexivity. auto using tile_imin.
- apply IHc1 in H6. decompose [ex and] H6. apply IHc2 in H7. decompose [ex and] H7.
apply inferE_complete in H4. decompose [ex and] H4.
repeat rewr_assumption. simpl. autounfold.
eexists. split. inversion H8. rewrite <- tleb_tle in H9. simpl in *.
repeat rewr_assumption. rewrite tyeqb_refl. simpl. reflexivity.
inversion H1; subst. rewrite imin_top_l. auto using tile_iadd_tsub.
inversion H3; subst. simpl. rewrite imin_top_r. assumption.
simpl. unfold imin. cases (ileb (Time' t) (Time' (tadd' d t1))).
assumption. simpl. constructor. unfold tadd', tsub' in *.
auto using tsub_tadd_tle.
Qed.
Definition has_type (tenv : TEnv) (c : Contr) : bool :=
match inferC nil tenv c with
| Some _ => true
| None => false
end.
Definition select_time t := match t with
| TimeTop => Time 0
| Time' t => t
end.
Lemma select_time_tile t : tile (select_time t) t.
Proof.
destruct t; simpl; constructor. apply tle_refl.
Qed.
Corollary has_type_causal c tenv :
has_type tenv c = true -> IsClosedCT c -> causal c tenv.
Proof.
unfold has_type. intros. cases (inferC [] tenv c) as T;tryfalse.
eauto using inferC_sound,select_time_tile, TiTyC_causal.
Qed.
|
/*
-----------------------------------------------------------------------------
General Sound
-----------------------------------------------------------------------------
18.08.2018 Reworked first verilog version
19.08.2018 Produce proper signed output
20.08.2018 Use external SDR/DDR RAM for page 2 and up
21.05.2020 Use external SDR/DDR RAM for all ROM/RAM
CPU: Z80 @ 28MHz
ROM: 32K
RAM: up to 4096KB
INT: 37.5KHz
#xxBB Command register - регистр команд, доступный для записи
#xxBB Status register - регистр состояния, доступный для чтения
bit 7 флаг данных
bit <6:1> Не определен
bit 0 флаг команд. Этот регистр позволяет определить состояние GS, в частности можно ли прочитать или записать очередной байт данных, или подать очередную команду, и т.п.
#xxB3 Data register - регистр данных, доступный для записи. В этот регистр Спектрум записывает данные, например, это могут быть аргументы команд.
#xxB3 Output register - регистр вывода, доступный для чтения. Из этого регистра Спектрум читает данные, идущие от GS
Внутренние порта:
#xx00 "расширенная память" - регистр доступный для записи
bit <3:0> переключают страницы по 32Kb, страница 0 - ПЗУ
bit <7:0> не используются
порты 1 - 5 "обеспечивают связь с SPECTRUM'ом"
#xx01 чтение команды General Sound'ом
bit <7:0> код команды
#xx02 чтение данных General Sound'ом
bit <7:0> данные
#xx03 запись данных General Sound'ом для SPECTRUM'a
bit <7:0> данные
#xx04 чтение слова состояния General Sound'ом
bit 0 флаг команд
bit 7 флаг данных
#xx05 сбрасывает бит D0 (флаг команд) слова состояния
порты 6 - 9 "регулировка громкости" в каналах 1 - 4
#xx06 "регулировка громкости" в канале 1
bit <5:0> громкость
bit <7:6> не используются
#xx07 "регулировка громкости" в канале 2
bit <5:0> громкость
bit <7:6> не используются
#xx08 "регулировка громкости" в канале 3
bit <5:0> громкость
bit <7:6> не используются
#xx09 "регулировка громкости" в канале 4
bit <5:0> громкость
bit <7:6> не используются
#xx0A устанавливает бит 7 слова состояния не равным биту 0 порта #xx00
#xx0B устанавливает бит 0 слова состояния равным биту 5 порта #xx06
Распределение памяти
#0000 - #3FFF - первые 16Kb ПЗУ
#4000 - #7FFF - первые 16Kb первой страницы ОЗУ
#8000 - #FFFF - листаемые страницы по 32Kb
страница 0 - ПЗУ,
страница 1 - первая страница ОЗУ
страницы 2... ОЗУ
Данные в каналы заносятся при чтении процессором ОЗУ по адресам #6000 - #7FFF автоматически.
*/
module gs
(
input RESET,
input CLK,
input CE_N,
input CE_P,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
output [20:0] MEM_ADDR,
output [7:0] MEM_DI,
input [7:0] MEM_DO,
output MEM_RD,
output MEM_WR,
input MEM_WAIT,
output [14:0] OUTL,
output [14:0] OUTR
);
parameter INT_DIV = 291;
// port #xxBB : #xxB3
assign DO = A ? {bit7, 6'b111111, bit0} : port_03;
// CPU
reg int_n;
wire cpu_m1_n;
wire cpu_mreq_n;
wire cpu_iorq_n;
wire cpu_rfsh_n;
wire cpu_rd_n;
wire cpu_wr_n;
wire [15:0] cpu_a_bus;
wire [7:0] cpu_do_bus;
T80pa cpu
(
.RESET_n(~RESET),
.CLK(CLK),
.CEN_n(CE_N),
.CEN_p(CE_P),
.INT_n(int_n),
.M1_n(cpu_m1_n),
.MREQ_n(cpu_mreq_n),
.RFSH_n(cpu_rfsh_n),
.IORQ_n(cpu_iorq_n),
.RD_n(cpu_rd_n),
.WR_n(cpu_wr_n),
.A(cpu_a_bus),
.DO(cpu_do_bus),
.DI(cpu_di_bus)
);
wire CE = CE_P;
// INT#
always @(posedge CLK) begin
reg [9:0] cnt;
if (RESET) begin
cnt <= 0;
int_n <= 1;
end else if(CE) begin
cnt <= cnt + 1'b1;
if (cnt == INT_DIV) begin // 37.48kHz
cnt <= 0;
int_n <= 0;
end
end
if (~cpu_iorq_n & ~cpu_m1_n) int_n <= 1;
end
reg bit7;
reg bit0;
always @(posedge CLK) begin
if (~cpu_iorq_n & cpu_m1_n) begin
case(cpu_a_bus[3:0])
'h2: bit7 <= 0;
'h3: bit7 <= 1;
'h5: bit0 <= 0;
'hA: bit7 <= ~port_00[0];
'hB: bit0 <= port_09[5];
endcase
end
else if (~CS_n) begin
if (~A & ~RD_n) bit7 <= 0;
if (~A & ~WR_n) bit7 <= 1;
if ( A & ~WR_n) bit0 <= 1;
end
end
reg [7:0] port_BB;
reg [7:0] port_B3;
always @(posedge CLK) begin
if (RESET) begin
port_BB <= 0;
port_B3 <= 0;
end
else if (~CS_n && ~WR_n) begin
if(A) port_BB <= DI;
else port_B3 <= DI;
end
end
reg [5:0] port_00;
reg [7:0] port_03;
reg signed [6:0] port_06, port_07, port_08, port_09;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
always @(posedge CLK) begin
if (RESET) begin
port_00 <= 0;
port_03 <= 0;
end
else begin
if (~cpu_iorq_n & ~cpu_wr_n) begin
case(cpu_a_bus[3:0])
0: port_00 <= cpu_do_bus[5:0];
3: port_03 <= cpu_do_bus;
6: port_06 <= cpu_do_bus[5:0];
7: port_07 <= cpu_do_bus[5:0];
8: port_08 <= cpu_do_bus[5:0];
9: port_09 <= cpu_do_bus[5:0];
endcase
end
if (mem_rd && cpu_a_bus[15:13] == 3 && ~MEM_WAIT) begin
case(cpu_a_bus[9:8])
0: ch_a <= {~MEM_DO[7],MEM_DO[6:0]};
1: ch_b <= {~MEM_DO[7],MEM_DO[6:0]};
2: ch_c <= {~MEM_DO[7],MEM_DO[6:0]};
3: ch_d <= {~MEM_DO[7],MEM_DO[6:0]};
endcase
end
end
end
wire [7:0] cpu_di_bus =
mem_rd ? MEM_DO :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} :
8'hFF;
wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr;
wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n;
wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14];
assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]};
assign MEM_RD = mem_rd;
assign MEM_WR = mem_wr;
assign MEM_DI = cpu_do_bus;
reg signed [14:0] out_a,out_b,out_c,out_d;
always @(posedge CLK) begin
if(CE) begin
out_a <= ch_a * port_06;
out_b <= ch_b * port_07;
out_c <= ch_c * port_08;
out_d <= ch_d * port_09;
end
end
reg signed [14:0] outl, outr;
always @(posedge CLK) begin
if(CE) begin
outl <= out_a + out_b;
outr <= out_c + out_d;
end
end
assign OUTL = outl;
assign OUTR = outr;
endmodule
|
//Alan Achtenberg
//Lab 7
//Part 3
module DFF (q,qbar,clock,data);
output q, qbar;
input clock, data;
wire databar, clockbar;
wire master_nand1, master_nand2;
wire nand1, nand2;
wire master_q, master_qbar;
not #1 (databar, data);
not #1 (clockbar, clock);
//Master
nand #1 m1(master_nand1,clock, data);
nand #1 m2(master_nand2,clock, databar);
nand #1 m3(master_qbar,master_nand2,master_q);
nand #1 m4(master_q,master_nand1,master_qbar);
//Slave
nand #1 s1(nand1,clockbar, master_q);
nand #1 s2(nand2,clockbar, master_qbar);
nand #1 s3(qbar,nand2,q);
nand #1 s4(q,nand1,qbar);
endmodule
module m555(clock);
parameter InitDelay = 10, Ton = 50, Toff = 50;
output clock;
reg clock;
initial begin
#InitDelay clock = 1;
end
always begin
#Ton clock = ~clock;
#Toff clock = ~clock;
end
endmodule
module testD(q, qbar, clock, data);
input q, qbar, clock;
output data;
reg data;
initial begin
$monitor ($time, " q = %d, qbar = %d, clock = %d, data = %d", q, qbar, clock, data);
data = 0;
#25
data = 1;
#100
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
$finish; /* $finish simulation after 100 time simulation units */
end
endmodule
module testBenchD;
wire clock, q, qbar, data;
m555 clk(clock);
DFF dff(q, qbar, clock, data);
testD td(q, qbar, clock, data);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_1_V
`define SKY130_FD_SC_MS__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V
|
//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module next_hop_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9_altera ram0 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[7:0] ),
.rden ( en ),
.wren ( we[0] ),
.q ( data_out[7:0] )
);
defparam ram0.altsyncram_component.init_file = "nh_ram0.mif";
RAMB16_S9_altera ram1 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[15:8] ),
.rden ( en ),
.wren ( we[1] ),
.q ( data_out[15:8] )
);
defparam ram1.altsyncram_component.init_file = "nh_ram1.mif";
RAMB16_S9_altera ram2 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[23:16] ),
.rden ( en ),
.wren ( we[2] ),
.q ( data_out[23:16] )
);
defparam ram2.altsyncram_component.init_file = "nh_ram2.mif";
RAMB16_S9_altera ram3 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[31:24] ),
.rden ( en ),
.wren ( we[3] ),
.q ( data_out[31:24] )
);
defparam ram3.altsyncram_component.init_file = "nh_ram3.mif";
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: city.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module city (
address,
clock,
q);
input [14:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./audio_mifs/city.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./audio_mifs/city.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./audio_mifs/city.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL city.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_6_V
`define SKY130_FD_SC_LP__DECAPKAPWR_6_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog wrapper for decapkapwr with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_6 (
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decapkapwr base (
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_6 ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_6_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p0(/*AUTOARG*/
// Outputs
pcx_spc0_grant_bufp0_pa, spc0_pcx_req_bufp0_pq,
spc0_pcx_atom_bufp0_pq, spc1_pcx_req_bufp0_pq,
spc1_pcx_atom_bufp0_pq,
// Inputs
spc0_pcx_req_bufpt_pq_l, spc0_pcx_atom_bufpt_pq_l,
spc1_pcx_req_bufpt_pq_l, spc1_pcx_atom_bufpt_pq_l,
pcx_spc0_grant_bufp1_pa_l
);
output [4:0] pcx_spc0_grant_bufp0_pa;
output [4:0] spc0_pcx_req_bufp0_pq;
output spc0_pcx_atom_bufp0_pq;
output [4:0] spc1_pcx_req_bufp0_pq;
output spc1_pcx_atom_bufp0_pq;
input [4:0] spc0_pcx_req_bufpt_pq_l;
input spc0_pcx_atom_bufpt_pq_l;
input [4:0] spc1_pcx_req_bufpt_pq_l;
input spc1_pcx_atom_bufpt_pq_l;
input [4:0] pcx_spc0_grant_bufp1_pa_l;
assign spc0_pcx_req_bufp0_pq[4:0] = ~spc0_pcx_req_bufpt_pq_l[4:0];
assign spc0_pcx_atom_bufp0_pq = ~spc0_pcx_atom_bufpt_pq_l;
assign pcx_spc0_grant_bufp0_pa = ~pcx_spc0_grant_bufp1_pa_l;
assign spc1_pcx_req_bufp0_pq[4:0] = ~spc1_pcx_req_bufpt_pq_l[4:0];
assign spc1_pcx_atom_bufp0_pq = ~spc1_pcx_atom_bufpt_pq_l;
endmodule
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: [email protected]
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module spi_dma_ext
(
// General
clk_i,
rst_i,
// SPI Interface
spi_clk_o,
spi_ss_o,
spi_mosi_o,
spi_miso_i,
// Memory interface
mem_address_o,
mem_data_o,
mem_data_i,
mem_rd_o,
mem_wr_o,
// Control
xfer_count_i,
xfer_address_i,
xfer_start_i,
xfer_rx_only_i,
xfer_done_o,
xfer_busy_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter MEM_ADDR_WIDTH = 18;
parameter XFER_COUNT_WIDTH = 32;
parameter SPI_CLK_DIV = 4;
parameter TRANSFER_WIDTH = 8;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
// General
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
// SPI Interface
output spi_clk_o /*verilator public*/;
output spi_ss_o /*verilator public*/;
output spi_mosi_o /*verilator public*/;
input spi_miso_i /*verilator public*/;
// Memory interface
output[MEM_ADDR_WIDTH - 1:0] mem_address_o /*verilator public*/;
output[TRANSFER_WIDTH - 1:0] mem_data_o /*verilator public*/;
input[TRANSFER_WIDTH - 1:0] mem_data_i /*verilator public*/;
output mem_rd_o /*verilator public*/;
output mem_wr_o /*verilator public*/;
// Control
input[XFER_COUNT_WIDTH - 1:0] xfer_count_i /*verilator public*/;
input[MEM_ADDR_WIDTH - 1:0] xfer_address_i /*verilator public*/;
input xfer_start_i /*verilator public*/;
input xfer_rx_only_i /*verilator public*/;
output xfer_done_o /*verilator public*/;
output xfer_busy_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire spim_start;
wire spim_done;
wire spim_busy;
wire [TRANSFER_WIDTH - 1:0] spim_data_tx;
wire [TRANSFER_WIDTH - 1:0] spim_data_rx;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// SPI Master
spi_master
#(
.CLK_DIV(SPI_CLK_DIV),
.TRANSFER_WIDTH(TRANSFER_WIDTH)
)
U1_SPIM
(
// Clocking / Reset
.clk_i(clk_i),
.rst_i(rst_i),
// Control & Status
.start_i(spim_start),
.done_o(spim_done),
.busy_o(spim_busy),
// Data
.data_i(spim_data_tx),
.data_o(spim_data_rx),
// SPI interface
.spi_clk_o(spi_clk_o),
.spi_ss_o(spi_ss_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
// DMA controller
spi_ctrl
#(
.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
.XFER_COUNT_WIDTH(XFER_COUNT_WIDTH),
.TRANSFER_WIDTH(TRANSFER_WIDTH)
)
U2_SPI_DMA
(
// General
.clk_i(clk_i),
.rst_i(rst_i),
// Memory interface
.mem_address_o(mem_address_o),
.mem_data_o(mem_data_o),
.mem_data_i(mem_data_i),
.mem_rd_o(mem_rd_o),
.mem_wr_o(mem_wr_o),
// SPI Access
.spi_start_o(spim_start),
.spi_done_i(spim_done),
.spi_busy_i(spim_busy),
.spi_data_i(spim_data_rx),
.spi_data_o(spim_data_tx),
// Control
.xfer_count_i(xfer_count_i),
.xfer_address_i(xfer_address_i),
.xfer_start_i(xfer_start_i),
.xfer_rx_only_i(xfer_rx_only_i),
.xfer_done_o(xfer_done_o),
.xfer_busy_o(xfer_busy_o)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: txfifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module txfifo #(
parameter DATA_WIDTH=64,
parameter LOCAL_FIFO_DEPTH=256
) (
clock,
aclr,
data,
rdreq,
wrreq,
almost_full,
almost_empty,
empty,
full,
q,
usedw);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam FIFO_ADDR_WIDTH=log2(LOCAL_FIFO_DEPTH);
input clock;
input aclr;
input [DATA_WIDTH-1:0] data;
input rdreq;
input wrreq;
output almost_full;
output almost_empty;
output empty;
output full;
output [DATA_WIDTH-1:0] q;
output [FIFO_ADDR_WIDTH-1:0] usedw;
wire [FIFO_ADDR_WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [DATA_WIDTH-1:0] sub_wire3;
wire sub_wire4;
wire [FIFO_ADDR_WIDTH-1:0] usedw = sub_wire0[FIFO_ADDR_WIDTH-1:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [DATA_WIDTH-1:0] q = sub_wire3[DATA_WIDTH-1:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.aclr (aclr),
.almost_empty (almost_empty),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 3*LOCAL_FIFO_DEPTH/4,
scfifo_component.almost_empty_value = 1*LOCAL_FIFO_DEPTH/4,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = LOCAL_FIFO_DEPTH,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = FIFO_ADDR_WIDTH,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_2_V
`define SKY130_FD_SC_HDLL__AND4B_2_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_2 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_2 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_2_V
|
// This file is part of Verilog-65c816.
//
// Copyright 2017 by FPGApeeps
//
// Verilog-65c816 is free software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// Verilog-65c816 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with Verilog-65c816. If not, see <http://www.gnu.org/licenses/>.
`include "src/inc/cpu_defines.v"
`include "src/inc/cpu_enums.v"
// A possible change to the ports would be to use a shared wire for input
// AND output data. This could be a good idea for connecting to memory
// outside the FPGA.
module Cpu(input wire clk, input wire rst, input wire enable,
input wire [`CPU_DATA_MSB_POS:0] data_in,
// If we're requesting a read or write
output reg req_rdwr,
// If req_rdwr == 1, then are we requesting a read or a write?
//
// Here would be a good place to use an enum if this project were
// written in SystemVerilog.
//
// Values used with this output reg are `ENUM__CPU_WH_RDWR__READ and
// `ENUM__CPU_WH_RDWR__WRITE, which are defined "src/inc/cpu_enums.v"
output reg which_rdwr,
// Address we want to read from or write to
//output reg [`CPU_FAR_ADDR_MSB_POS:0] addr,
// Just try a 16-bit address space for now. We will switch to a 24-bit
// address space later.
output reg [`CPU_ACTUAL_ADDR_MSB_POS:0] addr,
output reg [`CPU_DATA_MSB_POS:0] data_out);
// Parameters
`include "src/inc/generic_params.v"
`include "src/inc/cpu_state_params.v"
`include "src/inc/cpu_opcode_params.v"
// Buffer MSB positions
parameter __state_msb_pos = `_ENUM_MP__CPU_STATE;
// which_rdwr stuff
parameter __wh_rdwr__read = `ENUM__CPU_WH_RDWR__READ;
parameter __wh_rdwr__write = `ENUM__CPU_WH_RDWR__WRITE;
`include "src/inc/cpu_reg_params.v"
`include "src/inc/cpu_debug_params.v"
// Internal buffers
//reg [__buf_byte_msb_pos:0] __data_in_buf;
reg [__buf_byte_msb_pos:0] __opcode;
// State machine thing
reg [__state_msb_pos:0] __state;
reg [__state_msb_pos + 1:0] __state_enum_counter;
// Use the X macro pretending we have enums here.
`define X(enum_reg) enum_reg,
reg [__state_msb_pos:0]
`_LIST_OF_CPU_STATES
// This is necessary because of how the X macro is set up (having a
// comma at the end)
__st__dummy;
`undef X
initial
begin
__state_enum_counter = 0;
// Use the X macro pretending we have enums here.
//`define X(enum_reg) set_state_enum_reg(enum_reg);
`define X(enum_reg) \
enum_reg = __state_enum_counter; \
__state_enum_counter = __state_enum_counter + 1;
`_LIST_OF_CPU_STATES
`undef X
end
// Processor Registers
// The accumulator
reg [__reg_c_msb_pos:0] __reg_c;
// __reg_x is NOT a regular expression!
reg [__reg_index_big_msb_pos:0] __reg_x, __reg_y;
// Stack Pointer (SP)
reg [__reg_sp_msb_pos:0] __reg_sp;
// Program Counter (PC)
reg [__reg_pc_msb_pos:0] __reg_pc;
// Tasks
task prep_load;
input [`CPU_ACTUAL_ADDR_MSB_POS:0] some_addr;
begin
req_rdwr <= __true;
which_rdwr <= __wh_rdwr__read;
addr <= some_addr;
end
endtask
task prep_store;
input [`CPU_ACTUAL_ADDR_MSB_POS:0] some_addr;
input [`CPU_DATA_MSB_POS:0] some_data_out;
begin
req_rdwr <= __true;
which_rdwr <= __wh_rdwr__write;
addr <= some_addr;
data_out <= some_data_out;
end
endtask
// Completely unnecessary task
task disab_req_rdwr;
req_rdwr <= __false;
endtask
task debug_show_state;
case (__state)
`define X(enum_reg) \
enum_reg: \
begin \
$display(`"enum_reg\n\n`"); \
end
`_LIST_OF_CPU_STATES
`undef X
default:
begin
$display("Final __state\n");
end
endcase
endtask
always @ (posedge clk)
begin
if (!rst)
begin
debug_show_state();
if (enable)
begin
$display("CPU ENabled!");
end
else // if (!enable)
begin
$display("CPU DISabled!");
end
end
// Reset signal
if (rst)
begin
// Clear outputs
//req_rdwr <= __false;
disab_req_rdwr();
//which_rdwr <= __wh_rdwr__read;
addr <= `_CPU_ACTUAL_ADDR_WIDTH'h0000;
data_out <= `_CPU_DATA_WIDTH'h00;
// Clear internal buffers
//__data_in_buf <= 0;
__opcode <= 0;
// Clear processor registers
{__reg_c, __reg_x, __reg_y, __reg_sp, __reg_pc} <= 0;
//__reg_c <= 0;
//__reg_x <= 2;
//__reg_y <= 5;
//__reg_sp <= 16'h9001;
//__reg_pc <= 16'h2329;
// Initial state
__state <= __st_emu__reset;
end
else if (enable)
begin
case (__state)
__st_emu__reset:
begin
//__state <= __st_testing__test_load_0;
__state <= __st_testing__test_store_0;
end
// Test an 8-bit load
__st_testing__test_load_0:
begin
__state <= __state + 1;
prep_load(__debug_addr_0);
end
// Test another 8-bit load
__st_testing__test_load_1:
begin
__state <= __state + 1;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_c[__reg_b_msb_pos:__reg_b_lsb_pos] <= data_in;
prep_load(__debug_addr_1);
end
__st_testing__test_load_2:
begin
__state <= __state + 1;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_c[__reg_a_msb_pos:__reg_a_lsb_pos] <= data_in;
//disab_req_rdwr();
prep_load(__debug_addr_2);
end
__st_testing__test_load_3:
begin
__state <= __st_testing__done;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_x[__reg_index_hi_msb_pos:__reg_index_hi_lsb_pos]
<= data_in;
disab_req_rdwr();
end
// Test an 8-bit store
__st_testing__test_store_0:
begin
__state <= __state + 1;
prep_store(__debug_addr_0, `_CPU_DATA_WIDTH'h45);
end
__st_testing__test_store_1:
begin
__state <= __state + 1;
//__state <= __st_testing__test_load_0;
prep_store(__debug_addr_1, `_CPU_DATA_WIDTH'h87);
end
__st_testing__test_store_2:
begin
__state <= __st_testing__test_load_0;
prep_store(__debug_addr_2, `_CPU_DATA_WIDTH'haa);
end
default:
begin
$display("%h, %h\t\t%h, %h\t\t%h, %h, %h, %h, %h\n",
data_in, data_out,
__state, __opcode,
__reg_c, __reg_x, __reg_y, __reg_sp, __reg_pc);
$finish;
end
endcase
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 13:30:12 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[7:0],probe21[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
input [7:0]probe20;
input [7:0]probe21;
endmodule
|
//-----------------------------------------------------------------------------
// system_v_axi4s_vid_out_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "v_axi4s_vid_out_v2_01_a" *)
module system_v_axi4s_vid_out_0_wrapper
(
aclk,
rst,
aresetn,
aclken,
s_axis_video_tdata,
s_axis_video_tvalid,
s_axis_video_tready,
s_axis_video_tuser,
s_axis_video_tlast,
video_out_clk,
video_de,
video_vsync,
video_hsync,
video_vblank,
video_hblank,
video_data,
vtg_vsync,
vtg_hsync,
vtg_vblank,
vtg_hblank,
vtg_act_vid,
vtg_ce,
vtg_fsync,
locked,
wr_error,
empty
);
input aclk;
input rst;
input aresetn;
input aclken;
input [15:0] s_axis_video_tdata;
input s_axis_video_tvalid;
output s_axis_video_tready;
input s_axis_video_tuser;
input s_axis_video_tlast;
input video_out_clk;
output video_de;
output video_vsync;
output video_hsync;
output video_vblank;
output video_hblank;
output [15:0] video_data;
input vtg_vsync;
input vtg_hsync;
input vtg_vblank;
input vtg_hblank;
input vtg_act_vid;
output vtg_ce;
output vtg_fsync;
output locked;
output wr_error;
output empty;
v_axi4s_vid_out
#(
.C_S_AXIS_VIDEO_DATA_WIDTH ( 8 ),
.C_S_AXIS_VIDEO_FORMAT ( 0 ),
.VID_OUT_DATA_WIDTH ( 16 ),
.C_S_AXIS_VIDEO_TDATA_WIDTH ( 16 ),
.RAM_ADDR_BITS ( 10 ),
.HYSTERESIS_LEVEL ( 12 ),
.FILL_GUARDBAND ( 2 ),
.VTG_MASTER_SLAVE ( 1 )
)
v_axi4s_vid_out_0 (
.aclk ( aclk ),
.rst ( rst ),
.aresetn ( aresetn ),
.aclken ( aclken ),
.s_axis_video_tdata ( s_axis_video_tdata ),
.s_axis_video_tvalid ( s_axis_video_tvalid ),
.s_axis_video_tready ( s_axis_video_tready ),
.s_axis_video_tuser ( s_axis_video_tuser ),
.s_axis_video_tlast ( s_axis_video_tlast ),
.video_out_clk ( video_out_clk ),
.video_de ( video_de ),
.video_vsync ( video_vsync ),
.video_hsync ( video_hsync ),
.video_vblank ( video_vblank ),
.video_hblank ( video_hblank ),
.video_data ( video_data ),
.vtg_vsync ( vtg_vsync ),
.vtg_hsync ( vtg_hsync ),
.vtg_vblank ( vtg_vblank ),
.vtg_hblank ( vtg_hblank ),
.vtg_act_vid ( vtg_act_vid ),
.vtg_ce ( vtg_ce ),
.vtg_fsync ( vtg_fsync ),
.locked ( locked ),
.wr_error ( wr_error ),
.empty ( empty )
);
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Clock source selection. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer mclk_counter;
always @ (posedge mclk)
mclk_counter <= mclk_counter+1;
integer r5_counter;
always @ (posedge r5[0] or negedge r5[0])
r5_counter <= r5_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef WATCHDOG
// WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
//--------------------------------------------------------
@(r15 === 16'h0001);
@(posedge r5[0]);
@(negedge mclk);
mclk_counter = 0;
r5_counter = 0;
repeat(1024) @(negedge mclk);
if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
`ifdef SMCLK_DIVIDER
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
`endif
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef LFXT_DOMAIN
if (r5_counter !== 0) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 =====");
`endif
`else
`ifdef SMCLK_DIVIDER
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 =====");
`endif
`endif
`endif
`else
if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 =====");
`endif
// WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
//--------------------------------------------------------
@(r15 === 16'h1001);
@(negedge r5[0]);
@(negedge mclk);
mclk_counter = 0;
r5_counter = 0;
repeat(7815) @(negedge mclk);
if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef LFXT_DOMAIN
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 =====");
`else
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 =====");
`endif
`else
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 =====");
`endif
`endif
`else
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 =====");
`endif
`else
tb_skip_finish("| (the Watchdog is not included) |");
`endif
stimulus_done = 1;
end
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import String.
Require Import List.
Require Import Sorting.
Require Import Eqdep_dec.
Require Import Bool.
Require Import EquivDec.
Require Import Morphisms.
Require Import Utils.
Require Import BrandRelation.
Require Import ForeignType.
Section RType.
(* Possibly non-canonical relational types *)
Inductive record_kind : Set
:=
(** open records allow width subtyping: they can have additional fields not in the type description *)
| Open
(** closed records do not allow width subtyping. They must have exactly the specified fields. *)
| Closed.
Global Instance record_kind_eqdec : EqDec record_kind eq.
intros x y.
change ({x=y} + {x<>y}).
decide equality.
Defined.
Section rtypes₀.
(** Syntax of types. Note that there is no guarantee yet that records are well formed. i.e., having distinct fields. *)
Context {ftype:foreign_type}.
Unset Elimination Schemes.
Inductive rtype₀ : Set :=
| Bottom₀ : rtype₀
| Top₀ : rtype₀
| Unit₀ : rtype₀
| Nat₀ : rtype₀
| Float₀ : rtype₀
| Bool₀ : rtype₀
| String₀ : rtype₀
| Coll₀ (r:rtype₀) : rtype₀
| Rec₀ (k:record_kind) (srl:list (string* rtype₀)) : rtype₀
| Either₀ (tl tr:rtype₀) : rtype₀
| Arrow₀ (tin tout : rtype₀) : rtype₀
| Brand₀ : brands -> rtype₀
| Foreign₀ (ft:foreign_type_type) : rtype₀.
Set Elimination Schemes.
Notation "⊥₀" := Bottom₀.
Notation "⊤₀" := Top₀.
Definition rtype₀_rect (P : rtype₀ -> Type)
(ftop : P ⊤₀)
(fbottom : P ⊥₀)
(funit : P Unit₀)
(fnat : P Nat₀)
(ffloat : P Float₀)
(fbool : P Bool₀)
(fstring : P String₀)
(fcol : forall t : rtype₀, P t -> P (Coll₀ t))
(frec : forall (k:record_kind) (r : list (string * rtype₀)), Forallt (fun ab => P (snd ab)) r -> P (Rec₀ k r))
(feither : forall l r, P l -> P r -> P (Either₀ l r))
(farrow : forall tin tout, P tin -> P tout -> P (Arrow₀ tin tout))
(fbrand : forall b, P (Brand₀ b))
(fforeign : forall ft, P (Foreign₀ ft))
:=
fix F (t : rtype₀) : P t :=
match t as t0 return (P t0) with
| ⊤₀ => ftop
| ⊥₀ => fbottom
| Unit₀ => funit
| Nat₀ => fnat
| Float₀ => ffloat
| Bool₀ => fbool
| String₀ => fstring
| Coll₀ x => fcol x (F x)
| Rec₀ k x => frec k x ((fix Frec (r : list (string * rtype₀)) : Forallt (fun ab => P (snd ab)) r :=
match r as c0 with
| nil => Forallt_nil _
| cons sd c0 => @Forallt_cons _ (fun ab => P (snd ab)) sd c0 (F (snd sd)) (Frec c0)
end) x)
| Either₀ l r => feither l r (F l) (F r)
| Arrow₀ tin tout => farrow tin tout (F tin) (F tout)
| Brand₀ b => fbrand b
| Foreign₀ ft => fforeign ft
end.
Definition rtype₀_ind (P : rtype₀ -> Prop)
(ftop : P ⊤₀)
(fbottom : P ⊥₀)
(funit : P Unit₀)
(fnat : P Nat₀)
(ffloat : P Float₀)
(fbool : P Bool₀)
(fstring : P String₀)
(fcol : forall t : rtype₀, P t -> P (Coll₀ t))
(frec : forall (k:record_kind) (r : list (string * rtype₀)), Forall (fun ab => P (snd ab)) r -> P (Rec₀ k r))
(feither : forall l r, P l -> P r -> P (Either₀ l r))
(farrow : forall tin tout, P tin -> P tout -> P (Arrow₀ tin tout))
(fbrand : forall b, P (Brand₀ b))
(fforeign : forall ft, P (Foreign₀ ft))
:=
fix F (t : rtype₀) : P t :=
match t as t0 return (P t0) with
| ⊤₀ => ftop
| ⊥₀ => fbottom
| Unit₀ => funit
| Nat₀ => fnat
| Float₀ => ffloat
| Bool₀ => fbool
| String₀ => fstring
| Coll₀ x => fcol x (F x)
| Rec₀ k x => frec k x ((fix Frec (r : list (string * rtype₀)) : Forall (fun ab => P (snd ab)) r :=
match r as c0 with
| nil => Forall_nil _
| cons sd c0 => @Forall_cons _ (fun ab => P (snd ab)) sd c0 (F (snd sd)) (Frec c0)
end) x)
| Either₀ l r => feither l r (F l) (F r)
| Arrow₀ tin tout => farrow tin tout (F tin) (F tout)
| Brand₀ b => fbrand b
| Foreign₀ ft => fforeign ft
end.
Definition rtype₀_rec (P:rtype₀->Set) := rtype₀_rect P.
(* Equality is decidable for rtype₀ *)
Global Instance rtype₀_eqdec : EqDec rtype₀ eq.
Proof.
red; unfold equiv, complement.
induction x; destruct y;
try solve[right; inversion 1]; try solve[left; trivial].
- (* Col *)
destruct (IHx y) as [e|e].
+ left; f_equal; trivial.
+ right; intro n. apply e;inversion n; trivial.
- (* Rec *)
destruct (k == k0); unfold equiv, complement in *.
+ destruct (list_Forallt_eq_dec r srl); subst; auto.
* apply (forallt_impl H).
apply forallt_weaken; clear; intros.
destruct x; destruct y; simpl in *.
apply pair_eq_dec; eauto.
apply string_dec.
* right; inversion 1; auto.
+ right; inversion 1; auto.
- destruct (IHx1 y1); unfold equiv, complement in *.
+ destruct (IHx2 y2); unfold equiv, complement in *.
* left; subst; trivial.
* right; inversion 1; eauto.
+ right; inversion 1; eauto.
- destruct (IHx1 y1); unfold equiv, complement in *.
+ destruct (IHx2 y2); unfold equiv, complement in *.
* left; subst; trivial.
* right; inversion 1; eauto.
+ right; inversion 1; eauto.
- destruct (b == b0); unfold equiv, complement in *;
[left | right]; congruence.
- destruct (foreign_type_dec ft ft0).
+ left; f_equal; apply e.
+ right; inversion 1; congruence.
Defined.
End rtypes₀.
Notation "⊥₀" := Bottom₀.
Notation "⊤₀" := Top₀.
Section well_formed_rtypes.
Context {ftype:foreign_type}.
Context {br:brand_relation}.
Fixpoint wf_rtype₀ (τ:rtype₀): bool
:= match τ with
| Coll₀ τ' => wf_rtype₀ τ'
| Rec₀ oc srl => is_list_sorted ODT_lt_dec (domain srl)
&& forallb (fun ab => wf_rtype₀ (snd ab)) srl
| Either₀ τl τr => wf_rtype₀ τl && wf_rtype₀ τr
| Arrow₀ τin τout => wf_rtype₀ τin && wf_rtype₀ τout
| Brand₀ b => if is_canon_brands_dec brand_relation_brands b then true else false
| _ => true
end.
Definition rtype : Set := {τ₀:rtype₀ | wf_rtype₀ τ₀ = true}.
Lemma wf_rtype₀_ext {τ₀:rtype₀} (pf1 pf2:wf_rtype₀ τ₀ = true) : pf1 = pf2.
Proof.
apply UIP_dec; apply bool_dec.
Defined.
Lemma rtype_ext {τ₀} (wfτ1 wfτ2:wf_rtype₀ τ₀ = true) :
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) τ₀ wfτ1) =
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) τ₀ wfτ2).
Proof.
f_equal. apply wf_rtype₀_ext.
Defined.
Lemma rtype_fequal {τ₁ τ₂:rtype} : proj1_sig τ₁ = proj1_sig τ₂ -> τ₁ = τ₂.
Proof.
destruct τ₁; destruct τ₂; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma rtype_nequal {τ₁ τ₂:rtype} : τ₁ <> τ₂ -> proj1_sig τ₁ <> proj1_sig τ₂.
Proof.
intros a b.
apply a. apply rtype_fequal; trivial.
Qed.
Lemma map_rtype_fequal r1 r2 :
map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) r1 =
map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) r2 ->
r1 = r2.
Proof.
revert r2.
induction r1; destruct r2; simpl; trivial; try discriminate.
inversion 1.
f_equal; auto.
destruct a; destruct p; simpl in *; subst. f_equal.
apply rtype_fequal; auto.
Qed.
Lemma map_rtype_single_rec_fequal a τ r :
(a, proj1_sig τ)::nil =
map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) r ->
((a, τ)::nil) = r.
Proof.
assert ((a, proj1_sig τ)::nil =
map (fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) ((a, τ)::nil)) by reflexivity.
rewrite H.
apply map_rtype_fequal.
Qed.
Global Instance rtype_eq_dec : EqDec rtype eq.
Proof.
red; unfold equiv, complement.
intros [x₀ xwf] [y₀ ywf].
destruct (x₀ == y₀); unfold equiv, complement in *.
- left. apply rtype_fequal; simpl; trivial.
- right; congruence.
Defined.
(** Lifted versions of the type constructors *)
(** This is the main type system, and always carries a proofs that the records are well formed *)
Program Definition Bottom : rtype := Bottom₀.
Program Definition Top : rtype := Top₀.
Program Definition Unit : rtype := Unit₀.
Program Definition Nat : rtype := Nat₀.
Program Definition Float : rtype := Float₀.
Program Definition Bool : rtype := Bool₀.
Program Definition String : rtype := String₀.
Definition Coll (τ:rtype): rtype :=
exist _ (Coll₀ (proj1_sig τ)) (proj2_sig τ).
Program Definition Either (τl τr:rtype) : rtype :=
exist _ (Either₀ (proj1_sig τl) (proj1_sig τr)) _.
Next Obligation.
rewrite (proj2_sig τl), (proj2_sig τr).
reflexivity.
Defined.
Program Definition Arrow (τl τr:rtype) : rtype :=
exist _ (Arrow₀ (proj1_sig τl) (proj1_sig τr)) _.
Next Obligation.
rewrite (proj2_sig τl), (proj2_sig τr).
reflexivity.
Defined.
Program Definition Foreign (ft:foreign_type_type) : rtype
:= Foreign₀ ft.
Program Definition Rec
(k:record_kind)
(srl:list (string* rtype))
(pf_sorted:is_list_sorted ODT_lt_dec (domain srl) = true) : rtype
:= Rec₀ k (map (fun x => (fst x, proj1_sig (snd x))) srl).
Next Obligation.
unfold domain in *.
rewrite map_map; simpl.
rewrite (map_eq (g:=fst)) by (rewrite Forall_forall; trivial).
rewrite andb_true_iff; split.
- apply pf_sorted.
- rewrite forallb_map; simpl.
rewrite forallb_forall.
intros [? [??]] ?; simpl; trivial.
Defined.
Program Definition Brand b : rtype := Brand₀ (canon_brands brand_relation_brands b).
Next Obligation.
match_destr.
elim n.
apply canon_brands_is_canon_brands.
Defined.
Global Instance Brand_equiv_proper :
Proper (equiv_brands brand_relation_brands ==> eq) (Brand).
Proof.
unfold Proper, respectful; intros.
apply rtype_fequal; simpl.
rewrite H; trivial.
Qed.
Notation "⊥" := Bottom.
Notation "⊤" := Top.
Definition Option τ := Either τ Unit.
(* (derived) induction principle for rtype. Between the "smart"
constructors, and this eliminator, there should be no need to
operate on the underlying rtype₀. Unfortunately, we do lose
explicit pattern matching (it can still be written as a call to
this induction principle) *)
Hint Constructors Forallt : qcert.
Theorem rtype_rect (P : rtype -> Type)
(ftop : P ⊤)
(fbottom : P ⊥)
(funit : P Unit)
(fnat : P Nat)
(ffloat : P Float)
(fbool : P Bool)
(fstring : P String)
(fcol : forall t : rtype, P t -> P (Coll t))
(frec : forall (k:record_kind) (srl : list (string * rtype))
(pf:is_list_sorted ODT_lt_dec (domain srl) = true),
Forallt (fun ab => P (snd ab)) srl -> P (Rec k srl pf))
(feither : forall (τl τr:rtype), P τl -> P τr -> P (Either τl τr))
(farrow : forall (τin τout:rtype), P τin -> P τout -> P (Arrow τin τout))
(fbrand : forall b, P (Brand b))
(fforeign : forall ft, P (Foreign ft))
:
forall (τ:rtype), P τ.
Proof.
destruct τ as [τ₀ wfτ].
revert wfτ. (* ftop fbottom funit fnat fbool fstring fcol frec. *)
unfold Top, Bottom, Unit, Nat, Float, Bool, String, Coll, Rec, Either, Arrow in *.
(* Ltac r_ext := solve [erewrite (rtype_ext); eauto]. *)
induction τ₀; simpl; intros.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- specialize (fcol _ (IHτ₀ wfτ)).
erewrite rtype_ext; eauto.
- revert frec wfτ X; clear. intros frec.
intros.
assert (srlpf:{srl: list (string * rtype) | (map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) srl) = r}).
+ clear P X frec. rewrite andb_true_iff, forallb_forall in wfτ.
destruct wfτ as [iss fb].
revert iss fb.
induction r; intros.
* exists nil; simpl; trivial.
* rewrite domain_cons, is_list_sorted_cons in iss.
destruct iss as [iss isa].
destruct IHr as [srl srlpf]; intuition.
specialize (fb a).
simpl in fb; intuition.
exists ((fst a ,(exist _ (snd a) H1))::srl).
destruct a; simpl. congruence.
+ destruct srlpf as [srl srleq].
assert (dreq:domain srl = domain r).
rewrite <- srleq; simpl; unfold domain.
rewrite map_map. simpl. apply map_eq; apply Forall_forall; auto.
assert (pfs:is_list_sorted ODT_lt_dec (domain srl) = true).
rewrite dreq; rewrite andb_true_iff in wfτ; intuition.
assert (pff:Forallt (fun ab : string * rtype => P (snd ab)) srl).
revert X. rewrite <- srleq. clear.
induction srl; simpl; eauto with qcert.
destruct a; destruct r; simpl.
inversion 1; subst; eauto with qcert.
specialize (frec k srl pfs pff).
destruct srleq.
erewrite (rtype_ext); eapply frec.
- generalize wfτ; intros.
rewrite andb_true_iff in wfτ. destruct wfτ as [wfτ1 wfτ2].
specialize (feither _ _ (IHτ₀1 wfτ1) (IHτ₀2 wfτ2)).
erewrite rtype_ext; eauto.
- generalize wfτ; intros.
rewrite andb_true_iff in wfτ. destruct wfτ as [wfτ1 wfτ2].
specialize (farrow _ _ (IHτ₀1 wfτ1) (IHτ₀2 wfτ2)).
erewrite rtype_ext; eauto.
- revert fbrand b wfτ. clear; intros.
assert (isc:is_canon_brands brand_relation_brands b)
by match_destr_in wfτ.
replace (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Brand₀ b) wfτ) with (Brand b); trivial.
apply rtype_fequal; simpl.
rewrite is_canon_brands_canon_brands; trivial.
- specialize (fforeign ft).
erewrite rtype_ext.
eauto.
Defined.
Theorem rtype_ind (P : rtype -> Prop)
(ftop : P ⊤)
(fbottom : P ⊥)
(funit : P Unit)
(fnat : P Nat)
(ffloat : P Float)
(fbool : P Bool)
(fstring : P String)
(fcol : forall t : rtype, P t -> P (Coll t))
(frec : forall (k:record_kind) (srl : list (string * rtype))
(pf:is_list_sorted ODT_lt_dec (domain srl) = true),
Forall (fun ab => P (snd ab)) srl -> P (Rec k srl pf))
(feither : forall (τl τr:rtype), P τl -> P τr -> P (Either τl τr))
(farrow : forall (τin τout:rtype), P τin -> P τout -> P (Arrow τin τout))
(fbrand : forall b, P (Brand b))
(fforeign : forall ft, P (Foreign ft)) :
forall (τ:rtype), P τ.
Proof.
destruct τ as [τ₀ wfτ].
revert wfτ. (* ftop fbottom funit fnat fbool fstring fcol frec. *)
unfold Top, Bottom, Unit, Nat, Float, Bool, String, Coll, Rec in *.
(* Ltac r_ext := solve [erewrite (rtype_ext); eauto]. *)
induction τ₀; simpl; intros.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- erewrite rtype_ext; eauto.
- specialize (fcol _ (IHτ₀ wfτ)).
erewrite rtype_ext; eauto.
- revert frec wfτ H; clear. intros frec.
intros.
assert (srlpf:{srl: list (string * rtype) | (map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) srl) = r}).
+ clear P H frec. rewrite andb_true_iff, forallb_forall in wfτ.
destruct wfτ as [iss fb].
revert iss fb.
induction r; intros.
* exists nil; simpl; trivial.
* rewrite domain_cons, is_list_sorted_cons in iss.
destruct iss as [iss isa].
destruct IHr as [srl srlpf]; intuition.
specialize (fb a).
simpl in fb; intuition.
exists ((fst a ,(exist _ (snd a) H1))::srl).
destruct a; simpl. congruence.
+ destruct srlpf as [srl srleq].
assert (dreq:domain srl = domain r).
rewrite <- srleq; simpl; unfold domain.
rewrite map_map. simpl. apply map_eq; apply Forall_forall; auto.
assert (pfs:is_list_sorted ODT_lt_dec (domain srl) = true).
rewrite dreq; rewrite andb_true_iff in wfτ; intuition.
assert (pff:Forall (fun ab : string * rtype => P (snd ab)) srl).
revert H. rewrite <- srleq. clear.
induction srl; simpl; eauto.
destruct a; destruct r; simpl.
inversion 1; subst; eauto.
specialize (frec k srl pfs pff).
destruct srleq.
erewrite (rtype_ext); eapply frec.
- generalize wfτ; intros.
rewrite andb_true_iff in wfτ. destruct wfτ as [wfτ1 wfτ2].
specialize (feither _ _ (IHτ₀1 wfτ1) (IHτ₀2 wfτ2)).
erewrite rtype_ext; eauto.
- generalize wfτ; intros.
rewrite andb_true_iff in wfτ. destruct wfτ as [wfτ1 wfτ2].
specialize (farrow _ _ (IHτ₀1 wfτ1) (IHτ₀2 wfτ2)).
erewrite rtype_ext; eauto.
- revert fbrand b wfτ. clear; intros.
assert (isc:is_canon_brands brand_relation_brands b)
by match_destr_in wfτ.
replace (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Brand₀ b) wfτ) with (Brand b); trivial.
apply rtype_fequal; simpl.
rewrite is_canon_brands_canon_brands; trivial.
- specialize (fforeign ft).
erewrite rtype_ext.
eauto.
Defined.
Definition rtype_rec (P:rtype->Set) := rtype_rect P.
Lemma wf_rtype₀_kind_irrel k₁ k₂ l :
wf_rtype₀ (Rec₀ k₁ l) = wf_rtype₀ (Rec₀ k₂ l).
Proof.
reflexivity.
Qed.
Lemma wf_rtype₀_Brand₀ b :
wf_rtype₀ (Brand₀ b) = true ->
is_canon_brands brand_relation_brands b.
Proof.
simpl.
match_destr.
Qed.
Lemma brand_ext b pf : exist _ (Brand₀ b) pf = Brand b.
Proof.
apply rtype_fequal; simpl in *.
match_destr_in pf.
rewrite is_canon_brands_canon_brands; trivial.
Qed.
Lemma wf_rtype₀_cons_tail {k} {a r} :
wf_rtype₀ (Rec₀ k (a::r)) = true ->
wf_rtype₀ (Rec₀ k r) = true.
Proof.
simpl.
repeat rewrite andb_true_iff.
intuition.
destruct (domain r); intuition.
destruct (StringOrder.lt_dec (fst a) s); intuition.
Defined.
Lemma wf_rtype₀_cons_lt {k s r srl s' r'} :
wf_rtype₀ (Rec₀ k ((s, r) :: srl)) = true ->
lookup string_dec srl s' = Some r' ->
ODT_lt s s'.
Proof.
unfold wf_rtype₀. rewrite andb_true_iff.
intros [isl _].
apply is_list_sorted_Sorted_iff in isl.
apply Sorted_StronglySorted in isl; [|eapply StringOrder.lt_strorder].
simpl in isl. inversion isl. subst.
rewrite Forall_forall in H2.
specialize (H2 s').
intros los.
apply lookup_in in los. apply in_dom in los.
simpl.
auto.
Qed.
Lemma wf_rtype₀_cons_nin {k s r srl} :
wf_rtype₀ (Rec₀ k ((s, r) :: srl)) = true -> lookup string_dec srl s = None.
Proof.
unfold wf_rtype₀. rewrite andb_true_iff.
intros [isl _].
apply is_list_sorted_NoDup in isl; [|eapply StringOrder.lt_strorder].
inversion isl; subst.
eapply lookup_nin_none; auto.
Defined.
Lemma wf_rtype₀_cons_wf {k s r srl} :
wf_rtype₀ (Rec₀ k ((s, r) :: srl)) = true ->
wf_rtype₀ r = true.
Proof.
simpl; repeat rewrite andb_true_iff; intuition.
Qed.
End well_formed_rtypes.
Notation "⊥" := Bottom.
Notation "⊤" := Top.
Ltac equalizer :=
repeat match goal with
| [H:(@eq rtype₀ (proj1_sig _) (proj1_sig _)) |- _] => apply rtype_fequal in H
| [H: map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) _ =
map
(fun x' : string * {τ₀' : rtype₀ | wf_rtype₀ τ₀' = true} =>
(fst x', proj1_sig (snd x'))) _ |- _] => apply map_rtype_fequal in H
end.
Lemma to_Rec {ftype:foreign_type} {br:brand_relation} k l pf :
exists pf2,
exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true)
(Rec₀
k (map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) l)) pf
= Rec k l pf2.
Proof.
unfold Rec.
generalize pf. intros pf'.
simpl in pf. rewrite andb_true_iff in pf.
unfold domain in pf; rewrite map_map in pf; simpl in pf.
destruct pf as [isl ?].
exists isl.
apply rtype_ext.
Qed.
Lemma from_Rec₀ {ftype:foreign_type} {br:brand_relation} {k} (l:list (string * rtype₀)) (pf : wf_rtype₀ (Rec₀ k l) = true) :
{l' | exists pf',
l =
(map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) l')
/\ Rec k l' pf' = exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Rec₀ k l) pf}.
Proof.
revert pf. induction l; unfold Rec; intros pf.
- exists nil; simpl. exists eq_refl; intuition. apply rtype_ext.
- generalize (wf_rtype₀_cons_tail pf); intros pf'.
destruct (IHl pf') as [l' l'H].
destruct a.
exists ((s, (exist _ r (wf_rtype₀_cons_wf pf)))::l').
destruct l'H as [pf'' [eq1 eq2]].
generalize pf; intros pf_.
simpl in pf. repeat rewrite andb_true_iff in pf.
destruct pf as [isl [wfr wfb]].
assert (pf'0 : is_list_sorted ODT_lt_dec
(domain
((s, exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) r wfr)
:: l')) = true).
rewrite domain_cons, is_list_sorted_cons. simpl; intuition.
subst. unfold domain in isl; rewrite map_map in isl.
simpl in isl.
rewrite (map_eq (g:=fst)) in isl by (rewrite Forall_forall; trivial).
unfold domain. destruct (map fst l'); intuition.
destruct (StringOrder.lt_dec s s0); intuition.
exists pf'0. subst; simpl. intuition.
apply rtype_ext.
Defined.
Lemma lookup_map_some {ftype:foreign_type} {br:brand_relation} rl2 s x :
lookup string_dec rl2 s = Some x <->
lookup string_dec
(map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) rl2) s = Some (proj1_sig x).
Proof.
induction rl2; simpl; [split; discriminate|].
destruct a; simpl.
destruct (string_dec s s0); auto.
subst.
split; inversion 1; subst; auto.
equalizer. subst; auto.
Qed.
Lemma lookup_map_some' {ftype:foreign_type} {br:brand_relation} rl2 s x pf :
lookup string_dec rl2 s = Some (exist _ x pf) <->
lookup string_dec
(map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) rl2) s = Some x.
Proof.
rewrite lookup_map_some; simpl; reflexivity.
Qed.
Lemma lookup_map_some_ex {ftype:foreign_type} {br:brand_relation}
(rl2 : list (string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true}))
(s : string) (x : rtype₀) :
(exists pf, lookup string_dec rl2 s =
Some (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x pf)) <->
lookup string_dec
(map
(fun x0 : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x0, proj1_sig (snd x0))) rl2) s = Some x.
Proof.
induction rl2; simpl; split.
- intros [??]; discriminate.
- discriminate.
- intros [??].
destruct a; simpl.
destruct (string_dec s s0); auto.
+ inversion H.
subst. simpl; trivial.
+ apply IHrl2. eauto.
- destruct a; simpl.
destruct (string_dec s s0); auto.
+ inversion 1.
subst. destruct s1. eauto.
+ apply IHrl2.
Qed.
Lemma lookup_map_none {ftype:foreign_type} {br:brand_relation} rl2 s :
lookup string_dec rl2 s = None <->
lookup string_dec
(map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) rl2) s = None.
Proof.
induction rl2; simpl; [intuition|].
destruct a; simpl.
destruct (string_dec s s0); subst; intuition discriminate.
Qed.
End RType.
Section recmaybe.
Context {ftype:foreign_type}.
Context {br:brand_relation}.
Definition RecMaybe (k:record_kind) (lsr:list (string*rtype)) : option rtype.
case_eq (is_list_sorted ODT_lt_dec (domain lsr)); intros pf.
- exact (Some (Rec k lsr pf)).
- exact None.
Defined.
Lemma RecMaybe_some_pf_helper (z:bool) τ f :
(if z as b
return
(z = b -> option rtype)
then
fun pf : z = true =>
Some (f pf)
else
fun _ : z = false => None)
eq_refl = Some τ ->
{pf : z = true |
τ = f pf}.
Proof.
destruct z; inversion 1; eauto.
Qed.
Lemma RecMaybe_some_pf {k τ₀ τ} :
RecMaybe k τ₀ = Some τ ->
{pf | τ = Rec k τ₀ pf}.
Proof.
unfold RecMaybe. intros eqs.
apply RecMaybe_some_pf_helper in eqs.
auto.
Qed.
Lemma RecMaybe_pf_some_helper (z:bool) f pf :
z = true ->
(if z as b
return
(z = b -> option rtype)
then
fun pf : z = true =>
f pf
else
fun _ : z = false => None)
eq_refl = f pf.
Proof.
destruct z; inversion 1; eauto.
f_equal. apply UIP_dec. apply bool_dec.
Qed.
Lemma RecMaybe_pf_some k l pf :
RecMaybe k l = Some (Rec k l pf).
Proof.
unfold RecMaybe.
rewrite (@RecMaybe_pf_some_helper _ _ pf); trivial.
Qed.
Lemma RecMaybe_nil k : RecMaybe k nil = Some (Rec k nil eq_refl).
Proof.
apply RecMaybe_pf_some.
Qed.
End recmaybe.
Section other.
Context {ftype:foreign_type}.
Context {br:brand_relation}.
Lemma Rec_inv {k k' x pf1 y pf2} : Rec k x pf1 = Rec k' y pf2 -> x = y.
Proof.
intros.
unfold Rec in H.
inversion H.
apply map_rtype_fequal; trivial.
Qed.
Lemma Rec_kind_inv {k k' x pf1 y pf2} : Rec k x pf1 = Rec k' y pf2 -> k = k'.
Proof.
intros.
inversion H.
trivial.
Qed.
Lemma Rec_pr_irrel k l1 pf1 pf2 :
Rec k l1 pf1 = Rec k l1 pf2.
Proof.
f_equal. apply UIP_dec; apply bool_dec.
Qed.
Lemma Rec_rewrite {l1 l2} k pf1 pf2 :
l1 = l2 ->
Rec k l1 pf1 = Rec k l2 pf2.
Proof.
intros eqs.
destruct eqs.
apply Rec_pr_irrel.
Qed.
Lemma Rec_kind_rewrite k1 k2 l pf :
k1 = k2 ->
Rec k1 l pf = Rec k2 l pf.
Proof.
congruence.
Qed.
Lemma Coll_right_inv (τ₁ τ₂:rtype) :
(proj1_sig τ₁) = Coll₀ (proj1_sig τ₂) <-> τ₁ = Coll τ₂.
Proof.
split.
intros.
- destruct τ₁; simpl in *.
destruct τ₂; simpl in *.
destruct x; try discriminate; simpl in *.
inversion H. subst.
clear H.
assert (Coll (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x0 e0)
= Coll (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x0 e)).
apply rtype_fequal. simpl. reflexivity.
rewrite H.
reflexivity.
- intros.
rewrite H. reflexivity.
Defined.
Lemma Coll_inside (τ₁:rtype) (τ₂₀:rtype₀) :
(proj1_sig τ₁) = Coll₀ τ₂₀ ->
exists τ₂:rtype, proj1_sig τ₂ = τ₂₀.
Proof.
intros.
destruct τ₁. simpl in *.
destruct x; try congruence. simpl in e.
exists (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x e).
simpl. inversion H; reflexivity.
Defined.
Lemma Coll_String_inside (τ₁:rtype) :
(proj1_sig τ₁) = Coll₀ String₀ ->
τ₁ = Coll String.
Proof.
intros; apply rtype_fequal; auto.
Defined.
Lemma map_rtype_nil x0:
map (fun x2 : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x2, proj1_sig (snd x2))) x0 = nil <-> x0 = nil.
Proof.
split; intros.
- induction x0; try reflexivity; simpl in *.
congruence.
- rewrite H; reflexivity.
Qed.
Lemma Rec₀_eq_proj1_Rec {τ k l} :
proj1_sig τ =
Rec₀
k (map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) l) ->
exists pf, τ = Rec k l pf.
Proof.
destruct τ; simpl; intros; subst.
apply to_Rec.
Qed.
Lemma Nat_canon pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) Nat₀ pf) = Nat.
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Float_canon pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) Float₀ pf) = Float.
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma String_canon pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) String₀ pf) = String.
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Coll_canon x pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Coll₀ x) pf) = Coll (exist _ x pf).
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Coll_String_canon pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Coll₀ String₀) pf) = Coll String.
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Brand_canon x pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Brand₀ x) pf) = Brand x.
Proof.
apply rtype_fequal.
simpl in *.
match_destr_in pf.
rewrite is_canon_brands_canon_brands; trivial.
Qed.
Lemma Foreign_canon ft pf:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Foreign₀ ft) pf) = Foreign ft.
Proof.
apply rtype_fequal.
simpl in *.
trivial.
Qed.
Lemma Either₀_wf_inv {l r} :
wf_rtype₀ (Either₀ l r) = true ->
wf_rtype₀ l = true /\ wf_rtype₀ r = true.
Proof.
simpl. rewrite andb_true_iff. trivial.
Qed.
Lemma Either_canon l r pf pfl pfr:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Either₀ l r) pf) = Either (exist _ l pfl) (exist _ r pfr).
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Either_canon_ex l r pf:
exists pfl pfr,
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Either₀ l r) pf) = Either (exist _ l pfl) (exist _ r pfr).
Proof.
simpl in pf. destruct (Either₀_wf_inv pf) as [pfl pfr].
exists pfl; exists pfr.
apply Either_canon.
Qed.
Lemma Arrow₀_wf_inv {l r} :
wf_rtype₀ (Arrow₀ l r) = true ->
wf_rtype₀ l = true /\ wf_rtype₀ r = true.
Proof.
simpl. rewrite andb_true_iff. trivial.
Qed.
Lemma Arrow_canon l r pf pfl pfr:
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Arrow₀ l r) pf) = Arrow (exist _ l pfl) (exist _ r pfr).
Proof.
apply rtype_fequal.
simpl; trivial.
Qed.
Lemma Arrow_canon_ex l r pf:
exists pfl pfr,
(exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) (Arrow₀ l r) pf) = Arrow (exist _ l pfl) (exist _ r pfr).
Proof.
simpl in pf. destruct (Arrow₀_wf_inv pf) as [pfl pfr].
exists pfl; exists pfr.
apply Arrow_canon.
Qed.
Lemma wf_rtype₀_Rec_In {k srl} :
wf_rtype₀ (Rec₀ k srl) = true ->
forall a b, In (a,b) srl -> wf_rtype₀ b = true.
Proof.
simpl; intros wf a b inn.
rewrite andb_true_iff in wf. destruct wf.
rewrite forallb_forall in H0.
apply (H0 _ inn).
Defined.
Lemma wf_rec_pf_sublist {B} {l l'} :
is_list_sorted ODT_lt_dec (@domain _ B l) = true ->
sublist l' l ->
is_list_sorted ODT_lt_dec (domain l') = true.
Proof.
intros ? sl.
eapply is_list_sorted_sublist; eauto 2.
apply sublist_domain; trivial.
Qed.
Lemma lift_Rec₀_injective {k₁ k₂ l1 l2} : lift (Rec₀ k₁) l1 = lift (Rec₀ k₂) l2 -> l1 = l2.
Proof.
destruct l1; destruct l2; simpl; trivial; inversion 1; trivial.
Qed.
Lemma some_lift_Rec₀ {k₁ k₂ x y} :
lift (Rec₀ k₁) x = Some (Rec₀ k₂ y) ->
x = Some y.
Proof.
intros eq. apply some_lift in eq. destruct eq; subst.
inversion e0; congruence.
Qed.
Lemma lift_Coll₀_injective {l1 l2} : lift Coll₀ l1 = lift Coll₀ l2 -> l1 = l2.
Proof.
intros; eapply lift_injective; eauto.
inversion 1; trivial.
Qed.
Lemma some_lift_Coll₀ {x y} :
lift Coll₀ x = Some (Coll₀ y) ->
x = Some y.
Proof.
intros eq. apply some_lift in eq. destruct eq; subst.
inversion e0; congruence.
Qed.
Lemma lift_Coll_injective {l1 l2} : lift Coll l1 = lift Coll l2 -> l1 = l2.
Proof.
intros; eapply lift_injective; eauto.
inversion 1; trivial.
apply rtype_fequal; trivial.
Qed.
Lemma some_lift_Coll {x y} :
lift Coll x = Some (Coll y) ->
x = Some y.
Proof.
intros eq. apply some_lift in eq. destruct eq; subst.
inversion e0. f_equal. apply rtype_fequal; congruence.
Qed.
Lemma lift_col₀_some_col₀ {x y} :
lift Coll₀ x = Some y ->
{z | y = Coll₀ z}.
Proof.
destruct x; simpl; inversion 1; eauto.
Qed.
Lemma lift_col_some_col {x y} :
lift Coll x = Some y ->
{z | y = Coll z}.
Proof.
destruct x; simpl; inversion 1; eauto.
Qed.
Lemma lift_rec₀_some_rec₀ {k x y} :
lift (Rec₀ k) x = Some y ->
{z | y = Rec₀ k z}.
Proof.
destruct x; simpl; inversion 1; eauto.
Qed.
Definition isTop (τ:rtype) : bool.
destruct τ. destruct x; [ | exact true | .. ]; exact false.
Defined.
Lemma istop τ : {τ = Top} + {isTop τ = false}.
Proof.
destruct τ using rtype_rect; intuition.
Qed.
End other.
Notation "⊥₀" := Bottom₀.
Notation "⊤₀" := Top₀.
Notation "a ~~>₀ b" := (Arrow₀ a b) (at level 99, right associativity).
Notation "⊥" := Bottom.
Notation "⊤" := Top.
Notation "a ~~> b" := (Arrow a b) (at level 99, right associativity).
Ltac rtype_equalizer :=
repeat match goal with
| [H:(@eq rtype₀ (proj1_sig _) (proj1_sig _)) |- _] => apply rtype_fequal in H
| [H: map
(fun x : string * {τ₀ : rtype₀ | wf_rtype₀ τ₀ = true} =>
(fst x, proj1_sig (snd x))) _ =
map
(fun x' : string * {τ₀' : rtype₀ | wf_rtype₀ τ₀' = true} =>
(fst x', proj1_sig (snd x'))) _ |- _] => apply map_rtype_fequal in H
end.
Ltac r_ext := solve [erewrite (rtype_ext); eauto].
Ltac rtype_lift_simpler :=
match goal with
| [ |- lift ?f ?x = Some (?f ?y)] => apply (lift_some y); [|reflexivity]
| [ |- lift ?f ?x = None] => apply lift_none
| [H:lift ?f ?x = None |- _] => apply none_lift in H
| [H: lift (Rec₀ _) ?l1 = Some (Rec₀ _ ?l2) |- _ ] => apply some_lift_Rec₀ in H
| [H: lift (Rec₀ _) ?l1 = lift (Rec₀ _) ?l2 |- _ ] => apply lift_Rec₀_injective in H
| [H: lift Coll₀ ?l1 = Some (Coll₀ ?l2) |- _ ] => apply some_lift_Coll₀ in H
| [H: lift Coll₀ ?l1 = lift Coll₀ ?l2 |- _ ] => apply lift_Coll₀_injective in H
| [H: lift Coll ?l1 = Some (Coll ?l2) |- _ ] => apply some_lift_Coll in H
| [H: lift Coll ?l1 = lift Coll ?l2 |- _ ] => apply lift_Coll_injective in H
end.
(** Cases tactic for use with the derived rtypeRectt induction principle *)
Tactic Notation "rtype_rect_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Top"%string
| Case_aux c "Bottom"%string
| Case_aux c "Unit"%string
| Case_aux c "Nat"%string
| Case_aux c "Float"%string
| Case_aux c "Bool"%string
| Case_aux c "String"%string
| Case_aux c "Coll"%string
| Case_aux c "Rec"%string
| Case_aux c "Either"%string
| Case_aux c "Arrow"%string
| Case_aux c "Brand"%string
| Case_aux c "Foreign"%string
].
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2B_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_BLACKBOX_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// TX side of flow control -- when other side sends PAUSE, we wait
module flow_ctrl_tx
(input rst,
input tx_clk,
//host processor
input tx_pause_en,
// From MAC_rx_ctrl
input [15:0] pause_quanta,
input pause_quanta_val,
// MAC_tx_ctrl
output pause_apply,
input paused);
// ******************************************************************************
// Inhibit our TX from transmitting because they sent us a PAUSE frame
// ******************************************************************************
// Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
// as big as 16 bits, so 22 bits are needed for the counter
reg [15+6:0] pause_quanta_counter;
reg pqval_d1, pqval_d2;
always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
always @(posedge tx_clk) pqval_d2 <= pqval_d1;
always @ (posedge tx_clk or posedge rst)
if (rst)
pause_quanta_counter <= 0;
else if (pqval_d1 & ~pqval_d2)
pause_quanta_counter <= {pause_quanta, 6'b0};
else if((pause_quanta_counter!=0) & paused)
pause_quanta_counter <= pause_quanta_counter - 1;
assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
endmodule // flow_ctrl
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Nov 01 14:23:49 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30, probe31)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[7:0],probe31[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [7:0]probe30;
input [7:0]probe31;
endmodule
|
//`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:25 12/09/2014
// Design Name: cpu
// Module Name: /home/administrator/Documents/Xilinx/RiscCpu/test_cpu.v
// Project Name: RiscCpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cpu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
/*module test_cpu;
// Inputs
reg clk;
reg reset;
// Outputs
wire halt;
wire rd;
wire wr;
wire [12:0] addr;
// Bidirs
wire [7:0] data;
// Instantiate the Unit Under Test (UUT)
cpu uut (
.clk(clk),
.reset(reset),
.halt(halt),
.rd(rd),
.wr(wr),
.addr(addr),
.data(data)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
*/
`timescale 1ns / 100ps
`define PERIOD 100 // matches clk_gen.v
module cputop;
reg reset_req,clock;
integer test;
reg [(3*8):0] mnemonic; //array that holds 3 8-bit ASCII characters
reg [12:0] PC_addr,IR_addr;
wire [7:0] data;
wire [12:0] addr;
wire rd,wr,halt,ram_sel,rom_sel;
//------------------------ cpu ?????????ROM?RAM?????--------------------------------------
cpu t_cpu (.clk(clock),.reset(reset_req),.halt(halt),.rd(rd),
.wr(wr),.addr(addr),.data(data));
ram t_ram (.addr(addr[9:0]),.read(rd),.write(wr),.ena(ram_sel),.data(data));
rom t_rom (.addr(addr),.read(rd),.ena(rom_sel),.data(data));
addr_decode t_addr_decode (.addr(addr),.ram_sel(ram_sel),.rom_sel(rom_sel));
//--------------------cpu ?????????ROM?RAM???????----------------------------------
initial
begin
clock=1;
//display time in nanoseconds
$timeformat ( -9, 1, " ns", 12);
display_debug_message;
sys_reset;
test1;
$stop;
test2;
$stop;
test3;
$stop;
end
task display_debug_message;
begin
$display("\n**************************************************");
$display("* THE FOLLOWING DEBUG TASK ARE AVAILABLE: *");
$display("* \"test1; \" to load the 1st diagnostic progran. *");
$display("* \"test2; \" to load the 2nd diagnostic program. *");
$display("* \"test3; \" to load the Fibonacci program. *");
$display("*****************************************************\n");
end
endtask
task test1;
begin
test = 0;
disable MONITOR;
$readmemb ("test1.pro", t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test1.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 1;
#14800 ;
sys_reset;
end
endtask
task test2;
begin
test = 0;
disable MONITOR;
$readmemb("test2.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test2.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 2;
#11600;
sys_reset;
end
endtask
task test3;
begin
test = 0;
disable MONITOR;
$readmemb("test3.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test3.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 3;
#94000;
sys_reset;
end
endtask
task sys_reset;
begin
reset_req = 0;
#(`PERIOD*0.7) reset_req = 1;
#(1.5*`PERIOD) reset_req = 0;
end
endtask
always @(test)
begin: MONITOR
case (test)
1: begin //display results when running test 1
$display("\n*** RUNNING CPUtest1 - The Basic CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- ---- ----- ----- ----- ");
while (test == 1)
@(t_cpu.m_adr.pc_addr)//fixed
if ((t_cpu.m_adr.pc_addr%2 == 1)&&(t_cpu.m_adr.fetch == 1))//fixed
begin
# 60 PC_addr <=t_cpu.m_adr.pc_addr -1 ;
IR_addr <=t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr,data );
//HERE DATA HAS BEEN CHANGED T-CPU-M-REGISTER.DATA
end
end
2: begin
$display("\n*** RUNNING CPUtest2 - The Advanced CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- --- ----- ----- ---- ");
while (test == 2)
@(t_cpu.m_adr.pc_addr)
if ((t_cpu.m_adr.pc_addr%2 == 1)
&& (t_cpu.m_adr.fetch == 1))
begin
# 60 PC_addr <= t_cpu.m_adr.pc_addr - 1 ;
IR_addr <= t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr, data );
end
end
3: begin
$display("\n*** RUNNING CPUtest3 - An Executable Program ***");
$display("*** This program should calculate the fibonacci ***");
$display("\n TIME FIBONACCI NUMBER");
$display( " --------- -----------------");
while (test == 3)
begin
wait ( t_cpu.m_alu.opcode == 3'h1) // display Fib. No. at end of program loop
$strobe("%t %d", $time,t_ram.ram[10'h2]);
wait ( t_cpu.m_alu.opcode != 3'h1);
end
end
endcase
end
//-------------------------------------------------------------------------
always @(posedge halt) //STOP when HALT instruction decoded
begin
#500
$display("\n*********************************************");
$display( "** A HALT INSTRUCTION WAS PROCESSED !!! **");
$display( "*********************************************\n");
end
always #(`PERIOD/2) clock=~clock;
always @(t_cpu.m_alu.opcode)
//get an ASCII mnemonic for each opcode
case(t_cpu.m_alu.opcode)
3'b000 : mnemonic ="HLT";
3'h1 : mnemonic = "SKZ";
3'h2 : mnemonic = "ADD";
3'h3 : mnemonic = "AND";
3'h4 : mnemonic = "XOR";
3'h5 : mnemonic = "LDA";
3'h6 : mnemonic = "STO";
3'h7 : mnemonic = "JMP";
default : mnemonic = "???";
endcase
endmodule
//------------------------------------------- cputop.v ????? -----------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A2111O_BEHAVIORAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_BEHAVIORAL_PP_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import
Bool ZAxioms ZMulOrder ZPow ZDivFloor ZSgnAbs ZParity NZLog.
(** Derived properties of bitwise operations *)
Module Type ZBitsProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZParityProp A B)
(Import D : ZSgnAbsProp A B)
(Import E : ZPowProp A B C D)
(Import F : ZDivProp A B D)
(Import G : NZLog2Prop A A A B E).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Ltac order_pos' := try apply abs_nonneg; order_pos.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> 0<=c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha (H,H'). rewrite <- (sub_simpl_r b c) at 2.
rewrite pow_add_r; trivial.
rewrite div_mul. reflexivity.
now apply pow_nonzero.
now apply le_0_sub.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> 0<=c -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb Hc H. rewrite (div_mod a b Hb) at 2.
rewrite H, add_0_r, pow_mul_l, mul_comm, div_mul. reflexivity.
now apply pow_nonzero.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2z (b:bool) := if b then 1 else 0.
Local Coercion b2z : bool >-> t.
Instance b2z_wd : Proper (Logic.eq ==> eq) b2z := _.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n : 0<=n ->
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
now apply testbit_odd_succ.
now apply testbit_even_succ.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : 0<=n -> a.[n] == (a / 2^n) mod 2.
Proof.
intro Hn. revert a. apply le_ind with (4:=Hn).
solve_proper.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
left. destruct b; split; simpl; order'.
clear n Hn. intros n Hn IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH by trivial. f_equiv.
rewrite pow_succ_r, <- div_div by order_pos. f_equiv.
apply div_unique with b; trivial.
left. destruct b; split; simpl; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n : 0<=n ->
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
intro Hn. exists (a mod 2^n). exists (a / 2^n / 2). split.
apply mod_pos_bound; order_pos.
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec' by trivial. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n, 0<=n ->
(a.[n] = true <-> (a / 2^n) mod 2 == 1).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n, 0<=n ->
(a.[n] = false <-> (a / 2^n) mod 2 == 0).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n, 0<=n ->
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n Hn.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2z] *)
Lemma b2z_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2z_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; split; simpl; order').
Qed.
Lemma add_b2z_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2z_inj.
rewrite testbit_spec' by order.
nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; split; simpl; order').
Qed.
Lemma b2z_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2z_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2z_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2z_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
0<=l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
assert (0<=n).
destruct (le_gt_cases 0 n) as [Hn|Hn]; trivial.
rewrite pow_neg_r in Hl by trivial. destruct Hl; order.
apply b2z_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h.
left; destruct a0; simpl; split; order'.
symmetry. apply div_unique with l.
now left.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n.
destruct (le_gt_cases 0 n).
apply testbit_false; trivial. nzsimpl; order_nz.
now apply testbit_neg_r.
Qed.
(** For negative numbers, we are actually doing two's complement *)
Lemma bits_opp : forall a n, 0<=n -> (-a).[n] = negb (P a).[n].
Proof.
intros a n Hn.
destruct (testbit_spec (-a) n Hn) as (l & h & Hl & EQ).
fold (b2z (-a).[n]) in EQ.
apply negb_sym.
apply testbit_unique with (2^n-l-1) (-h-1).
split.
apply lt_succ_r. rewrite sub_1_r, succ_pred. now apply lt_0_sub.
apply le_succ_l. rewrite sub_1_r, succ_pred. apply le_sub_le_add_r.
rewrite <- (add_0_r (2^n)) at 1. now apply add_le_mono_l.
rewrite <- add_sub_swap, sub_1_r. f_equiv.
apply opp_inj. rewrite opp_add_distr, opp_sub_distr.
rewrite (add_comm _ l), <- add_assoc.
rewrite EQ at 1. apply add_cancel_l.
rewrite <- opp_add_distr.
rewrite <- (mul_1_l (2^n)) at 2. rewrite <- mul_add_distr_r.
rewrite <- mul_opp_l.
f_equiv.
rewrite !opp_add_distr.
rewrite <- mul_opp_r.
rewrite opp_sub_distr, opp_involutive.
rewrite (add_comm h).
rewrite mul_add_distr_l.
rewrite !add_assoc.
apply add_cancel_r.
rewrite mul_1_r.
rewrite add_comm, add_assoc, !add_opp_r, sub_1_r, two_succ, pred_succ.
destruct (-a).[n]; simpl. now rewrite sub_0_r. now nzsimpl'.
Qed.
(** All bits of number (-1) are 1 *)
Lemma bits_m1 : forall n, 0<=n -> (-1).[n] = true.
Proof.
intros. now rewrite bits_opp, one_succ, pred_succ, bits_0.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb by order. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec' by order. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit of positive numbers *)
Lemma bit_log2 : forall a, 0<a -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' := log2_nonneg a).
destruct (log2_spec_alt a Ha) as (r & EQ & Hr).
rewrite EQ at 1.
rewrite testbit_true, add_comm by trivial.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small; trivial.
rewrite add_0_l. apply mod_small. split; order'.
Qed.
Lemma bits_above_log2 : forall a n, 0<=a -> log2 a < n ->
a.[n] = false.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 a). apply log2_nonneg. order'.
rewrite testbit_false by trivial.
rewrite div_small. nzsimpl; order'.
split. order. apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** For negative numbers, things are the other ways around:
log2 gives the highest zero bit (for numbers below -1).
*)
Lemma bit_log2_neg : forall a, a < -1 -> a.[log2 (P (-a))] = false.
Proof.
intros a Ha.
rewrite <- (opp_involutive a) at 1.
rewrite bits_opp.
apply negb_false_iff.
apply bit_log2.
apply opp_lt_mono in Ha. rewrite opp_involutive in Ha.
apply lt_succ_lt_pred. now rewrite <- one_succ.
apply log2_nonneg.
Qed.
Lemma bits_above_log2_neg : forall a n, a < 0 -> log2 (P (-a)) < n ->
a.[n] = true.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 (P (-a))). apply log2_nonneg. order'.
rewrite <- (opp_involutive a), bits_opp, negb_true_iff by trivial.
apply bits_above_log2; trivial.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
(** Accesing a high enough bit of a number gives its sign *)
Lemma bits_iff_nonneg : forall a n, log2 (abs a) < n ->
(0<=a <-> a.[n] = false).
Proof.
intros a n Hn. split; intros H.
rewrite abs_eq in Hn; trivial. now apply bits_above_log2.
destruct (le_gt_cases 0 a); trivial.
rewrite abs_neq in Hn by order.
rewrite bits_above_log2_neg in H; try easy.
apply le_lt_trans with (log2 (-a)); trivial.
apply log2_le_mono. apply le_pred_l.
Qed.
Lemma bits_iff_nonneg' : forall a,
0<=a <-> a.[S (log2 (abs a))] = false.
Proof.
intros. apply bits_iff_nonneg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_nonneg_ex : forall a,
0<=a <-> (exists k, forall m, k<m -> a.[m] = false).
Proof.
intros a. split.
intros Ha. exists (log2 a). intros m Hm. now apply bits_above_log2.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_nonneg', Hk, lt_succ_r.
apply (bits_iff_nonneg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg : forall a n, log2 (abs a) < n ->
(a<0 <-> a.[n] = true).
Proof.
intros a n Hn.
now rewrite lt_nge, <- not_false_iff_true, (bits_iff_nonneg a n).
Qed.
Lemma bits_iff_neg' : forall a, a<0 <-> a.[S (log2 (abs a))] = true.
Proof.
intros. apply bits_iff_neg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg_ex : forall a,
a<0 <-> (exists k, forall m, k<m -> a.[m] = true).
Proof.
intros a. split.
intros Ha. exists (log2 (P (-a))). intros m Hm. now apply bits_above_log2_neg.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_neg', Hk, lt_succ_r.
apply (bits_iff_neg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, 0<=n -> (a/2).[n] = a.[S n].
Proof.
intros a n Hn.
apply eq_true_iff_eq. rewrite 2 testbit_true by order_pos.
rewrite pow_succ_r by trivial.
now rewrite div_div by order_pos.
Qed.
Lemma div_pow2_bits : forall a n m, 0<=n -> 0<=m -> (a/2^n).[m] = a.[m+n].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m Hm. now nzsimpl.
clear n Hn. intros n Hn IH a m Hm. nzsimpl; trivial.
rewrite <- div_div by order_pos.
now rewrite IH, div2_bits by order_pos.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now rewrite <- div2_bits, mul_comm, div_mul by order'.
rewrite (testbit_neg_r a n Hn).
apply le_succ_l in Hn. le_elim Hn.
now rewrite testbit_neg_r.
now rewrite Hn, bit0_odd, odd_mul, odd_2.
Qed.
Lemma double_bits : forall a n, (2*a).[n] = a.[P n].
Proof.
intros a n. rewrite <- (succ_pred n) at 1. apply double_bits_succ.
Qed.
Lemma mul_pow2_bits_add : forall a n m, 0<=n -> (a*2^n).[n+m] = a.[m].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m. now nzsimpl.
clear n Hn. intros n Hn IH a m. nzsimpl; trivial.
rewrite mul_assoc, (mul_comm _ 2), <- mul_assoc.
now rewrite double_bits_succ.
Qed.
Lemma mul_pow2_bits : forall a n m, 0<=n -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (add_simpl_r m n) at 1. rewrite add_sub_swap, add_comm.
now apply mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n).
rewrite mul_pow2_bits by trivial.
apply testbit_neg_r. now apply lt_sub_0.
now rewrite pow_neg_r, mul_0_r, bits_0.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, 0<=n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m (Hn,H).
destruct (mod_pos_bound a (2^n)) as [LE LT]. order_pos.
le_elim LE.
apply bits_above_log2; try order.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
now rewrite <- LE, bits_0.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
destruct (le_gt_cases 0 m) as [Hm|Hm]; [|now rewrite !testbit_neg_r].
rewrite testbit_eqb; trivial.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r, succ_pred.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add; trivial.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb; trivial.
apply le_0_sub; order.
now apply lt_le_pred, lt_0_sub.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]]; trivial.
apply (bits_above_log2_neg a (S (log2 (P (-a))))) in Ha.
now rewrite H in Ha.
apply lt_succ_diag_r.
apply bit_log2 in Ha. now rewrite H in Ha.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
assert (AUX : forall n, 0<=n -> forall a b,
0<=a<2^n -> testbit a === testbit b -> a == b).
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
intros a b Ha H. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (destruct Ha; order).
rewrite Ha' in *.
symmetry. apply bits_inj_0.
intros m. now rewrite <- H, bits_0.
clear n Hn. intros n Hn IH a b (Ha,Ha') H.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
intros m.
destruct (le_gt_cases 0 m).
rewrite 2 div2_bits by trivial. apply H.
now rewrite 2 testbit_neg_r.
intros a b H.
destruct (le_gt_cases 0 a) as [Ha|Ha].
apply (AUX a); trivial. split; trivial.
apply pow_gt_lin_r; order'.
apply succ_inj, opp_inj.
assert (0 <= - S a).
apply opp_le_mono. now rewrite opp_involutive, opp_0, le_succ_l.
apply (AUX (-(S a))); trivial. split; trivial.
apply pow_gt_lin_r; order'.
intros m. destruct (le_gt_cases 0 m).
now rewrite 2 bits_opp, 2 pred_succ, H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
(** In fact, checking the bits at positive indexes is enough. *)
Lemma bits_inj' : forall a b,
(forall n, 0<=n -> a.[n] = b.[n]) -> a == b.
Proof.
intros a b H. apply bits_inj.
intros n. destruct (le_gt_cases 0 n).
now apply H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff' : forall a b, (forall n, 0<=n -> a.[n] = b.[n]) <-> a == b.
Proof.
split. apply bits_inj'. intros EQ n Hn; now rewrite EQ.
Qed.
Ltac bitwise := apply bits_inj'; intros ?m ?Hm; autorewrite with bitwise.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
(** The streams of bits that correspond to a numbers are
exactly the ones which are stationary after some point. *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, forall m, 0<=m -> f m = n.[m]) <->
(exists k, forall m, k<=m -> f m = f k)).
Proof.
intros f Hf. split.
intros (a,H).
destruct (le_gt_cases 0 a).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 a); order_pos.
exists (S (log2 (P (-a)))). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2_neg; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 (P (-a))); order_pos.
intros (k,Hk).
destruct (lt_ge_cases k 0) as [LT|LE].
case_eq (f 0); intros H0.
exists (-1). intros m Hm. rewrite bits_m1, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
exists 0. intros m Hm. rewrite bits_0, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
revert f Hf Hk. apply le_ind with (4:=LE).
(* compat : solve_proper fails here *)
apply proper_sym_impl_iff. exact eq_sym.
clear k LE. intros k k' Hk IH f Hf H. apply IH; trivial.
now setoid_rewrite Hk.
(* /compat *)
intros f Hf H0. destruct (f 0).
exists (-1). intros m Hm. now rewrite bits_m1, H0.
exists 0. intros m Hm. now rewrite bits_0, H0.
clear k LE. intros k LE IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m Hm.
le_elim Hm.
rewrite <- (succ_pred m), Hn, <- div2_bits.
rewrite mul_comm, div_add, b2z_div2, add_0_l; trivial. order'.
now rewrite <- lt_succ_r, succ_pred.
now rewrite <- lt_succ_r, succ_pred.
rewrite <- Hm.
symmetry. apply add_b2z_double_bit0.
Qed.
(** * Properties of shifts *)
(** First, a unified specification for [shiftl] : the [shiftl_spec]
below (combined with [testbit_neg_r]) is equivalent to
[shiftl_spec_low] and [shiftl_spec_high]. *)
Lemma shiftl_spec : forall a n m, 0<=m -> (a << n).[m] = a.[m-n].
Proof.
intros.
destruct (le_gt_cases n m).
now apply shiftl_spec_high.
rewrite shiftl_spec_low, testbit_neg_r; trivial. now apply lt_sub_0.
Qed.
(** A shiftl by a negative number is a shiftr, and vice-versa *)
Lemma shiftr_opp_r : forall a n, a >> (-n) == a << n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, add_opp_r.
Qed.
Lemma shiftl_opp_r : forall a n, a << (-n) == a >> n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, sub_opp_r.
Qed.
(** Shifts correspond to multiplication or division by a power of two *)
Lemma shiftr_div_pow2 : forall a n, 0<=n -> a >> n == a / 2^n.
Proof.
intros. bitwise. now rewrite shiftr_spec, div_pow2_bits.
Qed.
Lemma shiftr_mul_pow2 : forall a n, n<=0 -> a >> n == a * 2^(-n).
Proof.
intros. bitwise. rewrite shiftr_spec, mul_pow2_bits; trivial.
now rewrite sub_opp_r.
now apply opp_nonneg_nonpos.
Qed.
Lemma shiftl_mul_pow2 : forall a n, 0<=n -> a << n == a * 2^n.
Proof.
intros. bitwise. now rewrite shiftl_spec, mul_pow2_bits.
Qed.
Lemma shiftl_div_pow2 : forall a n, n<=0 -> a << n == a / 2^(-n).
Proof.
intros. bitwise. rewrite shiftl_spec, div_pow2_bits; trivial.
now rewrite add_opp_r.
now apply opp_nonneg_nonpos.
Qed.
(** Shifts are morphisms *)
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha n n' Hn.
destruct (le_ge_cases n 0) as [H|H]; assert (H':=H); rewrite Hn in H'.
now rewrite 2 shiftr_mul_pow2, Ha, Hn.
now rewrite 2 shiftr_div_pow2, Ha, Hn.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha n n' Hn. now rewrite <- 2 shiftr_opp_r, Ha, Hn.
Qed.
(** We could also have specified shiftl with an addition on the left. *)
Lemma shiftl_spec_alt : forall a n m, 0<=n -> (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits, add_simpl_r.
Qed.
(** Chaining several shifts. The only case for which
there isn't any simple expression is a true shiftr
followed by a true shiftl.
*)
Lemma shiftl_shiftl : forall a n m, 0<=n ->
(a << n) << m == a << (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 2 (shiftl_spec _ _ m) by trivial.
rewrite add_comm, sub_add_distr.
destruct (le_gt_cases 0 (m-p)) as [H|H].
now rewrite shiftl_spec.
rewrite 2 testbit_neg_r; trivial.
apply lt_sub_0. now apply lt_le_trans with 0.
Qed.
Lemma shiftr_shiftl_l : forall a n m, 0<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_shiftl, add_opp_r.
Qed.
Lemma shiftr_shiftl_r : forall a n m, 0<=n ->
(a << n) >> m == a >> (m-n).
Proof.
intros. now rewrite <- 2 shiftl_opp_r, shiftl_shiftl, opp_sub_distr, add_comm.
Qed.
Lemma shiftr_shiftr : forall a n m, 0<=m ->
(a >> n) >> m == a >> (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 3 shiftr_spec; trivial.
now rewrite (add_comm n p), add_assoc.
now apply add_nonneg_nonneg.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros n. destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
rewrite shiftl_div_pow2, div_1_l, pow_neg_r; try order.
apply pow_gt_1. order'. now apply opp_pos_neg.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2 by order. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. now rewrite <- shiftl_opp_r, opp_0, shiftl_0_r.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros.
destruct (le_ge_cases 0 n).
rewrite shiftl_mul_pow2 by trivial. now nzsimpl.
rewrite shiftl_div_pow2 by trivial.
rewrite <- opp_nonneg_nonpos in H. nzsimpl; order_nz.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_0_l.
Qed.
Lemma shiftl_eq_0_iff : forall a n, 0<=n -> (a << n == 0 <-> a == 0).
Proof.
intros a n Hn.
rewrite shiftl_mul_pow2 by trivial. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (lt_trichotomy a 0) as [LT|[EQ|LT]].
split.
intros [(H,_)|(H,H')]. order. generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]; order.
rewrite EQ. split. now left. intros _; left. split; order_pos.
split. intros [(H,H')|(H,H')]; right. split; trivial.
apply log2_lt_pow2; trivial.
generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]. order. left.
split. order. now apply log2_lt_pow2.
rewrite shiftr_mul_pow2 by order. rewrite eq_mul_0.
split; intros [H|H].
now left.
elim (pow_nonzero 2 (-n)); try apply opp_nonneg_nonpos; order'.
now left.
destruct H. generalize (log2_nonneg a); order.
Qed.
Lemma shiftr_eq_0 : forall a n, 0<=a -> log2 a < n -> a >> n == 0.
Proof.
intros a n Ha H. apply shiftr_eq_0_iff.
le_elim Ha. right. now split. now left.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl. order'.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1 << n).
Definition clearbit a n := ldiff a (1 << n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, 0<=n -> (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)).
now rewrite mul_pow2_bits, sub_diag, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n); [|now rewrite pow_neg_r, bits_0].
destruct (le_gt_cases n m).
rewrite <- (mul_1_l (2^n)), mul_pow2_bits; trivial.
rewrite <- (succ_pred (m-n)), <- div2_bits.
now rewrite div_small, bits_0 by (split; order').
rewrite <- lt_succ_r, succ_pred, lt_0_sub. order.
rewrite <- (mul_1_l (2^n)), mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, 0<=n -> (2^n).[m] = eqb n m.
Proof.
intros n m Hn. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true; order.
Qed.
Lemma setbit_eqb : forall a n m, 0<=n ->
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m, 0<=n ->
((setbit a n).[m] = true <-> n==m \/ a.[m] = true).
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, 0<=n -> (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff; trivial. now left.
Qed.
Lemma setbit_neq : forall a n m, 0<=n -> n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m Hn H. rewrite setbit_eqb; trivial.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros.
destruct (le_gt_cases 0 m); [| now rewrite 2 testbit_neg_r].
rewrite clearbit_spec', ldiff_spec. f_equal. f_equal.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now apply pow2_bits_eqb.
symmetry. rewrite pow_neg_r, bits_0, <- not_true_iff_false, eqb_eq; order.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lxor_spec.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, land_spec.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lor_spec.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, ldiff_spec.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, ldiff_spec.
Qed.
(** For integers, we do have a binary complement function *)
Definition lnot a := P (-a).
Instance lnot_wd : Proper (eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma lnot_spec : forall a n, 0<=n -> (lnot a).[n] = negb a.[n].
Proof.
intros. unfold lnot. rewrite <- (opp_involutive a) at 2.
rewrite bits_opp, negb_involutive; trivial.
Qed.
Lemma lnot_involutive : forall a, lnot (lnot a) == a.
Proof.
intros a. bitwise. now rewrite 2 lnot_spec, negb_involutive.
Qed.
Lemma lnot_0 : lnot 0 == -1.
Proof.
unfold lnot. now rewrite opp_0, <- sub_1_r, sub_0_l.
Qed.
Lemma lnot_m1 : lnot (-1) == 0.
Proof.
unfold lnot. now rewrite opp_involutive, one_succ, pred_succ.
Qed.
(** Complement and other operations *)
Lemma lor_m1_r : forall a, lor a (-1) == -1.
Proof.
intros. bitwise. now rewrite bits_m1, orb_true_r.
Qed.
Lemma lor_m1_l : forall a, lor (-1) a == -1.
Proof.
intros. now rewrite lor_comm, lor_m1_r.
Qed.
Lemma land_m1_r : forall a, land a (-1) == a.
Proof.
intros. bitwise. now rewrite bits_m1, andb_true_r.
Qed.
Lemma land_m1_l : forall a, land (-1) a == a.
Proof.
intros. now rewrite land_comm, land_m1_r.
Qed.
Lemma ldiff_m1_r : forall a, ldiff a (-1) == 0.
Proof.
intros. bitwise. now rewrite bits_m1, andb_false_r.
Qed.
Lemma ldiff_m1_l : forall a, ldiff (-1) a == lnot a.
Proof.
intros. bitwise. now rewrite lnot_spec, bits_m1.
Qed.
Lemma lor_lnot_diag : forall a, lor a (lnot a) == -1.
Proof.
intros a. bitwise. rewrite lnot_spec, bits_m1; trivial.
now destruct a.[m].
Qed.
Lemma add_lnot_diag : forall a, a + lnot a == -1.
Proof.
intros a. unfold lnot.
now rewrite add_pred_r, add_opp_r, sub_diag, one_succ, opp_succ, opp_0.
Qed.
Lemma ldiff_land : forall a b, ldiff a b == land a (lnot b).
Proof.
intros. bitwise. now rewrite lnot_spec.
Qed.
Lemma land_lnot_diag : forall a, land a (lnot a) == 0.
Proof.
intros. now rewrite <- ldiff_land, ldiff_diag.
Qed.
Lemma lnot_lor : forall a b, lnot (lor a b) == land (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, lor_spec, negb_orb.
Qed.
Lemma lnot_land : forall a b, lnot (land a b) == lor (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, land_spec, negb_andb.
Qed.
Lemma lnot_ldiff : forall a b, lnot (ldiff a b) == lor (lnot a) b.
Proof.
intros a b. bitwise.
now rewrite !lnot_spec, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b, lxor (lnot a) (lnot b) == lxor a b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, xorb_negb_negb.
Qed.
Lemma lnot_lxor_l : forall a b, lnot (lxor a b) == lxor (lnot a) b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_l.
Qed.
Lemma lnot_lxor_r : forall a b, lnot (lxor a b) == lxor a (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_r.
Qed.
Lemma lxor_m1_r : forall a, lxor a (-1) == lnot a.
Proof.
intros. now rewrite <- (lxor_0_r (lnot a)), <- lnot_m1, lxor_lnot_lnot.
Qed.
Lemma lxor_m1_l : forall a, lxor (-1) a == lnot a.
Proof.
intros. now rewrite lxor_comm, lxor_m1_r.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
Lemma lnot_shiftr : forall a n, 0<=n -> lnot (a >> n) == (lnot a) >> n.
Proof.
intros a n Hn. bitwise.
now rewrite lnot_spec, 2 shiftr_spec, lnot_spec by order_pos.
Qed.
(** [(ones n)] is [2^n-1], the number with [n] digits 1 *)
Definition ones n := P (1<<n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros. unfold ones.
destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
f_equiv. rewrite pow_neg_r; trivial.
rewrite <- shiftr_opp_r. apply shiftr_eq_0_iff. right; split.
order'. rewrite log2_1. now apply opp_pos_neg.
Qed.
Lemma ones_add : forall n m, 0<=n -> 0<=m ->
ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m Hn Hm. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r by trivial.
rewrite add_sub_assoc, sub_add. reflexivity.
Qed.
Lemma ones_div_pow2 : forall n m, 0<=m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m (Hm,H). symmetry. apply div_unique with (ones m).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_mod_pow2 : forall n m, 0<=m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m (Hm,H). symmetry. apply mod_unique with (ones (n-m)).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_spec_low : forall n m, 0<=m<n -> (ones n).[m] = true.
Proof.
intros n m (Hm,H). apply testbit_true; trivial.
rewrite ones_div_pow2 by (split; order).
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
split. order'. apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, 0<=n<=m -> (ones n).[m] = false.
Proof.
intros n m (Hn,H). le_elim Hn.
apply bits_above_log2; rewrite ones_equiv.
rewrite <-lt_succ_r, succ_pred; order_pos.
rewrite log2_pred_pow2; trivial. now rewrite <-le_succ_l, succ_pred.
rewrite ones_equiv. now rewrite <- Hn, pow_0_r, one_succ, pred_succ, bits_0.
Qed.
Lemma ones_spec_iff : forall n m, 0<=n ->
((ones n).[m] = true <-> 0<=m<n).
Proof.
intros n m Hn. split. intros H.
destruct (lt_ge_cases m 0) as [Hm|Hm].
now rewrite testbit_neg_r in H.
split; trivial. apply lt_nge. intro H'. rewrite ones_spec_high in H.
discriminate. now split.
apply ones_spec_low.
Qed.
Lemma lor_ones_low : forall a n, 0<=a -> log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; try split; trivial.
now apply lt_le_trans with n.
apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, orb_true_r; try split; trivial.
Qed.
Lemma land_ones : forall a n, 0<=n -> land a (ones n) == a mod 2^n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r;
try split; trivial.
rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r;
try split; trivial.
Qed.
Lemma land_ones_low : forall a n, 0<=a -> log2 a < n ->
land a (ones n) == a.
Proof.
intros a n Ha H.
assert (Hn : 0<=n) by (generalize (log2_nonneg a); order).
rewrite land_ones; trivial. apply mod_small.
split; trivial.
apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
Lemma ldiff_ones_r : forall a n, 0<=n ->
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high, shiftr_spec; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now apply le_0_sub.
now split.
rewrite ones_spec_low, shiftl_spec_low, andb_false_r;
try split; trivial.
Qed.
Lemma ldiff_ones_r_low : forall a n, 0<=a -> log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, andb_false_r; try split; trivial.
Qed.
Lemma ldiff_ones_l_low : forall a n, 0<=a -> log2 a < n ->
ldiff (ones n) a == lxor a (ones n).
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, xorb_true_r; try split; trivial.
Qed.
(** Bitwise operations and sign *)
Lemma shiftl_nonneg : forall a n, 0 <= (a << n) <-> 0 <= a.
Proof.
intros a n.
destruct (le_ge_cases 0 n) as [Hn|Hn].
(* 0<=n *)
rewrite 2 bits_iff_nonneg_ex. split; intros (k,Hk).
exists (k-n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite <- (add_simpl_r m n), <- (shiftl_spec a n) by order_pos.
apply Hk. now apply lt_sub_lt_add_r.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftl_spec by trivial. apply Hk. now apply lt_add_lt_sub_r.
(* n<=0*)
rewrite <- shiftr_opp_r, 2 bits_iff_nonneg_ex. split; intros (k,Hk).
destruct (le_gt_cases 0 k).
exists (k-n). intros m Hm. apply lt_sub_lt_add_r in Hm.
rewrite <- (add_simpl_r m n), <- add_opp_r, <- (shiftr_spec a (-n)).
now apply Hk. order.
assert (EQ : a >> (-n) == 0).
apply bits_inj'. intros m Hm. rewrite bits_0. apply Hk; order.
apply shiftr_eq_0_iff in EQ.
rewrite <- bits_iff_nonneg_ex. destruct EQ as [EQ|[LT _]]; order.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec by trivial. apply Hk.
rewrite add_opp_r. now apply lt_add_lt_sub_r.
Qed.
Lemma shiftl_neg : forall a n, (a << n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftl_nonneg.
Qed.
Lemma shiftr_nonneg : forall a n, 0 <= (a >> n) <-> 0 <= a.
Proof.
intros. rewrite <- shiftl_opp_r. apply shiftl_nonneg.
Qed.
Lemma shiftr_neg : forall a n, (a >> n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftr_nonneg.
Qed.
Lemma div2_nonneg : forall a, 0 <= div2 a <-> 0 <= a.
Proof.
intros. rewrite div2_spec. apply shiftr_nonneg.
Qed.
Lemma div2_neg : forall a, div2 a < 0 <-> a < 0.
Proof.
intros a. now rewrite 2 lt_nge, div2_nonneg.
Qed.
Lemma lor_nonneg : forall a b, 0 <= lor a b <-> 0<=a /\ 0<=b.
Proof.
intros a b.
rewrite 3 bits_iff_nonneg_ex. split. intros (k,Hk).
split; exists k; intros m Hm; apply (orb_false_elim a.[m] b.[m]);
rewrite <- lor_spec; now apply Hk.
intros ((k,Hk),(k',Hk')).
destruct (le_ge_cases k k'); [ exists k' | exists k ];
intros m Hm; rewrite lor_spec, Hk, Hk'; trivial; order.
Qed.
Lemma lor_neg : forall a b, lor a b < 0 <-> a < 0 \/ b < 0.
Proof.
intros a b. rewrite 3 lt_nge, lor_nonneg. split.
apply not_and. apply le_decidable.
now intros [H|H] (H',H'').
Qed.
Lemma lnot_nonneg : forall a, 0 <= lnot a <-> a < 0.
Proof.
intros a; unfold lnot.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
Lemma lnot_neg : forall a, lnot a < 0 <-> 0 <= a.
Proof.
intros a. now rewrite le_ngt, lt_nge, lnot_nonneg.
Qed.
Lemma land_nonneg : forall a b, 0 <= land a b <-> 0<=a \/ 0<=b.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_nonneg,
lor_neg, !lnot_neg.
Qed.
Lemma land_neg : forall a b, land a b < 0 <-> a < 0 /\ b < 0.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_neg,
lor_nonneg, !lnot_nonneg.
Qed.
Lemma ldiff_nonneg : forall a b, 0 <= ldiff a b <-> 0<=a \/ b<0.
Proof.
intros. now rewrite ldiff_land, land_nonneg, lnot_nonneg.
Qed.
Lemma ldiff_neg : forall a b, ldiff a b < 0 <-> a<0 /\ 0<=b.
Proof.
intros. now rewrite ldiff_land, land_neg, lnot_neg.
Qed.
Lemma lxor_nonneg : forall a b, 0 <= lxor a b <-> (0<=a <-> 0<=b).
Proof.
assert (H : forall a b, 0<=a -> 0<=b -> 0<=lxor a b).
intros a b. rewrite 3 bits_iff_nonneg_ex. intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
assert (H' : forall a b, 0<=a -> b<0 -> lxor a b<0).
intros a b. rewrite bits_iff_nonneg_ex, 2 bits_iff_neg_ex.
intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
intros a b.
split.
intros Hab. split.
intros Ha. destruct (le_gt_cases 0 b) as [Hb|Hb]; trivial.
generalize (H' _ _ Ha Hb). order.
intros Hb. destruct (le_gt_cases 0 a) as [Ha|Ha]; trivial.
generalize (H' _ _ Hb Ha). rewrite lxor_comm. order.
intros E.
destruct (le_gt_cases 0 a) as [Ha|Ha]. apply H; trivial. apply E; trivial.
destruct (le_gt_cases 0 b) as [Hb|Hb]. apply H; trivial. apply E; trivial.
rewrite <- lxor_lnot_lnot. apply H; now apply lnot_nonneg.
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]].
(* a < 0 *)
destruct (proj1 (bits_iff_neg_ex a) Ha) as (k,Hk).
destruct (le_gt_cases n k).
specialize (Hk (S k) (lt_succ_diag_r _)).
rewrite H' in Hk. discriminate. apply lt_succ_r; order.
specialize (H' (S n) (lt_succ_diag_r _)).
rewrite Hk in H'. discriminate. apply lt_succ_r; order.
(* a = 0 *)
now rewrite Ha, bits_0 in H.
(* 0 < a *)
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H'.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, 0<a -> log2 (a >> n) == max 0 (log2 a - n).
Proof.
intros a n Ha.
destruct (le_gt_cases 0 (log2 a - n));
[rewrite max_r | rewrite max_l]; try order.
apply log2_bits_unique.
now rewrite shiftr_spec, sub_add, bit_log2.
intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
rewrite lt_sub_lt_add_r, add_0_l in H.
apply log2_nonpos. apply le_lteq; right.
apply shiftr_eq_0_iff. right. now split.
Qed.
Lemma log2_shiftl : forall a n, 0<a -> 0<=n -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha Hn.
rewrite shiftl_mul_pow2, add_comm by trivial.
now apply log2_mul_pow2.
Qed.
Lemma log2_shiftl' : forall a n, 0<a -> log2 (a << n) == max 0 (log2 a + n).
Proof.
intros a n Ha.
rewrite <- shiftr_opp_r, log2_shiftr by trivial.
destruct (le_gt_cases 0 (log2 a + n));
[rewrite 2 max_r | rewrite 2 max_l]; rewrite ?sub_opp_r; try order.
Qed.
Lemma log2_lor : forall a b, 0<=a -> 0<=b ->
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lor a b) == log2 b).
intros a b Ha H.
le_elim Ha; [|now rewrite <- Ha, lor_0_l].
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b Ha Hb. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b, 0<=a -> 0<=b ->
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (land a b) <= log2 a).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= land a b) by (apply land_nonneg; now left).
le_elim H.
generalize (bit_log2 (land a b) H).
now rewrite land_spec, bits_above_log2.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b, 0<=a -> 0<=b ->
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lxor a b) <= log2 b).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= lxor a b) by (apply lxor_nonneg; split; order).
le_elim H.
generalize (bit_log2 (lxor a b) H).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; split; order') || idtac.
symmetry. apply div_unique with 1. left; split; order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1.
rewrite (div2_odd b), <- bit0_odd at 1.
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits_aux : forall n, 0<=n ->
forall a b (c0:bool), -(2^n) <= a < 2^n -> -(2^n) <= b < 2^n ->
exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
(* base *)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r, <- !one_succ.
intros (Ha1,Ha2) (Hb1,Hb2).
le_elim Ha1; rewrite <- ?le_succ_l, ?succ_m1 in Ha1;
le_elim Hb1; rewrite <- ?le_succ_l, ?succ_m1 in Hb1.
(* base, a = 0, b = 0 *)
exists c0.
rewrite (le_antisymm _ _ Ha2 Ha1), (le_antisymm _ _ Hb2 Hb1).
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2z_div2, b2z_bit0; now repeat split.
(* base, a = 0, b = -1 *)
exists (-c0). rewrite <- Hb1, (le_antisymm _ _ Ha2 Ha1). repeat split.
rewrite add_0_l, lxor_0_l, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_l, !lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = 0 *)
exists (-c0). rewrite <- Ha1, (le_antisymm _ _ Hb2 Hb1). repeat split.
rewrite add_0_r, lxor_0_r, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_r, lor_0_r, lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = -1 *)
exists (c0 + 2*(-1)). rewrite <- Ha1, <- Hb1. repeat split.
rewrite lxor_m1_l, lnot_m1, lxor_0_l.
now rewrite two_succ, mul_succ_l, mul_1_l, add_comm, add_assoc.
rewrite land_m1_l, lor_m1_l.
apply add_b2z_double_div2.
apply add_b2z_double_bit0.
(* step *)
clear n Hn. intros n Hn IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
exists (c0 + 2*c). repeat split.
(* step, add *)
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, <- 2 lxor_spec by trivial.
f_equiv.
rewrite add_b2z_double_div2, <- IH1. apply add_carry_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0, add3_bit0, b2z_bit0.
(* step, carry *)
rewrite add_b2z_double_div2.
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, IH2 by trivial.
autorewrite with bitwise. now rewrite add_b2z_double_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0.
(* step, carry0 *)
apply add_b2z_double_bit0.
Qed.
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
set (n := max (abs a) (abs b)).
apply (add_carry_bits_aux n).
(* positivity *)
unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; order_pos'.
(* bound for a *)
assert (Ha : abs a < 2^n).
apply lt_le_trans with (2^(abs a)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Ha. destruct Ha; split; order.
(* bound for b *)
assert (Hb : abs b < 2^n).
apply lt_le_trans with (2^(abs b)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Hb. destruct Hb; split; order.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2 by order.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj'. intros n Hn. rewrite bits_0.
apply le_ind with (4:=Hn).
solve_proper.
trivial.
clear n Hn. intros n Hn IH.
rewrite <- div2_bits, H; trivial.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, 0<=b -> ldiff a b == 0 -> 0 <= a <= b.
Proof.
assert (AUX : forall n, 0<=n ->
forall a b, 0 <= a < 2^n -> 0<=b -> ldiff a b == 0 -> a <= b).
intros n Hn. apply le_ind with (4:=Hn); clear n Hn.
solve_proper.
intros a b Ha Hb _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
setoid_replace a with 0 by (destruct Ha; order'); trivial.
intros n Hn IH a b (Ha,Ha') Hb H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_pos_l; try order'.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound; try order'. now rewrite <- pow_succ_r.
apply div_pos; order'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2 by order'.
rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l; order'.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
(* main *)
intros a b Hb Hd.
assert (Ha : 0<=a).
apply le_ngt; intros Ha'. apply (lt_irrefl 0). rewrite <- Hd at 1.
apply ldiff_neg. now split.
split; trivial. apply (AUX a); try split; trivial. apply pow_gt_lin_r; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor; trivial.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
destruct (le_gt_cases a 0) as [Ha'|Ha'].
apply le_lt_trans with (0+b). now apply add_le_mono_r. now nzsimpl.
destruct (le_gt_cases b 0) as [Hb'|Hb'].
apply le_lt_trans with (a+0). now apply add_le_mono_l. now nzsimpl.
rewrite add_nocarry_lxor by order.
destruct (lt_ge_cases 0 (lxor a b)); [|apply le_lt_trans with 0; order_pos].
apply log2_lt_pow2; trivial.
apply log2_lt_pow2 in Ha; trivial.
apply log2_lt_pow2 in Hb; trivial.
apply le_lt_trans with (max (log2 a) (log2 b)).
apply log2_lxor; order.
destruct (le_ge_cases (log2 a) (log2 b));
[rewrite max_r|rewrite max_l]; order.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, 0<=n -> land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n Hn H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
rewrite mod_pow2_bits_high; now split.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_pos_bound; order_pos.
apply mod_pos_bound; order_pos.
Qed.
End ZBitsProp.
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// [email protected], [email protected]
//
// Create Date: 06:40:00 08/03/2014
// Design Name: ncl_simlib_ref
// Module Name: ncl_simlib_ref
// Project Name: Streaming Media on Null Convention Logic
// Description: Reference library for new gates function simulation
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module th34w32_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a) | (b&c) | (b&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th54w32_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module thxor0_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module thxor0n_ref (y,a,b,c,d,rsb);
output y;
input a;
input b;
input c;
input d;
input rsb;
reg yi;
always @(a or b or c or d or rsb) begin
if (rsb == 0) begin
yi <= 0;
end
else begin
if (((a&b) | (c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
end
assign #1 y = yi;
endmodule
module th24w2_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a) | (b&c) | (b&d) | (c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44w22_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c&d) | (b&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th34w2_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d) | (b&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th34w3_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a) | (b&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th24_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d) | (b&c) | (b&d) | (c&d) ))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th24comp_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&c) | (b&c) | (a&d) | (b&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th22_ref (y,a,b);
output y;
input a;
input b;
reg yi;
always @(a or b) begin
if (((a) & (b)))
begin
yi <= 1;
end
else if (((a==0) & (b==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th22x8_ref (y,a,b);
output y;
input a;
input b;
reg yi;
always @(a or b) begin
if (((a) & (b)))
begin
yi <= 1;
end
else if (((a==0) & (b==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th22r_ref (y,a,b,rsb);
output y;
input a;
input b;
input rsb;
reg yi;
always @(a or b or rsb) begin
if (rsb == 0) begin
yi <= 0;
end
else if (((a) & (b)))
begin
yi <= 1;
end
else if (((a==0) & (b==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th22s_ref (y,a,b,rsb);
output y;
input a;
input b;
input rsb;
reg yi;
always @(a or b or rsb) begin
if (rsb == 0) begin
yi <= 1;
end
else if (((a) & (b)))
begin
yi <= 1;
end
else if (((a==0) & (b==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th23_ref (y,a,b,c);
output y;
input a;
input b;
input c;
reg yi;
always @(a or b or c) begin
if (((a & b) | (a & c) | (b & c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th54w22_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b&c) | (a&b&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th34w22_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d) | (b&c) | (b&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a) & (b) & (c) & (d) ))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th24w22_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a) | (b) | (c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44w3_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44w2_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b&c) | (a&b&d) | (a&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th33w2_ref (y,a,b,c);
output y;
input a;
input b;
input c;
reg yi;
always @(a or b or c) begin
if (((a & b) | (a & c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th34_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b&c) | (a&b&d) | (a&c&d) | (b&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th23w2_ref (y,a,b,c);
output y;
input a;
input b;
input c;
reg yi;
always @(a or b or c) begin
if (((a) | (b & c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th13_ref (y,a,b,c);
output y;
input a;
input b;
input c;
assign #1 y = a | b | c;
endmodule
module th12_ref (y,a,b);
output y;
input a;
input b;
assign #1 y = a | b;
endmodule
module th54w322_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (b&c&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th14_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
assign #1 y = a | b | c | d;
endmodule
module th33_ref (y,a,b,c);
output y;
input a;
input b;
input c;
reg yi;
always @(a or b or c) begin
if (((a) & (b) & (c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th33r_ref (y,a,b,c,rsb);
output y;
input a;
input b;
input c;
input rsb;
reg yi;
always @(a or b or c or rsb) begin
if (rsb == 0)begin
yi <= 0;
end else if (((a) & (b) & (c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module thand0_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (b&c) | (a&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44w322_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d) | (b&c)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
module th44w322a_ref (y,a,b,c,d);
output y;
input a;
input b;
input c;
input d;
reg yi;
always @(a or b or c or d) begin
if (((a&b) | (a&c) | (a&d) | (b&d)))
begin
yi <= 1;
end
else if (((a==0) & (b==0) & (c==0) & (d==0)))
begin
yi <= 0;
end
end
assign #1 y = yi;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire clk_200mhz_p,
input wire clk_200mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire clk90_mmcm_out;
wire clk90_int;
wire rst_int;
wire clk_200mhz_mmcm_out;
wire clk_200mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_200mhz_ibufgds_inst(
.I(clk_200mhz_p),
.IB(clk_200mhz_n),
.O(clk_200mhz_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Need two 125 MHz outputs with 90 degree offset
// Also need 200 MHz out for IODELAY
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(90),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_200mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk90_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(clk_200mhz_mmcm_out),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk90_bufg_inst (
.I(clk90_mmcm_out),
.O(clk90_int)
);
BUFG
clk_200mhz_bufg_inst (
.I(clk_200mhz_mmcm_out),
.O(clk_200mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire phy_rx_ctl_delay;
IDELAYCTRL
idelayctrl_inst (
.REFCLK(clk_200mhz_int),
.RST(rst_int),
.RDY()
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0 (
.IDATAIN(phy_rxd[0]),
.DATAOUT(phy_rxd_delay[0]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1 (
.IDATAIN(phy_rxd[1]),
.DATAOUT(phy_rxd_delay[1]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2 (
.IDATAIN(phy_rxd[2]),
.DATAOUT(phy_rxd_delay[2]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3 (
.IDATAIN(phy_rxd[3]),
.DATAOUT(phy_rxd_delay[3]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay (
.IDATAIN(phy_rx_ctl),
.DATAOUT(phy_rx_ctl_delay),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd_delay),
.phy_rx_ctl(phy_rx_ctl_delay),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_2_V
`define SKY130_FD_SC_HDLL__NAND4B_2_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_2_V
|
// TODO(bluecmd): This module assumes that the G18 Flash is in
// asynchronous mode. It will assume 16 cycles latency (> worst case) and
// will not do brusts. Quite a lot of areas to improve :-).
module wb_g18 #(
parameter g18_size = 67108864, // 512 Mbit
parameter g18_aw = $clog2(g18_size/2),
parameter wb_aw = 32
) (
input wb_clk_i,
input wb_rst_i,
input [wb_aw-1:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output [31:0] wb_dat_o,
inout [15:0] g18_dat_io,
output [g18_aw-1:0] g18_adr_o,
output g18_csn_o,
output g18_oen_o,
output g18_wen_o,
output g18_advn_o,
output g18_clk_o,
output g18_rstn_o
);
reg [g18_aw-1:0] g18_adr_r = 0;
reg [3:0] latency_r = 4'hf;
reg [3:0] data_valid_cntr_r = 0;
reg data_half_r = 1'b0;
reg valid_r = 1'b0;
reg adr_valid_r = 1'b0;
reg wb_ack_r = 1'b0;
reg [31:0] wb_dat_r = 0;
wire valid = wb_cyc_i & wb_stb_i;
wire new_cycle = valid & !valid_r;
wire data_valid = (data_valid_cntr_r == 0);
assign wb_ack_o = wb_ack_r;
assign wb_dat_o = wb_dat_r;
assign g18_rstn_o = ~wb_rst_i;
assign g18_clk_o = 1'b0;
assign g18_csn_o = 1'b0;
assign g18_oen_o = 1'b0;
assign g18_wen_o = 1'b1;
assign g18_adr_o = g18_adr_r;
// For synchronous mode this should be ~adr_valid_r, but we set it to 0
// to keep the flash in async mode.
assign g18_advn_o = 1'b0;
always @(posedge wb_clk_i)
begin
if (wb_rst_i) begin
adr_valid_r <= 1'b0;
valid_r <= 1'b0;
g18_adr_r <= 0;
end else begin
adr_valid_r <= 1'b0;
valid_r <= valid;
if (new_cycle) begin
adr_valid_r <= 1'b1;
g18_adr_r <= wb_adr_i[1+:g18_aw];
end
if (data_valid & ~data_half_r) begin
g18_adr_r <= g18_adr_r + 1;
end
end
end
always @(posedge wb_clk_i)
begin
if (wb_rst_i) begin
data_half_r <= 1'b0;
data_valid_cntr_r <= data_valid_cntr_r - 4'b1;
wb_dat_r <= 0;
end else begin
if (~data_valid) begin
data_valid_cntr_r <= data_valid_cntr_r - 4'b1;
end
if (new_cycle) begin
data_half_r <= 1'b0;
data_valid_cntr_r <= latency_r;
wb_dat_r <= 0;
end
if (data_valid & ~data_half_r) begin
data_half_r <= 1'b1;
data_valid_cntr_r <= latency_r;
wb_dat_r[31:16] <= g18_dat_io;
end
if (data_valid & data_half_r) begin
wb_dat_r[15:0] <= g18_dat_io;
end
end
end
always @(posedge wb_clk_i)
begin
if (wb_rst_i) begin
wb_ack_r <= 1'b0;
end else begin
wb_ack_r <= valid & data_valid & ~wb_ack_r & ~new_cycle & data_half_r;
end
end
`ifdef DEBUG
always @(posedge wb_clk_i)
begin
if (adr_valid_r) begin
$display("New read cycle: 0x%08x", {g18_adr_r, 1'b0});
end
if (wb_ack_r) begin
$display("Finished read cycle: 0x%08x", {g18_adr_r, 1'b0});
$display("Data returned: 0x%08x", wb_dat_o);
end
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_M_V
`define SKY130_FD_SC_LP__OR2_M_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_m (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_m (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_M_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_rx_null_gen.v
// Version : 2.3
//----------------------------------------------------------------------------//
// File: axi_basic_rx_null_gen.v //
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [STRB_WIDTH-1:0] null_rx_tstrb, // NULL generated tstrb
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [STRB_WIDTH-1:0] eof_tstrb;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digist: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd2;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd2;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate TSTRB/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// TSTRB not used in 128-bit interface
assign eof_tstrb = {STRB_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign TSTRB to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tstrb = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so TSTRB is always 0xF
assign eof_tstrb = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tstrb = null_rx_tlast ? eof_tstrb : {STRB_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
module daala_4x4_transpose_v1_0_S00_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// AXI4Stream sink: Clock
input wire S_AXIS_ACLK,
// AXI4Stream sink: Reset
input wire S_AXIS_ARESETN,
// Ready to accept data in
output wire S_AXIS_TREADY,
// Data in
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
// Byte qualifier
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
// Indicates boundary of last packet
input wire S_AXIS_TLAST,
// Data is in valid
input wire S_AXIS_TVALID
);
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 8;
// bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
// Define the states of state machine
// The control state machine oversees the writing of input streaming data to the FIFO,
// and outputs the streaming data from the FIFO
parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
WRITE_FIFO = 1'b1; // In this state FIFO is written with the
// input stream data S_AXIS_TDATA
wire axis_tready;
// State variable
reg mst_exec_state;
// FIFO implementation signals
genvar byte_index;
// FIFO write enable
wire fifo_wren;
// FIFO full flag
reg fifo_full_flag;
// FIFO write pointer
reg [bit_num-1:0] write_pointer;
// sink has accepted all the streaming data and stored in FIFO
reg writes_done;
// I/O Connections assignments
assign S_AXIS_TREADY = axis_tready;
// Control state machine implementation
always @(posedge S_AXIS_ACLK)
begin
if (!S_AXIS_ARESETN)
// Synchronous reset (active low)
begin
mst_exec_state <= IDLE;
end
else
case (mst_exec_state)
IDLE:
// The sink starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if (S_AXIS_TVALID)
begin
mst_exec_state <= WRITE_FIFO;
end
else
begin
mst_exec_state <= IDLE;
end
WRITE_FIFO:
// When the sink has accepted all the streaming input data,
// the interface swiches functionality to a streaming master
if (writes_done)
begin
mst_exec_state <= IDLE;
end
else
begin
// The sink accepts and stores tdata
// into FIFO
mst_exec_state <= WRITE_FIFO;
end
endcase
end
// AXI Streaming Sink
//
// The example design sink is always ready to accept the S_AXIS_TDATA until
// the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
always@(posedge S_AXIS_ACLK)
begin
if(!S_AXIS_ARESETN)
begin
write_pointer <= 0;
writes_done <= 1'b0;
end
else
if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
begin
if (fifo_wren)
begin
// write pointer is incremented after every write to the FIFO
// when FIFO write signal is enabled.
write_pointer <= write_pointer + 1;
writes_done <= 1'b0;
end
if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
begin
// reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
// has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
writes_done <= 1'b1;
end
end
end
// FIFO write enable generation
assign fifo_wren = S_AXIS_TVALID && axis_tready;
// FIFO Implementation
generate
for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
begin:FIFO_GEN
reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
// Streaming input data is stored in FIFO
always @( posedge S_AXIS_ACLK )
begin
if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
begin
stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
end
end
end
endgenerate
// Add user logic here
// User logic ends
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_rdq_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Header Queue Control
// Top level Module: jbi_min_rq_rdq_ctl
// Where Instantiated: jbi_min_rq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_rdq_ctl(/*AUTOARG*/
// Outputs
rdq_full, rdq_wr_en, rdq_rd_en, rdq_waddr, rdq_raddr,
// Inputs
clk, rst_l, cpu_clk, cpu_rst_l, cpu_tx_en, cpu_rx_en, wdq_rdq_push,
issue_rdq_pop
);
input clk;
input rst_l;
input cpu_clk;
input cpu_rst_l;
input cpu_tx_en;
input cpu_rx_en;
// WDQ Interface
input wdq_rdq_push;
output rdq_full;
// SCTAG Issue Interface
input issue_rdq_pop;
// Request Header Queue Interface
output rdq_wr_en;
output rdq_rd_en;
output [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_waddr;
output [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_raddr;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire rdq_full;
wire rdq_wr_en;
wire rdq_rd_en;
wire [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_waddr;
wire [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_raddr;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_RDQ_ADDR_WIDTH:0] rdq_wptr;
wire [`JBI_RDQ_ADDR_WIDTH:0] rdq_rptr;
reg [`JBI_RDQ_ADDR_WIDTH:0] next_rdq_wptr;
reg [`JBI_RDQ_ADDR_WIDTH:0] next_rdq_rptr;
wire [`JBI_RDQ_ADDR_WIDTH:0] tx_rdq_rptr;
wire [`JBI_RDQ_ADDR_WIDTH:0] j_rdq_rptr;
wire next_j_rdq_empty;
wire [`JBI_RDQ_ADDR_WIDTH:0] next_free;
wire next_rdq_full;
wire [`JBI_RDQ_ADDR_WIDTH:0] rdq_wptr_d1;
wire [`JBI_RDQ_ADDR_WIDTH:0] rdq_wptr_d2;
wire [`JBI_RDQ_ADDR_WIDTH:0] c_rdq_wptr;
//
// Code start here
//
//*******************************************************************************
// Push Header Queue (JBUS CLK)
//*******************************************************************************
//----------------------
// Pointer Management
//----------------------
always @ ( /*AUTOSENSE*/rdq_wptr or wdq_rdq_push) begin
if (wdq_rdq_push)
next_rdq_wptr = rdq_wptr + 1'b1;
else
next_rdq_wptr = rdq_wptr;
end
assign rdq_waddr = rdq_wptr[`JBI_RDQ_ADDR_WIDTH-1:0];
assign rdq_wr_en = rst_l & wdq_rdq_push;
//*******************************************************************************
// Pop Header Queue (CPU CLK)
//*******************************************************************************
always @ ( /*AUTOSENSE*/issue_rdq_pop or rdq_rptr) begin
if (issue_rdq_pop)
next_rdq_rptr = rdq_rptr + 1'b1;
else
next_rdq_rptr = rdq_rptr;
end
assign rdq_raddr = next_rdq_rptr[`JBI_RDQ_ADDR_WIDTH-1:0];
assign rdq_rd_en = next_rdq_rptr != c_rdq_wptr;
//*******************************************************************************
// Flow Control (JBUS CLK)
//*******************************************************************************
assign next_j_rdq_empty = next_rdq_wptr == j_rdq_rptr;
assign next_free = j_rdq_rptr - next_rdq_wptr;
assign next_rdq_full = next_free[`JBI_RDQ_ADDR_WIDTH-1:0] < `JBI_RDQ_ADDR_WIDTH'd5
& ~next_j_rdq_empty;
//*******************************************************************************
// Synchronization DFFRLEs
//*******************************************************************************
//----------------------
// CPU -> JBUS
//----------------------
dffrle_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dffrle_tx_rdq_rptr
(.din(rdq_rptr),
.clk(cpu_clk),
.en(cpu_tx_en),
.rst_l(cpu_rst_l),
.q(tx_rdq_rptr)
);
dffrl_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dffrl_j_rdq_rptr
(.din(tx_rdq_rptr),
.clk(clk),
.rst_l(rst_l),
.q(j_rdq_rptr)
);
//----------------------
// JBUS -> CPU
//----------------------
dffrle_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dffrle_c_rdq_wptr
(.din(rdq_wptr_d2),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_rdq_wptr)
);
///*******************************************************************************
// DFF Instantiations
//*******************************************************************************
//----------------------
// JBUS CLK
//----------------------
dff_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dff_rdq_wptr_d1
(.din(rdq_wptr),
.clk(clk),
.q(rdq_wptr_d1)
);
dff_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dff_rdq_wptr_d2
(.din(rdq_wptr_d1),
.clk(clk),
.q(rdq_wptr_d2)
);
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
//----------------------
// JBUS CLK
//----------------------
dffrl_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dffrl_rdq_wptr
(.din(next_rdq_wptr),
.clk(clk),
.rst_l(rst_l),
.q(rdq_wptr)
);
dffrl_ns #(1) u_dffrl_rdq_full
(.din(next_rdq_full),
.clk(clk),
.rst_l(rst_l),
.q(rdq_full)
);
//----------------------
// CPU CLK
//----------------------
dffrl_ns #(`JBI_RDQ_ADDR_WIDTH+1) u_dffrl_rdq_rptr
(.din(next_rdq_rptr),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(rdq_rptr)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
wire rc_rdq_full = rdq_wptr[`JBI_RDQ_ADDR_WIDTH] != j_rdq_rptr[`JBI_RDQ_ADDR_WIDTH]
& rdq_wptr[`JBI_RDQ_ADDR_WIDTH-1:0] == j_rdq_rptr[`JBI_RDQ_ADDR_WIDTH-1:0];
wire rc_rdq_empty = c_rdq_wptr[`JBI_RDQ_ADDR_WIDTH:0] == rdq_rptr[`JBI_RDQ_ADDR_WIDTH:0];
always @ ( /*AUTOSENSE*/rc_rdq_full or wdq_rdq_push) begin
@clk;
if (rc_rdq_full && wdq_rdq_push)
$dispmon ("jbi_min_rq_rdq_ctl", 49,"%d %m: ERROR - RDQ overflow!", $time);
end
always @ ( /*AUTOSENSE*/issue_rdq_pop or rc_rdq_empty) begin
@cpu_clk;
if (rc_rdq_empty && issue_rdq_pop)
$dispmon ("jbi_min_rq_rdq_ctl", 49,"%d %m: ERROR - RDQ underflow!", $time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:19:07 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358;
XNOR2X1TS U42 ( .A(n227), .B(n226), .Y(res[29]) );
NAND2X1TS U43 ( .A(n59), .B(n237), .Y(n238) );
NAND2X1TS U44 ( .A(n233), .B(n232), .Y(n234) );
NAND2XLTS U45 ( .A(n58), .B(n296), .Y(n298) );
NAND2X1TS U46 ( .A(n64), .B(n210), .Y(n207) );
NAND2X1TS U47 ( .A(n225), .B(n224), .Y(n226) );
NAND2X1TS U48 ( .A(n241), .B(n240), .Y(n242) );
NAND2XLTS U49 ( .A(n61), .B(n282), .Y(n283) );
NAND2XLTS U50 ( .A(n286), .B(n285), .Y(n287) );
NAND2XLTS U51 ( .A(n269), .B(n268), .Y(n270) );
NAND2XLTS U52 ( .A(n278), .B(n277), .Y(n279) );
NAND2X1TS U53 ( .A(n258), .B(n257), .Y(n259) );
NAND2X1TS U54 ( .A(n265), .B(n264), .Y(n266) );
NAND2XLTS U55 ( .A(n251), .B(n250), .Y(n252) );
NAND2X6TS U56 ( .A(n222), .B(n11), .Y(n56) );
OAI21X1TS U57 ( .A0(n9), .A1(n310), .B0(n311), .Y(n309) );
OAI21X1TS U58 ( .A0(n288), .A1(n275), .B0(n274), .Y(n280) );
OA21XLTS U59 ( .A0(n314), .A1(n111), .B0(n44), .Y(n9) );
INVX4TS U60 ( .A(n244), .Y(n271) );
INVX2TS U61 ( .A(n290), .Y(n297) );
NAND2X2TS U62 ( .A(n219), .B(in1[31]), .Y(n221) );
CLKBUFX2TS U63 ( .A(n289), .Y(n290) );
CLKMX2X2TS U64 ( .A(in2[31]), .B(n218), .S0(n217), .Y(n219) );
NOR2X1TS U65 ( .A(n215), .B(in2[30]), .Y(n216) );
NOR2X4TS U66 ( .A(n230), .B(n231), .Y(n198) );
NAND2X1TS U67 ( .A(n178), .B(in1[25]), .Y(n250) );
NAND2X2TS U68 ( .A(n176), .B(in1[23]), .Y(n264) );
NAND2X2TS U69 ( .A(n177), .B(in1[24]), .Y(n257) );
CLKMX2X2TS U70 ( .A(in2[29]), .B(n202), .S0(n201), .Y(n203) );
NAND2X2TS U71 ( .A(n194), .B(in1[27]), .Y(n237) );
OR2X4TS U72 ( .A(n154), .B(in1[20]), .Y(n61) );
NAND2BX2TS U73 ( .AN(in2[29]), .B(n204), .Y(n215) );
XNOR2X1TS U74 ( .A(n200), .B(in2[24]), .Y(n165) );
INVX2TS U75 ( .A(in2[23]), .Y(n168) );
OR2X1TS U76 ( .A(n190), .B(in2[27]), .Y(n199) );
NOR2X2TS U77 ( .A(n171), .B(n170), .Y(n172) );
NOR2X2TS U78 ( .A(n200), .B(n190), .Y(n188) );
XNOR2X1TS U79 ( .A(n131), .B(in2[17]), .Y(n132) );
NAND2X1TS U80 ( .A(n187), .B(n186), .Y(n190) );
NAND2X1TS U81 ( .A(n143), .B(in2[19]), .Y(n144) );
XNOR2X1TS U82 ( .A(n141), .B(in2[18]), .Y(n133) );
XOR2X2TS U83 ( .A(n171), .B(n149), .Y(n148) );
INVX2TS U84 ( .A(in2[26]), .Y(n186) );
NOR2X2TS U85 ( .A(in2[25]), .B(in2[24]), .Y(n187) );
NAND2X6TS U86 ( .A(n161), .B(n160), .Y(n200) );
INVX12TS U87 ( .A(n18), .Y(n160) );
OR2X6TS U88 ( .A(n107), .B(in1[11]), .Y(n62) );
INVX2TS U89 ( .A(n316), .Y(n109) );
INVX2TS U90 ( .A(n110), .Y(n317) );
NOR2X4TS U91 ( .A(n320), .B(n110), .Y(n45) );
NAND2X2TS U92 ( .A(n91), .B(in1[9]), .Y(n330) );
NOR2X6TS U93 ( .A(n117), .B(in1[14]), .Y(n305) );
NAND2X6TS U94 ( .A(n107), .B(in1[11]), .Y(n320) );
NAND2X2TS U95 ( .A(n108), .B(in1[12]), .Y(n316) );
OR2X2TS U96 ( .A(in2[21]), .B(in2[20]), .Y(n170) );
NAND2X4TS U97 ( .A(n33), .B(n32), .Y(n60) );
AND2X2TS U98 ( .A(n119), .B(n124), .Y(n12) );
NOR2X1TS U99 ( .A(in2[19]), .B(in2[18]), .Y(n146) );
XNOR2X2TS U100 ( .A(n104), .B(in2[10]), .Y(n87) );
NOR2X2TS U101 ( .A(in2[17]), .B(in2[16]), .Y(n147) );
CLKINVX6TS U102 ( .A(n77), .Y(n33) );
BUFX12TS U103 ( .A(n217), .Y(n201) );
INVX2TS U104 ( .A(in2[14]), .Y(n119) );
NOR2X2TS U105 ( .A(n95), .B(in2[8]), .Y(n88) );
INVX4TS U106 ( .A(n46), .Y(n70) );
NAND2X2TS U107 ( .A(n10), .B(n113), .Y(n114) );
NOR2X4TS U108 ( .A(n104), .B(in2[10]), .Y(n105) );
NAND2X4TS U109 ( .A(n46), .B(n31), .Y(n30) );
INVX6TS U110 ( .A(n143), .Y(n217) );
AO22X2TS U111 ( .A0(add_sub), .A1(n69), .B0(n67), .B1(in2[5]), .Y(n68) );
NAND3X2TS U112 ( .A(n37), .B(n72), .C(n348), .Y(n65) );
INVX4TS U113 ( .A(add_sub), .Y(n83) );
INVX4TS U114 ( .A(in2[8]), .Y(n86) );
NAND2X4TS U115 ( .A(n41), .B(n69), .Y(n79) );
INVX4TS U116 ( .A(n118), .Y(n28) );
CLKINVX3TS U117 ( .A(in2[9]), .Y(n90) );
NOR2X4TS U118 ( .A(n28), .B(n111), .Y(n27) );
MXI2X2TS U119 ( .A(n127), .B(n126), .S0(n201), .Y(n128) );
MXI2X2TS U120 ( .A(n152), .B(n151), .S0(n143), .Y(n157) );
INVX2TS U121 ( .A(n240), .Y(n196) );
NAND2X2TS U122 ( .A(n154), .B(in1[20]), .Y(n282) );
NAND2X1TS U123 ( .A(n197), .B(in1[28]), .Y(n232) );
INVX4TS U124 ( .A(add_sub), .Y(n143) );
OAI21XLTS U125 ( .A0(n333), .A1(n329), .B0(n330), .Y(n328) );
NAND2X1TS U126 ( .A(n293), .B(n292), .Y(n294) );
NOR2X4TS U127 ( .A(n25), .B(n24), .Y(n23) );
NAND2X4TS U128 ( .A(n317), .B(n62), .Y(n111) );
MX2X2TS U129 ( .A(in2[15]), .B(n122), .S0(add_sub), .Y(n123) );
XNOR2X2TS U130 ( .A(n65), .B(in2[6]), .Y(n66) );
NOR4X2TS U131 ( .A(n159), .B(n170), .C(in2[23]), .D(in2[22]), .Y(n161) );
NOR2X4TS U132 ( .A(n197), .B(in1[28]), .Y(n231) );
NAND2X1TS U133 ( .A(n63), .B(n299), .Y(n300) );
NOR2X4TS U134 ( .A(n141), .B(in2[18]), .Y(n142) );
NOR3X4TS U135 ( .A(n200), .B(in2[28]), .C(n199), .Y(n204) );
NOR2X2TS U136 ( .A(n200), .B(n199), .Y(n191) );
NAND2X1TS U137 ( .A(n307), .B(n306), .Y(n308) );
NAND2X1TS U138 ( .A(n317), .B(n316), .Y(n318) );
NAND2X1TS U139 ( .A(n16), .B(n303), .Y(n304) );
NAND2X6TS U140 ( .A(n19), .B(n12), .Y(n18) );
NOR2X4TS U141 ( .A(n108), .B(in1[12]), .Y(n110) );
INVX6TS U142 ( .A(n125), .Y(n19) );
INVX2TS U143 ( .A(in1[6]), .Y(n31) );
INVX2TS U144 ( .A(in1[7]), .Y(n32) );
INVX4TS U145 ( .A(n236), .Y(n241) );
OR2X4TS U146 ( .A(n219), .B(in1[31]), .Y(n11) );
INVX2TS U147 ( .A(n263), .Y(n265) );
INVX2TS U148 ( .A(n249), .Y(n251) );
NAND2X4TS U149 ( .A(n193), .B(in1[26]), .Y(n240) );
OR2X4TS U150 ( .A(n206), .B(in1[30]), .Y(n64) );
NOR2X4TS U151 ( .A(n157), .B(in1[21]), .Y(n276) );
NAND2X4TS U152 ( .A(n153), .B(in1[19]), .Y(n285) );
INVX2TS U153 ( .A(n292), .Y(n137) );
NOR2X4TS U154 ( .A(n178), .B(in1[25]), .Y(n249) );
NAND2X4TS U155 ( .A(n135), .B(in1[17]), .Y(n296) );
XNOR2X1TS U156 ( .A(n216), .B(in2[31]), .Y(n218) );
XOR2X2TS U157 ( .A(n150), .B(in2[21]), .Y(n152) );
OR2X4TS U158 ( .A(n128), .B(in1[16]), .Y(n63) );
XOR2X2TS U159 ( .A(n163), .B(n162), .Y(n164) );
INVX2TS U160 ( .A(n305), .Y(n307) );
NAND2X4TS U161 ( .A(n116), .B(in1[13]), .Y(n311) );
NAND2X4TS U162 ( .A(n123), .B(in1[15]), .Y(n303) );
NAND2X4TS U163 ( .A(n92), .B(in1[10]), .Y(n325) );
NAND2X4TS U164 ( .A(n353), .B(n69), .Y(n47) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n120) );
XOR2X1TS U166 ( .A(n295), .B(n294), .Y(res[18]) );
INVX4TS U167 ( .A(n198), .Y(n8) );
NAND2X4TS U168 ( .A(n241), .B(n59), .Y(n230) );
NAND2X2TS U169 ( .A(n11), .B(n221), .Y(n220) );
AOI21X2TS U170 ( .A0(n64), .A1(n212), .B0(n211), .Y(n213) );
XOR2X1TS U171 ( .A(n302), .B(n304), .Y(res[15]) );
NAND2X4TS U172 ( .A(n64), .B(n225), .Y(n214) );
INVX2TS U173 ( .A(n237), .Y(n195) );
OAI21X2TS U174 ( .A0(n249), .A1(n257), .B0(n250), .Y(n179) );
NOR2X4TS U175 ( .A(n249), .B(n256), .Y(n180) );
NAND2X4TS U176 ( .A(n58), .B(n293), .Y(n140) );
XOR2X1TS U177 ( .A(n319), .B(n318), .Y(res[12]) );
NAND2X2TS U178 ( .A(n206), .B(in1[30]), .Y(n210) );
NAND2X4TS U179 ( .A(n203), .B(in1[29]), .Y(n224) );
NAND2X4TS U180 ( .A(n175), .B(in1[22]), .Y(n268) );
INVX2TS U181 ( .A(n256), .Y(n258) );
NAND2X2TS U182 ( .A(n157), .B(in1[21]), .Y(n277) );
XOR2X1TS U183 ( .A(n9), .B(n313), .Y(res[13]) );
MX2X2TS U184 ( .A(in2[30]), .B(n205), .S0(n217), .Y(n206) );
NOR2X4TS U185 ( .A(n203), .B(in1[29]), .Y(n209) );
OR2X6TS U186 ( .A(n135), .B(in1[17]), .Y(n58) );
OR2X6TS U187 ( .A(n194), .B(in1[27]), .Y(n59) );
MX2X2TS U188 ( .A(in2[27]), .B(n189), .S0(n217), .Y(n194) );
XNOR2X2TS U189 ( .A(n184), .B(in2[26]), .Y(n185) );
MX2X2TS U190 ( .A(in2[25]), .B(n164), .S0(n201), .Y(n178) );
XOR2X1TS U191 ( .A(n333), .B(n332), .Y(res[9]) );
XNOR2X2TS U192 ( .A(n188), .B(in2[27]), .Y(n189) );
INVX2TS U193 ( .A(n200), .Y(n183) );
NOR2X2TS U194 ( .A(n130), .B(in2[16]), .Y(n131) );
INVX4TS U195 ( .A(n339), .Y(n78) );
NAND2X6TS U196 ( .A(n29), .B(n342), .Y(n340) );
NOR2X4TS U197 ( .A(n91), .B(in1[9]), .Y(n329) );
NAND2X6TS U198 ( .A(n343), .B(n30), .Y(n29) );
NAND3X6TS U199 ( .A(n68), .B(n48), .C(n47), .Y(n46) );
OAI21XLTS U200 ( .A0(n355), .A1(n83), .B0(n354), .Y(res[5]) );
MXI2X4TS U201 ( .A(n66), .B(n71), .S0(n83), .Y(n343) );
OAI21XLTS U202 ( .A0(n358), .A1(n83), .B0(n357), .Y(res[4]) );
OAI21XLTS U203 ( .A0(n350), .A1(n83), .B0(n349), .Y(res[2]) );
OAI21XLTS U204 ( .A0(n347), .A1(n83), .B0(n346), .Y(res[3]) );
AND2X4TS U205 ( .A(n100), .B(n99), .Y(n101) );
OAI21XLTS U206 ( .A0(n352), .A1(n143), .B0(n351), .Y(res[1]) );
NAND2X2TS U207 ( .A(n147), .B(n146), .Y(n159) );
AND2X4TS U208 ( .A(n98), .B(n97), .Y(n99) );
NAND2X4TS U209 ( .A(n86), .B(n90), .Y(n96) );
OR2X1TS U210 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
INVX8TS U211 ( .A(n356), .Y(n82) );
AND2X6TS U212 ( .A(n60), .B(n340), .Y(n13) );
NOR2X8TS U213 ( .A(n85), .B(in1[8]), .Y(n334) );
NOR2X6TS U214 ( .A(n263), .B(n261), .Y(n255) );
INVX6TS U215 ( .A(n79), .Y(n37) );
INVX6TS U216 ( .A(n273), .Y(n288) );
NOR2X4TS U217 ( .A(n324), .B(n329), .Y(n94) );
NOR2X4TS U218 ( .A(n153), .B(in1[19]), .Y(n281) );
XNOR2X4TS U219 ( .A(n142), .B(in2[19]), .Y(n145) );
NOR2X4TS U220 ( .A(n356), .B(in2[4]), .Y(n353) );
AOI21X2TS U221 ( .A0(n356), .A1(n15), .B0(n49), .Y(n48) );
MXI2X4TS U222 ( .A(n134), .B(n133), .S0(n201), .Y(n136) );
NOR2X8TS U223 ( .A(n50), .B(n57), .Y(n223) );
MXI2X4TS U224 ( .A(n86), .B(n84), .S0(n217), .Y(n85) );
NOR2X4TS U225 ( .A(n200), .B(in2[24]), .Y(n163) );
INVX16TS U226 ( .A(in2[5]), .Y(n69) );
NAND2BX4TS U227 ( .AN(n159), .B(n160), .Y(n171) );
NOR2X4TS U228 ( .A(n175), .B(in1[22]), .Y(n261) );
MXI2X4TS U229 ( .A(n90), .B(n89), .S0(n201), .Y(n91) );
XOR2X4TS U230 ( .A(n88), .B(in2[9]), .Y(n89) );
CLKINVX12TS U231 ( .A(n95), .Y(n102) );
NOR2X4TS U232 ( .A(n171), .B(in2[20]), .Y(n150) );
NAND2X4TS U233 ( .A(n160), .B(n147), .Y(n141) );
NOR2X2TS U234 ( .A(n275), .B(n276), .Y(n158) );
OAI21X2TS U235 ( .A0(n274), .A1(n276), .B0(n277), .Y(n36) );
NAND3X4TS U236 ( .A(n72), .B(n14), .C(n71), .Y(n73) );
INVX2TS U237 ( .A(in2[6]), .Y(n71) );
XOR2X1TS U238 ( .A(n86), .B(n95), .Y(n84) );
MXI2X4TS U239 ( .A(n97), .B(n87), .S0(n201), .Y(n92) );
MX2X4TS U240 ( .A(in2[17]), .B(n132), .S0(add_sub), .Y(n135) );
NAND2X4TS U241 ( .A(n85), .B(in1[8]), .Y(n335) );
INVX2TS U242 ( .A(n323), .Y(n333) );
INVX2TS U243 ( .A(n314), .Y(n322) );
NAND2X4TS U244 ( .A(n128), .B(in1[16]), .Y(n299) );
NOR2X4TS U245 ( .A(n176), .B(in1[23]), .Y(n263) );
NOR2X4TS U246 ( .A(n177), .B(in1[24]), .Y(n256) );
NOR2X4TS U247 ( .A(n193), .B(in1[26]), .Y(n236) );
INVX2TS U248 ( .A(n209), .Y(n225) );
NAND2X4TS U249 ( .A(n198), .B(n54), .Y(n51) );
INVX2TS U250 ( .A(n96), .Y(n100) );
INVX2TS U251 ( .A(in2[15]), .Y(n124) );
CLKINVX6TS U252 ( .A(in2[4]), .Y(n41) );
CLKAND2X2TS U253 ( .A(in2[5]), .B(add_sub), .Y(n15) );
INVX2TS U254 ( .A(in1[5]), .Y(n49) );
NAND2X1TS U255 ( .A(in2[4]), .B(add_sub), .Y(n67) );
INVX2TS U256 ( .A(in2[10]), .Y(n97) );
NAND2X2TS U257 ( .A(n180), .B(n255), .Y(n182) );
NAND2X4TS U258 ( .A(n34), .B(n76), .Y(n77) );
NAND2X1TS U259 ( .A(n83), .B(in2[7]), .Y(n76) );
NAND2X4TS U260 ( .A(n75), .B(n74), .Y(n34) );
MXI2X4TS U261 ( .A(n119), .B(n112), .S0(n201), .Y(n117) );
INVX4TS U262 ( .A(n44), .Y(n43) );
NOR2X2TS U263 ( .A(n305), .B(n311), .Y(n25) );
INVX2TS U264 ( .A(n306), .Y(n24) );
NOR2X4TS U265 ( .A(n136), .B(in1[18]), .Y(n138) );
INVX2TS U266 ( .A(n299), .Y(n129) );
INVX2TS U267 ( .A(n182), .Y(n54) );
INVX2TS U268 ( .A(n224), .Y(n212) );
INVX2TS U269 ( .A(n210), .Y(n211) );
NOR2X2TS U270 ( .A(n214), .B(n8), .Y(n55) );
INVX2TS U271 ( .A(n57), .Y(n20) );
NAND2X2TS U272 ( .A(n77), .B(in1[7]), .Y(n339) );
NAND2X2TS U273 ( .A(n117), .B(in1[14]), .Y(n306) );
NAND2X2TS U274 ( .A(n136), .B(in1[18]), .Y(n292) );
INVX2TS U275 ( .A(n138), .Y(n293) );
INVX2TS U276 ( .A(n281), .Y(n286) );
INVX2TS U277 ( .A(n282), .Y(n155) );
INVX2TS U278 ( .A(n285), .Y(n156) );
NAND2X2TS U279 ( .A(n286), .B(n61), .Y(n275) );
CLKBUFX2TS U280 ( .A(n272), .Y(n273) );
INVX2TS U281 ( .A(n261), .Y(n269) );
INVX2TS U282 ( .A(n268), .Y(n262) );
OAI21X1TS U283 ( .A0(n246), .A1(n256), .B0(n257), .Y(n247) );
NOR2X1TS U284 ( .A(n245), .B(n256), .Y(n248) );
INVX2TS U285 ( .A(n255), .Y(n245) );
NOR2XLTS U286 ( .A(n38), .B(in2[2]), .Y(n345) );
NAND2X1TS U287 ( .A(n30), .B(n342), .Y(n344) );
XNOR2X1TS U288 ( .A(n341), .B(n340), .Y(res[7]) );
NAND2X1TS U289 ( .A(n60), .B(n339), .Y(n341) );
NAND2X1TS U290 ( .A(n336), .B(n335), .Y(n337) );
INVX2TS U291 ( .A(n334), .Y(n336) );
NAND2X1TS U292 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U293 ( .A(n329), .Y(n331) );
NAND2X1TS U294 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U295 ( .A(n324), .Y(n326) );
NAND2X1TS U296 ( .A(n62), .B(n320), .Y(n321) );
AOI21X1TS U297 ( .A0(n322), .A1(n62), .B0(n315), .Y(n319) );
INVX2TS U298 ( .A(n320), .Y(n315) );
NAND2X1TS U299 ( .A(n312), .B(n311), .Y(n313) );
INVX2TS U300 ( .A(n310), .Y(n312) );
AOI21X1TS U301 ( .A0(n58), .A1(n297), .B0(n291), .Y(n295) );
INVX2TS U302 ( .A(n296), .Y(n291) );
XOR2XLTS U303 ( .A(n288), .B(n287), .Y(res[19]) );
XNOR2X1TS U304 ( .A(n284), .B(n283), .Y(res[20]) );
OAI21X1TS U305 ( .A0(n288), .A1(n281), .B0(n285), .Y(n284) );
XNOR2X1TS U306 ( .A(n280), .B(n279), .Y(res[21]) );
INVX2TS U307 ( .A(n276), .Y(n278) );
XNOR2X1TS U308 ( .A(n271), .B(n270), .Y(res[22]) );
XOR2X1TS U309 ( .A(n243), .B(n242), .Y(res[26]) );
INVX2TS U310 ( .A(n231), .Y(n233) );
NAND2X8TS U311 ( .A(n40), .B(n39), .Y(n38) );
OR2X4TS U312 ( .A(n95), .B(n96), .Y(n104) );
OR2X8TS U313 ( .A(n244), .B(n182), .Y(n35) );
AND2X4TS U314 ( .A(n37), .B(n348), .Y(n14) );
INVX12TS U315 ( .A(n38), .Y(n348) );
OAI21X4TS U316 ( .A0(n223), .A1(n209), .B0(n224), .Y(n208) );
AND2X8TS U317 ( .A(n102), .B(n101), .Y(n10) );
INVX2TS U318 ( .A(n22), .Y(n302) );
INVX2TS U319 ( .A(n42), .Y(n314) );
OR2X4TS U320 ( .A(n123), .B(in1[15]), .Y(n16) );
NAND3X8TS U321 ( .A(n17), .B(n23), .C(n26), .Y(n22) );
NAND2X8TS U322 ( .A(n27), .B(n42), .Y(n17) );
MX2X4TS U323 ( .A(in2[13]), .B(n115), .S0(add_sub), .Y(n116) );
OA21X4TS U324 ( .A0(n20), .A1(n214), .B0(n213), .Y(n52) );
NAND2X8TS U325 ( .A(n21), .B(n303), .Y(n301) );
NAND2X8TS U326 ( .A(n16), .B(n22), .Y(n21) );
NAND2X4TS U327 ( .A(n43), .B(n118), .Y(n26) );
NOR2X8TS U328 ( .A(n78), .B(n13), .Y(n338) );
NAND2X8TS U329 ( .A(n35), .B(n181), .Y(n228) );
AOI21X4TS U330 ( .A0(n272), .A1(n158), .B0(n36), .Y(n244) );
OAI21X4TS U331 ( .A0(n289), .A1(n140), .B0(n139), .Y(n272) );
INVX16TS U332 ( .A(in2[1]), .Y(n39) );
INVX16TS U333 ( .A(in2[0]), .Y(n40) );
NAND2X4TS U334 ( .A(n56), .B(n221), .Y(res[32]) );
NOR2X4TS U335 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
MX2X4TS U336 ( .A(in2[11]), .B(n106), .S0(n201), .Y(n107) );
XOR2X4TS U337 ( .A(n172), .B(in2[22]), .Y(n173) );
XNOR2X4TS U338 ( .A(n167), .B(n168), .Y(n169) );
MXI2X4TS U339 ( .A(n166), .B(n165), .S0(n217), .Y(n177) );
AO21X4TS U340 ( .A0(n323), .A1(n94), .B0(n93), .Y(n42) );
NOR2X8TS U341 ( .A(n45), .B(n109), .Y(n44) );
NAND2X8TS U342 ( .A(n348), .B(n72), .Y(n356) );
NOR2X8TS U343 ( .A(in2[3]), .B(in2[2]), .Y(n72) );
OAI22X4TS U344 ( .A0(n51), .A1(n244), .B0(n181), .B1(n8), .Y(n50) );
NAND2X8TS U345 ( .A(n53), .B(n52), .Y(n222) );
NAND2X8TS U346 ( .A(n228), .B(n55), .Y(n53) );
OAI21X4TS U347 ( .A0(n229), .A1(n231), .B0(n232), .Y(n57) );
XOR2X1TS U348 ( .A(n253), .B(n252), .Y(res[25]) );
XOR2X1TS U349 ( .A(n267), .B(n266), .Y(res[23]) );
XOR2X1TS U350 ( .A(n260), .B(n259), .Y(res[24]) );
XNOR2X1TS U351 ( .A(n344), .B(n343), .Y(res[6]) );
XNOR2X4TS U352 ( .A(in2[14]), .B(n125), .Y(n112) );
XNOR2X1TS U353 ( .A(n301), .B(n300), .Y(res[16]) );
XNOR2X4TS U354 ( .A(n105), .B(in2[11]), .Y(n106) );
XOR2XLTS U355 ( .A(n338), .B(n337), .Y(res[8]) );
XOR2X4TS U356 ( .A(n10), .B(in2[12]), .Y(n103) );
NAND2X4TS U357 ( .A(n70), .B(in1[6]), .Y(n342) );
INVX2TS U358 ( .A(n83), .Y(n74) );
XOR2X4TS U359 ( .A(n73), .B(in2[7]), .Y(n75) );
NOR2BX4TS U360 ( .AN(n80), .B(n79), .Y(n81) );
NAND2X8TS U361 ( .A(n82), .B(n81), .Y(n95) );
OAI21X4TS U362 ( .A0(n338), .A1(n334), .B0(n335), .Y(n323) );
NOR2X8TS U363 ( .A(n92), .B(in1[10]), .Y(n324) );
OAI21X4TS U364 ( .A0(n324), .A1(n330), .B0(n325), .Y(n93) );
INVX2TS U365 ( .A(in2[11]), .Y(n98) );
INVX2TS U366 ( .A(in2[12]), .Y(n113) );
MXI2X4TS U367 ( .A(n103), .B(n113), .S0(n83), .Y(n108) );
NAND2X8TS U368 ( .A(n10), .B(n120), .Y(n125) );
XOR2X4TS U369 ( .A(n114), .B(in2[13]), .Y(n115) );
NOR2X8TS U370 ( .A(n116), .B(in1[13]), .Y(n310) );
NOR2X8TS U371 ( .A(n305), .B(n310), .Y(n118) );
NAND3X1TS U372 ( .A(n120), .B(n10), .C(n119), .Y(n121) );
XOR2X1TS U373 ( .A(n121), .B(in2[15]), .Y(n122) );
INVX2TS U374 ( .A(in2[16]), .Y(n127) );
XOR2X1TS U375 ( .A(in2[16]), .B(n160), .Y(n126) );
AOI21X4TS U376 ( .A0(n301), .A1(n63), .B0(n129), .Y(n289) );
INVX2TS U377 ( .A(n160), .Y(n130) );
INVX2TS U378 ( .A(in2[18]), .Y(n134) );
AOI2BB1X4TS U379 ( .A0N(n296), .A1N(n138), .B0(n137), .Y(n139) );
OAI2BB1X4TS U380 ( .A0N(add_sub), .A1N(n145), .B0(n144), .Y(n153) );
INVX2TS U381 ( .A(in2[20]), .Y(n149) );
MXI2X4TS U382 ( .A(n149), .B(n148), .S0(n217), .Y(n154) );
INVX2TS U383 ( .A(in2[21]), .Y(n151) );
AOI21X4TS U384 ( .A0(n156), .A1(n61), .B0(n155), .Y(n274) );
INVX2TS U385 ( .A(in2[25]), .Y(n162) );
INVX2TS U386 ( .A(in2[24]), .Y(n166) );
NOR3X4TS U387 ( .A(n171), .B(in2[22]), .C(n170), .Y(n167) );
MXI2X4TS U388 ( .A(n169), .B(n168), .S0(n83), .Y(n176) );
INVX2TS U389 ( .A(in2[22]), .Y(n174) );
MXI2X4TS U390 ( .A(n174), .B(n173), .S0(n201), .Y(n175) );
OAI21X4TS U391 ( .A0(n263), .A1(n268), .B0(n264), .Y(n254) );
AOI21X4TS U392 ( .A0(n254), .A1(n180), .B0(n179), .Y(n181) );
NAND2X2TS U393 ( .A(n183), .B(n187), .Y(n184) );
MXI2X4TS U394 ( .A(n186), .B(n185), .S0(n201), .Y(n193) );
XNOR2X1TS U395 ( .A(n191), .B(in2[28]), .Y(n192) );
MX2X4TS U396 ( .A(in2[28]), .B(n192), .S0(n217), .Y(n197) );
AOI21X4TS U397 ( .A0(n196), .A1(n59), .B0(n195), .Y(n229) );
XNOR2X1TS U398 ( .A(n204), .B(in2[29]), .Y(n202) );
XOR2X1TS U399 ( .A(n215), .B(in2[30]), .Y(n205) );
XNOR2X2TS U400 ( .A(n208), .B(n207), .Y(res[30]) );
XNOR2X4TS U401 ( .A(n222), .B(n220), .Y(res[31]) );
INVX2TS U402 ( .A(n223), .Y(n227) );
INVX12TS U403 ( .A(n228), .Y(n243) );
OAI21X4TS U404 ( .A0(n243), .A1(n230), .B0(n229), .Y(n235) );
XNOR2X4TS U405 ( .A(n235), .B(n234), .Y(res[28]) );
OAI21X4TS U406 ( .A0(n243), .A1(n236), .B0(n240), .Y(n239) );
XNOR2X4TS U407 ( .A(n239), .B(n238), .Y(res[27]) );
INVX2TS U408 ( .A(n254), .Y(n246) );
AOI21X4TS U409 ( .A0(n271), .A1(n248), .B0(n247), .Y(n253) );
AOI21X4TS U410 ( .A0(n271), .A1(n255), .B0(n254), .Y(n260) );
AOI21X4TS U411 ( .A0(n271), .A1(n269), .B0(n262), .Y(n267) );
XNOR2X1TS U412 ( .A(n298), .B(n297), .Y(res[17]) );
XNOR2X1TS U413 ( .A(n309), .B(n308), .Y(res[14]) );
XNOR2X1TS U414 ( .A(n322), .B(n321), .Y(res[11]) );
XNOR2X1TS U415 ( .A(n328), .B(n327), .Y(res[10]) );
XOR2X1TS U416 ( .A(n345), .B(in2[3]), .Y(n347) );
AOI21X1TS U417 ( .A0(n143), .A1(in2[3]), .B0(in1[3]), .Y(n346) );
XOR2X1TS U418 ( .A(in2[2]), .B(n348), .Y(n350) );
AOI21X1TS U419 ( .A0(n143), .A1(in2[2]), .B0(in1[2]), .Y(n349) );
XNOR2X1TS U420 ( .A(in2[0]), .B(in2[1]), .Y(n352) );
AOI21X1TS U421 ( .A0(n83), .A1(in2[1]), .B0(in1[1]), .Y(n351) );
XOR2X1TS U422 ( .A(n353), .B(in2[5]), .Y(n355) );
AOI21X1TS U423 ( .A0(n143), .A1(in2[5]), .B0(in1[5]), .Y(n354) );
XNOR2X1TS U424 ( .A(in2[4]), .B(n356), .Y(n358) );
AOI21X1TS U425 ( .A0(n143), .A1(in2[4]), .B0(in1[4]), .Y(n357) );
initial $sdf_annotate("Approx_adder_LOALPL6_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
|
//PROYECTO ELECTRICO
//Autor : Jose Johel Rodriguez Pineda
//DbC maquina de estados
//
`include "Defintions.v"
//`timescale 1ns / 1ps
//------------------------------------------------
module DbCPortStatMachine
(
input wire clock ,
input wire DCI ,
input wire CSC ,
input wire PLC ,
input wire PRC ,
input wire DCE ,
input wire PED ,
input wire CEC ,
input wire Reset_rcvd,
input wire set_config_succesful,
input wire EnumError,
input wire Deconfigure
);
reg [4:0] rstate;
reg [4:0] rNew_state;
always @ (posedge clock)
begin : FSM_SEQ
if (DCE == 1'b0) begin
rstate = #1 `DBC_OFF;
end else begin
rstate = #1 rNew_state;
end
end
always @ (posedge clock)
begin
if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else
case(rstate)
`DBC_OFF : if (DCE == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else begin
rNew_state = `DBC_OFF;
end
`DBC_DISCONNECTED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_DISCONNECTED;
end
`DBC_DISABLED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_DISABLED;
end
`DBC_ENABLED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (CEC == 1'b1 || PLC == 1'b1) begin
rNew_state = `DBC_DISABLED;
end else if (EnumError == 1'b1) begin
rNew_state = `DBC_ERROR;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else if (set_config_succesful == 1'b1) begin
rNew_state = `DBC_CONFIURED;
end else begin
rNew_state = `DBC_ENABLED;
end
`DBC_RESETTING : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (PRC == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_OFF;
end
`DBC_ERROR : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else begin
rNew_state = `DBC_ERROR;
end
`DBC_CONFIURED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else if (Deconfigure == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_CONFIURED;
end
default : rNew_state = `DBC_OFF;
endcase
end
endmodule
/*`define DBC_DISABLED 5'b11000
`define DBC_OFF 5'b00000
`define DBC_DISCONNECTED 5'b10000
`define DBC_ERROR 5'b11000
`define DBC_RESETTING 5'b11010
`define DBC_CONFIURED 5'b11101
*/
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:31:50 03/07/2016
// Design Name: mult4
// Module Name: C:/XilinxP/Practica1/mult4s_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mult4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Test para Multiplicador de 4 bits con signo, Practica 2
module mult4s_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg x4;
reg y0;
reg y1;
reg y2;
reg y3;
reg y4;
// Outputs
wire z0;
wire z1;
wire z2;
wire z3;
wire z4;
wire z5;
wire z6;
wire z7;
wire z8;
// Instantiate the Unit Under Test (UUT)
mult4s uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4),
.z0(z0),
.z1(z1),
.z2(z2),
.z3(z3),
.z4(z4),
.z5(z5),
.z6(z6),
.z7(z7),
.z8(z8)
);
initial begin
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
x4 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
y4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 0; y4 = 0; //1011 * 0101
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 1; y4 = 0; //1010 * 1101
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 0; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //1111 * 1110
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 1; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //1111 * 1111
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; x4 = 0; y0 = 0; y1 = 0; y2 = 1; y3 = 0; y4 = 1; //1000 * -0100
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //1010 * -0001
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 0; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //1111 * -0000
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; x4 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 1; y4 = 1; //0110 * -1001
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 0; x3 = 1; x4 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 0; y4 = 0; //-1011 * 0101
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 1; y4 = 0; //-1010 * 1101
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 1; y0 = 0; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //-1111 * 1110
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 1; y0 = 1; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //-1111 * 1111
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; y4 = 1; //-1000 * -0100
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);;
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //-1010 * -0001
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //-1111 * -0000
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 1; y4 = 1; //-0110 * -1001
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b%b%b%b%b", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z8, z7, z6, z5, z4, z3, z2, z1, z0);
end
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Missing pin: VPA
// All address decoding was checked except BITW1, nCTRL1_ZONE, and nCTRL2_ZONE
module neo_c1(
input [21:17] M68K_ADDR,
output [15:8] M68K_DATA,
input A22Z, A23Z,
input nLDS, nUDS,
input RW, nAS,
output nROMOEL, nROMOEU,
output nPORTOEL, nPORTOEU,
output nPORTWEL, nPORTWEU,
output nPORT_ZONE,
output nWRL, nWRU,
output nWWL, nWWU,
output nSROMOEL, nSROMOEU,
output nSRAMOEL, nSRAMOEU,
output nSRAMWEL, nSRAMWEU,
output nLSPOE, nLSPWE,
output nCRDO, nCRDW, nCRDC,
output nSDW,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nCD1, nCD2, nWP,
input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
inout [7:0] SDD,
input nSDZ80R, nSDZ80W, nSDZ80CLR,
input CLK_68KCLK,
output nDTACK,
output nBITW0, nBITW1, nDIPRD0, nDIPRD1,
output nPAL_ZONE,
input SYSTEM_MODE
);
wire nIO_ZONE; // Internal
wire nC1REGS_ZONE; // Internal
wire nROM_ZONE; // Internal
wire nWRAM_ZONE; // Internal (external for PCB)
wire nPORT_ZONE; // Internal (external for PCB)
wire nCTRL1_ZONE; // Internal (external for PCB)
wire nICOM_ZONE; // Internal
wire nCTRL2_ZONE; // Internal (external for PCB)
wire nSTATUSB_ZONE; // Internal (external for PCB)
wire nLSPC_ZONE; // Internal
wire nCARD_ZONE; // Internal
wire nSROM_ZONE; // Internal
wire nSRAM_ZONE; // Internal (external for PCB)
c1_regs C1REGS(nICOM_ZONE, RW, M68K_DATA, SDD, nSDZ80R, nSDZ80W, nSDZ80CLR, nSDW);
c1_wait C1WAIT(CLK_68KCLK, nAS, nROM_ZONE, nPORT_ZONE, nCARD_ZONE, nROMWAIT, nPWAIT0,
nPWAIT1, PDTACK, nDTACK);
c1_inputs C1INPUTS(nCTRL1_ZONE, nCTRL2_ZONE, nSTATUSB_ZONE, M68K_DATA, P1_IN[9:0], P2_IN[9:0],
nWP, nCD2, nCD1, SYSTEM_MODE);
// 000000~0FFFFF read/write
assign nROM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], M68K_ADDR[20]};
// 100000~1FFFFF read/write
assign nWRAM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], ~M68K_ADDR[20]};
// 200000~2FFFFF read/write
assign nPORT_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], M68K_ADDR[20]};
// 300000~3FFFFF read/write
assign nIO_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], ~M68K_ADDR[20]};
// 300000~3FFFFE even bytes read/write
assign nC1REGS_ZONE = nUDS | nIO_ZONE;
// 300000~31FFFE even bytes read only
assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 320000~33FFFE even bytes read/write
assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]};
// 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below
assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 360000~37FFFF is not mapped ?
// 30xxxx 31xxxx odd bytes read only
assign nDIPRD0 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], ~RW, nLDS};
// 32xxxx 33xxxx odd bytes read only
assign nDIPRD1 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17], ~RW, nLDS};
// 38xxxx 39xxxx odd bytes write only
assign nBITW0 = |{nIO_ZONE, ~M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], RW, nLDS};
// 380000~39FFFE even bytes read only
assign nSTATUSB_ZONE = nC1REGS_ZONE | ~RW | |{~M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 3A0001~3BFFFF odd bytes write only
assign nBITW1 = |{nIO_ZONE, ~M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17], RW, nLDS};
// 3C0000~3DFFFF
assign nLSPC_ZONE = |{nIO_ZONE, ~M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 3E0000~3FFFFF is not mapped ? To check
// 400000~7FFFFF
assign nPAL_ZONE = |{A23Z, ~A22Z, (nLDS & nUDS)};
// 800000~BFFFFF
assign nCARD_ZONE = |{~A23Z, A22Z};
// C00000~CFFFFF
assign nSROM_ZONE = |{~A23Z, ~A22Z, M68K_ADDR[21], M68K_ADDR[20]};
// D00000~DFFFFF
assign nSRAM_ZONE = |{~A23Z, ~A22Z, M68K_ADDR[21], ~M68K_ADDR[20]};
// Outputs:
assign nROMOEL = ~RW | nLDS | nROM_ZONE;
assign nROMOEU = ~RW | nUDS | nROM_ZONE;
assign nPORTOEL = ~RW | nLDS | nPORT_ZONE;
assign nPORTOEU = ~RW | nUDS | nPORT_ZONE;
assign nPORTWEL = RW | nLDS | nPORT_ZONE;
assign nPORTWEU = RW | nUDS | nPORT_ZONE;
assign nWRL = ~RW | nLDS | nWRAM_ZONE;
assign nWRU = ~RW | nUDS | nWRAM_ZONE;
assign nWWL = RW | nLDS | nWRAM_ZONE;
assign nWWU = RW | nUDS | nWRAM_ZONE;
assign nSROMOEL = ~RW | nLDS | nSROM_ZONE;
assign nSROMOEU = ~RW | nUDS | nSROM_ZONE;
assign nSRAMOEL = ~RW | nLDS | nSRAM_ZONE;
assign nSRAMOEU = ~RW | nUDS | nSRAM_ZONE;
assign nSRAMWEL = RW | nLDS | nSRAM_ZONE;
assign nSRAMWEU = RW | nUDS | nSRAM_ZONE;
// Todo: Check if TG68k duplicates byte on data bus on byte writes (it should !)
assign nLSPWE = RW | nUDS | nLSPC_ZONE;
assign nLSPOE = ~RW | nUDS | nLSPC_ZONE;
assign nCRDO = ~RW | nCARD_ZONE | nUDS;
assign nCRDW = RW | nCARD_ZONE | nUDS;
assign nCRDC = nCARD_ZONE | nAS;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*
* SVN revision information:
* $Rev:: $:
* $Author:: $:
* $Date:: $:
*
* Initial version: M. Lemarenko
*/
module uart_master(
input UART_CLK_X4,
input UART_RST,
input UART_RX,
output UART_TX,
inout [7:0] BUS_DATA,
output reg [31:0] BUS_ADD,
output reg BUS_WR,
output reg BUS_RD
);
wire clk;
assign clk = UART_CLK_X4;
wire [7:0] data_i;
reg [7:0] data_o;
assign data_i = BUS_DATA;
assign BUS_DATA = BUS_WR ? data_o : 8'bzzzz_zzzz;
reg [7:0] tx_byte;
wire [7:0] rx_byte;
wire is_receiving, is_transmitting, recv_error,received;
reg transmit;
uart u_uart(
// Inputs
.clk_uart_x4(clk),
.rst(UART_RST),
.rx(UART_RX),
.transmit(transmit),
.tx_byte(tx_byte),
// Outputs
.tx(UART_TX),
.received(received),
.rx_byte(rx_byte),
.is_receiving(is_receiving),
.is_transmitting(is_transmitting),
.recv_error(recv_error)
);
integer i;
reg [4:0] STATE, NEXTSTATE;
reg [31:0] cnt;
wire [31:0] block_len;
reg [7:0] block_len_0[3:0];
reg op_done;
wire [31:0] address_0;
reg [7:0] address_0_0[3:0];
//reg [7:0] test_mem [255:0];
wire[7:0] roger_word [2:0];
assign block_len = {block_len_0[3], block_len_0[2], block_len_0[1],block_len_0[0]};
assign address_0 = {address_0_0[3], address_0_0[2], address_0_0[1],address_0_0[0]};
assign roger_word[0] = {8'h4f}; // "OK\n"
assign roger_word[1] = {8'h4B}; // "OK\n"
assign roger_word[2] = {8'h0D}; // "OK\n"
localparam IDLE = 0, //idle :)
SET_LEN = 1, //sets the length of the block to be read
SET_ADD = 2, //sets the start address
READ = 3, //reads a block of mem
WRITE = 4, //writes a block of mem
ROGER = 5; //confirms the reception
////////////////////////////// TAKTBLOCK /////////////////////////////////////
always @(posedge clk or posedge UART_RST)
if (UART_RST) begin
STATE <= IDLE;
end
else begin
STATE <= NEXTSTATE;
end
// END ALWAYS
////////////////////////////// Kombinatorischer Block /////////////////////////////////////
assign uart_busy = is_receiving || is_transmitting;
//reset counter:
//reg rst_counter[31:0];
//
//always @(posedge clk) begin
// rst_counter <= rst_counter + 1;
// if(UART_RST or recv_error) begin
// rst_counter <= 0;
// end
//end
always @* begin
NEXTSTATE = IDLE;
//if (!uart_busy)
case (STATE)
IDLE: begin
if (received) begin
if (rx_byte ==8'h6c) begin // ascii "l"
$write(".........set length\n");
NEXTSTATE = SET_LEN;
end else if (rx_byte ==8'h61) begin // ascii "a"
NEXTSTATE = SET_ADD;
$write(".........set address\n");
end else if (rx_byte==8'h72) begin // ascii "r"
NEXTSTATE = READ;
$write(".........read\n");
end else if (rx_byte==8'h77) begin // ascii "w"
NEXTSTATE = WRITE;
$write(".........write\n");
end else
NEXTSTATE = IDLE;
end
end
SET_LEN:begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = SET_LEN;
end
SET_ADD:begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = SET_ADD;
end
READ: begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = READ;
end
WRITE: begin
if ((!uart_busy)&&op_done)
NEXTSTATE = ROGER;
else
NEXTSTATE = WRITE;
end
ROGER: begin
if ((!uart_busy)&&op_done) begin
NEXTSTATE = IDLE;
$write("ROGER\n");
end else
NEXTSTATE = ROGER;
end
default: begin
NEXTSTATE = IDLE;
end
endcase
end // END ALWAYS
////////////////////////////// Anweisungsblock /////////////////////////////////////
wire new_state_strobe;
assign new_state_strobe = (STATE != NEXTSTATE);
//assign add = address_0+cnt;
always @(posedge clk or posedge UART_RST)
if (UART_RST) begin
cnt <= 0;
op_done <= 0;
transmit <= 0;
BUS_WR <= 0;
BUS_RD <= 0;
address_0_0[3] <= 0;
address_0_0[2] <= 0;
address_0_0[1] <= 0;
address_0_0[0] <= 0;
block_len_0[3] <= 0;
block_len_0[2] <= 0;
block_len_0[1] <= 0;
block_len_0[0] <= 1;
end else if (new_state_strobe) begin
op_done <= 0;
cnt <= 0;
BUS_WR <= 0;
transmit <= 0;
BUS_RD <= 0;
end else begin
case (STATE)
IDLE: begin
end
SET_LEN:begin
if (cnt > 3)
op_done <=1;
else if (received) begin
$write("setting the length byte %d to value %d\n",cnt,rx_byte);
block_len_0[cnt] <= rx_byte;
cnt <= cnt+1;
end
end
SET_ADD:begin
if (cnt > 3)
op_done <=1;
else if (received) begin
$write("setting the address byte %d to value %d\n",cnt,rx_byte);
address_0_0[cnt] <= rx_byte;
cnt <= cnt+1;
end
end
READ: begin
//slow down the clk by 4 to get enogh time to update the value
//hence cnt/4 and cnt[1:0]==3
if(is_transmitting)
transmit <= 0;
else if (cnt/4 >= block_len)
op_done <= 1;
else if ((!is_transmitting)&&(!transmit)) begin
if (cnt[1:0]==3) begin
// $write("transmitting the byte %d of value %d\n",cnt/4,tx_byte);
transmit <= 1;
end
tx_byte <= data_i;
BUS_ADD <= address_0+cnt/4;
cnt <= cnt + 1;
BUS_RD <= 1;
end
end
WRITE: begin
if (cnt >= block_len)
op_done <=1;
else if (received) begin
$write("setting the byte %d to value %d\n",cnt,rx_byte);
//test_mem[address_0+cnt] <= rx_byte;
BUS_ADD <= address_0+cnt;
BUS_WR <= 1;
cnt <= cnt + 1;
data_o <= rx_byte;
end
end
ROGER: begin
if(is_transmitting)
transmit <= 0;
else if (cnt > 2) begin
op_done <=1;
end else if ((!is_transmitting)&&(!transmit)) begin
tx_byte <= roger_word[cnt];
cnt <= cnt + 1;
transmit <= 1;
end
end
default: begin
end
endcase // STATE
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1499934493 : 255;
endmodule
|
/* Generated by Yosys 0.4+19 (git sha1 abf81d7, clang 3.4-1ubuntu3 -fPIC -Os) */
(* src = "../lib/mux_2to1.v:1" *)
module mux_2to1(i1, i0, s, z);
(* src = "../lib/mux_2to1.v:2" *)
input i1;
(* src = "../lib/mux_2to1.v:2" *)
input i0;
(* src = "../lib/mux_2to1.v:2" *)
input s;
(* src = "../lib/mux_2to1.v:3" *)
output z;
(* src = "../lib/mux_2to1.v:5" *)
wire int0;
(* src = "../lib/mux_2to1.v:5" *)
wire int1;
(* src = "../lib/mux_2to1.v:5" *)
wire s_bar;
assign z = int0 | int1;
assign int1 = i1 & s;
assign int0 = i0 & s_bar;
assign s_bar = ~s;
endmodule
(* src = "../lib/flip_flop.v:3" *)
module d_flip_flop(d, clk, we, q, q_bar);
(* src = "../lib/flip_flop.v:7" *)
wire int0;
(* src = "../lib/flip_flop.v:7" *)
wire int1;
(* src = "../lib/flip_flop.v:4" *)
input d;
(* src = "../lib/flip_flop.v:4" *)
input clk;
(* src = "../lib/flip_flop.v:4" *)
input we;
(* src = "../lib/flip_flop.v:5" *)
output q;
(* src = "../lib/flip_flop.v:5" *)
output q_bar;
(* src = "../lib/flip_flop.v:7" *)
wire ff_input;
(* src = "../lib/flip_flop.v:15" *)
wire _00_;
(* src = "../lib/flip_flop.v:15" *)
wire _01_;
(* src = "../lib/flip_flop.v:16" *)
wire _02_;
(* src = "../lib/flip_flop.v:18" *)
wire _03_;
(* src = "../lib/flip_flop.v:19" *)
wire _04_;
(* src = "../lib/flip_flop.v:9" *)
mux_2to1 mux (
.i1(d),
.i0(q),
.s(we),
.z(ff_input)
);
assign q_bar = ~_04_;
assign _04_ = int1 & q;
assign q = ~_03_;
assign _03_ = int0 & q_bar;
assign int1 = ~_02_;
assign _02_ = int0 & _00_;
assign int0 = ~_01_;
assign _01_ = ff_input & _00_;
assign _00_ = ~clk;
endmodule
(* src = "../RF/reg_32bits.v:3" *)
module reg_32bits(d, we, clk, q);
(* src = "../RF/reg_32bits.v:4" *)
input [31:0] d;
(* src = "../RF/reg_32bits.v:5" *)
input clk;
(* src = "../RF/reg_32bits.v:5" *)
input we;
(* src = "../RF/reg_32bits.v:6" *)
output [31:0] q;
(* src = "../RF/reg_32bits.v:8" *)
d_flip_flop dff0 (
.d(d[0]),
.clk(clk),
.we(we),
.q(q[0])
);
(* src = "../RF/reg_32bits.v:9" *)
d_flip_flop dff1 (
.d(d[1]),
.clk(clk),
.we(we),
.q(q[1])
);
(* src = "../RF/reg_32bits.v:10" *)
d_flip_flop dff2 (
.d(d[2]),
.clk(clk),
.we(we),
.q(q[2])
);
(* src = "../RF/reg_32bits.v:11" *)
d_flip_flop dff3 (
.d(d[3]),
.clk(clk),
.we(we),
.q(q[3])
);
(* src = "../RF/reg_32bits.v:12" *)
d_flip_flop dff4 (
.d(d[4]),
.clk(clk),
.we(we),
.q(q[4])
);
(* src = "../RF/reg_32bits.v:13" *)
d_flip_flop dff5 (
.d(d[5]),
.clk(clk),
.we(we),
.q(q[5])
);
(* src = "../RF/reg_32bits.v:14" *)
d_flip_flop dff6 (
.d(d[6]),
.clk(clk),
.we(we),
.q(q[6])
);
(* src = "../RF/reg_32bits.v:15" *)
d_flip_flop dff7 (
.d(d[7]),
.clk(clk),
.we(we),
.q(q[7])
);
(* src = "../RF/reg_32bits.v:16" *)
d_flip_flop dff8 (
.d(d[8]),
.clk(clk),
.we(we),
.q(q[8])
);
(* src = "../RF/reg_32bits.v:17" *)
d_flip_flop dff9 (
.d(d[9]),
.clk(clk),
.we(we),
.q(q[9])
);
(* src = "../RF/reg_32bits.v:18" *)
d_flip_flop dff10 (
.d(d[10]),
.clk(clk),
.we(we),
.q(q[10])
);
(* src = "../RF/reg_32bits.v:19" *)
d_flip_flop dff11 (
.d(d[11]),
.clk(clk),
.we(we),
.q(q[11])
);
(* src = "../RF/reg_32bits.v:20" *)
d_flip_flop dff12 (
.d(d[12]),
.clk(clk),
.we(we),
.q(q[12])
);
(* src = "../RF/reg_32bits.v:21" *)
d_flip_flop dff13 (
.d(d[13]),
.clk(clk),
.we(we),
.q(q[13])
);
(* src = "../RF/reg_32bits.v:22" *)
d_flip_flop dff14 (
.d(d[14]),
.clk(clk),
.we(we),
.q(q[14])
);
(* src = "../RF/reg_32bits.v:23" *)
d_flip_flop dff15 (
.d(d[15]),
.clk(clk),
.we(we),
.q(q[15])
);
(* src = "../RF/reg_32bits.v:24" *)
d_flip_flop dff16 (
.d(d[16]),
.clk(clk),
.we(we),
.q(q[16])
);
(* src = "../RF/reg_32bits.v:25" *)
d_flip_flop dff17 (
.d(d[17]),
.clk(clk),
.we(we),
.q(q[17])
);
(* src = "../RF/reg_32bits.v:26" *)
d_flip_flop dff18 (
.d(d[18]),
.clk(clk),
.we(we),
.q(q[18])
);
(* src = "../RF/reg_32bits.v:27" *)
d_flip_flop dff19 (
.d(d[19]),
.clk(clk),
.we(we),
.q(q[19])
);
(* src = "../RF/reg_32bits.v:28" *)
d_flip_flop dff20 (
.d(d[20]),
.clk(clk),
.we(we),
.q(q[20])
);
(* src = "../RF/reg_32bits.v:29" *)
d_flip_flop dff21 (
.d(d[21]),
.clk(clk),
.we(we),
.q(q[21])
);
(* src = "../RF/reg_32bits.v:30" *)
d_flip_flop dff22 (
.d(d[22]),
.clk(clk),
.we(we),
.q(q[22])
);
(* src = "../RF/reg_32bits.v:31" *)
d_flip_flop dff23 (
.d(d[23]),
.clk(clk),
.we(we),
.q(q[23])
);
(* src = "../RF/reg_32bits.v:32" *)
d_flip_flop dff24 (
.d(d[24]),
.clk(clk),
.we(we),
.q(q[24])
);
(* src = "../RF/reg_32bits.v:33" *)
d_flip_flop dff25 (
.d(d[25]),
.clk(clk),
.we(we),
.q(q[25])
);
(* src = "../RF/reg_32bits.v:34" *)
d_flip_flop dff26 (
.d(d[26]),
.clk(clk),
.we(we),
.q(q[26])
);
(* src = "../RF/reg_32bits.v:35" *)
d_flip_flop dff27 (
.d(d[27]),
.clk(clk),
.we(we),
.q(q[27])
);
(* src = "../RF/reg_32bits.v:36" *)
d_flip_flop dff28 (
.d(d[28]),
.clk(clk),
.we(we),
.q(q[28])
);
(* src = "../RF/reg_32bits.v:37" *)
d_flip_flop dff29 (
.d(d[29]),
.clk(clk),
.we(we),
.q(q[29])
);
(* src = "../RF/reg_32bits.v:38" *)
d_flip_flop dff30 (
.d(d[30]),
.clk(clk),
.we(we),
.q(q[30])
);
(* src = "../RF/reg_32bits.v:39" *)
d_flip_flop dff31 (
.d(d[31]),
.clk(clk),
.we(we),
.q(q[31])
);
endmodule
(* src = "../lib/mux_32to1.v:1" *)
module mux_32to1(s, i31, i30, i29, i28, i27, i26, i25, i24, i23, i22, i21, i20, i19, i18, i17, i16, i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0, z);
(* src = "../lib/mux_32to1.v:4" *)
input i1;
(* src = "../lib/mux_32to1.v:4" *)
input i0;
(* src = "../lib/mux_32to1.v:2" *)
input [4:0] s;
(* src = "../lib/mux_32to1.v:5" *)
output z;
(* src = "../lib/mux_32to1.v:7" *)
wire int0;
(* src = "../lib/mux_32to1.v:7" *)
wire int1;
(* src = "../lib/mux_32to1.v:3" *)
input i31;
(* src = "../lib/mux_32to1.v:3" *)
input i30;
(* src = "../lib/mux_32to1.v:3" *)
input i29;
(* src = "../lib/mux_32to1.v:3" *)
input i28;
(* src = "../lib/mux_32to1.v:3" *)
input i27;
(* src = "../lib/mux_32to1.v:3" *)
input i26;
(* src = "../lib/mux_32to1.v:3" *)
input i25;
(* src = "../lib/mux_32to1.v:3" *)
input i24;
(* src = "../lib/mux_32to1.v:3" *)
input i23;
(* src = "../lib/mux_32to1.v:3" *)
input i22;
(* src = "../lib/mux_32to1.v:3" *)
input i21;
(* src = "../lib/mux_32to1.v:3" *)
input i20;
(* src = "../lib/mux_32to1.v:3" *)
input i19;
(* src = "../lib/mux_32to1.v:3" *)
input i18;
(* src = "../lib/mux_32to1.v:3" *)
input i17;
(* src = "../lib/mux_32to1.v:3" *)
input i16;
(* src = "../lib/mux_32to1.v:4" *)
input i15;
(* src = "../lib/mux_32to1.v:4" *)
input i14;
(* src = "../lib/mux_32to1.v:4" *)
input i13;
(* src = "../lib/mux_32to1.v:4" *)
input i12;
(* src = "../lib/mux_32to1.v:4" *)
input i11;
(* src = "../lib/mux_32to1.v:4" *)
input i10;
(* src = "../lib/mux_32to1.v:4" *)
input i9;
(* src = "../lib/mux_32to1.v:4" *)
input i8;
(* src = "../lib/mux_32to1.v:4" *)
input i7;
(* src = "../lib/mux_32to1.v:4" *)
input i6;
(* src = "../lib/mux_32to1.v:4" *)
input i5;
(* src = "../lib/mux_32to1.v:4" *)
input i4;
(* src = "../lib/mux_32to1.v:4" *)
input i3;
(* src = "../lib/mux_32to1.v:4" *)
input i2;
(* src = "../lib/mux_32to1.v:7" *)
wire int2;
(* src = "../lib/mux_32to1.v:7" *)
wire int3;
(* src = "../lib/mux_32to1.v:7" *)
wire int4;
(* src = "../lib/mux_32to1.v:7" *)
wire int5;
(* src = "../lib/mux_32to1.v:7" *)
wire int6;
(* src = "../lib/mux_32to1.v:7" *)
wire int7;
(* src = "../lib/mux_32to1.v:8" *)
wire int8;
(* src = "../lib/mux_32to1.v:8" *)
wire int9;
(* src = "../lib/mux_32to1.v:8" *)
wire int10;
(* src = "../lib/mux_32to1.v:8" *)
wire int11;
(* src = "../lib/mux_32to1.v:8" *)
wire int12;
(* src = "../lib/mux_32to1.v:8" *)
wire int13;
(* src = "../lib/mux_32to1.v:8" *)
wire int14;
(* src = "../lib/mux_32to1.v:8" *)
wire int15;
(* src = "../lib/mux_32to1.v:10" *)
wire s0_bar;
(* src = "../lib/mux_32to1.v:11" *)
wire s1_bar;
(* src = "../lib/mux_32to1.v:12" *)
wire s2_bar;
(* src = "../lib/mux_32to1.v:13" *)
wire s3_bar;
(* src = "../lib/mux_32to1.v:14" *)
wire s4_bar;
(* src = "../lib/mux_32to1.v:17" *)
wire _000_;
(* src = "../lib/mux_32to1.v:17" *)
wire _001_;
(* src = "../lib/mux_32to1.v:17" *)
wire _002_;
(* src = "../lib/mux_32to1.v:17" *)
wire _003_;
(* src = "../lib/mux_32to1.v:18" *)
wire _004_;
(* src = "../lib/mux_32to1.v:18" *)
wire _005_;
(* src = "../lib/mux_32to1.v:18" *)
wire _006_;
(* src = "../lib/mux_32to1.v:18" *)
wire _007_;
(* src = "../lib/mux_32to1.v:19" *)
wire _008_;
(* src = "../lib/mux_32to1.v:19" *)
wire _009_;
(* src = "../lib/mux_32to1.v:19" *)
wire _010_;
(* src = "../lib/mux_32to1.v:19" *)
wire _011_;
(* src = "../lib/mux_32to1.v:20" *)
wire _012_;
(* src = "../lib/mux_32to1.v:20" *)
wire _013_;
(* src = "../lib/mux_32to1.v:20" *)
wire _014_;
(* src = "../lib/mux_32to1.v:20" *)
wire _015_;
(* src = "../lib/mux_32to1.v:21" *)
wire _016_;
(* src = "../lib/mux_32to1.v:21" *)
wire _017_;
(* src = "../lib/mux_32to1.v:21" *)
wire _018_;
(* src = "../lib/mux_32to1.v:21" *)
wire _019_;
(* src = "../lib/mux_32to1.v:22" *)
wire _020_;
(* src = "../lib/mux_32to1.v:22" *)
wire _021_;
(* src = "../lib/mux_32to1.v:22" *)
wire _022_;
(* src = "../lib/mux_32to1.v:22" *)
wire _023_;
(* src = "../lib/mux_32to1.v:23" *)
wire _024_;
(* src = "../lib/mux_32to1.v:23" *)
wire _025_;
(* src = "../lib/mux_32to1.v:23" *)
wire _026_;
(* src = "../lib/mux_32to1.v:23" *)
wire _027_;
(* src = "../lib/mux_32to1.v:24" *)
wire _028_;
(* src = "../lib/mux_32to1.v:24" *)
wire _029_;
(* src = "../lib/mux_32to1.v:24" *)
wire _030_;
(* src = "../lib/mux_32to1.v:24" *)
wire _031_;
(* src = "../lib/mux_32to1.v:25" *)
wire _032_;
(* src = "../lib/mux_32to1.v:25" *)
wire _033_;
(* src = "../lib/mux_32to1.v:25" *)
wire _034_;
(* src = "../lib/mux_32to1.v:25" *)
wire _035_;
(* src = "../lib/mux_32to1.v:26" *)
wire _036_;
(* src = "../lib/mux_32to1.v:26" *)
wire _037_;
(* src = "../lib/mux_32to1.v:26" *)
wire _038_;
(* src = "../lib/mux_32to1.v:26" *)
wire _039_;
(* src = "../lib/mux_32to1.v:27" *)
wire _040_;
(* src = "../lib/mux_32to1.v:27" *)
wire _041_;
(* src = "../lib/mux_32to1.v:27" *)
wire _042_;
(* src = "../lib/mux_32to1.v:27" *)
wire _043_;
(* src = "../lib/mux_32to1.v:28" *)
wire _044_;
(* src = "../lib/mux_32to1.v:28" *)
wire _045_;
(* src = "../lib/mux_32to1.v:28" *)
wire _046_;
(* src = "../lib/mux_32to1.v:28" *)
wire _047_;
(* src = "../lib/mux_32to1.v:29" *)
wire _048_;
(* src = "../lib/mux_32to1.v:29" *)
wire _049_;
(* src = "../lib/mux_32to1.v:29" *)
wire _050_;
(* src = "../lib/mux_32to1.v:29" *)
wire _051_;
(* src = "../lib/mux_32to1.v:30" *)
wire _052_;
(* src = "../lib/mux_32to1.v:30" *)
wire _053_;
(* src = "../lib/mux_32to1.v:30" *)
wire _054_;
(* src = "../lib/mux_32to1.v:30" *)
wire _055_;
(* src = "../lib/mux_32to1.v:31" *)
wire _056_;
(* src = "../lib/mux_32to1.v:31" *)
wire _057_;
(* src = "../lib/mux_32to1.v:31" *)
wire _058_;
(* src = "../lib/mux_32to1.v:31" *)
wire _059_;
(* src = "../lib/mux_32to1.v:32" *)
wire _060_;
(* src = "../lib/mux_32to1.v:32" *)
wire _061_;
(* src = "../lib/mux_32to1.v:32" *)
wire _062_;
(* src = "../lib/mux_32to1.v:32" *)
wire _063_;
(* src = "../lib/mux_32to1.v:33" *)
wire _064_;
(* src = "../lib/mux_32to1.v:33" *)
wire _065_;
(* src = "../lib/mux_32to1.v:33" *)
wire _066_;
(* src = "../lib/mux_32to1.v:33" *)
wire _067_;
(* src = "../lib/mux_32to1.v:33" *)
wire int16;
(* src = "../lib/mux_32to1.v:34" *)
wire _068_;
(* src = "../lib/mux_32to1.v:34" *)
wire _069_;
(* src = "../lib/mux_32to1.v:34" *)
wire _070_;
(* src = "../lib/mux_32to1.v:34" *)
wire _071_;
(* src = "../lib/mux_32to1.v:34" *)
wire int17;
(* src = "../lib/mux_32to1.v:35" *)
wire _072_;
(* src = "../lib/mux_32to1.v:35" *)
wire _073_;
(* src = "../lib/mux_32to1.v:35" *)
wire _074_;
(* src = "../lib/mux_32to1.v:35" *)
wire _075_;
(* src = "../lib/mux_32to1.v:35" *)
wire int18;
(* src = "../lib/mux_32to1.v:36" *)
wire _076_;
(* src = "../lib/mux_32to1.v:36" *)
wire _077_;
(* src = "../lib/mux_32to1.v:36" *)
wire _078_;
(* src = "../lib/mux_32to1.v:36" *)
wire _079_;
(* src = "../lib/mux_32to1.v:36" *)
wire int19;
(* src = "../lib/mux_32to1.v:37" *)
wire _080_;
(* src = "../lib/mux_32to1.v:37" *)
wire _081_;
(* src = "../lib/mux_32to1.v:37" *)
wire _082_;
(* src = "../lib/mux_32to1.v:37" *)
wire _083_;
(* src = "../lib/mux_32to1.v:37" *)
wire int20;
(* src = "../lib/mux_32to1.v:38" *)
wire _084_;
(* src = "../lib/mux_32to1.v:38" *)
wire _085_;
(* src = "../lib/mux_32to1.v:38" *)
wire _086_;
(* src = "../lib/mux_32to1.v:38" *)
wire _087_;
(* src = "../lib/mux_32to1.v:38" *)
wire int21;
(* src = "../lib/mux_32to1.v:39" *)
wire _088_;
(* src = "../lib/mux_32to1.v:39" *)
wire _089_;
(* src = "../lib/mux_32to1.v:39" *)
wire _090_;
(* src = "../lib/mux_32to1.v:39" *)
wire _091_;
(* src = "../lib/mux_32to1.v:39" *)
wire int22;
(* src = "../lib/mux_32to1.v:40" *)
wire _092_;
(* src = "../lib/mux_32to1.v:40" *)
wire _093_;
(* src = "../lib/mux_32to1.v:40" *)
wire _094_;
(* src = "../lib/mux_32to1.v:40" *)
wire _095_;
(* src = "../lib/mux_32to1.v:40" *)
wire int23;
(* src = "../lib/mux_32to1.v:41" *)
wire _096_;
(* src = "../lib/mux_32to1.v:41" *)
wire _097_;
(* src = "../lib/mux_32to1.v:41" *)
wire _098_;
(* src = "../lib/mux_32to1.v:41" *)
wire _099_;
(* src = "../lib/mux_32to1.v:41" *)
wire int24;
(* src = "../lib/mux_32to1.v:42" *)
wire _100_;
(* src = "../lib/mux_32to1.v:42" *)
wire _101_;
(* src = "../lib/mux_32to1.v:42" *)
wire _102_;
(* src = "../lib/mux_32to1.v:42" *)
wire _103_;
(* src = "../lib/mux_32to1.v:42" *)
wire int25;
(* src = "../lib/mux_32to1.v:43" *)
wire _104_;
(* src = "../lib/mux_32to1.v:43" *)
wire _105_;
(* src = "../lib/mux_32to1.v:43" *)
wire _106_;
(* src = "../lib/mux_32to1.v:43" *)
wire _107_;
(* src = "../lib/mux_32to1.v:43" *)
wire int26;
(* src = "../lib/mux_32to1.v:44" *)
wire _108_;
(* src = "../lib/mux_32to1.v:44" *)
wire _109_;
(* src = "../lib/mux_32to1.v:44" *)
wire _110_;
(* src = "../lib/mux_32to1.v:44" *)
wire _111_;
(* src = "../lib/mux_32to1.v:44" *)
wire int27;
(* src = "../lib/mux_32to1.v:45" *)
wire _112_;
(* src = "../lib/mux_32to1.v:45" *)
wire _113_;
(* src = "../lib/mux_32to1.v:45" *)
wire _114_;
(* src = "../lib/mux_32to1.v:45" *)
wire _115_;
(* src = "../lib/mux_32to1.v:45" *)
wire int28;
(* src = "../lib/mux_32to1.v:46" *)
wire _116_;
(* src = "../lib/mux_32to1.v:46" *)
wire _117_;
(* src = "../lib/mux_32to1.v:46" *)
wire _118_;
(* src = "../lib/mux_32to1.v:46" *)
wire _119_;
(* src = "../lib/mux_32to1.v:46" *)
wire int29;
(* src = "../lib/mux_32to1.v:47" *)
wire _120_;
(* src = "../lib/mux_32to1.v:47" *)
wire _121_;
(* src = "../lib/mux_32to1.v:47" *)
wire _122_;
(* src = "../lib/mux_32to1.v:47" *)
wire _123_;
(* src = "../lib/mux_32to1.v:47" *)
wire int30;
(* src = "../lib/mux_32to1.v:48" *)
wire _124_;
(* src = "../lib/mux_32to1.v:48" *)
wire _125_;
(* src = "../lib/mux_32to1.v:48" *)
wire _126_;
(* src = "../lib/mux_32to1.v:48" *)
wire _127_;
(* src = "../lib/mux_32to1.v:48" *)
wire int31;
(* src = "../lib/mux_32to1.v:51" *)
wire _128_;
(* src = "../lib/mux_32to1.v:51" *)
wire _129_;
(* src = "../lib/mux_32to1.v:51" *)
wire _130_;
(* src = "../lib/mux_32to1.v:51" *)
wire _131_;
(* src = "../lib/mux_32to1.v:51" *)
wire _132_;
(* src = "../lib/mux_32to1.v:51" *)
wire _133_;
(* src = "../lib/mux_32to1.v:51" *)
wire _134_;
(* src = "../lib/mux_32to1.v:51" *)
wire _135_;
(* src = "../lib/mux_32to1.v:51" *)
wire _136_;
(* src = "../lib/mux_32to1.v:51" *)
wire _137_;
(* src = "../lib/mux_32to1.v:51" *)
wire _138_;
(* src = "../lib/mux_32to1.v:51" *)
wire _139_;
(* src = "../lib/mux_32to1.v:51" *)
wire _140_;
(* src = "../lib/mux_32to1.v:51" *)
wire _141_;
(* src = "../lib/mux_32to1.v:51" *)
wire _142_;
(* src = "../lib/mux_32to1.v:51" *)
wire _143_;
(* src = "../lib/mux_32to1.v:51" *)
wire _144_;
(* src = "../lib/mux_32to1.v:51" *)
wire _145_;
(* src = "../lib/mux_32to1.v:51" *)
wire _146_;
(* src = "../lib/mux_32to1.v:51" *)
wire _147_;
(* src = "../lib/mux_32to1.v:51" *)
wire _148_;
(* src = "../lib/mux_32to1.v:51" *)
wire _149_;
(* src = "../lib/mux_32to1.v:51" *)
wire _150_;
(* src = "../lib/mux_32to1.v:51" *)
wire _151_;
(* src = "../lib/mux_32to1.v:51" *)
wire _152_;
(* src = "../lib/mux_32to1.v:51" *)
wire _153_;
(* src = "../lib/mux_32to1.v:51" *)
wire _154_;
(* src = "../lib/mux_32to1.v:51" *)
wire _155_;
(* src = "../lib/mux_32to1.v:51" *)
wire _156_;
(* src = "../lib/mux_32to1.v:51" *)
wire _157_;
assign z = _157_ | int15;
assign _157_ = _156_ | int14;
assign _156_ = _155_ | int13;
assign _155_ = _154_ | int12;
assign _154_ = _153_ | int11;
assign _153_ = _152_ | int10;
assign _152_ = _151_ | int9;
assign _151_ = _150_ | int8;
assign _150_ = _149_ | int7;
assign _149_ = _148_ | int6;
assign _148_ = _147_ | int5;
assign _147_ = _146_ | int4;
assign _146_ = _145_ | int3;
assign _145_ = _144_ | int2;
assign _144_ = _143_ | int1;
assign _143_ = _142_ | int0;
assign _142_ = _141_ | int16;
assign _141_ = _140_ | int17;
assign _140_ = _139_ | int18;
assign _139_ = _138_ | int19;
assign _138_ = _137_ | int20;
assign _137_ = _136_ | int21;
assign _136_ = _135_ | int22;
assign _135_ = _134_ | int23;
assign _134_ = _133_ | int24;
assign _133_ = _132_ | int25;
assign _132_ = _131_ | int26;
assign _131_ = _130_ | int27;
assign _130_ = _129_ | int28;
assign _129_ = _128_ | int29;
assign _128_ = int31 | int30;
assign int31 = _127_ & s[0];
assign _127_ = _126_ & s[1];
assign _126_ = _125_ & s[2];
assign _125_ = _124_ & s[3];
assign _124_ = i31 & s[4];
assign int30 = _123_ & s0_bar;
assign _123_ = _122_ & s[1];
assign _122_ = _121_ & s[2];
assign _121_ = _120_ & s[3];
assign _120_ = i30 & s[4];
assign int29 = _119_ & s[0];
assign _119_ = _118_ & s1_bar;
assign _118_ = _117_ & s[2];
assign _117_ = _116_ & s[3];
assign _116_ = i29 & s[4];
assign int28 = _115_ & s0_bar;
assign _115_ = _114_ & s1_bar;
assign _114_ = _113_ & s[2];
assign _113_ = _112_ & s[3];
assign _112_ = i28 & s[4];
assign int27 = _111_ & s[0];
assign _111_ = _110_ & s[1];
assign _110_ = _109_ & s2_bar;
assign _109_ = _108_ & s[3];
assign _108_ = i27 & s[4];
assign int26 = _107_ & s0_bar;
assign _107_ = _106_ & s[1];
assign _106_ = _105_ & s2_bar;
assign _105_ = _104_ & s[3];
assign _104_ = i26 & s[4];
assign int25 = _103_ & s[0];
assign _103_ = _102_ & s1_bar;
assign _102_ = _101_ & s2_bar;
assign _101_ = _100_ & s[3];
assign _100_ = i25 & s[4];
assign int24 = _099_ & s0_bar;
assign _099_ = _098_ & s1_bar;
assign _098_ = _097_ & s2_bar;
assign _097_ = _096_ & s[3];
assign _096_ = i24 & s[4];
assign int23 = _095_ & s[0];
assign _095_ = _094_ & s[1];
assign _094_ = _093_ & s[2];
assign _093_ = _092_ & s3_bar;
assign _092_ = i23 & s[4];
assign int22 = _091_ & s0_bar;
assign _091_ = _090_ & s[1];
assign _090_ = _089_ & s[2];
assign _089_ = _088_ & s3_bar;
assign _088_ = i22 & s[4];
assign int21 = _087_ & s[0];
assign _087_ = _086_ & s1_bar;
assign _085_ = _084_ & s3_bar;
assign _084_ = i21 & s[4];
assign int20 = _083_ & s0_bar;
assign _083_ = _082_ & s1_bar;
assign _082_ = _081_ & s[2];
assign _081_ = _080_ & s3_bar;
assign _080_ = i20 & s[4];
assign int19 = _079_ & s[0];
assign _079_ = _078_ & s[1];
assign _078_ = _077_ & s2_bar;
assign _077_ = _076_ & s3_bar;
assign _076_ = i19 & s[4];
assign int18 = _075_ & s0_bar;
assign _075_ = _074_ & s[1];
assign _074_ = _073_ & s2_bar;
assign _073_ = _072_ & s3_bar;
assign _072_ = i18 & s[4];
assign int17 = _071_ & s[0];
assign _071_ = _070_ & s1_bar;
assign _070_ = _069_ & s2_bar;
assign _069_ = _068_ & s3_bar;
assign _068_ = i17 & s[4];
assign int16 = _067_ & s0_bar;
assign _067_ = _066_ & s1_bar;
assign _066_ = _065_ & s2_bar;
assign _065_ = _064_ & s3_bar;
assign _064_ = i16 & s[4];
assign int15 = _063_ & s[0];
assign _063_ = _062_ & s[1];
assign _062_ = _061_ & s[2];
assign _061_ = _060_ & s[3];
assign _060_ = i15 & s4_bar;
assign int14 = _059_ & s0_bar;
assign _059_ = _058_ & s[1];
assign _058_ = _057_ & s[2];
assign _057_ = _056_ & s[3];
assign _056_ = i14 & s4_bar;
assign int13 = _055_ & s[0];
assign _055_ = _054_ & s1_bar;
assign _054_ = _053_ & s[2];
assign _053_ = _052_ & s[3];
assign _052_ = i13 & s4_bar;
assign int12 = _051_ & s0_bar;
assign _051_ = _050_ & s1_bar;
assign _050_ = _049_ & s[2];
assign _086_ = _085_ & s[2];
assign _049_ = _048_ & s[3];
assign _048_ = i12 & s4_bar;
assign int11 = _047_ & s[0];
assign _047_ = _046_ & s[1];
assign _046_ = _045_ & s2_bar;
assign _044_ = i11 & s4_bar;
assign _045_ = _044_ & s[3];
assign int10 = _043_ & s0_bar;
assign _043_ = _042_ & s[1];
assign _042_ = _041_ & s2_bar;
assign _041_ = _040_ & s[3];
assign _040_ = i10 & s4_bar;
assign int9 = _039_ & s[0];
assign _039_ = _038_ & s1_bar;
assign _038_ = _037_ & s2_bar;
assign _037_ = _036_ & s[3];
assign _036_ = i9 & s4_bar;
assign int8 = _035_ & s0_bar;
assign _035_ = _034_ & s1_bar;
assign _034_ = _033_ & s2_bar;
assign _033_ = _032_ & s[3];
assign _032_ = i8 & s4_bar;
assign int7 = _031_ & s[0];
assign _031_ = _030_ & s[1];
assign _030_ = _029_ & s[2];
assign _029_ = _028_ & s3_bar;
assign _028_ = i7 & s4_bar;
assign int6 = _027_ & s0_bar;
assign _027_ = _026_ & s[1];
assign _026_ = _025_ & s[2];
assign _025_ = _024_ & s3_bar;
assign _024_ = i6 & s4_bar;
assign int5 = _023_ & s[0];
assign _023_ = _022_ & s1_bar;
assign _022_ = _021_ & s[2];
assign _021_ = _020_ & s3_bar;
assign _020_ = i5 & s4_bar;
assign int4 = _019_ & s0_bar;
assign _019_ = _018_ & s1_bar;
assign _018_ = _017_ & s[2];
assign _017_ = _016_ & s3_bar;
assign _016_ = i4 & s4_bar;
assign int3 = _015_ & s[0];
assign _015_ = _014_ & s[1];
assign _014_ = _013_ & s2_bar;
assign _013_ = _012_ & s3_bar;
assign _012_ = i3 & s4_bar;
assign int2 = _011_ & s0_bar;
assign _011_ = _010_ & s[1];
assign _010_ = _009_ & s2_bar;
assign _009_ = _008_ & s3_bar;
assign _008_ = i2 & s4_bar;
assign int1 = _007_ & s[0];
assign _007_ = _006_ & s1_bar;
assign _006_ = _005_ & s2_bar;
assign _005_ = _004_ & s3_bar;
assign _004_ = i1 & s4_bar;
assign int0 = _003_ & s0_bar;
assign _003_ = _002_ & s1_bar;
assign _002_ = _001_ & s2_bar;
assign _001_ = _000_ & s3_bar;
assign _000_ = i0 & s4_bar;
assign s4_bar = ~s[4];
assign s3_bar = ~s[3];
assign s2_bar = ~s[2];
assign s1_bar = ~s[1];
assign s0_bar = ~s[0];
endmodule
(* src = "../lib/mux32bits_32to1.v:3" *)
module mux32bits_32to1(s, i31, i30, i29, i28, i27, i26, i25, i24, i23, i22, i21, i20, i19, i18, i17, i16, i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0, z);
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i1;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i0;
(* src = "../lib/mux32bits_32to1.v:4" *)
input [4:0] s;
(* src = "../lib/mux32bits_32to1.v:7" *)
output [31:0] z;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i31;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i30;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i29;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i28;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i27;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i26;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i25;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i24;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i23;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i22;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i21;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i20;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i19;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i18;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i17;
(* src = "../lib/mux32bits_32to1.v:5" *)
input [31:0] i16;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i15;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i14;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i13;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i12;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i11;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i10;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i9;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i8;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i7;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i6;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i5;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i4;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i3;
(* src = "../lib/mux32bits_32to1.v:6" *)
input [31:0] i2;
(* src = "../lib/mux32bits_32to1.v:9" *)
mux_32to1 mux0 (
.i1(i1[0]),
.i0(i0[0]),
.s(s),
.z(z[0]),
.i31(i31[0]),
.i30(i30[0]),
.i29(i29[0]),
.i28(i28[0]),
.i27(i27[0]),
.i26(i26[0]),
.i25(i25[0]),
.i24(i24[0]),
.i23(i23[0]),
.i22(i22[0]),
.i21(i21[0]),
.i20(i20[0]),
.i19(i19[0]),
.i18(i18[0]),
.i17(i17[0]),
.i16(i16[0]),
.i15(i15[0]),
.i14(i14[0]),
.i13(i13[0]),
.i12(i12[0]),
.i11(i11[0]),
.i10(i10[0]),
.i9(i9[0]),
.i8(i8[0]),
.i7(i7[0]),
.i6(i6[0]),
.i5(i5[0]),
.i4(i4[0]),
.i3(i3[0]),
.i2(i2[0])
);
(* src = "../lib/mux32bits_32to1.v:11" *)
mux_32to1 mux1 (
.i1(i1[1]),
.i0(i0[1]),
.s(s),
.z(z[1]),
.i31(i31[1]),
.i30(i30[1]),
.i29(i29[1]),
.i28(i28[1]),
.i27(i27[1]),
.i26(i26[1]),
.i25(i25[1]),
.i24(i24[1]),
.i23(i23[1]),
.i22(i22[1]),
.i21(i21[1]),
.i20(i20[1]),
.i19(i19[1]),
.i18(i18[1]),
.i17(i17[1]),
.i16(i16[1]),
.i15(i15[1]),
.i14(i14[1]),
.i13(i13[1]),
.i12(i12[1]),
.i11(i11[1]),
.i10(i10[1]),
.i9(i9[1]),
.i8(i8[1]),
.i7(i7[1]),
.i6(i6[1]),
.i5(i5[1]),
.i4(i4[1]),
.i3(i3[1]),
.i2(i2[1])
);
(* src = "../lib/mux32bits_32to1.v:13" *)
mux_32to1 mux2 (
.i1(i1[2]),
.i0(i0[2]),
.s(s),
.z(z[2]),
.i31(i31[2]),
.i30(i30[2]),
.i29(i29[2]),
.i28(i28[2]),
.i27(i27[2]),
.i26(i26[2]),
.i25(i25[2]),
.i24(i24[2]),
.i23(i23[2]),
.i22(i22[2]),
.i21(i21[2]),
.i20(i20[2]),
.i19(i19[2]),
.i18(i18[2]),
.i17(i17[2]),
.i16(i16[2]),
.i15(i15[2]),
.i14(i14[2]),
.i13(i13[2]),
.i12(i12[2]),
.i11(i11[2]),
.i10(i10[2]),
.i9(i9[2]),
.i8(i8[2]),
.i7(i7[2]),
.i6(i6[2]),
.i5(i5[2]),
.i4(i4[2]),
.i3(i3[2]),
.i2(i2[2])
);
(* src = "../lib/mux32bits_32to1.v:15" *)
mux_32to1 mux3 (
.i1(i1[3]),
.i0(i0[3]),
.s(s),
.z(z[3]),
.i31(i31[3]),
.i30(i30[3]),
.i29(i29[3]),
.i28(i28[3]),
.i27(i27[3]),
.i26(i26[3]),
.i25(i25[3]),
.i24(i24[3]),
.i23(i23[3]),
.i22(i22[3]),
.i21(i21[3]),
.i20(i20[3]),
.i19(i19[3]),
.i18(i18[3]),
.i17(i17[3]),
.i16(i16[3]),
.i15(i15[3]),
.i14(i14[3]),
.i13(i13[3]),
.i12(i12[3]),
.i11(i11[3]),
.i10(i10[3]),
.i9(i9[3]),
.i8(i8[3]),
.i7(i7[3]),
.i6(i6[3]),
.i5(i5[3]),
.i4(i4[3]),
.i3(i3[3]),
.i2(i2[3])
);
(* src = "../lib/mux32bits_32to1.v:17" *)
mux_32to1 mux4 (
.i1(i1[4]),
.i0(i0[4]),
.s(s),
.z(z[4]),
.i31(i31[4]),
.i30(i30[4]),
.i29(i29[4]),
.i28(i28[4]),
.i27(i27[4]),
.i26(i26[4]),
.i25(i25[4]),
.i24(i24[4]),
.i23(i23[4]),
.i22(i22[4]),
.i21(i21[4]),
.i20(i20[4]),
.i19(i19[4]),
.i18(i18[4]),
.i17(i17[4]),
.i16(i16[4]),
.i15(i15[4]),
.i14(i14[4]),
.i13(i13[4]),
.i12(i12[4]),
.i11(i11[4]),
.i10(i10[4]),
.i9(i9[4]),
.i8(i8[4]),
.i7(i7[4]),
.i6(i6[4]),
.i5(i5[4]),
.i4(i4[4]),
.i3(i3[4]),
.i2(i2[4])
);
(* src = "../lib/mux32bits_32to1.v:19" *)
mux_32to1 mux5 (
.i1(i1[5]),
.i0(i0[5]),
.s(s),
.z(z[5]),
.i31(i31[5]),
.i30(i30[5]),
.i29(i29[5]),
.i28(i28[5]),
.i27(i27[5]),
.i26(i26[5]),
.i25(i25[5]),
.i24(i24[5]),
.i23(i23[5]),
.i22(i22[5]),
.i21(i21[5]),
.i20(i20[5]),
.i19(i19[5]),
.i18(i18[5]),
.i17(i17[5]),
.i16(i16[5]),
.i15(i15[5]),
.i14(i14[5]),
.i13(i13[5]),
.i12(i12[5]),
.i11(i11[5]),
.i10(i10[5]),
.i9(i9[5]),
.i8(i8[5]),
.i7(i7[5]),
.i6(i6[5]),
.i5(i5[5]),
.i4(i4[5]),
.i3(i3[5]),
.i2(i2[5])
);
(* src = "../lib/mux32bits_32to1.v:21" *)
mux_32to1 mux6 (
.i1(i1[6]),
.i0(i0[6]),
.s(s),
.z(z[6]),
.i31(i31[6]),
.i30(i30[6]),
.i29(i29[6]),
.i28(i28[6]),
.i27(i27[6]),
.i26(i26[6]),
.i25(i25[6]),
.i24(i24[6]),
.i23(i23[6]),
.i22(i22[6]),
.i21(i21[6]),
.i20(i20[6]),
.i19(i19[6]),
.i18(i18[6]),
.i17(i17[6]),
.i16(i16[6]),
.i15(i15[6]),
.i14(i14[6]),
.i13(i13[6]),
.i12(i12[6]),
.i11(i11[6]),
.i10(i10[6]),
.i9(i9[6]),
.i8(i8[6]),
.i7(i7[6]),
.i6(i6[6]),
.i5(i5[6]),
.i4(i4[6]),
.i3(i3[6]),
.i2(i2[6])
);
(* src = "../lib/mux32bits_32to1.v:23" *)
mux_32to1 mux7 (
.i1(i1[7]),
.i0(i0[7]),
.s(s),
.z(z[7]),
.i31(i31[7]),
.i30(i30[7]),
.i29(i29[7]),
.i28(i28[7]),
.i27(i27[7]),
.i26(i26[7]),
.i25(i25[7]),
.i24(i24[7]),
.i23(i23[7]),
.i22(i22[7]),
.i21(i21[7]),
.i20(i20[7]),
.i19(i19[7]),
.i18(i18[7]),
.i17(i17[7]),
.i16(i16[7]),
.i15(i15[7]),
.i14(i14[7]),
.i13(i13[7]),
.i12(i12[7]),
.i11(i11[7]),
.i10(i10[7]),
.i9(i9[7]),
.i8(i8[7]),
.i7(i7[7]),
.i6(i6[7]),
.i5(i5[7]),
.i4(i4[7]),
.i3(i3[7]),
.i2(i2[7])
);
(* src = "../lib/mux32bits_32to1.v:25" *)
mux_32to1 mux8 (
.i1(i1[8]),
.i0(i0[8]),
.s(s),
.z(z[8]),
.i31(i31[8]),
.i30(i30[8]),
.i29(i29[8]),
.i28(i28[8]),
.i27(i27[8]),
.i26(i26[8]),
.i25(i25[8]),
.i24(i24[8]),
.i23(i23[8]),
.i22(i22[8]),
.i21(i21[8]),
.i20(i20[8]),
.i19(i19[8]),
.i18(i18[8]),
.i17(i17[8]),
.i16(i16[8]),
.i15(i15[8]),
.i14(i14[8]),
.i13(i13[8]),
.i12(i12[8]),
.i11(i11[8]),
.i10(i10[8]),
.i9(i9[8]),
.i8(i8[8]),
.i7(i7[8]),
.i6(i6[8]),
.i5(i5[8]),
.i4(i4[8]),
.i3(i3[8]),
.i2(i2[8])
);
(* src = "../lib/mux32bits_32to1.v:27" *)
mux_32to1 mux9 (
.i1(i1[9]),
.i0(i0[9]),
.s(s),
.z(z[9]),
.i31(i31[9]),
.i30(i30[9]),
.i29(i29[9]),
.i28(i28[9]),
.i27(i27[9]),
.i26(i26[9]),
.i25(i25[9]),
.i24(i24[9]),
.i23(i23[9]),
.i22(i22[9]),
.i21(i21[9]),
.i20(i20[9]),
.i19(i19[9]),
.i18(i18[9]),
.i17(i17[9]),
.i16(i16[9]),
.i15(i15[9]),
.i14(i14[9]),
.i13(i13[9]),
.i12(i12[9]),
.i11(i11[9]),
.i10(i10[9]),
.i9(i9[9]),
.i8(i8[9]),
.i7(i7[9]),
.i6(i6[9]),
.i5(i5[9]),
.i4(i4[9]),
.i3(i3[9]),
.i2(i2[9])
);
(* src = "../lib/mux32bits_32to1.v:29" *)
mux_32to1 mux10 (
.i1(i1[10]),
.i0(i0[10]),
.s(s),
.z(z[10]),
.i31(i31[10]),
.i30(i30[10]),
.i29(i29[10]),
.i28(i28[10]),
.i27(i27[10]),
.i26(i26[10]),
.i25(i25[10]),
.i24(i24[10]),
.i23(i23[10]),
.i22(i22[10]),
.i21(i21[10]),
.i20(i20[10]),
.i19(i19[10]),
.i18(i18[10]),
.i17(i17[10]),
.i16(i16[10]),
.i15(i15[10]),
.i14(i14[10]),
.i13(i13[10]),
.i12(i12[10]),
.i11(i11[10]),
.i10(i10[10]),
.i9(i9[10]),
.i8(i8[10]),
.i7(i7[10]),
.i6(i6[10]),
.i5(i5[10]),
.i4(i4[10]),
.i3(i3[10]),
.i2(i2[10])
);
(* src = "../lib/mux32bits_32to1.v:31" *)
mux_32to1 mux11 (
.i1(i1[11]),
.i0(i0[11]),
.s(s),
.z(z[11]),
.i31(i31[11]),
.i30(i30[11]),
.i29(i29[11]),
.i28(i28[11]),
.i27(i27[11]),
.i26(i26[11]),
.i25(i25[11]),
.i24(i24[11]),
.i23(i23[11]),
.i22(i22[11]),
.i21(i21[11]),
.i20(i20[11]),
.i19(i19[11]),
.i18(i18[11]),
.i17(i17[11]),
.i16(i16[11]),
.i15(i15[11]),
.i14(i14[11]),
.i13(i13[11]),
.i12(i12[11]),
.i11(i11[11]),
.i10(i10[11]),
.i9(i9[11]),
.i8(i8[11]),
.i7(i7[11]),
.i6(i6[11]),
.i5(i5[11]),
.i4(i4[11]),
.i3(i3[11]),
.i2(i2[11])
);
(* src = "../lib/mux32bits_32to1.v:33" *)
mux_32to1 mux12 (
.i1(i1[12]),
.i0(i0[12]),
.s(s),
.z(z[12]),
.i31(i31[12]),
.i30(i30[12]),
.i29(i29[12]),
.i28(i28[12]),
.i27(i27[12]),
.i26(i26[12]),
.i25(i25[12]),
.i24(i24[12]),
.i23(i23[12]),
.i22(i22[12]),
.i21(i21[12]),
.i20(i20[12]),
.i19(i19[12]),
.i18(i18[12]),
.i17(i17[12]),
.i16(i16[12]),
.i15(i15[12]),
.i14(i14[12]),
.i13(i13[12]),
.i12(i12[12]),
.i11(i11[12]),
.i10(i10[12]),
.i9(i9[12]),
.i8(i8[12]),
.i7(i7[12]),
.i6(i6[12]),
.i5(i5[12]),
.i4(i4[12]),
.i3(i3[12]),
.i2(i2[12])
);
(* src = "../lib/mux32bits_32to1.v:35" *)
mux_32to1 mux13 (
.i1(i1[13]),
.i0(i0[13]),
.s(s),
.z(z[13]),
.i31(i31[13]),
.i30(i30[13]),
.i29(i29[13]),
.i28(i28[13]),
.i27(i27[13]),
.i26(i26[13]),
.i25(i25[13]),
.i24(i24[13]),
.i23(i23[13]),
.i22(i22[13]),
.i21(i21[13]),
.i20(i20[13]),
.i19(i19[13]),
.i18(i18[13]),
.i17(i17[13]),
.i16(i16[13]),
.i15(i15[13]),
.i14(i14[13]),
.i13(i13[13]),
.i12(i12[13]),
.i11(i11[13]),
.i10(i10[13]),
.i9(i9[13]),
.i8(i8[13]),
.i7(i7[13]),
.i6(i6[13]),
.i5(i5[13]),
.i4(i4[13]),
.i3(i3[13]),
.i2(i2[13])
);
(* src = "../lib/mux32bits_32to1.v:37" *)
mux_32to1 mux14 (
.i1(i1[14]),
.i0(i0[14]),
.s(s),
.z(z[14]),
.i31(i31[14]),
.i30(i30[14]),
.i29(i29[14]),
.i28(i28[14]),
.i27(i27[14]),
.i26(i26[14]),
.i25(i25[14]),
.i24(i24[14]),
.i23(i23[14]),
.i22(i22[14]),
.i21(i21[14]),
.i20(i20[14]),
.i19(i19[14]),
.i18(i18[14]),
.i17(i17[14]),
.i16(i16[14]),
.i15(i15[14]),
.i14(i14[14]),
.i13(i13[14]),
.i12(i12[14]),
.i11(i11[14]),
.i10(i10[14]),
.i9(i9[14]),
.i8(i8[14]),
.i7(i7[14]),
.i6(i6[14]),
.i5(i5[14]),
.i4(i4[14]),
.i3(i3[14]),
.i2(i2[14])
);
(* src = "../lib/mux32bits_32to1.v:39" *)
mux_32to1 mux15 (
.i1(i1[15]),
.i0(i0[15]),
.s(s),
.z(z[15]),
.i31(i31[15]),
.i30(i30[15]),
.i29(i29[15]),
.i28(i28[15]),
.i27(i27[15]),
.i26(i26[15]),
.i25(i25[15]),
.i24(i24[15]),
.i23(i23[15]),
.i22(i22[15]),
.i21(i21[15]),
.i20(i20[15]),
.i19(i19[15]),
.i18(i18[15]),
.i17(i17[15]),
.i16(i16[15]),
.i15(i15[15]),
.i14(i14[15]),
.i13(i13[15]),
.i12(i12[15]),
.i11(i11[15]),
.i10(i10[15]),
.i9(i9[15]),
.i8(i8[15]),
.i7(i7[15]),
.i6(i6[15]),
.i5(i5[15]),
.i4(i4[15]),
.i3(i3[15]),
.i2(i2[15])
);
(* src = "../lib/mux32bits_32to1.v:41" *)
mux_32to1 mux16 (
.i1(i1[16]),
.i0(i0[16]),
.s(s),
.z(z[16]),
.i31(i31[16]),
.i30(i30[16]),
.i29(i29[16]),
.i28(i28[16]),
.i27(i27[16]),
.i26(i26[16]),
.i25(i25[16]),
.i24(i24[16]),
.i23(i23[16]),
.i22(i22[16]),
.i21(i21[16]),
.i20(i20[16]),
.i19(i19[16]),
.i18(i18[16]),
.i17(i17[16]),
.i16(i16[16]),
.i15(i15[16]),
.i14(i14[16]),
.i13(i13[16]),
.i12(i12[16]),
.i11(i11[16]),
.i10(i10[16]),
.i9(i9[16]),
.i8(i8[16]),
.i7(i7[16]),
.i6(i6[16]),
.i5(i5[16]),
.i4(i4[16]),
.i3(i3[16]),
.i2(i2[16])
);
(* src = "../lib/mux32bits_32to1.v:43" *)
mux_32to1 mux17 (
.i1(i1[17]),
.i0(i0[17]),
.s(s),
.z(z[17]),
.i31(i31[17]),
.i30(i30[17]),
.i29(i29[17]),
.i28(i28[17]),
.i27(i27[17]),
.i26(i26[17]),
.i25(i25[17]),
.i24(i24[17]),
.i23(i23[17]),
.i22(i22[17]),
.i21(i21[17]),
.i20(i20[17]),
.i19(i19[17]),
.i18(i18[17]),
.i17(i17[17]),
.i16(i16[17]),
.i15(i15[17]),
.i14(i14[17]),
.i13(i13[17]),
.i12(i12[17]),
.i11(i11[17]),
.i10(i10[17]),
.i9(i9[17]),
.i8(i8[17]),
.i7(i7[17]),
.i6(i6[17]),
.i5(i5[17]),
.i4(i4[17]),
.i3(i3[17]),
.i2(i2[17])
);
(* src = "../lib/mux32bits_32to1.v:45" *)
mux_32to1 mux18 (
.i1(i1[18]),
.i0(i0[18]),
.s(s),
.z(z[18]),
.i31(i31[18]),
.i30(i30[18]),
.i29(i29[18]),
.i28(i28[18]),
.i27(i27[18]),
.i26(i26[18]),
.i25(i25[18]),
.i24(i24[18]),
.i23(i23[18]),
.i22(i22[18]),
.i21(i21[18]),
.i20(i20[18]),
.i19(i19[18]),
.i18(i18[18]),
.i17(i17[18]),
.i16(i16[18]),
.i15(i15[18]),
.i14(i14[18]),
.i13(i13[18]),
.i12(i12[18]),
.i11(i11[18]),
.i10(i10[18]),
.i9(i9[18]),
.i8(i8[18]),
.i7(i7[18]),
.i6(i6[18]),
.i5(i5[18]),
.i4(i4[18]),
.i3(i3[18]),
.i2(i2[18])
);
(* src = "../lib/mux32bits_32to1.v:47" *)
mux_32to1 mux19 (
.i1(i1[19]),
.i0(i0[19]),
.s(s),
.z(z[19]),
.i31(i31[19]),
.i30(i30[19]),
.i29(i29[19]),
.i28(i28[19]),
.i27(i27[19]),
.i26(i26[19]),
.i25(i25[19]),
.i24(i24[19]),
.i23(i23[19]),
.i22(i22[19]),
.i21(i21[19]),
.i20(i20[19]),
.i19(i19[19]),
.i18(i18[19]),
.i17(i17[19]),
.i16(i16[19]),
.i15(i15[19]),
.i14(i14[19]),
.i13(i13[19]),
.i12(i12[19]),
.i11(i11[19]),
.i10(i10[19]),
.i9(i9[19]),
.i8(i8[19]),
.i7(i7[19]),
.i6(i6[19]),
.i5(i5[19]),
.i4(i4[19]),
.i3(i3[19]),
.i2(i2[19])
);
(* src = "../lib/mux32bits_32to1.v:49" *)
mux_32to1 mux20 (
.i1(i1[20]),
.i0(i0[20]),
.s(s),
.z(z[20]),
.i31(i31[20]),
.i30(i30[20]),
.i29(i29[20]),
.i28(i28[20]),
.i27(i27[20]),
.i26(i26[20]),
.i25(i25[20]),
.i24(i24[20]),
.i23(i23[20]),
.i22(i22[20]),
.i21(i21[20]),
.i20(i20[20]),
.i19(i19[20]),
.i18(i18[20]),
.i17(i17[20]),
.i16(i16[20]),
.i15(i15[20]),
.i14(i14[20]),
.i13(i13[20]),
.i12(i12[20]),
.i11(i11[20]),
.i10(i10[20]),
.i9(i9[20]),
.i8(i8[20]),
.i7(i7[20]),
.i6(i6[20]),
.i5(i5[20]),
.i4(i4[20]),
.i3(i3[20]),
.i2(i2[20])
);
(* src = "../lib/mux32bits_32to1.v:51" *)
mux_32to1 mux21 (
.i1(i1[21]),
.i0(i0[21]),
.s(s),
.z(z[21]),
.i31(i31[21]),
.i30(i30[21]),
.i29(i29[21]),
.i28(i28[21]),
.i27(i27[21]),
.i26(i26[21]),
.i25(i25[21]),
.i24(i24[21]),
.i23(i23[21]),
.i22(i22[21]),
.i21(i21[21]),
.i20(i20[21]),
.i19(i19[21]),
.i18(i18[21]),
.i17(i17[21]),
.i16(i16[21]),
.i15(i15[21]),
.i14(i14[21]),
.i13(i13[21]),
.i12(i12[21]),
.i11(i11[21]),
.i10(i10[21]),
.i9(i9[21]),
.i8(i8[21]),
.i7(i7[21]),
.i6(i6[21]),
.i5(i5[21]),
.i4(i4[21]),
.i3(i3[21]),
.i2(i2[21])
);
(* src = "../lib/mux32bits_32to1.v:53" *)
mux_32to1 mux22 (
.i1(i1[22]),
.i0(i0[22]),
.s(s),
.z(z[22]),
.i31(i31[22]),
.i30(i30[22]),
.i29(i29[22]),
.i28(i28[22]),
.i27(i27[22]),
.i26(i26[22]),
.i25(i25[22]),
.i24(i24[22]),
.i23(i23[22]),
.i22(i22[22]),
.i21(i21[22]),
.i20(i20[22]),
.i19(i19[22]),
.i18(i18[22]),
.i17(i17[22]),
.i16(i16[22]),
.i15(i15[22]),
.i14(i14[22]),
.i13(i13[22]),
.i12(i12[22]),
.i11(i11[22]),
.i10(i10[22]),
.i9(i9[22]),
.i8(i8[22]),
.i7(i7[22]),
.i6(i6[22]),
.i5(i5[22]),
.i4(i4[22]),
.i3(i3[22]),
.i2(i2[22])
);
(* src = "../lib/mux32bits_32to1.v:56" *)
mux_32to1 mux23 (
.i1(i1[23]),
.i0(i0[23]),
.s(s),
.z(z[23]),
.i31(i31[23]),
.i30(i30[23]),
.i29(i29[23]),
.i28(i28[23]),
.i27(i27[23]),
.i26(i26[23]),
.i25(i25[23]),
.i24(i24[23]),
.i23(i23[23]),
.i22(i22[23]),
.i21(i21[23]),
.i20(i20[23]),
.i19(i19[23]),
.i18(i18[23]),
.i17(i17[23]),
.i16(i16[23]),
.i15(i15[23]),
.i14(i14[23]),
.i13(i13[23]),
.i12(i12[23]),
.i11(i11[23]),
.i10(i10[23]),
.i9(i9[23]),
.i8(i8[23]),
.i7(i7[23]),
.i6(i6[23]),
.i5(i5[23]),
.i4(i4[23]),
.i3(i3[23]),
.i2(i2[23])
);
(* src = "../lib/mux32bits_32to1.v:58" *)
mux_32to1 mux24 (
.i1(i1[24]),
.i0(i0[24]),
.s(s),
.z(z[24]),
.i31(i31[24]),
.i30(i30[24]),
.i29(i29[24]),
.i28(i28[24]),
.i27(i27[24]),
.i26(i26[24]),
.i25(i25[24]),
.i24(i24[24]),
.i23(i23[24]),
.i22(i22[24]),
.i21(i21[24]),
.i20(i20[24]),
.i19(i19[24]),
.i18(i18[24]),
.i17(i17[24]),
.i16(i16[24]),
.i15(i15[24]),
.i14(i14[24]),
.i13(i13[24]),
.i12(i12[24]),
.i11(i11[24]),
.i10(i10[24]),
.i9(i9[24]),
.i8(i8[24]),
.i7(i7[24]),
.i6(i6[24]),
.i5(i5[24]),
.i4(i4[24]),
.i3(i3[24]),
.i2(i2[24])
);
(* src = "../lib/mux32bits_32to1.v:60" *)
mux_32to1 mux25 (
.i1(i1[25]),
.i0(i0[25]),
.s(s),
.z(z[25]),
.i31(i31[25]),
.i30(i30[25]),
.i29(i29[25]),
.i28(i28[25]),
.i27(i27[25]),
.i26(i26[25]),
.i25(i25[25]),
.i24(i24[25]),
.i23(i23[25]),
.i22(i22[25]),
.i21(i21[25]),
.i20(i20[25]),
.i19(i19[25]),
.i18(i18[25]),
.i17(i17[25]),
.i16(i16[25]),
.i15(i15[25]),
.i14(i14[25]),
.i13(i13[25]),
.i12(i12[25]),
.i11(i11[25]),
.i10(i10[25]),
.i9(i9[25]),
.i8(i8[25]),
.i7(i7[25]),
.i6(i6[25]),
.i5(i5[25]),
.i4(i4[25]),
.i3(i3[25]),
.i2(i2[25])
);
(* src = "../lib/mux32bits_32to1.v:62" *)
mux_32to1 mux26 (
.i1(i1[26]),
.i0(i0[26]),
.s(s),
.z(z[26]),
.i31(i31[26]),
.i30(i30[26]),
.i29(i29[26]),
.i28(i28[26]),
.i27(i27[26]),
.i26(i26[26]),
.i25(i25[26]),
.i24(i24[26]),
.i23(i23[26]),
.i22(i22[26]),
.i21(i21[26]),
.i20(i20[26]),
.i19(i19[26]),
.i18(i18[26]),
.i17(i17[26]),
.i16(i16[26]),
.i15(i15[26]),
.i14(i14[26]),
.i13(i13[26]),
.i12(i12[26]),
.i11(i11[26]),
.i10(i10[26]),
.i9(i9[26]),
.i8(i8[26]),
.i7(i7[26]),
.i6(i6[26]),
.i5(i5[26]),
.i4(i4[26]),
.i3(i3[26]),
.i2(i2[26])
);
(* src = "../lib/mux32bits_32to1.v:64" *)
mux_32to1 mux27 (
.i1(i1[27]),
.i0(i0[27]),
.s(s),
.z(z[27]),
.i31(i31[27]),
.i30(i30[27]),
.i29(i29[27]),
.i28(i28[27]),
.i27(i27[27]),
.i26(i26[27]),
.i25(i25[27]),
.i24(i24[27]),
.i23(i23[27]),
.i22(i22[27]),
.i21(i21[27]),
.i20(i20[27]),
.i19(i19[27]),
.i18(i18[27]),
.i17(i17[27]),
.i16(i16[27]),
.i15(i15[27]),
.i14(i14[27]),
.i13(i13[27]),
.i12(i12[27]),
.i11(i11[27]),
.i10(i10[27]),
.i9(i9[27]),
.i8(i8[27]),
.i7(i7[27]),
.i6(i6[27]),
.i5(i5[27]),
.i4(i4[27]),
.i3(i3[27]),
.i2(i2[27])
);
(* src = "../lib/mux32bits_32to1.v:66" *)
mux_32to1 mux28 (
.i1(i1[28]),
.i0(i0[28]),
.s(s),
.z(z[28]),
.i31(i31[28]),
.i30(i30[28]),
.i29(i29[28]),
.i28(i28[28]),
.i27(i27[28]),
.i26(i26[28]),
.i25(i25[28]),
.i24(i24[28]),
.i23(i23[28]),
.i22(i22[28]),
.i21(i21[28]),
.i20(i20[28]),
.i19(i19[28]),
.i18(i18[28]),
.i17(i17[28]),
.i16(i16[28]),
.i15(i15[28]),
.i14(i14[28]),
.i13(i13[28]),
.i12(i12[28]),
.i11(i11[28]),
.i10(i10[28]),
.i9(i9[28]),
.i8(i8[28]),
.i7(i7[28]),
.i6(i6[28]),
.i5(i5[28]),
.i4(i4[28]),
.i3(i3[28]),
.i2(i2[28])
);
(* src = "../lib/mux32bits_32to1.v:68" *)
mux_32to1 mux29 (
.i1(i1[29]),
.i0(i0[29]),
.s(s),
.z(z[29]),
.i31(i31[29]),
.i30(i30[29]),
.i29(i29[29]),
.i28(i28[29]),
.i27(i27[29]),
.i26(i26[29]),
.i25(i25[29]),
.i24(i24[29]),
.i23(i23[29]),
.i22(i22[29]),
.i21(i21[29]),
.i20(i20[29]),
.i19(i19[29]),
.i18(i18[29]),
.i17(i17[29]),
.i16(i16[29]),
.i15(i15[29]),
.i14(i14[29]),
.i13(i13[29]),
.i12(i12[29]),
.i11(i11[29]),
.i10(i10[29]),
.i9(i9[29]),
.i8(i8[29]),
.i7(i7[29]),
.i6(i6[29]),
.i5(i5[29]),
.i4(i4[29]),
.i3(i3[29]),
.i2(i2[29])
);
(* src = "../lib/mux32bits_32to1.v:70" *)
mux_32to1 mux30 (
.i1(i1[30]),
.i0(i0[30]),
.s(s),
.z(z[30]),
.i31(i31[30]),
.i30(i30[30]),
.i29(i29[30]),
.i28(i28[30]),
.i27(i27[30]),
.i26(i26[30]),
.i25(i25[30]),
.i24(i24[30]),
.i23(i23[30]),
.i22(i22[30]),
.i21(i21[30]),
.i20(i20[30]),
.i19(i19[30]),
.i18(i18[30]),
.i17(i17[30]),
.i16(i16[30]),
.i15(i15[30]),
.i14(i14[30]),
.i13(i13[30]),
.i12(i12[30]),
.i11(i11[30]),
.i10(i10[30]),
.i9(i9[30]),
.i8(i8[30]),
.i7(i7[30]),
.i6(i6[30]),
.i5(i5[30]),
.i4(i4[30]),
.i3(i3[30]),
.i2(i2[30])
);
(* src = "../lib/mux32bits_32to1.v:72" *)
mux_32to1 mux31 (
.i1(i1[31]),
.i0(i0[31]),
.s(s),
.z(z[31]),
.i31(i31[31]),
.i30(i30[31]),
.i29(i29[31]),
.i28(i28[31]),
.i27(i27[31]),
.i26(i26[31]),
.i25(i25[31]),
.i24(i24[31]),
.i23(i23[31]),
.i22(i22[31]),
.i21(i21[31]),
.i20(i20[31]),
.i19(i19[31]),
.i18(i18[31]),
.i17(i17[31]),
.i16(i16[31]),
.i15(i15[31]),
.i14(i14[31]),
.i13(i13[31]),
.i12(i12[31]),
.i11(i11[31]),
.i10(i10[31]),
.i9(i9[31]),
.i8(i8[31]),
.i7(i7[31]),
.i6(i6[31]),
.i5(i5[31]),
.i4(i4[31]),
.i3(i3[31]),
.i2(i2[31])
);
endmodule
(* src = "../lib/dec_5to32.v:1" *)
module dec_5to32(a, b);
(* src = "../lib/dec_5to32.v:2" *)
input [4:0] a;
(* src = "../lib/dec_5to32.v:3" *)
output [31:0] b;
(* src = "../lib/dec_5to32.v:5" *)
wire _00_;
(* src = "../lib/dec_5to32.v:5" *)
wire _01_;
(* src = "../lib/dec_5to32.v:5" *)
wire _02_;
(* src = "../lib/dec_5to32.v:5" *)
wire _03_;
(* src = "../lib/dec_5to32.v:5" *)
wire _04_;
(* src = "../lib/dec_5to32.v:5" *)
wire _05_;
(* src = "../lib/dec_5to32.v:5" *)
wire _06_;
(* src = "../lib/dec_5to32.v:5" *)
wire _07_;
(* src = "../lib/dec_5to32.v:7" *)
wire _08_;
(* src = "../lib/dec_5to32.v:9" *)
wire _09_;
(* src = "../lib/dec_5to32.v:9" *)
wire _10_;
(* src = "../lib/dec_5to32.v:11" *)
wire _11_;
(* src = "../lib/dec_5to32.v:13" *)
wire _12_;
(* src = "../lib/dec_5to32.v:13" *)
wire _13_;
(* src = "../lib/dec_5to32.v:13" *)
wire _14_;
(* src = "../lib/dec_5to32.v:15" *)
wire _15_;
(* src = "../lib/dec_5to32.v:17" *)
wire _16_;
(* src = "../lib/dec_5to32.v:17" *)
wire _17_;
(* src = "../lib/dec_5to32.v:19" *)
wire _18_;
(* src = "../lib/dec_5to32.v:21" *)
wire _19_;
(* src = "../lib/dec_5to32.v:21" *)
wire _20_;
(* src = "../lib/dec_5to32.v:21" *)
wire _21_;
(* src = "../lib/dec_5to32.v:23" *)
wire _22_;
(* src = "../lib/dec_5to32.v:25" *)
wire _23_;
(* src = "../lib/dec_5to32.v:25" *)
wire _24_;
(* src = "../lib/dec_5to32.v:27" *)
wire _25_;
(* src = "../lib/dec_5to32.v:29" *)
wire _26_;
(* src = "../lib/dec_5to32.v:29" *)
wire _27_;
(* src = "../lib/dec_5to32.v:29" *)
wire _28_;
(* src = "../lib/dec_5to32.v:31" *)
wire _29_;
(* src = "../lib/dec_5to32.v:33" *)
wire _30_;
(* src = "../lib/dec_5to32.v:33" *)
wire _31_;
(* src = "../lib/dec_5to32.v:35" *)
wire _32_;
assign b[5] = _10_ & a[0];
assign b[4] = _10_ & _07_;
assign _10_ = _09_ & _05_;
assign _09_ = _02_ & a[2];
assign b[3] = _08_ & a[0];
assign b[2] = _08_ & _07_;
assign _08_ = _04_ & a[1];
assign b[1] = _06_ & a[0];
assign b[0] = _06_ & _07_;
assign _07_ = ~a[0];
assign _06_ = _04_ & _05_;
assign _05_ = ~a[1];
assign _04_ = _02_ & _03_;
assign _03_ = ~a[2];
assign _02_ = _00_ & _01_;
assign _01_ = ~a[3];
assign _00_ = ~a[4];
assign b[31] = _32_ & a[0];
assign b[30] = _32_ & _07_;
assign _32_ = _30_ & a[1];
assign b[29] = _31_ & a[0];
assign b[28] = _31_ & _07_;
assign _31_ = _30_ & _05_;
assign _30_ = _26_ & a[2];
assign b[27] = _29_ & a[0];
assign b[26] = _29_ & _07_;
assign _29_ = _27_ & a[1];
assign b[25] = _28_ & a[0];
assign b[24] = _28_ & _07_;
assign _28_ = _27_ & _05_;
assign _27_ = _26_ & _03_;
assign _26_ = a[4] & a[3];
assign b[23] = _25_ & a[0];
assign b[22] = _25_ & _07_;
assign _25_ = _23_ & a[1];
assign b[21] = _24_ & a[0];
assign b[20] = _24_ & _07_;
assign _24_ = _23_ & _05_;
assign _23_ = _19_ & a[2];
assign b[19] = _22_ & a[0];
assign b[18] = _22_ & _07_;
assign _22_ = _20_ & a[1];
assign b[17] = _21_ & a[0];
assign b[16] = _21_ & _07_;
assign _21_ = _20_ & _05_;
assign _20_ = _19_ & _03_;
assign _19_ = a[4] & _01_;
assign b[15] = _18_ & a[0];
assign b[14] = _18_ & _07_;
assign _18_ = _16_ & a[1];
assign b[13] = _17_ & a[0];
assign b[12] = _17_ & _07_;
assign _17_ = _16_ & _05_;
assign _16_ = _12_ & a[2];
assign b[11] = _15_ & a[0];
assign b[10] = _15_ & _07_;
assign _15_ = _13_ & a[1];
assign b[9] = _14_ & a[0];
assign b[8] = _14_ & _07_;
assign _14_ = _13_ & _05_;
assign _13_ = _12_ & _03_;
assign _12_ = _00_ & a[3];
assign b[7] = _11_ & a[0];
assign b[6] = _11_ & _07_;
assign _11_ = _09_ & a[1];
endmodule
(* src = "../RF/reg_file.v:5" *)
module reg_file(readReg1, readReg2, writeReg, writeData, regWrite, clk, readData1, readData2);
(* src = "../RF/reg_file.v:8" *)
input clk;
(* src = "../RF/reg_file.v:15" *)
wire [31:0] we;
(* src = "../RF/reg_file.v:6" *)
input [4:0] readReg1;
(* src = "../RF/reg_file.v:6" *)
input [4:0] readReg2;
(* src = "../RF/reg_file.v:6" *)
input [4:0] writeReg;
(* src = "../RF/reg_file.v:7" *)
input [31:0] writeData;
(* src = "../RF/reg_file.v:8" *)
input regWrite;
(* src = "../RF/reg_file.v:9" *)
output [31:0] readData1;
(* src = "../RF/reg_file.v:9" *)
output [31:0] readData2;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput0;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput1;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput2;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput3;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput4;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput5;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput6;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput7;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput8;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput9;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput10;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput11;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput12;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput13;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput14;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput15;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput16;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput17;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput18;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput19;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput20;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput21;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput22;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput23;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput24;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput25;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput26;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput27;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput28;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput29;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput30;
(* src = "../RF/reg_file.v:11" *)
wire [31:0] regOutput31;
(* src = "../RF/reg_file.v:15" *)
wire [31:0] int;
assign we[31] = regWrite & int[31];
assign we[30] = regWrite & int[30];
assign we[29] = regWrite & int[29];
assign we[28] = regWrite & int[28];
assign we[27] = regWrite & int[27];
assign we[26] = regWrite & int[26];
assign we[25] = regWrite & int[25];
assign we[24] = regWrite & int[24];
assign we[23] = regWrite & int[23];
assign we[22] = regWrite & int[22];
assign we[21] = regWrite & int[21];
assign we[20] = regWrite & int[20];
assign we[19] = regWrite & int[19];
assign we[18] = regWrite & int[18];
assign we[17] = regWrite & int[17];
assign we[16] = regWrite & int[16];
assign we[15] = regWrite & int[15];
assign we[14] = regWrite & int[14];
assign we[13] = regWrite & int[13];
assign we[12] = regWrite & int[12];
assign we[11] = regWrite & int[11];
assign we[10] = regWrite & int[10];
assign we[9] = regWrite & int[9];
assign we[8] = regWrite & int[8];
assign we[7] = regWrite & int[7];
assign we[6] = regWrite & int[6];
assign we[5] = regWrite & int[5];
assign we[4] = regWrite & int[4];
assign we[3] = regWrite & int[3];
assign we[2] = regWrite & int[2];
assign we[1] = regWrite & int[1];
(* src = "../RF/reg_file.v:18" *)
dec_5to32 dec (
.a(writeReg),
.b(int)
);
(* src = "../RF/reg_file.v:53" *)
reg_32bits reg0 (
.d(1'b0),
.clk(clk),
.we(1'b1),
.q(regOutput0)
);
(* src = "../RF/reg_file.v:54" *)
reg_32bits reg1 (
.d(writeData),
.clk(clk),
.we(we[1]),
.q(regOutput1)
);
(* src = "../RF/reg_file.v:55" *)
reg_32bits reg2 (
.d(writeData),
.clk(clk),
.we(we[2]),
.q(regOutput2)
);
(* src = "../RF/reg_file.v:56" *)
reg_32bits reg3 (
.d(writeData),
.clk(clk),
.we(we[3]),
.q(regOutput3)
);
(* src = "../RF/reg_file.v:57" *)
reg_32bits reg4 (
.d(writeData),
.clk(clk),
.we(we[4]),
.q(regOutput4)
);
(* src = "../RF/reg_file.v:58" *)
reg_32bits reg5 (
.d(writeData),
.clk(clk),
.we(we[5]),
.q(regOutput5)
);
(* src = "../RF/reg_file.v:59" *)
reg_32bits reg6 (
.d(writeData),
.clk(clk),
.we(we[6]),
.q(regOutput6)
);
(* src = "../RF/reg_file.v:60" *)
reg_32bits reg7 (
.d(writeData),
.clk(clk),
.we(we[7]),
.q(regOutput7)
);
(* src = "../RF/reg_file.v:61" *)
reg_32bits reg8 (
.d(writeData),
.clk(clk),
.we(we[8]),
.q(regOutput8)
);
(* src = "../RF/reg_file.v:62" *)
reg_32bits reg9 (
.d(writeData),
.clk(clk),
.we(we[9]),
.q(regOutput9)
);
(* src = "../RF/reg_file.v:63" *)
reg_32bits reg10 (
.d(writeData),
.clk(clk),
.we(we[10]),
.q(regOutput10)
);
(* src = "../RF/reg_file.v:64" *)
reg_32bits reg11 (
.d(writeData),
.clk(clk),
.we(we[11]),
.q(regOutput11)
);
(* src = "../RF/reg_file.v:65" *)
reg_32bits reg12 (
.d(writeData),
.clk(clk),
.we(we[12]),
.q(regOutput12)
);
(* src = "../RF/reg_file.v:66" *)
reg_32bits reg13 (
.d(writeData),
.clk(clk),
.we(we[13]),
.q(regOutput13)
);
(* src = "../RF/reg_file.v:67" *)
reg_32bits reg14 (
.d(writeData),
.clk(clk),
.we(we[14]),
.q(regOutput14)
);
(* src = "../RF/reg_file.v:68" *)
reg_32bits reg15 (
.d(writeData),
.clk(clk),
.we(we[15]),
.q(regOutput15)
);
(* src = "../RF/reg_file.v:69" *)
reg_32bits reg16 (
.d(writeData),
.clk(clk),
.we(we[16]),
.q(regOutput16)
);
(* src = "../RF/reg_file.v:70" *)
reg_32bits reg17 (
.d(writeData),
.clk(clk),
.we(we[17]),
.q(regOutput17)
);
(* src = "../RF/reg_file.v:71" *)
reg_32bits reg18 (
.d(writeData),
.clk(clk),
.we(we[18]),
.q(regOutput18)
);
(* src = "../RF/reg_file.v:72" *)
reg_32bits reg19 (
.d(writeData),
.clk(clk),
.we(we[19]),
.q(regOutput19)
);
(* src = "../RF/reg_file.v:73" *)
reg_32bits reg20 (
.d(writeData),
.clk(clk),
.we(we[20]),
.q(regOutput20)
);
(* src = "../RF/reg_file.v:74" *)
reg_32bits reg21 (
.d(writeData),
.clk(clk),
.we(we[21]),
.q(regOutput21)
);
(* src = "../RF/reg_file.v:75" *)
reg_32bits reg22 (
.d(writeData),
.clk(clk),
.we(we[22]),
.q(regOutput22)
);
(* src = "../RF/reg_file.v:76" *)
reg_32bits reg23 (
.d(writeData),
.clk(clk),
.we(we[23]),
.q(regOutput23)
);
(* src = "../RF/reg_file.v:77" *)
reg_32bits reg24 (
.d(writeData),
.clk(clk),
.we(we[24]),
.q(regOutput24)
);
(* src = "../RF/reg_file.v:78" *)
reg_32bits reg25 (
.d(writeData),
.clk(clk),
.we(we[25]),
.q(regOutput25)
);
(* src = "../RF/reg_file.v:79" *)
reg_32bits reg26 (
.d(writeData),
.clk(clk),
.we(we[26]),
.q(regOutput26)
);
(* src = "../RF/reg_file.v:80" *)
reg_32bits reg27 (
.d(writeData),
.clk(clk),
.we(we[27]),
.q(regOutput27)
);
(* src = "../RF/reg_file.v:81" *)
reg_32bits reg28 (
.d(writeData),
.clk(clk),
.we(we[28]),
.q(regOutput28)
);
(* src = "../RF/reg_file.v:82" *)
reg_32bits reg29 (
.d(writeData),
.clk(clk),
.we(we[29]),
.q(regOutput29)
);
(* src = "../RF/reg_file.v:83" *)
reg_32bits reg30 (
.d(writeData),
.clk(clk),
.we(we[30]),
.q(regOutput30)
);
(* src = "../RF/reg_file.v:84" *)
reg_32bits reg31 (
.d(writeData),
.clk(clk),
.we(we[31]),
.q(regOutput31)
);
(* src = "../RF/reg_file.v:87" *)
mux32bits_32to1 rd1 (
.i1(regOutput1),
.i0(regOutput0),
.s(readReg1),
.z(readData1),
.i31(regOutput31),
.i30(regOutput30),
.i29(regOutput29),
.i28(regOutput28),
.i27(regOutput27),
.i26(regOutput26),
.i25(regOutput25),
.i24(regOutput24),
.i23(regOutput23),
.i22(regOutput22),
.i21(regOutput21),
.i20(regOutput20),
.i19(regOutput19),
.i18(regOutput18),
.i17(regOutput17),
.i16(regOutput16),
.i15(regOutput15),
.i14(regOutput14),
.i13(regOutput13),
.i12(regOutput12),
.i11(regOutput11),
.i10(regOutput10),
.i9(regOutput9),
.i8(regOutput8),
.i7(regOutput7),
.i6(regOutput6),
.i5(regOutput5),
.i4(regOutput4),
.i3(regOutput3),
.i2(regOutput2)
);
(* src = "../RF/reg_file.v:90" *)
mux32bits_32to1 rd2 (
.i1(regOutput1),
.i0(regOutput0),
.s(readReg2),
.z(readData2),
.i31(regOutput31),
.i30(regOutput30),
.i29(regOutput29),
.i28(regOutput28),
.i27(regOutput27),
.i26(regOutput26),
.i25(regOutput25),
.i24(regOutput24),
.i23(regOutput23),
.i22(regOutput22),
.i21(regOutput21),
.i20(regOutput20),
.i19(regOutput19),
.i18(regOutput18),
.i17(regOutput17),
.i16(regOutput16),
.i15(regOutput15),
.i14(regOutput14),
.i13(regOutput13),
.i12(regOutput12),
.i11(regOutput11),
.i10(regOutput10),
.i9(regOutput9),
.i8(regOutput8),
.i7(regOutput7),
.i6(regOutput6),
.i5(regOutput5),
.i4(regOutput4),
.i3(regOutput3),
.i2(regOutput2)
);
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_ps7_irq_const_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd0),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/layer_ctrl_def.v"
module layer_ctrl_isolation #(
`ifdef LC_MEM_ENABLE
parameter LC_MEM_DATA_WIDTH = 32,
parameter LC_MEM_ADDR_WIDTH = 32,
`endif
`ifdef LC_INT_ENABLE
parameter LC_INT_DEPTH = 8,
`endif
parameter LC_RF_DEPTH = 128 // 1 ~ 2^8
)
(
// Interface with MBus
input [`ADDR_WIDTH-1:0] TX_ADDR_FROM_LC,
input [`DATA_WIDTH-1:0] TX_DATA_FROM_LC,
input TX_PEND_FROM_LC,
input TX_REQ_FROM_LC,
input PRIORITY_FROM_LC,
input RX_ACK_FROM_LC,
input TX_RESP_ACK_FROM_LC,
// Interface with Registers
input [`LC_RF_DATA_WIDTH-1:0] RF_DATA_FROM_LC,
input [LC_RF_DEPTH-1:0] RF_LOAD_FROM_LC,
`ifdef LC_MEM_ENABLE
// Interface with MEM
input MEM_REQ_OUT_FROM_LC,
input MEM_WRITE_FROM_LC,
input [LC_MEM_DATA_WIDTH-1:0] MEM_DOUT_FROM_LC,
input [LC_MEM_ADDR_WIDTH-3:0] MEM_AOUT_FROM_LC,
`endif
`ifdef LC_INT_ENABLE
// Interrupt
input [LC_INT_DEPTH-1:0] CLR_INT_FROM_LC,
`endif
// Interface with MBus
output reg [`ADDR_WIDTH-1:0] TX_ADDR_TO_MBUS,
output reg [`DATA_WIDTH-1:0] TX_DATA_TO_MBUS,
output reg TX_PEND_TO_MBUS,
output reg TX_REQ_TO_MBUS,
output reg PRIORITY_TO_MBUS,
output reg RX_ACK_TO_MBUS,
output reg TX_RESP_ACK_TO_MBUS,
// Interface with Registers
output reg [`LC_RF_DATA_WIDTH-1:0] RF_DATA_TO_RF,
output reg [LC_RF_DEPTH-1:0] RF_LOAD_TO_RF,
`ifdef LC_MEM_ENABLE
// Interface with MEM
output reg MEM_REQ_OUT_TO_MEM,
output reg MEM_WRITE_TO_MEM,
output reg [LC_MEM_DATA_WIDTH-1:0] MEM_DOUT_TO_MEM,
output reg [LC_MEM_ADDR_WIDTH-3:0] MEM_AOUT_TO_MEM,
`endif
`ifdef LC_INT_ENABLE
// Interrupt
output reg [LC_INT_DEPTH-1:0] CLR_INT_EXTERNAL,
`endif
input LC_ISOLATION
);
always @ *
begin
if (LC_ISOLATION==`IO_HOLD)
begin
TX_ADDR_TO_MBUS <= 0;
TX_DATA_TO_MBUS <= 0;
TX_PEND_TO_MBUS <= 0;
TX_REQ_TO_MBUS <= 0;
PRIORITY_TO_MBUS <= 0;
RX_ACK_TO_MBUS <= 0;
TX_RESP_ACK_TO_MBUS <= 0;
end
else
begin
TX_ADDR_TO_MBUS <= TX_ADDR_FROM_LC;
TX_DATA_TO_MBUS <= TX_DATA_FROM_LC;
TX_PEND_TO_MBUS <= TX_PEND_FROM_LC;
TX_REQ_TO_MBUS <= TX_REQ_FROM_LC;
PRIORITY_TO_MBUS <= PRIORITY_FROM_LC;
RX_ACK_TO_MBUS <= RX_ACK_FROM_LC;
TX_RESP_ACK_TO_MBUS <= TX_RESP_ACK_FROM_LC;
end
end
always @ *
begin
if (LC_ISOLATION==`IO_HOLD)
begin
RF_DATA_TO_RF <= 0;
RF_LOAD_TO_RF <= 0;
end
else
begin
RF_DATA_TO_RF <= RF_DATA_FROM_LC;
RF_LOAD_TO_RF <= RF_LOAD_FROM_LC;
end
end
`ifdef LC_MEM_ENABLE
always @ *
begin
if (LC_ISOLATION==`IO_HOLD)
begin
MEM_REQ_OUT_TO_MEM <= 0;
MEM_WRITE_TO_MEM <= 0;
MEM_DOUT_TO_MEM <= 0;
MEM_AOUT_TO_MEM <= 0;
end
else
begin
MEM_REQ_OUT_TO_MEM <= MEM_REQ_OUT_FROM_LC;
MEM_WRITE_TO_MEM <= MEM_WRITE_FROM_LC;
MEM_DOUT_TO_MEM <= MEM_DOUT_FROM_LC;
MEM_AOUT_TO_MEM <= MEM_AOUT_FROM_LC;
end
end
`endif
`ifdef LC_INT_ENABLE
always @ *
begin
if (LC_ISOLATION==`IO_HOLD)
begin
CLR_INT_EXTERNAL <= 0;
end
else
begin
CLR_INT_EXTERNAL <= CLR_INT_FROM_LC;
end
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V
|
// MBT 7/25/2014
// async pointer
//
// In this design, there are two clock domains. The first
// clock domain (w_) increments the grey-coded pointer; and the
// clock domain (r_) reads the grey-coded pointer.
//
// w_: signals in "receive credits" clock domain
// r_: signals in "spend credits" clock domain
//
// RESET: both resets must be asserted and w_ clock most be posedge toggled
// at least once; and the r_ clock posedge toggled at least three times after that.
// This will be a sufficient number of clocks to pass through the synchronizers.
// ASYNC RESET: w_ clock cannot toggle during reset
`include "bsg_defines.v"
module bsg_async_ptr_gray #(parameter `BSG_INV_PARAM(lg_size_p )
,parameter use_negedge_for_launch_p=0
,parameter use_async_reset_p = 0)
(
input w_clk_i
, input w_reset_i
, input w_inc_i // increment pointer
, input r_clk_i
, output [lg_size_p-1:0] w_ptr_binary_r_o // ptr value; binary
, output [lg_size_p-1:0] w_ptr_gray_r_o // same; gray coded; value before synchronizers
, output [lg_size_p-1:0] w_ptr_gray_r_rsync_o // value after synchronizers
);
logic [lg_size_p-1:0] w_ptr_r, w_ptr_n;
logic [lg_size_p-1:0] w_ptr_p1_r, w_ptr_p1_n, w_ptr_p2;
logic [lg_size_p-1:0] w_ptr_gray_n, w_ptr_gray_r, w_ptr_gray_r_rsync;
// minor fixme: this could possibly be done more efficiently or at least more elegantly
// with a bsg_binary_plus_one_to_gray module. something like
// assign w_ptr_n = w_inc_i ? w_ptr_r+1 : w_ptr_r;
// assign w_ptr_gray_n = w_inc_i ? (bsg_binary_plus_one_to_gray(w_ptr_r) : (wptr_r >> 1) ^ wptr_r;
// cycle time optimization
// assign w_ptr_n = w_ptr_r + w_inc_i;
// assign w_ptr_gray_n = (w_ptr_n >> 1) ^ w_ptr_n;
assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
assign w_ptr_n = w_inc_i ? w_ptr_p1_r : w_ptr_r;
assign w_ptr_p1_n = w_inc_i ? w_ptr_p2 : w_ptr_p1_r;
assign w_ptr_gray_n = w_inc_i ? ((w_ptr_p1_r >> 1) ^ w_ptr_p1_r) : w_ptr_gray_r;
// pointer, in binary
// feature wish: pass in negedge or posedge as parameter!
if (use_async_reset_p == 0) begin: sync
if (use_negedge_for_launch_p)
begin
// synopsys sync_set_reset "w_reset_i"
always @(negedge w_clk_i)
if (w_reset_i)
begin
w_ptr_r <= 0;
w_ptr_p1_r <= 1;
end
else
begin
w_ptr_r <= w_ptr_n;
w_ptr_p1_r <= w_ptr_p1_n;
end
end
else
begin
// synopsys sync_set_reset "w_reset_i"
always @(posedge w_clk_i)
if (w_reset_i)
begin
w_ptr_r <= 0;
w_ptr_p1_r <= 1;
end
else
begin
w_ptr_r <= w_ptr_n;
w_ptr_p1_r <= w_ptr_p1_n;
end
end
end
else begin: async
// we declare shadow registers inside this block
// so that they will pick up the BSG_NO_CLOCK_GATE_X tag
if (use_negedge_for_launch_p)
begin : BSG_NO_CLOCK_GATE_1
logic [lg_size_p-1:0] async_reset_w_ptr_r;
logic [lg_size_p-1:0] async_reset_w_ptr_p1_r;
assign w_ptr_r = async_reset_w_ptr_r;
assign w_ptr_p1_r = async_reset_w_ptr_p1_r;
// synopsys async_set_reset "w_reset_i"
always @(negedge w_clk_i or posedge w_reset_i)
if (w_reset_i)
begin
async_reset_w_ptr_r <= 0;
async_reset_w_ptr_p1_r <= 1;
end
else
begin
async_reset_w_ptr_r <= w_ptr_n;
async_reset_w_ptr_p1_r <= w_ptr_p1_n;
end
end
else
begin : BSG_NO_CLOCK_GATE_2
logic [lg_size_p-1:0] async_reset_w_ptr_r;
logic [lg_size_p-1:0] async_reset_w_ptr_p1_r;
assign w_ptr_r = async_reset_w_ptr_r;
assign w_ptr_p1_r = async_reset_w_ptr_p1_r;
// synopsys async_set_reset "w_reset_i"
always @(posedge w_clk_i or posedge w_reset_i)
if (w_reset_i)
begin
async_reset_w_ptr_r <= 0;
async_reset_w_ptr_p1_r <= 1;
end
else
begin
async_reset_w_ptr_r <= w_ptr_n;
async_reset_w_ptr_p1_r <= w_ptr_p1_n;
end
end
end
assign w_ptr_binary_r_o = w_ptr_r;
// synchronize the grey coded pointer across clock domains
// we use these to send pointers across clock boundaries
// this includes both launch flops and synchronization flops
// these should be abutted in physical design
bsg_launch_sync_sync #(.width_p(lg_size_p)
,.use_negedge_for_launch_p(use_negedge_for_launch_p)
,.use_async_reset_p(use_async_reset_p)) ptr_sync
(
.iclk_i(w_clk_i)
,.iclk_reset_i(w_reset_i)
,.oclk_i(r_clk_i)
,.iclk_data_i(w_ptr_gray_n)
,.iclk_data_o(w_ptr_gray_r)
,.oclk_data_o(w_ptr_gray_r_rsync)
);
// fixme: probably wise to put a dont_touch'ed buffer cell on the launch flop.
assign w_ptr_gray_r_o = w_ptr_gray_r;
assign w_ptr_gray_r_rsync_o = w_ptr_gray_r_rsync;
endmodule
`BSG_ABSTRACT_MODULE(bsg_async_ptr_gray)
|
// File: read_pointerTBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:10:12 2018
`timescale 1ns/10ps
module read_pointerTBV (
);
// myHDL -> Verilog Testbench for `read_pointer` module
reg clk = 0;
reg rst_n = 0;
reg rd = 0;
reg fifo_empty = 0;
wire [4:0] rptr;
wire fifo_rd;
wire read_pointer0_0_fifo_rd_i;
reg [4:0] read_pointer0_0_rptr_i = 0;
always @(rd, fifo_rd, fifo_empty, rst_n, rptr, clk) begin: READ_POINTERTBV_PRINT_DATA
$write("%h", rd);
$write(" ");
$write("%h", fifo_empty);
$write(" ");
$write("%h", rptr);
$write(" ");
$write("%h", fifo_rd);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst_n);
$write("\n");
end
assign read_pointer0_0_fifo_rd_i = ((!fifo_empty) && rd);
always @(posedge clk, negedge rst_n) begin: READ_POINTERTBV_READ_POINTER0_0_POINTERUPDATE
if (rst_n) begin
read_pointer0_0_rptr_i <= 0;
end
else if (read_pointer0_0_fifo_rd_i) begin
read_pointer0_0_rptr_i <= (read_pointer0_0_rptr_i + 1);
end
else begin
read_pointer0_0_rptr_i <= read_pointer0_0_rptr_i;
end
end
assign fifo_rd = read_pointer0_0_fifo_rd_i;
assign rptr = read_pointer0_0_rptr_i;
initial begin: READ_POINTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: READ_POINTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h0: begin
rd <= 1;
end
'ha: begin
rd <= 0;
end
'hc: begin
rd <= 1;
end
'he: begin
fifo_empty <= 1;
end
'h10: begin
rst_n <= 1;
end
'h12: begin
rst_n <= 0;
end
'h14: begin
$finish;
end
default: begin
// pass
end
endcase
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The CPU-TOP module to implement CPU and SRAMs
//
// ====================================================================
`include "e203_defines.v"
module e203_cpu_top(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
// If this signal is high, then indicate the Core have executed WFI instruction
// and entered into the sleep state
output core_wfi,
// This signal is from our self-defined COUNTERSTOP (0xBFF) CSR's TM field
// software can programe this CSR to turn off the MTIME timer to save power
// If this signal is high, then the MTIME timer from CLINT module will stop counting
output tm_stop,
// This signal can be used to indicate the PC value for the core after reset
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// The interface to Debug Module: Begin
//
// The synced debug interrupt back to Debug module
output dbg_irq_r,
// The debug mode CSR registers control interface from/to Debug module
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
// The debug mode control signals from Debug Module
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
input dbg_irq_a,
// The interface to Debug Module: End
// This signal can be used to indicate the HART ID for this core
input [`E203_HART_ID_W-1:0] core_mhartid,
// The External Interrupt signal from PLIC
input ext_irq_a,
// The Software Interrupt signal from CLINT
input sft_irq_a,
// The Timer Interrupt signal from CLINT
input tmr_irq_a,
// The PMU control signal from PMU to control the TCM Shutdown
input tcm_sd,
// The PMU control signal from PMU to control the TCM Deep-Sleep
input tcm_ds,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access ITCM: Begin
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
// External interface (ICB) to access ITCM: End
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access DTCM: Start
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
// External interface (ICB) to access DTCM: End
`endif//}
//////////////////////////////////////////////////////////////
// The Private Peripheral Interface (ICB): Begin
//
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
// The Private Peripheral Interface (ICB): End
//////////////////////////////////////////////////////////////
// The CLINT Interface (ICB): Begin
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
// The CLINT Interface (ICB): End
//////////////////////////////////////////////////////////////
// The PLIC Interface (ICB): Begin
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
// The PLIC Interface (ICB): End
//////////////////////////////////////////////////////////////
// The Fast IO Interface (ICB): Begin
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
// The Fast IO Interface (ICB): End
//////////////////////////////////////////////////////////////
// The System Memory Interface (ICB): Begin
//
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
// The System Memory Interface (ICB): End
// The test mode signal
input test_mode,
// The Clock
input clk,
// The low-level active reset signal, treated as async
input rst_n
);
`ifdef E203_HAS_ITCM //{
wire itcm_ls;
wire rst_itcm;
wire itcm_ram_cs ;
wire itcm_ram_we ;
wire [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
wire [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
`endif//}
wire clk_itcm_ram ;
`endif//}
`ifdef E203_HAS_DTCM //{
wire dtcm_ls;
wire rst_dtcm;
wire dtcm_ram_cs ;
wire dtcm_ram_we ;
wire [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
wire [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
`endif//}
wire clk_dtcm_ram ;
`endif//}
`ifndef E203_HAS_LOCKSTEP//{
wire ppi_icb_rsp_excl_ok ;
wire fio_icb_rsp_excl_ok ;
wire plic_icb_rsp_excl_ok ;
wire clint_icb_rsp_excl_ok ;
wire mem_icb_rsp_excl_ok ;
`ifdef E203_HAS_PPI
wire ppi_icb_enable;
wire [`E203_ADDR_SIZE-1:0] ppi_region_indic;
`endif
`ifdef E203_HAS_PLIC
wire plic_icb_enable;
wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
`endif
`ifdef E203_HAS_CLINT
wire clint_icb_enable;
wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
`endif
`ifdef E203_HAS_MEM_ITF
wire mem_icb_enable;
`endif
`ifdef E203_HAS_FIO
wire fio_icb_enable;
wire [`E203_ADDR_SIZE-1:0] fio_region_indic;
`endif
`endif//}
assign ppi_icb_rsp_excl_ok = 1'b0;
assign fio_icb_rsp_excl_ok = 1'b0;
assign plic_icb_rsp_excl_ok = 1'b0;
assign clint_icb_rsp_excl_ok = 1'b0;
assign mem_icb_rsp_excl_ok = 1'b0;
`ifdef E203_HAS_PPI
assign ppi_icb_enable = 1'b1;
assign ppi_region_indic = `E203_PPI_ADDR_BASE;
`else
assign ppi_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_PLIC
assign plic_icb_enable = 1'b1;
assign plic_region_indic = `E203_PLIC_ADDR_BASE;
`else
assign plic_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_CLINT
assign clint_icb_enable = 1'b1;
assign clint_region_indic = `E203_CLINT_ADDR_BASE;
`else
assign clint_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_MEM_ITF
assign mem_icb_enable = 1'b1;
`else
assign mem_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_FIO
assign fio_icb_enable = 1'b1;
assign fio_region_indic = `E203_FIO_ADDR_BASE;
`else
assign fio_icb_enable = 1'b0;
`endif
e203_cpu #(.MASTER(1)) u_e203_cpu(
.inspect_pc (inspect_pc),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_mem_cmd_valid (inspect_mem_cmd_valid),
.inspect_mem_cmd_ready (inspect_mem_cmd_ready),
.inspect_mem_rsp_valid (inspect_mem_rsp_valid),
.inspect_mem_rsp_ready (inspect_mem_rsp_ready),
.inspect_core_clk (inspect_core_clk ),
.core_csr_clk (core_csr_clk ),
.tm_stop (tm_stop),
.pc_rtvec(pc_rtvec),
`ifdef E203_HAS_ITCM //{
.itcm_ls (itcm_ls),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ls (dtcm_ls),
`endif//}
.core_wfi (core_wfi),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq_a),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (),
.ppi_icb_cmd_excl (),
.ppi_icb_cmd_size (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok ),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.clint_region_indic (clint_region_indic),
.clint_icb_enable (clint_icb_enable),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (),
.clint_icb_cmd_excl (),
.clint_icb_cmd_size (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok ),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
.plic_region_indic (plic_region_indic),
.plic_icb_enable (plic_icb_enable),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (),
.plic_icb_cmd_excl (),
.plic_icb_cmd_size (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok ),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (),
.fio_icb_cmd_excl (),
.fio_icb_cmd_size (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (),
.mem_icb_cmd_excl (),
.mem_icb_cmd_size (),
.mem_icb_cmd_burst (),
.mem_icb_cmd_beat (),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
.test_mode (test_mode),
`ifndef E203_HAS_LOCKSTEP//{
`endif//}
.rst_n (rst_n),
.clk (clk )
);
e203_srams u_e203_srams(
`ifdef E203_HAS_DTCM //{
.dtcm_ram_sd (tcm_sd),
.dtcm_ram_ds (tcm_ds),
.dtcm_ram_ls (dtcm_ls),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_sd (tcm_sd),
.itcm_ram_ds (tcm_ds),
.itcm_ram_ls (itcm_ls),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
.test_mode (test_mode)
);
endmodule
|
//
// 2 read-port, 1 write-port ram
//
// reads are synchronous
//
//
module bsg_mem_2r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
// add a parameter to switch between implementations of hard and soft macro
, parameter substitute_2r1w_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
if (substitute_2r1w_p)
begin: s2r1w
logic [width_p-1:0] r0_data_lo, r1_data_lo;
bsg_mem_2r1w #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(0)
) mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (w_v_i & w_v_i)
,.w_addr_i (w_addr_i)
,.w_data_i (w_data_i)
,.r0_v_i (r0_v_i & ~r0_v_i)
,.r0_addr_i(r0_addr_i)
,.r0_data_o(r0_data_lo)
,.r1_v_i (r1_v_i & ~r1_v_i)
,.r1_addr_i(r1_addr_i)
,.r1_data_o(r1_data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i) begin
r0_data_o <= r0_data_lo;
r1_data_o <= r1_data_lo;
end
end
else
if ((width_p == 32) && (els_p == 32))
begin: macro
// synopsys translate_off
initial
begin
assert(read_write_same_addr_p==0)
else
begin
$error("%L: this configuration does not permit simultaneous read and writes! (%m)");
$finish();
end
end
// synopsys translate_on
// use two 1R1W rams to create
tsmc40_2rf_lg5_w32_m2 mem0
(
//write port
.AA ( w_addr_i )
,.D ( w_data_i )
,.BWEB ( 32'b0 )
,.WEB ( ~w_v_i )
,.CLKW ( clk_i )
//read port
,.AB ( r0_addr_i )
,.REB ( ~r0_v_i )
,.CLKR ( clk_i )
,.Q ( r0_data_o )
,.RDELAY ( 2'b00 )
,.WDELAY ( 2'b00 )
);
tsmc40_2rf_lg5_w32_m2 mem1
(
//write port
.AA ( w_addr_i )
,.D ( w_data_i )
,.BWEB ( 32'b0 )
,.WEB ( ~w_v_i )
,.CLKW ( clk_i )
//read port
,.AB ( r1_addr_i )
,.REB ( ~r1_v_i )
,.CLKR ( clk_i )
,.Q ( r1_data_o )
,.RDELAY ( 2'b00 )
,.WDELAY ( 2'b00 )
);
end // block: macro
else
begin: notmacro
bsg_mem_2r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
end
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module hapara_bram_dma_switch_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output [C_S_AXI_DATA_WIDTH - 1 : 0] base,
output [C_S_AXI_DATA_WIDTH - 1 : 0] length,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
assign base = slv_reg0;
assign length = slv_reg1;
// User logic ends
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim, Ye-sheng Kuo
//Last Modified: Aug 23 2017
//Description: (Testbench) MBus Isolation for Master/Member Layer
//Update History: Mar 16 2013 - First committed (Ye-sheng Kuo)
// May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Dec 16 2016 - Updated for MBus r04 (Yejoong Kim)
// Added MBUS_BUSY isolation
// Apr 28 2017 - Updated for MBus r04p1
// Removed SLEEP_REQ* and MBUS_BUSY isolation.
// These should be isolated in mbus_master_ctrl or mbus_member_ctrl.
// Aug 23 2017 - Checked for mbus_testbench
//*******************************************************************************************
`include "include/mbus_def_testbench.v"
module mbus_isolation_testbench(
input MBC_ISOLATE,
// Layer Ctrl --> MBus Ctrl
input [`MBUSTB_ADDR_WIDTH-1:0] TX_ADDR_uniso,
input [`MBUSTB_DATA_WIDTH-1:0] TX_DATA_uniso,
input TX_PEND_uniso,
input TX_REQ_uniso,
input TX_PRIORITY_uniso,
input RX_ACK_uniso,
input TX_RESP_ACK_uniso,
output reg [`MBUSTB_ADDR_WIDTH-1:0] TX_ADDR,
output reg [`MBUSTB_DATA_WIDTH-1:0] TX_DATA,
output reg TX_PEND,
output reg TX_REQ,
output reg TX_PRIORITY,
output reg RX_ACK,
output reg TX_RESP_ACK,
// NOTE: This testbench does not include Layer Controller
// Layer Ctrl --> Other
//`ifdef LNAME_LAYERCTRL_INT_ENABLE
//input [`LNAME_LAYERCTRL_INT_DEPTH-1:0] LC_CLR_INT_uniso,
//output reg [`LNAME_LAYERCTRL_INT_DEPTH-1:0] LC_CLR_INT,
//`endif
// MBus Ctrl --> Other
input LRC_SLEEP_uniso,
input LRC_CLKENB_uniso,
input LRC_RESET_uniso,
input LRC_ISOLATE_uniso,
output reg LRC_SLEEP,
output LRC_SLEEPB,
output reg LRC_CLKENB,
output LRC_CLKEN,
output reg LRC_RESET,
output LRC_RESETB,
output reg LRC_ISOLATE
);
assign LRC_SLEEPB = ~LRC_SLEEP;
assign LRC_CLKEN = ~LRC_CLKENB;
assign LRC_RESETB = ~LRC_RESET;
//********************************************
// Isolated using MBC_ISOLATE
//********************************************
always @* begin
if (MBC_ISOLATE) begin
LRC_SLEEP = 1;
LRC_CLKENB = 1;
LRC_RESET = 1;
LRC_ISOLATE = 1;
end
else begin
LRC_SLEEP = LRC_SLEEP_uniso;
LRC_CLKENB = LRC_CLKENB_uniso;
LRC_RESET = LRC_RESET_uniso;
LRC_ISOLATE = LRC_ISOLATE_uniso;
end
end
//********************************************
// Isolated using LRC_ISOLATE
//********************************************
always @* begin
if (LRC_ISOLATE) begin
TX_ADDR = 0;
TX_DATA = 0;
TX_PEND = 0;
TX_REQ = 0;
TX_PRIORITY = 0;
RX_ACK = 0;
TX_RESP_ACK = 0;
//`ifdef LNAME_LAYERCTRL_INT_ENABLE
// LC_CLR_INT = 0;
//`endif
end
else begin
TX_ADDR = TX_ADDR_uniso;
TX_DATA = TX_DATA_uniso;
TX_PEND = TX_PEND_uniso;
TX_REQ = TX_REQ_uniso;
TX_PRIORITY = TX_PRIORITY_uniso;
RX_ACK = RX_ACK_uniso;
TX_RESP_ACK = TX_RESP_ACK_uniso;
//`ifdef LNAME_LAYERCTRL_INT_ENABLE
// LC_CLR_INT = LC_CLR_INT_uniso;
//`endif
end
end
endmodule // mbus_isolation_testbench
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_rx_core
#(
parameter ABUSWIDTH = 16,
parameter [1:0] ADC_ID = 0,
parameter [0:0] HEADER_ID = 0
)
(
input wire ADC_ENC,
input wire [13:0] ADC_IN,
input wire ADC_SYNC,
input wire ADC_TRIGGER,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 1;
// 0 - soft reset
// 1 - start/status
//TODO:
// - external trigger /rising falling
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000; // CONF_START_WITH_SYNC = TRUE
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 0;
status_regs[6] <= 1;
status_regs[7] <= 0;
status_regs[8] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
wire START;
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_WITH_SYNC;
assign CONF_START_WITH_SYNC = status_regs[2][0];
wire CONF_EN_EX_TRIGGER;
assign CONF_EN_EX_TRIGGER = status_regs[2][1];
wire CONF_SINGLE_DATA;
assign CONF_SINGLE_DATA = status_regs[2][2];
wire [23:0] CONF_DATA_CNT;
assign CONF_DATA_CNT = {status_regs[5], status_regs[4], status_regs[3]};
wire [7:0] CONF_SAMPLE_SKIP = status_regs[6];
wire [7:0] CONF_SAMPEL_DLY = status_regs[7];
reg [7:0] CONF_ERROR_LOST;
assign LOST_ERROR = CONF_ERROR_LOST != 0;
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_ERROR_LOST;
else if(BUS_ADD < 16)
BUS_DATA_OUT <= BUS_STATUS_OUT;
end
end
wire rst_adc_sync;
cdc_reset_sync isync_rst (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(ADC_ENC), .pulse_out(rst_adc_sync));
wire start_adc_sync;
cdc_pulse_sync istart_rst (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(ADC_ENC), .pulse_out(start_adc_sync));
wire adc_sync_pulse;
pulse_gen_rising pulse_adc_sync (.clk_in(ADC_ENC), .in(ADC_SYNC), .out(adc_sync_pulse));
//long reset is needed
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
/*
reg [7:0] align_cnt;
always@(posedge ADC_ENC) begin
if(adc_sync_pulse)
align_cnt <= 0;
else if(align_cnt == (CONF_SAMPLE_SKIP - 1))
align_cnt <= 0;
else
align_cnt <= align_cnt + 1;
end
*/
reg adc_sync_wait;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
adc_sync_wait <= 0;
else if(start_adc_sync)
adc_sync_wait <= 1;
else if (adc_sync_pulse)
adc_sync_wait <= 0;
end
wire start_data_count;
assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
reg [23:0] rec_cnt;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
rec_cnt <= 0;
else if(start_data_count && (rec_cnt > CONF_DATA_CNT || rec_cnt == 0))
rec_cnt <= 1;
else if(rec_cnt != -1 && rec_cnt>0 && CONF_DATA_CNT!=0 )
rec_cnt <= rec_cnt + 1;
end
wire DONE;
assign DONE = rec_cnt > CONF_DATA_CNT;
reg cdc_fifo_write_single;
always@(*) begin
if(CONF_DATA_CNT==0 && rec_cnt>=1) //forever
cdc_fifo_write_single = 1;
else if(rec_cnt>=1 && rec_cnt <= CONF_DATA_CNT) //to CONF_DATA_CNT
cdc_fifo_write_single = 1;
else
cdc_fifo_write_single = 0;
end
reg [13:0] prev_data;
reg prev_sync;
reg prev_ready;
always@(posedge ADC_ENC) begin
if(rst_adc_sync || start_adc_sync)
prev_ready <= 0;
else
prev_ready <= !prev_ready;
end
//
reg [13:0] ADC_IN_DLY, adc_dly_mem;
reg [13:0] dly_mem [255:0];
reg [7:0] dly_addr_read, dly_addr_write;
always@(posedge ADC_ENC)
if(rst_adc_sync)
dly_addr_write <= 0;
else
dly_addr_write <= dly_addr_write + 1;
always@(posedge ADC_ENC)
dly_mem[dly_addr_write] <= ADC_IN;
always@(posedge ADC_ENC)
adc_dly_mem <= dly_mem[dly_addr_read];
always@(*) begin
dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
end
//
always@(posedge ADC_ENC) begin
prev_data <= ADC_IN_DLY;
prev_sync <= ADC_SYNC;
end
wire fifo_full, cdc_fifo_empty, cdc_fifo_write_double;
assign cdc_fifo_write_double = cdc_fifo_write_single && prev_ready; //write every second
wire wfull;
reg cdc_fifo_write;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
CONF_ERROR_LOST <= 0;
else if (CONF_ERROR_LOST!=8'hff && wfull && cdc_fifo_write)
CONF_ERROR_LOST <= CONF_ERROR_LOST +1;
end
reg [31:0] data_to_fifo;
always@(*) begin
if(CONF_SINGLE_DATA)
data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
else
data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
if(CONF_SINGLE_DATA)
cdc_fifo_write = cdc_fifo_write_single;
else
cdc_fifo_write = cdc_fifo_write_double;
end
wire [31:0] cdc_data_out;
cdc_syncfifo #(.DSIZE(32), .ASIZE(3)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_fifo), //.wdata({ADC_SYNC,2'd0,ADC_SYNC,14'd0,adc_des}),
.winc(cdc_fifo_write), .wclk(ADC_ENC), .wrst(RST_LONG),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(RST_LONG)
);
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size());
//assign FIFO_DATA[31:30] = 0;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(ADC_ENC), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : mem_stage.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/cpu/mem_stage.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-12-08 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "isa.h"
`include "cpu.h"
module mem_stage (
input wire clk,
input wire reset,
input wire stall,
input wire flush,
output wire busy,
output wire [`WordDataBus] fwd_data,
input wire [`WordDataBus] spm_rd_data,
output wire [`WordAddrBus] spm_addr,
output wire spm_as_n,
output wire spm_rw,
output wire [`WordDataBus] spm_wr_data,
input wire [`WordDataBus] bus_rd_data,
input wire bus_rdy_n,
input wire bus_grant_n,
output wire bus_req_n,
output wire [`WordAddrBus] bus_addr,
output wire bus_as_n,
output wire bus_rw,
output wire [`WordDataBus] bus_wr_data,
input wire [`WordAddrBus] ex_pc,
input wire ex_en,
input wire ex_br_flag,
input wire [`MemOpBus] ex_mem_op,
input wire [`WordDataBus] ex_mem_wr_data,
input wire [`CtrlOpBus] ex_ctrl_op,
input wire [`RegAddrBus] ex_dst_addr,
input wire ex_gpr_we_n,
input wire [`IsaExpBus] ex_exp_code,
input wire [`WordDataBus] ex_out,
output wire [`WordAddrBus] mem_pc,
output wire mem_en,
output wire mem_br_flag,
output wire [`CtrlOpBus] mem_ctrl_op,
output wire [`RegAddrBus] mem_dst_addr,
output wire mem_gpr_we_n,
output wire [`IsaExpBus] mem_exp_code,
output wire [`WordDataBus] mem_out
);
wire [`WordDataBus] rd_data;
wire [`WordAddrBus] addr;
wire as_n;
wire rw;
wire [`WordDataBus] wr_data;
wire [`WordDataBus] out;
wire miss_align;
assign fwd_data = out;
mem_ctrl mem_ctrl (
.ex_en (ex_en),
.ex_mem_op (ex_mem_op),
.ex_mem_wr_data (ex_mem_wr_data),
.ex_out (ex_out),
.rd_data (rd_data),
.addr (addr),
.as_n (as_n),
.rw (rw),
.wr_data (wr_data),
.out (out),
.miss_align (miss_align)
);
bus_if bus_if (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (flush),
.busy (busy),
.addr (addr),
.as_n (as_n),
.rw (rw),
.wr_data (wr_data),
.rd_data (rd_data),
.spm_rd_data (spm_rd_data),
.spm_addr (spm_addr),
.spm_as_n (spm_as_n),
.spm_rw (spm_rw),
.spm_wr_data (spm_wr_data),
.bus_rd_data (bus_rd_data),
.bus_rdy_n (bus_rdy_n),
.bus_grant_n (bus_grant_n),
.bus_req_n (bus_req_n),
.bus_addr (bus_addr),
.bus_as_n (bus_as_n),
.bus_rw (bus_rw),
.bus_wr_data (bus_wr_data)
);
mem_reg mem_reg (
.clk (clk),
.reset (reset),
.out (out),
.miss_align (miss_align),
.stall (stall),
.flush (flush),
.ex_pc (ex_pc),
.ex_en (ex_en),
.ex_br_flag (ex_br_flag),
.ex_ctrl_op (ex_ctrl_op),
.ex_dst_addr (ex_dst_addr),
.ex_gpr_we_n (ex_gpr_we_n),
.ex_exp_code (ex_exp_code),
.mem_pc (mem_pc),
.mem_en (mem_en),
.mem_br_flag (mem_br_flag),
.mem_ctrl_op (mem_ctrl_op),
.mem_dst_addr (mem_dst_addr),
.mem_gpr_we_n (mem_gpr_we_n),
.mem_exp_code (mem_exp_code),
.mem_out (mem_out)
);
endmodule
|
(** * References: Typing Mutable References *)
(** Up to this point, we have considered a variety of _pure_
language features, including functional abstraction, basic types
such as numbers and booleans, and structured types such as records
and variants. These features form the backbone of most
programming languages -- including purely functional languages
such as Haskell and "mostly functional" languages such as ML, as
well as imperative languages such as C and object-oriented
languages such as Java, C[#], and Scala.
However, most practical languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, computation in these languages may assign to mutable
variables (reference cells, arrays, mutable record fields, etc.);
perform input and output to files, displays, or network
connections; make non-local transfers of control via exceptions,
jumps, or continuations; engage in inter-process synchronization
and communication; and so on. In the literature on programming
languages, such "side effects" of computation are collectively
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational effect --
mutable references -- can be added to the calculi we have studied.
The main extension will be dealing explicitly with a _store_ (or
_heap_) and _pointers_ that name store locations. This extension
is fairly straightforward to define; the most interesting part is
the refinement we need to make to the statement of the type
preservation theorem. *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Strings.String.
From Coq Require Import Arith.Arith.
From Coq Require Import Lia.
From PLF Require Import Maps.
From PLF Require Import Smallstep.
From Coq Require Import Lists.List.
(* ################################################################# *)
(** * Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language Gallina is a
rare exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] to assign a new value to the
cell that it points to (by writing [y:=84]), but we cannot use [y]
directly as an argument to an operation like [+]. Instead, we
must explicitly _dereference_ it, writing [!y] to obtain its
current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a
mutable cell, and the operation of dereferencing a variable to
obtain its current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit. *)
(* ################################################################# *)
(** * Syntax *)
(** In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and reduces to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] reduces
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. *)
(* ----------------------------------------------------------------- *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. Besides the base natural number type and arrow
types, we need to add two more types to deal with
references. First, we need the _unit type_, which we will use as
the result type of an assignment operation. We then add
_reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references to
cells holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| Ty_Nat : ty
| Ty_Unit : ty
| Ty_Arrow : ty -> ty -> ty
| Ty_Ref : ty -> ty.
(* ----------------------------------------------------------------- *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tm_var : string -> tm
| tm_app : tm -> tm -> tm
| tm_abs : string -> ty -> tm -> tm
| tm_const : nat -> tm
| tm_succ : tm -> tm
| tm_pred : tm -> tm
| tm_mult : tm -> tm -> tm
| tm_if0 : tm -> tm -> tm -> tm
(* New terms: *)
| tm_unit : tm
| tm_ref : tm -> tm
| tm_deref : tm -> tm
| tm_assign : tm -> tm -> tm
| tm_loc : nat -> tm.
Declare Custom Entry stlc.
Notation "<{ e }>" := e (e custom stlc at level 99).
Notation "( x )" := x (in custom stlc, x at level 99).
Notation "x" := x (in custom stlc at level 0, x constr at level 0).
Notation "S -> T" := (Ty_Arrow S T) (in custom stlc at level 50, right associativity).
Notation "x y" := (tm_app x y) (in custom stlc at level 1, left associativity).
Notation "\ x : t , y" :=
(tm_abs x t y) (in custom stlc at level 90, x at level 99,
t custom stlc at level 99,
y custom stlc at level 99,
left associativity).
Coercion tm_var : string >-> tm.
Notation "{ x }" := x (in custom stlc at level 0, x constr).
Notation "'Unit'" :=
(Ty_Unit) (in custom stlc at level 0).
Notation "'unit'" := tm_unit (in custom stlc at level 0).
Notation "'Natural'" := Ty_Nat (in custom stlc at level 0).
Notation "'succ' x" := (tm_succ x) (in custom stlc at level 0,
x custom stlc at level 0).
Notation "'pred' x" := (tm_pred x) (in custom stlc at level 0,
x custom stlc at level 0).
Notation "x * y" := (tm_mult x y) (in custom stlc at level 1,
left associativity).
Notation "'if0' x 'then' y 'else' z" :=
(tm_if0 x y z) (in custom stlc at level 89,
x custom stlc at level 99,
y custom stlc at level 99,
z custom stlc at level 99,
left associativity).
Coercion tm_const : nat >-> tm.
Notation "'Ref' t" :=
(Ty_Ref t) (in custom stlc at level 4).
Notation "'loc' x" := (tm_loc x) (in custom stlc at level 2).
Notation "'ref' x" := (tm_ref x) (in custom stlc at level 2).
Notation "'!' x " := (tm_deref x) (in custom stlc at level 2).
Notation " e1 ':=' e2 " := (tm_assign e1 e2) (in custom stlc at level 21).
(** Intuitively:
- [ref t] (formally, [ref t]) allocates a new reference cell
with the value [t] and reduces to the location of the newly
allocated cell;
- [!t] (formally, [deref t]) reduces to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [assign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [loc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. (It
would be easy to do so, since there are no very interesting
interactions between those features and references.) *)
(* ----------------------------------------------------------------- *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T1
-------------------- (T_Deref)
Gamma |- !t1 : T1
Gamma |- t1 : Ref T2
Gamma |- t2 : T2
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ----------------------------------------------------------------- *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T2 t1,
value <{\x:T2, t1}>
| v_nat : forall n : nat ,
value <{ n }>
| v_unit :
value <{ unit }>
| v_loc : forall l,
value <{ loc l }>.
Hint Constructors value : core.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Reserved Notation "'[' x ':=' s ']' t" (in custom stlc at level 20, x constr).
Fixpoint subst (x : string) (s : tm) (t : tm) : tm :=
match t with
(* pure STLC *)
| tm_var y =>
if eqb_string x y then s else t
| <{\y:T, t1}> =>
if eqb_string x y then t else <{\y:T, [x:=s] t1}>
| <{t1 t2}> =>
<{([x:=s] t1) ([x:=s] t2)}>
(* numbers *)
| tm_const _ =>
t
| <{succ t1}> =>
<{succ [x := s] t1}>
| <{pred t1}> =>
<{pred [x := s] t1}>
| <{t1 * t2}> =>
<{ ([x := s] t1) * ([x := s] t2)}>
| <{if0 t1 then t2 else t3}> =>
<{if0 [x := s] t1 then [x := s] t2 else [x := s] t3}>
(* unit *)
| <{ unit }> =>
<{ unit }>
(* references *)
| <{ ref t1 }> =>
<{ ref ([x:=s] t1) }>
| <{ !t1 }> =>
<{ !([x:=s] t1) }>
| <{ t1 := t2 }> =>
<{ ([x:=s] t1) := ([x:=s] t2) }>
| <{ loc _ }> =>
t
end
where "'[' x ':=' s ']' t" := (subst x s t) (in custom stlc).
(* ################################################################# *)
(** * Pragmatics *)
(* ================================================================= *)
(** ** Side Effects and Sequencing *)
(** The fact that we've chosen the result of an assignment
expression to be the trivial value [unit] allows a nice
abbreviation for _sequencing_. For example, we can write
r:=succ(!r); !r
as an abbreviation for
(\x:Unit. !r) (r:=succ(!r)).
This has the effect of reducing two expressions in order and
returning the value of the second. Restricting the type of the
first expression to [Unit] helps the typechecker to catch some
silly errors by permitting us to throw away the first value only
if it is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
*)
(** Formally, we introduce sequencing as a _derived form_
[tseq] that expands into an abstraction and an application. *)
Definition x : string := "x".
Definition y : string := "y".
Definition z : string := "z".
Hint Unfold x : core.
Hint Unfold y : core.
Hint Unfold z : core.
Definition tseq t1 t2 :=
<{ (\ x : Unit, t2) t1 }>.
Notation "t1 ; t2" := (tseq t1 t2) (in custom stlc at level 3).
(* ================================================================= *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to some variable [r] and the _cell_
in the store that is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after reducing
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
r := 5; r := !s
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
r := !s
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ================================================================= *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
*)
(** Note that, since their argument types are [Unit], the
arguments to the abstractions in the definitions of [incc] and
[decc] are not providing any useful information to the bodies of
these functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose of these
abstractions is to "slow down" the execution of the function
bodies. Since function abstractions are values, the two [let]s are
executed simply by binding these functions to the names [incc] and
[decc], rather than by actually incrementing or decrementing [c].
Later, each call to one of these functions results in its body
being executed once and performing the appropriate mutation on
[c]. Such functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(* ================================================================= *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
*)
(** **** Exercise: 1 star, standard, optional (store_draw)
Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(*
c1: (i, d), i and d both refers to a ref cell c.
c1: (i, d), i and d both refers to a different ref cell c.
*)
(* [] *)
(* ================================================================= *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give an (inefficient) implementation of arrays
of numbers, as follows. Write [NaturalArray] for the type
[Ref (Natural->Natural)].
Recall the [equal] function from the [MoreStlc] chapter:
equal =
fix
(\eq:Natural->Natural->Bool.
\m:Natural. \n:Natural.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
To build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
newarray = \_:Unit. ref (\n:Natural.0)
To look up an element of an array, we simply apply
the function to the desired index.
lookup = \a:NaturalArray. \n:Natural. (!a) n
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], while on all other indices it passes the
lookup to the function that was previously stored in the reference.
update = \a:NaturalArray. \m:Natural. \v:Natural.
let oldf = !a in
a := (\n:Natural. if equal m n then v else oldf n);
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars, standard, especially useful (compact_update)
If we defined [update] more compactly like this
update = \a:NaturalArray. \m:Natural. \v:Natural.
a := (\n:Natural. if equal m n then v else (!a) n)
would it behave the same? *)
(*
Not the same.
In the first version, oldf takes out a copy of the function
in the refcell a, then when assigning a with a different function, it
refers to the copy of the old function.
In the second version, when n<>m, the else branch will try to get the current
function inside refcell a. Effectively creating an infinite loop.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_compact_update : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Null References *)
(** There is one final significant difference between our
references and C-style mutable variables: in C-like languages,
variables holding pointers into the heap may sometimes have the
value [NULL]. Dereferencing such a "null pointer" is an error,
and results either in a clean exception (Java and C[#]) or in
arbitrary and possibly insecure behavior (C and relatives like
C++). Null pointers cause significant trouble in C-like
languages: the fact that any pointer might be null means that any
dereference operation in the program can potentially fail.
Even in ML-like languages, there are occasionally situations where
we may or may not have a valid pointer in our hands. Fortunately,
there is no need to extend the basic mechanisms of references to
represent such situations: the sum types introduced in the
[MoreStlc] chapter already give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter of _Logical Foundations_.
Define [Option T] to be an abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ================================================================= *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, automatically identifying and reusing cells that can
no longer be reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. One reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Natural] and the
other with type [Ref Bool]. *)
(** **** Exercise: 2 stars, standard (type_safety_violation)
Show how this can lead to a violation of type safety. *)
(*
Say pointer A is created to refer to a refcell of type Nat, then the
refcell gets deallocated. Later a pointer B is created to refer to a
refcell of type Bool. Suppose the refcell holding a Bool happens to
overlap with the deallocated refcell holding the Nat. Then when we
read from A (dangling pointer), it can may read out corrupted data
because the underlying memory representation for Bool and Nat may be
different.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_type_safety_violation : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Operational Semantics *)
(* ================================================================= *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that reducing a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming-language implementations is
essentially just a big array of bytes. The run-time system keeps
track of which parts of this array are currently in use; when we
need to allocate a new reference cell, we allocate a large enough
segment from the free region of the store (4 bytes for integer
cells, 8 bytes for cells storing [Float]s, etc.), record somewhere
that it is being used, and return the index (typically, a 32- or
64-bit integer) of the start of the newly allocated region. These
indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is convenient to use
numbers.) We use the word _location_ instead of _reference_ or
_pointer_ to emphasize this abstract quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type-safety violations. *)
(* ================================================================= *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
Imp, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in Imp, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we didn't use this representation
before is that, in Imp, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [ref t1], which puts the value of [t1]
in a new reference cell and reduces to the location of the newly
created reference cell. When reducing such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
that we don't will require a bit of work.) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st <{ unit }>.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** As might be expected, we will also need some technical
lemmas about [replace]; they are straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
- (* st = [] *)
inversion Hlen.
- (* st = t' :: st' *)
destruct l; simpl...
apply IHst'. simpl in Hlen. lia.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
- (* l1 = 0 *)
destruct st.
+ (* st = [] *) rewrite replace_nil...
+ (* st = _ :: _ *) destruct l2... contradict Hneq...
- (* l1 = S l1' *)
destruct st as [|t2 st2].
+ (* st = [] *) destruct l2...
+ (* st = t2 :: st2 *)
destruct l2...
simpl; apply IHl1'...
Qed.
(* ================================================================= *)
(** ** Reduction *)
(** Next, we need to extend the operational semantics to take
stores into account. Since the result of reducing an expression
will in general depend on the contents of the store in which it is
reduced, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the reduction of a
term can cause side effects on the store, and these may affect the
reduction of other terms in the future, the reduction rules need
to return a new store. Thus, the shape of the single-step
reduction relation needs to change from [t --> t'] to [t / st --> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing reduction rules with stores:
value v2
------------------------------------- (ST_AppAbs)
(\x:T2.t1) v2 / st --> [x:=v2]t1 / st
t1 / st --> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st --> t1' t2 / st'
value v1 t2 / st --> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st --> v1 t2' / st'
Note that the first rule here returns the store unchanged, since
function application, in itself, has no side effects. The other
two rules simply propagate side effects from premise to
conclusion.
Now, the result of reducing a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values. It is crucial to note that making this
extension to the syntax of terms does not mean that we intend
_programmers_ to write terms involving explicit, concrete locations:
such terms will arise only as intermediate results during reduction.
This may seem odd, but it follows naturally from our design decision
to represent the result of every reduction step by a modified _term_.
If we had chosen a more "machine-like" model, e.g., with an explicit
stack to contain values of bound identifiers, then the idea of adding
locations to the set of allowed values might seem more obvious.
In terms of this expanded syntax, we can state reduction rules
for the new constructs that manipulate locations and the store.
First, to reduce a dereferencing expression [!t1], we must first
reduce [t1] until it becomes a value:
t1 / st --> t1' / st'
--------------------- (ST_Deref)
!t1 / st --> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to dereference a
location that is larger than the size [|st|] of the currently
allocated store; the reduction rules simply get stuck in this
case. The type-safety properties established below assure us
that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st --> lookup l st / st
Next, to reduce an assignment expression [t1:=t2], we must first
reduce [t1] until it becomes a value (a location), and then
reduce [t2] until it becomes a value (of any sort):
t1 / st --> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st --> t1' := t2 / st'
t2 / st --> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st --> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v], which we execute by updating the store to make
location [l] contain [v]:
l < |st|
----------------------------------- (ST_Assign)
loc l := v / st --> unit / [l:=v]st
The notation [[l:=v]st] means "the store that maps [l] to [v]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this reduction step is just [unit];
the interesting result is the updated store.
Finally, to reduct an expression of the form [ref t1], we first
reduce [t1] until it becomes a value:
t1 / st --> t1' / st'
--------------------------- (ST_Ref)
ref t1 / st --> ref t1' / st'
Then, to reduce the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v].
-------------------------------- (ST_RefValue)
ref v / st --> loc |st| / st,v
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v] means [st ++ v::nil] -- i.e., to add
a new reference cell to the store, we append it to the end.)
Note that these reduction rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as reduction proceeds. This does not affect the
correctness of the results of reduction (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
reduction), but it means that a naive implementation of our
evaluator might run out of memory where a more sophisticated
evaluator would be able to continue by reusing locations whose
contents have become garbage.
Here are the rules again, formally: *)
Reserved Notation "t '/' st '-->' t' '/' st'"
(at level 40, st at level 39, t' at level 39).
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T2 t1 v2 st,
value v2 ->
<{ (\x : T2, t1) v2 }> / st --> <{ [x := v2] t1 }> / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st --> t1' / st' ->
<{ t1 t2 }> / st --> <{ t1' t2 }> / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st --> t2' / st' ->
<{ v1 t2 }> / st --> <{ v1 t2' }> / st'
(* numbers *)
| ST_SuccNatural : forall (n : nat) st,
<{ succ n }> / st --> tm_const (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st --> t1' / st' ->
<{ succ t1 }> / st --> <{ succ t1' }> / st'
| ST_PredNatural : forall (n : nat) st,
<{ pred n }> / st --> tm_const (n - 1) / st
| ST_Pred : forall t1 t1' st st',
t1 / st --> t1' / st' ->
<{ pred t1 }> / st --> <{ pred t1' }> / st'
| ST_MultNaturals : forall (n1 n2 : nat) st,
<{ n1 * n2 }> / st --> tm_const (n1 * n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st --> t1' / st' ->
<{ t1 * t2 }> / st --> <{ t1' * t2 }> / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st --> t2' / st' ->
<{ v1 * t2 }> / st --> <{ v1 * t2' }> / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st --> t1' / st' ->
<{ if0 t1 then t2 else t3 }> / st --> <{ if0 t1' then t2 else t3 }> / st'
| ST_If0_Zero : forall t2 t3 st,
<{ if0 0 then t2 else t3 }> / st --> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
<{ if0 {S n} then t2 else t3 }> / st --> t3 / st
(* references *)
| ST_RefValue : forall v st,
value v ->
<{ ref v }> / st --> <{ loc { length st } }> / (st ++ v::nil)
| ST_Ref : forall t1 t1' st st',
t1 / st --> t1' / st' ->
<{ ref t1 }> / st --> <{ ref t1' }> / st'
| ST_DerefLoc : forall st l,
l < length st ->
<{ !(loc l) }> / st --> <{ { store_lookup l st } }> / st
| ST_Deref : forall t1 t1' st st',
t1 / st --> t1' / st' ->
<{ ! t1 }> / st --> <{ ! t1' }> / st'
| ST_Assign : forall v l st,
value v ->
l < length st ->
<{ (loc l) := v }> / st --> <{ unit }> / replace l v st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st --> t1' / st' ->
<{ t1 := t2 }> / st --> <{ t1' := t2 }> / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st --> t2' / st' ->
<{ v1 := t2 }> / st --> <{ v1 := t2' }> / st'
where "t '/' st '-->' t' '/' st'" := (step (t,st) (t',st')).
(** One slightly ugly point should be noted here: In the [ST_RefValue]
rule, we extend the state by writing [st ++ v::nil] rather than
the more natural [st ++ [v]]. The reason for this is that the
notation we've defined for substitution uses square brackets,
which clash with the standard library's notation for lists. *)
Hint Constructors step : core.
Definition multistep := (multi step).
Notation "t '/' st '-->*' t' '/' st'" :=
(multistep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(* ################################################################# *)
(** * Typing *)
(** The contexts assigning types to free variables are exactly the
same as for the STLC: partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ================================================================= *)
(** ** Store typings *)
(** Having extended our syntax and reduction rules to accommodate
references, our last job is to write down typing rules for the new
constructs (and, of course, to check that these rules are sound!).
Naturalurally, the key question is, "What is the type of a location?"
First of all, notice that this question doesn't arise when
typechecking terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of reduction; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of a reduction
sequence, e.g., trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we reduce a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we reduce the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we reduce the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. (The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.)
However, this rule will not quite do. For one thing, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear. Worse yet, the
proposed typing rule for locations may not allow us to derive
anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
[\x:Natural. (!(loc 1)) x, \x:Natural. (!(loc 0)) x]
*)
(** **** Exercise: 2 stars, standard (cyclic_store)
Can you find a term whose reduction will create this particular
cyclic store? *)
(*
let a = ref (\x:Nat, unit)
in let b = ref (\x:Nat, (!a) x)
in a := ref (\x:Nat (!b) x)
*)
(* Do not modify the following line: *)
Definition manual_grade_for_cyclic_store : option (nat*string) := None.
(** [] *)
(** These problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ -- a finite function
mapping locations to types.
As with the other type systems we've seen, this conservative typing
restriction on allowed updates means that we will rule out as
ill-typed some programs that could reduce perfectly well without
getting stuck.
Just as we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
values that we expect to be stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST <{ Unit }>.
(** Suppose we are given a store typing [ST] describing the store
[st] in which some term [t] will be reduced. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we can immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location, we can compute the
type of [l] just by looking it up in [ST]. Typing is again a
four-place relation, but it is parameterized on a store _typing_
rather than a concrete store. The rest of the typing rules are
analogously augmented with store typings. *)
(* ================================================================= *)
(** ** The Typing Relation *)
(** We can now formalize the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T1
------------------------- (T_Deref)
Gamma; ST |- !t1 : T1
Gamma; ST |- t1 : Ref T2
Gamma; ST |- t2 : T2
---------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40, t custom stlc, T custom stlc at level 0).
Inductive has_type (ST : store_ty) : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T1,
Gamma x = Some T1 ->
Gamma ; ST |- x \in T1
| T_Abs : forall Gamma x T1 T2 t1,
update Gamma x T2 ; ST |- t1 \in T1 ->
Gamma ; ST |- \x:T2, t1 \in (T2 -> T1)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma ; ST |- t1 \in (T2 -> T1) ->
Gamma ; ST |- t2 \in T2 ->
Gamma ; ST |- t1 t2 \in T1
| T_Natural : forall Gamma (n : nat),
Gamma ; ST |- n \in Natural
| T_Succ : forall Gamma t1,
Gamma ; ST |- t1 \in Natural ->
Gamma ; ST |- succ t1 \in Natural
| T_Pred : forall Gamma t1,
Gamma ; ST |- t1 \in Natural ->
Gamma ; ST |- pred t1 \in Natural
| T_Mult : forall Gamma t1 t2,
Gamma ; ST |- t1 \in Natural ->
Gamma ; ST |- t2 \in Natural ->
Gamma ; ST |- t1 * t2 \in Natural
| T_If0 : forall Gamma t1 t2 t3 T0,
Gamma ; ST |- t1 \in Natural ->
Gamma ; ST |- t2 \in T0 ->
Gamma ; ST |- t3 \in T0 ->
Gamma ; ST |- if0 t1 then t2 else t3 \in T0
| T_Unit : forall Gamma,
Gamma ; ST |- unit \in Unit
| T_Loc : forall Gamma l,
l < length ST ->
Gamma ; ST |- (loc l) \in (Ref {store_Tlookup l ST })
| T_Ref : forall Gamma t1 T1,
Gamma ; ST |- t1 \in T1 ->
Gamma ; ST |- (ref t1) \in (Ref T1)
| T_Deref : forall Gamma t1 T1,
Gamma ; ST |- t1 \in (Ref T1) ->
Gamma ; ST |- (! t1) \in T1
| T_Assign : forall Gamma t1 t2 T2,
Gamma ; ST |- t1 \in (Ref T2) ->
Gamma ; ST |- t2 \in T2 ->
Gamma ; ST |- (t1 := t2) \in Unit
where "Gamma ';' ST '|-' t '\in' T" := (has_type ST Gamma t T).
Hint Constructors has_type : core.
(** Of course, these typing rules will accurately predict the results
of reduction only if the concrete store used during reduction
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the basic STLC: the substitution lemma
promises that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will reduce to a final result of type [T] if it yields
any result at all. We will see below how to formalize an
analogous intuition for stores and store typings.
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Concrete locations arise only in
terms that are the intermediate results of reduction; they are
not in the language that programmers write. Thus, we can simply
typecheck the programmer's terms with respect to the _empty_ store
typing. As reduction proceeds and new locations are created, we
will always be able to see how to extend the store typing by
looking at the type of the initial values being placed in newly
allocated cells; this intuition is formalized in the statement of
the type preservation theorem below. *)
(* ################################################################# *)
(** * Properties *)
(** Our final task is to check that standard type safety
properties continue to hold for the STLC with references. The
progress theorem ("well-typed terms are not stuck") can be stated
and proved almost as for the STLC; we just need to add a few
straightforward cases to the proof to deal with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ================================================================= *)
(** ** Well-Typed Stores *)
(** Since we have extended both the reduction relation (with
initial and final stores) and the typing relation (with a store
typing), we need to change the statement of preservation to
include these parameters. But clearly we cannot just add stores
and store typings without saying anything about how they are
related -- i.e., this is wrong: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty ; ST |- t \in T ->
t / st --> t' / st' ->
empty ; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then reduce with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- { store_lookup l st } \in {store_Tlookup l ST }).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation. This allows us to type circular
stores like the one we saw above. *)
(** **** Exercise: 2 stars, standard (store_not_unique)
Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
Example store_not_unique :
store_well_typed (<{Natural}> :: nil) (<{!(loc 0)}> :: nil) /\
store_well_typed (<{Unit}> :: nil) (<{!(loc 0)}> :: nil).
Proof.
split.
- constructor; auto.
unfold store_lookup. unfold store_Tlookup.
intros. simpl in H. inversion H.
+ simpl. constructor. constructor. simpl. apply le_n.
+ subst. inversion H1.
- constructor; auto.
unfold store_lookup. unfold store_Tlookup.
intros. simpl in H. inversion H.
+ simpl. constructor. constructor. simpl. apply le_n.
+ subst. inversion H1.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_store_not_unique : option (nat*string) := None.
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
empty ; ST |- t \in T ->
t / st --> t' / st' ->
store_well_typed ST st ->
empty ; ST |- t' \in T.
Abort.
(** This statement is fine for all of the reduction rules except
the allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st'] includes
a binding for a fresh location [l], then [l] cannot be in the
domain of [ST], and it will not be the case that [t'] (which
definitely mentions [l]) is typable under [ST]. *)
(* ================================================================= *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during reduction,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends : core.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST.
generalize dependent l.
induction ST as [|a ST2]; intros l ST' Hlen HST'.
- (* nil *) inversion Hlen.
- (* cons *) unfold store_Tlookup in *.
destruct ST'.
+ (* ST' = nil *) inversion HST'.
+ (* ST' = a' :: ST'2 *)
inversion HST'; subst.
destruct l as [|l'].
* (* l = 0 *) auto.
* (* l = S l' *) simpl. apply IHST2...
simpl in Hlen; lia.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
- inversion Hlen.
- simpl in *.
destruct l; try lia.
apply lt_n_S. apply IHextends. lia.
Qed.
(** Finally, [ST ++ T] extends [ST], and [extends] is reflexive. *)
Lemma extends_app : forall ST T,
extends (ST ++ T) ST.
Proof.
induction ST; intros T.
auto.
simpl. auto.
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ================================================================= *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty ; ST |- t \in T ->
store_well_typed ST st ->
t / st --> t' / st' ->
exists ST',
extends ST' ST /\
empty ; ST' |- t' \in T /\
store_well_typed ST' st'.
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else exactly [ST ++ T1::nil], where
[T1] is the type of the value [v1] in the extended store [st ++
v1::nil], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of reduction steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ================================================================= *)
(** ** Substitution Lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Lemma weakening : forall Gamma Gamma' ST t T,
inclusion Gamma Gamma' ->
Gamma ; ST |- t \in T ->
Gamma' ; ST |- t \in T.
Proof.
intros Gamma Gamma' ST t T H Ht.
generalize dependent Gamma'.
induction Ht; eauto using inclusion_update.
Qed.
Lemma weakening_empty : forall Gamma ST t T,
empty ; ST |- t \in T ->
Gamma ; ST |- t \in T.
Proof.
intros Gamma ST t T.
eapply weakening.
discriminate.
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x U t v T,
(update Gamma x U); ST |- t \in T ->
empty ; ST |- v \in U ->
Gamma ; ST |- [x:=v]t \in T.
Proof.
intros Gamma ST x U t v T Ht Hv.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; clear H; subst; simpl; eauto.
- (* var *)
rename s into y. destruct (eqb_stringP x y); subst.
+ (* x=y *)
rewrite update_eq in H2.
injection H2 as H2; subst.
apply weakening_empty. assumption.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2; auto.
- (* abs *)
rename s into y, t into T.
destruct (eqb_stringP x y); subst; apply T_Abs.
+ (* x=y *)
rewrite update_shadow in H5. assumption.
+ (* x<>y *)
apply IHt.
rewrite update_permute; auto.
Qed.
(* ================================================================= *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty ; ST |- t \in {store_Tlookup l ST} ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (l' =? l) eqn: Heqll'.
- (* l' = l *)
apply Nat.eqb_eq in Heqll'; subst.
rewrite lookup_replace_eq...
- (* l' <> l *)
apply Nat.eqb_neq in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ================================================================= *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma ; ST |- t \in T ->
Gamma ; ST' |- t \in T.
Proof with eauto.
intros. induction H0; eauto.
- (* T_Loc *)
rewrite <- (extends_lookup _ _ ST')...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_app : forall ST st t1 T1,
store_well_typed ST st ->
empty ; ST |- t1 \in T1 ->
store_well_typed (ST ++ T1::nil) (st ++ t1::nil).
Proof with auto.
intros.
unfold store_well_typed in *.
destruct H as [Hlen Hmatch].
rewrite app_length, plus_comm. simpl.
rewrite app_length, plus_comm. simpl.
split...
- (* types match. *)
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; destruct Hl as [Hlt | Heq].
+ (* l < length st *)
apply lt_S_n in Hlt.
rewrite !app_nth1...
* apply store_weakening with ST. apply extends_app.
apply Hmatch...
* rewrite Hlen...
+ (* l = length st *)
injection Heq as Heq; subst.
rewrite app_nth2; try lia.
rewrite <- Hlen.
rewrite minus_diag. simpl.
apply store_weakening with ST...
{ apply extends_app. }
rewrite app_nth2; [|lia].
rewrite minus_diag. simpl. assumption.
Qed.
(* ================================================================= *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
(** Begin with one technical lemma: *)
Lemma nth_eq_last : forall A (l:list A) x d,
nth (length l) (l ++ x::nil) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** And here, at last, is the preservation theorem and proof: *)
Theorem preservation : forall ST t t' T st st',
empty ; ST |- t \in T ->
store_well_typed ST st ->
t / st --> t' / st' ->
exists ST',
extends ST' ST /\
empty ; ST' |- t' \in T /\
store_well_typed ST' st'.
Proof with eauto using store_weakening, extends_refl.
remember empty as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
induction Ht; intros t' HST Hstep;
subst; try solve_by_invert; inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
(* T_App *)
- (* ST_AppAbs *) exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
- (* ST_App1 *)
eapply IHHt1 in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_App2 *)
eapply IHHt2 in H5...
destruct H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Succ *)
+ (* ST_Succ *)
eapply IHHt in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Pred *)
+ (* ST_Pred *)
eapply IHHt in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Mult *)
- (* ST_Mult1 *)
eapply IHHt1 in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Mult2 *)
eapply IHHt2 in H5...
destruct H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_If0 *)
+ (* ST_If0_1 *)
eapply IHHt1 in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'. split...
(* T_Ref *)
- (* ST_RefValue *)
exists (ST ++ T1::nil).
inversion HST; subst.
split.
{ apply extends_app. }
split.
{ replace <{ Ref T1 }>
with <{ Ref {store_Tlookup (length st) (ST ++ T1::nil)} }>.
{ apply T_Loc.
rewrite <- H. rewrite app_length, plus_comm. simpl. lia. }
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_last.
reflexivity. }
apply store_well_typed_app; assumption.
- (* ST_Ref *)
eapply IHHt in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Deref *)
- (* ST_DerefLoc *)
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T1 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
- (* ST_Deref *)
eapply IHHt in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Assign *)
- (* ST_Assign *)
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
- (* ST_Assign1 *)
eapply IHHt1 in H0...
destruct H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Assign2 *)
eapply IHHt2 in H5...
destruct H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars, standard (preservation_informal)
Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
(* SKIPPED *)
*)
(* Do not modify the following line: *)
Definition manual_grade_for_preservation_informal : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Progress *)
(** As we've said, progress for this system is pretty easy to prove;
the proof is very similar to the proof of progress for the STLC,
with a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty ; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t' st', t / st --> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember empty as Gamma.
induction Ht; subst; try solve_by_invert...
- (* T_App *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve_by_invert.
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 steps *)
destruct Ht2p as [t2' [st' Hstep]].
exists <{ (\ x0 : T0, t0) t2' }>, st'...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ t1' t2 }>, st'...
- (* T_Succ *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [ inversion Ht ].
* (* t1 is a const *)
exists <{ {S n} }>, st...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ succ t1' }>, st'...
- (* T_Pred *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht ].
* (* t1 is a const *)
exists <{ {n - 1} }>, st...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ pred t1' }>, st'...
- (* T_Mult *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 is a value *)
inversion Ht2p; subst; try solve [inversion Ht2].
exists <{ {n * n0} }>, st...
* (* t2 steps *)
destruct Ht2p as [t2' [st' Hstep]].
exists <{ n * t2' }>, st'...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ t1' * t2 }>, st'...
- (* T_If0 *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
* (* n = 0 *) exists t2, st...
* (* n = S n' *) exists t3, st...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ if0 t1' then t2 else t3 }>, st'...
- (* T_Ref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ref t1'}>, st'...
- (* T_Deref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve_by_invert.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ ! t1' }>, st'...
- (* T_Assign *)
right. destruct IHHt1 as [Ht1p|Ht1p]...
+ (* t1 is a value *)
destruct IHHt2 as [Ht2p|Ht2p]...
* (* t2 is a value *)
inversion Ht1p; subst; try solve_by_invert.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H4...
* (* t2 steps *)
destruct Ht2p as [t2' [st' Hstep]].
exists <{ t1 := t2' }>, st'...
+ (* t1 steps *)
destruct Ht1p as [t1' [st' Hstep]].
exists <{ t1' := t2 }>, st'...
Qed.
(* ################################################################# *)
(** * References and Nontermination *)
(** An important fact about the STLC (proved in chapter [Norm]) is
that it is is _normalizing_ -- that is, every well-typed term can
be reduced to a value in a finite number of steps.
What about STLC + references? Surprisingly, adding references
causes us to lose the normalization property: there exist
well-typed terms in the STLC + references which can continue to
reduce forever, without ever reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function [\x:Unit.(!r) unit] -- that is, the function which ignores
its argument and calls the function stored in [r] on the argument
[unit]; but of course, that function is itself! To start the
divergent loop, we execute the function stored in the cell by
evaluating [(!r) unit].
Here is the divergent term in Coq: *)
Module ExampleVariables.
Open Scope string_scope.
Definition x := "x".
Definition y := "y".
Definition r := "r".
Definition s := "s".
End ExampleVariables.
Module RefsAndNontermination.
Import ExampleVariables.
Definition loop_fun :=
<{ \x : Unit, (!r) unit }>.
Definition loop :=
<{ (\r : Ref (Unit -> Unit), (( r := loop_fun ); ( (! r) unit ) )) (ref (\x : Unit, unit)) }> .
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
rewrite update_neq; [|intros; discriminate].
rewrite update_eq. reflexivity. auto.
eapply T_Assign.
eapply T_Var. rewrite update_eq. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[-->+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [-->*]), except
that it is not reflexive: [t -->+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '-->+' t2 '/' st'" :=
(multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store
[[r:=(loc 0)]loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
(** Next, we use [reduce] to show that [loop] steps to
[!(loc 0) unit], starting from the empty store. *)
Lemma loop_steps_to_loop_fun :
loop / nil -->*
<{ (! (loc 0)) unit }> / cons <{ [r := loc 0] loop_fun }> nil.
Proof.
unfold loop.
reduce.
Qed.
(** Finally, we show that the latter expression reduces in
two steps to itself! *)
Lemma loop_fun_step_self :
<{ (! (loc 0)) unit }> / cons <{ [r := loc 0] loop_fun }> nil -->+
<{ (! (loc 0)) unit }> / cons <{ [r := loc 0] loop_fun }> nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars, standard (factorial_ref)
Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just uncomment the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition factorial_fun :=
<{\y : Natural, if0 y then 1 else y * ((!r) (pred y))}>.
Definition factorial : tm :=
<{(\y : Natural,
(\r : Ref (Natural -> Natural),
((r := factorial_fun); (!r) y))
(ref (\z:Natural, z)))
}>.
Lemma factorial_type : empty; nil |- factorial \in (Natural -> Natural).
Proof with eauto.
unfold factorial.
repeat econstructor.
Qed.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
Lemma factorial_4 : exists st,
<{ factorial 4 }> / nil -->* tm_const 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, standard, optional (garabage_collector)
Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(*
I completed this problem in a separate file because the namespace in this file
is contaminated with existing notations that I failed to fix.
See my solution in ReferencesWithGC.v.
*)
End RefsAndNontermination.
End STLCRef.
(* 2020-09-09 21:08 *)
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (20),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_PP_V
|
// This file has NOT been automatically generated by goFB
// Written by Hammond Pearce and available at github.com/kiwih/goFB
// This file represents the Top of the IEC61499 network
module top_4
(
input wire clk,
//input events
input wire InjectorArmFinishMovement_eI_1,
input wire InjectorArmFinishMovement_eI_2,
input wire InjectorArmFinishMovement_eI_3,
input wire InjectorArmFinishMovement_eI_4,
input wire EmergencyStopChanged_eI_1,
input wire EmergencyStopChanged_eI_2,
input wire EmergencyStopChanged_eI_3,
input wire EmergencyStopChanged_eI_4,
input wire CanisterPressureChanged_eI_1,
input wire CanisterPressureChanged_eI_2,
input wire CanisterPressureChanged_eI_3,
input wire CanisterPressureChanged_eI_4,
input wire FillContentsAvailableChanged_eI_1,
input wire FillContentsAvailableChanged_eI_2,
input wire FillContentsAvailableChanged_eI_3,
input wire FillContentsAvailableChanged_eI_4,
input wire LasersChanged_eI_1,
input wire LasersChanged_eI_2,
input wire LasersChanged_eI_3,
input wire LasersChanged_eI_4,
input wire DoorOverride_eI_1,
input wire DoorOverride_eI_2,
input wire DoorOverride_eI_3,
input wire DoorOverride_eI_4,
input wire VacuumTimerElapsed_eI_1,
input wire VacuumTimerElapsed_eI_2,
input wire VacuumTimerElapsed_eI_3,
input wire VacuumTimerElapsed_eI_4,
//output events
output wire DoorReleaseCanister_eO_1,
output wire DoorReleaseCanister_eO_2,
output wire DoorReleaseCanister_eO_3,
output wire DoorReleaseCanister_eO_4,
output wire ConveyorChanged_eO_1,
output wire ConveyorChanged_eO_2,
output wire ConveyorChanged_eO_3,
output wire ConveyorChanged_eO_4,
output wire InjectorPositionChanged_eO_1,
output wire InjectorPositionChanged_eO_2,
output wire InjectorPositionChanged_eO_3,
output wire InjectorPositionChanged_eO_4,
output wire InjectorControlsChanged_eO_1,
output wire InjectorControlsChanged_eO_2,
output wire InjectorControlsChanged_eO_3,
output wire InjectorControlsChanged_eO_4,
output wire FillContentsChanged_eO_1,
output wire FillContentsChanged_eO_2,
output wire FillContentsChanged_eO_3,
output wire FillContentsChanged_eO_4,
output wire StartVacuumTimer_eO_1,
output wire StartVacuumTimer_eO_2,
output wire StartVacuumTimer_eO_3,
output wire StartVacuumTimer_eO_4,
output wire GoRejectArm_eO_1,
output wire GoRejectArm_eO_2,
output wire GoRejectArm_eO_3,
output wire GoRejectArm_eO_4,
output wire CanisterCountChanged_eO_1,
output wire CanisterCountChanged_eO_2,
output wire CanisterCountChanged_eO_3,
output wire CanisterCountChanged_eO_4,
output wire InjectDone_eO_1,
output wire InjectDone_eO_2,
output wire InjectDone_eO_3,
output wire InjectDone_eO_4,
//input variables
input wire EmergencyStop_I_1,
input wire EmergencyStop_I_2,
input wire EmergencyStop_I_3,
input wire EmergencyStop_I_4,
input wire [7:0] CanisterPressure_I_1,
input wire [7:0] CanisterPressure_I_2,
input wire [7:0] CanisterPressure_I_3,
input wire [7:0] CanisterPressure_I_4,
input wire [7:0] FillContentsAvailable_I_1,
input wire [7:0] FillContentsAvailable_I_2,
input wire [7:0] FillContentsAvailable_I_3,
input wire [7:0] FillContentsAvailable_I_4,
input wire DoorSiteLaser_I_1,
input wire DoorSiteLaser_I_2,
input wire DoorSiteLaser_I_3,
input wire DoorSiteLaser_I_4,
input wire InjectSiteLaser_I_1,
input wire InjectSiteLaser_I_2,
input wire InjectSiteLaser_I_3,
input wire InjectSiteLaser_I_4,
input wire RejectSiteLaser_I_1,
input wire RejectSiteLaser_I_2,
input wire RejectSiteLaser_I_3,
input wire RejectSiteLaser_I_4,
input wire RejectBinLaser_I_1,
input wire RejectBinLaser_I_2,
input wire RejectBinLaser_I_3,
input wire RejectBinLaser_I_4,
input wire AcceptBinLaser_I_1,
input wire AcceptBinLaser_I_2,
input wire AcceptBinLaser_I_3,
input wire AcceptBinLaser_I_4,
//output variables
output wire [7:0] ConveyorSpeed_O_1,
output wire [7:0] ConveyorSpeed_O_2,
output wire [7:0] ConveyorSpeed_O_3,
output wire [7:0] ConveyorSpeed_O_4,
output wire [7:0] InjectorPosition_O_1,
output wire [7:0] InjectorPosition_O_2,
output wire [7:0] InjectorPosition_O_3,
output wire [7:0] InjectorPosition_O_4,
output wire InjectorContentsValveOpen_O_1,
output wire InjectorContentsValveOpen_O_2,
output wire InjectorContentsValveOpen_O_3,
output wire InjectorContentsValveOpen_O_4,
output wire InjectorVacuumRun_O_1,
output wire InjectorVacuumRun_O_2,
output wire InjectorVacuumRun_O_3,
output wire InjectorVacuumRun_O_4,
output wire InjectorPressurePumpRun_O_1,
output wire InjectorPressurePumpRun_O_2,
output wire InjectorPressurePumpRun_O_3,
output wire InjectorPressurePumpRun_O_4,
output wire FillContents_O_1,
output wire FillContents_O_2,
output wire FillContents_O_3,
output wire FillContents_O_4,
output wire [7:0] CanisterCount_O_1,
output wire [7:0] CanisterCount_O_2,
output wire [7:0] CanisterCount_O_3,
output wire [7:0] CanisterCount_O_4,
input reset
);
// I/O
FB_FlexPRET t1(
.clk(clk),
//input events
.InjectorArmFinishMovement_eI(InjectorArmFinishMovement_eI_1),
.EmergencyStopChanged_eI(EmergencyStopChanged_eI_1),
.CanisterPressureChanged_eI(CanisterPressureChanged_eI_1),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_eI_1),
.LasersChanged_eI(LasersChanged_eI_1),
.DoorOverride_eI(DoorOverride_eI_1),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_eI_1),
//output events
.DoorReleaseCanister_eO(DoorReleaseCanister_eO_1),
.ConveyorChanged_eO(ConveyorChanged_eO_1),
.InjectorPositionChanged_eO(InjectorPositionChanged_eO_1),
.InjectorControlsChanged_eO(InjectorControlsChanged_eO_1),
.FillContentsChanged_eO(FillContentsChanged_eO_1),
.StartVacuumTimer_eO(StartVacuumTimer_eO_1),
.GoRejectArm_eO(GoRejectArm_eO_1),
.CanisterCountChanged_eO(CanisterCountChanged_eO_1),
.InjectDone_eO(InjectDone_eO_1),
//input variables
.EmergencyStop_I(EmergencyStop_I_1),
.CanisterPressure_I(CanisterPressure_I_1),
.FillContentsAvailable_I(FillContentsAvailable_I_1),
.DoorSiteLaser_I(DoorSiteLaser_I_1),
.InjectSiteLaser_I(InjectSiteLaser_I_1),
.RejectSiteLaser_I(RejectSiteLaser_I_1),
.RejectBinLaser_I(RejectBinLaser_I_1),
.AcceptBinLaser_I(AcceptBinLaser_I_1),
//output variables
.ConveyorSpeed_O(ConveyorSpeed_O_1),
.InjectorPosition_O(InjectorPosition_O_1),
.InjectorContentsValveOpen_O(InjectorContentsValveOpen_O_1),
.InjectorVacuumRun_O(InjectorVacuumRun_O_1),
.InjectorPressurePumpRun_O(InjectorPressurePumpRun_O_1),
.FillContents_O(FillContents_O_1),
.CanisterCount_O(CanisterCount_O_1),
.reset(reset)
);
// I/O
FB_FlexPRET t2(
.clk(clk),
//input events
.InjectorArmFinishMovement_eI(InjectorArmFinishMovement_eI_2),
.EmergencyStopChanged_eI(EmergencyStopChanged_eI_2),
.CanisterPressureChanged_eI(CanisterPressureChanged_eI_2),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_eI_2),
.LasersChanged_eI(LasersChanged_eI_2),
.DoorOverride_eI(DoorOverride_eI_2),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_eI_2),
//output events
.DoorReleaseCanister_eO(DoorReleaseCanister_eO_2),
.ConveyorChanged_eO(ConveyorChanged_eO_2),
.InjectorPositionChanged_eO(InjectorPositionChanged_eO_2),
.InjectorControlsChanged_eO(InjectorControlsChanged_eO_2),
.FillContentsChanged_eO(FillContentsChanged_eO_2),
.StartVacuumTimer_eO(StartVacuumTimer_eO_2),
.GoRejectArm_eO(GoRejectArm_eO_2),
.CanisterCountChanged_eO(CanisterCountChanged_eO_2),
.InjectDone_eO(InjectDone_eO_2),
//input variables
.EmergencyStop_I(EmergencyStop_I_2),
.CanisterPressure_I(CanisterPressure_I_2),
.FillContentsAvailable_I(FillContentsAvailable_I_2),
.DoorSiteLaser_I(DoorSiteLaser_I_2),
.InjectSiteLaser_I(InjectSiteLaser_I_2),
.RejectSiteLaser_I(RejectSiteLaser_I_2),
.RejectBinLaser_I(RejectBinLaser_I_2),
.AcceptBinLaser_I(AcceptBinLaser_I_2),
//output variables
.ConveyorSpeed_O(ConveyorSpeed_O_2),
.InjectorPosition_O(InjectorPosition_O_2),
.InjectorContentsValveOpen_O(InjectorContentsValveOpen_O_2),
.InjectorVacuumRun_O(InjectorVacuumRun_O_2),
.InjectorPressurePumpRun_O(InjectorPressurePumpRun_O_2),
.FillContents_O(FillContents_O_2),
.CanisterCount_O(CanisterCount_O_2),
.reset(reset)
);
// I/O
FB_FlexPRET t3(
.clk(clk),
//input events
.InjectorArmFinishMovement_eI(InjectorArmFinishMovement_eI_3),
.EmergencyStopChanged_eI(EmergencyStopChanged_eI_3),
.CanisterPressureChanged_eI(CanisterPressureChanged_eI_3),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_eI_3),
.LasersChanged_eI(LasersChanged_eI_3),
.DoorOverride_eI(DoorOverride_eI_3),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_eI_3),
//output events
.DoorReleaseCanister_eO(DoorReleaseCanister_eO_3),
.ConveyorChanged_eO(ConveyorChanged_eO_3),
.InjectorPositionChanged_eO(InjectorPositionChanged_eO_3),
.InjectorControlsChanged_eO(InjectorControlsChanged_eO_3),
.FillContentsChanged_eO(FillContentsChanged_eO_3),
.StartVacuumTimer_eO(StartVacuumTimer_eO_3),
.GoRejectArm_eO(GoRejectArm_eO_3),
.CanisterCountChanged_eO(CanisterCountChanged_eO_3),
.InjectDone_eO(InjectDone_eO_3),
//input variables
.EmergencyStop_I(EmergencyStop_I_3),
.CanisterPressure_I(CanisterPressure_I_3),
.FillContentsAvailable_I(FillContentsAvailable_I_3),
.DoorSiteLaser_I(DoorSiteLaser_I_3),
.InjectSiteLaser_I(InjectSiteLaser_I_3),
.RejectSiteLaser_I(RejectSiteLaser_I_3),
.RejectBinLaser_I(RejectBinLaser_I_3),
.AcceptBinLaser_I(AcceptBinLaser_I_3),
//output variables
.ConveyorSpeed_O(ConveyorSpeed_O_3),
.InjectorPosition_O(InjectorPosition_O_3),
.InjectorContentsValveOpen_O(InjectorContentsValveOpen_O_3),
.InjectorVacuumRun_O(InjectorVacuumRun_O_3),
.InjectorPressurePumpRun_O(InjectorPressurePumpRun_O_3),
.FillContents_O(FillContents_O_3),
.CanisterCount_O(CanisterCount_O_3),
.reset(reset)
);
// I/O
FB_FlexPRET t4(
.clk(clk),
//input events
.InjectorArmFinishMovement_eI(InjectorArmFinishMovement_eI_4),
.EmergencyStopChanged_eI(EmergencyStopChanged_eI_4),
.CanisterPressureChanged_eI(CanisterPressureChanged_eI_4),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_eI_4),
.LasersChanged_eI(LasersChanged_eI_4),
.DoorOverride_eI(DoorOverride_eI_4),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_eI_4),
//output events
.DoorReleaseCanister_eO(DoorReleaseCanister_eO_4),
.ConveyorChanged_eO(ConveyorChanged_eO_4),
.InjectorPositionChanged_eO(InjectorPositionChanged_eO_4),
.InjectorControlsChanged_eO(InjectorControlsChanged_eO_4),
.FillContentsChanged_eO(FillContentsChanged_eO_4),
.StartVacuumTimer_eO(StartVacuumTimer_eO_4),
.GoRejectArm_eO(GoRejectArm_eO_4),
.CanisterCountChanged_eO(CanisterCountChanged_eO_4),
.InjectDone_eO(InjectDone_eO_4),
//input variables
.EmergencyStop_I(EmergencyStop_I_4),
.CanisterPressure_I(CanisterPressure_I_4),
.FillContentsAvailable_I(FillContentsAvailable_I_4),
.DoorSiteLaser_I(DoorSiteLaser_I_4),
.InjectSiteLaser_I(InjectSiteLaser_I_4),
.RejectSiteLaser_I(RejectSiteLaser_I_4),
.RejectBinLaser_I(RejectBinLaser_I_4),
.AcceptBinLaser_I(AcceptBinLaser_I_4),
//output variables
.ConveyorSpeed_O(ConveyorSpeed_O_4),
.InjectorPosition_O(InjectorPosition_O_4),
.InjectorContentsValveOpen_O(InjectorContentsValveOpen_O_4),
.InjectorVacuumRun_O(InjectorVacuumRun_O_4),
.InjectorPressurePumpRun_O(InjectorPressurePumpRun_O_4),
.FillContents_O(FillContents_O_4),
.CanisterCount_O(CanisterCount_O_4),
.reset(reset)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Boston University
// Engineer: Zafar M. Takhirov
//
// Create Date: 12:59:40 04/12/2011
// Design Name: EC311 Support Files
// Module Name: vga_display
// Project Name: Lab5 / Lab6 / Project
// Target Devices: xc6slx16-3csg324
// Tool versions: XILINX ISE 13.3
// Description:
//
// Dependencies: vga_controller_640_60
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_display(St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar,
HS, VS, R, G, B, An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp,
Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7,
rst, ClkPort, btnU, btnD);
input rst; // global reset
input ClkPort, btnU, btnD;
input Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7;
// color outputs to show on display (current pixel)
output [2:0] R, G;
output [1:0] B;
output St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar;
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
reg [2:0] R, G;
reg [1:0] B;
wire [2:0] sprite_R, sprite_G;
wire [1:0] sprite_B;
assign {St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar} = {5'b00000};//{5'b11111};
assign {An0, An1, An2, An3} = {4'b0000};
assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {8'hFF};
wire [7:0] switches;
assign switches = {Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7};
// Synchronization signals
output HS;
output VS;
// controls:
wire [10:0] hcount, vcount; // coordinates for the current pixel
wire blank; // signal to indicate the current coordinate is blank
wire figure; // the figure you want to display
// memory interface:
reg [7:0] dout;
wire [7:0] ben_dout;
wire [7:0] dec_dout;
reg [14:0] ben_read_addr;
wire [14:0] decr_read_addr;
wire [14:0] sprite_read_addr;
wire inside_image;
// wire [7:0] pezh_dout;
/////////////////////////////////////////////////////
// Begin clock division
parameter N = 2; // VGA clock divider
parameter dec_N = 12; //16; // decryptor clock divider
reg clk_25Mhz;
reg clk_decrypter;
reg [dec_N-1:0] count;
initial count = 0;
always @ (posedge ClkPort) begin
count <= count + 1'b1;
clk_25Mhz <= count[N-1];
clk_decrypter <= count[dec_N-1];
end
assign MEM_READ_CLOCK = clk_25Mhz;
assign MEM_WRITE_CLOCK = clk_25Mhz;
reg [30:0] icount;
initial icount = 0;
reg decrypter_active;
initial decrypter_active = 0;
reg [14:0] write_addr;
wire [14:0] write_addr_dec;
reg [14:0] reset_addr;
wire dec_done;
always @ (posedge MEM_WRITE_CLOCK) begin
icount <= icount + 1;
if (!dec_done) begin
write_addr <= write_addr_dec;
dec_mem_din <= dec_din;
reset_addr <= 0;
if (icount[26]) begin
dout <= dec_dout;
ben_read_addr <= decr_read_addr;
decrypter_active <= 1'b1;
end else begin
dout <= ben_dout;
ben_read_addr <= sprite_read_addr;
decrypter_active <= 1'b0;
end
R <= sprite_R;
G <= sprite_G;
B <= sprite_B;
end else begin
// why the f is this - 4 who knows :'(
write_addr <= reset_addr - 4;
ben_read_addr <= reset_addr;
dec_mem_din <= ben_dout;
reset_addr <= reset_addr + 1;
R <= 3'd0;
G <= 3'd0;
B <= 2'd0;
end
end
// End clock division
/////////////////////////////////////////////////////
// Call driver
vga_controller_640_60 vc(
.rst(rst),
.pixel_clk(clk_25Mhz),
.HS(HS),
.VS(VS),
.hcounter(hcount),
.vcounter(vcount),
.blank(blank)
);
vga_bsprite sprites_mem(
.hc(hcount),
.vc(vcount),
.mem_value(dout),
.rom_addr(sprite_read_addr),
.R(sprite_R),
.G(sprite_G),
.B(sprite_B),
.blank(blank),
.inside_image(inside_image)
);
pezhman_mem /*ben_mem*/ ben (
.clka(clk_25Mhz), // input clka
.addra(ben_read_addr), // input [14 : 0] read_addr
.douta(ben_dout) // output [7 : 0] douta
);
wire write_en;
wire [7:0] dec_din;
reg [7:0] dec_mem_din;
assign write_en = 1'b1; //(~blank) & inside_image;
// this will take some thought
// we want to read some part of the image (some address) and show that
// switch between ^ and reading some other part of the image that the decryptor is now decrypting and write correspondingly
reg [63:0] button_key;
always @(posedge ClkPort) begin: KEY_GEN
integer i;
for (i = 0; i < 8; i = i + 1) begin
if (switches[i])
button_key[8 * i +: 8] = 8'hFF;
else
button_key[8 * i +: 8] = 8'h00;
end
end
decrypter dec(
.clk(clk_decrypter),
.reset(rst),
.encrypted_data(ben_dout),
.read_addr(decr_read_addr),
.write_addr(write_addr_dec),
.decrypted_data(dec_din),
.decrypter_active(decrypter_active),
.done(dec_done),
.key(button_key)
);
decryption_mem dec_mem (
.clka(MEM_WRITE_CLOCK),
.addra(write_addr),
.dina(dec_mem_din),
.wea(write_en),
.clkb(MEM_READ_CLOCK),
.addrb(sprite_read_addr),
.doutb(dec_dout),
.rstb(1'b0)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_PP_SYMBOL_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_to_stream (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
reading_first_pixel_in_frame,
reading_last_pixel_in_frame,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_arbiterlock,
master_read,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input reading_first_pixel_in_frame;
input reading_last_pixel_in_frame;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output master_arbiterlock;
output master_read;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [ 3: 0] pending_reads;
reg startofpacket;
// State Machine Registers
reg [ 1: 0] s_dma_to_stream;
reg [ 1: 0] ns_dma_to_stream;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
s_dma_to_stream <= STATE_0_IDLE;
else
s_dma_to_stream <= ns_dma_to_stream;
end
always @(*)
begin
case (s_dma_to_stream)
STATE_0_IDLE:
begin
if (reset)
ns_dma_to_stream = STATE_0_IDLE;
else if (fifo_almost_empty)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else
ns_dma_to_stream = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if (reading_last_pixel_in_frame)
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_dma_to_stream = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
startofpacket <= 1'b0;
else if ((s_dma_to_stream == STATE_0_IDLE) & (reading_first_pixel_in_frame))
startofpacket <= 1'b1;
else if (master_readdatavalid)
startofpacket <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
assign master_arbiterlock = !((s_dma_to_stream == STATE_2_READ_BUFFER) |
(s_dma_to_stream == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_dma_to_stream == STATE_2_READ_BUFFER);
assign inc_address = master_read & ~master_waitrequest;
assign reset_address = inc_address & reading_last_pixel_in_frame;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = startofpacket;
assign fifo_data_in[DW+2] = (s_dma_to_stream == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full),
// synopsys translate_off
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_1_V
`define SKY130_FD_SC_HS__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_1_V
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_controlFlagsIn (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 1: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] data_out;
wire [ 1: 0] out_port;
wire [ 1: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2011, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// *** PLEASE NOTE THIS IS NOT A COMPLETE DESIGN ***
//
// This file contains sections of Verilog code intended to be helpful reference when using
// a KCPSM6 (PicoBlaze) processor in a Spartan-6 or Virtex-6 design. Please refer to the
// documentation provided with PicoBlaze.
//
// Nick Sawyer and Ken Chapman - Xilinx - 4th March 2011
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Signals for connection of KCPSM6 and Program Memory.
//
// NOTE: In Verilog a 'reg' must be used when a signal is used in a process and a 'wire'
// must be used when using a simple assignment. This means that you may need to
// change the definition for the 'interrupt', 'kcpsm6_sleep' and 'kcpsm6_reset'
// depending on how you use them in your design. For example, if you don't use
// interrupt then you will probably tie it to '0' and this will require a 'wire'.
//
//
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
wire [7:0] port_id;
wire [7:0] out_port;
reg [7:0] in_port;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
reg interrupt; //See note above
wire interrupt_ack;
wire kcpsm6_sleep; //See note above
reg kcpsm6_reset; //See note above
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
wire cpu_reset;
wire rdl;
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
//
///////////////////////////////////////////////////////////////////////////////////////////
// Circuit Descriptions
///////////////////////////////////////////////////////////////////////////////////////////
//
//
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to Program Memory
/////////////////////////////////////////////////////////////////////////////////////////
//
// The KCPSM6 parameters can be defined as required but the default values are shown below
// and these would be adequate for most designs.
//
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// In many designs (especially your first) interrupt and sleep are not used.
// Tie these inputs Low until you need them.
//
assign kcpsm6_sleep = 1'b0;
assign interrupt = 1'b0;
//
// The default Program Memory recommended for development.
//
// The generics should be set to define the family, program size and enable the JTAG
// Loader. As described in the documentation the initial recommended values are.
// 'S6', '1' and '1' for a Spartan-6 design.
// 'V6', '2' and '1' for a Virtex-6 design.
// Note that all 12-bits of the address are connected regardless of the program size
// specified by the generic. Within the program memory only the appropriate address bits
// will be used (e.g. 10 bits for 1K memory). This means it that you only need to modify
// the generic when changing the size of your program.
//
// When JTAG Loader updates the contents of the program memory KCPSM6 should be reset
// so that the new program executes from address zero. The Reset During Load port 'rdl'
// is therefore connected to the reset input of KCPSM6.
//
<your_program> #(
.C_FAMILY ("V6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (1)) //Include JTAG Loader when set to '1'
program_rom ( //Name to match your PSM file
.rdl (kcpsm6_reset),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
<your_program> #(
.C_FAMILY ("V6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (1)) //Include JTAG Loader when set to 1'b1
program_rom ( //Name to match your PSM file
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset | rdl;
//
/////////////////////////////////////////////////////////////////////////////////////////
// Example of General Purose I/O Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// The following code corresponds with the circuit diagram shown on page 72 of the
// KCPSM6 Guide and includes additional advice and recommendations.
//
//
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// The inputs connect via a pipelined multiplexer. For optimum implementation, the input
// selection control of the multiplexer is limited to only those signals of 'port_id'
// that are necessary. In this case, only 2-bits are required to identify each of
// four input ports to be read by KCPSM6.
//
// Note that 'read_strobe' only needs to be used when whatever supplying information to
// KPPSM6 needs to know when that information has been read. For example, when reading
// a FIFO a read signal would need to be generated when that port is read such that the
// FIFO would know to present the next oldest information.
//
always @ (posedge clk)
begin
case (port_id[1:0])
// Read input_port_a at port address 00 hex
2'b00 : in_port <= input_port_a;
// Read input_port_b at port address 01 hex
2'b01 : in_port <= input_port_b;
// Read input_port_c at port address 02 hex
2'b10 : in_port <= input_port_c;
// Read input_port_d at port address 03 hex
2'b11 : in_port <= input_port_d;
// To ensure minimum logic implementation when defining a multiplexer always
// use don't care for any of the unused cases (although there are none in this
// example).
default : in_port <= 8'bXXXXXXXX ;
endcase
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// Output ports must capture the value presented on the 'out_port' based on the value of
// 'port_id' when 'write_strobe' is High.
//
// For an optimum implementation the allocation of output ports should be made in a way
// that means that the decoding of 'port_id' is minimised. Whilst there is nothing
// logically wrong with decoding all 8-bits of 'port_id' it does result in a function
// that can not fit into a single 6-input look up table (LUT6) and requires all signals
// to be routed which impacts size, performance and power consumption of your design.
// So unless you really have a lot of output ports it is best practice to use 'one-hot'
// allocation of addresses as used below or to limit the number of 'port_id' bits to
// be decoded to the number required to cover the ports.
//
// Code examples in which the port address is 04 hex.
//
// Best practice in which one-hot allocation only requires a single bit to be tested.
// Supports up to 8 output ports with each allocated a different bit of 'port_id'.
//
// if (port_id[2] == 1'b1) output_port_x <= out_port;
//
//
// Limited decode in which 5-bits of 'port_id' are used to identify up to 32 ports and
// the decode logic can still fit within a LUT6 (the 'write_strobe' requiring the 6th
// input to complete the decode).
//
// if (port_id[4:0] == 5'b00100) output_port_x <= out_port;
//
//
// The 'generic' code may be the easiest to write with the minimum of thought but will
// result in two LUT6 being used to implement each decoder. This will also impact
// performance and power. This is not generally a problem and hence it is reasonable to
// consider this as over attention to detail but good design practice will often bring
// rewards in the long term. When a large design struggles to fit into a given device
// and/or meet timing closure then it is often the result of many small details rather
// that one big cause. PicoBlaze is extremely efficient so it would be a shame to
// spoil that efficiency with unnecessarily large and slow peripheral logic.
//
// if port_id = X"04" then output_port_x <= out_port;
//
always @ (posedge clk)
begin
// 'write_strobe' is used to qualify all writes to general output ports.
if (write_strobe == 1'b1) begin
// Write to output_port_w at port address 01 hex
if (port_id[0] == 1'b1) begin
output_port_w <= out_port;
end
// Write to output_port_x at port address 02 hex
if (port_id[1] == 1'b1) begin
output_port_x <= out_port;
end
// Write to output_port_y at port address 04 hex
if (port_id[2] == 1'b1) begin
output_port_y <= out_port;
end
// Write to output_port_z at port address 08 hex
if (port_id[3] == 1'b1) begin
output_port_z <= out_port;
end
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
//
// Implementation of the Constant-Optimised Output Ports should follow the same basic
// concepts as General Output Ports but remember that only the lower 4-bits of 'port_id'
// are used and that 'k_write_strobe' is used as the qualifier.
//
always @ (posedge clk)
begin
// 'k_write_strobe' is used to qualify all writes to constant output ports.
if (k_write_strobe == 1'b1) begin
// Write to output_port_k at port address 01 hex
if (port_id[0] == 1'b1) begin
output_port_k <= out_port;
end
// Write to output_port_c at port address 02 hex
if (port_id[1] == 1'b1) begin
output_port_c <= out_port;
end
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// Recommended 'closed loop' interrupt interface (when required).
/////////////////////////////////////////////////////////////////////////////////////////
//
// Interrupt becomes active when 'int_request' is observed and then remains active until
// acknowledged by KCPSM6. Please see description and waveforms in documentation.
//
always @ (posedge clk)
begin
if (interrupt_ack == 1'b1) begin
interrupt <= 1'b0;
end
else if (int_request == 1'b1) begin
interrupt <= 1'b1;
end
else begin
interrupt <= interrupt;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE kcpsm6_design_template.v
//
///////////////////////////////////////////////////////////////////////////////////////////
|
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: lshift.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lshift (
data,
distance,
overflow,
result,
underflow);
input wire [31:0] data;
input wire [4:0] distance;
output wire overflow;
output wire [31:0] result;
output wire underflow;
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (1'h0),
.distance (distance),
.overflow (overflow),
.result (result),
.underflow (underflow)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "LOGICAL",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 32,
LPM_CLSHIFT_component.lpm_widthdist = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "32"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "5"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "5"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: distance 0 0 5 0 INPUT NODEFVAL "distance[4..0]"
// Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL "overflow"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: USED_PORT: underflow 0 0 0 0 OUTPUT NODEFVAL "underflow"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @direction 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 5 0 distance 0 0 5 0
// Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: underflow 0 0 0 0 @underflow 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lshift_bb.v TRUE
|
`include "gcd2.generated.vh"
`default_nettype none
module Gcd2 (input wire CLK, input wire nRST,
input wire request$say__ENA,
input wire [31:0]request$say$va,
input wire [31:0]request$say$vb,
output wire request$say__RDY,
output wire indication$gcd__ENA,
output wire [31:0]indication$gcd$v,
input wire indication$gcd__RDY);
reg [31:0]a;
reg [31:0]b;
reg running;
wire RULE$respond_rule__ENA;
wire RULE$respond_rule__RDY;
assign indication$gcd$v = a;
assign indication$gcd__ENA = running & ( b == 32'd0 );
assign request$say__RDY = !running;
// Extra assigments, not to output wires
assign RULE$respond_rule__ENA = ( b != 32'd0 ) | indication$gcd__RDY | ( !running );
assign RULE$respond_rule__RDY = ( b != 32'd0 ) | indication$gcd__RDY | ( !running );
always @( posedge CLK) begin
if (!nRST) begin
a <= 0;
b <= 0;
running <= 0;
end // nRST
else begin
// RULE$flip_rule__ENA
if (( a < b ) & ( running != 0 )) begin
b <= a;
a <= b;
end;
// End of RULE$flip_rule__ENA
// RULE$mod_rule__ENA
if (( b != 0 ) & ( a >= b ) & ( running != 0 ))
a <= a - b;
// End of RULE$mod_rule__ENA
if (RULE$respond_rule__ENA & RULE$respond_rule__RDY) begin // RULE$respond_rule__ENA
if (( b == 0 ) & ( running != 0 ))
running <= 0;
end; // End of RULE$respond_rule__ENA
if (!( running | ( !request$say__ENA ) )) begin // request$say__ENA
a <= request$say$va;
b <= request$say$vb;
running <= 1;
end; // End of request$say__ENA
end
end // always @ (posedge CLK)
endmodule
`default_nettype wire // set back to default value
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Logic to determine if the virtual-channel held by a particular packet
* (buffered in an input PL FIFO) is blocked or ready?
*
* Looks at currently allocated PL or the next free PL that would be allocated
* at this port (as PL allocation may be taking place concurrently).
*
*/
module LAG_pl_status (output_port,
allocated_pl,
allocated_pl_valid,
pl_status,
pl_blocked);
parameter np=5;
parameter nv=4;
parameter unrestricted_pl_alloc = 0;
input output_port_t output_port [np-1:0][nv-1:0];
input [nv-1:0] allocated_pl [np-1:0][nv-1:0]; // allocated PL ID
input [np-1:0][nv-1:0] allocated_pl_valid; // holding allocated PL?
input [np-1:0][nv-1:0] pl_status; // blocked/ready status for each output PL
output [np-1:0][nv-1:0] pl_blocked;
logic [np-1:0][nv-1:0] b, current_pl_blocked;
genvar ip,pl,op;
generate
for (ip=0; ip<np; ip++) begin:il
for (pl=0; pl<nv; pl++) begin:vl
unary_select_pair #(ip, np, nv) blocked_mux
(output_port[ip][pl],
allocated_pl[ip][pl],
pl_status,
current_pl_blocked[ip][pl]);
assign b[ip][pl] = current_pl_blocked[ip][pl];
assign pl_blocked[ip][pl] = (LAG_route_valid_input_pl (ip,pl)) ? b[ip][pl] : 1'b0;
end
end
endgenerate
endmodule // LAG_pl_status
|
`timescale 1ns / 1ps
module Simulacion_Controlador_menu;
// Inputs
reg boton_arriba;
reg boton_abajo;
reg boton_izq;
reg boton_der;
reg boton_elige;
// Outputs
wire text_red;
wire text_green;
wire text_blue;
wire char_scale;
wire es_mayuscula;
wire nuevo;
wire guardar;
wire cerrar;
wire wf;
wire wc;
// Instantiate the Unit Under Test (UUT)
Controlador_Menu_Editor uut (
.boton_arriba(boton_arriba),
.boton_abajo(boton_abajo),
.boton_izq(boton_izq),
.boton_der(boton_der),
.boton_elige(boton_elige),
.text_red(text_red),
.text_green(text_green),
.text_blue(text_blue),
.char_scale(char_scale),
.es_mayuscula(es_mayuscula),
.nuevo(nuevo),
.guardar(guardar),
.cerrar(cerrar),
.where_fila (wf),
.where_columna (wc)
);
initial begin
// Initialize Inputs
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A32O_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FAHCIN_PP_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_LP_V
`define SKY130_FD_SC_LP__O31AI_LP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_lp (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3b (
VPWR,
VGND,
X ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Parameters of the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_defines.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.45 2006/04/09 01:32:29 lampret
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
//
// Revision 1.44 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.43 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.41 2004/05/09 20:03:20 lampret
// By default l.cust5 insns are disabled
//
// Revision 1.40 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.39 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.38 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.35.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.35.4.3 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
// Static exception prefix.
//
// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.33 2003/04/07 20:56:07 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
//
// Revision 1.32 2003/04/07 01:26:57 lampret
// RFRAM defines comments updated. Altera LPM option added.
//
// Revision 1.31 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.30 2002/10/28 15:09:22 mohor
// Previous check-in was done by mistake.
//
// Revision 1.29 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.28 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.27 2002/09/16 03:13:23 lampret
// Removed obsolete comment.
//
// Revision 1.26 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.25 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.24 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.23 2002/09/04 00:50:34 lampret
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
//
// Revision 1.22 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.21 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.20 2002/08/18 21:59:45 lampret
// Disable SB until it is tested
//
// Revision 1.19 2002/08/18 19:53:08 lampret
// Added store buffer.
//
// Revision 1.18 2002/08/15 06:04:11 lampret
// Fixed Xilinx trace buffer address. REported by Taylor Su.
//
// Revision 1.17 2002/08/12 05:31:44 lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
// Revision 1.16 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.15 2002/06/08 16:20:21 lampret
// Added defines for enabling generic FF based memory macro for register file.
//
// Revision 1.14 2002/03/29 16:24:06 lampret
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
//
// Revision 1.13 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.12 2002/03/28 19:25:42 lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.11 2002/03/28 19:13:17 lampret
// Updated defines.
//
// Revision 1.10 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.9 2002/03/11 01:26:26 lampret
// Fixed async loop. Changed multiplier type for ASIC.
//
// Revision 1.8 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.7 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.6 2002/01/19 14:10:22 lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.5 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4 2002/01/14 09:44:12 lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3 2002/01/08 00:51:08 lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
// Revision 1.2 2002/01/03 21:23:03 lampret
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.20 2001/12/04 05:02:36 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.19 2001/11/27 19:46:57 lampret
// Now FPGA and ASIC target are separate.
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 21:30:38 lampret
// Added OR1200_REGISTERED_INPUTS.
//
// Revision 1.15 2001/11/19 14:29:48 simons
// Cashes disabled.
//
// Revision 1.14 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.13 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.12 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.11 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.2 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
// `define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
//`define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`else
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
//
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
//XLNX_MODIFIED uncomment below
`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//
// Do not implement Data cache
//
//XLNX_MODIFIED commented the line below
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//XLNX_MODIFIED commented the line below below
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//XLNX_MODIFIED comment out below
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//XLNX_MODIFIED commented the line below
//`define OR1200_NO_IMMU
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
//XLNX_MODIFIED go to 1W 8k for more cache depth
//`define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
//`define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`endif
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
//XLNX_MODIFIED - This design needs more output registers
//hacked the code to register some of them
`define XLNX_MODIFIED
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//XLNX_MODIFIED uncommeted the line below
`define OR1200_WB_RETRY 7
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
`define OR1200_WB_CAB
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
//v6 mod
`define OR1200_WB_B3
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
//XLNX_MODIFIED - want the full_case as well as the ||case.
//going back to remove the full_case due to complaints about the synthesis messaging
`define OR1200_CASE_DEFAULT
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//v6 mod
`define OR1200_ADDITIONAL_FLAG_MODIFIERS
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
`define OR1200_IMPL_ADDC
//
// Implement carry bit SR[CY]
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However
// SR[CY] is explicitly only used by l.addc/l.addic
// instructions and if these two insns are not
// implemented there is not much point having SR[CY].
//
`define OR1200_IMPL_CY
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
//
// To implement divide, multiplier needs to be implemented.
//
//XLNX_MODIFIED 3/30
`define OR1200_IMPL_DIV
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//XLNX_MODIFIED 3/30
`define OR1200_IMPL_ALU_ROTATE
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
//
// Low power, slower multiplier
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//
//`define OR1200_LOWPWR_MULT
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
`define OR1200_RFRAM_GENERIC
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4
/* Order defined by arith insns that have two source operands both in regs
(see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD 4'd0
`define OR1200_ALUOP_ADDC 4'd1
`define OR1200_ALUOP_SUB 4'd2
`define OR1200_ALUOP_AND 4'd3
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_FF1 4'd15
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 2
`define OR1200_MACOP_NOP 2'b00
`define OR1200_MACOP_MAC 2'b01
`define OR1200_MACOP_MSB 2'b10
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 2
`define OR1200_SHROTOP_NOP 2'd0
`define OR1200_SHROTOP_SLL 2'd0
`define OR1200_SHROTOP_SRL 2'd1
`define OR1200_SHROTOP_SRA 2'd2
`define OR1200_SHROTOP_ROR 2'd3
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE 2'd0
`define OR1200_TWO_CYCLES 2'd1
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH 3
`define OR1200_RFWBOP_NOP 3'b000
`define OR1200_RFWBOP_ALU 3'b001
`define OR1200_RFWBOP_LSU 3'b011
`define OR1200_RFWBOP_SPRS 3'b101
`define OR1200_RFWBOP_LR 3'b111
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS 9:8
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
//`define OR1200_OR32_MOVHI 6'b000111
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
//`define OR1200_OR32_CUST5 6'b111100
/////////////////////////////////////////////////////
//
// Exceptions
//
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
/////////////////////////////////////////////////////
//
// SPR groups
//
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
/////////////////////////////////////////////////////
//
// System group
//
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
// PM group
`define OR1200_SPRGRP_PM 5'd8
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
`define OR1200_DU_HWBKPTS
// Number of DVR/DCR pairs if HW breakpoints enabled
`define OR1200_DU_DVRDCR_PAIRS 8
// Define if you want trace buffer
`define OR1200_DU_TB_IMPLEMENTED
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`endif
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_BE 12
`define OR1200_DU_DSR_TE 13
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_BE 12
`define OR1200_DU_DRR_TE 13
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
// Define if IF/LSU status is not needed by devel i/f
//`define OR1200_DU_STATUS_UNIMPLEMENTED
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
//
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[30]
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI icpu_adr_i[30]
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS 4
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Data cache (DC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS 3
// Define to perform store refill (potential performance penalty)
`define OR1200_DC_STORE_REFILL
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
`define OR1200_SB_IMPLEMENTED
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 3 // 2 or 3
`define OR1200_SB_ENTRIES 8 // 4 or 8
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
`define OR1200_QMEM_IMPLEMENTED
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
`define OR1200_QMEM_BSEL
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
// VR values
`define OR1200_VR_REV 6'h01
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_RES1_BITS 23:11
`define OR1200_UPR_CUP_BITS 31:24
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`define OR1200_UPR_MP 1'b1 // MAC always present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`define OR1200_UPR_RES1 13'h0000
`define OR1200_UPR_CUP 8'h00
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`define OR1200_CPUCFGR_HGF 1'b0
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`define OR1200_CPUCFGR_OF32S 1'b0
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`define OR1200_DCCFGR_RES1 17'h00000
`endif
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 2:0
`define OR1200_DCFGR_WPCI_BITS 3
`define OR1200_DCFGR_RES1_BITS 31:4
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
|
// iverilog -y .. -o tb-DataBuffer.vvp tb-DataBuffer.v
// vvp tb-DataBuffer.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata_vld;
reg odata_rdy;
wire [W-1:0] odata;
DataBuffer#(W) dut(clk, rst, idata_vld, idata_rdy, idata, odata_vld, odata_rdy, odata);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h23456789;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy
reg [31:0] rngseed, rnum;
integer n;
#0;
odata_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-DataBuffer.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (odata_vld & odata_rdy) begin
rnum = $random(rngseed);
if (odata !== rnum[W-1:0]) begin
$display("%0t: Error: odata %h != %h", $time, odata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata);
end
@(posedge clk);
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2006-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_phy_calib.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Thu Aug 10 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module handles calibration after memory initialization.
//Reference:
//Revision History:
// Rev 1.1 - Default statement is added for the CASE statement of
// rdd_mux_sel logic. PK. 03/23/09
// Rev 1.2 - Change training pattern detected for stage 3 calibration.
// Use 2-bits per DQS group for stage 3 pattern detection.
// RC. 09/21/09
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_calib #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter ADDITIVE_LAT = 0,
parameter CAS_LAT = 5,
parameter REG_ENABLE = 1,
parameter CLK_PERIOD = 3000,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0
)
(
input clk,
input clkdiv,
input rstdiv,
input [3:0] calib_start,
input ctrl_rden,
input phy_init_rden,
input [DQ_WIDTH-1:0] rd_data_rise,
input [DQ_WIDTH-1:0] rd_data_fall,
input calib_ref_done,
output reg [3:0] calib_done,
output reg calib_ref_req,
output [DQS_WIDTH-1:0] calib_rden,
output reg [DQS_WIDTH-1:0] calib_rden_sel,
output reg dlyrst_dq,
output reg [DQ_WIDTH-1:0] dlyce_dq,
output reg [DQ_WIDTH-1:0] dlyinc_dq,
output reg dlyrst_dqs,
output reg [DQS_WIDTH-1:0] dlyce_dqs,
output reg [DQS_WIDTH-1:0] dlyinc_dqs,
output reg [DQS_WIDTH-1:0] dlyrst_gate,
output reg [DQS_WIDTH-1:0] dlyce_gate,
output reg [DQS_WIDTH-1:0] dlyinc_gate,
//(* XIL_PAR_NO_REG_ORDER = "TRUE", XIL_PAR_PATH="Q->u_iodelay_dq_ce.DATAIN", syn_keep = "1", keep = "TRUE"*)
output [DQS_WIDTH-1:0] en_dqs,
output [DQS_WIDTH-1:0] rd_data_sel,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
);
// minimum time (in IDELAY taps) for which capture data must be stable for
// algorithm to consider
localparam MIN_WIN_SIZE = 5;
// IDEL_SET_VAL = (# of cycles - 1) to wait after changing IDELAY value
// we only have to wait enough for input with new IDELAY value to
// propagate through pipeline stages.
localparam IDEL_SET_VAL = 3'b111;
// # of clock cycles to delay read enable to determine if read data pattern
// is correct for stage 3/4 (RDEN, DQS gate) calibration
localparam CALIB_RDEN_PIPE_LEN = 31;
// translate CAS latency into number of clock cycles for read valid delay
// determination. Really only needed for CL = 2.5 (set to 2)
localparam CAS_LAT_RDEN = (CAS_LAT == 25) ? 2 : CAS_LAT;
// an SRL32 is used to delay CTRL_RDEN to generate read valid signal. This
// is min possible value delay through SRL32 can be
localparam RDEN_BASE_DELAY = CAS_LAT_RDEN + ADDITIVE_LAT + REG_ENABLE;
// an SRL32 is used to delay the CTRL_RDEN from the read postamble DQS
// gate. This is min possible value the SRL32 delay can be:
// - Delay from end of deassertion of CTRL_RDEN to last falling edge of
// read burst = 3.5 (CTRL_RDEN -> CAS delay) + 3 (min CAS latency) = 6.5
// - Minimum time for DQS gate circuit to be generated:
// * 1 cyc to register CTRL_RDEN from controller
// * 1 cyc after RDEN_CTRL falling edge
// * 1 cyc min through SRL32
// * 1 cyc through SRL32 output flop
// * 0 (<1) cyc of synchronization to DQS domain via IDELAY
// * 1 cyc of delay through IDDR to generate CE to DQ IDDR's
// Total = 5 cyc < 6.5 cycles
// The total should be less than 5.5 cycles to account prop delays
// adding one cycle to the synchronization time via the IDELAY.
// NOTE: Value differs because of optional pipeline register added
// for case of RDEN_BASE_DELAY > 3 to improve timing
localparam GATE_BASE_DELAY = RDEN_BASE_DELAY - 3;
localparam GATE_BASE_INIT = (GATE_BASE_DELAY <= 1) ? 0 : GATE_BASE_DELAY;
// used for RDEN calibration: difference between shift value used during
// calibration, and shift value for actual RDEN SRL. Only applies when
// RDEN edge is immediately captured by CLKDIV0. If not (depends on phase
// of CLK0 and CLKDIV0 when RDEN is asserted), then add 1 to this value.
localparam CAL3_RDEN_SRL_DLY_DELTA = 6;
// fix minimum value of DQS to be 1 to handle the case where's there's only
// one DQS group. We could also enforce that user always inputs minimum
// value of 1 for DQS_BITS (even when DQS_WIDTH=1). Leave this as safeguard
// Assume we don't have to do this for DQ, DQ_WIDTH always > 1
localparam DQS_BITS_FIX = (DQS_BITS == 0) ? 1 : DQS_BITS;
// how many taps to "pre-delay" DQ before stg 1 calibration - not needed for
// current calibration, but leave for debug
localparam DQ_IDEL_INIT = 6'b000000;
// # IDELAY taps per bit time (i.e. half cycle). Limit to 63.
localparam integer BIT_TIME_TAPS = (CLK_PERIOD/150 < 64) ?
CLK_PERIOD/150 : 63;
// used in various places during stage 4 cal: (1) determines maximum taps
// to increment when finding right edge, (2) amount to decrement after
// finding left edge, (3) amount to increment after finding right edge
localparam CAL4_IDEL_BIT_VAL = (BIT_TIME_TAPS >= 6'b100000) ?
6'b100000 : BIT_TIME_TAPS;
localparam CAL1_IDLE = 4'h0;
localparam CAL1_INIT = 4'h1;
localparam CAL1_INC_IDEL = 4'h2;
localparam CAL1_FIND_FIRST_EDGE = 4'h3;
localparam CAL1_FIRST_EDGE_IDEL_WAIT = 4'h4;
localparam CAL1_FOUND_FIRST_EDGE_WAIT = 4'h5;
localparam CAL1_FIND_SECOND_EDGE = 4'h6;
localparam CAL1_SECOND_EDGE_IDEL_WAIT = 4'h7;
localparam CAL1_CALC_IDEL = 4'h8;
localparam CAL1_DEC_IDEL = 4'h9;
localparam CAL1_DONE = 4'hA;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_INIT = 4'h1;
localparam CAL2_INIT_IDEL_WAIT = 4'h2;
localparam CAL2_FIND_EDGE_POS = 4'h3;
localparam CAL2_FIND_EDGE_IDEL_WAIT_POS = 4'h4;
localparam CAL2_FIND_EDGE_NEG = 4'h5;
localparam CAL2_FIND_EDGE_IDEL_WAIT_NEG = 4'h6;
localparam CAL2_DEC_IDEL = 4'h7;
localparam CAL2_DONE = 4'h8;
localparam CAL3_IDLE = 3'h0;
localparam CAL3_INIT = 3'h1;
localparam CAL3_DETECT = 3'h2;
localparam CAL3_RDEN_PIPE_CLR_WAIT = 3'h3;
localparam CAL3_DONE = 3'h4;
localparam CAL4_IDLE = 3'h0;
localparam CAL4_INIT = 3'h1;
localparam CAL4_FIND_WINDOW = 3'h2;
localparam CAL4_FIND_EDGE = 3'h3;
localparam CAL4_IDEL_WAIT = 3'h4;
localparam CAL4_RDEN_PIPE_CLR_WAIT = 3'h5;
localparam CAL4_ADJ_IDEL = 3'h6;
localparam CAL4_DONE = 3'h7;
integer i, j;
reg [5:0] cal1_bit_time_tap_cnt;
reg [1:0] cal1_data_chk_last;
reg cal1_data_chk_last_valid;
reg [1:0] cal1_data_chk_r;
reg cal1_dlyce_dq;
reg cal1_dlyinc_dq;
reg cal1_dqs_dq_init_phase;
reg cal1_detect_edge;
reg cal1_detect_stable;
reg cal1_found_second_edge;
reg cal1_found_rising;
reg cal1_found_window;
reg cal1_first_edge_done;
reg [5:0] cal1_first_edge_tap_cnt;
reg [6:0] cal1_idel_dec_cnt;
reg [5:0] cal1_idel_inc_cnt;
reg [5:0] cal1_idel_max_tap;
reg cal1_idel_max_tap_we;
reg [5:0] cal1_idel_tap_cnt;
reg cal1_idel_tap_limit_hit;
reg [6:0] cal1_low_freq_idel_dec;
reg cal1_ref_req;
wire cal1_refresh;
reg [3:0] cal1_state;
reg [3:0] cal1_window_cnt;
reg cal2_curr_sel;
wire cal2_detect_edge;
reg cal2_dlyce_dqs;
reg cal2_dlyinc_dqs;
reg [5:0] cal2_idel_dec_cnt;
reg [5:0] cal2_idel_tap_cnt;
reg [5:0] cal2_idel_tap_limit;
reg cal2_idel_tap_limit_hit;
reg cal2_rd_data_fall_last_neg;
reg cal2_rd_data_fall_last_pos;
reg cal2_rd_data_last_valid_neg;
reg cal2_rd_data_last_valid_pos;
reg cal2_rd_data_rise_last_neg;
reg cal2_rd_data_rise_last_pos;
reg [DQS_WIDTH-1:0] cal2_rd_data_sel;
wire cal2_rd_data_sel_edge;
reg [DQS_WIDTH-1:0] cal2_rd_data_sel_r;
reg cal2_ref_req;
reg [3:0] cal2_state;
reg cal3_data_match;
reg cal3_data_match_stgd;
wire cal3_data_valid;
wire cal3_match_found;
wire [4:0] cal3_rden_dly;
reg [4:0] cal3_rden_srl_a;
reg [2:0] cal3_state;
wire cal4_data_good;
reg cal4_data_match;
reg cal4_data_match_stgd;
wire cal4_data_valid;
reg cal4_dlyce_gate;
reg cal4_dlyinc_gate;
reg cal4_dlyrst_gate;
reg [4:0] cal4_gate_srl_a;
reg [5:0] cal4_idel_adj_cnt;
reg cal4_idel_adj_inc;
reg cal4_idel_bit_tap;
reg [5:0] cal4_idel_tap_cnt;
reg cal4_idel_max_tap;
reg [4:0] cal4_rden_srl_a;
reg cal4_ref_req;
reg cal4_seek_left;
reg cal4_stable_window;
reg [2:0] cal4_state;
reg [3:0] cal4_window_cnt;
reg [3:0] calib_done_tmp; // only for stg1/2/4
reg calib_ctrl_gate_pulse_r;
reg calib_ctrl_rden;
reg calib_ctrl_rden_r;
wire calib_ctrl_rden_negedge;
reg calib_ctrl_rden_negedge_r;
reg [3:0] calib_done_r;
reg [3:0] calib_err;
reg [1:0] calib_err_2;
wire calib_init_gate_pulse;
reg calib_init_gate_pulse_r;
reg calib_init_gate_pulse_r1;
reg calib_init_rden;
reg calib_init_rden_r;
reg [4:0] calib_rden_srl_a;
wire [4:0] calib_rden_srl_a_r;
reg [(5*DQS_WIDTH)-1:0] calib_rden_dly;
reg calib_rden_edge_r;
reg [4:0] calib_rden_pipe_cnt;
wire calib_rden_srl_out;
wire calib_rden_srl_out_r;
reg calib_rden_srl_out_r1;
reg calib_rden_valid;
reg calib_rden_valid_stgd;
reg [DQ_BITS-1:0] count_dq;
reg [DQS_BITS_FIX-1:0] count_dqs;
reg [DQS_BITS_FIX-1:0] count_gate;
reg [DQS_BITS_FIX-1:0] count_rden;
reg ctrl_rden_r;
wire dlyce_or;
reg [(5*DQS_WIDTH)-1:0] gate_dly;
wire [(5*DQS_WIDTH)-1:0] gate_dly_r;
wire gate_srl_in;
wire [DQS_WIDTH-1:0] gate_srl_out;
wire [DQS_WIDTH-1:0] gate_srl_out_r;
reg [2:0] idel_set_cnt;
wire idel_set_wait;
reg [DQ_BITS-1:0] next_count_dq;
reg [DQS_BITS_FIX-1:0] next_count_dqs;
reg [DQS_BITS_FIX-1:0] next_count_gate;
reg phy_init_rden_r;
reg phy_init_rden_r1;
reg [DQS_WIDTH-1:0] rd_data_fall_1x_bit1_r1;
reg [DQ_WIDTH-1:0] rd_data_fall_1x_r;
reg [DQS_WIDTH-1:0] rd_data_fall_1x_r1;
reg [DQS_WIDTH-1:0] rd_data_fall_2x_bit1_r;
reg [DQS_WIDTH-1:0] rd_data_fall_2x_r;
wire [DQS_WIDTH-1:0] rd_data_fall_chk_q1;
wire [DQS_WIDTH-1:0] rd_data_fall_chk_q1_bit1;
wire [DQS_WIDTH-1:0] rd_data_fall_chk_q2;
wire [DQS_WIDTH-1:0] rd_data_fall_chk_q2_bit1;
reg [DQS_WIDTH-1:0] rd_data_rise_1x_bit1_r1;
reg [DQ_WIDTH-1:0] rd_data_rise_1x_r;
reg [DQS_WIDTH-1:0] rd_data_rise_1x_r1;
reg [DQS_WIDTH-1:0] rd_data_rise_2x_bit1_r;
reg [DQS_WIDTH-1:0] rd_data_rise_2x_r;
wire [DQS_WIDTH-1:0] rd_data_rise_chk_q1;
wire [DQS_WIDTH-1:0] rd_data_rise_chk_q1_bit1;
wire [DQS_WIDTH-1:0] rd_data_rise_chk_q2;
wire [DQS_WIDTH-1:0] rd_data_rise_chk_q2_bit1;
reg rdd_fall_q1;
reg rdd_fall_q1_bit1;
reg rdd_fall_q1_bit1_r;
reg rdd_fall_q1_bit1_r1;
reg rdd_fall_q1_r;
reg rdd_fall_q1_r1;
reg rdd_fall_q2;
reg rdd_fall_q2_bit1;
reg rdd_fall_q2_bit1_r;
reg rdd_fall_q2_r;
reg rdd_rise_q1;
reg rdd_rise_q1_bit1;
reg rdd_rise_q1_bit1_r;
reg rdd_rise_q1_bit1_r1;
reg rdd_rise_q1_r;
reg rdd_rise_q1_r1;
reg rdd_rise_q2;
reg rdd_rise_q2_bit1;
reg rdd_rise_q2_bit1_r;
reg rdd_rise_q2_r;
reg [DQS_BITS_FIX-1:0] rdd_mux_sel;
reg rden_dec;
reg [(5*DQS_WIDTH)-1:0] rden_dly;
wire [(5*DQS_WIDTH)-1:0] rden_dly_r;
reg [4:0] rden_dly_0;
reg rden_inc;
reg [DQS_WIDTH-1:0] rden_mux;
wire [DQS_WIDTH-1:0] rden_srl_out;
// Debug
integer x;
reg [5:0] dbg_dq_tap_cnt [DQ_WIDTH-1:0];
reg [5:0] dbg_dqs_tap_cnt [DQS_WIDTH-1:0];
reg [5:0] dbg_gate_tap_cnt [DQS_WIDTH-1:0];
//***************************************************************************
// Debug output ("dbg_phy_calib_*")
// NOTES:
// 1. All debug outputs coming out of PHY_CALIB are clocked off CLKDIV0,
// although they are also static after calibration is complete. This
// means the user can either connect them to a Chipscope ILA, or to
// either a sync/async VIO input block. Using an async VIO has the
// advantage of not requiring these paths to meet cycle-to-cycle timing.
// 2. The widths of most of these debug buses are dependent on the # of
// DQS/DQ bits (e.g. dq_tap_cnt width = 6 * (# of DQ bits)
// SIGNAL DESCRIPTION:
// 1. calib_done: 4 bits - each one asserted as each phase of calibration
// is completed.
// 2. calib_err: 4 bits - each one asserted when a calibration error
// encountered for that stage. Some of these bits may not
// be used (not all cal stages report an error).
// 3. dq_tap_cnt: final IDELAY tap counts for all DQ IDELAYs
// 4. dqs_tap_cnt: final IDELAY tap counts for all DQS IDELAYs
// 5. gate_tap_cnt: final IDELAY tap counts for all DQS gate
// synchronization IDELAYs
// 6. rd_data_sel: final read capture MUX (either "positive" or "negative"
// edge capture) settings for all DQS groups
// 7. rden_dly: related to # of cycles after issuing a read until when
// read data is valid - for all DQS groups
// 8. gate_dly: related to # of cycles after issuing a read until when
// clock enable for all DQ's is deasserted to prevent
// effect of DQS postamble glitch - for all DQS groups
//***************************************************************************
//*****************************************************************
// Record IDELAY tap values by "snooping" IDELAY control signals
//*****************************************************************
// record DQ IDELAY tap values
genvar dbg_dq_tc_i;
generate
for (dbg_dq_tc_i = 0; dbg_dq_tc_i < DQ_WIDTH;
dbg_dq_tc_i = dbg_dq_tc_i + 1) begin: gen_dbg_dq_tap_cnt
assign dbg_calib_dq_tap_cnt[(6*dbg_dq_tc_i)+5:(6*dbg_dq_tc_i)]
= dbg_dq_tap_cnt[dbg_dq_tc_i];
always @(posedge clkdiv)
if (rstdiv | dlyrst_dq)
dbg_dq_tap_cnt[dbg_dq_tc_i] <= 6'b000000;
else
if (dlyce_dq[dbg_dq_tc_i])
if (dlyinc_dq[dbg_dq_tc_i])
dbg_dq_tap_cnt[dbg_dq_tc_i]
<= dbg_dq_tap_cnt[dbg_dq_tc_i] + 1;
else
dbg_dq_tap_cnt[dbg_dq_tc_i]
<= dbg_dq_tap_cnt[dbg_dq_tc_i] - 1;
end
endgenerate
// record DQS IDELAY tap values
genvar dbg_dqs_tc_i;
generate
for (dbg_dqs_tc_i = 0; dbg_dqs_tc_i < DQS_WIDTH;
dbg_dqs_tc_i = dbg_dqs_tc_i + 1) begin: gen_dbg_dqs_tap_cnt
assign dbg_calib_dqs_tap_cnt[(6*dbg_dqs_tc_i)+5:(6*dbg_dqs_tc_i)]
= dbg_dqs_tap_cnt[dbg_dqs_tc_i];
always @(posedge clkdiv)
if (rstdiv | dlyrst_dqs)
dbg_dqs_tap_cnt[dbg_dqs_tc_i] <= 6'b000000;
else
if (dlyce_dqs[dbg_dqs_tc_i])
if (dlyinc_dqs[dbg_dqs_tc_i])
dbg_dqs_tap_cnt[dbg_dqs_tc_i]
<= dbg_dqs_tap_cnt[dbg_dqs_tc_i] + 1;
else
dbg_dqs_tap_cnt[dbg_dqs_tc_i]
<= dbg_dqs_tap_cnt[dbg_dqs_tc_i] - 1;
end
endgenerate
// record DQS gate IDELAY tap values
genvar dbg_gate_tc_i;
generate
for (dbg_gate_tc_i = 0; dbg_gate_tc_i < DQS_WIDTH;
dbg_gate_tc_i = dbg_gate_tc_i + 1) begin: gen_dbg_gate_tap_cnt
assign dbg_calib_gate_tap_cnt[(6*dbg_gate_tc_i)+5:(6*dbg_gate_tc_i)]
= dbg_gate_tap_cnt[dbg_gate_tc_i];
always @(posedge clkdiv)
if (rstdiv | dlyrst_gate[dbg_gate_tc_i])
dbg_gate_tap_cnt[dbg_gate_tc_i] <= 6'b000000;
else
if (dlyce_gate[dbg_gate_tc_i])
if (dlyinc_gate[dbg_gate_tc_i])
dbg_gate_tap_cnt[dbg_gate_tc_i]
<= dbg_gate_tap_cnt[dbg_gate_tc_i] + 1;
else
dbg_gate_tap_cnt[dbg_gate_tc_i]
<= dbg_gate_tap_cnt[dbg_gate_tc_i] - 1;
end
endgenerate
assign dbg_calib_done = calib_done;
assign dbg_calib_err = calib_err;
assign dbg_calib_rd_data_sel = cal2_rd_data_sel;
assign dbg_calib_rden_dly = rden_dly;
assign dbg_calib_gate_dly = gate_dly;
//***************************************************************************
// Read data pipelining, and read data "ISERDES" data width expansion
//***************************************************************************
// For all data bits, register incoming capture data to slow clock to improve
// timing. Adding single pipeline stage does not affect functionality (as
// long as we make sure to wait extra clock cycle after changing DQ IDELAY)
// Also note in this case that we're "missing" every other clock cycle's
// worth of data capture since we're sync'ing to the slow clock. This is
// fine for stage 1 and stage 2 cal, but not for stage 3 and 4 (see below
// for different circuit to handle those stages)
always @(posedge clkdiv) begin
rd_data_rise_1x_r <= rd_data_rise;
rd_data_fall_1x_r <= rd_data_fall;
end
// For every DQ_PER_DQS bit, generate what is essentially a ISERDES-type
// data width expander. Will need this for stage 3 and 4 cal, where we need
// to compare data over consecutive clock cycles. We can also use this for
// stage 2 as well (stage 2 doesn't require every bit to be looked at, only
// one bit per DQS group)
// MIG 3.3: Expand to use lower two bits of each DQS group - use for stage
// 3 calibration for added robustness, since we will be checking for the
// training pattern from the memory even when the data bus is 3-stated.
// Theoretically it is possible for whatever garbage data is on the bus
// to be interpreted as the training sequence, although this can be made
// very unlikely by the choice of training sequence (bit sequence, length)
// and the number of bits compared for each DQS group.
genvar rdd_i;
generate
for (rdd_i = 0; rdd_i < DQS_WIDTH; rdd_i = rdd_i + 1) begin: gen_rdd
// first stage: keep data in fast clk domain. Store data over two
// consecutive clock cycles for rise/fall data for proper transfer
// to slow clock domain
always @(posedge clk) begin
rd_data_rise_2x_r[rdd_i] <= rd_data_rise[(rdd_i*DQ_PER_DQS)];
rd_data_fall_2x_r[rdd_i] <= rd_data_fall[(rdd_i*DQ_PER_DQS)];
rd_data_rise_2x_bit1_r[rdd_i] <= rd_data_rise[(rdd_i*DQ_PER_DQS)+1];
rd_data_fall_2x_bit1_r[rdd_i] <= rd_data_fall[(rdd_i*DQ_PER_DQS)+1];
end
// second stage, register first stage to slow clock domain, 2nd stage
// consists of both these flops, and the rd_data_rise_1x_r flops
always @(posedge clkdiv) begin
rd_data_rise_1x_r1[rdd_i] <= rd_data_rise_2x_r[rdd_i];
rd_data_fall_1x_r1[rdd_i] <= rd_data_fall_2x_r[rdd_i];
rd_data_rise_1x_bit1_r1[rdd_i] <= rd_data_rise_2x_bit1_r[rdd_i];
rd_data_fall_1x_bit1_r1[rdd_i] <= rd_data_fall_2x_bit1_r[rdd_i];
end
// now we have four outputs - representing rise/fall outputs over last
// 2 fast clock cycles. However, the ordering these represent can either
// be: (1) Q2 = data @ time = n, Q1 = data @ time = n+1, or (2)
// Q2 = data @ time = n - 1, Q1 = data @ time = n (and data at [Q1,Q2]
// is "staggered") - leave it up to the stage of calibration using this
// to figure out which is which, if they care at all (e.g. stage 2 cal
// doesn't care about the ordering)
assign rd_data_rise_chk_q1[rdd_i]
= rd_data_rise_1x_r[(rdd_i*DQ_PER_DQS)];
assign rd_data_rise_chk_q2[rdd_i]
= rd_data_rise_1x_r1[rdd_i];
assign rd_data_fall_chk_q1[rdd_i]
= rd_data_fall_1x_r[(rdd_i*DQ_PER_DQS)];
assign rd_data_fall_chk_q2[rdd_i]
= rd_data_fall_1x_r1[rdd_i];
// MIG 3.3: Added comparison for second bit in DQS group for stage 3 cal
assign rd_data_rise_chk_q1_bit1[rdd_i]
= rd_data_rise_1x_r[(rdd_i*DQ_PER_DQS)+1];
assign rd_data_rise_chk_q2_bit1[rdd_i]
= rd_data_rise_1x_bit1_r1[rdd_i];
assign rd_data_fall_chk_q1_bit1[rdd_i]
= rd_data_fall_1x_r[(rdd_i*DQ_PER_DQS)+1];
assign rd_data_fall_chk_q2_bit1[rdd_i]
= rd_data_fall_1x_bit1_r1[rdd_i];
end
endgenerate
//*****************************************************************
// Outputs of these simplified ISERDES circuits then feed MUXes based on
// which DQ the current calibration algorithm needs to look at
//*****************************************************************
// generate MUX control; assume that adding an extra pipeline stage isn't
// an issue - whatever stage cal logic is using output of MUX will wait
// enough time after changing it
always @(posedge clkdiv) begin
(* full_case, parallel_case *) case (calib_done[2:0])
3'b001: rdd_mux_sel <= next_count_dqs;
3'b011: rdd_mux_sel <= count_rden;
3'b111: rdd_mux_sel <= next_count_gate;
default: rdd_mux_sel <= {DQS_BITS_FIX{1'bx}};
endcase
end
always @(posedge clkdiv) begin
rdd_rise_q1 <= rd_data_rise_chk_q1[rdd_mux_sel];
rdd_rise_q2 <= rd_data_rise_chk_q2[rdd_mux_sel];
rdd_fall_q1 <= rd_data_fall_chk_q1[rdd_mux_sel];
rdd_fall_q2 <= rd_data_fall_chk_q2[rdd_mux_sel];
rdd_rise_q1_bit1 <= rd_data_rise_chk_q1_bit1[rdd_mux_sel];
rdd_rise_q2_bit1 <= rd_data_rise_chk_q2_bit1[rdd_mux_sel];
rdd_fall_q1_bit1 <= rd_data_fall_chk_q1_bit1[rdd_mux_sel];
rdd_fall_q2_bit1 <= rd_data_fall_chk_q2_bit1[rdd_mux_sel];
end
//***************************************************************************
// Demultiplexor to control (reset, increment, decrement) IDELAY tap values
// For DQ:
// STG1: for per-bit-deskew, only inc/dec the current DQ. For non-per
// deskew, increment all bits in the current DQS set
// STG2: inc/dec all DQ's in the current DQS set.
// NOTE: Nice to add some error checking logic here (or elsewhere in the
// code) to check if logic attempts to overflow tap value
//***************************************************************************
// don't use DLYRST to reset value of IDELAY after reset. Need to change this
// if we want to allow user to recalibrate after initial reset
always @(posedge clkdiv)
if (rstdiv) begin
dlyrst_dq <= 1'b1;
dlyrst_dqs <= 1'b1;
end else begin
dlyrst_dq <= 1'b0;
dlyrst_dqs <= 1'b0;
end
always @(posedge clkdiv) begin
if (rstdiv) begin
dlyce_dq <= 'b0;
dlyinc_dq <= 'b0;
dlyce_dqs <= 'b0;
dlyinc_dqs <= 'b0;
end else begin
dlyce_dq <= 'b0;
dlyinc_dq <= 'b0;
dlyce_dqs <= 'b0;
dlyinc_dqs <= 'b0;
// stage 1 cal: change only specified DQ
if (cal1_dlyce_dq) begin
if (SIM_ONLY == 0) begin
dlyce_dq[count_dq] <= 1'b1;
dlyinc_dq[count_dq] <= cal1_dlyinc_dq;
end else begin
// if simulation, then calibrate only first DQ, apply results
// to all DQs (i.e. assume delay on all DQs is the same)
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: loop_sim_dq_dly
dlyce_dq[i] <= 1'b1;
dlyinc_dq[i] <= cal1_dlyinc_dq;
end
end
end else if (cal2_dlyce_dqs) begin
// stage 2 cal: change DQS and all corresponding DQ's
if (SIM_ONLY == 0) begin
dlyce_dqs[count_dqs] <= 1'b1;
dlyinc_dqs[count_dqs] <= cal2_dlyinc_dqs;
for (i = 0; i < DQ_PER_DQS; i = i + 1) begin: loop_dqs_dly
dlyce_dq[(DQ_PER_DQS*count_dqs)+i] <= 1'b1;
dlyinc_dq[(DQ_PER_DQS*count_dqs)+i] <= cal2_dlyinc_dqs;
end
end else begin
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_sim_dqs_dly
// if simulation, then calibrate only first DQS
dlyce_dqs[i] <= 1'b1;
dlyinc_dqs[i] <= cal2_dlyinc_dqs;
for (j = 0; j < DQ_PER_DQS; j = j + 1) begin: loop_sim_dq_dqs_dly
dlyce_dq[(DQ_PER_DQS*i)+j] <= 1'b1;
dlyinc_dq[(DQ_PER_DQS*i)+j] <= cal2_dlyinc_dqs;
end
end
end
end else if (DEBUG_EN != 0) begin
// DEBUG: allow user to vary IDELAY tap settings
// For DQ IDELAY taps
if (dbg_idel_up_all || dbg_idel_down_all ||
dbg_sel_all_idel_dq) begin
for (x = 0; x < DQ_WIDTH; x = x + 1) begin: loop_dly_inc_dq
dlyce_dq[x] <= dbg_idel_up_all | dbg_idel_down_all |
dbg_idel_up_dq | dbg_idel_down_dq;
dlyinc_dq[x] <= dbg_idel_up_all | dbg_idel_up_dq;
end
end else begin
dlyce_dq <= 'b0;
dlyce_dq[dbg_sel_idel_dq] <= dbg_idel_up_dq |
dbg_idel_down_dq;
dlyinc_dq[dbg_sel_idel_dq] <= dbg_idel_up_dq;
end
// For DQS IDELAY taps
if (dbg_idel_up_all || dbg_idel_down_all ||
dbg_sel_all_idel_dqs) begin
for (x = 0; x < DQS_WIDTH; x = x + 1) begin: loop_dly_inc_dqs
dlyce_dqs[x] <= dbg_idel_up_all | dbg_idel_down_all |
dbg_idel_up_dqs | dbg_idel_down_dqs;
dlyinc_dqs[x] <= dbg_idel_up_all | dbg_idel_up_dqs;
end
end else begin
dlyce_dqs <= 'b0;
dlyce_dqs[dbg_sel_idel_dqs] <= dbg_idel_up_dqs |
dbg_idel_down_dqs;
dlyinc_dqs[dbg_sel_idel_dqs] <= dbg_idel_up_dqs;
end
end
end
end
// GATE synchronization is handled directly by Stage 4 calibration FSM
always @(posedge clkdiv)
if (rstdiv) begin
dlyrst_gate <= {DQS_WIDTH{1'b1}};
dlyce_gate <= {DQS_WIDTH{1'b0}};
dlyinc_gate <= {DQS_WIDTH{1'b0}};
end else begin
dlyrst_gate <= {DQS_WIDTH{1'b0}};
dlyce_gate <= {DQS_WIDTH{1'b0}};
dlyinc_gate <= {DQS_WIDTH{1'b0}};
if (cal4_dlyrst_gate) begin
if (SIM_ONLY == 0)
dlyrst_gate[count_gate] <= 1'b1;
else
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_gate_sim_dly_rst
dlyrst_gate[i] <= 1'b1;
end
end
if (cal4_dlyce_gate) begin
if (SIM_ONLY == 0) begin
dlyce_gate[count_gate] <= 1'b1;
dlyinc_gate[count_gate] <= cal4_dlyinc_gate;
end else begin
// if simulation, then calibrate only first gate
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_gate_sim_dly
dlyce_gate[i] <= 1'b1;
dlyinc_gate[i] <= cal4_dlyinc_gate;
end
end
end else if (DEBUG_EN != 0) begin
// DEBUG: allow user to vary IDELAY tap settings
if (dbg_idel_up_all || dbg_idel_down_all ||
dbg_sel_all_idel_gate) begin
for (x = 0; x < DQS_WIDTH; x = x + 1) begin: loop_dly_inc_gate
dlyce_gate[x] <= dbg_idel_up_all | dbg_idel_down_all |
dbg_idel_up_gate | dbg_idel_down_gate;
dlyinc_gate[x] <= dbg_idel_up_all | dbg_idel_up_gate;
end
end else begin
dlyce_gate <= {DQS_WIDTH{1'b0}};
dlyce_gate[dbg_sel_idel_gate] <= dbg_idel_up_gate |
dbg_idel_down_gate;
dlyinc_gate[dbg_sel_idel_gate] <= dbg_idel_up_gate;
end
end
end
//***************************************************************************
// signal to tell calibration state machines to wait and give IDELAY time to
// settle after it's value is changed (both time for IDELAY chain to settle,
// and for settled output to propagate through ISERDES). For general use: use
// for any calibration state machines that modify any IDELAY.
// Should give at least enough time for IDELAY output to settle (technically
// for V5, this should be "glitchless" when IDELAY taps are changed, so don't
// need any time here), and also time for new data to propagate through both
// ISERDES and the "RDD" MUX + associated pipelining
// For now, give very "generous" delay - doesn't really matter since only
// needed during calibration
//***************************************************************************
// determine if calibration polarity has changed
always @(posedge clkdiv)
cal2_rd_data_sel_r <= cal2_rd_data_sel;
assign cal2_rd_data_sel_edge = |(cal2_rd_data_sel ^ cal2_rd_data_sel_r);
// combine requests to modify any of the IDELAYs into one. Also when second
// stage capture "edge" polarity is changed (IDELAY isn't changed in this
// case, but use the same counter to stall cal logic)
assign dlyce_or = cal1_dlyce_dq |
cal2_dlyce_dqs |
cal2_rd_data_sel_edge |
cal4_dlyce_gate |
cal4_dlyrst_gate;
// SYN_NOTE: Can later recode to avoid combinational path
assign idel_set_wait = dlyce_or || (idel_set_cnt != IDEL_SET_VAL);
always @(posedge clkdiv)
if (rstdiv)
idel_set_cnt <= 4'b0000;
else if (dlyce_or)
idel_set_cnt <= 4'b0000;
else if (idel_set_cnt != IDEL_SET_VAL)
idel_set_cnt <= idel_set_cnt + 1;
// generate request to PHY_INIT logic to issue auto-refresh
// used by certain states to force prech/auto-refresh part way through
// calibration to avoid a tRAS violation (which will happen if that
// stage of calibration lasts long enough). This signal must meet the
// following requirements: (1) only transition from 0->1 when the refresh
// request is needed, (2) stay at 1 and only transition 1->0 when
// CALIB_REF_DONE is asserted
always @(posedge clkdiv)
if (rstdiv)
calib_ref_req <= 1'b0;
else
calib_ref_req <= cal1_ref_req | cal2_ref_req | cal4_ref_req;
// stage 1 calibration requests auto-refresh every 4 bits
generate
if (DQ_BITS < 2) begin: gen_cal1_refresh_dq_lte4
assign cal1_refresh = 1'b0;
end else begin: gen_cal1_refresh_dq_gt4
assign cal1_refresh = (next_count_dq[1:0] == 2'b00);
end
endgenerate
//***************************************************************************
// First stage calibration: DQ-DQS
// Definitions:
// edge: detected when varying IDELAY, and current capture data != prev
// capture data
// valid bit window: detected when current capture data == prev capture
// data for more than half the bit time
// starting conditions for DQS-DQ phase:
// case 1: when DQS starts somewhere in rising edge bit window, or
// on the right edge of the rising bit window.
// case 2: when DQS starts somewhere in falling edge bit window, or
// on the right edge of the falling bit window.
// Algorithm Description:
// 1. Increment DQ IDELAY until we find an edge.
// 2. While we're finding the first edge, note whether a valid bit window
// has been detected before we found an edge. If so, then figure out if
// this is the rising or falling bit window. If rising, then our starting
// DQS-DQ phase is case 1. If falling, then it's case 2. If don't detect
// a valid bit window, then we must have started on the edge of a window.
// Need to wait until later on to decide which case we are.
// - Store FIRST_EDGE IDELAY value
// 3. Now look for second edge.
// 4. While we're finding the second edge, note whether valid bit window
// is detected. If so, then use to, along with results from (2) to figure
// out what the starting case is. If in rising bit window, then we're in
// case 2. If falling, then case 1.
// - Store SECOND_EDGE IDELAY value
// NOTES:
// a. Finding two edges allows us to calculate the bit time (although
// not the "same" bit time polarity - need to investigate this
// more).
// b. If we run out of taps looking for the second edge, then the bit
// time must be too long (>= 2.5ns, and DQS-DQ starting phase must be
// case 1).
// 5. Calculate absolute amount to delay DQ as:
// If second edge found, and case 1:
// - DQ_IDELAY = FIRST_EDGE - 0.5*(SECOND_EDGE - FIRST_EDGE)
// If second edge found, and case 2:
// - DQ_IDELAY = SECOND_EDGE - 0.5*(SECOND_EDGE - FIRST_EDGE)
// If second edge not found, then need to make an approximation on
// how much to shift by (should be okay, because we have more timing
// margin):
// - DQ_IDELAY = FIRST_EDGE - 0.5 * (bit_time)
// NOTE: Does this account for either case 1 or case 2?????
// NOTE: It's also possible even when we find the second edge, that
// to instead just use half the bit time to subtract from either
// FIRST or SECOND_EDGE. Finding the actual bit time (which is
// what (SECOND_EDGE - FIRST_EDGE) is, is slightly more accurate,
// since it takes into account duty cycle distortion.
// 6. Repeat for each DQ in current DQS set.
//***************************************************************************
//*****************************************************************
// for first stage calibration - used for checking if DQS is aligned to the
// particular DQ, such that we're in the data valid window. Basically, this
// is one giant MUX.
// = [falling data, rising data]
// = [0, 1] = rising DQS aligned in proper (rising edge) bit window
// = [1, 0] = rising DQS aligned in wrong (falling edge) bit window
// = [0, 0], or [1,1] = in uncertain region between windows
//*****************************************************************
// SYN_NOTE: May have to split this up into multiple levels - MUX can get
// very wide - as wide as the data bus width
always @(posedge clkdiv)
cal1_data_chk_r <= {rd_data_fall_1x_r[next_count_dq],
rd_data_rise_1x_r[next_count_dq]};
//*****************************************************************
// determine when an edge has occurred - when either the current value
// is different from the previous latched value or when the DATA_CHK
// outputs are the same (rare, but indicates that we're at an edge)
// This is only valid when the IDELAY output and propagation of the
// data through the capture flops has had a chance to settle out.
//*****************************************************************
// write CAL1_DETECT_EDGE and CAL1_DETECT_STABLE in such a way that
// if X's are captured on the bus during functional simulation, that
// the logic will register this as an edge detected. Do this to allow
// use of this HDL with Denali memory models (Denali models drive DQ
// to X's on both edges of the data valid window to simulate jitter)
// This is only done for functional simulation purposes. **Should not**
// make the final synthesized logic more complicated, but it does make
// the HDL harder to understand b/c we have to "phrase" the logic
// slightly differently than when not worrying about X's
always @(*) begin
// no edge found if: (1) we have recorded prev edge, and rise
// data == fall data, (2) we haven't yet recorded prev edge, but
// rise/fall data is equal to either [0,1] or [1,0] (i.e. rise/fall
// data isn't either X's, or [0,0] or [1,1], which indicates we're
// in the middle of an edge, since normally rise != fall data for stg1)
if ((cal1_data_chk_last_valid &&
(cal1_data_chk_r == cal1_data_chk_last)) ||
(!cal1_data_chk_last_valid &&
((cal1_data_chk_r == 2'b01) || (cal1_data_chk_r == 2'b10))))
cal1_detect_edge = 1'b0;
else
cal1_detect_edge = 1'b1;
end
always @(*) begin
// assert if we've found a region where data valid window is stable
// over consecutive IDELAY taps, and either rise/fall = [1,0], or [0,1]
if ((cal1_data_chk_last_valid &&
(cal1_data_chk_r == cal1_data_chk_last)) &&
((cal1_data_chk_r == 2'b01) || (cal1_data_chk_r == 2'b10)))
cal1_detect_stable = 1'b1;
else
cal1_detect_stable = 1'b0;
end
//*****************************************************************
// Find valid window: keep track of how long we've been in the same data
// window. If it's been long enough, then declare that we've found a valid
// window. Also returns whether we found a rising or falling window (only
// valid when found_window is asserted)
//*****************************************************************
always @(posedge clkdiv) begin
if (cal1_state == CAL1_INIT) begin
cal1_window_cnt <= 4'b0000;
cal1_found_window <= 1'b0;
cal1_found_rising <= 1'bx;
end else if (!cal1_data_chk_last_valid) begin
// if we haven't stored a previous value of CAL1_DATA_CHK (or it got
// invalidated because we detected an edge, and are now looking for the
// second edge), then make sure FOUND_WINDOW deasserted on following
// clock edge (to avoid finding a false window immediately after finding
// an edge). Note that because of jitter, it's possible to not find an
// edge at the end of the IDELAY increment settling time, but to find an
// edge on the next clock cycle (e.g. during CAL1_FIND_FIRST_EDGE)
cal1_window_cnt <= 4'b0000;
cal1_found_window <= 1'b0;
cal1_found_rising <= 1'bx;
end else if (((cal1_state == CAL1_FIRST_EDGE_IDEL_WAIT) ||
(cal1_state == CAL1_SECOND_EDGE_IDEL_WAIT)) &&
!idel_set_wait) begin
// while finding the first and second edges, see if we can detect a
// stable bit window (occurs over MIN_WIN_SIZE number of taps). If
// so, then we're away from an edge, and can conclusively determine the
// starting DQS-DQ phase.
if (cal1_detect_stable) begin
cal1_window_cnt <= cal1_window_cnt + 1;
if (cal1_window_cnt == MIN_WIN_SIZE-1) begin
cal1_found_window <= 1'b1;
if (cal1_data_chk_r == 2'b01)
cal1_found_rising <= 1'b1;
else
cal1_found_rising <= 1'b0;
end
end else begin
// otherwise, we're not in a data valid window, reset the window
// counter, and indicate we're not currently in window. This should
// happen by design at least once after finding the first edge.
cal1_window_cnt <= 4'b0000;
cal1_found_window <= 1'b0;
cal1_found_rising <= 1'bx;
end
end
end
//*****************************************************************
// keep track of edge tap counts found, and whether we've
// incremented to the maximum number of taps allowed
//*****************************************************************
always @(posedge clkdiv)
if (cal1_state == CAL1_INIT) begin
cal1_idel_tap_limit_hit <= 1'b0;
cal1_idel_tap_cnt <= 6'b000000;
end else if (cal1_dlyce_dq) begin
if (cal1_dlyinc_dq) begin
cal1_idel_tap_cnt <= cal1_idel_tap_cnt + 1;
cal1_idel_tap_limit_hit <= (cal1_idel_tap_cnt == 6'b111110);
end else begin
cal1_idel_tap_cnt <= cal1_idel_tap_cnt - 1;
cal1_idel_tap_limit_hit <= 1'b0;
end
end
//*****************************************************************
// Pipeline for better timing - amount to decrement by if second
// edge not found
//*****************************************************************
// if only one edge found (possible for low frequencies), then:
// 1. Assume starting DQS-DQ phase has DQS in DQ window (aka "case 1")
// 2. We have to decrement by (63 - first_edge_tap_cnt) + (BIT_TIME_TAPS/2)
// (i.e. decrement by 63-first_edge_tap_cnt to get to right edge of
// DQ window. Then decrement again by (BIT_TIME_TAPS/2) to get to center
// of DQ window.
// 3. Clamp the above value at 63 to ensure we don't underflow IDELAY
// (note: clamping happens in the CAL1 state machine)
always @(posedge clkdiv)
cal1_low_freq_idel_dec
<= (7'b0111111 - {1'b0, cal1_first_edge_tap_cnt}) +
(BIT_TIME_TAPS/2);
//*****************************************************************
// Keep track of max taps used during stage 1, use this to limit
// the number of taps that can be used in stage 2
//*****************************************************************
always @(posedge clkdiv)
if (rstdiv) begin
cal1_idel_max_tap <= 6'b000000;
cal1_idel_max_tap_we <= 1'b0;
end else begin
// pipeline latch enable for CAL1_IDEL_MAX_TAP - we have plenty
// of time, tap count gets updated, then dead cycles waiting for
// IDELAY output to settle
cal1_idel_max_tap_we <= (cal1_idel_max_tap < cal1_idel_tap_cnt);
// record maximum # of taps used for stg 1 cal
if ((cal1_state == CAL1_DONE) && cal1_idel_max_tap_we)
cal1_idel_max_tap <= cal1_idel_tap_cnt;
end
//*****************************************************************
always @(posedge clkdiv)
if (rstdiv) begin
calib_done[0] <= 1'b0;
calib_done_tmp[0] <= 1'bx;
calib_err[0] <= 1'b0;
count_dq <= {DQ_BITS{1'b0}};
next_count_dq <= {DQ_BITS{1'b0}};
cal1_bit_time_tap_cnt <= 6'bxxxxxx;
cal1_data_chk_last <= 2'bxx;
cal1_data_chk_last_valid <= 1'bx;
cal1_dlyce_dq <= 1'b0;
cal1_dlyinc_dq <= 1'b0;
cal1_dqs_dq_init_phase <= 1'bx;
cal1_first_edge_done <= 1'bx;
cal1_found_second_edge <= 1'bx;
cal1_first_edge_tap_cnt <= 6'bxxxxxx;
cal1_idel_dec_cnt <= 7'bxxxxxxx;
cal1_idel_inc_cnt <= 6'bxxxxxx;
cal1_ref_req <= 1'b0;
cal1_state <= CAL1_IDLE;
end else begin
// default values for all "pulse" outputs
cal1_ref_req <= 1'b0;
cal1_dlyce_dq <= 1'b0;
cal1_dlyinc_dq <= 1'b0;
case (cal1_state)
CAL1_IDLE: begin
count_dq <= {DQ_BITS{1'b0}};
next_count_dq <= {DQ_BITS{1'b0}};
if (calib_start[0]) begin
calib_done[0] <= 1'b0;
calib_done_tmp[0] <= 1'b0;
cal1_state <= CAL1_INIT;
end
end
CAL1_INIT: begin
cal1_data_chk_last_valid <= 1'b0;
cal1_found_second_edge <= 1'b0;
cal1_dqs_dq_init_phase <= 1'b0;
cal1_idel_inc_cnt <= 6'b000000;
cal1_state <= CAL1_INC_IDEL;
end
// increment DQ IDELAY so that either: (1) DQS starts somewhere in
// first rising DQ window, or (2) DQS starts in first falling DQ
// window. The amount to shift is frequency dependent (and is either
// precalculated by MIG or possibly adjusted by the user)
CAL1_INC_IDEL:
if ((cal1_idel_inc_cnt == DQ_IDEL_INIT) && !idel_set_wait) begin
cal1_state <= CAL1_FIND_FIRST_EDGE;
end else if (cal1_idel_inc_cnt != DQ_IDEL_INIT) begin
cal1_idel_inc_cnt <= cal1_idel_inc_cnt + 1;
cal1_dlyce_dq <= 1'b1;
cal1_dlyinc_dq <= 1'b1;
end
// look for first edge
CAL1_FIND_FIRST_EDGE: begin
// Determine DQS-DQ phase if we can detect enough of a valid window
if (cal1_found_window)
cal1_dqs_dq_init_phase <= ~cal1_found_rising;
// find first edge - if found then record position
if (cal1_detect_edge) begin
cal1_state <= CAL1_FOUND_FIRST_EDGE_WAIT;
cal1_first_edge_done <= 1'b0;
cal1_first_edge_tap_cnt <= cal1_idel_tap_cnt;
cal1_data_chk_last_valid <= 1'b0;
end else begin
// otherwise, store the current value of DATA_CHK, increment
// DQ IDELAY, and compare again
cal1_state <= CAL1_FIRST_EDGE_IDEL_WAIT;
cal1_data_chk_last <= cal1_data_chk_r;
// avoid comparing against DATA_CHK_LAST for previous iteration
cal1_data_chk_last_valid <= 1'b1;
cal1_dlyce_dq <= 1'b1;
cal1_dlyinc_dq <= 1'b1;
end
end
// wait for DQ IDELAY to settle
CAL1_FIRST_EDGE_IDEL_WAIT:
if (!idel_set_wait)
cal1_state <= CAL1_FIND_FIRST_EDGE;
// delay state between finding first edge and looking for second
// edge. Necessary in order to invalidate CAL1_FOUND_WINDOW before
// starting to look for second edge
CAL1_FOUND_FIRST_EDGE_WAIT:
cal1_state <= CAL1_FIND_SECOND_EDGE;
// Try and find second edge
CAL1_FIND_SECOND_EDGE: begin
// When looking for 2nd edge, first make sure data stabilized (by
// detecting valid data window) - needed to avoid false edges
if (cal1_found_window) begin
cal1_first_edge_done <= 1'b1;
cal1_dqs_dq_init_phase <= cal1_found_rising;
end
// exit if run out of taps to increment
if (cal1_idel_tap_limit_hit)
cal1_state <= CAL1_CALC_IDEL;
else begin
// found second edge, record the current edge count
if (cal1_first_edge_done && cal1_detect_edge) begin
cal1_state <= CAL1_CALC_IDEL;
cal1_found_second_edge <= 1'b1;
cal1_bit_time_tap_cnt <= cal1_idel_tap_cnt -
cal1_first_edge_tap_cnt + 1;
end else begin
cal1_state <= CAL1_SECOND_EDGE_IDEL_WAIT;
cal1_data_chk_last <= cal1_data_chk_r;
cal1_data_chk_last_valid <= 1'b1;
cal1_dlyce_dq <= 1'b1;
cal1_dlyinc_dq <= 1'b1;
end
end
end
// wait for DQ IDELAY to settle, then store ISERDES output
CAL1_SECOND_EDGE_IDEL_WAIT:
if (!idel_set_wait)
cal1_state <= CAL1_FIND_SECOND_EDGE;
// pipeline delay state to calculate amount to decrement DQ IDELAY
// NOTE: We're calculating the amount to decrement by, not the
// absolute setting for DQ IDELAY
CAL1_CALC_IDEL: begin
// if two edges found
if (cal1_found_second_edge)
// case 1: DQS was in DQ window to start with. First edge found
// corresponds to left edge of DQ rising window. Backup by 1.5*BT
// NOTE: In this particular case, it is possible to decrement
// "below 0" in the case where DQS delay is less than 0.5*BT,
// need to limit decrement to prevent IDELAY tap underflow
if (!cal1_dqs_dq_init_phase)
cal1_idel_dec_cnt <= {1'b0, cal1_bit_time_tap_cnt} +
{1'b0, (cal1_bit_time_tap_cnt >> 1)};
// case 2: DQS was in wrong DQ window (in DQ falling window).
// First edge found is right edge of DQ rising window. Second
// edge is left edge of DQ rising window. Backup by 0.5*BT
else
cal1_idel_dec_cnt <= {1'b0, (cal1_bit_time_tap_cnt >> 1)};
// if only one edge found - assume will always be case 1 - DQS in
// DQS window. Case 2 only possible if path delay on DQS > 5ns
else
cal1_idel_dec_cnt <= cal1_low_freq_idel_dec;
cal1_state <= CAL1_DEC_IDEL;
end
// decrement DQ IDELAY for final adjustment
CAL1_DEC_IDEL:
// once adjustment is complete, we're done with calibration for
// this DQ, now return to IDLE state and repeat for next DQ
// Add underflow protection for case of 2 edges found and DQS
// starting in DQ window (see comments for above state) - note we
// have to take into account delayed value of CAL1_IDEL_TAP_CNT -
// gets updated one clock cycle after CAL1_DLYCE/INC_DQ
if ((cal1_idel_dec_cnt == 7'b0000000) ||
(cal1_dlyce_dq && (cal1_idel_tap_cnt == 6'b000001))) begin
cal1_state <= CAL1_DONE;
// stop when all DQ's calibrated, or DQ[0] cal'ed (for sim)
if ((count_dq == DQ_WIDTH-1) || (SIM_ONLY != 0))
calib_done_tmp[0] <= 1'b1;
else
// need for VHDL simulation to prevent out-of-index error
next_count_dq <= count_dq + 1;
end else begin
// keep decrementing until final tap count reached
cal1_idel_dec_cnt <= cal1_idel_dec_cnt - 1;
cal1_dlyce_dq <= 1'b1;
cal1_dlyinc_dq <= 1'b0;
end
// delay state to allow count_dq and DATA_CHK to point to the next
// DQ bit (allows us to potentially begin checking for an edge on
// next DQ right away).
CAL1_DONE:
if (!idel_set_wait) begin
count_dq <= next_count_dq;
if (calib_done_tmp[0]) begin
calib_done[0] <= 1'b1;
cal1_state <= CAL1_IDLE;
end else begin
// request auto-refresh after every 8-bits calibrated to
// avoid tRAS violation
if (cal1_refresh) begin
cal1_ref_req <= 1'b1;
if (calib_ref_done)
cal1_state <= CAL1_INIT;
end else
// if no need this time for refresh, proceed to next bit
cal1_state <= CAL1_INIT;
end
end
endcase
end
//***************************************************************************
// Second stage calibration: DQS-FPGA Clock
// Algorithm Description:
// 1. Assumes a training pattern that will produce a pattern oscillating at
// half the core clock frequency each on rise and fall outputs, and such
// that rise and fall outputs are 180 degrees out of phase from each
// other. Note that since the calibration logic runs at half the speed
// of the interface, expect that data sampled with the slow clock always
// to be constant (either always = 1, or = 0, and rise data != fall data)
// unless we cross the edge of the data valid window
// 2. Start by setting RD_DATA_SEL = 0. This selects the rising capture data
// sync'ed to rising edge of core clock, and falling edge data sync'ed
// to falling edge of core clock
// 3. Start looking for an edge. An edge is defined as either: (1) a
// change in capture value or (2) an invalid capture value (e.g. rising
// data != falling data for that same clock cycle).
// 4. If an edge is found, go to step (6). If edge hasn't been found, then
// set RD_DATA_SEL = 1, and try again.
// 5. If no edge is found, then increment IDELAY and return to step (3)
// 6. If an edge if found, then invert RD_DATA_SEL - this shifts the
// capture point 180 degrees from the edge of the window (minus duty
// cycle distortion, delay skew between rising/falling edge capture
// paths, etc.)
// 7. If no edge is found by CAL2_IDEL_TAP_LIMIT (= 63 - # taps used for
// stage 1 calibration), then decrement IDELAY (without reinverting
// RD_DATA_SEL) by CAL2_IDEL_TAP_LIMIT/2. This guarantees we at least
// have CAL2_IDEL_TAP_LIMIT/2 of slack both before and after the
// capture point (not optimal, but best we can do not having found an
// of the window). This happens only for very low frequencies.
// 8. Repeat for each DQS group.
// NOTE: Step 6 is not optimal. A better (and perhaps more complicated)
// algorithm might be to find both edges of the data valid window (using
// the same polarity of RD_DATA_SEL), and then decrement to the midpoint.
//***************************************************************************
// RD_DATA_SEL should be tagged with FROM-TO (multi-cycle) constraint in
// UCF file to relax timing. This net is "pseudo-static" (after value is
// changed, FSM waits number of cycles before using the output).
// Note that we are adding one clock cycle of delay (to isolate it from
// the other logic CAL2_RD_DATA_SEL feeds), make sure FSM waits long
// enough to compensate (by default it does, it waits a few cycles more
// than minimum # of clock cycles)
genvar rd_i;
generate
for (rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i+1) begin: gen_rd_data_sel
FDRSE u_ff_rd_data_sel
(
.Q (rd_data_sel[rd_i]),
.C (clkdiv),
.CE (1'b1),
.D (cal2_rd_data_sel[rd_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
//*****************************************************************
// Max number of taps used for stg2 cal dependent on number of taps
// used for stg1 (give priority to stg1 cal - let it use as many
// taps as it needs - the remainder of the IDELAY taps can be used
// by stg2)
//*****************************************************************
always @(posedge clkdiv)
cal2_idel_tap_limit <= 6'b111111 - cal1_idel_max_tap;
//*****************************************************************
// second stage calibration uses readback pattern of "1100" (i.e.
// 1st rising = 1, 1st falling = 1, 2nd rising = 0, 2nd falling = 0)
// only look at the first bit of each DQS group
//*****************************************************************
// deasserted when captured data has changed since IDELAY was
// incremented, or when we're right on the edge (i.e. rise data =
// fall data).
assign cal2_detect_edge =
((((rdd_rise_q1 != cal2_rd_data_rise_last_pos) ||
(rdd_fall_q1 != cal2_rd_data_fall_last_pos)) &&
cal2_rd_data_last_valid_pos && (!cal2_curr_sel)) ||
(((rdd_rise_q1 != cal2_rd_data_rise_last_neg) ||
(rdd_fall_q1 != cal2_rd_data_fall_last_neg)) &&
cal2_rd_data_last_valid_neg && (cal2_curr_sel)) ||
(rdd_rise_q1 != rdd_fall_q1));
//*****************************************************************
// keep track of edge tap counts found, and whether we've
// incremented to the maximum number of taps allowed
// NOTE: Assume stage 2 cal always increments the tap count (never
// decrements) when searching for edge of the data valid window
//*****************************************************************
always @(posedge clkdiv)
if (cal2_state == CAL2_INIT) begin
cal2_idel_tap_limit_hit <= 1'b0;
cal2_idel_tap_cnt <= 6'b000000;
end else if (cal2_dlyce_dqs) begin
cal2_idel_tap_cnt <= cal2_idel_tap_cnt + 1;
cal2_idel_tap_limit_hit <= (cal2_idel_tap_cnt ==
cal2_idel_tap_limit - 1);
end
//*****************************************************************
always @(posedge clkdiv)
if (rstdiv) begin
calib_done[1] <= 1'b0;
calib_done_tmp[1] <= 1'bx;
calib_err[1] <= 1'b0;
count_dqs <= 'b0;
next_count_dqs <= 'b0;
cal2_dlyce_dqs <= 1'b0;
cal2_dlyinc_dqs <= 1'b0;
cal2_idel_dec_cnt <= 6'bxxxxxx;
cal2_rd_data_last_valid_neg <= 1'bx;
cal2_rd_data_last_valid_pos <= 1'bx;
cal2_rd_data_sel <= 'b0;
cal2_ref_req <= 1'b0;
cal2_state <= CAL2_IDLE;
end else begin
cal2_ref_req <= 1'b0;
cal2_dlyce_dqs <= 1'b0;
cal2_dlyinc_dqs <= 1'b0;
case (cal2_state)
CAL2_IDLE: begin
count_dqs <= 'b0;
next_count_dqs <= 'b0;
if (calib_start[1]) begin
cal2_rd_data_sel <= {DQS_WIDTH{1'b0}};
calib_done[1] <= 1'b0;
calib_done_tmp[1] <= 1'b0;
cal2_state <= CAL2_INIT;
end
end
// Pass through this state every time we calibrate a new DQS group
CAL2_INIT: begin
cal2_curr_sel <= 1'b0;
cal2_rd_data_last_valid_neg <= 1'b0;
cal2_rd_data_last_valid_pos <= 1'b0;
cal2_state <= CAL2_INIT_IDEL_WAIT;
end
// Stall state only used if calibration run more than once. Can take
// this state out if design never runs calibration more than once.
// We need this state to give time for MUX'ed data to settle after
// resetting RD_DATA_SEL
CAL2_INIT_IDEL_WAIT:
if (!idel_set_wait)
cal2_state <= CAL2_FIND_EDGE_POS;
// Look for an edge - first check "positive-edge" stage 2 capture
CAL2_FIND_EDGE_POS: begin
// if found an edge, then switch to the opposite edge stage 2
// capture and we're done - no need to decrement the tap count,
// since switching to the opposite edge will shift the capture
// point by 180 degrees
if (cal2_detect_edge) begin
cal2_curr_sel <= 1'b1;
cal2_state <= CAL2_DONE;
// set all DQS groups to be the same for simulation
if (SIM_ONLY != 0)
cal2_rd_data_sel <= {DQS_WIDTH{1'b1}};
else
cal2_rd_data_sel[count_dqs] <= 1'b1;
if ((count_dqs == DQS_WIDTH-1) || (SIM_ONLY != 0))
calib_done_tmp[1] <= 1'b1;
else
// MIG 2.1: Fix for simulation out-of-bounds error when
// SIM_ONLY=0, and DQS_WIDTH=(power of 2) (needed for VHDL)
next_count_dqs <= count_dqs + 1;
end else begin
// otherwise, invert polarity of stage 2 capture and look for
// an edge with opposite capture clock polarity
cal2_curr_sel <= 1'b1;
cal2_rd_data_sel[count_dqs] <= 1'b1;
cal2_state <= CAL2_FIND_EDGE_IDEL_WAIT_POS;
cal2_rd_data_rise_last_pos <= rdd_rise_q1;
cal2_rd_data_fall_last_pos <= rdd_fall_q1;
cal2_rd_data_last_valid_pos <= 1'b1;
end
end
// Give time to switch from positive-edge to negative-edge second
// stage capture (need time for data to filter though pipe stages)
CAL2_FIND_EDGE_IDEL_WAIT_POS:
if (!idel_set_wait)
cal2_state <= CAL2_FIND_EDGE_NEG;
// Look for an edge - check "negative-edge" stage 2 capture
CAL2_FIND_EDGE_NEG:
if (cal2_detect_edge) begin
cal2_curr_sel <= 1'b0;
cal2_state <= CAL2_DONE;
// set all DQS groups to be the same for simulation
if (SIM_ONLY != 0)
cal2_rd_data_sel <= {DQS_WIDTH{1'b0}};
else
cal2_rd_data_sel[count_dqs] <= 1'b0;
if ((count_dqs == DQS_WIDTH-1) || (SIM_ONLY != 0))
calib_done_tmp[1] <= 1'b1;
else
// MIG 2.1: Fix for simulation out-of-bounds error when
// SIM_ONLY=0, and DQS_WIDTH=(power of 2) (needed for VHDL)
next_count_dqs <= count_dqs + 1;
end else if (cal2_idel_tap_limit_hit) begin
// otherwise, if we've run out of taps, then immediately
// backoff by half # of taps used - that's our best estimate
// for optimal calibration point. Doesn't matter whether which
// polarity we're using for capture (we don't know which one is
// best to use)
cal2_idel_dec_cnt <= {1'b0, cal2_idel_tap_limit[5:1]};
cal2_state <= CAL2_DEC_IDEL;
if ((count_dqs == DQS_WIDTH-1) || (SIM_ONLY != 0))
calib_done_tmp[1] <= 1'b1;
else
// MIG 2.1: Fix for simulation out-of-bounds error when
// SIM_ONLY=0, and DQS_WIDTH=(power of 2) (needed for VHDL)
next_count_dqs <= count_dqs + 1;
end else begin
// otherwise, increment IDELAY, and start looking for edge again
cal2_curr_sel <= 1'b0;
cal2_rd_data_sel[count_dqs] <= 1'b0;
cal2_state <= CAL2_FIND_EDGE_IDEL_WAIT_NEG;
cal2_rd_data_rise_last_neg <= rdd_rise_q1;
cal2_rd_data_fall_last_neg <= rdd_fall_q1;
cal2_rd_data_last_valid_neg <= 1'b1;
cal2_dlyce_dqs <= 1'b1;
cal2_dlyinc_dqs <= 1'b1;
end
CAL2_FIND_EDGE_IDEL_WAIT_NEG:
if (!idel_set_wait)
cal2_state <= CAL2_FIND_EDGE_POS;
// if no edge found, then decrement by half # of taps used
CAL2_DEC_IDEL: begin
if (cal2_idel_dec_cnt == 6'b000000)
cal2_state <= CAL2_DONE;
else begin
cal2_idel_dec_cnt <= cal2_idel_dec_cnt - 1;
cal2_dlyce_dqs <= 1'b1;
cal2_dlyinc_dqs <= 1'b0;
end
end
// delay state to allow count_dqs and ISERDES data to point to next
// DQ bit (DQS group) before going to INIT
CAL2_DONE:
if (!idel_set_wait) begin
count_dqs <= next_count_dqs;
if (calib_done_tmp[1]) begin
calib_done[1] <= 1'b1;
cal2_state <= CAL2_IDLE;
end else begin
// request auto-refresh after every DQS group calibrated to
// avoid tRAS violation
cal2_ref_req <= 1'b1;
if (calib_ref_done)
cal2_state <= CAL2_INIT;
end
end
endcase
end
//***************************************************************************
// Stage 3 calibration: Read Enable
// Description:
// read enable calibration determines the "round-trip" time (in # of CLK0
// cycles) between when a read command is issued by the controller, and
// when the corresponding read data is synchronized by into the CLK0 domain
// this is a long delay chain to delay read enable signal from controller/
// initialization logic (i.e. this is used for both initialization and
// during normal controller operation). Stage 3 calibration logic decides
// which delayed version is appropriate to use (which is affected by the
// round trip delay of DQ/DQS) as a "valid" signal to tell rest of logic
// when the captured data output from ISERDES is valid.
//***************************************************************************
//*****************************************************************
// Delay chains: Use shift registers
// Two sets of delay chains are used:
// 1. One to delay RDEN from PHY_INIT module for calibration
// purposes (delay required for RDEN for calibration is different
// than during normal operation)
// 2. One per DQS group to delay RDEN from controller for normal
// operation - the value to delay for each DQS group can be different
// as is determined during calibration
//*****************************************************************
//*****************************************************************
// First delay chain, use only for calibration
// input = asserted on rising edge of RDEN from PHY_INIT module
//*****************************************************************
always @(posedge clk) begin
ctrl_rden_r <= ctrl_rden;
phy_init_rden_r <= phy_init_rden;
phy_init_rden_r1 <= phy_init_rden_r;
calib_rden_edge_r <= phy_init_rden_r & ~phy_init_rden_r1;
end
// Calibration shift register used for both Stage 3 and Stage 4 cal
// (not strictly necessary for stage 4, but use as an additional check
// to make sure we're checking for correct data on the right clock cycle)
always @(posedge clkdiv)
if (!calib_done[2])
calib_rden_srl_a <= cal3_rden_srl_a;
else
calib_rden_srl_a <= cal4_rden_srl_a;
// Flops for targetting of multi-cycle path in UCF
genvar cal_rden_ff_i;
generate
for (cal_rden_ff_i = 0; cal_rden_ff_i < 5;
cal_rden_ff_i = cal_rden_ff_i+1) begin: gen_cal_rden_dly
FDRSE u_ff_cal_rden_dly
(
.Q (calib_rden_srl_a_r[cal_rden_ff_i]),
.C (clkdiv),
.CE (1'b1),
.D (calib_rden_srl_a[cal_rden_ff_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
SRLC32E u_calib_rden_srl
(
.Q (calib_rden_srl_out),
.Q31 (),
.A (calib_rden_srl_a_r),
.CE (1'b1),
.CLK (clk),
.D (calib_rden_edge_r)
);
FDRSE u_calib_rden_srl_out_r
(
.Q (calib_rden_srl_out_r),
.C (clk),
.CE (1'b1),
.D (calib_rden_srl_out),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */;
// convert to CLKDIV domain. Two version are generated because we need
// to be able to tell exactly which fast (clk) clock cycle the read
// enable was asserted in. Only one of CALIB_DATA_VALID or
// CALIB_DATA_VALID_STGD will be asserted for any given shift value
always @(posedge clk)
calib_rden_srl_out_r1 <= calib_rden_srl_out_r;
always @(posedge clkdiv) begin
calib_rden_valid <= calib_rden_srl_out_r;
calib_rden_valid_stgd <= calib_rden_srl_out_r1;
end
//*****************************************************************
// Second set of delays chain, use for normal reads
// input = RDEN from controller
//*****************************************************************
// Flops for targetting of multi-cycle path in UCF
genvar rden_ff_i;
generate
for (rden_ff_i = 0; rden_ff_i < 5*DQS_WIDTH;
rden_ff_i = rden_ff_i+1) begin: gen_rden_dly
FDRSE u_ff_rden_dly
(
.Q (rden_dly_r[rden_ff_i]),
.C (clkdiv),
.CE (1'b1),
.D (rden_dly[rden_ff_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
// NOTE: Comment this section explaining purpose of SRL's
genvar rden_i;
generate
for (rden_i = 0; rden_i < DQS_WIDTH; rden_i = rden_i + 1) begin: gen_rden
SRLC32E u_rden_srl
(
.Q (rden_srl_out[rden_i]),
.Q31 (),
.A ({rden_dly_r[(rden_i*5)+4],
rden_dly_r[(rden_i*5)+3],
rden_dly_r[(rden_i*5)+2],
rden_dly_r[(rden_i*5)+1],
rden_dly_r[(rden_i*5)]}),
.CE (1'b1),
.CLK (clk),
.D (ctrl_rden_r)
);
FDRSE u_calib_rden_r
(
.Q (calib_rden[rden_i]),
.C (clk),
.CE (1'b1),
.D (rden_srl_out[rden_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */;
end
endgenerate
//*****************************************************************
// indicates that current received data is the correct pattern. Check both
// rising and falling data for first DQ in each DQS group. Note that
// we're checking using a pipelined version of read data, so need to take
// this inherent delay into account in determining final read valid delay
// Data is written to the memory in the following order (first -> last):
// 0x1, 0xE, 0xE, 0x1, 0x1, 0xE, 0x1, 0xE
// Looking at the two LSb bits, expect data in sequence (in binary):
// bit[0]: 1, 0, 0, 1, 0, 1, 0, 1
// bit[1]: 0, 1, 1, 0, 1, 0, 1, 0
// Check for the presence of the first 7 words, and compensate read valid
// delay accordingly. Don't check last falling edge data, it may be
// corrupted by the DQS tri-state glitch at end of read postamble
// (glitch protection not yet active until stage 4 cal)
//*****************************************************************
always @(posedge clkdiv) begin
rdd_rise_q1_r <= rdd_rise_q1;
rdd_fall_q1_r <= rdd_fall_q1;
rdd_rise_q2_r <= rdd_rise_q2;
rdd_fall_q2_r <= rdd_fall_q2;
rdd_rise_q1_r1 <= rdd_rise_q1_r;
rdd_fall_q1_r1 <= rdd_fall_q1_r;
// MIG 3.3: Added comparison for second bit in DQS group for stage 3 cal
rdd_rise_q1_bit1_r <= rdd_rise_q1_bit1;
rdd_fall_q1_bit1_r <= rdd_fall_q1_bit1;
rdd_rise_q2_bit1_r <= rdd_rise_q2_bit1;
rdd_fall_q2_bit1_r <= rdd_fall_q2_bit1;
rdd_rise_q1_bit1_r1 <= rdd_rise_q1_bit1_r;
rdd_fall_q1_bit1_r1 <= rdd_fall_q1_bit1_r;
end
always @(posedge clkdiv) begin
// For the following sequence from memory:
// rise[0], fall[0], rise[1], fall[1]
// if data is aligned out of fabric ISERDES:
// RDD_RISE_Q2 = rise[0]
// RDD_FALL_Q2 = fall[0]
// RDD_RISE_Q1 = rise[1]
// RDD_FALL_Q1 = fall[1]
cal3_data_match <= ((rdd_rise_q2_r == 1) &&
(rdd_fall_q2_r == 0) &&
(rdd_rise_q1_r == 0) &&
(rdd_fall_q1_r == 1) &&
(rdd_rise_q2 == 0) &&
(rdd_fall_q2 == 1) &&
(rdd_rise_q1 == 0) &&
(rdd_rise_q2_bit1_r == 0) &&
(rdd_fall_q2_bit1_r == 1) &&
(rdd_rise_q1_bit1_r == 1) &&
(rdd_fall_q1_bit1_r == 0) &&
(rdd_rise_q2_bit1 == 1) &&
(rdd_fall_q2_bit1 == 0) &&
(rdd_rise_q1_bit1 == 1));
// if data is staggered out of fabric ISERDES:
// RDD_RISE_Q1_R = rise[0]
// RDD_FALL_Q1_R = fall[0]
// RDD_RISE_Q2 = rise[1]
// RDD_FALL_Q2 = fall[1]
cal3_data_match_stgd <= ((rdd_rise_q1_r1 == 1) &&
(rdd_fall_q1_r1 == 0) &&
(rdd_rise_q2_r == 0) &&
(rdd_fall_q2_r == 1) &&
(rdd_rise_q1_r == 0) &&
(rdd_fall_q1_r == 1) &&
(rdd_rise_q2 == 0) &&
(rdd_rise_q1_bit1_r1 == 0) &&
(rdd_fall_q1_bit1_r1 == 1) &&
(rdd_rise_q2_bit1_r == 1) &&
(rdd_fall_q2_bit1_r == 0) &&
(rdd_rise_q1_bit1_r == 1) &&
(rdd_fall_q1_bit1_r == 0) &&
(rdd_rise_q2_bit1 == 1));
end
assign cal3_rden_dly = cal3_rden_srl_a - CAL3_RDEN_SRL_DLY_DELTA;
assign cal3_data_valid = (calib_rden_valid | calib_rden_valid_stgd);
assign cal3_match_found
= ((calib_rden_valid && cal3_data_match) ||
(calib_rden_valid_stgd && cal3_data_match_stgd));
// when calibrating, check to see which clock cycle (after the read is
// issued) does the expected data pattern arrive. Record this result
// NOTE: Can add error checking here in case valid data not found on any
// of the available pipeline stages
always @(posedge clkdiv) begin
if (rstdiv) begin
cal3_rden_srl_a <= 5'bxxxxx;
cal3_state <= CAL3_IDLE;
calib_done[2] <= 1'b0;
calib_err_2[0] <= 1'b0;
count_rden <= {DQS_WIDTH{1'b0}};
rden_dly <= {5*DQS_WIDTH{1'b0}};
end else begin
case (cal3_state)
CAL3_IDLE: begin
count_rden <= {DQS_WIDTH{1'b0}};
if (calib_start[2]) begin
calib_done[2] <= 1'b0;
cal3_state <= CAL3_INIT;
end
end
CAL3_INIT: begin
cal3_rden_srl_a <= RDEN_BASE_DELAY;
// let SRL pipe clear after loading initial shift value
cal3_state <= CAL3_RDEN_PIPE_CLR_WAIT;
end
CAL3_DETECT:
if (cal3_data_valid)
// if match found at the correct clock cycle
if (cal3_match_found) begin
// For simulation, load SRL addresses for all DQS with same value
if (SIM_ONLY != 0) begin
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_sim_rden_dly
rden_dly[(i*5)] <= cal3_rden_dly[0];
rden_dly[(i*5)+1] <= cal3_rden_dly[1];
rden_dly[(i*5)+2] <= cal3_rden_dly[2];
rden_dly[(i*5)+3] <= cal3_rden_dly[3];
rden_dly[(i*5)+4] <= cal3_rden_dly[4];
end
end else begin
rden_dly[(count_rden*5)] <= cal3_rden_dly[0];
rden_dly[(count_rden*5)+1] <= cal3_rden_dly[1];
rden_dly[(count_rden*5)+2] <= cal3_rden_dly[2];
rden_dly[(count_rden*5)+3] <= cal3_rden_dly[3];
rden_dly[(count_rden*5)+4] <= cal3_rden_dly[4];
end
// Use for stage 4 calibration
calib_rden_dly[(count_rden*5)] <= cal3_rden_srl_a[0];
calib_rden_dly[(count_rden*5)+1] <= cal3_rden_srl_a[1];
calib_rden_dly[(count_rden*5)+2] <= cal3_rden_srl_a[2];
calib_rden_dly[(count_rden*5)+3] <= cal3_rden_srl_a[3];
calib_rden_dly[(count_rden*5)+4] <= cal3_rden_srl_a[4];
cal3_state <= CAL3_DONE;
end else begin
// If we run out of stages to shift, without finding correct
// result, the stop and assert error
if (cal3_rden_srl_a == 5'b11111) begin
calib_err_2[0] <= 1'b1;
cal3_state <= CAL3_IDLE;
end else begin
// otherwise, increase the shift value and try again
cal3_rden_srl_a <= cal3_rden_srl_a + 1;
cal3_state <= CAL3_RDEN_PIPE_CLR_WAIT;
end
end
// give additional time for RDEN_R pipe to clear from effects of
// previous pipeline or IDELAY tap change
CAL3_RDEN_PIPE_CLR_WAIT:
if (calib_rden_pipe_cnt == 5'b00000)
cal3_state <= CAL3_DETECT;
CAL3_DONE: begin
if ((count_rden == DQS_WIDTH-1) || (SIM_ONLY != 0)) begin
calib_done[2] <= 1'b1;
cal3_state <= CAL3_IDLE;
end else begin
count_rden <= count_rden + 1;
cal3_state <= CAL3_INIT;
end
end
endcase
end
end
//*****************************************************************
// Last part of stage 3 calibration - compensate for differences
// in delay between different DQS groups. Assume that in the worst
// case, DQS groups can only differ by one clock cycle. Data for
// certain DQS groups must be delayed by one clock cycle.
// NOTE: May need to increase allowable variation to greater than
// one clock cycle in certain customer designs.
// Algorithm is:
// 1. Record shift delay value for DQS[0]
// 2. Compare each DQS[x] delay value to that of DQS[0]:
// - If different, than record this fact (RDEN_MUX)
// - If greater than DQS[0], set RDEN_INC. Assume greater by
// one clock cycle only - this is a key assumption, assume no
// more than a one clock cycle variation.
// - If less than DQS[0], set RDEN_DEC
// 3. After calibration is complete, set control for DQS group
// delay (CALIB_RDEN_SEL):
// - If RDEN_DEC = 1, then assume that DQS[0] is the lowest
// delay (and at least one other DQS group has a higher
// delay).
// - If RDEN_INC = 1, then assume that DQS[0] is the highest
// delay (and that all other DQS groups have the same or
// lower delay).
// - If both RDEN_INC and RDEN_DEC = 1, then flag error
// (variation is too high for this algorithm to handle)
//*****************************************************************
always @(posedge clkdiv) begin
if (rstdiv) begin
calib_err_2[1] <= 1'b0;
calib_rden_sel <= {DQS_WIDTH{1'bx}};
rden_dec <= 1'b0;
rden_dly_0 <= 5'bxxxxx;
rden_inc <= 1'b0;
rden_mux <= {DQS_WIDTH{1'b0}};
end else begin
// if a match if found, then store the value of rden_dly
if (!calib_done[2]) begin
if ((cal3_state == CAL3_DETECT) && cal3_match_found) begin
// store the value for DQS[0] as a reference
if (count_rden == 0) begin
// for simulation, RDEN calibration only happens for DQS[0]
// set RDEN_MUX for all DQS groups to be the same as DQS[0]
if (SIM_ONLY != 0)
rden_mux <= {DQS_WIDTH{1'b0}};
else begin
// otherwise, load values for DQS[0]
rden_dly_0 <= cal3_rden_srl_a;
rden_mux[0] <= 1'b0;
end
end else if (SIM_ONLY == 0) begin
// for all other DQS groups, compare RDEN_DLY delay value with
// that of DQS[0]
if (rden_dly_0 != cal3_rden_srl_a) begin
// record that current DQS group has a different delay
// than DQS[0] (the "reference" DQS group)
rden_mux[count_rden] <= 1'b1;
if (rden_dly_0 > cal3_rden_srl_a)
rden_inc <= 1'b1;
else if (rden_dly_0 < cal3_rden_srl_a)
rden_dec <= 1'b1;
// otherwise, if current DQS group has same delay as DQS[0],
// then rden_mux[count_rden] remains at 0 (since rden_mux
// array contents initialized to 0)
end
end
end
end else begin
// Otherwise - if we're done w/ stage 2 calibration:
// set final value for RDEN data delay
// flag error if there's more than one cycle variation from DQS[0]
calib_err_2[1] <= (rden_inc && rden_dec);
if (rden_inc)
// if DQS[0] delay represents max delay
calib_rden_sel <= ~rden_mux;
else
// if DQS[0] delay represents min delay (or all the delays are
// the same between DQS groups)
calib_rden_sel <= rden_mux;
end
end
end
// flag error for stage 3 if appropriate
always @(posedge clkdiv)
calib_err[2] <= calib_err_2[0] | calib_err_2[1];
//***************************************************************************
// Stage 4 calibration: DQS gate
//***************************************************************************
//*****************************************************************
// indicates that current received data is the correct pattern. Same as
// for READ VALID calibration, except that the expected data sequence is
// different since DQS gate is asserted after the 6th word.
// Data sequence:
// Arrives from memory (at FPGA input) (R, F): 1 0 0 1 1 0 0 1
// After gating the sequence looks like: 1 0 0 1 1 0 1 0 (7th word =
// 5th word, 8th word = 6th word)
// What is the gate timing is off? Need to make sure we can distinquish
// between the results of correct vs. incorrect gate timing. We also use
// the "read_valid" signal from stage 3 calibration to help us determine
// when to check for a valid sequence for stage 4 calibration (i.e. use
// CAL4_DATA_VALID in addition to CAL4_DATA_MATCH/CAL4_DATA_MATCH_STGD)
// Note that since the gate signal from the CLK0 domain is synchronized
// to the falling edge of DQS, that the effect of the gate will only be
// seen starting with a rising edge data (although it is possible
// the GATE IDDR output could go metastable and cause a unexpected result
// on the first rising and falling edges after the gate is enabled).
// Also note that the actual DQS glitch can come more than 0.5*tCK after
// the last falling edge of DQS and the constraint for this path is can
// be > 0.5*tCK; however, this means when calibrating, the output of the
// GATE IDDR may miss the setup time requirement of the rising edge flop
// and only meet it for the falling edge flop. Therefore the rising
// edge data immediately following the assertion of the gate can either
// be a 1 or 0 (can rely on either)
// As the timing on the gate is varied, we expect to see (sequence of
// captured read data shown below):
// - 1 0 0 1 1 0 0 1 (gate is really early, starts and ends before
// read burst even starts)
// - x 0 0 1 1 0 0 1 (gate pulse starts before the burst, and ends
// - x y 0 1 1 0 0 1 sometime during the burst; x,y = 0, or 1, but
// - x y x 1 1 0 0 1 all bits that show an x are the same value,
// - x y x y 1 0 0 1 and y are the same value)
// - x y x y x 0 0 1
// - x y x y x y 0 1 (gate starts just before start of burst)
// - 1 0 x 0 x 0 x 0 (gate starts after 1st falling word. The "x"
// represents possiblity that gate may not disable
// clock for 2nd rising word in time)
// - 1 0 0 1 x 1 x 1 (gate starts after 2nd falling word)
// - 1 0 0 1 1 0 x 0 (gate starts after 3rd falling word - GOOD!!)
// - 1 0 0 1 1 0 0 1 (gate starts after burst is already done)
//*****************************************************************
assign cal4_data_valid = calib_rden_valid | calib_rden_valid_stgd;
assign cal4_data_good = (calib_rden_valid &
cal4_data_match) |
(calib_rden_valid_stgd &
cal4_data_match_stgd);
always @(posedge clkdiv) begin
// if data is aligned out of fabric ISERDES:
cal4_data_match <= ((rdd_rise_q2_r == 1) &&
(rdd_fall_q2_r == 0) &&
(rdd_rise_q1_r == 0) &&
(rdd_fall_q1_r == 1) &&
(rdd_rise_q2 == 1) &&
(rdd_fall_q2 == 0) &&
// MIG 2.1: Last rising edge data value not
// guaranteed to be certain value at higher
// frequencies
// (rdd_rise_q1 == 0) &&
(rdd_fall_q1 == 0));
// if data is staggered out of fabric ISERDES:
cal4_data_match_stgd <= ((rdd_rise_q1_r1 == 1) &&
(rdd_fall_q1_r1 == 0) &&
(rdd_rise_q2_r == 0) &&
(rdd_fall_q2_r == 1) &&
(rdd_rise_q1_r == 1) &&
(rdd_fall_q1_r == 0) &&
// MIG 2.1: Last rising edge data value not
// guaranteed to be certain value at higher
// frequencies
// (rdd_rise_q2 == 0) &&
(rdd_fall_q2 == 0));
end
//*****************************************************************
// DQS gate enable generation:
// This signal gets synchronized to DQS domain, and drives IDDR
// register that in turn asserts/deasserts CE to all 4 or 8 DQ
// IDDR's in that DQS group.
// 1. During normal (post-cal) operation, this is only for 2 clock
// cycles following the end of a burst. Check for falling edge
// of RDEN. But must also make sure NOT assert for a read-idle-
// read (two non-consecutive reads, separated by exactly one
// idle cycle) - in this case, don't assert the gate because:
// (1) we don't have enough time to deassert the gate before the
// first rising edge of DQS for second burst (b/c of fact
// that DQS gate is generated in the fabric only off rising
// edge of CLK0 - if we somehow had an ODDR in fabric, we
// could pull this off, (2) assumption is that the DQS glitch
// will not rise enough to cause a glitch because the
// post-amble of the first burst is followed immediately by
// the pre-amble of the next burst
// 2. During stage 4 calibration, assert for 3 clock cycles
// (assert gate enable one clock cycle early), since we gate out
// the last two words (in addition to the crap on the DQ bus after
// the DQS read postamble).
// NOTE: PHY_INIT_RDEN and CTRL_RDEN have slightly different timing w/r
// to when they are asserted w/r to the start of the read burst
// (PHY_INIT_RDEN is one cycle earlier than CTRL_RDEN).
//*****************************************************************
// register for timing purposes for fast clock path - currently only
// calib_done_r[2] used
always @(posedge clk)
calib_done_r <= calib_done;
always @(*) begin
calib_ctrl_rden = ctrl_rden;
calib_init_rden = calib_done_r[2] & phy_init_rden;
end
assign calib_ctrl_rden_negedge = ~calib_ctrl_rden & calib_ctrl_rden_r;
// check for read-idle-read before asserting DQS pulse at end of read
assign calib_ctrl_gate_pulse = calib_ctrl_rden_negedge_r &
~calib_ctrl_rden;
always @(posedge clk) begin
calib_ctrl_rden_r <= calib_ctrl_rden;
calib_ctrl_rden_negedge_r <= calib_ctrl_rden_negedge;
calib_ctrl_gate_pulse_r <= calib_ctrl_gate_pulse;
end
assign calib_init_gate_pulse = ~calib_init_rden & calib_init_rden_r;
always @(posedge clk) begin
calib_init_rden_r <= calib_init_rden;
calib_init_gate_pulse_r <= calib_init_gate_pulse;
calib_init_gate_pulse_r1 <= calib_init_gate_pulse_r;
end
// Gate is asserted: (1) during cal, for 3 cycles, starting 1 cycle
// after falling edge of CTRL_RDEN, (2) during normal ops, for 2
// cycles, starting 2 cycles after falling edge of CTRL_RDEN
assign gate_srl_in = ~((calib_ctrl_gate_pulse |
calib_ctrl_gate_pulse_r) |
(calib_init_gate_pulse |
calib_init_gate_pulse_r |
calib_init_gate_pulse_r1));
//*****************************************************************
// generate DQS enable signal for each DQS group
// There are differences between DQS gate signal for calibration vs. during
// normal operation:
// * calibration gates the second to last clock cycle of the burst,
// rather than after the last word (e.g. for a 8-word, 4-cycle burst,
// cycle 4 is gated for calibration; during normal operation, cycle
// 5 (i.e. cycle after the last word) is gated)
// enable for DQS is deasserted for two clock cycles, except when
// we have the preamble for the next read immediately following
// the postamble of the current read - assume DQS does not glitch
// during this time, that it stays low. Also if we did have to gate
// the DQS for this case, then we don't have enough time to deassert
// the gate in time for the first rising edge of DQS for the second
// read
//*****************************************************************
// Flops for targetting of multi-cycle path in UCF
genvar gate_ff_i;
generate
for (gate_ff_i = 0; gate_ff_i < 5*DQS_WIDTH;
gate_ff_i = gate_ff_i+1) begin: gen_gate_dly
FDRSE u_ff_gate_dly
(
.Q (gate_dly_r[gate_ff_i]),
.C (clkdiv),
.CE (1'b1),
.D (gate_dly[gate_ff_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
genvar gate_i;
generate
for (gate_i = 0; gate_i < DQS_WIDTH; gate_i = gate_i + 1) begin: gen_gate
SRLC32E u_gate_srl
(
.Q (gate_srl_out[gate_i]),
.Q31 (),
.A ({gate_dly_r[(gate_i*5)+4],
gate_dly_r[(gate_i*5)+3],
gate_dly_r[(gate_i*5)+2],
gate_dly_r[(gate_i*5)+1],
gate_dly_r[(gate_i*5)]}),
.CE (1'b1),
.CLK (clk),
.D (gate_srl_in)
);
// For GATE_BASE_DELAY > 0, have one extra cycle to register outputs
// from controller before generating DQS gate pulse. In PAR, the
// location of the controller logic can be far from the DQS gate
// logic (DQS gate logic located near the DQS I/O's), contributing
// to large net delays. Registering the controller outputs for
// CL >= 4 (above 200MHz) adds a stage of pipelining to reduce net
// delays
if (GATE_BASE_DELAY > 0) begin: gen_gate_base_dly_gt3
// add flop between SRL32 and EN_DQS flop (which is located near the
// DDR2 IOB's)
FDRSE u_gate_srl_ff
(
.Q (gate_srl_out_r[gate_i]),
.C (clk),
.CE (1'b1),
.D (gate_srl_out[gate_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */;
end else begin: gen_gate_base_dly_le3
assign gate_srl_out_r[gate_i] = gate_srl_out[gate_i];
end
FDRSE u_en_dqs_ff
(
.Q (en_dqs[gate_i]),
.C (clk),
.CE (1'b1),
.D (gate_srl_out_r[gate_i]),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
//*****************************************************************
// Find valid window: keep track of how long we've been in the same data
// window. If it's been long enough, then declare that we've found a stable
// valid window - in particular, that we're past any region of instability
// associated with the edge of the window. Use only when finding left edge
//*****************************************************************
always @(posedge clkdiv)
// reset before we start to look for window
if (cal4_state == CAL4_INIT) begin
cal4_window_cnt <= 4'b0000;
cal4_stable_window <= 1'b0;
end else if ((cal4_state == CAL4_FIND_EDGE) && cal4_seek_left) begin
// if we're looking for left edge, and incrementing IDELAY, count
// consecutive taps over which we're in the window
if (cal4_data_valid) begin
if (cal4_data_good)
cal4_window_cnt <= cal4_window_cnt + 1;
else
cal4_window_cnt <= 4'b0000;
end
if (cal4_window_cnt == MIN_WIN_SIZE-1)
cal4_stable_window <= 1'b1;
end
//*****************************************************************
// keep track of edge tap counts found, and whether we've
// incremented to the maximum number of taps allowed
//*****************************************************************
always @(posedge clkdiv)
if ((cal4_state == CAL4_INIT) || cal4_dlyrst_gate) begin
cal4_idel_max_tap <= 1'b0;
cal4_idel_bit_tap <= 1'b0;
cal4_idel_tap_cnt <= 6'b000000;
end else if (cal4_dlyce_gate) begin
if (cal4_dlyinc_gate) begin
cal4_idel_tap_cnt <= cal4_idel_tap_cnt + 1;
cal4_idel_bit_tap <= (cal4_idel_tap_cnt == CAL4_IDEL_BIT_VAL-2);
cal4_idel_max_tap <= (cal4_idel_tap_cnt == 6'b111110);
end else begin
cal4_idel_tap_cnt <= cal4_idel_tap_cnt - 1;
cal4_idel_bit_tap <= 1'b0;
cal4_idel_max_tap <= 1'b0;
end
end
always @(posedge clkdiv)
if ((cal4_state != CAL4_RDEN_PIPE_CLR_WAIT) &&
(cal3_state != CAL3_RDEN_PIPE_CLR_WAIT))
calib_rden_pipe_cnt <= CALIB_RDEN_PIPE_LEN-1;
else
calib_rden_pipe_cnt <= calib_rden_pipe_cnt - 1;
//*****************************************************************
// Stage 4 cal state machine
//*****************************************************************
always @(posedge clkdiv)
if (rstdiv) begin
calib_done[3] <= 1'b0;
calib_done_tmp[3] <= 1'b0;
calib_err[3] <= 1'b0;
count_gate <= 'b0;
gate_dly <= 'b0;
next_count_gate <= 'b0;
cal4_idel_adj_cnt <= 6'bxxxxxx;
cal4_dlyce_gate <= 1'b0;
cal4_dlyinc_gate <= 1'b0;
cal4_dlyrst_gate <= 1'b0; // reset handled elsewhere in code
cal4_gate_srl_a <= 5'bxxxxx;
cal4_rden_srl_a <= 5'bxxxxx;
cal4_ref_req <= 1'b0;
cal4_seek_left <= 1'bx;
cal4_state <= CAL4_IDLE;
end else begin
cal4_ref_req <= 1'b0;
cal4_dlyce_gate <= 1'b0;
cal4_dlyinc_gate <= 1'b0;
cal4_dlyrst_gate <= 1'b0;
case (cal4_state)
CAL4_IDLE: begin
count_gate <= 'b0;
next_count_gate <= 'b0;
if (calib_start[3]) begin
gate_dly <= 'b0;
calib_done[3] <= 1'b0;
cal4_state <= CAL4_INIT;
end
end
CAL4_INIT: begin
// load: (1) initial value of gate delay SRL, (2) appropriate
// value of RDEN SRL (so that we get correct "data valid" timing)
cal4_gate_srl_a <= GATE_BASE_INIT;
cal4_rden_srl_a <= {calib_rden_dly[(count_gate*5)+4],
calib_rden_dly[(count_gate*5)+3],
calib_rden_dly[(count_gate*5)+2],
calib_rden_dly[(count_gate*5)+1],
calib_rden_dly[(count_gate*5)]};
// let SRL pipe clear after loading initial shift value
cal4_state <= CAL4_RDEN_PIPE_CLR_WAIT;
end
// sort of an initial state - start checking to see whether we're
// already in the window or not
CAL4_FIND_WINDOW:
// decide right away if we start in the proper window - this
// determines if we are then looking for the left (trailing) or
// right (leading) edge of the data valid window
if (cal4_data_valid) begin
// if we find a match - then we're already in window, now look
// for left edge. Otherwise, look for right edge of window
cal4_seek_left <= cal4_data_good;
cal4_state <= CAL4_FIND_EDGE;
end
CAL4_FIND_EDGE:
// don't do anything until the exact clock cycle when to check that
// readback data is valid or not
if (cal4_data_valid) begin
// we're currently in the window, look for left edge of window
if (cal4_seek_left) begin
// make sure we've passed the right edge before trying to detect
// the left edge (i.e. avoid any edge "instability") - else, we
// may detect an "false" edge too soon. By design, if we start in
// the data valid window, always expect at least
// MIN(BIT_TIME_TAPS,32) (-/+ jitter, see below) taps of valid
// window before we hit the left edge (this is because when stage
// 4 calibration first begins (i.e., gate_dly = 00, and IDELAY =
// 00), we're guaranteed to NOT be in the window, and we always
// start searching for MIN(BIT_TIME_TAPS,32) for the right edge
// of window. If we don't find it, increment gate_dly, and if we
// now start in the window, we have at least approximately
// CLK_PERIOD-MIN(BIT_TIME_TAPS,32) = MIN(BIT_TIME_TAPS,32) taps.
// It's approximately because jitter, noise, etc. can bring this
// value down slightly. Because of this (although VERY UNLIKELY),
// we have to protect against not decrementing IDELAY below 0
// during adjustment phase).
if (cal4_stable_window && !cal4_data_good) begin
// found left edge of window, dec by MIN(BIT_TIME_TAPS,32)
cal4_idel_adj_cnt <= CAL4_IDEL_BIT_VAL;
cal4_idel_adj_inc <= 1'b0;
cal4_state <= CAL4_ADJ_IDEL;
end else begin
// Otherwise, keep looking for left edge:
if (cal4_idel_max_tap) begin
// ran out of taps looking for left edge (max=63) - happens
// for low frequency case, decrement by 32
cal4_idel_adj_cnt <= 6'b100000;
cal4_idel_adj_inc <= 1'b0;
cal4_state <= CAL4_ADJ_IDEL;
end else begin
cal4_dlyce_gate <= 1'b1;
cal4_dlyinc_gate <= 1'b1;
cal4_state <= CAL4_IDEL_WAIT;
end
end
end else begin
// looking for right edge of window:
// look for the first match - this means we've found the right
// (leading) edge of the data valid window, increment by
// MIN(BIT_TIME_TAPS,32)
if (cal4_data_good) begin
cal4_idel_adj_cnt <= CAL4_IDEL_BIT_VAL;
cal4_idel_adj_inc <= 1'b1;
cal4_state <= CAL4_ADJ_IDEL;
end else begin
// Otherwise, keep looking:
// only look for MIN(BIT_TIME_TAPS,32) taps for right edge,
// if we haven't found it, then inc gate delay, try again
if (cal4_idel_bit_tap) begin
// if we're already maxed out on gate delay, then error out
// (simulation only - calib_err isn't currently connected)
if (cal4_gate_srl_a == 5'b11111) begin
calib_err[3] <= 1'b1;
cal4_state <= CAL4_IDLE;
end else begin
// otherwise, increment gate delay count, and start
// over again
cal4_gate_srl_a <= cal4_gate_srl_a + 1;
cal4_dlyrst_gate <= 1'b1;
cal4_state <= CAL4_RDEN_PIPE_CLR_WAIT;
end
end else begin
// keep looking for right edge
cal4_dlyce_gate <= 1'b1;
cal4_dlyinc_gate <= 1'b1;
cal4_state <= CAL4_IDEL_WAIT;
end
end
end
end
// wait for GATE IDELAY to settle, after reset or increment
CAL4_IDEL_WAIT: begin
// For simulation, load SRL addresses for all DQS with same value
if (SIM_ONLY != 0) begin
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_sim_gate_dly
gate_dly[(i*5)+4] <= cal4_gate_srl_a[4];
gate_dly[(i*5)+3] <= cal4_gate_srl_a[3];
gate_dly[(i*5)+2] <= cal4_gate_srl_a[2];
gate_dly[(i*5)+1] <= cal4_gate_srl_a[1];
gate_dly[(i*5)] <= cal4_gate_srl_a[0];
end
end else begin
gate_dly[(count_gate*5)+4] <= cal4_gate_srl_a[4];
gate_dly[(count_gate*5)+3] <= cal4_gate_srl_a[3];
gate_dly[(count_gate*5)+2] <= cal4_gate_srl_a[2];
gate_dly[(count_gate*5)+1] <= cal4_gate_srl_a[1];
gate_dly[(count_gate*5)] <= cal4_gate_srl_a[0];
end
// check to see if we've found edge of window
if (!idel_set_wait)
cal4_state <= CAL4_FIND_EDGE;
end
// give additional time for RDEN_R pipe to clear from effects of
// previous pipeline (and IDELAY reset)
CAL4_RDEN_PIPE_CLR_WAIT: begin
// MIG 2.2: Bug fix - make sure to update GATE_DLY count, since
// possible for FIND_EDGE->RDEN_PIPE_CLR_WAIT->FIND_WINDOW
// transition (i.e. need to make sure the gate count updated in
// FIND_EDGE gets reflected in GATE_DLY by the time we reach
// state FIND_WINDOW) - previously GATE_DLY only being updated
// during state CAL4_IDEL_WAIT
if (SIM_ONLY != 0) begin
for (i = 0; i < DQS_WIDTH; i = i + 1) begin: loop_sim_gate_dly_pipe
gate_dly[(i*5)+4] <= cal4_gate_srl_a[4];
gate_dly[(i*5)+3] <= cal4_gate_srl_a[3];
gate_dly[(i*5)+2] <= cal4_gate_srl_a[2];
gate_dly[(i*5)+1] <= cal4_gate_srl_a[1];
gate_dly[(i*5)] <= cal4_gate_srl_a[0];
end
end else begin
gate_dly[(count_gate*5)+4] <= cal4_gate_srl_a[4];
gate_dly[(count_gate*5)+3] <= cal4_gate_srl_a[3];
gate_dly[(count_gate*5)+2] <= cal4_gate_srl_a[2];
gate_dly[(count_gate*5)+1] <= cal4_gate_srl_a[1];
gate_dly[(count_gate*5)] <= cal4_gate_srl_a[0];
end
// look for new window
if (calib_rden_pipe_cnt == 5'b00000)
cal4_state <= CAL4_FIND_WINDOW;
end
// increment/decrement DQS/DQ IDELAY for final adjustment
CAL4_ADJ_IDEL:
// add underflow protection for corner case when left edge found
// using fewer than MIN(BIT_TIME_TAPS,32) taps
if ((cal4_idel_adj_cnt == 6'b000000) ||
(cal4_dlyce_gate && !cal4_dlyinc_gate &&
(cal4_idel_tap_cnt == 6'b000001))) begin
cal4_state <= CAL4_DONE;
// stop when all gates calibrated, or gate[0] cal'ed (for sim)
if ((count_gate == DQS_WIDTH-1) || (SIM_ONLY != 0))
calib_done_tmp[3] <= 1'b1;
else
// need for VHDL simulation to prevent out-of-index error
next_count_gate <= count_gate + 1;
end else begin
cal4_idel_adj_cnt <= cal4_idel_adj_cnt - 1;
cal4_dlyce_gate <= 1'b1;
// whether inc or dec depends on whether left or right edge found
cal4_dlyinc_gate <= cal4_idel_adj_inc;
end
// wait for IDELAY output to settle after decrement. Check current
// COUNT_GATE value and decide if we're done
CAL4_DONE:
if (!idel_set_wait) begin
count_gate <= next_count_gate;
if (calib_done_tmp[3]) begin
calib_done[3] <= 1'b1;
cal4_state <= CAL4_IDLE;
end else begin
// request auto-refresh after every DQS group calibrated to
// avoid tRAS violation
cal4_ref_req <= 1'b1;
if (calib_ref_done)
cal4_state <= CAL4_INIT;
end
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_SS_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_SS_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_SS//Dígitos BCD ya concatenados hacia los registros(8 bits)
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 1)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_SS = {digit1,digit0};
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SPI Slave Model ////
//// ////
//// ////
//// Authors: Richard Herveille ([email protected]) www.asics.ws ////
//// ////
//// http://www.opencores.org/projects/simple_spi/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: spi_slave_model.v,v 1.1 2004-02-28 15:32:54 rherveille Exp $
//
// $Date: 2004-02-28 15:32:54 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
// Requires: Verilog2001
`include "timescale.v"
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
//
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr];
else
sro <= #1 {sro[6:0],1'bx};
assign do = sro[7];
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr];
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : ex_reg.v
-- DESCRIPTION : EX¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module ex_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ALU¤Î³öÁ¦ **********/
input wire [`WordDataBus] alu_out, // ÑÝËã½Y¹û
input wire alu_of, // ¥ª©`¥Ð¥Õ¥í©`
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire int_detect, // ¸î¤êÞz¤ßʳö
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire id_br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] id_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire id_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] id_exp_code, // ÀýÍ⥳©`¥É
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output reg [`WordAddrBus] ex_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output reg ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output reg ex_br_flag, // ·Ö᪥ե饰
output reg [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output reg [`CtrlOpBus] ex_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`RegAddrBus] ex_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output reg ex_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output reg [`IsaExpBus] ex_exp_code, // ÀýÍ⥳©`¥É
output reg [`WordDataBus] ex_out // IÀí½Y¹û
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
always @(posedge clk or `RESET_EDGE reset) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
if (reset == `RESET_ENABLE) begin
ex_pc <= #1 `WORD_ADDR_W'h0;
ex_en <= #1 `DISABLE;
ex_br_flag <= #1 `DISABLE;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_NO_EXP;
ex_out <= #1 `WORD_DATA_W'h0;
end else begin
/* ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿¤Î¸üР*/
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // ¥Õ¥é¥Ã¥·¥å
ex_pc <= #1 `WORD_ADDR_W'h0;
ex_en <= #1 `DISABLE;
ex_br_flag <= #1 `DISABLE;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_NO_EXP;
ex_out <= #1 `WORD_DATA_W'h0;
end else if (int_detect == `ENABLE) begin // ¸î¤êÞz¤ß¤Îʳö
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_EXT_INT;
ex_out <= #1 `WORD_DATA_W'h0;
end else if (alu_of == `ENABLE) begin // ËãÐg¥ª©`¥Ð¥Õ¥í©`
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 `MEM_OP_NOP;
ex_mem_wr_data <= #1 `WORD_DATA_W'h0;
ex_ctrl_op <= #1 `CTRL_OP_NOP;
ex_dst_addr <= #1 `REG_ADDR_W'd0;
ex_gpr_we_ <= #1 `DISABLE_;
ex_exp_code <= #1 `ISA_EXP_OVERFLOW;
ex_out <= #1 `WORD_DATA_W'h0;
end else begin // ´Î¤Î¥Ç©`¥¿
ex_pc <= #1 id_pc;
ex_en <= #1 id_en;
ex_br_flag <= #1 id_br_flag;
ex_mem_op <= #1 id_mem_op;
ex_mem_wr_data <= #1 id_mem_wr_data;
ex_ctrl_op <= #1 id_ctrl_op;
ex_dst_addr <= #1 id_dst_addr;
ex_gpr_we_ <= #1 id_gpr_we_;
ex_exp_code <= #1 id_exp_code;
ex_out <= #1 alu_out;
end
end
end
end
endmodule
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