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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_par34.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_par34
// Description:
// Generates 34b parity. Odd number of ones => out = 1
*/
module sparc_ifu_par34 (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [33:0] in;
output out;
assign out = (^in[33:0]);
endmodule // sparc_ifu_par34
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module csrbrg(
input sys_clk,
input sys_rst,
/* WB */
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* CSR */
output reg [13:0] csr_a,
output reg csr_we,
output reg [31:0] csr_do,
input [31:0] csr_di
);
/* Datapath: WB <- CSR */
always @(posedge sys_clk) begin
wb_dat_o <= csr_di;
end
/* Datapath: CSR -> WB */
reg next_csr_we;
always @(posedge sys_clk) begin
csr_a <= wb_adr_i[15:2];
csr_we <= next_csr_we;
csr_do <= wb_dat_i;
end
/* Controller */
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter DELAYACK1 = 2'd1;
parameter DELAYACK2 = 2'd2;
parameter ACK = 2'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
wb_ack_o = 1'b0;
next_csr_we = 1'b0;
case(state)
IDLE: begin
if(wb_cyc_i & wb_stb_i) begin
/* We have a request for us */
next_csr_we = wb_we_i;
if(wb_we_i)
next_state = ACK;
else
next_state = DELAYACK1;
end
end
DELAYACK1: next_state = DELAYACK2;
DELAYACK2: next_state = ACK;
ACK: begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Template for a 1K program for KCPSM6 in a Spartan-6 device using a RAMB18WER primitive.
Includes generic parameters to allow for the inclusion of Jtag Loader hardware for
software development.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
Kris Chaplin (Xilinx Ltd)
3rd March 2011 - Initial Verilog Release
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
20th April 2012 - Correction to copyright year range.
26th November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a Verilog template file for the KCPSM6 assembler.
This Verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Definition of a program memory for KCPSM6 including generic parameters for the
// convenient selection of device family, program memory size and the ability to include
// the JTAG Loader hardware for rapid software development.
//
// This file is primarily for use during code development and it is recommended that the
// appropriate simplified program memory definition be used in a final production design.
//
//
// Generic Values Comments
// Parameter Supported
//
// C_FAMILY "S6" Spartan-6 device
// "V6" Virtex-6 device
// "7S" 7-Series device
// (Artix-7, Kintex-7, Virtex-7 or Zynq)
//
// C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
//
// C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
//
// Notes
//
// If your design contains MULTIPLE KCPSM6 instances then only one should have the
// JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
// '1' on one instance of the program memory). Advanced users may be interested to know
// that it is possible to connect JTAG Loader to multiple memories and then to use the
// JTAG Loader utility to specify which memory contents are to be modified. However,
// this scheme does require some effort to set up and the additional connectivity of the
// multiple BRAMs can impact the placement, routing and performance of the complete
// design. Please contact the author at Xilinx for more detailed information.
//
// Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
// 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
// without requiring changes to the fundamental hardware definition. However, when the
// program memory is 1K then only the lower 10-bits of the address are actually used and
// the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
// 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
//
// Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
// size of the program and the device family.
//
// In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
// will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
// should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
// the implementation also requires a small amount of logic resulting in slightly lower
// performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
// that a program containing up to 512 instructions could be implemented. However, there
// is a silicon errata which makes this unsuitable and therefore it is not supported by
// this file.
//
// In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
// obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
// 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
// reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
//
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.v
//
//
`timescale 1ps/1ps
module {name} (address, instruction, enable, rdl, clk);
//
parameter integer C_JTAG_LOADER_ENABLE = 0;
parameter C_FAMILY = "7S";
parameter integer C_RAM_SIZE_KWORDS = 1;
//
input clk;
input [11:0] address;
input enable;
output [17:0] instruction;
output rdl;
//
//
wire [15:0] address_a;
wire pipe_a11;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [35:0] data_out_a_ll;
wire [35:0] data_out_a_lh;
wire [35:0] data_out_a_hl;
wire [35:0] data_out_a_hh;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_in_b_l;
wire [35:0] data_in_b_ll;
wire [35:0] data_in_b_hl;
wire [35:0] data_out_b;
wire [35:0] data_out_b_l;
wire [35:0] data_out_b_ll;
wire [35:0] data_out_b_hl;
wire [35:0] data_in_b_h;
wire [35:0] data_in_b_lh;
wire [35:0] data_in_b_hh;
wire [35:0] data_out_b_h;
wire [35:0] data_out_b_lh;
wire [35:0] data_out_b_hh;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
wire [3:0] we_b_l;
wire [3:0] we_b_h;
//
wire [11:0] jtag_addr;
wire jtag_we;
wire jtag_clk;
wire [17:0] jtag_din;
wire [17:0] jtag_dout;
wire [17:0] jtag_dout_1;
wire [0:0] jtag_en;
//
wire [0:0] picoblaze_reset;
wire [0:0] rdl_bus;
//
parameter integer BRAM_ADDRESS_WIDTH = addr_width_calc(C_RAM_SIZE_KWORDS);
//
//
function integer addr_width_calc;
input integer size_in_k;
if (size_in_k == 1) begin addr_width_calc = 10; end
else if (size_in_k == 2) begin addr_width_calc = 11; end
else if (size_in_k == 4) begin addr_width_calc = 12; end
else begin
if (C_RAM_SIZE_KWORDS != 1 && C_RAM_SIZE_KWORDS != 2 && C_RAM_SIZE_KWORDS != 4) begin
//#0;
$display("Invalid BlockRAM size. Please set to 1, 2 or 4 K words..\n");
$finish;
end
end
endfunction
//
//
generate
if (C_RAM_SIZE_KWORDS == 1) begin : ram_1k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a[13:0] = {address[9:0], 4'b1111};
assign instruction = data_out_a[17:0];
assign data_in_a[17:0] = {16'b0000000000000000, address[11:10]};
assign jtag_dout = data_out_b[17:0];
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b[17:0] = data_out_b[17:0];
assign address_b[13:0] = 14'b11111111111111;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b[17:0] = jtag_din[17:0];
assign address_b[13:0] = {jtag_addr[9:0], 4'b1111};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB18E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (18'b000000000000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (18'b000000000000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (18'b000000000000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (18'b000000000000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}))
kcpsm6_rom( .ADDRARDADDR (address_a[13:0]),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[15:0]),
.DOPADOP (data_out_a[17:16]),
.DIADI (data_in_a[15:0]),
.DIPADIP (data_in_a[17:16]),
.WEA (2'b00),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b[13:0]),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[15:0]),
.DOPBDOP (data_out_b[17:16]),
.DIBDI (data_in_b[15:0]),
.DIPBDIP (data_in_b[17:16]),
.WEBWE (we_b[3:0]),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0));
end // akv7;
//
end // ram_1k_generate;
endgenerate
//
generate
if (C_RAM_SIZE_KWORDS == 2) begin : ram_2k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b = {1'b1, jtag_addr[10:0], 4'b1111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INIT_40 (256'h{INIT_40}),
.INIT_41 (256'h{INIT_41}),
.INIT_42 (256'h{INIT_42}),
.INIT_43 (256'h{INIT_43}),
.INIT_44 (256'h{INIT_44}),
.INIT_45 (256'h{INIT_45}),
.INIT_46 (256'h{INIT_46}),
.INIT_47 (256'h{INIT_47}),
.INIT_48 (256'h{INIT_48}),
.INIT_49 (256'h{INIT_49}),
.INIT_4A (256'h{INIT_4A}),
.INIT_4B (256'h{INIT_4B}),
.INIT_4C (256'h{INIT_4C}),
.INIT_4D (256'h{INIT_4D}),
.INIT_4E (256'h{INIT_4E}),
.INIT_4F (256'h{INIT_4F}),
.INIT_50 (256'h{INIT_50}),
.INIT_51 (256'h{INIT_51}),
.INIT_52 (256'h{INIT_52}),
.INIT_53 (256'h{INIT_53}),
.INIT_54 (256'h{INIT_54}),
.INIT_55 (256'h{INIT_55}),
.INIT_56 (256'h{INIT_56}),
.INIT_57 (256'h{INIT_57}),
.INIT_58 (256'h{INIT_58}),
.INIT_59 (256'h{INIT_59}),
.INIT_5A (256'h{INIT_5A}),
.INIT_5B (256'h{INIT_5B}),
.INIT_5C (256'h{INIT_5C}),
.INIT_5D (256'h{INIT_5D}),
.INIT_5E (256'h{INIT_5E}),
.INIT_5F (256'h{INIT_5F}),
.INIT_60 (256'h{INIT_60}),
.INIT_61 (256'h{INIT_61}),
.INIT_62 (256'h{INIT_62}),
.INIT_63 (256'h{INIT_63}),
.INIT_64 (256'h{INIT_64}),
.INIT_65 (256'h{INIT_65}),
.INIT_66 (256'h{INIT_66}),
.INIT_67 (256'h{INIT_67}),
.INIT_68 (256'h{INIT_68}),
.INIT_69 (256'h{INIT_69}),
.INIT_6A (256'h{INIT_6A}),
.INIT_6B (256'h{INIT_6B}),
.INIT_6C (256'h{INIT_6C}),
.INIT_6D (256'h{INIT_6D}),
.INIT_6E (256'h{INIT_6E}),
.INIT_6F (256'h{INIT_6F}),
.INIT_70 (256'h{INIT_70}),
.INIT_71 (256'h{INIT_71}),
.INIT_72 (256'h{INIT_72}),
.INIT_73 (256'h{INIT_73}),
.INIT_74 (256'h{INIT_74}),
.INIT_75 (256'h{INIT_75}),
.INIT_76 (256'h{INIT_76}),
.INIT_77 (256'h{INIT_77}),
.INIT_78 (256'h{INIT_78}),
.INIT_79 (256'h{INIT_79}),
.INIT_7A (256'h{INIT_7A}),
.INIT_7B (256'h{INIT_7B}),
.INIT_7C (256'h{INIT_7C}),
.INIT_7D (256'h{INIT_7D}),
.INIT_7E (256'h{INIT_7E}),
.INIT_7F (256'h{INIT_7F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}),
.INITP_08 (256'h{INITP_08}),
.INITP_09 (256'h{INITP_09}),
.INITP_0A (256'h{INITP_0A}),
.INITP_0B (256'h{INITP_0B}),
.INITP_0C (256'h{INITP_0C}),
.INITP_0D (256'h{INITP_0D}),
.INITP_0E (256'h{INITP_0E}),
.INITP_0F (256'h{INITP_0F}))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // akv7;
//
end // ram_2k_generate;
endgenerate
//
//
// JTAG Loader
//
generate
if (C_JTAG_LOADER_ENABLE == 1) begin: instantiate_loader
jtag_loader_6 #( .C_FAMILY (C_FAMILY),
.C_NUM_PICOBLAZE (1),
.C_JTAG_LOADER_ENABLE (C_JTAG_LOADER_ENABLE),
.C_BRAM_MAX_ADDR_WIDTH (BRAM_ADDRESS_WIDTH),
.C_ADDR_WIDTH_0 (BRAM_ADDRESS_WIDTH))
jtag_loader_6_inst(.picoblaze_reset (rdl_bus),
.jtag_en (jtag_en),
.jtag_din (jtag_din),
.jtag_addr (jtag_addr[BRAM_ADDRESS_WIDTH-1 : 0]),
.jtag_clk (jtag_clk),
.jtag_we (jtag_we),
.jtag_dout_0 (jtag_dout),
.jtag_dout_1 (jtag_dout), // ports 1-7 are not used
.jtag_dout_2 (jtag_dout), // in a 1 device debug
.jtag_dout_3 (jtag_dout), // session. However, Synplify
.jtag_dout_4 (jtag_dout), // etc require all ports are
.jtag_dout_5 (jtag_dout), // connected
.jtag_dout_6 (jtag_dout),
.jtag_dout_7 (jtag_dout));
end //instantiate_loader
endgenerate
//
//
endmodule
//
//
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// JTAG Loader
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// JTAG Loader 6 - Version 6.00
//
// Kris Chaplin - 4th February 2010
// Nick Sawyer - 3rd March 2011 - Initial conversion to Verilog
// Ken Chapman - 16th August 2011 - Revised coding style
//
`timescale 1ps/1ps
module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "V6";
parameter integer C_NUM_PICOBLAZE = 1;
parameter integer C_BRAM_MAX_ADDR_WIDTH = 10;
parameter integer C_PICOBLAZE_INSTRUCTION_DATA_WIDTH = 18;
parameter integer C_JTAG_CHAIN = 2;
parameter [4:0] C_ADDR_WIDTH_0 = 10;
parameter [4:0] C_ADDR_WIDTH_1 = 10;
parameter [4:0] C_ADDR_WIDTH_2 = 10;
parameter [4:0] C_ADDR_WIDTH_3 = 10;
parameter [4:0] C_ADDR_WIDTH_4 = 10;
parameter [4:0] C_ADDR_WIDTH_5 = 10;
parameter [4:0] C_ADDR_WIDTH_6 = 10;
parameter [4:0] C_ADDR_WIDTH_7 = 10;
//
output [C_NUM_PICOBLAZE-1:0] picoblaze_reset;
output [C_NUM_PICOBLAZE-1:0] jtag_en;
output [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din;
output [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr;
output jtag_clk ;
output jtag_we;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7;
//
//
wire [2:0] num_picoblaze;
wire [4:0] picoblaze_instruction_data_width;
//
wire drck;
wire shift_clk;
wire shift_din;
wire shift_dout;
wire shift;
wire capture;
//
reg control_reg_ce;
reg [C_NUM_PICOBLAZE-1:0] bram_ce;
wire [C_NUM_PICOBLAZE-1:0] bus_zero;
wire [C_NUM_PICOBLAZE-1:0] jtag_en_int;
wire [7:0] jtag_en_expanded;
reg [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr_int;
reg [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_din;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_dout;
reg [7:0] control_dout_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] bram_dout_int;
reg jtag_we_int;
wire jtag_clk_int;
wire bram_ce_valid;
reg din_load;
//
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7_masked;
reg [C_NUM_PICOBLAZE-1:0] picoblaze_reset_int;
//
initial picoblaze_reset_int = 0;
//
genvar i;
//
generate
for (i = 0; i <= C_NUM_PICOBLAZE-1; i = i+1)
begin : npzero_loop
assign bus_zero[i] = 1'b0;
end
endgenerate
//
generate
//
if (C_JTAG_LOADER_ENABLE == 1)
begin : jtag_loader_gen
//
// Insert BSCAN primitive for target device architecture.
//
if (C_FAMILY == "S6")
begin : BSCAN_SPARTAN6_gen
BSCAN_SPARTAN6 # (.JTAG_CHAIN (C_JTAG_CHAIN))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "V6")
begin : BSCAN_VIRTEX6_gen
BSCAN_VIRTEX6 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "7S")
begin : BSCAN_7SERIES_gen
BSCANE2 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
// Insert clock buffer to ensure reliable shift operations.
//
BUFG upload_clock (.I (drck), .O (shift_clk));
//
//
// Shift Register
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
control_reg_ce <= shift_din;
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[0] <= control_reg_ce;
end
end
//
for (i = 0; i <= C_NUM_PICOBLAZE-2; i = i+1)
begin : loop0
if (C_NUM_PICOBLAZE > 1) begin
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[i+1] <= bram_ce[i];
end
end
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_we_int <= bram_ce[C_NUM_PICOBLAZE-1];
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[0] <= jtag_we_int;
end
end
//
for (i = 0; i <= C_BRAM_MAX_ADDR_WIDTH-2; i = i+1)
begin : loop1
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[i+1] <= jtag_addr_int[i];
end
end
end
//
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[0] <= bram_dout_int[0];
end
else if (shift == 1'b1) begin
jtag_din_int[0] <= jtag_addr_int[C_BRAM_MAX_ADDR_WIDTH-1];
end
end
//
for (i = 0; i <= C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2; i = i+1)
begin : loop2
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[i+1] <= bram_dout_int[i+1];
end
if (shift == 1'b1) begin
jtag_din_int[i+1] <= jtag_din_int[i];
end
end
end
//
assign shift_dout = jtag_din_int[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1];
//
//
always @ (bram_ce or din_load or capture or bus_zero or control_reg_ce) begin
if ( bram_ce == bus_zero ) begin
din_load <= capture & control_reg_ce;
end else begin
din_load <= capture;
end
end
//
//
// Control Registers
//
assign num_picoblaze = C_NUM_PICOBLAZE-3'h1;
assign picoblaze_instruction_data_width = C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-5'h01;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b0 && control_reg_ce == 1'b1) begin
case (jtag_addr_int[3:0])
0 : // 0 = version - returns (7:4) illustrating number of PB
// and [3:0] picoblaze instruction data width
control_dout_int <= {num_picoblaze, picoblaze_instruction_data_width};
1 : // 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) begin
control_dout_int <= {picoblaze_reset_int[0], 2'b00, C_ADDR_WIDTH_0-5'h01};
end else begin
control_dout_int <= 8'h00;
end
2 : // 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) begin
control_dout_int <= {picoblaze_reset_int[1], 2'b00, C_ADDR_WIDTH_1-5'h01};
end else begin
control_dout_int <= 8'h00;
end
3 : // 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) begin
control_dout_int <= {picoblaze_reset_int[2], 2'b00, C_ADDR_WIDTH_2-5'h01};
end else begin
control_dout_int <= 8'h00;
end
4 : // 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) begin
control_dout_int <= {picoblaze_reset_int[3], 2'b00, C_ADDR_WIDTH_3-5'h01};
end else begin
control_dout_int <= 8'h00;
end
5: // 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) begin
control_dout_int <= {picoblaze_reset_int[4], 2'b00, C_ADDR_WIDTH_4-5'h01};
end else begin
control_dout_int <= 8'h00;
end
6 : // 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) begin
control_dout_int <= {picoblaze_reset_int[5], 2'b00, C_ADDR_WIDTH_5-5'h01};
end else begin
control_dout_int <= 8'h00;
end
7 : // 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) begin
control_dout_int <= {picoblaze_reset_int[6], 2'b00, C_ADDR_WIDTH_6-5'h01};
end else begin
control_dout_int <= 8'h00;
end
8 : // 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) begin
control_dout_int <= {picoblaze_reset_int[7], 2'b00, C_ADDR_WIDTH_7-5'h01};
end else begin
control_dout_int <= 8'h00;
end
15 : control_dout_int <= C_BRAM_MAX_ADDR_WIDTH -1;
default : control_dout_int <= 8'h00;
//
endcase
end else begin
control_dout_int <= 8'h00;
end
end
//
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8] = control_dout_int;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b1 && control_reg_ce == 1'b1) begin
picoblaze_reset_int[C_NUM_PICOBLAZE-1:0] <= control_din[C_NUM_PICOBLAZE-1:0];
end
end
//
//
// Assignments
//
if (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8) begin
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9:0] = 10'h000;
end
//
// Qualify the blockram CS signal with bscan select output
assign jtag_en_int = (bram_ce_valid) ? bram_ce : bus_zero;
//
assign jtag_en_expanded[C_NUM_PICOBLAZE-1:0] = jtag_en_int;
//
for (i = 7; i >= C_NUM_PICOBLAZE; i = i-1)
begin : loop4
if (C_NUM_PICOBLAZE < 8) begin : jtag_en_expanded_gen
assign jtag_en_expanded[i] = 1'b0;
end
end
//
assign bram_dout_int = control_dout | jtag_dout_0_masked | jtag_dout_1_masked | jtag_dout_2_masked | jtag_dout_3_masked | jtag_dout_4_masked | jtag_dout_5_masked | jtag_dout_6_masked | jtag_dout_7_masked;
//
assign control_din = jtag_din_int;
//
assign jtag_dout_0_masked = (jtag_en_expanded[0]) ? jtag_dout_0 : 18'h00000;
assign jtag_dout_1_masked = (jtag_en_expanded[1]) ? jtag_dout_1 : 18'h00000;
assign jtag_dout_2_masked = (jtag_en_expanded[2]) ? jtag_dout_2 : 18'h00000;
assign jtag_dout_3_masked = (jtag_en_expanded[3]) ? jtag_dout_3 : 18'h00000;
assign jtag_dout_4_masked = (jtag_en_expanded[4]) ? jtag_dout_4 : 18'h00000;
assign jtag_dout_5_masked = (jtag_en_expanded[5]) ? jtag_dout_5 : 18'h00000;
assign jtag_dout_6_masked = (jtag_en_expanded[6]) ? jtag_dout_6 : 18'h00000;
assign jtag_dout_7_masked = (jtag_en_expanded[7]) ? jtag_dout_7 : 18'h00000;
//
assign jtag_en = jtag_en_int;
assign jtag_din = jtag_din_int;
assign jtag_addr = jtag_addr_int;
assign jtag_clk = jtag_clk_int;
assign jtag_we = jtag_we_int;
assign picoblaze_reset = picoblaze_reset_int;
//
end
endgenerate
//
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
///////////////////////////////////////////////////////////////////////////////////////////
//
|
// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2019
// Owner : Alex Grobman
// Description:
// This module Synchronizes the signals between JTAG (TCK) and
// processor (Core_clk)
//
//-------------------------------------------------------------------------------------
module dmi_jtag_to_core_sync (
// JTAG signals
input rd_en, // 1 bit Read Enable from JTAG
input wr_en, // 1 bit Write enable from JTAG
// Processor Signals
input rst_n, // Core reset
input clk, // Core clock
output reg_en, // 1 bit Write interface bit to Processor
output reg_wr_en // 1 bit Write enable to Processor
);
wire c_rd_en;
wire c_wr_en;
reg [2:0] rden, wren;
// Outputs
assign reg_en = c_wr_en | c_rd_en;
assign reg_wr_en = c_wr_en;
// synchronizers
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
rden <= '0;
wren <= '0;
end
else begin
rden <= {rden[1:0], rd_en};
wren <= {wren[1:0], wr_en};
end
end
assign c_rd_en = rden[1] & ~rden[2];
assign c_wr_en = wren[1] & ~wren[2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp2 (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 11-12-2018
Each channel can use the full range of the DAC as they do not
get summed in the real chip.
Operator data is summed up without adding extra bits. This is
the case of real YM3438, which was used on Megadrive 2 models.
*/
/* Mixer for Megadrive/Genesis
cen_fm must be 1 over 7 of clk
psg_cen_240 must be 1 over 15 of clk
PSG and FM signals are interpolated up to clk sample rate.
*/
module jt12_genmix(
input rst,
input clk,
input signed [15:0] fm_left,
input signed [15:0] fm_right,
input signed [10:0] psg_snd,
input fm_en, // enable FM
input psg_en, // enable PSG
// Mixed sound at clk sample rate
output signed [15:0] snd_left,
output signed [15:0] snd_right
);
/////////////////////////////////////////////////
// PSG
// x5 -> div 3 -> div 7
// 54MHz count up to:
// orig -> 16*15 = 240
// x5 -> 16*15/5 = 48
// div 3 -> 48*3 = 144
// div 7 -> 144*7 = 1008 <=> fm_sample
// 48 x 5 = 240,
reg [5:0] psgcnt48;
reg [2:0] psgcnt240, psgcnt1008;
reg [1:0] psgcnt144;
always @(posedge clk)
if( rst ) begin
psgcnt48 <= 6'd0;
psgcnt240 <= 3'd0;
psgcnt144 <= 2'd0;
psgcnt1008<= 3'd0;
end else begin
psgcnt48 <= psgcnt48 ==6'd47 ? 6'd0 : psgcnt48 +6'd1;
if( psgcnt48 == 6'd47 ) begin
psgcnt240 <= psgcnt240==3'd4 ? 3'd0 : psgcnt240+3'd1;
psgcnt144 <= psgcnt144 ==2'd2 ? 2'd0 : psgcnt144+2'd1;
if( psgcnt144==2'd0 )
psgcnt1008 <= psgcnt1008==3'd6 ? 3'd0 : psgcnt1008+3'd1;
end
end
reg psg_cen_1008, psg_cen_240, psg_cen_48, psg_cen_144;
always @(posedge clk) begin
psg_cen_240 <= psgcnt48 ==6'd47 && psgcnt240 == 3'd0;
psg_cen_48 <= psgcnt48 ==6'd47;
psg_cen_144 <= psgcnt48 ==6'd47 && psgcnt144==2'd0;
psg_cen_1008<= psgcnt48 ==6'd47 && psgcnt144==2'd0 && psgcnt1008==3'd0;
end
wire signed [11:0] psg0, psg1, psg2, psg3;
assign psg0 = psg_en ? { psg_snd[10], psg_snd } : 12'b0;
// 48
jt12_interpol #(.calcw(19),.inw(12),.rate(5),.m(4),.n(2))
u_psg1(
.clk ( clk ),
.rst ( rst ),
.cen_in ( psg_cen_240 ),
.cen_out( psg_cen_48 ),
.snd_in ( psg0 ),
.snd_out( psg1 )
);
// 144
jt12_decim #(.calcw(19),.inw(12),.rate(3),.m(2),.n(3) )
u_psg2(
.clk ( clk ),
.rst ( rst ),
.cen_in ( psg_cen_48 ),
.cen_out( psg_cen_144 ),
.snd_in ( psg1 ),
.snd_out( psg2 )
);
// 1008
jt12_decim #(.calcw(15),.inw(12),.rate(7),.m(1),.n(1) )
u_psg3(
.clk ( clk ),
.rst ( rst ),
.cen_in ( psg_cen_144 ),
.cen_out( psg_cen_1008),
.snd_in ( psg2 ),
.snd_out( psg3 )
);
/////////////////////////////////////////////////
// FM
// x4 -> x4 -> x7 -> x9
// 54MHz count up to:
// 252 -> 63 -> 9 -> 1
reg [1:0] clkcnt252, clkcnt1008;
reg [2:0] clkcnt63;
reg [3:0] clkcnt9;
always @(posedge clk)
if( rst ) begin
clkcnt1008<= 2'd0;
clkcnt252 <= 2'd0;
clkcnt63 <= 3'd0;
clkcnt9 <= 4'd0;
end else begin
clkcnt9 <= clkcnt9 ==4'd8 ? 4'd0 : clkcnt9 +4'd1;
if( clkcnt9== 4'd8 ) begin
clkcnt63 <= clkcnt63 ==3'd6 ? 3'd0 : clkcnt63 +3'd1;
if( clkcnt63==3'd6 ) begin
clkcnt252 <= clkcnt252+2'd1;
if(clkcnt252==2'd3) clkcnt1008<=clkcnt1008+2'd1;
end
end
end
// evenly spaced clock enable signals
reg cen_1008, cen_252, cen_63, cen_9;
always @(posedge clk) begin
cen_9 <= clkcnt9 ==4'd8;
cen_63 <= clkcnt9 ==4'd8 && clkcnt63 ==3'd0;
cen_252 <= clkcnt9 ==4'd8 && clkcnt63 ==3'd0 && clkcnt252 ==2'd0;
cen_1008 <= clkcnt9 ==4'd8 && clkcnt63 ==3'd0 && clkcnt252 ==2'd0 && clkcnt1008==2'd0;
end
jt12_fm_uprate u_left(
.rst ( rst ),
.clk ( clk ),
.fm_snd ( fm_left ),
.psg_snd ( psg3 ),
.fm_en ( fm_en ),
.cen_1008 ( cen_1008 ),
.cen_252 ( cen_252 ),
.cen_63 ( cen_63 ),
.cen_9 ( cen_9 ),
.snd ( snd_left ) // Mixed sound at clk sample rate
);
jt12_fm_uprate u_right(
.rst ( rst ),
.clk ( clk ),
.fm_snd ( fm_right ),
.psg_snd ( psg3 ),
.fm_en ( fm_en ),
.cen_1008 ( cen_1008 ),
.cen_252 ( cen_252 ),
.cen_63 ( cen_63 ),
.cen_9 ( cen_9 ),
.snd ( snd_right ) // Mixed sound at clk sample rate
);
endmodule // jt12_genmix
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
|
module discus(input wire clk,
input wire reset,
output wire memory_read,
output wire memory_write,
output wire [7:0] memory_address,
output wire [7:0] memory_D,
input wire [7:0] memory_Q,
output bit [7:0] fetch_PC,
output bit fetch_reset,
input wire [7:0] fetch_instruction);
// Buffer the reset line a bit.
bit reset_input = 1;
always@(posedge clk) begin : reset_buffer
bit reset_io;
reset_io <= reset;
reset_input <= reset_io;
end
// Pipeline stages:
// Instruction fetch.
// Instruction decode.
// Execute.
// Commit.
//
// Instructions looking up memory do two cycles in Execute.
// Commit saves Z and result. (Execute writes C).
// Z has fast-forward processing in decode.
// Results of previous instructions have a fast-forward path into execute.
// decode_PC is 1+ the address of the instruction in decode.
// SP and the stack is updated by decode.
// Cflag is updated by exec.
// regs & Zflag is updated by commit.
bit [7:0] decode_PC;
bit [7:0] A;
bit Cflag;
bit Zflag;
bit [7:0] regs[0:3];
bit [7:0] stack[0:3];
bit fetch_prev_was_data;
bit [1:0] SP;
bit [7:0] return_PC;
// Instruction in decode; downstream uses the decoded flags.
bit [7:0] decode_instruction = 8'h80;
// For instruction decode only.
bit decode_is_branch;
bit [5:0] decode_prev_data;
bit decode_prev_was_data;
bit decode_not_mem_read = 1;
// For exec.
bit [7:0] exec_constant;
wire [7:0] exec_memB;
bit [1:0] exec_reg_to_write;
bit [1:0] exec_reg_to_read;
bit exec_reg_read;
bit exec_reg_ff;
bit exec_use_C;
bit exec_reg_write;
bit exec_C_write;
bit exec_Z_write;
bit exec_mem_read;
bit exec_mem_write;
bit [2:0] exec_op;
// For commit.
bit commit_Z_write;
bit commit_reg_write;
bit commit_reg_write_A;
bit [1:0] commit_reg_to_write;
bit [7:0] Q;
localparam Bpass = 0;
localparam AandB = 1;
localparam AorB = 2;
localparam AxorB = 3;
localparam AplusB = 4;
localparam AminusB = 5;
localparam Bplus1 = 6;
localparam Bminus1 = 7;
assign memory_address = effB;
assign memory_D = effA;
assign memory_read = exec_mem_read;
assign memory_write = exec_mem_write;
(* keep = "true" *)
bit decode_take_branch;
(* keep = "true" *)
bit conditionZ;
(* keep = "true" *)
bit conditionNZ;
always@(*) begin : decode_branch_evaluateZ
case (decode_instruction[4:3])
2'b00: conditionZ = !decode_instruction[2];
2'b01: conditionZ = !decode_instruction[2];
2'b10: conditionZ = (Zflag | commit_Z_write) ^ decode_instruction[2];
2'b11: conditionZ = Cflag ^ decode_instruction[2];
endcase
end
always@(*) begin : decode_branch_evaluateNZ
case (decode_instruction[4:3])
2'b00: conditionNZ = !decode_instruction[2];
2'b01: conditionNZ = !decode_instruction[2];
2'b10: conditionNZ = (Zflag & !commit_Z_write) ^ decode_instruction[2];
2'b11: conditionNZ = Cflag ^ decode_instruction[2];
endcase
end
always@(*) begin : decode_branch_evaluate2
bit [7:0] decode_branch_target;
decode_take_branch = decode_is_branch && ((Q == 0) ? conditionZ : conditionNZ);
if (decode_instruction[7])
decode_branch_target = return_PC;
else
decode_branch_target = { decode_instruction[1:0], decode_prev_data[5:0] };
if (decode_take_branch)
fetch_PC = decode_branch_target;
else if (decode_not_mem_read)
fetch_PC = decode_PC + 1;
else
fetch_PC = decode_PC;
end
always@(posedge clk) begin : fetch
if (fetch_instruction[7:6] == 2'b00 && fetch_prev_was_data)
decode_is_branch <= 1;
else if (fetch_instruction[4:3] == 2'b00)
decode_is_branch <= 0;
else if (fetch_instruction[7:5] == 3'b101)
decode_is_branch <= 1;
else
decode_is_branch <= 0;
// We can only update the SP every other clock cycle, so we can process
// the SP both in fetch & decode.
return_PC <= stack[SP];
decode_instruction <= fetch_instruction;
if (!fetch_prev_was_data && fetch_instruction[7:6] == 2'b00
&& decode_not_mem_read)
fetch_prev_was_data <= 1;
else
fetch_prev_was_data <= 0;
decode_prev_was_data <= fetch_prev_was_data;
// Work out if this instruction really does read memory. The memory read
// takes two cycles. For the second cycle in fetch (= first cycle in
// decode), the instruction is bogus and and we take care to ignore it.
if (fetch_instruction[7:6] == 2'b00
|| fetch_instruction[7:5] == 3'b101)
decode_not_mem_read <= 1;
else
decode_not_mem_read <= !fetch_instruction[2] | !decode_not_mem_read;
decode_PC <= fetch_PC;
if (reset_input)
fetch_reset <= 1;
else if (fetch_prev_was_data)
fetch_reset <= 0;
// In decode_mem_read the fetch instruction is bogus; we need to continue
// the previous instruction. So pause appropriate outputs.
if (!decode_not_mem_read) begin
decode_instruction <= decode_instruction;
decode_is_branch <= decode_is_branch;
end
// If we took a branch then the currently fetched instruction is bogus.
// Pass a NOP (mov A,A) through to decode.
if (decode_take_branch) begin
fetch_prev_was_data <= 0;
decode_not_mem_read <= 1;
decode_is_branch <= 0;
decode_instruction <= 8'h80;
end
end
always@(posedge clk) begin : decode
decode_prev_data <= decode_instruction[5:0];
if (!decode_take_branch)
SP <= SP;
else if (decode_instruction[7])
SP <= SP + 1; // For returns.
else if (decode_instruction[5])
SP <= SP; // Jumps.
else
SP <= SP - 1; // For calls.
// If we are taking a 'call' then write the stack.
if (decode_take_branch && !decode_instruction[7] && !decode_instruction[5])
stack[SP - 1] <= decode_PC;
if (decode_instruction[7])
exec_reg_to_write <= decode_instruction[4:3]; // Load / inc /dec.
else
exec_reg_to_write <= 2'b00; // ALU.
if (decode_instruction[7:6] != 2'b00
&& decode_instruction[7:3] != 5'b01111
&& decode_instruction[7:5] != 3'b101)
exec_reg_write <= decode_not_mem_read;
else
exec_reg_write <= 0;
if (decode_instruction[7:2] == 6'b101001)
exec_mem_write <= 1;
else
exec_mem_write <= 0;
// Arith operation...
if (decode_instruction[7:4] == 5'b0100)
exec_op <= AplusB;
else if (decode_instruction[7:4] == 5'b0101)
exec_op <= AminusB;
else if (decode_instruction[7:3] == 5'b01100)
exec_op <= AorB;
else if (decode_instruction[7:3] == 5'b01101)
exec_op <= AxorB;
else if (decode_instruction[7:3] == 5'b01110)
exec_op <= AandB;
else if (decode_instruction[7:3] == 5'b01111)
exec_op <= AminusB;
else if (decode_instruction[7:5] == 3'b110)
exec_op <= Bplus1;
else if (decode_instruction[7:5] == 3'b111)
exec_op <= Bminus1;
else
exec_op <= Bpass;
exec_use_C <= (decode_instruction[7:3] == 5'b01001 || decode_instruction[7:3] == 5'b01011);
// Work out the source of the 'B' input to the ALU. If can be any of:
// Constant.
// Memory read.
// Register read (normal).
// Register read (ff).
// For post-mem-read or using a constant, set exec_reg_read=0 and
// reg_to_read=0. The values are OR'd in.
if (exec_mem_read || decode_prev_was_data)
exec_reg_read <= 0;
else
exec_reg_read <= 1;
exec_reg_to_read <= decode_instruction[1:0];
if (exec_reg_write && exec_reg_to_write == decode_instruction[1:0])
exec_reg_ff <= 1;
else
exec_reg_ff <= 0;
if (decode_prev_was_data && !exec_mem_read)
exec_constant <= { decode_instruction[1:0], decode_prev_data };
else
exec_constant <= 0;
exec_mem_read <= !decode_not_mem_read;
exec_Z_write <= decode_instruction[6] && decode_not_mem_read;
exec_C_write <= (decode_instruction[7:6] == 2'b01) && decode_not_mem_read;
end
wire [7:0] effB;
wire [7:0] effA;
assign effB = exec_reg_read
? (exec_reg_ff ? Q : regs[exec_reg_to_read])
: exec_constant;
assign effA = commit_reg_write_A ? Q : A;
(* keep = "true" *)
bit [7:0] logicB0;
(* keep = "true" *)
bit [7:0] logicB1;
(* keep = "true" *)
bit [10:0] addendA;
always@(*) begin : addends
logicB0 = 0;
logicB1 = 8'b11111111;
addendA = 0;
case (exec_op)
AorB: logicB0 = effA;
AxorB: logicB0 = effA;
AminusB: logicB0 = 8'b11111111;
endcase
case (exec_op)
AandB: logicB1 = effA;
AxorB: logicB1 = ~effA;
AminusB: logicB1 = 0;
endcase
case (exec_op)
AplusB: addendA = { 2'b01, effA, 1'b1 };
AminusB: addendA = { 2'b01, effA, 1'b1 };
Bplus1: addendA = 11'b00000000010;
Bminus1: addendA = 11'b00111111110;
AandB: addendA = 11'b01000000000;
endcase
if (!exec_C_write) begin
addendA[10] = Cflag;
addendA[9] = 0;
end
end
always@(posedge clk) begin : exec
reg [10:0] addendB;
reg [10:0] sum;
addendB = { 2'b00,
((effB | memory_Q) & logicB1) | (~effB & ~memory_Q & logicB0), 1'b0 };
if (exec_op == AminusB)
addendB[0] = Cflag | !exec_use_C;
if (exec_op == AplusB)
addendB[0] = Cflag & exec_use_C;
if (exec_op == AandB)
addendB[9] = 1'b1;
// If we are not writing C, then overwrite logicA/B[9] to force preserving
// the previous value.
if (!exec_C_write)
addendB[9] = 0;
sum = addendA + addendB;
Q <= sum[8:1];
Cflag <= sum[10];
end
always@(posedge clk) begin : commit
commit_reg_write <= exec_reg_write;
commit_reg_to_write <= exec_reg_to_write;
commit_reg_write_A <= exec_reg_write && exec_reg_to_write == 0;
commit_Z_write <= exec_Z_write;
if (commit_reg_write)
regs[commit_reg_to_write] <= Q;
if (commit_reg_write_A)
A <= Q;
if (commit_Z_write)
Zflag <= (Q == 0);
end
endmodule
|
module step_ex_ts(clk, rst_, ena_, rdy_,
mode, r0_dout,
fl_din, fl_dout, fl_we_);
input clk;
input rst_;
input ena_;
output rdy_;
input[1:0] mode;
input[7:0] r0_dout;
output[7:0] fl_din;
input[7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
wire result = mode[1] ? mode[0] ? r0_dout[7] : r0_dout != 8'b0 : r0_dout[0];
reg fl_din_en;
assign fl_din = fl_din_en ? {fl_dout[7:1], result} : 8'bZ;
reg fl_we_en;
assign fl_we_ = fl_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
fl_din_en <= 1;
fl_we_en <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
fl_din_en <= 1;
fl_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
end
endmodule
|
// Power-on reset timer.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module por (
input clk,
output reg rst
);
reg [31:0] counter;
always @(posedge clk) begin
if (counter < 32'hffffff) begin
rst <= 1;
counter <= counter + 1;
end
else begin
rst <= 0;
end
end
endmodule
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d", u.core.decompressor.dmf_cnt);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im08_a.imf.cnt, u.core.im09_a.imf.cnt, u.core.im10_a.imf.cnt, u.core.im11_a.imf.cnt,
u.core.im12_a.imf.cnt, u.core.im13_a.imf.cnt, u.core.im14_a.imf.cnt, u.core.im15_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt,
u.core.im08_b.imf.cnt, u.core.im09_b.imf.cnt, u.core.im10_b.imf.cnt, u.core.im11_b.imf.cnt,
u.core.im12_b.imf.cnt, u.core.im13_b.imf.cnt, u.core.im14_b.imf.cnt, u.core.im15_b.imf.cnt);
$write("| %d %d", u.core.ob_a.compressor.tmp.cnt, u.core.ob_b.compressor.tmp.cnt);
$write("| %d %d|", u.core.ob_a.OB_cnt, u.core.ob_b.OB_cnt);
if (u.core.decompressor.dmf_cnt > (1<<`IB_SIZE)) begin $write("\noverflow at dc"); $finish(); end
if (u.core.im00_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_a"); $finish(); end
if (u.core.im01_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_a"); $finish(); end
if (u.core.im02_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_a"); $finish(); end
if (u.core.im03_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_a"); $finish(); end
if (u.core.im04_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_a"); $finish(); end
if (u.core.im05_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_a"); $finish(); end
if (u.core.im06_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_a"); $finish(); end
if (u.core.im07_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_a"); $finish(); end
if (u.core.im08_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im08_a"); $finish(); end
if (u.core.im09_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im09_a"); $finish(); end
if (u.core.im10_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im10_a"); $finish(); end
if (u.core.im11_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im11_a"); $finish(); end
if (u.core.im12_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im12_a"); $finish(); end
if (u.core.im13_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im13_a"); $finish(); end
if (u.core.im14_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im14_a"); $finish(); end
if (u.core.im15_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im15_a"); $finish(); end
if (u.core.im00_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_b"); $finish(); end
if (u.core.im01_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_b"); $finish(); end
if (u.core.im02_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_b"); $finish(); end
if (u.core.im03_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_b"); $finish(); end
if (u.core.im04_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im04_b"); $finish(); end
if (u.core.im05_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im05_b"); $finish(); end
if (u.core.im06_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im06_b"); $finish(); end
if (u.core.im07_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im07_b"); $finish(); end
if (u.core.im08_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im08_b"); $finish(); end
if (u.core.im09_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im09_b"); $finish(); end
if (u.core.im10_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im10_b"); $finish(); end
if (u.core.im11_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im11_b"); $finish(); end
if (u.core.im12_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im12_b"); $finish(); end
if (u.core.im13_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im13_b"); $finish(); end
if (u.core.im14_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im14_b"); $finish(); end
if (u.core.im15_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im15_b"); $finish(); end
if (u.core.ob_a.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_a.cmp"); $finish(); end
if (u.core.ob_b.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_b.cmp"); $finish(); end
if (u.core.ob_a.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_a"); $finish(); end
if (u.core.ob_b.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_b"); $finish(); end
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M %08x %08x ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
// wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
// (selector == 1) ? {r07,r06,r05,r04} :
// (selector == 2) ? {r11,r10,r09,r08} :
// (selector == 3) ? {r15,r14,r13,r12} : 0;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,(r01 % 32'd65536),(r00 % 32'd65536)} :
(selector == 1) ? {r07,(r06 % 32'd65536),r05,(r04 % 32'd65536)} :
(selector == 2) ? {r11,(r10 % 32'd65536),r09,(r08 % 32'd65536)} :
(selector == 3) ? {(r15 % 32'd65536),(r14 % 32'd65536),r13,(r12 % 32'd65536)} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_1_V
`define SKY130_FD_SC_HS__FA_1_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
/*
-- Module Name: Data Path
-- Description: Camino de datos. Top level para la instancia de los
elementos que manejan datos a travez del router.
-- Dependencies: -- system.vh
-- input_queue.v x 4
-- switch_fabric.v x 1
-- Parameters: -- {X_POS, Y_POS, X_NEG, Y_NEG, PE} Identificador
asignado a cada direccion de IO del router. El
identificador es utilizado como medio para
realizar las conexiones correctas en los ciclos
for : generate durante la instancia de sub
modulos.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 05 de Junio 2015: Creacion
-- 11 de Junio 2015: + Puertos de salida 'buffer_xxxx_dout' para
comunicarse con el control path.
-- 14 de Junio 2015: + Puerto de salida de buffer para arbitraje
en PE. Se agrego señales de control
(read/write_strobe) para buffer de PE.
Se Anexo al vector outgoing_flit el
elemeto para reresentar la salida del
buffer de PE.
*/
`include "system.vh"
module data_path
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire [`CHANNEL_WIDTH-1:0] channel_xpos_din,
input wire [`CHANNEL_WIDTH-1:0] channel_ypos_din,
input wire [`CHANNEL_WIDTH-1:0] channel_xneg_din,
input wire [`CHANNEL_WIDTH-1:0] channel_yneg_din,
input wire [`CHANNEL_WIDTH-1:0] channel_pe_din,
input wire [4:0] write_strobe_din,
input wire [4:0] read_strobe_din,
input wire [3:0] xbar_conf_vector_xpos_din,
input wire [3:0] xbar_conf_vector_ypos_din,
input wire [3:0] xbar_conf_vector_xneg_din,
input wire [3:0] xbar_conf_vector_yneg_din,
input wire [3:0] xbar_conf_vector_pe_din,
// -- output ------------------------------------------------- >>>>>
output wire [29:24] buffer_xpos_dout,
output wire [29:24] buffer_ypos_dout,
output wire [29:24] buffer_xneg_dout,
output wire [29:24] buffer_yneg_dout,
output wire [29:24] buffer_pe_dout,
output wire done_buffer_xpos_dout,
output wire done_buffer_ypos_dout,
output wire done_buffer_xneg_dout,
output wire done_buffer_yneg_dout,
output wire done_buffer_pe_dout,
output wire [`CHANNEL_WIDTH-1:0] channel_xpos_dout,
output wire [`CHANNEL_WIDTH-1:0] channel_ypos_dout,
output wire [`CHANNEL_WIDTH-1:0] channel_xneg_dout,
output wire [`CHANNEL_WIDTH-1:0] channel_yneg_dout,
output wire [`CHANNEL_WIDTH-1:0] channel_pe_dout
);
/*
-- Instancia :: Buffers de Entrada (Input Queue)
-- Descripcion: Colas de almacenamiento ligadas a cada puerto de entrada
. Las señales de control para operaciones de lectura/
escritura provienen del camino de control del router, en
especifico del modulo 'control de enlace'.
Los canales de entrada se agrupan en el arreglo
'input_channels' para poder ser conectados de manera
automatica en el loop - generate.
*/
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Consolidacion de Canalas de Entrada ---------------- >>>>>
wire [`CHANNEL_WIDTH-1:0] input_channels [4:0];
assign input_channels[`X_POS] = channel_xpos_din;
assign input_channels[`Y_POS] = channel_ypos_din;
assign input_channels[`X_NEG] = channel_xneg_din;
assign input_channels[`Y_NEG] = channel_yneg_din;
assign input_channels[`PE] = channel_pe_din;
// -- Salida :: Flit a la Salida del Buffer -------------- >>>>>
wire [`CHANNEL_WIDTH-1:0] outgoing_flit [4:0];
wire [4:0] full_flag;
wire [4:0] empty_flag;
// -- Intancias :: Input Queue ------------------------------- >>>>>
/* -- Nota : No se crea instancia de Queue para PE por que el
medio de almacenamiento se encuentra dentro de la
unidad funcional.
*/
genvar index;
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: input_queue
fifo buffer_de_paquetes
(
.clk(clk),
.reset(reset),
// -- inputs ------------------------- >>>>>
.write_strobe_din (write_strobe_din[index]),
.read_strobe_din (read_strobe_din[index]),
.write_data_din (input_channels[index]),
// -- outputs ------------------------ >>>>>
.full_dout (full_flag[index]),
.empty_dout (empty_flag[index]),
.read_data_dout (outgoing_flit[index])
);
end
endgenerate
assign buffer_xpos_dout = outgoing_flit[`X_POS][29:24];
assign buffer_ypos_dout = outgoing_flit[`Y_POS][29:24];
assign buffer_xneg_dout = outgoing_flit[`X_NEG][29:24];
assign buffer_yneg_dout = outgoing_flit[`Y_NEG][29:24];
assign buffer_pe_dout = outgoing_flit[`PE][29:24];
assign done_buffer_xpos_dout = outgoing_flit[`X_POS][30];
assign done_buffer_ypos_dout = outgoing_flit[`Y_POS][30];
assign done_buffer_xneg_dout = outgoing_flit[`X_NEG][30];
assign done_buffer_yneg_dout = outgoing_flit[`Y_NEG][30];
assign done_buffer_pe_dout = outgoing_flit[`PE][30];
/*
-- Instancia :: Medio de Interconexion del router
-- Descripcion: Crossbar para la conexion de puertos de entrada con
puertos de salida. El diseño consiste en un conjunto
de multiplexores para permitir el paso de los datos
provenientes de una de las colas de almacenamiento en
direccion de un puerto de salida.
Las señales de control para los multiplexores provienen
del camino de contol, en especifico de los modulos
'planificador de salida.'
*/
// -- Instancia :: SF ---------------------------------------- >>>>>
switch_fabric xbar
(
.clk (clk),
.reset (reset),
// -- input ------------------------------------------ >>>>>
.inport_xpos_din (outgoing_flit[`X_POS]),
.inport_ypos_din (outgoing_flit[`Y_POS]),
.inport_xneg_din (outgoing_flit[`X_NEG]),
.inport_yneg_din (outgoing_flit[`Y_NEG]),
.inport_pe_din (outgoing_flit[`PE]),
.conf_xpos_din (xbar_conf_vector_xpos_din),
.conf_ypos_din (xbar_conf_vector_ypos_din),
.conf_xneg_din (xbar_conf_vector_xneg_din),
.conf_yneg_din (xbar_conf_vector_yneg_din),
.conf_pe_din (xbar_conf_vector_pe_din),
// -- output ----------------------------------------- >>>>>
.outport_xpos_dout (channel_xpos_dout),
.outport_ypos_dout (channel_ypos_dout),
.outport_xneg_dout (channel_xneg_dout),
.outport_yneg_dout (channel_yneg_dout),
.outport_pe_dout (channel_pe_dout)
);
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
data_path camino_de_datos
(
.clk (clk),
.reset (reset),
// -- input -------------------------------------------------- >>>>>
.channel_xpos_din (channel_xpos_din),
.channel_ypos_din (channel_ypos_din),
.channel_xneg_din (channel_xneg_din),
.channel_yneg_din (channel_yneg_din),
.channel_pe_din (channel_pe_din),
.write_strobe_din (write_strobe_din),
.read_strobe_din (read_strobe_din),
.xbar_conf_vector_xpos_din (xbar_conf_vector_xpos_din),
.xbar_conf_vector_ypos_din (xbar_conf_vector_ypos_din),
.xbar_conf_vector_xneg_din (xbar_conf_vector_xneg_din),
.xbar_conf_vector_yneg_din (xbar_conf_vector_yneg_din),
.xbar_conf_vector_pe_din (xbar_conf_vector_pe_din),
// -- output ------------------------------------------------- >>>>>
.buffer_xpos_dout (buffer_xpos_dout),
.buffer_ypos_dout (buffer_ypos_dout),
.buffer_xneg_dout (buffer_xneg_dout),
.buffer_yneg_dout (buffer_yneg_dout),
.buffer_pe_dout (buffer_pe_dout),
.done_buffer_xpos_dout (done_buffer_xpos_dout),
.done_buffer_ypos_dout (done_buffer_ypos_dout),
.done_buffer_xneg_dout (done_buffer_xneg_dout),
.done_buffer_yneg_dout (done_buffer_yneg_dout),
.done_buffer_pe_dout (done_buffer_pe_dout),
.channel_xpos_dout (channel_xpos_dout),
.channel_ypos_dout (channel_ypos_dout),
.channel_xneg_dout (channel_xneg_dout),
.channel_yneg_dout (channel_yneg_dout),
.channel_pe_dout (channel_pe_dout)
);
*/
|
`timescale 1ns / 1ps
//**********************************************************************
// File: spi_master.v
// Module:spi_master
// by Robin zhang
//**********************************************************************
module spi_master(
clk,rst_n,
spi_miso,spi_mosi,spi_clk,
spi_tx_en,spi_rx_en,spi_over,mode_select,receive_status,
cs
);
input clk;
input rst_n;
input spi_miso;
output spi_mosi;
output spi_clk;
output cs;
input spi_tx_en;
output spi_over;
output receive_status;
input spi_rx_en;
input mode_select;
reg[7:0] data_count;
reg[7:0] recv_detect;
reg[7:0] spi_tx_db;
reg[4:0] cnt8;
reg spi_clkr;
reg spi_mosir;
reg spi_mosir1;
reg receive_status;
reg[7:0] spi_rx_dbr;
reg[7:0] spi_rx_dbr1;
reg frame_delay;
reg start_delay;
reg cs;
reg[7:0] frame_delay_cnt;
reg[7:0] start_delay_cnt;
wire[7:0] spi_rx_db;
wire[4:0] mode_reg;
wire[4:0] start_reg;
/***********************************************************************
*detect spi mode
***********************************************************************/
assign mode_reg = mode_select ? 5'd18 : 5'd17;
assign start_reg = mode_select ? 5'd1 : 5'd0;
/***********************************************************************
*control the spi timimg
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt8 <= 5'd0;
data_count <= 8'h0;
spi_tx_db <= 8'h0;
recv_detect <= 8'h0;
cs <= 1'b1;
end
else if((spi_tx_en || spi_rx_en) && (data_count < 8'd64) && (start_delay == 1'b1)) begin
if(cnt8 < mode_reg)begin
cnt8 <= cnt8+1'b1;
cs <= 1'b0;
end
else begin
if(spi_tx_en && spi_rx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
else begin
if(spi_tx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
end
else if(frame_delay == 1'b0) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
end
end
end
else begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count;
end
end
/***********************************************************************
*start delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
start_delay <= 1'b0;
start_delay_cnt <= 'h0;
end
else begin
if((spi_tx_en || spi_rx_en) && (start_delay_cnt < 'd250))begin
start_delay_cnt <= start_delay_cnt + 1'b1;
end
else begin
start_delay <= 1'b1;
end
end
end
/***********************************************************************
*frame to frame delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
frame_delay <= 1'b1;
frame_delay_cnt <= 'h0;
end
else begin
if((cnt8 >= (mode_reg - 1'b1)) && (frame_delay_cnt < 'd250))begin
frame_delay <= 1'b1;
frame_delay_cnt <= frame_delay_cnt + 1'b1;
end
else begin
frame_delay <= 1'b0;
frame_delay_cnt <= 'h0;
end
end
end
/***********************************************************************
*generate spi clk
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_clkr <= mode_select ? 1'b1 : 1'b0;
else if(cnt8 > start_reg && cnt8 < mode_reg)
spi_clkr <= ~spi_clkr;
else
spi_clkr <= spi_clkr;
end
assign spi_clk = spi_clkr;
/***********************************************************************
*spi master output data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd0: spi_mosir <= spi_tx_db[7];
4'd1: spi_mosir <= spi_tx_db[6];
4'd2: spi_mosir <= spi_tx_db[5];
4'd3: spi_mosir <= spi_tx_db[4];
4'd4: spi_mosir <= spi_tx_db[3];
4'd5: spi_mosir <= spi_tx_db[2];
4'd6: spi_mosir <= spi_tx_db[1];
4'd7: spi_mosir <= spi_tx_db[0];
default: spi_mosir <= 1'b1;
endcase
end
else
spi_mosir <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir1 <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd1: spi_mosir1 <= spi_tx_db[7];
4'd2: spi_mosir1 <= spi_tx_db[6];
4'd3: spi_mosir1 <= spi_tx_db[5];
4'd4: spi_mosir1 <= spi_tx_db[4];
4'd5: spi_mosir1 <= spi_tx_db[3];
4'd6: spi_mosir1 <= spi_tx_db[2];
4'd7: spi_mosir1 <= spi_tx_db[1];
4'd8: spi_mosir1 <= spi_tx_db[0];
default: spi_mosir1 <= 1'b1;
endcase
end
else
spi_mosir1 <= 1'b1;
end
assign spi_mosi = mode_select ? spi_mosir1 : spi_mosir;
/***********************************************************************
*spi master input data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd1: spi_rx_dbr[7] <= spi_miso;
5'd3: spi_rx_dbr[6] <= spi_miso;
5'd5: spi_rx_dbr[5] <= spi_miso;
5'd7: spi_rx_dbr[4] <= spi_miso;
5'd9: spi_rx_dbr[3] <= spi_miso;
5'd11: spi_rx_dbr[2] <= spi_miso;
5'd13: spi_rx_dbr[1] <= spi_miso;
5'd15: spi_rx_dbr[0] <= spi_miso;
default: spi_rx_dbr <= spi_rx_dbr;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr1 <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd3: spi_rx_dbr1[7] <= spi_miso;
5'd5: spi_rx_dbr1[6] <= spi_miso;
5'd7: spi_rx_dbr1[5] <= spi_miso;
5'd9: spi_rx_dbr1[4] <= spi_miso;
5'd11: spi_rx_dbr1[3] <= spi_miso;
5'd13: spi_rx_dbr1[2] <= spi_miso;
5'd15: spi_rx_dbr1[1] <= spi_miso;
5'd17: spi_rx_dbr1[0] <= spi_miso;
default: spi_rx_dbr1 <= spi_rx_dbr1;
endcase
end
end
assign spi_rx_db = mode_select ? spi_rx_dbr1 : spi_rx_dbr;
assign spi_over = (data_count == 8'd64) ? 1'b1 :1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <= (recv_detect == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
|
`timescale 1ns / 1ps
module pcie_2_0_ep #(
parameter PL_FAST_TRAIN = "FALSE"
)
(
output [7:0] pci_exp_txp,
output [7:0] pci_exp_txn,
input [7:0] pci_exp_rxp,
input [7:0] pci_exp_rxn,
output fifo_clk,
input CMGFTL_cmd_fifo_full_i,
input CMGFTL_cmd_fifo_almost_full_i,
output CMGFTL_cmd_fifo_wr_en_o,
output [127:0] CMGFTL_cmd_fifo_data_o,
input FTLCMG_cmd_fifo_empty_i,
input FTLCMG_cmd_fifo_almost_empty_i,
output FTLCMG_cmd_fifo_rd_en_o,
input [127:0] FTLCMG_cmd_fifo_data_i,
input RX_data_fifo_full_i,
input RX_data_fifo_almost_full_i,
output RX_data_fifo_wr_en_o,
output [127:0] RX_data_fifo_data_o,
input RX_data_fifo_av_i,
input TX_data_fifo_empty_i,
input TX_data_fifo_almost_empty_i,
output TX_data_fifo_rd_en_o,
input [127:0] TX_data_fifo_data_i,
`ifdef ENABLE_LEDS
output led_0,
output led_1,
output led_2,
`endif
input sys_clk_p,
input sys_clk_n,
input sys_reset_n
);
wire trn_clk;
wire trn_reset_n;
wire trn_lnk_up_n;
// Tx
wire [5:0] trn_tbuf_av;
wire trn_tcfg_req_n;
wire trn_terr_drop_n;
wire trn_tdst_rdy_n;
wire [127:0] trn_td;
wire [1:0] trn_trem_n;
wire trn_tsof_n;
wire trn_teof_n;
wire trn_tsrc_rdy_n;
wire trn_tsrc_dsc_n;
wire trn_terrfwd_n;
wire trn_tcfg_gnt_n;
wire trn_tstr_n;
// Rx
wire [127:0] trn_rd;
wire [1:0] trn_rrem_n;
wire trn_rsof_n;
wire trn_reof_n;
wire trn_rsrc_rdy_n;
wire trn_rsrc_dsc_n;
wire trn_rerrfwd_n;
wire [6:0] trn_rbar_hit_n;
wire trn_rdst_rdy_n;
wire trn_rnp_ok_n;
// Flow Control
wire [11:0] trn_fc_cpld;
wire [7:0] trn_fc_cplh;
wire [11:0] trn_fc_npd;
wire [7:0] trn_fc_nph;
wire [11:0] trn_fc_pd;
wire [7:0] trn_fc_ph;
wire [2:0] trn_fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire [31:0] cfg_do;
wire cfg_rd_wr_done_n;
wire [31:0] cfg_di;
wire [3:0] cfg_byte_en_n;
wire [9:0] cfg_dwaddr;
wire cfg_wr_en_n;
wire cfg_rd_en_n;
wire cfg_err_cor_n;
wire cfg_err_ur_n;
wire cfg_err_ecrc_n;
wire cfg_err_cpl_timeout_n;
wire cfg_err_cpl_abort_n;
wire cfg_err_cpl_unexpect_n;
wire cfg_err_posted_n;
wire cfg_err_locked_n;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy_n;
wire cfg_interrupt_n;
wire cfg_interrupt_rdy_n;
wire cfg_interrupt_assert_n;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_turnoff_ok_n;
wire cfg_to_turnoff_n;
wire cfg_trn_pending_n;
wire cfg_pm_wake_n;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state_n;
wire [63:0] cfg_dsn;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_capable;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_capable;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_link_rate;
wire [1:0] pl_sel_link_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_clk_c;
wire sys_reset_n_c;
assign fifo_clk = trn_clk;
//-------------------------------------------------------
IBUFDS_GTXE1 refclk_ibuf (.O(sys_clk_c), .ODIV2(), .I(sys_clk_p), .IB(sys_clk_n), .CEB(1'b0));
IBUF sys_reset_n_ibuf (.O(sys_reset_n_c), .I(sys_reset_n));
`ifdef ENABLE_LEDS
OBUF led_0_obuf (.O(led_0), .I(sys_reset_n_c));
OBUF led_1_obuf (.O(led_1), .I(trn_reset_n));
OBUF led_2_obuf (.O(led_2), .I(trn_lnk_up_n));
`endif
FDCP #(
.INIT(1'b1)
) trn_lnk_up_n_int_i (
.Q (trn_lnk_up_n),
.D (trn_lnk_up_n_int1),
.C (trn_clk),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) trn_reset_n_i (
.Q (trn_reset_n),
.D (trn_reset_n_int1),
.C (trn_clk),
.CLR (1'b0),
.PRE (1'b0)
);
v6_pcie_v1_7 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN )
)
core (
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
.pci_exp_txp( pci_exp_txp ),
.pci_exp_txn( pci_exp_txn ),
// Rx
.pci_exp_rxp( pci_exp_rxp ),
.pci_exp_rxn( pci_exp_rxn ),
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
.trn_clk( trn_clk ),
.trn_reset_n( trn_reset_n_int1 ),
.trn_lnk_up_n( trn_lnk_up_n_int1 ),
// Tx
.trn_tbuf_av( trn_tbuf_av ),
.trn_terr_drop_n( trn_terr_drop_n ),
.trn_tdst_rdy_n( trn_tdst_rdy_n ),
.trn_td( trn_td ),
.trn_trem_n( trn_trem_n ),
.trn_tsof_n( trn_tsof_n ),
.trn_teof_n( trn_teof_n ),
.trn_tsrc_rdy_n( trn_tsrc_rdy_n ),
.trn_tsrc_dsc_n( trn_tsrc_dsc_n ),
.trn_terrfwd_n( trn_terrfwd_n ),
.trn_tstr_n( trn_tstr_n ),
// Rx
.trn_rd( trn_rd ),
.trn_rrem_n( trn_rrem_n ),
.trn_rsof_n( trn_rsof_n ),
.trn_reof_n( trn_reof_n ),
.trn_rsrc_rdy_n( trn_rsrc_rdy_n ),
.trn_rsrc_dsc_n( trn_rsrc_dsc_n ),
.trn_rerrfwd_n( trn_rerrfwd_n ),
.trn_rbar_hit_n( trn_rbar_hit_n ),
.trn_rdst_rdy_n( trn_rdst_rdy_n ),
.trn_rnp_ok_n( trn_rnp_ok_n ),
// Flow Control
.trn_fc_cpld( trn_fc_cpld ),
.trn_fc_cplh( trn_fc_cplh ),
.trn_fc_npd( trn_fc_npd ),
.trn_fc_nph( trn_fc_nph ),
.trn_fc_pd( trn_fc_pd ),
.trn_fc_ph( trn_fc_ph ),
.trn_fc_sel( trn_fc_sel ),
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
.cfg_do( cfg_do ),
.cfg_rd_wr_done_n( cfg_rd_wr_done_n),
.cfg_di( cfg_di ),
.cfg_byte_en_n( cfg_byte_en_n ),
.cfg_dwaddr( cfg_dwaddr ),
.cfg_wr_en_n( cfg_wr_en_n ),
.cfg_rd_en_n( cfg_rd_en_n ),
.cfg_err_cor_n( cfg_err_cor_n ),
.cfg_err_ur_n( cfg_err_ur_n ),
.cfg_err_ecrc_n( cfg_err_ecrc_n ),
.cfg_err_cpl_timeout_n( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_abort_n( cfg_err_cpl_abort_n ),
.cfg_err_cpl_unexpect_n( cfg_err_cpl_unexpect_n ),
.cfg_err_posted_n( cfg_err_posted_n ),
.cfg_err_locked_n( cfg_err_locked_n ),
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy_n( cfg_err_cpl_rdy_n ),
.cfg_interrupt_n( cfg_interrupt_n ),
.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n ),
.cfg_interrupt_assert_n( cfg_interrupt_assert_n ),
.cfg_interrupt_di( cfg_interrupt_di ),
.cfg_interrupt_do( cfg_interrupt_do ),
.cfg_interrupt_mmenable( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm( cfg_interrupt_msixfm ),
.cfg_turnoff_ok_n( cfg_turnoff_ok_n ),
.cfg_to_turnoff_n( cfg_to_turnoff_n ),
.cfg_trn_pending_n( cfg_trn_pending_n ),
.cfg_pm_wake_n( cfg_pm_wake_n ),
.cfg_bus_number( cfg_bus_number ),
.cfg_device_number( cfg_device_number ),
.cfg_function_number( cfg_function_number ),
.cfg_status( cfg_status ),
.cfg_command( cfg_command ),
.cfg_dstatus( cfg_dstatus ),
.cfg_dcommand( cfg_dcommand ),
.cfg_lstatus( cfg_lstatus ),
.cfg_lcommand( cfg_lcommand ),
.cfg_dcommand2( cfg_dcommand2 ),
.cfg_pcie_link_state_n( cfg_pcie_link_state_n ),
.cfg_dsn( cfg_dsn ),
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
.pl_initial_link_width( pl_initial_link_width ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_received_hot_rst( pl_received_hot_rst ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_directed_link_change( pl_directed_link_change ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph ),
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
.sys_clk( sys_clk_c ),
.sys_reset_n( sys_reset_n_c )
);
pcie_app_v6 app (
//-------------------------------------------------------
// 1. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
.trn_clk( trn_clk ),
.trn_reset_n( trn_reset_n_int1 ),
.trn_lnk_up_n( trn_lnk_up_n_int1 ),
// Tx
.trn_tbuf_av( trn_tbuf_av ),
.trn_tcfg_req_n( trn_tcfg_req_n ),
.trn_terr_drop_n( trn_terr_drop_n ),
.trn_tdst_rdy_n( trn_tdst_rdy_n ),
.trn_td( trn_td ),
.trn_trem_n( trn_trem_n ),
.trn_tsof_n( trn_tsof_n ),
.trn_teof_n( trn_teof_n ),
.trn_tsrc_rdy_n( trn_tsrc_rdy_n ),
.trn_tsrc_dsc_n( trn_tsrc_dsc_n ),
.trn_terrfwd_n( trn_terrfwd_n ),
.trn_tcfg_gnt_n( trn_tcfg_gnt_n ),
.trn_tstr_n( trn_tstr_n ),
// Rx
.trn_rd( trn_rd ),
.trn_rrem_n( trn_rrem_n ),
.trn_rsof_n( trn_rsof_n ),
.trn_reof_n( trn_reof_n ),
.trn_rsrc_rdy_n( trn_rsrc_rdy_n ),
.trn_rsrc_dsc_n( trn_rsrc_dsc_n ),
.trn_rerrfwd_n( trn_rerrfwd_n ),
.trn_rbar_hit_n( trn_rbar_hit_n ),
.trn_rdst_rdy_n( trn_rdst_rdy_n ),
.trn_rnp_ok_n( trn_rnp_ok_n ),
// Flow Control
.trn_fc_cpld( trn_fc_cpld ),
.trn_fc_cplh( trn_fc_cplh ),
.trn_fc_npd( trn_fc_npd ),
.trn_fc_nph( trn_fc_nph ),
.trn_fc_pd( trn_fc_pd ),
.trn_fc_ph( trn_fc_ph ),
.trn_fc_sel( trn_fc_sel ),
.CMGFTL_cmd_fifo_full_i(CMGFTL_cmd_fifo_full_i),
.CMGFTL_cmd_fifo_almost_full_i(CMGFTL_cmd_fifo_almost_full_i),
.CMGFTL_cmd_fifo_wr_en_o(CMGFTL_cmd_fifo_wr_en_o),
.CMGFTL_cmd_fifo_data_o(CMGFTL_cmd_fifo_data_o),
.FTLCMG_cmd_fifo_empty_i(FTLCMG_cmd_fifo_empty_i),
.FTLCMG_cmd_fifo_almost_empty_i(FTLCMG_cmd_fifo_almost_empty_i),
.FTLCMG_cmd_fifo_rd_en_o(FTLCMG_cmd_fifo_rd_en_o),
.FTLCMG_cmd_fifo_data_i(FTLCMG_cmd_fifo_data_i),
.RX_data_fifo_full_i(RX_data_fifo_full_i),
.RX_data_fifo_almost_full_i(RX_data_fifo_almost_full_i),
.RX_data_fifo_wr_en_o(RX_data_fifo_wr_en_o),
.RX_data_fifo_data_o(RX_data_fifo_data_o),
.RX_data_fifo_av_i(RX_data_fifo_av_i),
.TX_data_fifo_empty_i(TX_data_fifo_empty_i),
.TX_data_fifo_almost_empty_i(TX_data_fifo_almost_empty_i),
.TX_data_fifo_rd_en_o(TX_data_fifo_rd_en_o),
.TX_data_fifo_data_i(TX_data_fifo_data_i),
//-------------------------------------------------------
// 2. Configuration (CFG) Interface
//-------------------------------------------------------
.cfg_do( cfg_do ),
.cfg_rd_wr_done_n( cfg_rd_wr_done_n),
.cfg_di( cfg_di ),
.cfg_byte_en_n( cfg_byte_en_n ),
.cfg_dwaddr( cfg_dwaddr ),
.cfg_wr_en_n( cfg_wr_en_n ),
.cfg_rd_en_n( cfg_rd_en_n ),
.cfg_err_cor_n( cfg_err_cor_n ),
.cfg_err_ur_n( cfg_err_ur_n ),
.cfg_err_ecrc_n( cfg_err_ecrc_n ),
.cfg_err_cpl_timeout_n( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_abort_n( cfg_err_cpl_abort_n ),
.cfg_err_cpl_unexpect_n( cfg_err_cpl_unexpect_n ),
.cfg_err_posted_n( cfg_err_posted_n ),
.cfg_err_locked_n( cfg_err_locked_n ),
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy_n( cfg_err_cpl_rdy_n ),
.cfg_interrupt_n( cfg_interrupt_n ),
.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n ),
.cfg_interrupt_assert_n( cfg_interrupt_assert_n ),
.cfg_interrupt_di( cfg_interrupt_di ),
.cfg_interrupt_do( cfg_interrupt_do ),
.cfg_interrupt_mmenable( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm( cfg_interrupt_msixfm ),
.cfg_turnoff_ok_n( cfg_turnoff_ok_n ),
.cfg_to_turnoff_n( cfg_to_turnoff_n ),
.cfg_trn_pending_n( cfg_trn_pending_n ),
.cfg_pm_wake_n( cfg_pm_wake_n ),
.cfg_bus_number( cfg_bus_number ),
.cfg_device_number( cfg_device_number ),
.cfg_function_number( cfg_function_number ),
.cfg_status( cfg_status ),
.cfg_command( cfg_command ),
.cfg_dstatus( cfg_dstatus ),
.cfg_dcommand( cfg_dcommand ),
.cfg_lstatus( cfg_lstatus ),
.cfg_lcommand( cfg_lcommand ),
.cfg_dcommand2( cfg_dcommand2 ),
.cfg_pcie_link_state_n( cfg_pcie_link_state_n ),
.cfg_dsn( cfg_dsn ),
//-------------------------------------------------------
// 3. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
.pl_initial_link_width( pl_initial_link_width ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_received_hot_rst( pl_received_hot_rst ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_directed_link_change( pl_directed_link_change ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph )
);
endmodule
|
// megafunction wizard: %ALTFP_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_add_sub
// ============================================================
// File Name: altfp_add_sub0.v
// Megafunction Name(s):
// altfp_add_sub
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module altfp_add_sub0 (
aclr,
clock,
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input aclr;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altfp_add_sub0_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
Distributed under the MIT license.
Copyright (c) 2017 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes: Who? What?
* XX/XX/XXXX XXX XXXX
*/
`timescale 1ps / 1ps
module TEMPLATE (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
`default_nettype none
module pulse_gen(
input clk, // 12 MHz base clock
input clk_pll,
input RS232_Rx, // Receive pin for the FTDI chip
// input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output Block
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
wire [23:0] period;
wire [15:0] p1width;
wire [15:0] delay;
wire [15:0] p2width;
wire block;
wire [7:0] pulse_block;
// wire [15:0] pulse_block_off;
wire cpmg;
wire rx_done;
// wire [6:0] pre_att;
// wire [6:0] post_att;
// Setting up communications with LabView over USB
pulse_control control(
.clk(clk),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
// .p_bl(pulse_block),
// .p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done)
);
// Generating the necessary pulses
pulses pulses(
.clk_pll(clk_pll),
.clk(clk),
// .reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
// .p_bl(pulse_block),
// .p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(Block)
// .test({FM, P3, P4})
);
endmodule // pulse_gen
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone V" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEV" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=32 aclr0 clock0 dataa datab ena0 result
//VERSION_BEGIN 15.0 cbx_altera_mult_add 2015:04:15:19:11:38:SJ cbx_altera_mult_add_rtl 2015:04:15:19:11:38:SJ cbx_mgl 2015:04:15:20:18:26:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_37p2
(
aclr0,
clock0,
dataa,
datab,
ena0,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
input ena0;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.negate(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_adder_direction = "ADD",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.latency = 0,
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.negate_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.negate_register = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_negate = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone V",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.use_subnadd = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_37p2
//VALID FILE
|
/*********************************************************************
* SAED_EDK90nm_SRAM : SRAM2RW128x8 Verilog description *
* --------------------------------------------------------------- *
* Filename : SRAM2RW128x8.v *
* SRAM name : SRAM2RW128x8 *
* Word width : 8 bits *
* Word number : 128 *
* Adress width : 7 bits *
**********************************************************************/
`timescale 1ns/100fs
`define numAddr 7
`define numWords 128
`define wordLength 8
module SRAM2RW128x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
input CE1;
input CE2;
input WEB1;
input WEB2;
input OEB1;
input OEB2;
input CSB1;
input CSB2;
input [`numAddr-1:0] A1;
input [`numAddr-1:0] A2;
input [`wordLength-1:0] I1;
input [`wordLength-1:0] I2;
output [`wordLength-1:0] O1;
output [`wordLength-1:0] O2;
/*reg [`wordLength-1:0] memory[`numWords-1:0];*/
/*reg [`wordLength-1:0] data_out1;*/
/*reg [`wordLength-1:0] data_out2;*/
wire [`wordLength-1:0] O1;
wire [`wordLength-1:0] O2;
wire RE1;
wire RE2;
wire WE1;
wire WE2;
SRAM2RW128x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
SRAM2RW128x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
SRAM2RW128x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
SRAM2RW128x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
SRAM2RW128x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
SRAM2RW128x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
SRAM2RW128x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
SRAM2RW128x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2, A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
endmodule
module SRAM2RW128x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i, A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
input CSB1_i, CSB2_i;
input OEB1_i, OEB2_i;
input CE1_i, CE2_i;
input WEB1_i, WEB2_i;
input [`numAddr-1:0] A1_i, A2_i;
input [0:0] I1_i, I2_i;
output [0:0] O1_i, O2_i;
reg [0:0] O1_i, O2_i;
reg [0:0] memory[`numWords-1:0];
reg [0:0] data_out1, data_out2;
and u1 (RE1, ~CSB1_i, WEB1_i);
and u2 (WE1, ~CSB1_i, ~WEB1_i);
and u3 (RE2, ~CSB2_i, WEB2_i);
and u4 (WE2, ~CSB2_i, ~WEB2_i);
//Primary ports
always @ (posedge CE1_i)
if (RE1)
data_out1 = memory[A1_i];
always @ (posedge CE1_i)
if (WE1)
memory[A1_i] = I1_i;
always @ (data_out1 or OEB1_i)
if (!OEB1_i)
O1_i = data_out1;
else
O1_i = 1'bz;
//Dual ports
always @ (posedge CE2_i)
if (RE2)
data_out2 = memory[A2_i];
always @ (posedge CE2_i)
if (WE2)
memory[A2_i] = I2_i;
always @ (data_out2 or OEB2_i)
if (!OEB2_i)
O2_i = data_out2;
else
O2_i = 1'bz;
endmodule
|
//
// timing.v -- timing generator
//
module timing(clk, pixclk,
txtrow, txtcol,
chrrow, chrcol,
blank, hsync, vsync, blink);
input clk;
output pixclk;
output [4:0] txtrow;
output [6:0] txtcol;
output [3:0] chrrow;
output [2:0] chrcol;
output blank;
output hsync;
output vsync;
output reg blink;
reg pclk;
reg [9:0] hcnt;
reg hblank, hsynch;
reg [9:0] vcnt;
reg vblank, vsynch;
reg [5:0] bcnt;
always @(posedge clk) begin
pclk <= ~pclk;
end
assign pixclk = pclk;
always @(posedge clk) begin
if (pclk == 1) begin
if (hcnt == 10'd799) begin
hcnt <= 10'd0;
hblank <= 1;
end else begin
hcnt <= hcnt + 1;
end
if (hcnt == 10'd639) begin
hblank <= 0;
end
if (hcnt == 10'd655) begin
hsynch <= 0;
end
if (hcnt == 10'd751) begin
hsynch <= 1;
end
end
end
always @(posedge clk) begin
if (pclk == 1 && hcnt == 10'd799) begin
if (vcnt == 10'd524) begin
vcnt <= 10'd0;
vblank <= 1;
end else begin
vcnt <= vcnt + 1;
end
if (vcnt == 10'd479) begin
vblank <= 0;
end
if (vcnt == 10'd489) begin
vsynch <= 0;
end
if (vcnt == 10'd491) begin
vsynch <= 1;
end
end
end
always @(posedge clk) begin
if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
if (bcnt == 6'd59) begin
bcnt <= 6'd0;
blink <= 1;
end else begin
bcnt <= bcnt + 1;
end
if (bcnt == 6'd29) begin
blink <= 0;
end
end
end
assign blank = hblank & vblank;
assign hsync = hsynch;
assign vsync = vsynch;
assign txtrow[4:0] = vcnt[8:4];
assign txtcol[6:0] = hcnt[9:3];
assign chrrow[3:0] = vcnt[3:0];
assign chrcol[2:0] = hcnt[2:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_PP_SYMBOL_V
|
// CRTC6845(HD46505) CORE
//
// Version : beta 4
//
// Copyright(c) 2004 Katsumi Degawa , All rights reserved.
// Copyright(c) 2004 Tatsuyuki Satoh , All rights reserved.
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// VerilogHDL model of MC6845(HD46505) compatible CRTC.
// This was made for FPGA-GAME(ROCK-OLA).
// Therefore. There is a limitation in the function.
// 1. This doesn't implement interlace mode.
// 2. This doesn't implement light pen detection founction.
// 3. This doesn't implement cursor control founction.
//
// 4. This doesn't implement display sque (HD46505SP)
// 5. This doesn't support case Nht==0
//
// File History
// 2005. 4. 5 by T.satoh
// bugfix port size mismatch
// 2005. 1.13 by T.satoh
// bugfix VSYNC pulse width (line to raster)
// bugfix NEXT_R_RA bit size mismatch.
// 2004.12. 9 by T.satoh
// rewrite source with minimize code. (178 -> 119 slice to Spartan3 with Area optimize)
// bugfix , bypass wite register 10H-1FH ( R_ADR width change 5bit from 4bit).
// fix register mismatch width W_Nr,O_Nr,Nvt,Nvd and Nvsp.
// change R_V_CNT width 9bit to 7bit.
//
// 2004.10.23 First release
//--------------------------------------------------------------------------------------
module crtc6845(
// INPUT
I_E,
I_DI,
I_RS,
I_RWn,
I_CSn,
I_CLK,
I_RSTn,
// OUTPUT
O_RA,
O_MA,
O_H_SYNC,
O_V_SYNC,
O_DISPTMG,
video_offset_o
);
input I_E;
input [7:0]I_DI;
input I_RS;
input I_RWn;
input I_CSn;
input I_CLK;
input I_RSTn;
output [4:0]O_RA;
output [13:0]O_MA;
output O_H_SYNC;
output O_V_SYNC;
output O_DISPTMG;
output [15:0] video_offset_o;
wire [7:0]W_Nht;
wire [7:0]W_Nhd;
wire [7:0]W_Nhsp;
wire [3:0]W_Nhsw;
wire [6:0]W_Nvt;
wire [4:0]W_Nadj;
wire [6:0]W_Nvd;
wire [6:0]W_Nvsp;
wire [3:0]W_Nvsw;
wire [4:0]W_Nr;
wire [13:0]W_Msa;
wire W_Vmode;
wire W_IntSync;
wire [1:0] W_DScue;
wire [1:0] W_CScue;
//assign video_offset_o = {8'b11000000,W_Msa[6:0],1'b0};
assign video_offset_o = {5'b11000,W_Msa[9:0],1'b0};
mpu_if mpu_if(
.I_RSTn(I_RSTn),
.I_E(I_E),
.I_DI(I_DI),
.I_RS(I_RS),
.I_RWn(I_RWn),
.I_CSn(I_CSn),
.O_Nht(W_Nht),
.O_Nhd(W_Nhd),
.O_Nhsp(W_Nhsp),
.O_Nhsw(W_Nhsw),
.O_Nvt(W_Nvt),
.O_Nadj(W_Nadj),
.O_Nvd(W_Nvd),
.O_Nvsp(W_Nvsp),
.O_Nvsw(W_Nvsw),
.O_Nr(W_Nr),
.O_Msa(W_Msa),
.O_VMode(W_Vmode),
.O_IntSync(W_IntSync),
// HD46505-SP only
.O_DScue(W_DScue),
.O_CScue(W_CScue)
);
crtc_gen crtc_gen(
.I_CLK(I_CLK),
.I_RSTn(I_RSTn),
.I_Nht(W_Nht),
.I_Nhd(W_Nhd),
.I_Nhsp(W_Nhsp),
.I_Nhsw(W_Nhsw),
.I_Nvt(W_Nvt),
.I_Nadj(W_Nadj),
.I_Nvd(W_Nvd),
.I_Nvsp(W_Nvsp),
.I_Nvsw(W_Nvsw),
.I_Nr(W_Nr),
.I_Msa(W_Msa),
.O_RA(O_RA),
.O_MA(O_MA),
.O_H_SYNC(O_H_SYNC),
.O_V_SYNC(O_V_SYNC),
.O_DISPTMG(O_DISPTMG)
);
endmodule
module mpu_if(
I_RSTn,
I_E,
I_DI,
I_RS,
I_RWn,
I_CSn,
O_Nht,
O_Nhd,
O_Nhsp,
O_Nhsw,
O_Nvt,
O_Nadj,
O_Nvd,
O_Nvsp,
O_Nvsw,
O_Nr,
O_Msa,
O_DScue,
O_CScue,
O_VMode,
O_IntSync
);
input I_RSTn;
input I_E;
input [7:0]I_DI;
input I_RS;
input I_RWn;
input I_CSn;
output [7:0]O_Nht;
output [7:0]O_Nhd;
output [7:0]O_Nhsp;
output [3:0]O_Nhsw;
output [6:0]O_Nvt;
output [4:0]O_Nadj;
output [6:0]O_Nvd;
output [6:0]O_Nvsp;
output [3:0]O_Nvsw;
output [4:0]O_Nr;
output [13:0]O_Msa;
output [1:0] O_DScue;
output [1:0] O_CScue;
output O_VMode;
output O_IntSync;
reg [4:0]R_ADR;
reg [7:0]R_Nht;
reg [7:0]R_Nhd;
reg [7:0]R_Nhsp;
reg [7:0]R_Nsw;
reg [6:0]R_Nvt;
reg [4:0]R_Nadj;
reg [6:0]R_Nvd;
reg [6:0]R_Nvsp;
reg [7:0]R_Intr;
reg [4:0]R_Nr;
reg [5:0]R_Msah;
reg [7:0]R_Msal;
assign O_Nht = R_Nht;
assign O_Nhd = R_Nhd;
assign O_Nhsp = R_Nhsp;
assign O_Nhsw = R_Nsw[3:0];
assign O_Nvt = R_Nvt;
assign O_Nadj = R_Nadj;
assign O_Nvd = R_Nvd;
assign O_Nvsp = R_Nvsp;
assign O_Nvsw = R_Nsw[7:4];
assign O_Nr = R_Nr;
assign O_Msa = {R_Msah,R_Msal};
assign O_VMode = R_Intr[1];
assign O_IntSync = R_Intr[0];
// HD46505-SP only
assign O_DScue = R_Intr[5:4]; // disp scue 0,1,2 or OFF
assign O_CScue = R_Intr[7:6]; // cursor scue 0,1,2 or OFF
always@(negedge I_RSTn or negedge I_E)
begin
if(~I_RSTn) begin
// this is currently set for "non-interlace MODE 7"
// - it's a fudge because this controller doesn't support interlace
R_Nht <= 8'h3F; // 0
R_Nhd <= 8'h28; // 1
R_Nhsp <= 8'h33; // 2
R_Nsw <= 8'h24; // 3
R_Nvt <= 7'h1E; // 4
R_Nadj <= 5'h02; // 5
R_Nvd <= 7'h19; // 6
R_Nvsp <= 7'h1B; //1C; // 7
R_Intr <= 8'h91; //93; // 8
R_Nr <= 5'h09; //12; // 9
R_Msah <= 6'h28; // 12
R_Msal <= 8'h00; // 13
end else
if(~I_CSn)begin
if(~I_RWn)begin
if(~I_RS)begin
R_ADR <= I_DI[4:0];
end else begin
case(R_ADR)
5'h0 : R_Nht <= I_DI ;
5'h1 : R_Nhd <= I_DI ;
5'h2 : R_Nhsp <= I_DI ;
5'h3 : R_Nsw <= I_DI ;
5'h4 : R_Nvt <= I_DI[6:0] ;
4'h5 : R_Nadj <= I_DI[4:0] ;
5'h6 : R_Nvd <= I_DI[6:0] ;
5'h7 : R_Nvsp <= I_DI[6:0] ;
5'h8 : R_Intr <= I_DI[7:0] ;
5'h9 : R_Nr <= I_DI[4:0] ;
5'hC : R_Msah <= I_DI[5:0] ;
5'hD : R_Msal <= I_DI ;
default:;
endcase
end
end
end
end
endmodule
module crtc_gen(
I_CLK,
I_RSTn,
I_Nht,
I_Nhd,
I_Nhsp,
I_Nhsw,
I_Nvt,
I_Nadj,
I_Nvd,
I_Nvsp,
I_Nvsw,
I_Nr,
I_Msa,
O_RA,
O_MA,
O_H_SYNC,
O_V_SYNC,
O_DISPTMG
);
input I_CLK;
input I_RSTn;
input [7:0]I_Nht;
input [7:0]I_Nhd;
input [7:0]I_Nhsp;
input [3:0]I_Nhsw;
input [6:0]I_Nvt;
input [4:0]I_Nr;
input [4:0]I_Nadj; // (I_Nadj-1 <= I_Nr) is Support. (I_Nadj-1 > I_Nr) is Not Support.
input [6:0]I_Nvd;
input [6:0]I_Nvsp;
input [3:0]I_Nvsw;
input [13:0]I_Msa;
output [4:0]O_RA;
output [13:0]O_MA;
output O_H_SYNC;
output O_V_SYNC;
output O_DISPTMG;
reg [7:0]R_H_CNT;
reg [6:0]R_V_CNT;
reg [4:0]R_RA;
reg [13:0]R_MA;
reg R_H_SYNC,R_V_SYNC;
reg R_DISPTMG ,R_V_DISPTMG;
reg R_LAST_LINE;
// next count value (cnt+1)
wire [7:0] NEXT_R_H_CNT = (R_H_CNT+8'h01);
wire [6:0] NEXT_R_V_CNT = (R_V_CNT+7'h01);
wire [4:0] NEXT_R_RA = R_RA + 1'b1;
// h return trigger
wire W_HD = (R_H_CNT==I_Nht);
// v return trigger
wire W_VD = (R_V_CNT==I_Nvt);
wire W_ADJ_C = R_LAST_LINE & (NEXT_R_RA==I_Nadj);
wire W_VCNT_RET = ((R_RA==I_Nr) & (I_Nadj==0) & W_VD) | W_ADJ_C;
// RA return trigger
wire W_RA_C = (R_RA==I_Nr) | W_ADJ_C;
// sync trigger
wire W_HSYNC_P = (NEXT_R_H_CNT == I_Nhsp);
wire W_HSYNC_W = (NEXT_R_H_CNT[3:0] == (I_Nhsp[3:0]+I_Nhsw) );
wire W_VSYNC_P = (NEXT_R_V_CNT == I_Nvsp ) & W_RA_C;
wire W_VSYNC_W = (NEXT_R_RA[3:0]==I_Nvsw);
// disp trigger
wire W_HDISP_N = (NEXT_R_H_CNT==I_Nhd);
wire W_VDISP_N = (NEXT_R_V_CNT==I_Nvd) & W_RA_C;
//output assign
assign O_H_SYNC = R_H_SYNC;
assign O_V_SYNC = R_V_SYNC;
assign O_RA = R_RA;
assign O_MA = R_MA;
assign O_DISPTMG = R_DISPTMG;
// MA MAX = 14'h3FFF ---------------------
reg [13:0] R_MA_C;
always@(negedge I_CLK or negedge I_RSTn)
begin
if(! I_RSTn)begin
R_MA <= 14'h0000;
R_MA_C <= 14'h0000;
R_H_CNT <= 8'h00;
R_H_SYNC <= 0;
R_RA <= 5'h00;
R_V_CNT <= 7'h00;
R_LAST_LINE <= 1'b0;
R_V_SYNC <= 0;
R_V_DISPTMG <= 1'b0;
R_DISPTMG <= 1'b0;
end
else begin
// H CNT
R_H_CNT <= W_HD ? 8'h00 : NEXT_R_H_CNT;
// MA
R_MA <= W_HD ? R_MA_C : R_MA + 1'b1;
// MA return address
if(W_RA_C & (R_H_CNT==I_Nhd) )
R_MA_C <= W_VCNT_RET ? I_Msa : R_MA;
// HSYNC
if(W_HSYNC_P) R_H_SYNC <= 1'b1;
else if(W_HSYNC_W) R_H_SYNC <= 1'b0;
// H RETURN
if(W_HD)
begin
// RA
R_RA <= W_RA_C ? 5'h00 : NEXT_R_RA;
// VSYNC
if(W_VSYNC_P) R_V_SYNC <= 1'b1;
else if(W_VSYNC_W) R_V_SYNC <= 1'b0;
if(W_RA_C)
begin
// for adjust line
R_LAST_LINE <= W_VD;
// V CNT
R_V_CNT <= W_VCNT_RET ? 7'h00 : NEXT_R_V_CNT;
end
end
// V DISPTMG (next line)
if(W_VCNT_RET) R_V_DISPTMG <= 1'b1;
else if(W_VDISP_N) R_V_DISPTMG <= 1'b0;
// H & V DISPTMG
if(W_HD) R_DISPTMG <= R_V_DISPTMG;
else if(W_HDISP_N) R_DISPTMG <= 1'b0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O311A_FUNCTIONAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_1_V
`define SKY130_FD_SC_MS__SEDFXTP_1_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_1 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_1 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_1_V
|
// Switch stops the clock in the PHI2 state
// Size of clock delay pipe - needs to be 0 for the Master but 2 or 3 for BBC /Elk depending on xtal
`define CLKDEL_PIPE_SZ 3
// Select this to use a simple /2, /4 ripple counter divider
`define RIPPLE_DIVIDER
// Set this for super slow debug clocking
//`define RIPPLE_DIV8 1
// Select this to use the /2 and /3 rather than /2 and /4 in the synchronous divider module
//`define USE_DIVIDER_23
// Use this to get a latch on the HS clock enable rather than a FF
//`define USE_LATCH_ENABLE 1
`ifdef USE_DIVIDER_23
`define USE_LATCH_ENABLE 1
`endif
`define SINGLE_HS_RETIMER 1
module clkctrl_phi2(
input hsclk_in,
input lsclk_in,
input rst_b,
input hsclk_sel,
input delay_bypass,
input cpuclk_div_sel,
output hsclk_selected,
output lsclk_selected,
output clkout, // Selected clock
output fast_clkout // RAW fast clock (divided down from HSCLK_IN)
);
reg hs_enable_q, ls_enable_q;
reg selected_ls_q;
reg selected_hs_q;
`ifdef SINGLE_HS_RETIMER
reg retimed_ls_enable_q;
`else
reg [1:0] retimed_ls_enable_q;
`endif
reg retimed_hs_enable_q;
reg [`CLKDEL_PIPE_SZ-1:0] del_q;
wire retimed_ls_enable_w;
// Force Keep clock nets to prevent ISE merging divider logic into other equations and
// causing timing issues
(* KEEP="TRUE" *) wire cpuclk_w;
(* KEEP="TRUE" *) wire lsclk_del_w;
assign lsclk_del_w = (delay_bypass) ? lsclk_in : del_q[0];
assign clkout = (cpuclk_w & hs_enable_q) | (lsclk_del_w & ls_enable_q);
assign lsclk_selected = selected_ls_q;
assign hsclk_selected = selected_hs_q;
assign fast_clkout = cpuclk_w;
`ifdef RIPPLE_DIVIDER
reg ripple_div2_q;
reg ripple_div4_q;
`ifdef RIPPLE_DIV8
reg ripple_div8_q;
`endif
always @ ( posedge hsclk_in )
ripple_div2_q <= !ripple_div2_q;
always @ ( posedge ripple_div2_q )
ripple_div4_q <= !ripple_div4_q;
`ifdef RIPPLE_DIV8
always @ ( posedge ripple_div4_q )
ripple_div8_q <= !ripple_div8_q;
assign cpuclk_w = ( cpuclk_div_sel) ? ripple_div8_q : ripple_div2_q;
`else
assign cpuclk_w = ( cpuclk_div_sel) ? ripple_div4_q : ripple_div2_q;
`endif
`else
clkdiv234 divider_u ( .clkin(hsclk_in),
.rstb(rst_b),
`ifdef USE_DIVIDER_23
.div4(1'b0),
.div3(cpuclk_div_sel==1'b1),
`else
.div4(cpuclk_div_sel==1'b1),
.div3(1'b0),
`endif
.div2(cpuclk_div_sel==1'b0),
.clkout(cpuclk_w));
`endif // !`ifdef RIPPLE_DIVIDER
// Delay the host clock to match delays on the motherboard
always @ (posedge hsclk_in) begin
del_q <= { lsclk_in, del_q[`CLKDEL_PIPE_SZ-1:1]};
end
// Selected LS signal must change on posedge of clock
always @ (posedge lsclk_del_w or negedge rst_b)
if ( ! rst_b )
selected_ls_q <= 1'b1;
else
selected_ls_q <= !hsclk_sel & !retimed_hs_enable_q;
// Edge triggered FF for feedback to clock selection
always @ ( posedge cpuclk_w or negedge rst_b )
if ( ! rst_b )
selected_hs_q <= 1'b0;
else
selected_hs_q <= hs_enable_q;
`ifdef USE_LATCH_ENABLE
// Use a latch on the HS enable to allow maximum time for the
// enable to stabilize before being used to gate the clock
always @ ( cpuclk_w or rst_b )
if ( !rst_b )
hs_enable_q <= 1'b0;
else if ( !cpuclk_w )
hs_enable_q <= hsclk_sel & !retimed_ls_enable_w;
`else
// Simulate a latch transparent on low cpuclk_w by oversampling
// with hsclk_in - allows 1/2 hsclk cycle less time then using
// an actual latch
always @ ( negedge hsclk_in or negedge rst_b )
if ( !rst_b )
hs_enable_q <= 1'b0;
else if ( !cpuclk_w )
hs_enable_q <= hsclk_sel & !retimed_ls_enable_w;
`endif // !`ifdef USE_LATCH_ENABLE
always @ ( negedge lsclk_del_w or negedge rst_b )
if ( ! rst_b )
ls_enable_q <= 1'b1;
else
ls_enable_q <= !hsclk_sel & !retimed_hs_enable_q;
always @ ( negedge lsclk_del_w or posedge hs_enable_q )
if ( hs_enable_q )
retimed_hs_enable_q <= 1'b1;
else
retimed_hs_enable_q <= selected_hs_q;
`ifdef SINGLE_HS_RETIMER
always @ ( negedge cpuclk_w or posedge ls_enable_q )
if (ls_enable_q)
retimed_ls_enable_q <= 1'b1;
else
retimed_ls_enable_q <= selected_ls_q;
assign retimed_ls_enable_w = retimed_ls_enable_q;
`else
// Use two FFs here for safety because reset might be deasserted at the same
// time as a cpuclk_w negedge (both of which are on a hsclk posedge)
always @ ( negedge cpuclk_w or posedge ls_enable_q )
if (ls_enable_q)
retimed_ls_enable_q <= 2'b11;
else
retimed_ls_enable_q <= {selected_ls_q, retimed_ls_enable_q[1]} ;
assign retimed_ls_enable_w = retimed_ls_enable_q[0];
`endif // !`ifdef SINGLE_HS_RETIMER
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_4_V
`define SKY130_FD_SC_HD__NOR3_4_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
|
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: ashift16.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ashift16 (
data,
distance,
result);
input [31:0] data;
input [3:0] distance;
output [31:0] result;
wire [31:0] sub_wire0;
wire sub_wire1 = 1'h1;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (sub_wire1),
.distance (distance),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.overflow (),
.underflow ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "ARITHMETIC",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 32,
LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "1"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "32"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "ARITHMETIC"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ashift16_bb.v FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_1_V
`define SKY130_FD_SC_LS__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_1_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 0
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARVALID" *)
output wire M_AXI_GP1_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWVALID" *)
output wire M_AXI_GP1_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BREADY" *)
output wire M_AXI_GP1_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RREADY" *)
output wire M_AXI_GP1_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WLAST" *)
output wire M_AXI_GP1_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WVALID" *)
output wire M_AXI_GP1_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARID" *)
output wire [11 : 0] M_AXI_GP1_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWID" *)
output wire [11 : 0] M_AXI_GP1_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WID" *)
output wire [11 : 0] M_AXI_GP1_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARBURST" *)
output wire [1 : 0] M_AXI_GP1_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARLOCK" *)
output wire [1 : 0] M_AXI_GP1_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARSIZE" *)
output wire [2 : 0] M_AXI_GP1_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWBURST" *)
output wire [1 : 0] M_AXI_GP1_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWLOCK" *)
output wire [1 : 0] M_AXI_GP1_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWSIZE" *)
output wire [2 : 0] M_AXI_GP1_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARPROT" *)
output wire [2 : 0] M_AXI_GP1_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWPROT" *)
output wire [2 : 0] M_AXI_GP1_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARADDR" *)
output wire [31 : 0] M_AXI_GP1_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWADDR" *)
output wire [31 : 0] M_AXI_GP1_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WDATA" *)
output wire [31 : 0] M_AXI_GP1_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARCACHE" *)
output wire [3 : 0] M_AXI_GP1_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARLEN" *)
output wire [3 : 0] M_AXI_GP1_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARQOS" *)
output wire [3 : 0] M_AXI_GP1_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWCACHE" *)
output wire [3 : 0] M_AXI_GP1_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWLEN" *)
output wire [3 : 0] M_AXI_GP1_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWQOS" *)
output wire [3 : 0] M_AXI_GP1_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WSTRB" *)
output wire [3 : 0] M_AXI_GP1_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP1_ACLK CLK" *)
input wire M_AXI_GP1_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARREADY" *)
input wire M_AXI_GP1_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWREADY" *)
input wire M_AXI_GP1_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BVALID" *)
input wire M_AXI_GP1_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RLAST" *)
input wire M_AXI_GP1_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RVALID" *)
input wire M_AXI_GP1_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WREADY" *)
input wire M_AXI_GP1_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BID" *)
input wire [11 : 0] M_AXI_GP1_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RID" *)
input wire [11 : 0] M_AXI_GP1_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BRESP" *)
input wire [1 : 0] M_AXI_GP1_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RRESP" *)
input wire [1 : 0] M_AXI_GP1_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RDATA" *)
input wire [31 : 0] M_AXI_GP1_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg484")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWVALID(M_AXI_GP1_AWVALID),
.M_AXI_GP1_BREADY(M_AXI_GP1_BREADY),
.M_AXI_GP1_RREADY(M_AXI_GP1_RREADY),
.M_AXI_GP1_WLAST(M_AXI_GP1_WLAST),
.M_AXI_GP1_WVALID(M_AXI_GP1_WVALID),
.M_AXI_GP1_ARID(M_AXI_GP1_ARID),
.M_AXI_GP1_AWID(M_AXI_GP1_AWID),
.M_AXI_GP1_WID(M_AXI_GP1_WID),
.M_AXI_GP1_ARBURST(M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARLOCK(M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARSIZE(M_AXI_GP1_ARSIZE),
.M_AXI_GP1_AWBURST(M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWLOCK(M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWSIZE(M_AXI_GP1_AWSIZE),
.M_AXI_GP1_ARPROT(M_AXI_GP1_ARPROT),
.M_AXI_GP1_AWPROT(M_AXI_GP1_AWPROT),
.M_AXI_GP1_ARADDR(M_AXI_GP1_ARADDR),
.M_AXI_GP1_AWADDR(M_AXI_GP1_AWADDR),
.M_AXI_GP1_WDATA(M_AXI_GP1_WDATA),
.M_AXI_GP1_ARCACHE(M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARLEN(M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARQOS(M_AXI_GP1_ARQOS),
.M_AXI_GP1_AWCACHE(M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWLEN(M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWQOS(M_AXI_GP1_AWQOS),
.M_AXI_GP1_WSTRB(M_AXI_GP1_WSTRB),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK),
.M_AXI_GP1_ARREADY(M_AXI_GP1_ARREADY),
.M_AXI_GP1_AWREADY(M_AXI_GP1_AWREADY),
.M_AXI_GP1_BVALID(M_AXI_GP1_BVALID),
.M_AXI_GP1_RLAST(M_AXI_GP1_RLAST),
.M_AXI_GP1_RVALID(M_AXI_GP1_RVALID),
.M_AXI_GP1_WREADY(M_AXI_GP1_WREADY),
.M_AXI_GP1_BID(M_AXI_GP1_BID),
.M_AXI_GP1_RID(M_AXI_GP1_RID),
.M_AXI_GP1_BRESP(M_AXI_GP1_BRESP),
.M_AXI_GP1_RRESP(M_AXI_GP1_RRESP),
.M_AXI_GP1_RDATA(M_AXI_GP1_RDATA),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
|
module nkmd_dai_rx(
input wire clk,
input wire rst,
// dmix interface
input wire [23:0] rx_data_i,
input wire rx_ack_i,
// To nkmm R bus
input wire [31:0] data_i,
output wire [31:0] data_o,
input wire [31:0] addr_i,
input wire we_i);
reg [5:0] nextw_ff;
always @(posedge clk) begin
if (rst)
nextw_ff <= 0;
else if (rx_ack_i)
nextw_ff <= nextw_ff + 1;
end
reg [23:0] ringbuf [63:0];
always @(posedge clk) begin
if (rx_ack_i)
ringbuf[nextw_ff] <= rx_data_i;
end
reg [5:0] unread_ff;
reg [5:0] shift_ff;
wire should_shift;
assign should_shift = we_i && addr_i[15:12] == 4'hd && addr_i[7:0] == 8'h00;
always @(posedge clk) begin
if (rst) begin
unread_ff <= 0;
shift_ff <= 0;
end else if (should_shift && !rx_ack_i) begin
unread_ff <= unread_ff - 1;
shift_ff <= shift_ff + 1;
end else if (!should_shift && rx_ack_i) begin
unread_ff <= unread_ff + 1;
end else if (should_shift && rx_ack_i) begin
shift_ff <= shift_ff + 1;
end
end
// RAM interface
reg [31:0] data_o_ff;
assign data_o = data_o_ff;
// {4'hd, ch[3:0], 8'h00} => rx ringbuf unread
// {4'hf, ch[3:0], offset} => rx ringbuf
// FIXME: add ch check
wire [5:0] offset_i;
assign offset_i = addr_i[5:0];
always @(posedge clk) begin
if (addr_i[15:12] == 4'hf)
data_o_ff <= ringbuf[shift_ff + offset_i];
else if (addr_i[15:12] == 4'hd && addr_i[7:0] == 8'h00)
data_o_ff <= unread_ff;
else
data_o_ff <= 0;
end
endmodule
module nkmd_dai_tx(
input wire clk,
input wire rst,
// dmix interface
output wire [23:0] tx_data_o,
input wire tx_pop_i,
output wire tx_ack_o,
// To nkmm R bus
input wire [31:0] data_i,
output wire [31:0] data_o,
input wire [31:0] addr_i,
input wire we_i);
reg [5:0] queued_ff;
reg [5:0] lastr_ff;
reg [5:0] nextw_ff;
reg [23:0] ringbuf [63:0];
assign tx_data_o = ringbuf[lastr_ff];
wire should_queue;
assign should_queue = we_i && addr_i[15:12] == 4'hd && addr_i[7:0] == 8'h01;
always @(posedge clk) begin
if (rst) begin
queued_ff <= 0;
lastr_ff <= 6'h3f;
nextw_ff <= 0;
end else if (should_queue && !tx_pop_i) begin
ringbuf[nextw_ff] <= data_i;
queued_ff <= queued_ff + 1;
nextw_ff <= nextw_ff + 1;
end else if (!should_queue && tx_pop_i) begin
if (queued_ff > 0) begin
queued_ff <= queued_ff - 1;
lastr_ff <= lastr_ff + 1;
end
end else if (should_queue && tx_pop_i) begin
ringbuf[nextw_ff] <= data_i;
if (queued_ff > 0) begin
lastr_ff <= lastr_ff + 1;
end else begin
queued_ff <= queued_ff + 1;
end
nextw_ff <= nextw_ff + 1;
end
end
reg tx_ack_ff;
always @(posedge clk)
tx_ack_ff <= tx_pop_i;
assign tx_ack_o = tx_ack_ff;
// RAM interface
reg [31:0] data_o_ff;
assign data_o = data_o_ff;
// {4'hd, ch[3:0], 8'h01} => tx ringbuf queued
// {4'he, ch[3:0], offset} => tx ringbuf
// FIXME: add ch check
wire [5:0] offset_i;
assign offset_i = addr_i[5:0];
always @(posedge clk) begin
if (addr_i[15:12] == 4'he)
data_o_ff <= ringbuf[nextw_ff - 1 - offset_i];
else if (addr_i[15:12] == 4'hd && addr_i[7:0] == 8'h01)
data_o_ff <= queued_ff;
else
data_o_ff <= 0;
end
endmodule
|
`default_nettype none
`define CLKFBOUT_MULT 2
// ============================================================================
module top
(
input wire clk,
input wire rst,
input wire [1:0] sw,
output wire [9:0] led,
);
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
wire CLK;
BUFG bufg(.I(clk), .O(CLK));
always @(posedge CLK)
if (rst)
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// Clocks for ISERDES
wire PRE_BUFG_SYSCLK;
wire PRE_BUFG_CLKDIV;
wire PRE_BUFG_REFCLK;
wire SYSCLK;
wire CLKDIV;
wire REFCLK;
wire clk_fb_i;
wire clk_fb_o;
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (`CLKFBOUT_MULT),
.CLKOUT0_DIVIDE (`CLKFBOUT_MULT / 2), // SYSCLK, 200MHz (Fast clock)
.CLKOUT1_DIVIDE ((`CLKFBOUT_MULT * 4) / 2), // CLKDIV, 50MHz (Slow clock)
.CLKOUT2_DIVIDE (`CLKFBOUT_MULT / 2), // REFCLK (IDELAYCTRL), 200 MHz
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1'd1)
)
pll
(
.CLKIN1 (CLK),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (PRE_BUFG_SYSCLK),
.CLKOUT1 (PRE_BUFG_CLKDIV),
.CLKOUT2 (PRE_BUFG_REFCLK)
);
BUFG bufg_clk(.I(PRE_BUFG_SYSCLK), .O(SYSCLK));
BUFG bufg_clkdiv(.I(PRE_BUFG_CLKDIV), .O(CLKDIV));
BUFG bufg_refclk(.I(PRE_BUFG_REFCLK), .O(REFCLK));
IDELAYCTRL idelayctrl_1 (
.REFCLK(REFCLK)
);
IDELAYCTRL idelayctrl_2 (
.REFCLK(REFCLK)
);
assign led[0] = 0;
assign led[1] = 0;
wire OUTPUTS[7:0];
// ISERDES reset generator
wire i_rstdiv;
// First ISERDES/IDELAY bank
wire DDLY_1;
IDELAYE2 #
(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IDATAIN"),
.IDELAY_VALUE (5'd31)
)
idelay_1
(
.C (SYSCLK),
.CE (1'b1),
.LD (1'b1),
.INC (1'b1),
.IDATAIN (sw[0]),
.DATAOUT (DDLY_1)
);
ISERDESE2 #
(
.DATA_RATE ("SDR"),
.DATA_WIDTH (3'd4),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (2)
)
iserdes_1
(
.CLK (SYSCLK),
.CLKB (SYSCLK),
.CLKDIV (CLKDIV),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (RST),
.DDLY (DDLY_1),
.Q1 (led[5]),
.Q2 (led[4]),
.Q3 (led[3]),
.Q4 (led[2]),
);
// Second ISERDES/IDELAY bank
wire DDLY_2;
IDELAYE2 #
(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IDATAIN"),
.IDELAY_VALUE (5'd31)
)
idelay_2
(
.C (SYSCLK),
.CE (1'b1),
.LD (1'b1),
.INC (1'b1),
.IDATAIN (sw[1]),
.DATAOUT (DDLY_2)
);
ISERDESE2 #
(
.DATA_RATE ("SDR"),
.DATA_WIDTH (3'd4),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (2)
)
iserdes_2
(
.CLK (SYSCLK),
.CLKB (SYSCLK),
.CLKDIV (CLKDIV),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (RST),
.DDLY (DDLY_2),
.Q1 (led[9]),
.Q2 (led[8]),
.Q3 (led[7]),
.Q4 (led[6]),
);
endmodule
|
/*
* Miller Encoder
*
* By our algorithm, Miller Encoder can operate in the lowest frequency
* to save the power dissipation
*
* This algorithm is also applied to FMo Encoder
*
* If enable Miller Encoder, disable FM0 Encoder and vice versa
*/
`timescale 1us / 1ns
module miller_enc
(
output miller_data,
output mil_complete,
input clk_mil,
input rst_for_new_package,
input clk_blf,
input send_data,
input en_fm0, // if en_fm0 = 0, enable miller encoder
input trext,
input st_enc,
input fg_complete
);
parameter GetData = 2'b00;
parameter DataP = 2'b01;
parameter DataN = 2'b10;
reg [1:0]ps;
reg [1:0]ns;
wire clk_blf_n;
wire en_mil_out;
wire m2o;
wire mp_complete;
wire me_start;
reg [5:0]mp_end;
reg [5:0]mp_cnt;
reg m_cnt;
reg m1o;
reg [1:0]data_select;
reg [1:0]fg_comp_cnt;
assign clk_blf_n = ~clk_blf;
assign en_mil_out = (mp_cnt > 6'h0)? 1'b1 : 1'b0;
assign miller_data = (en_mil_out & ~mil_complete)? m2o : 1'b0;
assign m2o = mp_complete? m1o : clk_blf;
assign mp_complete = (mp_cnt == mp_end)? 1'b1 : 1'b0;
assign me_start = (mp_cnt > mp_end - 6'h2)? 1'b1 : 1'b0;
always@(*) begin
if(~trext) mp_end = 6'h9;
else mp_end = 6'h21;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) mp_cnt <= 6'h0;
else begin
if(mp_cnt == mp_end) mp_cnt <= mp_cnt;
else if(~en_fm0 & st_enc) mp_cnt <= mp_cnt + 6'h1;
end
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) m_cnt <= 1'b0;
else if(me_start) m_cnt <= m_cnt + 1'b1;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0 & me_start) ns = DataP;
else ns = GetData;
DataP : if(~send_data) ns = DataP;
else begin
if(~m_cnt) ns = DataP;
else ns = DataN;
end
DataN : if(~send_data) ns = DataN;
else begin
if(~m_cnt) ns = DataN;
else ns = DataP;
end
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
DataP : data_select = 2'h1;
DataN : data_select = 2'h2;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = clk_blf;
2'h2 : m1o = clk_blf_n;
default : m1o = 1'b0;
endcase
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b11) fg_comp_cnt <= fg_comp_cnt;
else if(~en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign mil_complete = (fg_comp_cnt == 2'b11)? 1'b1 : 1'b0;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:05:07 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, OP_FLAG_SFG,
ZERO_FLAG_SFG, N59, N60, ADD_OVRFLW_SGF,
inst_ShiftRegister_net3648770, SFT2FRMT_STAGE_VARS_net3648693,
FRMT_STAGE_DATAOUT_net3648634, SGF_STAGE_DMP_net3648688,
NRM_STAGE_Raw_mant_net3648670, INPUT_STAGE_OPERANDY_net3648634,
EXP_STAGE_DMP_net3648688, SHT1_STAGE_DMP_net3648688,
SHT2_STAGE_DMP_net3648688, SHT2_SHIFT_DATA_net3648670,
array_comparators_GTComparator_N0, array_comparators_LTComparator_N0,
n388, n389, n390, DP_OP_15J179_122_6956_n28,
DP_OP_15J179_122_6956_n18, DP_OP_15J179_122_6956_n17,
DP_OP_15J179_122_6956_n16, DP_OP_15J179_122_6956_n15,
DP_OP_15J179_122_6956_n14, DP_OP_15J179_122_6956_n8,
DP_OP_15J179_122_6956_n7, DP_OP_15J179_122_6956_n6,
DP_OP_15J179_122_6956_n5, DP_OP_15J179_122_6956_n4,
DP_OP_15J179_122_6956_n3, DP_OP_15J179_122_6956_n2,
DP_OP_15J179_122_6956_n1, intadd_427_CI, intadd_427_SUM_2_,
intadd_427_SUM_1_, intadd_427_SUM_0_, intadd_427_n3, intadd_427_n2,
intadd_427_n1, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412,
n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [30:0] intDY_EWSW;
wire [30:0] DMP_INIT_EWSW;
wire [27:0] DmP_INIT_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [4:0] Shift_amount_EXP_EW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [4:0] LZD_raw_out_EWR;
wire [4:2] shft_value_mux_o_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [51:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [25:0] sftr_odat_SHT2_SWR;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:2] DmP_mant_SFG_SWR;
wire [25:1] Raw_mant_SGF;
wire [31:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n390), .ENCLK(inst_ShiftRegister_net3648770), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3648693), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[0]), .ENCLK(
FRMT_STAGE_DATAOUT_net3648634), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3648688), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3648670), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3648634), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3648688),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3648688),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3648688), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3648670), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1277), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1235), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1235), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1235), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1235), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1235), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[28]), .QN(
n419) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1239), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1240), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1241), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1242), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1243), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1244), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1245), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1246), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1249), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1252), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n512), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n511), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n512), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1252), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1246), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1249), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1249), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1252), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n531), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1246), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1246), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1249), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_EXP_EWSW[23]), .QN(n420)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_EXP_EWSW[24]), .QN(n1204) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_EXP_EWSW[25]), .QN(n1229) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1252), .Q(DMP_EXP_EWSW[26]), .QN(n1228) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3648688), .RN(n1250), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1250), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1251), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1252), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1246), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n513), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1249), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1275), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1248), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n1252), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n513), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3648688), .RN(n512), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1275), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1275), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n512), .Q(DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[23]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1262), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n512), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1246), .Q(DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[24]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1263), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1247), .Q(DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[25]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1263), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1263), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1249), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1253), .Q(DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[26]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1263), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1263), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[27]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1263), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1263), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[28]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1263), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1263), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[29]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1263), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1254), .Q(DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[30]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1264), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1268), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3648688), .RN(n1254), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1255), .Q(ZERO_FLAG_SFG) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[15])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[18])
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[20])
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[22])
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[23])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1262), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1255), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1255), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1255), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1255), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .RN(n1255), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1268), .Q(ADD_OVRFLW_NRM), .QN(
n1153) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[50]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(Data_array_SWR[29]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(Data_array_SWR[28]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(Data_array_SWR[26]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1159), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[14]), .QN(
n1124) );
CMPR32X2TS DP_OP_15J179_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(
DP_OP_15J179_122_6956_n28), .C(DP_OP_15J179_122_6956_n18), .CO(
DP_OP_15J179_122_6956_n8), .S(exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS intadd_427_U4 ( .A(DmP_EXP_EWSW[24]), .B(n1204), .C(intadd_427_CI), .CO(intadd_427_n3), .S(intadd_427_SUM_0_) );
CMPR32X2TS intadd_427_U3 ( .A(DmP_EXP_EWSW[25]), .B(n1229), .C(intadd_427_n3), .CO(intadd_427_n2), .S(intadd_427_SUM_1_) );
CMPR32X2TS intadd_427_U2 ( .A(DmP_EXP_EWSW[26]), .B(n1228), .C(intadd_427_n2), .CO(intadd_427_n1), .S(intadd_427_SUM_2_) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[25]), .QN(
n1230) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDY_EWSW[0]), .QN(
n1227) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1247), .Q(intDY_EWSW[26]), .QN(
n1226) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1243), .Q(intDY_EWSW[15]), .QN(
n1225) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1239), .Q(intDY_EWSW[3]), .QN(
n1224) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1242), .Q(intDY_EWSW[11]), .QN(
n1222) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1247), .Q(intDY_EWSW[25]), .QN(
n1221) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1244), .Q(intDY_EWSW[18]), .QN(
n1220) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1244), .Q(intDY_EWSW[17]), .QN(
n1219) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1241), .Q(intDY_EWSW[8]), .QN(
n1218) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1242), .Q(intDY_EWSW[12]), .QN(
n1217) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1275), .Q(intDY_EWSW[27]), .QN(
n1216) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1241), .Q(intDY_EWSW[9]), .QN(
n1215) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1245), .Q(intDY_EWSW[22]), .QN(
n1214) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1244), .Q(intDY_EWSW[20]), .QN(
n1213) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1239), .Q(intDY_EWSW[2]), .QN(
n1212) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1245), .Q(intDY_EWSW[21]), .QN(
n1211) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1242), .Q(intDY_EWSW[13]), .QN(
n1210) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n512), .Q(intDY_EWSW[24]), .QN(
n1209) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1241), .Q(intDY_EWSW[10]), .QN(
n1208) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1240), .Q(intDY_EWSW[4]), .QN(
n1207) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1243), .Q(intDY_EWSW[16]), .QN(
n1206) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1240), .Q(intDY_EWSW[6]), .QN(
n1205) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[23]), .QN(
n1201) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1240), .Q(intDY_EWSW[5]), .QN(
n1199) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1241), .Q(intDY_EWSW[7]), .QN(
n1198) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n389), .CK(clk), .RN(
n1234), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1197) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1255), .Q(Data_array_SWR[51]), .QN(
n1195) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[21]), .QN(
n1191) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[3]),
.QN(n1190) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[49]), .QN(
n1189) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[48]), .QN(
n1188) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[23]), .QN(
n1187) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .QN(n1186) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .QN(n1185) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[12]),
.QN(n1182) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[16]), .QN(
n1181) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[17]), .QN(
n1178) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(shift_value_SHT2_EWR[2]),
.QN(n1177) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[30]), .QN(
n1176) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[29]), .QN(
n1175) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[21]), .QN(
n1174) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[13]), .QN(
n1173) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[26]), .QN(
n1172) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[19]), .QN(
n1171) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[14]), .QN(
n1170) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[12]), .QN(
n1169) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[11]), .QN(
n1168) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[25]), .QN(
n1167) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[17]), .QN(
n1166) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[10]), .QN(
n1165) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1235), .Q(intDX_EWSW[1]), .QN(
n1164) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(N60), .QN(n1154) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[1]),
.QN(n1151) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1247), .Q(intDY_EWSW[29]), .QN(
n1150) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[3]), .QN(
n1149) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[7]), .QN(
n1147) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[9]), .QN(
n1146) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[4]), .QN(
n1145) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[6]), .QN(
n1144) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[8]), .QN(
n1143) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1243), .Q(intDY_EWSW[14]), .QN(
n1142) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1244), .Q(intDY_EWSW[19]), .QN(
n1141) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n388), .CK(clk), .RN(
n1234), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n1140) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1245), .Q(intDY_EWSW[23]), .QN(
n1139) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[6]), .QN(
n1137) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[24]), .QN(
n1136) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[4]), .QN(
n1135) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1235), .Q(intDX_EWSW[2]), .QN(
n1134) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1235), .Q(intDX_EWSW[0]), .QN(
n1133) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[15]), .QN(
n1132) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[3]), .QN(
n1131) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[27]), .QN(
n1130) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[22]), .QN(
n1129) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[20]), .QN(
n1128) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1237), .Q(intDX_EWSW[18]), .QN(
n1127) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[9]), .QN(
n1126) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1236), .Q(intDX_EWSW[8]), .QN(
n1125) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1158), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[15]), .QN(
n1123) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n511), .Q(intDY_EWSW[30]), .QN(
n1122) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1160), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[13]), .QN(
n1119) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1161), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[12]), .QN(
n1118) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1163), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[10]), .QN(
n1117) );
DFFRX1TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7[1]),
.QN(n1155) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[6]),
.QN(n1116) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n1277), .CK(clk), .RN(
n1234), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1115) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1235),
.Q(ready) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1262), .Q(final_result_ieee[23])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[24])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[25])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[26])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[27])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[28])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[29])
);
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(array_comparators_LTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(overflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1255), .Q(zero_flag) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1255), .Q(final_result_ieee[31])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1258), .Q(final_result_ieee[8])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1258), .Q(final_result_ieee[9])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[13])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[1])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[2])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[3])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[4])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1259), .Q(final_result_ieee[5])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[6])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[7])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1260), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3648634), .RN(n1261), .Q(final_result_ieee[22])
);
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(busy) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[5]),
.QN(n1196) );
ADDFX2TS DP_OP_15J179_122_6956_U2 ( .A(DP_OP_15J179_122_6956_n28), .B(
DMP_exp_NRM2_EW[7]), .CI(DP_OP_15J179_122_6956_n2), .CO(
DP_OP_15J179_122_6956_n1), .S(exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_15J179_122_6956_U3 ( .A(DP_OP_15J179_122_6956_n28), .B(
DMP_exp_NRM2_EW[6]), .C(DP_OP_15J179_122_6956_n3), .CO(
DP_OP_15J179_122_6956_n2), .S(exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J179_122_6956_U4 ( .A(DP_OP_15J179_122_6956_n28), .B(
DMP_exp_NRM2_EW[5]), .C(DP_OP_15J179_122_6956_n4), .CO(
DP_OP_15J179_122_6956_n3), .S(exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J179_122_6956_U6 ( .A(DP_OP_15J179_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J179_122_6956_n6), .CO(
DP_OP_15J179_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J179_122_6956_U7 ( .A(DP_OP_15J179_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J179_122_6956_n7), .CO(
DP_OP_15J179_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
DFFSXLTS R_0 ( .D(n1231), .CK(INPUT_STAGE_OPERANDY_net3648634), .SN(n1235),
.Q(n1276) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[25]),
.QN(n1180) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[24]), .QN(
n1202) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(shift_value_SHT2_EWR[3])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n511), .Q(intDY_EWSW[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[4]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SFG[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[42]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SFG[3]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1270), .Q(DMP_SFG[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[44]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1275), .Q(DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1273), .Q(DMP_SFG[12]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[35]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[34]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[36]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[37]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(OP_FLAG_SFG) );
DFFRX1TS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3648770), .RN(n1234), .Q(Shift_reg_FLAGS_7[0])
);
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(shift_value_SHT2_EWR[4]),
.QN(n1156) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1238), .Q(intDX_EWSW[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[40]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[41]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[11])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N59), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1264), .Q(Raw_mant_NRM_SWR[0]) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n622), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1255), .Q(bit_shift_SHT2) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[46]), .QN(
n1200) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1256), .Q(Data_array_SWR[47]), .QN(
n1138) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[5]), .QN(
n1148) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[33]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1257), .Q(Data_array_SWR[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1258), .Q(Data_array_SWR[30]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[17])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[19]),
.QN(n1194) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1266), .Q(Raw_mant_NRM_SWR[21]),
.QN(n1183) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[24]),
.QN(n1184) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[22]), .QN(
n1203) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[20]), .QN(
n1193) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[18]), .QN(
n1179) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[16]), .QN(
n1157) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3648670), .RN(n1265), .Q(Raw_mant_NRM_SWR[14]),
.QN(n1121) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1162), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1268), .Q(DmP_mant_SFG_SWR[11]), .QN(
n1120) );
DFFSX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1153), .CK(
SFT2FRMT_STAGE_VARS_net3648693), .SN(n1262), .Q(
DP_OP_15J179_122_6956_n28), .QN(ADD_OVRFLW_NRM2) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1274), .Q(DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1266), .Q(N59), .QN(n422) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1267), .Q(DmP_mant_SFG_SWR[2]), .QN(
n1152) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SFG[7]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1272), .Q(DMP_SFG[8]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1271), .Q(DMP_SFG[6]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3648688), .RN(n1269), .Q(DmP_mant_SFG_SWR[19]), .QN(
n1192) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3648634), .RN(n1239), .Q(intDY_EWSW[1]), .QN(
n1223) );
CMPR32X2TS DP_OP_15J179_122_6956_U8 ( .A(DP_OP_15J179_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J179_122_6956_n8), .CO(
DP_OP_15J179_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J179_122_6956_U5 ( .A(DP_OP_15J179_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J179_122_6956_n5), .CO(
DP_OP_15J179_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n559), .CK(
SHT2_SHIFT_DATA_net3648670), .RN(n1268), .Q(left_right_SHT2), .QN(n399) );
BUFX3TS U582 ( .A(n1102), .Y(n1095) );
AOI222X4TS U583 ( .A0(n1232), .A1(Raw_mant_NRM_SWR[4]), .B0(n1233), .B1(
Raw_mant_NRM_SWR[21]), .C0(n1114), .C1(DmP_mant_SHT1_SW[2]), .Y(n655)
);
INVX4TS U584 ( .A(n393), .Y(n394) );
BUFX3TS U585 ( .A(n1090), .Y(n1102) );
BUFX8TS U586 ( .A(n455), .Y(n408) );
BUFX8TS U587 ( .A(n455), .Y(n662) );
CLKBUFX2TS U588 ( .A(n1156), .Y(n400) );
NOR2X1TS U589 ( .A(n760), .B(n761), .Y(n485) );
NOR2X1TS U590 ( .A(n778), .B(n780), .Y(n783) );
OAI21X1TS U591 ( .A0(n972), .A1(n980), .B0(n973), .Y(n950) );
OAI21X1TS U592 ( .A0(n766), .A1(n928), .B0(n765), .Y(n794) );
NOR2X1TS U593 ( .A(n1117), .B(DMP_SFG[8]), .Y(n766) );
NAND2X1TS U594 ( .A(n1146), .B(DMP_SFG[7]), .Y(n928) );
NAND2X1TS U595 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n746) );
NOR2XLTS U596 ( .A(n1047), .B(intDY_EWSW[10]), .Y(n1048) );
OAI21XLTS U597 ( .A0(intDX_EWSW[15]), .A1(n1225), .B0(intDX_EWSW[14]), .Y(
n1055) );
NOR2XLTS U598 ( .A(n1068), .B(intDY_EWSW[16]), .Y(n1069) );
OAI21XLTS U599 ( .A0(intDX_EWSW[23]), .A1(n1139), .B0(intDX_EWSW[22]), .Y(
n1075) );
NOR2XLTS U600 ( .A(n1119), .B(DMP_SFG[11]), .Y(n807) );
OAI21X1TS U601 ( .A0(n982), .A1(n517), .B0(n516), .Y(n964) );
INVX2TS U602 ( .A(n426), .Y(n427) );
NOR2XLTS U603 ( .A(n1191), .B(DMP_SFG[19]), .Y(n848) );
OAI21X2TS U604 ( .A0(n808), .A1(n807), .B0(n806), .Y(n922) );
OAI21XLTS U605 ( .A0(n1188), .A1(n710), .B0(n705), .Y(n706) );
AND2X4TS U606 ( .A(n457), .B(n456), .Y(n393) );
OAI21X1TS U607 ( .A0(n630), .A1(n412), .B0(n629), .Y(Data_array_SWR[15]) );
OAI21X1TS U608 ( .A0(n649), .A1(n413), .B0(n615), .Y(Data_array_SWR[19]) );
OAI21X1TS U609 ( .A0(n663), .A1(n413), .B0(n469), .Y(Data_array_SWR[12]) );
OAI21X1TS U610 ( .A0(n627), .A1(n413), .B0(n626), .Y(Data_array_SWR[16]) );
OAI21X1TS U611 ( .A0(n650), .A1(n412), .B0(n467), .Y(Data_array_SWR[20]) );
OAI21X1TS U612 ( .A0(n661), .A1(n413), .B0(n638), .Y(Data_array_SWR[11]) );
OAI21X1TS U613 ( .A0(n631), .A1(n413), .B0(n620), .Y(Data_array_SWR[8]) );
OAI21X1TS U614 ( .A0(n655), .A1(n412), .B0(n464), .Y(Data_array_SWR[4]) );
OAI21X1TS U615 ( .A0(n613), .A1(n413), .B0(n612), .Y(Data_array_SWR[3]) );
OAI21X1TS U616 ( .A0(n609), .A1(n412), .B0(n608), .Y(Data_array_SWR[1]) );
OAI21X1TS U617 ( .A0(n634), .A1(n412), .B0(n633), .Y(Data_array_SWR[7]) );
OAI21X1TS U618 ( .A0(n642), .A1(n413), .B0(n471), .Y(Data_array_SWR[21]) );
OAI21X1TS U619 ( .A0(n645), .A1(n413), .B0(n475), .Y(Data_array_SWR[13]) );
OAI21X1TS U620 ( .A0(n654), .A1(n413), .B0(n653), .Y(Data_array_SWR[17]) );
OAI21X1TS U621 ( .A0(n656), .A1(n413), .B0(n473), .Y(Data_array_SWR[5]) );
OAI21X1TS U622 ( .A0(n660), .A1(n412), .B0(n659), .Y(Data_array_SWR[2]) );
OAI21X1TS U623 ( .A0(n667), .A1(n412), .B0(n666), .Y(Data_array_SWR[9]) );
INVX4TS U624 ( .A(n393), .Y(n411) );
OAI211X1TS U625 ( .A0(n660), .A1(n415), .B0(n609), .C0(n560), .Y(
Data_array_SWR[0]) );
OAI21X1TS U626 ( .A0(n1106), .A1(n412), .B0(n556), .Y(Data_array_SWR[25]) );
AO22X1TS U627 ( .A0(n1233), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n1109), .Y(shft_value_mux_o_EWR[3]) );
AO22X1TS U628 ( .A0(n559), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n1109), .Y(shft_value_mux_o_EWR[4]) );
NAND3BX1TS U629 ( .AN(n510), .B(n509), .C(n508), .Y(LZD_raw_out_EWR[4]) );
INVX3TS U630 ( .A(n506), .Y(n504) );
NOR2X2TS U631 ( .A(n554), .B(n551), .Y(n552) );
INVX3TS U632 ( .A(n1095), .Y(n1093) );
AOI31X1TS U633 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n443), .A2(n1182), .B0(n442),
.Y(n438) );
INVX3TS U634 ( .A(n1095), .Y(n1097) );
INVX3TS U635 ( .A(n1095), .Y(n1098) );
OAI21X1TS U636 ( .A0(n396), .A1(n694), .B0(n539), .Y(sftr_odat_SHT2_SWR[0])
);
OAI21X1TS U637 ( .A0(n414), .A1(n694), .B0(n544), .Y(sftr_odat_SHT2_SWR[1])
);
OAI21X1TS U638 ( .A0(n701), .A1(n396), .B0(n548), .Y(sftr_odat_SHT2_SWR[25])
);
OAI21X1TS U639 ( .A0(n710), .A1(n564), .B0(n497), .Y(n498) );
CLKINVX2TS U640 ( .A(n658), .Y(n613) );
NAND3BX1TS U641 ( .AN(n1068), .B(n1066), .C(n1065), .Y(n1086) );
OAI21X1TS U642 ( .A0(n710), .A1(n1189), .B0(n709), .Y(n711) );
OAI21X1TS U643 ( .A0(n710), .A1(n1195), .B0(n495), .Y(n496) );
NAND3X1TS U644 ( .A(exp_rslt_NRM2_EW1[2]), .B(exp_rslt_NRM2_EW1[1]), .C(
exp_rslt_NRM2_EW1[0]), .Y(n549) );
AOI21X2TS U645 ( .A0(n784), .A1(n783), .B0(n782), .Y(n808) );
OAI21X2TS U646 ( .A0(Data_array_SWR[51]), .A1(n583), .B0(n582), .Y(n396) );
OAI211X1TS U647 ( .A0(n1027), .A1(n1083), .B0(n1026), .C0(n1025), .Y(n1032)
);
INVX3TS U648 ( .A(n532), .Y(n559) );
INVX3TS U649 ( .A(n532), .Y(n1233) );
INVX3TS U650 ( .A(n532), .Y(n621) );
NOR2X4TS U651 ( .A(n410), .B(n545), .Y(n546) );
INVX1TS U652 ( .A(n676), .Y(n679) );
INVX3TS U653 ( .A(n710), .Y(n536) );
AOI21X2TS U654 ( .A0(n964), .A1(n521), .B0(n520), .Y(n740) );
OR2X2TS U655 ( .A(shift_value_SHT2_EWR[4]), .B(n580), .Y(n397) );
OAI211X2TS U656 ( .A0(intDX_EWSW[20]), .A1(n1213), .B0(n1079), .C0(n1064),
.Y(n1073) );
NAND3X1TS U657 ( .A(n1226), .B(n1024), .C(intDX_EWSW[26]), .Y(n1026) );
OAI21X1TS U658 ( .A0(n445), .A1(Raw_mant_NRM_SWR[23]), .B0(n1184), .Y(n446)
);
NOR2X1TS U659 ( .A(n1082), .B(intDY_EWSW[24]), .Y(n1023) );
INVX2TS U660 ( .A(n774), .Y(n776) );
OAI211X2TS U661 ( .A0(intDX_EWSW[12]), .A1(n1217), .B0(n1059), .C0(n1045),
.Y(n1061) );
OR2X2TS U662 ( .A(shift_value_SHT2_EWR[4]), .B(n540), .Y(n398) );
CLKAND2X2TS U663 ( .A(n1124), .B(DMP_SFG[12]), .Y(n809) );
NAND2BX1TS U664 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1064) );
NAND2BX1TS U665 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1070) );
NAND2BX1TS U666 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1045) );
NAND2BX1TS U667 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1049) );
NOR2X4TS U668 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n493) );
NAND2BX1TS U669 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1024) );
NAND2BX1TS U670 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1025) );
NAND2BX1TS U671 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1080) );
NOR3X8TS U672 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[4]), .C(n675),
.Y(n672) );
NAND2X6TS U673 ( .A(n507), .B(n1116), .Y(n675) );
INVX4TS U674 ( .A(n447), .Y(n423) );
AOI21X2TS U675 ( .A0(n868), .A1(n867), .B0(n491), .Y(n876) );
OAI21X2TS U676 ( .A0(n805), .A1(n802), .B0(n803), .Y(n846) );
AOI21X2TS U677 ( .A0(n829), .A1(n828), .B0(n489), .Y(n805) );
OAI21X2TS U678 ( .A0(n897), .A1(n816), .B0(n815), .Y(n888) );
AOI21X2TS U679 ( .A0(n905), .A1(n814), .B0(n813), .Y(n897) );
OAI21X2TS U680 ( .A0(n841), .A1(n820), .B0(n819), .Y(n832) );
OAI21X2TS U681 ( .A0(n914), .A1(n812), .B0(n811), .Y(n905) );
NAND2X1TS U682 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n980) );
OAI21X2TS U683 ( .A0(n894), .A1(n891), .B0(n892), .Y(n885) );
OAI21X2TS U684 ( .A0(n838), .A1(n835), .B0(n836), .Y(n829) );
NAND2X1TS U685 ( .A(n1154), .B(n422), .Y(n982) );
AOI21X4TS U686 ( .A0(n861), .A1(n860), .B0(n859), .Y(n871) );
OAI21X2TS U687 ( .A0(n849), .A1(n848), .B0(n847), .Y(n861) );
CLKAND2X2TS U688 ( .A(n1203), .B(DMP_SFG[20]), .Y(n859) );
CLKAND2X2TS U689 ( .A(n1179), .B(DMP_SFG[16]), .Y(n817) );
AOI21X2TS U690 ( .A0(n832), .A1(n822), .B0(n821), .Y(n849) );
CLKAND2X2TS U691 ( .A(n1193), .B(DMP_SFG[18]), .Y(n821) );
CLKAND2X2TS U692 ( .A(n1157), .B(DMP_SFG[14]), .Y(n813) );
AOI2BB2XLTS U693 ( .B0(intDX_EWSW[3]), .B1(n1224), .A0N(intDY_EWSW[2]),
.A1N(n1038), .Y(n1039) );
OAI21XLTS U694 ( .A0(intDX_EWSW[3]), .A1(n1224), .B0(intDX_EWSW[2]), .Y(
n1038) );
OAI21X2TS U695 ( .A0(n740), .A1(n739), .B0(n738), .Y(n784) );
NAND2X1TS U696 ( .A(n750), .B(n737), .Y(n739) );
OAI21X2TS U697 ( .A0(n514), .A1(n481), .B0(n480), .Y(n758) );
NOR2X1TS U698 ( .A(n745), .B(n726), .Y(n479) );
AOI21X1TS U699 ( .A0(n794), .A1(n768), .B0(n767), .Y(n781) );
CLKAND2X2TS U700 ( .A(n1120), .B(DMP_SFG[9]), .Y(n767) );
NAND2X1TS U701 ( .A(n793), .B(n768), .Y(n778) );
OAI21XLTS U702 ( .A0(n930), .A1(n796), .B0(n795), .Y(n799) );
INVX2TS U703 ( .A(n793), .Y(n796) );
INVX2TS U704 ( .A(n794), .Y(n795) );
AOI222X1TS U705 ( .A0(n622), .A1(Raw_mant_NRM_SWR[18]), .B0(n559), .B1(
Raw_mant_NRM_SWR[7]), .C0(n1109), .C1(DmP_mant_SHT1_SW[16]), .Y(n623)
);
OAI21XLTS U706 ( .A0(n946), .A1(n752), .B0(n751), .Y(n755) );
INVX2TS U707 ( .A(n950), .Y(n963) );
INVX2TS U708 ( .A(n515), .Y(n938) );
OAI21XLTS U709 ( .A0(n930), .A1(n929), .B0(n928), .Y(n933) );
XNOR2X2TS U710 ( .A(DP_OP_15J179_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(n553)
);
INVX2TS U711 ( .A(n732), .Y(n522) );
NAND2X1TS U712 ( .A(n926), .B(n791), .Y(n760) );
OAI21XLTS U713 ( .A0(n930), .A1(n778), .B0(n781), .Y(n771) );
INVX2TS U714 ( .A(n972), .Y(n974) );
AOI222X4TS U715 ( .A0(n1232), .A1(Raw_mant_NRM_SWR[2]), .B0(n1233), .B1(
Raw_mant_NRM_SWR[23]), .C0(n1114), .C1(DmP_mant_SHT1_SW[0]), .Y(n660)
);
AOI211X2TS U716 ( .A0(n559), .A1(Raw_mant_NRM_SWR[0]), .B0(n555), .C0(n1109),
.Y(n1106) );
NOR2X1TS U717 ( .A(n424), .B(Raw_mant_NRM_SWR[15]), .Y(n676) );
NOR2XLTS U718 ( .A(n1192), .B(DMP_SFG[17]), .Y(n820) );
NOR2XLTS U719 ( .A(n1178), .B(DMP_SFG[15]), .Y(n816) );
NOR2XLTS U720 ( .A(n1123), .B(DMP_SFG[13]), .Y(n812) );
AOI21X1TS U721 ( .A0(n919), .A1(n918), .B0(n486), .Y(n911) );
MX2X1TS U722 ( .A(n882), .B(n881), .S0(n947), .Y(Raw_mant_SGF[25]) );
AOI2BB1XLTS U723 ( .A0N(array_comparators_LTComparator_N0), .A1N(
SIGN_FLAG_SHT1SHT2), .B0(array_comparators_GTComparator_N0), .Y(
formatted_number_W[31]) );
OAI2BB2XLTS U724 ( .B0(intDY_EWSW[0]), .B1(n1035), .A0N(intDX_EWSW[1]),
.A1N(n1223), .Y(n1037) );
NAND2BXLTS U725 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1036) );
NAND2BXLTS U726 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1051) );
NAND3XLTS U727 ( .A(n1218), .B(n1049), .C(intDX_EWSW[8]), .Y(n1050) );
OAI21XLTS U728 ( .A0(intDX_EWSW[13]), .A1(n1210), .B0(intDX_EWSW[12]), .Y(
n1046) );
OAI21XLTS U729 ( .A0(n735), .A1(n751), .B0(n734), .Y(n736) );
OAI21XLTS U730 ( .A0(n726), .A1(n746), .B0(n727), .Y(n478) );
NOR2X1TS U731 ( .A(n929), .B(n766), .Y(n793) );
INVX2TS U732 ( .A(n745), .Y(n747) );
INVX2TS U733 ( .A(n726), .Y(n728) );
INVX2TS U734 ( .A(n960), .Y(n962) );
INVX2TS U735 ( .A(n940), .Y(n942) );
INVX2TS U736 ( .A(n936), .Y(n937) );
CLKAND2X2TS U737 ( .A(n1202), .B(DMP_SFG[22]), .Y(n877) );
INVX2TS U738 ( .A(n951), .Y(n953) );
INVX2TS U739 ( .A(exp_rslt_NRM2_EW1[7]), .Y(n554) );
AO22XLTS U740 ( .A0(n403), .A1(Data_array_SWR[45]), .B0(n406), .B1(
Data_array_SWR[41]), .Y(n708) );
INVX2TS U741 ( .A(n761), .Y(n763) );
CLKBUFX2TS U742 ( .A(OP_FLAG_SFG), .Y(n985) );
AO22XLTS U743 ( .A0(Data_array_SWR[44]), .A1(n403), .B0(n406), .B1(
Data_array_SWR[40]), .Y(n713) );
NAND4XLTS U744 ( .A(n1022), .B(n1021), .C(n1020), .D(n1019), .Y(n1088) );
INVX2TS U745 ( .A(intDX_EWSW[28]), .Y(n1103) );
NAND2BXLTS U746 ( .AN(busy), .B(n1114), .Y(n_7_net_) );
OAI21XLTS U747 ( .A0(n634), .A1(n394), .B0(n459), .Y(Data_array_SWR[6]) );
MX2X1TS U748 ( .A(n788), .B(n787), .S0(n852), .Y(Raw_mant_SGF[13]) );
MX2X1TS U749 ( .A(n801), .B(n800), .S0(n852), .Y(Raw_mant_SGF[11]) );
OAI21XLTS U750 ( .A0(n927), .A1(n789), .B0(n925), .Y(n792) );
OAI21XLTS U751 ( .A0(n630), .A1(n394), .B0(n462), .Y(Data_array_SWR[14]) );
OAI21XLTS U752 ( .A0(n661), .A1(n411), .B0(n648), .Y(Data_array_SWR[10]) );
OAI21XLTS U753 ( .A0(n649), .A1(n411), .B0(n644), .Y(Data_array_SWR[18]) );
MX2X1TS U754 ( .A(n757), .B(n756), .S0(n852), .Y(Raw_mant_SGF[8]) );
MX2X1TS U755 ( .A(n744), .B(n743), .S0(n852), .Y(Raw_mant_SGF[9]) );
MX2X1TS U756 ( .A(n971), .B(n970), .S0(n985), .Y(Raw_mant_SGF[4]) );
MX2X1TS U757 ( .A(n949), .B(n948), .S0(n947), .Y(Raw_mant_SGF[7]) );
MX2X1TS U758 ( .A(n984), .B(n983), .S0(n985), .Y(Raw_mant_SGF[2]) );
CLKAND2X2TS U759 ( .A(n981), .B(n980), .Y(n984) );
MX2X1TS U760 ( .A(n935), .B(n934), .S0(n947), .Y(Raw_mant_SGF[10]) );
MX2X1TS U761 ( .A(n959), .B(n958), .S0(n985), .Y(Raw_mant_SGF[5]) );
CLKAND2X2TS U762 ( .A(n417), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
CLKAND2X2TS U763 ( .A(n416), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
CLKAND2X2TS U764 ( .A(n418), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
CLKAND2X2TS U765 ( .A(n417), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
CLKAND2X2TS U766 ( .A(n416), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
CLKAND2X2TS U767 ( .A(n418), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
CLKAND2X2TS U768 ( .A(n417), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U769 ( .A(n416), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
CLKAND2X2TS U770 ( .A(n418), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
CLKAND2X2TS U771 ( .A(n417), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
CLKAND2X2TS U772 ( .A(n416), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
CLKAND2X2TS U773 ( .A(n418), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U774 ( .A(n417), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U775 ( .A(n416), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
CLKAND2X2TS U776 ( .A(n418), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
CLKAND2X2TS U777 ( .A(n417), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
CLKAND2X2TS U778 ( .A(n416), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
CLKAND2X2TS U779 ( .A(n417), .B(n1158), .Y(formatted_number_W[13]) );
CLKAND2X2TS U780 ( .A(n416), .B(n1159), .Y(formatted_number_W[12]) );
CLKAND2X2TS U781 ( .A(n418), .B(n1160), .Y(formatted_number_W[11]) );
CLKAND2X2TS U782 ( .A(n417), .B(n1161), .Y(formatted_number_W[10]) );
CLKAND2X2TS U783 ( .A(n416), .B(n1162), .Y(formatted_number_W[9]) );
CLKAND2X2TS U784 ( .A(n418), .B(n1163), .Y(formatted_number_W[8]) );
NOR3X6TS U785 ( .A(n553), .B(exp_rslt_NRM2_EW1[7]), .C(n530), .Y(
array_comparators_LTComparator_N0) );
OR4X2TS U786 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n529), .Y(n530) );
NOR2XLTS U787 ( .A(array_comparators_GTComparator_N0), .B(n554), .Y(
formatted_number_W[30]) );
OR2X1TS U788 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[6]), .Y(formatted_number_W[29]) );
OR2X1TS U789 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[5]), .Y(formatted_number_W[28]) );
OR2X1TS U790 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[4]), .Y(formatted_number_W[27]) );
OR2X1TS U791 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[3]), .Y(formatted_number_W[26]) );
OR2X1TS U792 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[2]), .Y(formatted_number_W[25]) );
OR2X1TS U793 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[1]), .Y(formatted_number_W[24]) );
OR2X1TS U794 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[0]), .Y(formatted_number_W[23]) );
MX2X1TS U795 ( .A(n528), .B(n527), .S0(n985), .Y(Raw_mant_SGF[6]) );
MX2X1TS U796 ( .A(n924), .B(n923), .S0(n947), .Y(Raw_mant_SGF[14]) );
MX2X1TS U797 ( .A(N60), .B(n986), .S0(n985), .Y(Raw_mant_SGF[1]) );
AO22XLTS U798 ( .A0(n451), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n1109), .Y(shft_value_mux_o_EWR[2]) );
MX2X1TS U799 ( .A(n773), .B(n772), .S0(n852), .Y(Raw_mant_SGF[12]) );
OAI21XLTS U800 ( .A0(n927), .A1(n760), .B0(n759), .Y(n764) );
OAI21XLTS U801 ( .A0(n1106), .A1(n408), .B0(n641), .Y(Data_array_SWR[22]) );
MX2X1TS U802 ( .A(n979), .B(n978), .S0(n985), .Y(Raw_mant_SGF[3]) );
AOI211X1TS U803 ( .A0(n506), .A1(Raw_mant_NRM_SWR[0]), .B0(n505), .C0(n677),
.Y(n509) );
NAND4BX1TS U804 ( .AN(n505), .B(n438), .C(n437), .D(n436), .Y(
LZD_raw_out_EWR[1]) );
AOI31XLTS U805 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n447), .A2(n432), .B0(n678),
.Y(n437) );
NAND3BXLTS U806 ( .AN(Raw_mant_NRM_SWR[17]), .B(n447), .C(
Raw_mant_NRM_SWR[16]), .Y(n448) );
MX2X1TS U807 ( .A(n875), .B(n874), .S0(n947), .Y(Raw_mant_SGF[24]) );
MX2X1TS U808 ( .A(n865), .B(n864), .S0(n947), .Y(Raw_mant_SGF[23]) );
MX2X1TS U809 ( .A(n854), .B(n853), .S0(n852), .Y(Raw_mant_SGF[22]) );
MX2X1TS U810 ( .A(n826), .B(n825), .S0(n852), .Y(Raw_mant_SGF[21]) );
MX2X1TS U811 ( .A(n834), .B(n833), .S0(n852), .Y(Raw_mant_SGF[20]) );
MX2X1TS U812 ( .A(n843), .B(n842), .S0(n852), .Y(Raw_mant_SGF[19]) );
MX2X1TS U813 ( .A(n890), .B(n889), .S0(n947), .Y(Raw_mant_SGF[18]) );
MX2X1TS U814 ( .A(n899), .B(n898), .S0(n947), .Y(Raw_mant_SGF[17]) );
MX2X1TS U815 ( .A(n907), .B(n906), .S0(n947), .Y(Raw_mant_SGF[16]) );
MX2X1TS U816 ( .A(n916), .B(n915), .S0(n947), .Y(Raw_mant_SGF[15]) );
XOR2XLTS U817 ( .A(intadd_427_n1), .B(n987), .Y(Shift_amount_EXP_EW[4]) );
OA21XLTS U818 ( .A0(n583), .A1(Data_array_SWR[50]), .B0(n582), .Y(n395) );
NAND2X1TS U819 ( .A(n457), .B(n454), .Y(n452) );
BUFX3TS U820 ( .A(n452), .Y(n413) );
BUFX3TS U821 ( .A(n452), .Y(n412) );
INVX2TS U822 ( .A(n410), .Y(n715) );
CLKINVX3TS U823 ( .A(rst), .Y(n531) );
NOR2X4TS U824 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(n434)
);
NAND2X4TS U825 ( .A(n680), .B(n676), .Y(n431) );
NOR2X6TS U826 ( .A(n457), .B(n456), .Y(n625) );
OR2X2TS U827 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n421) );
XOR2X1TS U828 ( .A(DP_OP_15J179_122_6956_n28), .B(n421), .Y(
DP_OP_15J179_122_6956_n18) );
OR2X4TS U829 ( .A(array_comparators_LTComparator_N0), .B(
array_comparators_GTComparator_N0), .Y(n1108) );
INVX2TS U830 ( .A(n398), .Y(n401) );
INVX2TS U831 ( .A(n398), .Y(n402) );
INVX2TS U832 ( .A(n397), .Y(n403) );
INVX2TS U833 ( .A(n397), .Y(n404) );
INVX2TS U834 ( .A(n494), .Y(n405) );
INVX2TS U835 ( .A(n405), .Y(n406) );
INVX2TS U836 ( .A(n405), .Y(n407) );
INVX4TS U837 ( .A(n637), .Y(n455) );
INVX2TS U838 ( .A(left_right_SHT2), .Y(n409) );
INVX2TS U839 ( .A(n409), .Y(n410) );
OAI221X1TS U840 ( .A0(n1131), .A1(intDY_EWSW[3]), .B0(n1172), .B1(
intDY_EWSW[26]), .C0(n997), .Y(n1000) );
OAI221X1TS U841 ( .A0(n1128), .A1(intDY_EWSW[20]), .B0(n1176), .B1(
intDY_EWSW[30]), .C0(n1011), .Y(n1018) );
NOR2X2TS U842 ( .A(n423), .B(Raw_mant_NRM_SWR[18]), .Y(n680) );
INVX2TS U843 ( .A(n395), .Y(n414) );
OAI21X2TS U844 ( .A0(n583), .A1(Data_array_SWR[48]), .B0(n582), .Y(n697) );
OAI21X2TS U845 ( .A0(n583), .A1(Data_array_SWR[49]), .B0(n582), .Y(n700) );
CLKBUFX3TS U846 ( .A(n511), .Y(n1275) );
BUFX3TS U847 ( .A(n531), .Y(n513) );
CLKBUFX3TS U848 ( .A(n531), .Y(n511) );
AOI21X2TS U849 ( .A0(n493), .A1(Data_array_SWR[47]), .B0(n563), .Y(n594) );
AOI21X2TS U850 ( .A0(n493), .A1(Data_array_SWR[46]), .B0(n565), .Y(n600) );
OAI21X2TS U851 ( .A0(n1121), .A1(n556), .B0(n460), .Y(n636) );
NOR2XLTS U852 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[11]), .Y(n668)
);
INVX4TS U853 ( .A(n625), .Y(n415) );
INVX4TS U854 ( .A(n625), .Y(n704) );
INVX2TS U855 ( .A(n1108), .Y(n416) );
INVX2TS U856 ( .A(n1108), .Y(n417) );
INVX2TS U857 ( .A(n1108), .Y(n418) );
OAI221X1TS U858 ( .A0(n1165), .A1(intDY_EWSW[10]), .B0(n1134), .B1(
intDY_EWSW[2]), .C0(n989), .Y(n992) );
OAI221X1TS U859 ( .A0(n1130), .A1(intDY_EWSW[27]), .B0(n1171), .B1(
intDY_EWSW[19]), .C0(n1005), .Y(n1008) );
OAI221X1TS U860 ( .A0(n1166), .A1(intDY_EWSW[17]), .B0(n1181), .B1(
intDY_EWSW[16]), .C0(n1013), .Y(n1016) );
OAI21XLTS U861 ( .A0(DmP_EXP_EWSW[23]), .A1(n420), .B0(n534), .Y(
Shift_amount_EXP_EW[0]) );
OAI221X1TS U862 ( .A0(n1186), .A1(intDY_EWSW[7]), .B0(n1170), .B1(
intDY_EWSW[14]), .C0(n995), .Y(n1002) );
NOR2X2TS U863 ( .A(n1121), .B(n431), .Y(n678) );
OAI2BB2XLTS U864 ( .B0(n1054), .B1(n1061), .A0N(n1053), .A1N(n1052), .Y(
n1057) );
NAND2X4TS U865 ( .A(n715), .B(n400), .Y(n701) );
NAND2X4TS U866 ( .A(n1156), .B(left_right_SHT2), .Y(n694) );
BUFX3TS U867 ( .A(n531), .Y(n512) );
OAI21X2TS U868 ( .A0(n532), .A1(n1190), .B0(n465), .Y(n640) );
OAI21X2TS U869 ( .A0(n1116), .A1(n556), .B0(n453), .Y(n611) );
OR2X1TS U870 ( .A(n1120), .B(DMP_SFG[9]), .Y(n768) );
NOR2X1TS U871 ( .A(n1201), .B(DMP_SFG[21]), .Y(n870) );
AOI21X2TS U872 ( .A0(n493), .A1(Data_array_SWR[45]), .B0(n581), .Y(n687) );
AOI21X2TS U873 ( .A0(n493), .A1(Data_array_SWR[44]), .B0(n572), .Y(n691) );
NOR2X2TS U874 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n960) );
NOR2X2TS U875 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n951) );
AOI211X2TS U876 ( .A0(n493), .A1(Data_array_SWR[43]), .B0(n707), .C0(n541),
.Y(n589) );
AOI211X2TS U877 ( .A0(n493), .A1(Data_array_SWR[42]), .B0(n707), .C0(n535),
.Y(n604) );
NOR2X1TS U878 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n503)
);
NAND2X1TS U879 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n925) );
NOR2X4TS U880 ( .A(Raw_mant_NRM_SWR[7]), .B(n426), .Y(n507) );
AOI211X4TS U881 ( .A0(intDY_EWSW[28]), .A1(n419), .B0(n1030), .C0(n1028),
.Y(n1081) );
OAI221X1TS U882 ( .A0(n1103), .A1(intDY_EWSW[28]), .B0(n1137), .B1(
intDY_EWSW[6]), .C0(n1003), .Y(n1010) );
NOR2X4TS U883 ( .A(Raw_mant_NRM_SWR[10]), .B(n502), .Y(n425) );
OAI31X1TS U884 ( .A0(n503), .A1(Raw_mant_NRM_SWR[10]), .A2(n502), .B0(n501),
.Y(n510) );
OAI21XLTS U885 ( .A0(intDX_EWSW[1]), .A1(n1223), .B0(intDX_EWSW[0]), .Y(
n1035) );
OAI21XLTS U886 ( .A0(intDX_EWSW[21]), .A1(n1211), .B0(intDX_EWSW[20]), .Y(
n1067) );
NOR2X1TS U887 ( .A(n752), .B(n735), .Y(n737) );
NAND2X1TS U888 ( .A(n725), .B(n479), .Y(n481) );
INVX2TS U889 ( .A(n730), .Y(n523) );
OR2X1TS U890 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n791) );
OAI21XLTS U891 ( .A0(n963), .A1(n960), .B0(n961), .Y(n954) );
OR2X1TS U892 ( .A(n707), .B(n712), .Y(n714) );
NOR2X2TS U893 ( .A(Raw_mant_NRM_SWR[3]), .B(n439), .Y(n506) );
AOI21X2TS U894 ( .A0(n888), .A1(n818), .B0(n817), .Y(n841) );
OAI21X2TS U895 ( .A0(n911), .A1(n908), .B0(n909), .Y(n902) );
OAI21XLTS U896 ( .A0(n748), .A1(n745), .B0(n746), .Y(n729) );
OAI21XLTS U897 ( .A0(n977), .A1(n966), .B0(n965), .Y(n969) );
AND2X2TS U898 ( .A(n553), .B(n552), .Y(array_comparators_GTComparator_N0) );
OAI21XLTS U899 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n1111), .B0(
n1110), .Y(n388) );
NOR3X2TS U900 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .Y(n684) );
NOR3X2TS U901 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n670) );
NOR2X2TS U902 ( .A(Raw_mant_NRM_SWR[22]), .B(Raw_mant_NRM_SWR[23]), .Y(n433)
);
NAND2X2TS U903 ( .A(n434), .B(n433), .Y(n669) );
NOR2BX4TS U904 ( .AN(n670), .B(n669), .Y(n447) );
NOR2X2TS U905 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[17]), .Y(n432)
);
INVX2TS U906 ( .A(n432), .Y(n424) );
NOR2X4TS U907 ( .A(Raw_mant_NRM_SWR[14]), .B(n431), .Y(n430) );
NAND2X4TS U908 ( .A(n684), .B(n430), .Y(n502) );
NAND2X4TS U909 ( .A(n503), .B(n425), .Y(n426) );
OA21XLTS U910 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[2]), .B0(n672), .Y(n429) );
OAI21X1TS U911 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n427), .Y(n428) );
NAND2BX2TS U912 ( .AN(n429), .B(n428), .Y(n505) );
INVX2TS U913 ( .A(n430), .Y(n683) );
NOR2X1TS U914 ( .A(Raw_mant_NRM_SWR[13]), .B(n683), .Y(n443) );
NAND2BX1TS U915 ( .AN(n502), .B(Raw_mant_NRM_SWR[10]), .Y(n681) );
OAI2BB1X1TS U916 ( .A0N(Raw_mant_NRM_SWR[18]), .A1N(n447), .B0(n681), .Y(
n442) );
OAI31X1TS U917 ( .A0(n1194), .A1(Raw_mant_NRM_SWR[21]), .A2(
Raw_mant_NRM_SWR[20]), .B0(n433), .Y(n435) );
NAND2X1TS U918 ( .A(n435), .B(n434), .Y(n436) );
NAND2BX1TS U919 ( .AN(n675), .B(Raw_mant_NRM_SWR[4]), .Y(n501) );
AOI21X1TS U920 ( .A0(n1151), .A1(Raw_mant_NRM_SWR[0]), .B0(
Raw_mant_NRM_SWR[2]), .Y(n440) );
INVX2TS U921 ( .A(n672), .Y(n439) );
OAI22X4TS U922 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n501), .B0(n440), .B1(n504),
.Y(n441) );
AOI211X2TS U923 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n443), .B0(n442), .C0(n441),
.Y(n674) );
NOR4X1TS U924 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .D(n683), .Y(n444) );
AOI22X1TS U925 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n444), .B0(
Raw_mant_NRM_SWR[6]), .B1(n507), .Y(n450) );
AOI21X1TS U926 ( .A0(n1183), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n445) );
AOI21X1TS U927 ( .A0(n446), .A1(n1180), .B0(n678), .Y(n449) );
NAND4X2TS U928 ( .A(n674), .B(n450), .C(n449), .D(n448), .Y(
LZD_raw_out_EWR[0]) );
OR2X2TS U929 ( .A(n1155), .B(n1153), .Y(n556) );
INVX2TS U930 ( .A(n556), .Y(n616) );
BUFX3TS U931 ( .A(n1155), .Y(n618) );
NOR2X1TS U932 ( .A(ADD_OVRFLW_NRM), .B(n618), .Y(n451) );
INVX2TS U933 ( .A(n451), .Y(n532) );
BUFX3TS U934 ( .A(n1155), .Y(n1114) );
AOI222X4TS U935 ( .A0(n622), .A1(Raw_mant_NRM_SWR[7]), .B0(n621), .B1(
Raw_mant_NRM_SWR[18]), .C0(n1114), .C1(DmP_mant_SHT1_SW[5]), .Y(n634)
);
AOI22X4TS U936 ( .A0(n621), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n618), .Y(n457) );
OAI22X4TS U937 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n532), .Y(n454) );
INVX4TS U938 ( .A(n454), .Y(n456) );
INVX2TS U939 ( .A(n452), .Y(n647) );
AOI22X1TS U940 ( .A0(n1233), .A1(Raw_mant_NRM_SWR[19]), .B0(n618), .B1(
DmP_mant_SHT1_SW[4]), .Y(n453) );
INVX2TS U941 ( .A(n556), .Y(n622) );
AOI222X4TS U942 ( .A0(n618), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1232), .C0(Raw_mant_NRM_SWR[16]), .C1(n621),
.Y(n667) );
NOR2X4TS U943 ( .A(n454), .B(n457), .Y(n637) );
AOI222X4TS U944 ( .A0(n622), .A1(Raw_mant_NRM_SWR[8]), .B0(n621), .B1(
Raw_mant_NRM_SWR[17]), .C0(n1114), .C1(DmP_mant_SHT1_SW[6]), .Y(n631)
);
OAI22X1TS U945 ( .A0(n667), .A1(n408), .B0(n631), .B1(n704), .Y(n458) );
AOI21X1TS U946 ( .A0(n647), .A1(n611), .B0(n458), .Y(n459) );
INVX2TS U947 ( .A(n556), .Y(n1232) );
AOI222X4TS U948 ( .A0(n1114), .A1(DmP_mant_SHT1_SW[13]), .B0(n559), .B1(
Raw_mant_NRM_SWR[10]), .C0(Raw_mant_NRM_SWR[15]), .C1(n616), .Y(n630)
);
AOI22X1TS U949 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1233), .B0(
DmP_mant_SHT1_SW[12]), .B1(n618), .Y(n460) );
BUFX3TS U950 ( .A(n1155), .Y(n1109) );
AOI222X4TS U951 ( .A0(n622), .A1(Raw_mant_NRM_SWR[17]), .B0(n621), .B1(
Raw_mant_NRM_SWR[8]), .C0(n1109), .C1(DmP_mant_SHT1_SW[15]), .Y(n654)
);
AOI222X4TS U952 ( .A0(n1114), .A1(DmP_mant_SHT1_SW[14]), .B0(n621), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[16]), .C1(n1232), .Y(n627)
);
OAI22X1TS U953 ( .A0(n654), .A1(n408), .B0(n627), .B1(n704), .Y(n461) );
AOI21X1TS U954 ( .A0(n647), .A1(n636), .B0(n461), .Y(n462) );
AOI222X4TS U955 ( .A0(n616), .A1(Raw_mant_NRM_SWR[5]), .B0(n1233), .B1(
Raw_mant_NRM_SWR[20]), .C0(n1114), .C1(DmP_mant_SHT1_SW[3]), .Y(n656)
);
OAI22X1TS U956 ( .A0(n634), .A1(n408), .B0(n656), .B1(n411), .Y(n463) );
AOI21X1TS U957 ( .A0(n625), .A1(n611), .B0(n463), .Y(n464) );
AOI222X4TS U958 ( .A0(n1232), .A1(Raw_mant_NRM_SWR[20]), .B0(n621), .B1(
Raw_mant_NRM_SWR[5]), .C0(n1114), .C1(DmP_mant_SHT1_SW[18]), .Y(n650)
);
AOI22X1TS U959 ( .A0(n622), .A1(Raw_mant_NRM_SWR[22]), .B0(n618), .B1(
DmP_mant_SHT1_SW[20]), .Y(n465) );
AOI222X4TS U960 ( .A0(n1232), .A1(Raw_mant_NRM_SWR[23]), .B0(n559), .B1(
Raw_mant_NRM_SWR[2]), .C0(n1109), .C1(DmP_mant_SHT1_SW[21]), .Y(n703)
);
AOI222X4TS U961 ( .A0(n616), .A1(Raw_mant_NRM_SWR[21]), .B0(n559), .B1(
Raw_mant_NRM_SWR[4]), .C0(n1109), .C1(DmP_mant_SHT1_SW[19]), .Y(n642)
);
OAI22X1TS U962 ( .A0(n703), .A1(n408), .B0(n642), .B1(n394), .Y(n466) );
AOI21X1TS U963 ( .A0(n625), .A1(n640), .B0(n466), .Y(n467) );
AOI222X4TS U964 ( .A0(n618), .A1(DmP_mant_SHT1_SW[10]), .B0(
Raw_mant_NRM_SWR[12]), .B1(n616), .C0(Raw_mant_NRM_SWR[13]), .C1(n621),
.Y(n663) );
AOI222X4TS U965 ( .A0(n1114), .A1(DmP_mant_SHT1_SW[11]), .B0(n559), .B1(
Raw_mant_NRM_SWR[12]), .C0(Raw_mant_NRM_SWR[13]), .C1(n1232), .Y(n645)
);
OAI22X1TS U966 ( .A0(n630), .A1(n662), .B0(n645), .B1(n411), .Y(n468) );
AOI21X1TS U967 ( .A0(n625), .A1(n636), .B0(n468), .Y(n469) );
AOI222X4TS U968 ( .A0(n622), .A1(Raw_mant_NRM_SWR[24]), .B0(n559), .B1(
Raw_mant_NRM_SWR[1]), .C0(n1109), .C1(DmP_mant_SHT1_SW[22]), .Y(n1107)
);
OAI22X1TS U969 ( .A0(n1107), .A1(n408), .B0(n703), .B1(n704), .Y(n470) );
AOI21X1TS U970 ( .A0(n393), .A1(n640), .B0(n470), .Y(n471) );
OAI22X1TS U971 ( .A0(n631), .A1(n408), .B0(n634), .B1(n704), .Y(n472) );
AOI21X1TS U972 ( .A0(n393), .A1(n611), .B0(n472), .Y(n473) );
OAI22X1TS U973 ( .A0(n627), .A1(n662), .B0(n630), .B1(n704), .Y(n474) );
AOI21X1TS U974 ( .A0(n393), .A1(n636), .B0(n474), .Y(n475) );
NOR2X1TS U975 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n972) );
NAND2X1TS U976 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n973) );
NOR2X1TS U977 ( .A(n960), .B(n951), .Y(n477) );
NAND2X1TS U978 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n961) );
NAND2X1TS U979 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n952) );
OAI21X1TS U980 ( .A0(n951), .A1(n961), .B0(n952), .Y(n476) );
AOI21X2TS U981 ( .A0(n950), .A1(n477), .B0(n476), .Y(n514) );
NOR2X1TS U982 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n515) );
NOR2X2TS U983 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n940) );
NOR2X1TS U984 ( .A(n515), .B(n940), .Y(n725) );
NOR2X2TS U985 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n745) );
NOR2X2TS U986 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n726) );
NAND2X1TS U987 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n936) );
NAND2X1TS U988 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n941) );
OAI21X1TS U989 ( .A0(n940), .A1(n936), .B0(n941), .Y(n724) );
NAND2X1TS U990 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n727) );
AOI21X1TS U991 ( .A0(n724), .A1(n479), .B0(n478), .Y(n480) );
NOR2X1TS U992 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n789) );
INVX2TS U993 ( .A(n789), .Y(n926) );
NOR2X2TS U994 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n761) );
INVX2TS U995 ( .A(n925), .Y(n483) );
NAND2X1TS U996 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n790) );
INVX2TS U997 ( .A(n790), .Y(n482) );
AOI21X1TS U998 ( .A0(n791), .A1(n483), .B0(n482), .Y(n759) );
NAND2X1TS U999 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n762) );
OAI21X1TS U1000 ( .A0(n759), .A1(n761), .B0(n762), .Y(n484) );
AOI21X4TS U1001 ( .A0(n758), .A1(n485), .B0(n484), .Y(n777) );
NOR2X1TS U1002 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n774) );
NAND2X1TS U1003 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n775) );
OAI21X4TS U1004 ( .A0(n777), .A1(n774), .B0(n775), .Y(n919) );
OR2X1TS U1005 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n918) );
NAND2X1TS U1006 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n917) );
INVX2TS U1007 ( .A(n917), .Y(n486) );
NOR2X1TS U1008 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n908) );
NAND2X1TS U1009 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n909) );
OR2X1TS U1010 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n901) );
NAND2X1TS U1011 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n900) );
INVX2TS U1012 ( .A(n900), .Y(n487) );
AOI21X4TS U1013 ( .A0(n902), .A1(n901), .B0(n487), .Y(n894) );
NOR2X1TS U1014 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n891) );
NAND2X1TS U1015 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n892) );
OR2X1TS U1016 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n884) );
NAND2X1TS U1017 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n883) );
INVX2TS U1018 ( .A(n883), .Y(n488) );
AOI21X4TS U1019 ( .A0(n885), .A1(n884), .B0(n488), .Y(n838) );
NOR2X1TS U1020 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n835) );
NAND2X1TS U1021 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n836) );
OR2X1TS U1022 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n828) );
NAND2X1TS U1023 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n827) );
INVX2TS U1024 ( .A(n827), .Y(n489) );
NOR2X1TS U1025 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n802) );
NAND2X1TS U1026 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n803) );
OR2X1TS U1027 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n845) );
NAND2X1TS U1028 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n844) );
INVX2TS U1029 ( .A(n844), .Y(n490) );
AOI21X4TS U1030 ( .A0(n846), .A1(n845), .B0(n490), .Y(n858) );
NOR2X1TS U1031 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n855) );
NAND2X1TS U1032 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n856) );
OAI21X4TS U1033 ( .A0(n858), .A1(n855), .B0(n856), .Y(n868) );
OR2X1TS U1034 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n867) );
NAND2X1TS U1035 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n866) );
INVX2TS U1036 ( .A(n866), .Y(n491) );
NAND2X1TS U1037 ( .A(n876), .B(n1230), .Y(n492) );
BUFX3TS U1038 ( .A(OP_FLAG_SFG), .Y(n852) );
NOR2BX1TS U1039 ( .AN(n492), .B(n852), .Y(ADD_OVRFLW_SGF) );
NAND2X1TS U1040 ( .A(shift_value_SHT2_EWR[3]), .B(n1177), .Y(n540) );
NAND2X1TS U1041 ( .A(shift_value_SHT2_EWR[4]), .B(bit_shift_SHT2), .Y(n545)
);
INVX2TS U1042 ( .A(n545), .Y(n712) );
NAND3X2TS U1043 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.C(n400), .Y(n710) );
NAND2BX2TS U1044 ( .AN(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n580) );
NOR2BX1TS U1045 ( .AN(n493), .B(shift_value_SHT2_EWR[4]), .Y(n494) );
AOI22X1TS U1046 ( .A0(n403), .A1(Data_array_SWR[43]), .B0(n406), .B1(
Data_array_SWR[39]), .Y(n495) );
AOI211X1TS U1047 ( .A0(n402), .A1(Data_array_SWR[47]), .B0(n712), .C0(n496),
.Y(n499) );
INVX1TS U1048 ( .A(Data_array_SWR[50]), .Y(n564) );
AOI22X1TS U1049 ( .A0(n403), .A1(Data_array_SWR[42]), .B0(n406), .B1(
Data_array_SWR[38]), .Y(n497) );
AOI211X1TS U1050 ( .A0(n402), .A1(Data_array_SWR[46]), .B0(n712), .C0(n498),
.Y(n500) );
MXI2X1TS U1051 ( .A(n499), .B(n500), .S0(left_right_SHT2), .Y(n1160) );
MXI2X1TS U1052 ( .A(n500), .B(n499), .S0(n410), .Y(n1161) );
NAND2X1TS U1053 ( .A(DmP_EXP_EWSW[23]), .B(n420), .Y(n534) );
NOR3X1TS U1054 ( .A(Raw_mant_NRM_SWR[2]), .B(n504), .C(n1151), .Y(n677) );
NAND2X1TS U1055 ( .A(Raw_mant_NRM_SWR[5]), .B(n507), .Y(n508) );
AOI33XLTS U1056 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n1140), .B1(n1115), .B2(n1197), .Y(n390) );
BUFX3TS U1057 ( .A(n511), .Y(n1250) );
BUFX3TS U1058 ( .A(n531), .Y(n1249) );
BUFX3TS U1059 ( .A(n513), .Y(n1257) );
BUFX3TS U1060 ( .A(n531), .Y(n1248) );
BUFX3TS U1061 ( .A(n511), .Y(n1270) );
BUFX3TS U1062 ( .A(n1253), .Y(n1271) );
BUFX3TS U1063 ( .A(n512), .Y(n1272) );
BUFX3TS U1064 ( .A(n1252), .Y(n1273) );
BUFX3TS U1065 ( .A(n513), .Y(n1274) );
BUFX3TS U1066 ( .A(n531), .Y(n1253) );
BUFX3TS U1067 ( .A(n1248), .Y(n1263) );
BUFX3TS U1068 ( .A(n512), .Y(n1254) );
BUFX3TS U1069 ( .A(n511), .Y(n1251) );
BUFX3TS U1070 ( .A(n531), .Y(n1252) );
BUFX3TS U1071 ( .A(n1249), .Y(n1265) );
BUFX3TS U1072 ( .A(n1246), .Y(n1262) );
BUFX3TS U1073 ( .A(n513), .Y(n1259) );
BUFX3TS U1074 ( .A(n1246), .Y(n1260) );
BUFX3TS U1075 ( .A(n1248), .Y(n1261) );
BUFX3TS U1076 ( .A(n512), .Y(n1239) );
BUFX3TS U1077 ( .A(n1252), .Y(n1242) );
BUFX3TS U1078 ( .A(n1275), .Y(n1240) );
BUFX3TS U1079 ( .A(n1275), .Y(n1241) );
BUFX3TS U1080 ( .A(n1249), .Y(n1255) );
BUFX3TS U1081 ( .A(n1275), .Y(n1256) );
BUFX3TS U1082 ( .A(n511), .Y(n1266) );
BUFX3TS U1083 ( .A(n511), .Y(n1269) );
BUFX3TS U1084 ( .A(n531), .Y(n1246) );
BUFX3TS U1085 ( .A(n1249), .Y(n1238) );
BUFX3TS U1086 ( .A(n1253), .Y(n1237) );
BUFX3TS U1087 ( .A(n512), .Y(n1236) );
BUFX3TS U1088 ( .A(n1246), .Y(n1235) );
BUFX3TS U1089 ( .A(n1252), .Y(n1268) );
BUFX3TS U1090 ( .A(n1252), .Y(n1245) );
BUFX3TS U1091 ( .A(n1246), .Y(n1258) );
BUFX3TS U1092 ( .A(n1248), .Y(n1264) );
BUFX3TS U1093 ( .A(n1253), .Y(n1234) );
BUFX3TS U1094 ( .A(n1275), .Y(n1244) );
BUFX3TS U1095 ( .A(n1249), .Y(n1267) );
BUFX3TS U1096 ( .A(n1253), .Y(n1243) );
INVX2TS U1097 ( .A(n514), .Y(n939) );
NAND2X1TS U1098 ( .A(n938), .B(n936), .Y(n524) );
XNOR2X1TS U1099 ( .A(n939), .B(n524), .Y(n528) );
NOR2XLTS U1100 ( .A(n1152), .B(DMP_SFG[0]), .Y(n517) );
NAND2X1TS U1101 ( .A(n1152), .B(DMP_SFG[0]), .Y(n516) );
NOR2X1TS U1102 ( .A(n1149), .B(DMP_SFG[1]), .Y(n966) );
NOR2X1TS U1103 ( .A(n1145), .B(DMP_SFG[2]), .Y(n519) );
NOR2X1TS U1104 ( .A(n966), .B(n519), .Y(n521) );
NAND2X1TS U1105 ( .A(n1149), .B(DMP_SFG[1]), .Y(n965) );
NAND2X1TS U1106 ( .A(n1145), .B(DMP_SFG[2]), .Y(n518) );
OAI21X1TS U1107 ( .A0(n519), .A1(n965), .B0(n518), .Y(n520) );
INVX2TS U1108 ( .A(n740), .Y(n957) );
NOR2X1TS U1109 ( .A(n1148), .B(DMP_SFG[3]), .Y(n730) );
NAND2X1TS U1110 ( .A(n1148), .B(DMP_SFG[3]), .Y(n732) );
AOI21X1TS U1111 ( .A0(n957), .A1(n523), .B0(n522), .Y(n526) );
INVX2TS U1112 ( .A(n524), .Y(n525) );
XOR2X1TS U1113 ( .A(n526), .B(n525), .Y(n527) );
OR4X2TS U1114 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n529) );
CLKBUFX3TS U1115 ( .A(n531), .Y(n1247) );
NAND2X1TS U1116 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1115), .Y(
n1111) );
NAND2X1TS U1117 ( .A(n1140), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(
n1110) );
INVX2TS U1118 ( .A(intadd_427_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
OAI211X1TS U1119 ( .A0(n1115), .A1(n1110), .B0(n1111), .C0(beg_OP), .Y(n533)
);
INVX2TS U1120 ( .A(n533), .Y(enable_Pipeline_input) );
INVX2TS U1121 ( .A(intadd_427_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
INVX2TS U1122 ( .A(intadd_427_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U1123 ( .A(n534), .Y(intadd_427_CI) );
NOR2BX2TS U1124 ( .AN(bit_shift_SHT2), .B(n493), .Y(n583) );
OR2X2TS U1125 ( .A(n583), .B(n493), .Y(n582) );
NAND2X2TS U1126 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n579)
);
NOR2X2TS U1127 ( .A(n579), .B(n1177), .Y(n707) );
OAI22X1TS U1128 ( .A0(n580), .A1(n1200), .B0(n540), .B1(n564), .Y(n535) );
AOI22X1TS U1129 ( .A0(n407), .A1(Data_array_SWR[26]), .B0(n536), .B1(
Data_array_SWR[38]), .Y(n538) );
AOI22X1TS U1130 ( .A0(n404), .A1(Data_array_SWR[30]), .B0(n402), .B1(
Data_array_SWR[34]), .Y(n537) );
OAI211X1TS U1131 ( .A0(n604), .A1(n1156), .B0(n538), .C0(n537), .Y(n547) );
NOR2X2TS U1132 ( .A(n715), .B(n545), .Y(n692) );
AOI21X1TS U1133 ( .A0(n547), .A1(n715), .B0(n692), .Y(n539) );
OAI22X1TS U1134 ( .A0(n580), .A1(n1138), .B0(n540), .B1(n1195), .Y(n541) );
AOI22X1TS U1135 ( .A0(n536), .A1(Data_array_SWR[39]), .B0(n401), .B1(
Data_array_SWR[35]), .Y(n543) );
AOI22X1TS U1136 ( .A0(n404), .A1(Data_array_SWR[31]), .B0(n407), .B1(
Data_array_SWR[27]), .Y(n542) );
OAI211X1TS U1137 ( .A0(n589), .A1(n1156), .B0(n543), .C0(n542), .Y(n561) );
AOI21X1TS U1138 ( .A0(n561), .A1(n715), .B0(n692), .Y(n544) );
AOI21X1TS U1139 ( .A0(n410), .A1(n547), .B0(n546), .Y(n548) );
NAND3BX1TS U1140 ( .AN(n549), .B(exp_rslt_NRM2_EW1[4]), .C(
exp_rslt_NRM2_EW1[3]), .Y(n550) );
NAND3BX1TS U1141 ( .AN(n550), .B(exp_rslt_NRM2_EW1[6]), .C(
exp_rslt_NRM2_EW1[5]), .Y(n551) );
NOR2X1TS U1142 ( .A(n559), .B(n1180), .Y(n555) );
AOI22X1TS U1143 ( .A0(n616), .A1(Raw_mant_NRM_SWR[1]), .B0(n1233), .B1(
Raw_mant_NRM_SWR[24]), .Y(n609) );
NAND2X1TS U1144 ( .A(n616), .B(Raw_mant_NRM_SWR[3]), .Y(n558) );
AOI22X1TS U1145 ( .A0(n621), .A1(Raw_mant_NRM_SWR[22]), .B0(n618), .B1(
DmP_mant_SHT1_SW[1]), .Y(n557) );
NAND2X1TS U1146 ( .A(n558), .B(n557), .Y(n658) );
AOI22X1TS U1147 ( .A0(n637), .A1(n658), .B0(n1233), .B1(Raw_mant_NRM_SWR[25]), .Y(n560) );
AOI21X1TS U1148 ( .A0(left_right_SHT2), .A1(n561), .B0(n546), .Y(n562) );
OAI21X1TS U1149 ( .A0(n701), .A1(n414), .B0(n562), .Y(sftr_odat_SHT2_SWR[24]) );
OAI21X1TS U1150 ( .A0(n580), .A1(n1195), .B0(n579), .Y(n563) );
OAI21X1TS U1151 ( .A0(n580), .A1(n564), .B0(n579), .Y(n565) );
AOI22X1TS U1152 ( .A0(n536), .A1(Data_array_SWR[42]), .B0(n401), .B1(
Data_array_SWR[38]), .Y(n567) );
AOI22X1TS U1153 ( .A0(n404), .A1(Data_array_SWR[34]), .B0(n407), .B1(
Data_array_SWR[30]), .Y(n566) );
OAI211X1TS U1154 ( .A0(n600), .A1(n1156), .B0(n567), .C0(n566), .Y(n590) );
NAND2X1TS U1155 ( .A(n590), .B(n715), .Y(n568) );
INVX2TS U1156 ( .A(n692), .Y(n602) );
OAI211X1TS U1157 ( .A0(n594), .A1(n694), .B0(n568), .C0(n602), .Y(
sftr_odat_SHT2_SWR[4]) );
AOI22X1TS U1158 ( .A0(n406), .A1(Data_array_SWR[35]), .B0(n536), .B1(
Data_array_SWR[47]), .Y(n570) );
AOI22X1TS U1159 ( .A0(n404), .A1(Data_array_SWR[39]), .B0(n401), .B1(
Data_array_SWR[43]), .Y(n569) );
OAI211X1TS U1160 ( .A0(n396), .A1(n1156), .B0(n570), .C0(n569), .Y(n601) );
AOI21X1TS U1161 ( .A0(n410), .A1(n601), .B0(n546), .Y(n571) );
OAI21X1TS U1162 ( .A0(n701), .A1(n604), .B0(n571), .Y(sftr_odat_SHT2_SWR[16]) );
OAI21X1TS U1163 ( .A0(n580), .A1(n1188), .B0(n579), .Y(n572) );
AOI22X1TS U1164 ( .A0(n404), .A1(Data_array_SWR[37]), .B0(n407), .B1(
Data_array_SWR[33]), .Y(n574) );
AOI22X1TS U1165 ( .A0(n536), .A1(Data_array_SWR[45]), .B0(n401), .B1(
Data_array_SWR[41]), .Y(n573) );
OAI211X1TS U1166 ( .A0(n700), .A1(n1156), .B0(n574), .C0(n573), .Y(n605) );
NAND2X1TS U1167 ( .A(n605), .B(n409), .Y(n575) );
OAI211X1TS U1168 ( .A0(n691), .A1(n694), .B0(n575), .C0(n602), .Y(
sftr_odat_SHT2_SWR[7]) );
AOI22X1TS U1169 ( .A0(n404), .A1(Data_array_SWR[38]), .B0(n407), .B1(
Data_array_SWR[34]), .Y(n577) );
AOI22X1TS U1170 ( .A0(n536), .A1(Data_array_SWR[46]), .B0(n401), .B1(
Data_array_SWR[42]), .Y(n576) );
OAI211X1TS U1171 ( .A0(n414), .A1(n1156), .B0(n577), .C0(n576), .Y(n587) );
NAND2X1TS U1172 ( .A(n587), .B(n399), .Y(n578) );
OAI211X1TS U1173 ( .A0(n589), .A1(n694), .B0(n578), .C0(n602), .Y(
sftr_odat_SHT2_SWR[8]) );
OAI21X1TS U1174 ( .A0(n580), .A1(n1189), .B0(n579), .Y(n581) );
AOI22X1TS U1175 ( .A0(n404), .A1(Data_array_SWR[36]), .B0(Data_array_SWR[32]), .B1(n407), .Y(n585) );
AOI22X1TS U1176 ( .A0(Data_array_SWR[44]), .A1(n536), .B0(Data_array_SWR[40]), .B1(n401), .Y(n584) );
OAI211X1TS U1177 ( .A0(n697), .A1(n1156), .B0(n585), .C0(n584), .Y(n596) );
NAND2X1TS U1178 ( .A(n596), .B(n409), .Y(n586) );
OAI211X1TS U1179 ( .A0(n687), .A1(n694), .B0(n586), .C0(n602), .Y(
sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U1180 ( .A0(n410), .A1(n587), .B0(n546), .Y(n588) );
OAI21X1TS U1181 ( .A0(n701), .A1(n589), .B0(n588), .Y(sftr_odat_SHT2_SWR[17]) );
AOI21X1TS U1182 ( .A0(left_right_SHT2), .A1(n590), .B0(n546), .Y(n591) );
OAI21X1TS U1183 ( .A0(n701), .A1(n594), .B0(n591), .Y(sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U1184 ( .A0(n536), .A1(Data_array_SWR[43]), .B0(n402), .B1(
Data_array_SWR[39]), .Y(n593) );
AOI22X1TS U1185 ( .A0(n404), .A1(Data_array_SWR[35]), .B0(n407), .B1(
Data_array_SWR[31]), .Y(n592) );
OAI211X1TS U1186 ( .A0(n594), .A1(n400), .B0(n593), .C0(n592), .Y(n598) );
NAND2X1TS U1187 ( .A(n598), .B(n399), .Y(n595) );
OAI211X1TS U1188 ( .A0(n600), .A1(n694), .B0(n595), .C0(n602), .Y(
sftr_odat_SHT2_SWR[5]) );
AOI21X1TS U1189 ( .A0(left_right_SHT2), .A1(n596), .B0(n546), .Y(n597) );
OAI21X1TS U1190 ( .A0(n687), .A1(n701), .B0(n597), .Y(sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U1191 ( .A0(n410), .A1(n598), .B0(n546), .Y(n599) );
OAI21X1TS U1192 ( .A0(n701), .A1(n600), .B0(n599), .Y(sftr_odat_SHT2_SWR[20]) );
NAND2X1TS U1193 ( .A(n601), .B(n409), .Y(n603) );
OAI211X1TS U1194 ( .A0(n604), .A1(n694), .B0(n603), .C0(n602), .Y(
sftr_odat_SHT2_SWR[9]) );
AOI21X1TS U1195 ( .A0(left_right_SHT2), .A1(n605), .B0(n546), .Y(n606) );
OAI21X1TS U1196 ( .A0(n701), .A1(n691), .B0(n606), .Y(sftr_odat_SHT2_SWR[18]) );
OAI22X1TS U1197 ( .A0(n655), .A1(n662), .B0(n660), .B1(n411), .Y(n607) );
AOI21X1TS U1198 ( .A0(n625), .A1(n658), .B0(n607), .Y(n608) );
OAI22X1TS U1199 ( .A0(n656), .A1(n415), .B0(n655), .B1(n411), .Y(n610) );
AOI21X1TS U1200 ( .A0(n637), .A1(n611), .B0(n610), .Y(n612) );
AOI222X4TS U1201 ( .A0(n616), .A1(Raw_mant_NRM_SWR[19]), .B0(n621), .B1(
Raw_mant_NRM_SWR[6]), .C0(n1109), .C1(DmP_mant_SHT1_SW[17]), .Y(n649)
);
OAI22X1TS U1202 ( .A0(n642), .A1(n704), .B0(n650), .B1(n394), .Y(n614) );
AOI21X1TS U1203 ( .A0(n637), .A1(n640), .B0(n614), .Y(n615) );
AOI22X1TS U1204 ( .A0(n622), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n618), .Y(n617) );
OAI2BB1X1TS U1205 ( .A0N(n1233), .A1N(Raw_mant_NRM_SWR[15]), .B0(n617), .Y(
n665) );
AOI222X4TS U1206 ( .A0(n618), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n616), .C0(Raw_mant_NRM_SWR[14]), .C1(n1233), .Y(n661) );
OAI22X1TS U1207 ( .A0(n661), .A1(n662), .B0(n667), .B1(n394), .Y(n619) );
AOI21X1TS U1208 ( .A0(n625), .A1(n665), .B0(n619), .Y(n620) );
INVX2TS U1209 ( .A(n623), .Y(n652) );
OAI22X1TS U1210 ( .A0(n649), .A1(n662), .B0(n654), .B1(n394), .Y(n624) );
AOI21X1TS U1211 ( .A0(n625), .A1(n652), .B0(n624), .Y(n626) );
OAI22X1TS U1212 ( .A0(n654), .A1(n415), .B0(n627), .B1(n394), .Y(n628) );
AOI21X1TS U1213 ( .A0(n637), .A1(n652), .B0(n628), .Y(n629) );
OAI22X1TS U1214 ( .A0(n667), .A1(n415), .B0(n631), .B1(n394), .Y(n632) );
AOI21X1TS U1215 ( .A0(n637), .A1(n665), .B0(n632), .Y(n633) );
OAI22X1TS U1216 ( .A0(n645), .A1(n415), .B0(n663), .B1(n394), .Y(n635) );
AOI21X1TS U1217 ( .A0(n637), .A1(n636), .B0(n635), .Y(n638) );
OAI22X1TS U1218 ( .A0(n1107), .A1(n415), .B0(n703), .B1(n411), .Y(n639) );
AOI21X1TS U1219 ( .A0(n647), .A1(n640), .B0(n639), .Y(n641) );
OAI22X1TS U1220 ( .A0(n642), .A1(n408), .B0(n650), .B1(n415), .Y(n643) );
AOI21X1TS U1221 ( .A0(n647), .A1(n652), .B0(n643), .Y(n644) );
OAI22X1TS U1222 ( .A0(n645), .A1(n662), .B0(n663), .B1(n704), .Y(n646) );
AOI21X1TS U1223 ( .A0(n647), .A1(n665), .B0(n646), .Y(n648) );
OAI22X1TS U1224 ( .A0(n650), .A1(n408), .B0(n649), .B1(n415), .Y(n651) );
AOI21X1TS U1225 ( .A0(n393), .A1(n652), .B0(n651), .Y(n653) );
OAI22X1TS U1226 ( .A0(n656), .A1(n662), .B0(n655), .B1(n704), .Y(n657) );
AOI21X1TS U1227 ( .A0(n393), .A1(n658), .B0(n657), .Y(n659) );
OAI22X1TS U1228 ( .A0(n663), .A1(n662), .B0(n661), .B1(n415), .Y(n664) );
AOI21X1TS U1229 ( .A0(n393), .A1(n665), .B0(n664), .Y(n666) );
OAI22X1TS U1230 ( .A0(n670), .A1(n669), .B0(n668), .B1(n683), .Y(n671) );
AOI21X1TS U1231 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n672), .B0(n671), .Y(n673)
);
OAI211X1TS U1232 ( .A0(n675), .A1(n1196), .B0(n674), .C0(n673), .Y(
LZD_raw_out_EWR[2]) );
AOI211X1TS U1233 ( .A0(n680), .A1(n679), .B0(n678), .C0(n677), .Y(n682) );
OAI211X1TS U1234 ( .A0(n684), .A1(n683), .B0(n682), .C0(n681), .Y(
LZD_raw_out_EWR[3]) );
AOI22X1TS U1235 ( .A0(n536), .A1(Data_array_SWR[41]), .B0(n401), .B1(
Data_array_SWR[37]), .Y(n686) );
AOI22X1TS U1236 ( .A0(n403), .A1(Data_array_SWR[33]), .B0(n407), .B1(
Data_array_SWR[29]), .Y(n685) );
OAI211X1TS U1237 ( .A0(n687), .A1(n1156), .B0(n686), .C0(n685), .Y(n695) );
AOI21X1TS U1238 ( .A0(n695), .A1(n715), .B0(n692), .Y(n688) );
OAI21X1TS U1239 ( .A0(n697), .A1(n694), .B0(n688), .Y(sftr_odat_SHT2_SWR[3])
);
AOI22X1TS U1240 ( .A0(n536), .A1(Data_array_SWR[40]), .B0(n401), .B1(
Data_array_SWR[36]), .Y(n690) );
AOI22X1TS U1241 ( .A0(n404), .A1(Data_array_SWR[32]), .B0(n407), .B1(
Data_array_SWR[28]), .Y(n689) );
OAI211X1TS U1242 ( .A0(n691), .A1(n400), .B0(n690), .C0(n689), .Y(n698) );
AOI21X1TS U1243 ( .A0(n698), .A1(n409), .B0(n692), .Y(n693) );
OAI21X1TS U1244 ( .A0(n700), .A1(n694), .B0(n693), .Y(sftr_odat_SHT2_SWR[2])
);
AOI21X1TS U1245 ( .A0(left_right_SHT2), .A1(n695), .B0(n546), .Y(n696) );
OAI21X1TS U1246 ( .A0(n701), .A1(n697), .B0(n696), .Y(sftr_odat_SHT2_SWR[22]) );
AOI21X1TS U1247 ( .A0(left_right_SHT2), .A1(n698), .B0(n546), .Y(n699) );
OAI21X1TS U1248 ( .A0(n701), .A1(n700), .B0(n699), .Y(sftr_odat_SHT2_SWR[23]) );
NOR2BX1TS U1249 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n702)
);
XOR2X1TS U1250 ( .A(DP_OP_15J179_122_6956_n28), .B(n702), .Y(
DP_OP_15J179_122_6956_n14) );
OAI222X1TS U1251 ( .A0(n415), .A1(n1106), .B0(n412), .B1(n703), .C0(n394),
.C1(n1107), .Y(Data_array_SWR[23]) );
AOI22X1TS U1252 ( .A0(n403), .A1(Data_array_SWR[40]), .B0(n406), .B1(
Data_array_SWR[36]), .Y(n705) );
AOI211X1TS U1253 ( .A0(Data_array_SWR[44]), .A1(n402), .B0(n712), .C0(n706),
.Y(n720) );
AOI211X1TS U1254 ( .A0(n402), .A1(Data_array_SWR[49]), .B0(n714), .C0(n708),
.Y(n719) );
MXI2X1TS U1255 ( .A(n720), .B(n719), .S0(n715), .Y(n1158) );
AOI22X1TS U1256 ( .A0(n403), .A1(Data_array_SWR[41]), .B0(n406), .B1(
Data_array_SWR[37]), .Y(n709) );
AOI211X1TS U1257 ( .A0(n402), .A1(Data_array_SWR[45]), .B0(n712), .C0(n711),
.Y(n717) );
AOI211X1TS U1258 ( .A0(Data_array_SWR[48]), .A1(n402), .B0(n714), .C0(n713),
.Y(n716) );
MXI2X1TS U1259 ( .A(n717), .B(n716), .S0(n409), .Y(n1159) );
MXI2X1TS U1260 ( .A(n717), .B(n716), .S0(left_right_SHT2), .Y(n1162) );
MXI2X1TS U1261 ( .A(n720), .B(n719), .S0(n410), .Y(n1163) );
NOR2BX1TS U1262 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n721)
);
XOR2X1TS U1263 ( .A(DP_OP_15J179_122_6956_n28), .B(n721), .Y(
DP_OP_15J179_122_6956_n15) );
NOR2BX1TS U1264 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n722)
);
XOR2X1TS U1265 ( .A(DP_OP_15J179_122_6956_n28), .B(n722), .Y(
DP_OP_15J179_122_6956_n16) );
NOR2BX1TS U1266 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n723)
);
XOR2X1TS U1267 ( .A(DP_OP_15J179_122_6956_n28), .B(n723), .Y(
DP_OP_15J179_122_6956_n17) );
AOI21X1TS U1268 ( .A0(n939), .A1(n725), .B0(n724), .Y(n748) );
NAND2X1TS U1269 ( .A(n728), .B(n727), .Y(n741) );
XNOR2X1TS U1270 ( .A(n729), .B(n741), .Y(n744) );
NOR2X1TS U1271 ( .A(n1144), .B(DMP_SFG[4]), .Y(n733) );
NOR2X1TS U1272 ( .A(n730), .B(n733), .Y(n750) );
NOR2X1TS U1273 ( .A(n1147), .B(DMP_SFG[5]), .Y(n752) );
NOR2X1TS U1274 ( .A(n1143), .B(DMP_SFG[6]), .Y(n735) );
NAND2X1TS U1275 ( .A(n1144), .B(DMP_SFG[4]), .Y(n731) );
OAI21X1TS U1276 ( .A0(n733), .A1(n732), .B0(n731), .Y(n749) );
NAND2X1TS U1277 ( .A(n1147), .B(DMP_SFG[5]), .Y(n751) );
NAND2X1TS U1278 ( .A(n1143), .B(DMP_SFG[6]), .Y(n734) );
AOI21X1TS U1279 ( .A0(n749), .A1(n737), .B0(n736), .Y(n738) );
INVX2TS U1280 ( .A(n784), .Y(n930) );
INVX2TS U1281 ( .A(n741), .Y(n742) );
XOR2X1TS U1282 ( .A(n930), .B(n742), .Y(n743) );
NAND2X1TS U1283 ( .A(n747), .B(n746), .Y(n753) );
XOR2X1TS U1284 ( .A(n748), .B(n753), .Y(n757) );
AOI21X1TS U1285 ( .A0(n957), .A1(n750), .B0(n749), .Y(n946) );
INVX2TS U1286 ( .A(n753), .Y(n754) );
XNOR2X1TS U1287 ( .A(n755), .B(n754), .Y(n756) );
INVX2TS U1288 ( .A(n758), .Y(n927) );
NAND2X1TS U1289 ( .A(n763), .B(n762), .Y(n769) );
XNOR2X1TS U1290 ( .A(n764), .B(n769), .Y(n773) );
NOR2X1TS U1291 ( .A(n1146), .B(DMP_SFG[7]), .Y(n929) );
NAND2X1TS U1292 ( .A(n1117), .B(DMP_SFG[8]), .Y(n765) );
INVX2TS U1293 ( .A(n769), .Y(n770) );
XNOR2X1TS U1294 ( .A(n771), .B(n770), .Y(n772) );
NAND2X1TS U1295 ( .A(n776), .B(n775), .Y(n785) );
XOR2X1TS U1296 ( .A(n777), .B(n785), .Y(n788) );
NOR2X1TS U1297 ( .A(n1118), .B(DMP_SFG[10]), .Y(n780) );
NAND2X1TS U1298 ( .A(n1118), .B(DMP_SFG[10]), .Y(n779) );
OAI21X1TS U1299 ( .A0(n781), .A1(n780), .B0(n779), .Y(n782) );
INVX2TS U1300 ( .A(n785), .Y(n786) );
XOR2X1TS U1301 ( .A(n808), .B(n786), .Y(n787) );
NAND2X1TS U1302 ( .A(n791), .B(n790), .Y(n797) );
XNOR2X1TS U1303 ( .A(n792), .B(n797), .Y(n801) );
INVX2TS U1304 ( .A(n797), .Y(n798) );
XNOR2X1TS U1305 ( .A(n799), .B(n798), .Y(n800) );
INVX2TS U1306 ( .A(n802), .Y(n804) );
NAND2X1TS U1307 ( .A(n804), .B(n803), .Y(n823) );
XOR2X1TS U1308 ( .A(n805), .B(n823), .Y(n826) );
NAND2X1TS U1309 ( .A(n1119), .B(DMP_SFG[11]), .Y(n806) );
OR2X1TS U1310 ( .A(n1124), .B(DMP_SFG[12]), .Y(n810) );
AOI21X4TS U1311 ( .A0(n922), .A1(n810), .B0(n809), .Y(n914) );
NAND2X1TS U1312 ( .A(n1123), .B(DMP_SFG[13]), .Y(n811) );
OR2X1TS U1313 ( .A(n1157), .B(DMP_SFG[14]), .Y(n814) );
NAND2X1TS U1314 ( .A(n1178), .B(DMP_SFG[15]), .Y(n815) );
OR2X1TS U1315 ( .A(n1179), .B(DMP_SFG[16]), .Y(n818) );
NAND2X1TS U1316 ( .A(n1192), .B(DMP_SFG[17]), .Y(n819) );
OR2X1TS U1317 ( .A(n1193), .B(DMP_SFG[18]), .Y(n822) );
INVX2TS U1318 ( .A(n823), .Y(n824) );
XOR2X1TS U1319 ( .A(n849), .B(n824), .Y(n825) );
NAND2X1TS U1320 ( .A(n828), .B(n827), .Y(n830) );
XNOR2X1TS U1321 ( .A(n829), .B(n830), .Y(n834) );
INVX2TS U1322 ( .A(n830), .Y(n831) );
XNOR2X1TS U1323 ( .A(n832), .B(n831), .Y(n833) );
INVX2TS U1324 ( .A(n835), .Y(n837) );
NAND2X1TS U1325 ( .A(n837), .B(n836), .Y(n839) );
XOR2X1TS U1326 ( .A(n838), .B(n839), .Y(n843) );
INVX2TS U1327 ( .A(n839), .Y(n840) );
XOR2X1TS U1328 ( .A(n841), .B(n840), .Y(n842) );
NAND2X1TS U1329 ( .A(n845), .B(n844), .Y(n850) );
XNOR2X1TS U1330 ( .A(n846), .B(n850), .Y(n854) );
NAND2X1TS U1331 ( .A(n1191), .B(DMP_SFG[19]), .Y(n847) );
INVX2TS U1332 ( .A(n850), .Y(n851) );
XNOR2X1TS U1333 ( .A(n861), .B(n851), .Y(n853) );
INVX2TS U1334 ( .A(n855), .Y(n857) );
NAND2X1TS U1335 ( .A(n857), .B(n856), .Y(n862) );
XOR2X1TS U1336 ( .A(n858), .B(n862), .Y(n865) );
OR2X1TS U1337 ( .A(n1203), .B(DMP_SFG[20]), .Y(n860) );
INVX2TS U1338 ( .A(n862), .Y(n863) );
XOR2X1TS U1339 ( .A(n871), .B(n863), .Y(n864) );
BUFX3TS U1340 ( .A(OP_FLAG_SFG), .Y(n947) );
NAND2X1TS U1341 ( .A(n867), .B(n866), .Y(n872) );
XNOR2X1TS U1342 ( .A(n868), .B(n872), .Y(n875) );
NAND2X1TS U1343 ( .A(n1201), .B(DMP_SFG[21]), .Y(n869) );
OAI21X2TS U1344 ( .A0(n871), .A1(n870), .B0(n869), .Y(n879) );
INVX2TS U1345 ( .A(n872), .Y(n873) );
XNOR2X1TS U1346 ( .A(n879), .B(n873), .Y(n874) );
XOR2X1TS U1347 ( .A(n876), .B(DmP_mant_SFG_SWR[25]), .Y(n882) );
OR2X1TS U1348 ( .A(n1202), .B(DMP_SFG[22]), .Y(n878) );
AOI21X1TS U1349 ( .A0(n879), .A1(n878), .B0(n877), .Y(n880) );
XOR2X1TS U1350 ( .A(n880), .B(n1230), .Y(n881) );
NAND2X1TS U1351 ( .A(n884), .B(n883), .Y(n886) );
XNOR2X1TS U1352 ( .A(n885), .B(n886), .Y(n890) );
INVX2TS U1353 ( .A(n886), .Y(n887) );
XNOR2X1TS U1354 ( .A(n888), .B(n887), .Y(n889) );
INVX2TS U1355 ( .A(n891), .Y(n893) );
NAND2X1TS U1356 ( .A(n893), .B(n892), .Y(n895) );
XOR2X1TS U1357 ( .A(n894), .B(n895), .Y(n899) );
INVX2TS U1358 ( .A(n895), .Y(n896) );
XOR2X1TS U1359 ( .A(n897), .B(n896), .Y(n898) );
NAND2X1TS U1360 ( .A(n901), .B(n900), .Y(n903) );
XNOR2X1TS U1361 ( .A(n902), .B(n903), .Y(n907) );
INVX2TS U1362 ( .A(n903), .Y(n904) );
XNOR2X1TS U1363 ( .A(n905), .B(n904), .Y(n906) );
INVX2TS U1364 ( .A(n908), .Y(n910) );
NAND2X1TS U1365 ( .A(n910), .B(n909), .Y(n912) );
XOR2X1TS U1366 ( .A(n911), .B(n912), .Y(n916) );
INVX2TS U1367 ( .A(n912), .Y(n913) );
XOR2X1TS U1368 ( .A(n914), .B(n913), .Y(n915) );
NAND2X1TS U1369 ( .A(n918), .B(n917), .Y(n920) );
XNOR2X1TS U1370 ( .A(n919), .B(n920), .Y(n924) );
INVX2TS U1371 ( .A(n920), .Y(n921) );
XNOR2X1TS U1372 ( .A(n922), .B(n921), .Y(n923) );
NAND2X1TS U1373 ( .A(n926), .B(n925), .Y(n931) );
XOR2X1TS U1374 ( .A(n927), .B(n931), .Y(n935) );
INVX2TS U1375 ( .A(n931), .Y(n932) );
XNOR2X1TS U1376 ( .A(n933), .B(n932), .Y(n934) );
AOI21X1TS U1377 ( .A0(n939), .A1(n938), .B0(n937), .Y(n943) );
NAND2X1TS U1378 ( .A(n942), .B(n941), .Y(n944) );
XOR2X1TS U1379 ( .A(n943), .B(n944), .Y(n949) );
INVX2TS U1380 ( .A(n944), .Y(n945) );
XOR2X1TS U1381 ( .A(n946), .B(n945), .Y(n948) );
NAND2X1TS U1382 ( .A(n953), .B(n952), .Y(n955) );
XNOR2X1TS U1383 ( .A(n954), .B(n955), .Y(n959) );
INVX2TS U1384 ( .A(n955), .Y(n956) );
XNOR2X1TS U1385 ( .A(n957), .B(n956), .Y(n958) );
NAND2X1TS U1386 ( .A(n962), .B(n961), .Y(n967) );
XOR2X1TS U1387 ( .A(n963), .B(n967), .Y(n971) );
INVX2TS U1388 ( .A(n964), .Y(n977) );
INVX2TS U1389 ( .A(n967), .Y(n968) );
XNOR2X1TS U1390 ( .A(n969), .B(n968), .Y(n970) );
NAND2X1TS U1391 ( .A(n974), .B(n973), .Y(n975) );
XOR2X1TS U1392 ( .A(n975), .B(n980), .Y(n979) );
INVX2TS U1393 ( .A(n975), .Y(n976) );
XOR2X1TS U1394 ( .A(n977), .B(n976), .Y(n978) );
OR2X1TS U1395 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n981) );
XOR2X1TS U1396 ( .A(n984), .B(n982), .Y(n983) );
XNOR2X1TS U1397 ( .A(N60), .B(n422), .Y(n986) );
XOR2X1TS U1398 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n987) );
AOI22X1TS U1399 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1110), .B1(n1115), .Y(n1277)
);
XNOR2X1TS U1400 ( .A(add_subt), .B(Data_Y[31]), .Y(n1231) );
XNOR2X1TS U1401 ( .A(intDX_EWSW[31]), .B(n1276), .Y(OP_FLAG_INIT) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[23]), .A1(intDY_EWSW[23]), .B0(n1139), .B1(
n1187), .Y(n994) );
AOI22X1TS U1403 ( .A0(n1132), .A1(intDY_EWSW[15]), .B0(n1173), .B1(
intDY_EWSW[13]), .Y(n988) );
OAI221XLTS U1404 ( .A0(n1132), .A1(intDY_EWSW[15]), .B0(n1173), .B1(
intDY_EWSW[13]), .C0(n988), .Y(n993) );
AOI22X1TS U1405 ( .A0(n1165), .A1(intDY_EWSW[10]), .B0(n1134), .B1(
intDY_EWSW[2]), .Y(n989) );
AOI22X1TS U1406 ( .A0(n1126), .A1(intDY_EWSW[9]), .B0(n1168), .B1(
intDY_EWSW[11]), .Y(n990) );
OAI221XLTS U1407 ( .A0(n1126), .A1(intDY_EWSW[9]), .B0(n1168), .B1(
intDY_EWSW[11]), .C0(n990), .Y(n991) );
NOR4X1TS U1408 ( .A(n994), .B(n993), .C(n992), .D(n991), .Y(n1022) );
AOI22X1TS U1409 ( .A0(n1186), .A1(intDY_EWSW[7]), .B0(n1170), .B1(
intDY_EWSW[14]), .Y(n995) );
AOI22X1TS U1410 ( .A0(n1185), .A1(intDY_EWSW[5]), .B0(n1135), .B1(
intDY_EWSW[4]), .Y(n996) );
OAI221XLTS U1411 ( .A0(n1185), .A1(intDY_EWSW[5]), .B0(n1135), .B1(
intDY_EWSW[4]), .C0(n996), .Y(n1001) );
AOI22X1TS U1412 ( .A0(n1131), .A1(intDY_EWSW[3]), .B0(n1172), .B1(
intDY_EWSW[26]), .Y(n997) );
AOI22X1TS U1413 ( .A0(n1164), .A1(intDY_EWSW[1]), .B0(n1133), .B1(
intDY_EWSW[0]), .Y(n998) );
OAI221XLTS U1414 ( .A0(n1164), .A1(intDY_EWSW[1]), .B0(n1133), .B1(
intDY_EWSW[0]), .C0(n998), .Y(n999) );
NOR4X1TS U1415 ( .A(n1002), .B(n1001), .C(n1000), .D(n999), .Y(n1021) );
AOI22X1TS U1416 ( .A0(n1103), .A1(intDY_EWSW[28]), .B0(n1137), .B1(
intDY_EWSW[6]), .Y(n1003) );
AOI22X1TS U1417 ( .A0(n1127), .A1(intDY_EWSW[18]), .B0(n1175), .B1(
intDY_EWSW[29]), .Y(n1004) );
OAI221XLTS U1418 ( .A0(n1127), .A1(intDY_EWSW[18]), .B0(n1175), .B1(
intDY_EWSW[29]), .C0(n1004), .Y(n1009) );
AOI22X1TS U1419 ( .A0(n1130), .A1(intDY_EWSW[27]), .B0(n1171), .B1(
intDY_EWSW[19]), .Y(n1005) );
AOI22X1TS U1420 ( .A0(n1167), .A1(intDY_EWSW[25]), .B0(n1136), .B1(
intDY_EWSW[24]), .Y(n1006) );
OAI221XLTS U1421 ( .A0(n1167), .A1(intDY_EWSW[25]), .B0(n1136), .B1(
intDY_EWSW[24]), .C0(n1006), .Y(n1007) );
NOR4X1TS U1422 ( .A(n1010), .B(n1009), .C(n1008), .D(n1007), .Y(n1020) );
AOI22X1TS U1423 ( .A0(n1128), .A1(intDY_EWSW[20]), .B0(n1176), .B1(
intDY_EWSW[30]), .Y(n1011) );
AOI22X1TS U1424 ( .A0(n1125), .A1(intDY_EWSW[8]), .B0(n1174), .B1(
intDY_EWSW[21]), .Y(n1012) );
OAI221XLTS U1425 ( .A0(n1125), .A1(intDY_EWSW[8]), .B0(n1174), .B1(
intDY_EWSW[21]), .C0(n1012), .Y(n1017) );
AOI22X1TS U1426 ( .A0(n1166), .A1(intDY_EWSW[17]), .B0(n1181), .B1(
intDY_EWSW[16]), .Y(n1013) );
AOI22X1TS U1427 ( .A0(n1129), .A1(intDY_EWSW[22]), .B0(n1169), .B1(
intDY_EWSW[12]), .Y(n1014) );
OAI221XLTS U1428 ( .A0(n1129), .A1(intDY_EWSW[22]), .B0(n1169), .B1(
intDY_EWSW[12]), .C0(n1014), .Y(n1015) );
NOR4X1TS U1429 ( .A(n1018), .B(n1017), .C(n1016), .D(n1015), .Y(n1019) );
NOR2BX1TS U1430 ( .AN(OP_FLAG_INIT), .B(n1088), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U1431 ( .AN(Shift_reg_FLAGS_7[3]), .B(Shift_reg_FLAGS_7[0]), .Y(
n_21_net_) );
NOR2X1TS U1432 ( .A(n1221), .B(intDX_EWSW[25]), .Y(n1082) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[25]), .A1(n1221), .B0(intDX_EWSW[24]), .B1(
n1023), .Y(n1027) );
OAI21X1TS U1434 ( .A0(intDX_EWSW[26]), .A1(n1226), .B0(n1024), .Y(n1083) );
NOR2X1TS U1435 ( .A(n1122), .B(intDX_EWSW[30]), .Y(n1030) );
NOR2X1TS U1436 ( .A(n1150), .B(intDX_EWSW[29]), .Y(n1028) );
NOR3X1TS U1437 ( .A(n419), .B(n1028), .C(intDY_EWSW[28]), .Y(n1029) );
AOI221X1TS U1438 ( .A0(intDX_EWSW[30]), .A1(n1122), .B0(intDX_EWSW[29]),
.B1(n1150), .C0(n1029), .Y(n1031) );
AOI2BB2X1TS U1439 ( .B0(n1032), .B1(n1081), .A0N(n1031), .A1N(n1030), .Y(
n1087) );
NOR2X1TS U1440 ( .A(n1219), .B(intDX_EWSW[17]), .Y(n1068) );
NOR2X1TS U1441 ( .A(n1222), .B(intDX_EWSW[11]), .Y(n1047) );
AOI21X1TS U1442 ( .A0(intDY_EWSW[10]), .A1(n1165), .B0(n1047), .Y(n1052) );
OAI211X1TS U1443 ( .A0(intDX_EWSW[8]), .A1(n1218), .B0(n1049), .C0(n1052),
.Y(n1063) );
OAI2BB1X1TS U1444 ( .A0N(n1185), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1033) );
OAI22X1TS U1445 ( .A0(intDY_EWSW[4]), .A1(n1033), .B0(n1185), .B1(
intDY_EWSW[5]), .Y(n1044) );
OAI2BB1X1TS U1446 ( .A0N(n1186), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1034) );
OAI22X1TS U1447 ( .A0(intDY_EWSW[6]), .A1(n1034), .B0(n1186), .B1(
intDY_EWSW[7]), .Y(n1043) );
OAI211X1TS U1448 ( .A0(n1224), .A1(intDX_EWSW[3]), .B0(n1037), .C0(n1036),
.Y(n1040) );
AOI222X1TS U1449 ( .A0(intDY_EWSW[4]), .A1(n1135), .B0(n1040), .B1(n1039),
.C0(intDY_EWSW[5]), .C1(n1185), .Y(n1042) );
AOI22X1TS U1450 ( .A0(intDY_EWSW[7]), .A1(n1186), .B0(intDY_EWSW[6]), .B1(
n1137), .Y(n1041) );
OAI32X1TS U1451 ( .A0(n1044), .A1(n1043), .A2(n1042), .B0(n1041), .B1(n1043),
.Y(n1062) );
OA22X1TS U1452 ( .A0(n1142), .A1(intDX_EWSW[14]), .B0(n1225), .B1(
intDX_EWSW[15]), .Y(n1059) );
OAI2BB2XLTS U1453 ( .B0(intDY_EWSW[12]), .B1(n1046), .A0N(intDX_EWSW[13]),
.A1N(n1210), .Y(n1058) );
AOI22X1TS U1454 ( .A0(intDX_EWSW[11]), .A1(n1222), .B0(intDX_EWSW[10]), .B1(
n1048), .Y(n1054) );
AOI21X1TS U1455 ( .A0(n1051), .A1(n1050), .B0(n1061), .Y(n1053) );
OAI2BB2XLTS U1456 ( .B0(intDY_EWSW[14]), .B1(n1055), .A0N(intDX_EWSW[15]),
.A1N(n1225), .Y(n1056) );
AOI211X1TS U1457 ( .A0(n1059), .A1(n1058), .B0(n1057), .C0(n1056), .Y(n1060)
);
OAI31X1TS U1458 ( .A0(n1063), .A1(n1062), .A2(n1061), .B0(n1060), .Y(n1066)
);
OA22X1TS U1459 ( .A0(n1214), .A1(intDX_EWSW[22]), .B0(n1139), .B1(
intDX_EWSW[23]), .Y(n1079) );
OAI21X1TS U1460 ( .A0(intDX_EWSW[18]), .A1(n1220), .B0(n1070), .Y(n1074) );
AOI211X1TS U1461 ( .A0(intDY_EWSW[16]), .A1(n1181), .B0(n1073), .C0(n1074),
.Y(n1065) );
OAI2BB2XLTS U1462 ( .B0(intDY_EWSW[20]), .B1(n1067), .A0N(intDX_EWSW[21]),
.A1N(n1211), .Y(n1078) );
AOI22X1TS U1463 ( .A0(intDX_EWSW[17]), .A1(n1219), .B0(intDX_EWSW[16]), .B1(
n1069), .Y(n1072) );
AOI32X1TS U1464 ( .A0(n1220), .A1(n1070), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1141), .Y(n1071) );
OAI32X1TS U1465 ( .A0(n1074), .A1(n1073), .A2(n1072), .B0(n1071), .B1(n1073),
.Y(n1077) );
OAI2BB2XLTS U1466 ( .B0(intDY_EWSW[22]), .B1(n1075), .A0N(intDX_EWSW[23]),
.A1N(n1139), .Y(n1076) );
AOI211X1TS U1467 ( .A0(n1079), .A1(n1078), .B0(n1077), .C0(n1076), .Y(n1085)
);
NAND4BBX1TS U1468 ( .AN(n1083), .BN(n1082), .C(n1081), .D(n1080), .Y(n1084)
);
AOI32X1TS U1469 ( .A0(n1087), .A1(n1086), .A2(n1085), .B0(n1084), .B1(n1087),
.Y(n1090) );
INVX2TS U1470 ( .A(n1102), .Y(n1105) );
AOI21X1TS U1471 ( .A0(n1088), .A1(n1100), .B0(intDX_EWSW[31]), .Y(n1089) );
AOI21X1TS U1472 ( .A0(n1276), .A1(n1105), .B0(n1089), .Y(SIGN_FLAG_INIT) );
AOI22X1TS U1473 ( .A0(n1102), .A1(n1227), .B0(n1133), .B1(n1091), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U1474 ( .A0(n1102), .A1(n1223), .B0(n1164), .B1(n1100), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U1475 ( .A0(n1102), .A1(n1212), .B0(n1134), .B1(n1105), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U1476 ( .A0(n1102), .A1(n1224), .B0(n1131), .B1(n1104), .Y(
DmP_INIT_EWSW[3]) );
AOI22X1TS U1477 ( .A0(n1095), .A1(n1207), .B0(n1135), .B1(n1091), .Y(
DmP_INIT_EWSW[4]) );
INVX2TS U1478 ( .A(n1102), .Y(n1091) );
AOI22X1TS U1479 ( .A0(n1102), .A1(n1199), .B0(n1185), .B1(n1100), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U1480 ( .A0(n1095), .A1(n1205), .B0(n1137), .B1(n1100), .Y(
DmP_INIT_EWSW[6]) );
BUFX3TS U1481 ( .A(n1090), .Y(n1101) );
BUFX3TS U1482 ( .A(n1101), .Y(n1092) );
AOI22X1TS U1483 ( .A0(n1092), .A1(n1198), .B0(n1186), .B1(n1105), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U1484 ( .A0(n1092), .A1(n1218), .B0(n1125), .B1(n1104), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U1485 ( .A0(n1092), .A1(n1215), .B0(n1126), .B1(n1104), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U1486 ( .A0(n1092), .A1(n1208), .B0(n1165), .B1(n1091), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U1487 ( .A0(n1092), .A1(n1222), .B0(n1168), .B1(n1105), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U1488 ( .A0(n1092), .A1(n1217), .B0(n1169), .B1(n1100), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U1489 ( .A0(n1092), .A1(n1210), .B0(n1173), .B1(n1104), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U1490 ( .A0(n1092), .A1(n1142), .B0(n1170), .B1(n1105), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U1491 ( .A0(n1092), .A1(n1225), .B0(n1132), .B1(n1104), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U1492 ( .A0(n1092), .A1(n1206), .B0(n1181), .B1(n1097), .Y(
DmP_INIT_EWSW[16]) );
BUFX3TS U1493 ( .A(n1095), .Y(n1094) );
AOI22X1TS U1494 ( .A0(n1094), .A1(n1219), .B0(n1166), .B1(n1097), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U1495 ( .A0(n1094), .A1(n1220), .B0(n1127), .B1(n1093), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U1496 ( .A0(n1094), .A1(n1141), .B0(n1171), .B1(n1093), .Y(
DmP_INIT_EWSW[19]) );
AOI22X1TS U1497 ( .A0(n1094), .A1(n1213), .B0(n1128), .B1(n1093), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U1498 ( .A0(n1094), .A1(n1211), .B0(n1174), .B1(n1097), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U1499 ( .A0(n1094), .A1(n1214), .B0(n1129), .B1(n1093), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U1500 ( .A0(n1094), .A1(n1139), .B0(n1187), .B1(n1097), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U1501 ( .A0(n1094), .A1(n1209), .B0(n1136), .B1(n1093), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U1502 ( .A0(n1094), .A1(n1221), .B0(n1167), .B1(n1097), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U1503 ( .A0(n1094), .A1(n1226), .B0(n1172), .B1(n1097), .Y(
DmP_INIT_EWSW[26]) );
BUFX3TS U1504 ( .A(n1095), .Y(n1096) );
AOI22X1TS U1505 ( .A0(n1096), .A1(n1216), .B0(n1130), .B1(n1093), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U1506 ( .A0(n1096), .A1(n1133), .B0(n1227), .B1(n1093), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U1507 ( .A0(n1096), .A1(n1164), .B0(n1223), .B1(n1093), .Y(
DMP_INIT_EWSW[1]) );
AOI22X1TS U1508 ( .A0(n1096), .A1(n1134), .B0(n1212), .B1(n1097), .Y(
DMP_INIT_EWSW[2]) );
AOI22X1TS U1509 ( .A0(n1096), .A1(n1131), .B0(n1224), .B1(n1097), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U1510 ( .A0(n1096), .A1(n1135), .B0(n1207), .B1(n1097), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U1511 ( .A0(n1096), .A1(n1185), .B0(n1199), .B1(n1093), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U1512 ( .A0(n1096), .A1(n1137), .B0(n1205), .B1(n1097), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U1513 ( .A0(n1096), .A1(n1186), .B0(n1198), .B1(n1098), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U1514 ( .A0(n1096), .A1(n1125), .B0(n1218), .B1(n1098), .Y(
DMP_INIT_EWSW[8]) );
BUFX3TS U1515 ( .A(n1095), .Y(n1099) );
AOI22X1TS U1516 ( .A0(n1099), .A1(n1126), .B0(n1215), .B1(n1098), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U1517 ( .A0(n1099), .A1(n1165), .B0(n1208), .B1(n1098), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U1518 ( .A0(n1099), .A1(n1168), .B0(n1222), .B1(n1098), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U1519 ( .A0(n1099), .A1(n1169), .B0(n1217), .B1(n1098), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U1520 ( .A0(n1099), .A1(n1173), .B0(n1210), .B1(n1098), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U1521 ( .A0(n1099), .A1(n1170), .B0(n1142), .B1(n1098), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U1522 ( .A0(n1099), .A1(n1132), .B0(n1225), .B1(n1098), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U1523 ( .A0(n1099), .A1(n1181), .B0(n1206), .B1(n1098), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U1524 ( .A0(n1099), .A1(n1166), .B0(n1219), .B1(n1093), .Y(
DMP_INIT_EWSW[17]) );
INVX2TS U1525 ( .A(n1102), .Y(n1100) );
AOI22X1TS U1526 ( .A0(n1099), .A1(n1127), .B0(n1220), .B1(n1091), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U1527 ( .A0(n1101), .A1(n1171), .B0(n1141), .B1(n1100), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U1528 ( .A0(n1101), .A1(n1128), .B0(n1213), .B1(n1100), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U1529 ( .A0(n1101), .A1(n1174), .B0(n1211), .B1(n1091), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U1530 ( .A0(n1101), .A1(n1129), .B0(n1214), .B1(n1105), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U1531 ( .A0(n1101), .A1(n1187), .B0(n1139), .B1(n1091), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U1532 ( .A0(n1101), .A1(n1136), .B0(n1209), .B1(n1100), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U1533 ( .A0(n1101), .A1(n1167), .B0(n1221), .B1(n1104), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U1534 ( .A0(n1101), .A1(n1172), .B0(n1226), .B1(n1105), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U1535 ( .A0(n1101), .A1(n1130), .B0(n1216), .B1(n1091), .Y(
DMP_INIT_EWSW[27]) );
INVX2TS U1536 ( .A(n1102), .Y(n1104) );
OAI2BB2XLTS U1537 ( .B0(n1105), .B1(n1103), .A0N(n1100), .A1N(intDY_EWSW[28]), .Y(DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U1538 ( .B0(n1091), .B1(n1175), .A0N(n1105), .A1N(intDY_EWSW[29]), .Y(DMP_INIT_EWSW[29]) );
OAI2BB2XLTS U1539 ( .B0(n1104), .B1(n1176), .A0N(n1104), .A1N(intDY_EWSW[30]), .Y(DMP_INIT_EWSW[30]) );
OAI22X1TS U1540 ( .A0(n1107), .A1(n412), .B0(n1106), .B1(n411), .Y(
Data_array_SWR[24]) );
INVX2TS U1542 ( .A(n1110), .Y(n1113) );
AOI22X1TS U1543 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1140), .B0(
beg_OP), .B1(n1115), .Y(n1112) );
OAI22X1TS U1544 ( .A0(n1113), .A1(n1112), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n1111), .Y(n389) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module runs through the 16x2 Character LCD initialization *
* commands for the DE2 Board. *
* *
******************************************************************************/
module altera_up_character_lcd_initialization (
// Inputs
clk,
reset,
initialize_LCD_display,
command_was_sent,
// Bidirectionals
// Outputs
done_initialization,
send_command,
the_command
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b1;
// Timing info for waiting for power up
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter W15 = 20; // Counter width required for 15ms
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for waiting between commands
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_5MS = 250000;
parameter W5 = 18; // Counter width required for 5ms
parameter COUNTER_INCREMENT_FOR_5MS = 18'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input initialize_LCD_display;
input command_was_sent;
// Bidirectionals
// Outputs
output done_initialization;
output send_command;
output reg [ 8: 0] the_command;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam LCD_INIT_STATE_0_WAIT_POWER_UP = 2'h0,
LCD_INIT_STATE_1_SEND_COMMAND = 2'h1,
LCD_INIT_STATE_2_CHECK_DONE = 2'h2,
LCD_INIT_STATE_3_DONE = 2'h3;
localparam AUTO_INIT_LENGTH = 4'h8;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [ 8: 0] command_rom;
// Internal Registers
reg [W15: 1] waiting_power_up;
reg [W5: 1] waiting_to_send;
reg [ 3: 0] command_counter;
// State Machine Registers
reg [ 1: 0] ns_lcd_initialize;
reg [ 1: 0] s_lcd_initialize;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_initialize <= LCD_INIT_STATE_0_WAIT_POWER_UP;
else
s_lcd_initialize <= ns_lcd_initialize;
end
always @(*)
begin
// Defaults
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
case (s_lcd_initialize)
LCD_INIT_STATE_0_WAIT_POWER_UP:
begin
if ((waiting_power_up == CLOCK_CYCLES_FOR_15MS) &
(initialize_LCD_display))
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
LCD_INIT_STATE_1_SEND_COMMAND:
begin
if (command_was_sent)
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
end
LCD_INIT_STATE_2_CHECK_DONE:
begin
if (command_counter == AUTO_INIT_LENGTH)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else if (waiting_to_send == CLOCK_CYCLES_FOR_5MS)
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
end
LCD_INIT_STATE_3_DONE:
begin
if (initialize_LCD_display)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
default:
begin
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
the_command <= 9'h000;
else
the_command <= command_rom;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
waiting_power_up <= {W15{1'b0}};
else if ((s_lcd_initialize == LCD_INIT_STATE_0_WAIT_POWER_UP) &&
(waiting_power_up != CLOCK_CYCLES_FOR_15MS))
waiting_power_up <= waiting_power_up + COUNTER_INCREMENT_FOR_15MS;
end
always @(posedge clk)
begin
if (reset)
waiting_to_send <= {W5{1'b0}};
else if (s_lcd_initialize == LCD_INIT_STATE_2_CHECK_DONE)
begin
if (waiting_to_send != CLOCK_CYCLES_FOR_5MS)
waiting_to_send <= waiting_to_send + COUNTER_INCREMENT_FOR_5MS;
end
else
waiting_to_send <= {W5{1'b0}};
end
always @(posedge clk)
begin
if (reset)
command_counter <= 4'h0;
else if (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND)
begin
if (command_was_sent)
command_counter <= command_counter + 4'h1;
end
else if (s_lcd_initialize == LCD_INIT_STATE_3_DONE)
command_counter <= 4'h5;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign send_command = (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND);
assign done_initialization = (s_lcd_initialize == LCD_INIT_STATE_3_DONE);
// Internal Assignments
always @(*)
begin
case (command_counter)
0 : command_rom <= 9'h030;
1 : command_rom <= 9'h030;
2 : command_rom <= 9'h030;
3 : command_rom <= 9'h03C;
4 : command_rom <= 9'h008;
5 : command_rom <= 9'h001;
6 : command_rom <= 9'h006;
7 : command_rom <= {7'h03, CURSOR_ON, BLINKING_ON};
default : command_rom <= 9'h000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name: red_pitaya_iq_fgen_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_hpf_block #(
parameter ALPHABITS = 25,
parameter HIGHESTALPHABIT = 18,
parameter LPFBITS = 14
)
(
input clk_i,
input reset_i ,
input signed [HIGHESTALPHABIT-1:0] alpha_i,
input signed [LPFBITS-1:0] signal_i,
output signed [LPFBITS-1:0] signal_o
);
//reg signed [ALPHABITS-1:0] alpha;
reg signed [LPFBITS+ALPHABITS-1:0] y;
reg signed [LPFBITS+ALPHABITS-1:0] delta; //we need this cumbersome imperfect implementation with a delta buffer to introduce some delay so the code works at 125 MHZ
wire signed [LPFBITS+1-1:0] diff;
reg signed [LPFBITS-1:0] delta_out;
wire signed [LPFBITS-1:0] y_out;
assign y_out = y[ALPHABITS+LPFBITS-1:ALPHABITS];
assign diff = signal_i-y_out;
always @(posedge clk_i) begin
// alpha <= $signed(alpha_i);
if (reset_i == 1'b1) begin
y <= {ALPHABITS+LPFBITS{1'b0}};
delta <= {ALPHABITS+LPFBITS{1'b0}};
delta_out <= {LPFBITS{1'b0}};
end
else begin
delta <= diff * alpha_i;
y <= y + delta;
if (diff[LPFBITS:LPFBITS-1] == 2'b01)
delta_out <= {1'b0,{LPFBITS-1{1'b1}}};
else if (diff[LPFBITS:LPFBITS-1] == 2'b10)
delta_out <= {1'b1,{LPFBITS-1{1'b0}}};
else
delta_out <= diff[LPFBITS-1:0];
end
end
assign signal_o = delta_out;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_tx.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_tx (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 32,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 5,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_cell.v
//
// *Module Description:
// Generic synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_cell (
// OUTPUTs
data_out, // Synchronized data output
// INPUTs
clk, // Receiving clock
data_in, // Asynchronous data input
rst // Receiving reset (active high)
);
// OUTPUTs
//=========
output data_out; // Synchronized data output
// INPUTs
//=========
input clk; // Receiving clock
input data_in; // Asynchronous data input
input rst; // Receiving reset (active high)
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst)
if (rst) data_sync <= 2'b00;
else data_sync <= {data_sync[0], data_in};
assign data_out = data_sync[1];
endmodule // omsp_sync_cell
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=8 LPM_WIDTHN=8 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgqfk
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [7:0] denom;
input [7:0] numer;
output [7:0] quotient;
output [7:0] remain;
wire [7:0] wire_mgl_prim1_quotient;
wire [7:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 8,
mgl_prim1.lpm_widthn = 8,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgqfk
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_1_V
`define SKY130_FD_SC_LP__SRSDFXTP_1_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog wrapper for srsdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srsdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srsdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:58:49 03/06/2017
// Design Name: Dlatch_NOR
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDlatch_NOR.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Dlatch_NOR
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDlatch_NOR;
// Inputs
reg En;
reg D;
// Outputs
wire Q;
wire not_Q;
// Instantiate the DESIGN Under Test (DUT)
Dlatch_NOR dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
// Initialize Inputs
En = 0;
D = 0;
// Wait 100 ns for global reset to finish
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
// Add stimulus here
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:45:17 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_stub.v
// Design : shd_pe_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3" *)
module shd_pe_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [7:0]din;
input wr_en;
input rd_en;
output [7:0]dout;
output full;
output empty;
endmodule
|
//
// Testbench
//
// by
// David M. Koltak 05/30/2017
//
// The MIT License (MIT)
//
// Copyright (c) 2017 David M. Koltak
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
module testbench();
reg sim_rst;
reg sim_clk;
reg sim_clk_gen;
integer cycle_count;
initial
begin
sim_rst = 1;
sim_clk_gen = 0;
$dumpfile("results.vcd");
$dumpvars(0);
cycle_count = 0;
#10 sim_rst = 0;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#5 sim_rst = 1;
#5 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;
while (1)
begin
#10 sim_clk_gen = ~sim_clk_gen;
cycle_count = (sim_clk_gen) ? cycle_count : cycle_count + 1;
end
end
always @ (sim_clk_gen)
sim_clk <= sim_clk_gen;
integer CLOCK_LIMIT;
wire [4:0] user_leds;
reg [31:0] test_progress;
always @ (posedge sim_clk or posedge sim_rst)
if (sim_rst)
begin
CLOCK_LIMIT <= 32'd0;
test_progress <= ip_test_top.testregs.test_progress;
end
else
begin
CLOCK_LIMIT <= CLOCK_LIMIT + 32'd1;
if (CLOCK_LIMIT === `MAX_CLOCKS)
begin
#20;
$display(" ****** MAX CLOCKS - ENDING SIMULATION *****");
$finish();
end
if (ip_test_top.testregs.test_progress != test_progress)
begin
test_progress <= ip_test_top.testregs.test_progress;
$display(" ****** TEST PROGRESS %X *****",
ip_test_top.testregs.test_progress);
end
if (ip_test_top.testregs.test_fail != 32'd0)
begin
#20;
$display(" ****** TEST FAILED %08X *****" ,
ip_test_top.testregs.test_fail);
$finish();
end
if (ip_test_top.testregs.test_pass != 32'd0)
begin
#20;
$display(" ****** TEST PASSED %08X *****" ,
ip_test_top.testregs.test_pass);
$finish();
end
end
reg sim_clk_slow;
reg sim_clk_slow_gen;
initial
begin
sim_clk_slow_gen = 0;
while (1)
begin
#33 sim_clk_slow_gen = ~sim_clk_slow_gen;
end
end
always @ (sim_clk_slow_gen)
sim_clk_slow <= sim_clk_slow_gen;
wire uart_tx;
wire uart_rx;
ip_test_top ip_test_top
(
.clk_50(sim_clk),
.clk_slow(sim_clk_slow),
.fpga_reset_n(!sim_rst),
.qspi_clk(),
.qspi_io(),
.qspi_csn(),
.uart_0_rx(uart_rx),
.uart_0_tx(uart_tx),
.uart_1_rx(uart_tx),
.uart_1_tx(uart_rx),
.user_led(user_leds),
.user_pb(4'b1111)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:40:58 04/14/2014
// Design Name:
// Module Name: TemperatureSensor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SystemMonitor(
input wire clk,
input wire [6:0] DADDR_IN,
output wire DRDY_OUT,
output wire [15:0] DO_OUT
);
//wire [6:0] DADDR_IN;
wire DEN_IN, DWE_IN, VP_IN, VN_IN;
wire [15:0] DI_IN;
//assign DADDR_IN = 7'h00;
assign DEN_IN = 1'b1;
assign DWE_IN = 1'b0;
assign VP_IN = 1'b0;
assign VN_IN = 1'b0;
assign DI_IN = 16'h0000;
TemperatureMonitor SysMon1(
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(clk),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
|
`timescale 1ns/1ps
module axi_lite_slave #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
)(
input clk ,
input rst_n ,
//---- AXI Lite bus----
// AXI write address channel
output reg s_axi_awready ,
input [ADDR_WIDTH - 1:0] s_axi_awaddr ,
input [02:0] s_axi_awprot ,
input s_axi_awvalid ,
// axi write data channel
output reg s_axi_wready ,
input [DATA_WIDTH - 1:0] s_axi_wdata ,
input [(DATA_WIDTH/8) - 1:0] s_axi_wstrb ,
input s_axi_wvalid ,
// AXI response channel
output [01:0] s_axi_bresp ,
output reg s_axi_bvalid ,
input s_axi_bready ,
// AXI read address channel
output reg s_axi_arready ,
input s_axi_arvalid ,
input [ADDR_WIDTH - 1:0] s_axi_araddr ,
input [02:0] s_axi_arprot ,
// AXI read data channel
output reg [DATA_WIDTH - 1:0] s_axi_rdata ,
output [01:0] s_axi_rresp ,
input s_axi_rready ,
output reg s_axi_rvalid ,
//---- local control ----
output pattern_memcpy_enable ,
output [63:0] pattern_source_address,
output [63:0] pattern_target_address,
output [63:0] pattern_total_number ,
//---- local status ----
input pattern_memcpy_done ,
//---- snap status ----
input i_app_ready ,
input [31:0] i_action_type ,
input [31:0] i_action_version ,
output [31:0] o_snap_context
);
//---- declarations ----
wire[31:0] write_data_snap_status;
wire[31:0] write_data_snap_int_enable;
wire[31:0] write_data_snap_context;
wire[31:0] write_data_control;
wire[63:0] write_data_pattern_source_address;
wire[63:0] write_data_pattern_target_address;
wire[31:0] write_data_pattern_total_number;
reg [31:0] write_address;
wire[31:0] wr_mask;
wire[31:0] REG_snap_status_rd;
wire idle;
reg idle_q;
reg app_done_q;
reg app_start_q;
reg reg_snap_status_bit0;
///////////////////////////////////////////////////
//***********************************************//
//> REGISTERS <//
//***********************************************//
// //
/**/ reg [31:0] REG_snap_status ; /**/
/**/ reg [31:0] REG_snap_int_enable ; /**/
/**/ reg [31:0] REG_snap_context ; /**/
/**/ reg [63:0] REG_control ; /**/
/**/ reg [63:0] REG_pattern_source_address; /**/
/**/ reg [63:0] REG_pattern_target_address; /**/
/**/ reg [63:0] REG_pattern_total_number ; /**/
/**/ reg [63:0] REG_status ; /**/
// //
//-----------------------------------------------//
// //
///////////////////////////////////////////////////
//---- parameters ----
// Register addresses arrangement
parameter ADDR_SNAP_STATUS = 32'h00,
ADDR_SNAP_INT_ENABLE = 32'h04,
ADDR_SNAP_ACTION_TYPE = 32'h10,
ADDR_SNAP_ACTION_VERSION = 32'h14,
ADDR_SNAP_CONTEXT = 32'h20,
ADDR_STATUS_L = 32'h30,
ADDR_STATUS_H = 32'h34,
ADDR_CONTROL = 32'h38,
ADDR_PATTERN_SOURCE_ADDRESS_L = 32'h48,
ADDR_PATTERN_SOURCE_ADDRESS_H = 32'h4C,
ADDR_PATTERN_TARGET_ADDRESS_L = 32'h50,
ADDR_PATTERN_TARGET_ADDRESS_H = 32'h54,
ADDR_PATTERN_TOTAL_NUMBER = 32'h68;
//---- local controlling signals assignments ----
assign pattern_memcpy_enable = REG_control[0];
assign pattern_source_address = REG_pattern_source_address;
assign pattern_target_address = REG_pattern_target_address;
assign pattern_total_number = REG_pattern_total_number;
assign o_snap_context = REG_snap_context;
//---- read-only registers assigned by local signals ----
always@(posedge clk)
begin
REG_status <= {
63'd0,
pattern_memcpy_done
};
end
/***********************************************************************
* writing registers *
***********************************************************************/
//---- write address capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
write_address <= 32'd0;
else if(s_axi_awvalid & s_axi_awready)
write_address <= s_axi_awaddr;
//---- write address ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_awready <= 1'b0;
else if(s_axi_awvalid)
s_axi_awready <= 1'b1;
else if(s_axi_wvalid & s_axi_wready)
s_axi_awready <= 1'b0;
//---- write data ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_wready <= 1'b0;
else if(s_axi_awvalid & s_axi_awready)
s_axi_wready <= 1'b1;
else if(s_axi_wvalid)
s_axi_wready <= 1'b0;
//---- handle write data strobe ----
assign wr_mask = {{8{s_axi_wstrb[3]}},{8{s_axi_wstrb[2]}},{8{s_axi_wstrb[1]}},{8{s_axi_wstrb[0]}}};
assign write_data_snap_status = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_status)};
assign write_data_snap_int_enable = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_int_enable)};
assign write_data_snap_context = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_context)};
assign write_data_control = {(s_axi_wdata&wr_mask)|(~wr_mask®_control)};
assign write_data_pattern_source_address = {(s_axi_wdata&wr_mask)|(~wr_mask®_pattern_source_address)};
assign write_data_pattern_target_address = {(s_axi_wdata&wr_mask)|(~wr_mask®_pattern_target_address)};
assign write_data_pattern_total_number = {(s_axi_wdata&wr_mask)|(~wr_mask®_pattern_total_number)};
//---- write registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
REG_snap_status <= 32'd0;
REG_snap_int_enable <= 32'd0;
REG_snap_context <= 32'd0;
REG_control <= 64'd0;
REG_pattern_source_address <= 64'd0;
REG_pattern_target_address <= 64'd0;
REG_pattern_total_number <= 64'd0;
end
else if(s_axi_wvalid & s_axi_wready)
case(write_address)
ADDR_SNAP_STATUS : REG_snap_status <= write_data_snap_status;
ADDR_SNAP_INT_ENABLE : REG_snap_int_enable <= write_data_snap_int_enable;
ADDR_SNAP_CONTEXT : REG_snap_context <= write_data_snap_context;
ADDR_CONTROL : REG_control <=
{32'd0,write_data_control};
ADDR_PATTERN_SOURCE_ADDRESS_H : REG_pattern_source_address <=
{write_data_pattern_source_address,REG_pattern_source_address[31:00]};
ADDR_PATTERN_SOURCE_ADDRESS_L : REG_pattern_source_address <=
{REG_pattern_source_address[63:32],write_data_pattern_source_address};
ADDR_PATTERN_TARGET_ADDRESS_H : REG_pattern_target_address <=
{write_data_pattern_target_address,REG_pattern_target_address[31:00]};
ADDR_PATTERN_TARGET_ADDRESS_L : REG_pattern_target_address <=
{REG_pattern_target_address[63:32],write_data_pattern_target_address};
ADDR_PATTERN_TOTAL_NUMBER : REG_pattern_total_number <=
{32'd0,write_data_pattern_total_number};
default :;
endcase
// All bit[2:0] from control (0x38) is 0 means idle
assign idle = ~(|(REG_control[2:0]));
// Prepare status for SNAP status register
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
idle_q <= 0;
app_start_q <= 0;
reg_snap_status_bit0 <= 0;
app_done_q <= 0;
end else begin
idle_q <= idle;
reg_snap_status_bit0 <= REG_snap_status[0];
// Action Status bit 0 means action done
if ((REG_status[0] == 1)) begin
app_done_q <= 1;
end else begin
app_done_q <= 0;
end
// SNAP status bit 0 changed from 0 to 1 means app started
if ((reg_snap_status_bit0 == 0) && (REG_snap_status[0] == 1)) begin
app_start_q <= 1;
end
// Idle changed from 0 to 1 means app stopped work
if ((idle_q == 1) && (idle == 0)) begin
app_start_q <= 0;
end
end
end
/***********************************************************************
* reading registers *
***********************************************************************/
assign REG_snap_status_rd = {REG_snap_status[31:4], i_app_ready, idle_q, app_done_q, app_start_q};
//---- read registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rdata <= 32'd0;
else if(s_axi_arvalid & s_axi_arready)
case(s_axi_araddr)
ADDR_SNAP_STATUS : s_axi_rdata <= REG_snap_status_rd[31:0];
ADDR_SNAP_INT_ENABLE : s_axi_rdata <= REG_snap_int_enable[31:0];
ADDR_SNAP_ACTION_TYPE : s_axi_rdata <= i_action_type;
ADDR_SNAP_ACTION_VERSION : s_axi_rdata <= i_action_version;
ADDR_SNAP_CONTEXT : s_axi_rdata <= REG_snap_context[31:0];
ADDR_STATUS_L : s_axi_rdata <= REG_status[31:0];
ADDR_STATUS_H : s_axi_rdata <= REG_status[63:32];
default : s_axi_rdata <= 32'h5a5aa5a5;
endcase
//---- address ready: deasserts once arvalid is seen; reasserts when current read is done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_arready <= 1'b1;
else if(s_axi_arvalid)
s_axi_arready <= 1'b0;
else if(s_axi_rvalid & s_axi_rready)
s_axi_arready <= 1'b1;
//---- data ready: deasserts once rvalid is seen; reasserts when new address has come ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rvalid <= 1'b0;
else if (s_axi_arvalid & s_axi_arready)
s_axi_rvalid <= 1'b1;
else if (s_axi_rready)
s_axi_rvalid <= 1'b0;
/***********************************************************************
* status reporting *
***********************************************************************/
//---- axi write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_bvalid <= 1'b0;
else if(s_axi_wvalid & s_axi_wready)
s_axi_bvalid <= 1'b1;
else if(s_axi_bready)
s_axi_bvalid <= 1'b0;
assign s_axi_bresp = 2'd0;
//---- axi read response ----
assign s_axi_rresp = 2'd0;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file wr_fifo32to256.v when simulating
// the core, wr_fifo32to256. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module wr_fifo32to256(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
output [9 : 0] rd_data_count;
output [12 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(13),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("8kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(8191),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(8190),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(13),
.C_WR_DEPTH(8192),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(13),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// amm_master_qsys_with_pcie_tb.v
// Generated using ACDS version 13.0sp1 232 at 2015.03.30.17:41:32
`timescale 1 ps / 1 ps
module amm_master_qsys_with_pcie_tb (
);
wire amm_master_qsys_with_pcie_inst_clk_bfm_clk_clk; // amm_master_qsys_with_pcie_inst_clk_bfm:clk -> [amm_master_qsys_with_pcie_inst:clk_clk, amm_master_qsys_with_pcie_inst_reset_bfm:clk]
wire amm_master_qsys_with_pcie_inst_reset_bfm_reset_reset; // amm_master_qsys_with_pcie_inst_reset_bfm:reset -> amm_master_qsys_with_pcie_inst:reset_reset_n
wire pcie_ip_pcie_bfm_0_refclk_export; // pcie_ip_pcie_bfm_0:refclk -> amm_master_qsys_with_pcie_inst:pcie_ip_refclk_export
wire [39:0] pcie_ip_pcie_bfm_0_test_in_test_in; // pcie_ip_pcie_bfm_0:test_in -> amm_master_qsys_with_pcie_inst:pcie_ip_test_in_test_in
wire pcie_ip_pcie_bfm_0_pcie_rstn_export; // pcie_ip_pcie_bfm_0:pcie_rstn -> amm_master_qsys_with_pcie_inst:pcie_ip_pcie_rstn_export
wire amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk250_export; // amm_master_qsys_with_pcie_inst:pcie_ip_clocks_sim_clk250_export -> pcie_ip_pcie_bfm_0:clk250_out
wire amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk125_export; // amm_master_qsys_with_pcie_inst:pcie_ip_clocks_sim_clk125_export -> pcie_ip_pcie_bfm_0:clk125_out
wire amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk500_export; // amm_master_qsys_with_pcie_inst:pcie_ip_clocks_sim_clk500_export -> pcie_ip_pcie_bfm_0:clk500_out
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdatak0_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_txdatak0_ext -> pcie_ip_pcie_bfm_0:txdatak0_ext
wire [7:0] amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdata0_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_txdata0_ext -> pcie_ip_pcie_bfm_0:txdata0_ext
wire pcie_ip_pcie_bfm_0_pipe_ext_rxelecidle0_ext; // pcie_ip_pcie_bfm_0:rxelecidle0_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxelecidle0_ext
wire pcie_ip_pcie_bfm_0_pipe_ext_pipe_mode; // pcie_ip_pcie_bfm_0:pipe_mode -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_pipe_mode
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txelecidle0_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_txelecidle0_ext -> pcie_ip_pcie_bfm_0:txelecidle0_ext
wire [7:0] pcie_ip_pcie_bfm_0_pipe_ext_rxdata0_ext; // pcie_ip_pcie_bfm_0:rxdata0_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxdata0_ext
wire pcie_ip_pcie_bfm_0_pipe_ext_rxvalid0_ext; // pcie_ip_pcie_bfm_0:rxvalid0_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxvalid0_ext
wire pcie_ip_pcie_bfm_0_pipe_ext_rxdatak0_ext; // pcie_ip_pcie_bfm_0:rxdatak0_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxdatak0_ext
wire pcie_ip_pcie_bfm_0_pipe_ext_phystatus_ext; // pcie_ip_pcie_bfm_0:phystatus_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_phystatus_ext
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rxpolarity0_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxpolarity0_ext -> pcie_ip_pcie_bfm_0:rxpolarity0_ext
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txcompl0_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_txcompl0_ext -> pcie_ip_pcie_bfm_0:txcompl0_ext
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rate_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rate_ext -> pcie_ip_pcie_bfm_0:rate_ext
wire amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdetectrx_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_txdetectrx_ext -> pcie_ip_pcie_bfm_0:txdetectrx_ext
wire [1:0] amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_powerdown_ext; // amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_powerdown_ext -> pcie_ip_pcie_bfm_0:powerdown_ext
wire [2:0] pcie_ip_pcie_bfm_0_pipe_ext_rxstatus0_ext; // pcie_ip_pcie_bfm_0:rxstatus0_ext -> amm_master_qsys_with_pcie_inst:pcie_ip_pipe_ext_rxstatus0_ext
wire pcie_ip_pcie_bfm_0_rx_in_rx_datain_0; // pcie_ip_pcie_bfm_0:rx_in0 -> amm_master_qsys_with_pcie_inst:pcie_ip_rx_in_rx_datain_0
wire amm_master_qsys_with_pcie_inst_pcie_ip_tx_out_tx_dataout_0; // amm_master_qsys_with_pcie_inst:pcie_ip_tx_out_tx_dataout_0 -> pcie_ip_pcie_bfm_0:tx_out0
wire pcie_ip_pcie_bfm_0_powerdown_pll_powerdown; // pcie_ip_pcie_bfm_0:pll_powerdown -> amm_master_qsys_with_pcie_inst:pcie_ip_powerdown_pll_powerdown
wire pcie_ip_pcie_bfm_0_powerdown_gxb_powerdown; // pcie_ip_pcie_bfm_0:gxb_powerdown -> amm_master_qsys_with_pcie_inst:pcie_ip_powerdown_gxb_powerdown
amm_master_qsys_with_pcie amm_master_qsys_with_pcie_inst (
.clk_clk (amm_master_qsys_with_pcie_inst_clk_bfm_clk_clk), // clk.clk
.reset_reset_n (amm_master_qsys_with_pcie_inst_reset_bfm_reset_reset), // reset.reset_n
.pcie_ip_reconfig_togxb_data (), // pcie_ip_reconfig_togxb.data
.pcie_ip_refclk_export (pcie_ip_pcie_bfm_0_refclk_export), // pcie_ip_refclk.export
.pcie_ip_test_in_test_in (pcie_ip_pcie_bfm_0_test_in_test_in), // pcie_ip_test_in.test_in
.pcie_ip_pcie_rstn_export (pcie_ip_pcie_bfm_0_pcie_rstn_export), // pcie_ip_pcie_rstn.export
.pcie_ip_clocks_sim_clk250_export (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk250_export), // pcie_ip_clocks_sim.clk250_export
.pcie_ip_clocks_sim_clk500_export (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk500_export), // .clk500_export
.pcie_ip_clocks_sim_clk125_export (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk125_export), // .clk125_export
.pcie_ip_reconfig_busy_busy_altgxb_reconfig (), // pcie_ip_reconfig_busy.busy_altgxb_reconfig
.pcie_ip_pipe_ext_pipe_mode (pcie_ip_pcie_bfm_0_pipe_ext_pipe_mode), // pcie_ip_pipe_ext.pipe_mode
.pcie_ip_pipe_ext_phystatus_ext (pcie_ip_pcie_bfm_0_pipe_ext_phystatus_ext), // .phystatus_ext
.pcie_ip_pipe_ext_rate_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rate_ext), // .rate_ext
.pcie_ip_pipe_ext_powerdown_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_powerdown_ext), // .powerdown_ext
.pcie_ip_pipe_ext_txdetectrx_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdetectrx_ext), // .txdetectrx_ext
.pcie_ip_pipe_ext_rxelecidle0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxelecidle0_ext), // .rxelecidle0_ext
.pcie_ip_pipe_ext_rxdata0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxdata0_ext), // .rxdata0_ext
.pcie_ip_pipe_ext_rxstatus0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxstatus0_ext), // .rxstatus0_ext
.pcie_ip_pipe_ext_rxvalid0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxvalid0_ext), // .rxvalid0_ext
.pcie_ip_pipe_ext_rxdatak0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxdatak0_ext), // .rxdatak0_ext
.pcie_ip_pipe_ext_txdata0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdata0_ext), // .txdata0_ext
.pcie_ip_pipe_ext_txdatak0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdatak0_ext), // .txdatak0_ext
.pcie_ip_pipe_ext_rxpolarity0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rxpolarity0_ext), // .rxpolarity0_ext
.pcie_ip_pipe_ext_txcompl0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txcompl0_ext), // .txcompl0_ext
.pcie_ip_pipe_ext_txelecidle0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txelecidle0_ext), // .txelecidle0_ext
.pcie_ip_rx_in_rx_datain_0 (pcie_ip_pcie_bfm_0_rx_in_rx_datain_0), // pcie_ip_rx_in.rx_datain_0
.pcie_ip_tx_out_tx_dataout_0 (amm_master_qsys_with_pcie_inst_pcie_ip_tx_out_tx_dataout_0), // pcie_ip_tx_out.tx_dataout_0
.pcie_ip_reconfig_fromgxb_0_data (), // pcie_ip_reconfig_fromgxb_0.data
.sdram_addr (), // sdram.addr
.sdram_ba (), // .ba
.sdram_cas_n (), // .cas_n
.sdram_cke (), // .cke
.sdram_cs_n (), // .cs_n
.sdram_dq (), // .dq
.sdram_dqm (), // .dqm
.sdram_ras_n (), // .ras_n
.sdram_we_n (), // .we_n
.altpll_sdram_clk (), // altpll_sdram.clk
.pcie_ip_powerdown_pll_powerdown (pcie_ip_pcie_bfm_0_powerdown_pll_powerdown), // pcie_ip_powerdown.pll_powerdown
.pcie_ip_powerdown_gxb_powerdown (pcie_ip_pcie_bfm_0_powerdown_gxb_powerdown), // .gxb_powerdown
.custom_module_conduit_rdwr_cntl (), // custom_module_conduit.rdwr_cntl
.custom_module_conduit_n_action (), // .n_action
.custom_module_conduit_add_data_sel (), // .add_data_sel
.custom_module_conduit_rdwr_address () // .rdwr_address
);
altera_avalon_clock_source #(
.CLOCK_RATE (50000000),
.CLOCK_UNIT (1)
) amm_master_qsys_with_pcie_inst_clk_bfm (
.clk (amm_master_qsys_with_pcie_inst_clk_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50)
) amm_master_qsys_with_pcie_inst_reset_bfm (
.reset (amm_master_qsys_with_pcie_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (amm_master_qsys_with_pcie_inst_clk_bfm_clk_clk) // clk.clk
);
altera_pcie_bfm pcie_ip_pcie_bfm_0 (
.test_out (), // test_out.test_out
.pcie_rstn (pcie_ip_pcie_bfm_0_pcie_rstn_export), // pcie_rstn.export
.refclk (pcie_ip_pcie_bfm_0_refclk_export), // refclk.export
.test_in (pcie_ip_pcie_bfm_0_test_in_test_in), // test_in.test_in
.rx_in0 (pcie_ip_pcie_bfm_0_rx_in_rx_datain_0), // rx_in.rx_datain_0
.tx_out0 (amm_master_qsys_with_pcie_inst_pcie_ip_tx_out_tx_dataout_0), // tx_out.tx_dataout_0
.txdetectrx_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdetectrx_ext), // pipe_ext.txdetectrx_ext
.rate_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rate_ext), // .rate_ext
.powerdown_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_powerdown_ext), // .powerdown_ext
.pipe_mode (pcie_ip_pcie_bfm_0_pipe_ext_pipe_mode), // .pipe_mode
.rxpolarity0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_rxpolarity0_ext), // .rxpolarity0_ext
.txcompl0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txcompl0_ext), // .txcompl0_ext
.txdata0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdata0_ext), // .txdata0_ext
.txdatak0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txdatak0_ext), // .txdatak0_ext
.txelecidle0_ext (amm_master_qsys_with_pcie_inst_pcie_ip_pipe_ext_txelecidle0_ext), // .txelecidle0_ext
.rxdata0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxdata0_ext), // .rxdata0_ext
.rxdatak0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxdatak0_ext), // .rxdatak0_ext
.rxelecidle0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxelecidle0_ext), // .rxelecidle0_ext
.rxstatus0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxstatus0_ext), // .rxstatus0_ext
.rxvalid0_ext (pcie_ip_pcie_bfm_0_pipe_ext_rxvalid0_ext), // .rxvalid0_ext
.phystatus_ext (pcie_ip_pcie_bfm_0_pipe_ext_phystatus_ext), // .phystatus_ext
.gxb_powerdown (pcie_ip_pcie_bfm_0_powerdown_gxb_powerdown), // powerdown.gxb_powerdown
.pll_powerdown (pcie_ip_pcie_bfm_0_powerdown_pll_powerdown), // .pll_powerdown
.clk500_out (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk500_export), // clocks_sim.clk500_export
.clk250_out (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk250_export), // .clk250_export
.clk125_out (amm_master_qsys_with_pcie_inst_pcie_ip_clocks_sim_clk125_export), // .clk125_export
.rxpolarity1_ext (1'b0), // (terminated)
.txcompl1_ext (1'b0), // (terminated)
.txdata1_ext (8'b00000000), // (terminated)
.txdatak1_ext (1'b0), // (terminated)
.txelecidle1_ext (1'b1), // (terminated)
.tx_out1 (1'b0), // (terminated)
.rx_in1 (), // (terminated)
.rxdata1_ext (), // (terminated)
.rxdatak1_ext (), // (terminated)
.rxelecidle1_ext (), // (terminated)
.rxstatus1_ext (), // (terminated)
.rxvalid1_ext (), // (terminated)
.rxpolarity2_ext (1'b0), // (terminated)
.txcompl2_ext (1'b0), // (terminated)
.txdata2_ext (8'b00000000), // (terminated)
.txdatak2_ext (1'b0), // (terminated)
.txelecidle2_ext (1'b1), // (terminated)
.tx_out2 (1'b0), // (terminated)
.rx_in2 (), // (terminated)
.rxdata2_ext (), // (terminated)
.rxdatak2_ext (), // (terminated)
.rxelecidle2_ext (), // (terminated)
.rxstatus2_ext (), // (terminated)
.rxvalid2_ext (), // (terminated)
.rxpolarity3_ext (1'b0), // (terminated)
.txcompl3_ext (1'b0), // (terminated)
.txdata3_ext (8'b00000000), // (terminated)
.txdatak3_ext (1'b0), // (terminated)
.txelecidle3_ext (1'b1), // (terminated)
.tx_out3 (1'b0), // (terminated)
.rx_in3 (), // (terminated)
.rxdata3_ext (), // (terminated)
.rxdatak3_ext (), // (terminated)
.rxelecidle3_ext (), // (terminated)
.rxstatus3_ext (), // (terminated)
.rxvalid3_ext (), // (terminated)
.rxpolarity4_ext (1'b0), // (terminated)
.txcompl4_ext (1'b0), // (terminated)
.txdata4_ext (8'b00000000), // (terminated)
.txdatak4_ext (1'b0), // (terminated)
.txelecidle4_ext (1'b1), // (terminated)
.tx_out4 (1'b0), // (terminated)
.rx_in4 (), // (terminated)
.rxdata4_ext (), // (terminated)
.rxdatak4_ext (), // (terminated)
.rxelecidle4_ext (), // (terminated)
.rxstatus4_ext (), // (terminated)
.rxvalid4_ext (), // (terminated)
.rxpolarity5_ext (1'b0), // (terminated)
.txcompl5_ext (1'b0), // (terminated)
.txdata5_ext (8'b00000000), // (terminated)
.txdatak5_ext (1'b0), // (terminated)
.txelecidle5_ext (1'b1), // (terminated)
.tx_out5 (1'b0), // (terminated)
.rx_in5 (), // (terminated)
.rxdata5_ext (), // (terminated)
.rxdatak5_ext (), // (terminated)
.rxelecidle5_ext (), // (terminated)
.rxstatus5_ext (), // (terminated)
.rxvalid5_ext (), // (terminated)
.rxpolarity6_ext (1'b0), // (terminated)
.txcompl6_ext (1'b0), // (terminated)
.txdata6_ext (8'b00000000), // (terminated)
.txdatak6_ext (1'b0), // (terminated)
.txelecidle6_ext (1'b1), // (terminated)
.tx_out6 (1'b0), // (terminated)
.rx_in6 (), // (terminated)
.rxdata6_ext (), // (terminated)
.rxdatak6_ext (), // (terminated)
.rxelecidle6_ext (), // (terminated)
.rxstatus6_ext (), // (terminated)
.rxvalid6_ext (), // (terminated)
.rxpolarity7_ext (1'b0), // (terminated)
.txcompl7_ext (1'b0), // (terminated)
.txdata7_ext (8'b00000000), // (terminated)
.txdatak7_ext (1'b0), // (terminated)
.txelecidle7_ext (1'b1), // (terminated)
.tx_out7 (1'b0), // (terminated)
.rx_in7 (), // (terminated)
.rxdata7_ext (), // (terminated)
.rxdatak7_ext (), // (terminated)
.rxelecidle7_ext (), // (terminated)
.rxstatus7_ext (), // (terminated)
.rxvalid7_ext () // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_4_V
`define SKY130_FD_SC_LP__MAJ3_4_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_4_V
|
/**
* $Id: red_pitaya_dfilt1.v 964 2014-01-24 12:58:17Z matej.oblak $
*
* @brief Red Pitaya equalization filter.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Filter to equalize input analog chain.
*
*/
module red_pitaya_dfilt1
(
// ADC
input adc_clk_i , //!< ADC clock
input adc_rstn_i , //!< ADC reset - active low
input [ 14-1: 0] adc_dat_i , //!< ADC data
output [ 14-1: 0] adc_dat_o , //!< ADC data
// configuration
input [ 18-1: 0] cfg_aa_i , //!< config AA coefficient
input [ 25-1: 0] cfg_bb_i , //!< config BB coefficient
input [ 25-1: 0] cfg_kk_i , //!< config KK coefficient
input [ 25-1: 0] cfg_pp_i //!< config PP coefficient
);
//---------------------------------------------------------------------------------
// register configuration - timing improvements
reg [ 18-1: 0] cfg_aa_r ;
reg [ 25-1: 0] cfg_bb_r ;
reg [ 25-1: 0] cfg_kk_r ;
reg [ 25-1: 0] cfg_pp_r ;
always @(posedge adc_clk_i) begin
cfg_aa_r <= cfg_aa_i ;
cfg_bb_r <= cfg_bb_i ;
cfg_kk_r <= cfg_kk_i ;
cfg_pp_r <= cfg_pp_i ;
end
//---------------------------------------------------------------------------------
// FIR
wire [ 39-1: 0] bb_mult ;
wire [ 33-1: 0] r2_sum ;
reg [ 33-1: 0] r1_reg ;
reg [ 23-1: 0] r2_reg ;
reg [ 32-1: 0] r01_reg ;
reg [ 28-1: 0] r02_reg ;
assign bb_mult = $signed(adc_dat_i) * $signed(cfg_bb_r);
assign r2_sum = $signed(r01_reg) + $signed(r1_reg);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r1_reg <= 33'h0 ;
r2_reg <= 23'h0 ;
r01_reg <= 32'h0 ;
r02_reg <= 28'h0 ;
end
else begin
r1_reg <= $signed(r02_reg) - $signed(r01_reg) ;
r2_reg <= r2_sum[33-1:10];
r01_reg <= {adc_dat_i,18'h0};
r02_reg <= bb_mult[39-2:10];
end
end
//---------------------------------------------------------------------------------
// IIR 1
wire [ 41-1: 0] aa_mult ;
wire [ 49-1: 0] r3_sum ; //24 + 25
(* use_dsp48="yes" *)
reg [ 23-1: 0] r3_reg ;
assign aa_mult = $signed(r3_reg) * $signed(cfg_aa_r);
assign r3_sum = $signed({r2_reg,25'h0}) + $signed({r3_reg,25'h0}) - $signed(aa_mult[41-1:0]);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r3_reg <= 23'h0 ;
end
else begin
r3_reg <= r3_sum[49-2:25] ;
end
end
//---------------------------------------------------------------------------------
// IIR 2
wire [ 40-1: 0] pp_mult ;
wire [ 16-1: 0] r4_sum ;
reg [ 15-1: 0] r4_reg ;
reg [ 15-1: 0] r3_shr ;
assign pp_mult = $signed(r4_reg) * $signed(cfg_pp_r);
assign r4_sum = $signed(r3_shr) + $signed(pp_mult[40-2:16]);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r3_shr <= 15'h0 ;
r4_reg <= 15'h0 ;
end
else begin
r3_shr <= r3_reg[23-1:8] ;
r4_reg <= r4_sum[16-2:0] ;
end
end
//---------------------------------------------------------------------------------
// Scaling
wire [ 40-1: 0] kk_mult ;
reg [ 15-1: 0] r4_reg_r ;
reg [ 15-1: 0] r4_reg_rr ;
reg [ 14-1: 0] r5_reg ;
assign kk_mult = $signed(r4_reg_rr) * $signed(cfg_kk_r);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r4_reg_r <= 15'h0 ;
r4_reg_rr <= 15'h0 ;
r5_reg <= 14'h0 ;
end
else begin
r4_reg_r <= r4_reg ;
r4_reg_rr <= r4_reg_r ;
if ($signed(kk_mult[40-2:24]) > $signed(14'h1FFF))
r5_reg <= 14'h1FFF ;
else if ($signed(kk_mult[40-2:24]) < $signed(14'h2000))
r5_reg <= 14'h2000 ;
else
r5_reg <= kk_mult[24+14-1:24];
end
end
assign adc_dat_o = r5_reg ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_TB_V
`define SKY130_FD_SC_HD__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_4_V
`define SKY130_FD_SC_HS__O31A_4_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31a_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 09 02:07:22 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______126.455____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_static_cmdgen.v
// Version : v1.0
// Description: Rd/wr command generator
// various features/status of the core.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_static_cmdgen
# (
parameter C_ATG_STATIC_ADDRESS = 32'h12A0_0000,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_MIF_ADDR_BITS = 4 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_STATIC_LENGTH = 3,
parameter C_ATG_SYSTEM_INIT = 0,
parameter C_ATG_SYSTEM_TEST = 0
) (
input Clk ,
input rst_l ,
input static_ctl_en ,
input [7:0] static_len ,
input [9:0] rom_addr_ptr_ff,
input [31:0] rom_addr ,
input [31:0] rom_data ,
output [127:0] cmd_out_mw ,
output [C_M_AXI_DATA_WIDTH-1:0] cmd_data ,
output [127:0] cmd_out_mr
);
wire [2:0] size;
generate if(C_M_AXI_DATA_WIDTH == 32 ) begin : M_SISE32
assign size = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64 ) begin : M_SISE64
assign size = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128 ) begin : M_SISE128
assign size = 3'b100;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256 ) begin : M_SISE256
assign size = 3'b101;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512 ) begin : M_SISE512
assign size = 3'b110;
end
endgenerate
wire [5:0] id = 6'h0;
wire [1:0] burst = 2'b01;
reg [7:0] len = 8'h0;
always @(posedge Clk) begin
len[7:0] <= (rst_l) ? static_len[7:0] : C_ATG_STATIC_LENGTH;
end
//
//Static-mode
//
generate if(C_ATG_SYSTEM_INIT == 0 &&
C_ATG_SYSTEM_TEST == 0 ) begin : STATIC_MODE_ON
assign cmd_out_mw = {
32'h0,
32'h0,
static_ctl_en,7'h0,3'b010,id,size,burst,2'b00,len,
C_ATG_STATIC_ADDRESS
};
assign cmd_out_mr = {
32'h0,
32'h0,
static_ctl_en,7'h0,3'b010,id,size,burst,2'b00,len,
C_ATG_STATIC_ADDRESS
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = {
64'hCAFE5AFE_C001CAFE,
64'hCAFE1AFE_C001DAFE,
64'hCAFE2AFE_C001EAFE,
64'hCAFE3AFE_C001FAFE
};
end
endgenerate
wire system_init_en;
wire system_init_cnt_en;
wire system_init_cmd_en;
// disable when no.of commands count reached Maximum limit(16)
assign system_init_cnt_en = (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS] != 1'b1);
// disable when command has cmd-valid bit set to 0
assign system_init_cmd_en = ~(&rom_addr); // All 1's is NOP OPCODE.
assign system_init_en = system_init_cnt_en && system_init_cmd_en;
generate if(C_ATG_SYSTEM_INIT == 1 || C_ATG_SYSTEM_TEST == 1 ) begin : SYSTEM_INIT_TEST_MODE_ON
assign cmd_out_mw = {
32'h0,
32'h0,
system_init_en,7'h0,3'b010,id,size,burst,2'b00,8'h0,
rom_addr[31:0]
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = rom_data[31:0];
end
endgenerate
endmodule
|
//-------------------------------------------------------------------------
// This Verilog file was developed by Altera Corporation. It may be
// freely copied and/or distributed at no cost. Any persons using this
// file for any purpose do so at their own risk, and are responsible for
// the results of such use. Altera Corporation does not guarantee that
// this file is complete, correct, or fit for any particular purpose.
// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
// accompany any copy of this file.
//------------------------------------------------------------------------
//
// Quartus II 13.1.3 Build 178 02/12/2014
//
//------------------------------------------------------------------------
// LPM Synthesizable Models (Support string type generic)
// These models are based on LPM version 220 (EIA-IS103 October 1998).
//------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Assumptions:
//
// 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and
// LPM_STRENGTH is string UNUSED.
//
//-----------------------------------------------------------------------------
// Verilog Language Issues:
//
// Two dimensional ports are not supported. Modules with two dimensional
// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
// bits wide.
//
//-----------------------------------------------------------------------------
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_MEMORY_INITIALIZATION
//
// Description : Common function to read intel-hex format data file with
// extension .hex and creates the equivalent verilog format
// data file with extension .ver.
//
// Limitation : Supports only record type '00'(data record), '01'(end of
// file record) and '02'(extended segment address record).
//
// Results expected: Creates the verilog format data file with extension .ver
// and return the name of the file.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
`define LPM_TRUE 1
`define LPM_FALSE 0
`define LPM_NULL 0
`define LPM_EOF -1
`define LPM_MAX_NAME_SZ 128
`define LPM_MAX_WIDTH 256
`define LPM_COLON ":"
`define LPM_DOT "."
`define LPM_NEWLINE "\n"
`define LPM_CARRIAGE_RETURN 8'h0D
`define LPM_SPACE " "
`define LPM_TAB "\t"
`define LPM_OPEN_BRACKET "["
`define LPM_CLOSE_BRACKET "]"
`define LPM_OFFSET 9
`define LPM_H10 8'h10
`define LPM_H10000 20'h10000
`define LPM_AWORD 8
`define LPM_MASK15 32'h000000FF
`define LPM_EXT_STR "ver"
`define LPM_PERCENT "%"
`define LPM_MINUS "-"
`define LPM_SEMICOLON ";"
`define LPM_EQUAL "="
// MODULE DECLARATION
module LPM_MEMORY_INITIALIZATION;
/****************************************************************/
/* convert uppercase character values to lowercase. */
/****************************************************************/
function [8:1] tolower;
input [8:1] given_character;
reg [8:1] conv_char;
begin
if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
tolower = conv_char;
end
else
tolower = given_character;
end
endfunction
/****************************************************************/
/* Read in Altera-mif format data to verilog format data. */
/****************************************************************/
task convert_mif2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] buffer;
reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2;
reg [8 : 1] c;
reg [3 : 0] hex, tmp_char;
reg [24 : 1] address_radix, data_radix;
reg get_width;
reg get_depth;
reg get_data_radix;
reg get_address_radix;
reg width_found;
reg depth_found;
reg data_radix_found;
reg address_radix_found;
reg get_address_data_pairs;
reg get_address;
reg get_data;
reg display_address;
reg invalid_address;
reg get_start_address;
reg get_end_address;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer memory_width, memory_depth;
integer value;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ;
integer start_address, end_address;
integer line_no;
integer character_count;
integer comment_with_percent_found;
integer comment_with_double_minus_found;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
comment_with_percent_found = `LPM_FALSE;
comment_with_double_minus_found = `LPM_FALSE;
off_addr= 0;
nn= 0;
address = 0;
start_address = 0;
end_address = 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
value = 0;
buffer = "";
character_count = 0;
memory_width = 0;
memory_depth = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}};
address_radix = "hex";
data_radix = "hex";
get_width = `LPM_FALSE;
get_depth = `LPM_FALSE;
get_data_radix = `LPM_FALSE;
get_address_radix = `LPM_FALSE;
width_found = `LPM_FALSE;
depth_found = `LPM_FALSE;
data_radix_found = `LPM_FALSE;
address_radix_found = `LPM_FALSE;
get_address_data_pairs = `LPM_FALSE;
display_address = `LPM_FALSE;
invalid_address = `LPM_FALSE;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_FALSE;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
// to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
done = `LPM_TRUE;
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
else if (buffer == "content")
begin
// continue to next character
end
else
if (buffer != "")
begin
// found invalid syntax in the particular line.
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
disable READER;
end
line_no = line_no +1;
end
else if ((r == `LPM_SPACE) || (r == `LPM_TAB))
begin
// continue to next character;
end
else if (r == `LPM_PERCENT)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else if (r == `LPM_MINUS)
begin
r = $fgetc(ifp);
if (r == `LPM_MINUS)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_EQUAL)
begin
if (buffer == "width")
begin
if (width_found == `LPM_FALSE)
begin
get_width = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (buffer == "depth")
begin
get_depth = `LPM_TRUE;
buffer = "";
end
else if (buffer == "data_radix")
begin
get_data_radix = `LPM_TRUE;
buffer = "";
end
else if (buffer == "address_radix")
begin
get_address_radix = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if (invalid_address == `LPM_TRUE)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
begin
get_address = `LPM_FALSE;
get_data = `LPM_TRUE;
display_address = `LPM_TRUE;
end
end
else if (r == `LPM_DOT)
begin
r = $fgetc(ifp);
if (r == `LPM_DOT)
begin
if (get_start_address == `LPM_TRUE)
begin
start_address = address;
address = 0;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_TRUE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_OPEN_BRACKET)
begin
get_start_address = `LPM_TRUE;
end
else if (r == `LPM_CLOSE_BRACKET)
begin
if (get_end_address == `LPM_TRUE)
begin
end_address = address;
address = 0;
get_end_address = `LPM_FALSE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_SEMICOLON)
begin
if (get_width == `LPM_TRUE)
begin
width_found = `LPM_TRUE;
memory_width = value;
value = 0;
get_width = `LPM_FALSE;
end
else if (get_depth == `LPM_TRUE)
begin
depth_found = `LPM_TRUE;
memory_depth = value;
value = 0;
get_depth = `LPM_FALSE;
end
else if (get_data_radix == `LPM_TRUE)
begin
data_radix_found = `LPM_TRUE;
get_data_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
data_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (get_address_radix == `LPM_TRUE)
begin
address_radix_found = `LPM_TRUE;
get_address_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
address_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (buffer == "end")
begin
if (get_address_data_pairs == `LPM_TRUE)
begin
last_rec = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_data == `LPM_TRUE)
begin
get_address = `LPM_TRUE;
get_data = `LPM_FALSE;
buffer = "";
character_count = 0;
if (start_address != end_address)
begin
for (address = start_address; address <= end_address; address = address+1)
begin
$fdisplay(ofp,"@%0h", address);
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
end
start_address = 0;
end_address = 0;
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
else
begin
if (display_address == `LPM_TRUE)
begin
$fdisplay(ofp,"@%0h", address);
display_address = `LPM_FALSE;
end
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE))
begin
if ((r >= "0") && (r <= "9"))
value = (value * 10) + (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_address == `LPM_TRUE)
begin
if (address_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 16) + value;
end
else if ((address_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 2) + value;
end
else if (address_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 8) + value;
end
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
else if (get_data == `LPM_TRUE)
begin
character_count = character_count +1;
if (data_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 16) + value;
end
else if ((data_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 2) + value;
end
else if (data_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 8) + value;
end
end
else
begin
first_rec = `LPM_TRUE;
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_mif2ver
/****************************************************************/
/* Read in Intel-hex format data to verilog format data. */
/* Intel-hex format :nnaaaaattddddcc */
/****************************************************************/
task convert_hex2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [8:1] c;
reg [3:0] hex, tmp_char;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ;
integer line_no;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
off_addr= 0;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
first_rec = `LPM_TRUE;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
// get record length bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
nn = (nn * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
nn = (nn * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
nn = (nn * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// get address bytes
for (i = 0; i < 4; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
aaaa = (aaaa * 16) + hex;
if (i < 2)
aal = (aal * 16) + hex;
else
aah = (aah * 16) + hex;
end
// get record type bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
tt = (tt * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
tt = (tt * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
tt = (tt * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
if((tt == 2) && (nn != 2) )
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else
begin
// get the sum of all the bytes for record length, address and record types
sum = nn + aah + aal + tt ;
// check the record type
case(tt)
// normal_record
8'h00 :
begin
first_rec = `LPM_TRUE;
i = 0;
k = width / `LPM_AWORD;
if ((width % `LPM_AWORD) != 0)
k = k + 1;
// k = no. of bytes per entry.
while (i < nn)
begin
$fdisplay(ofp,"@%0h", (aaaa + off_addr));
for (j = 1; j <= k; j = j +1)
begin
if ((k - j +1) > nn)
begin
for(m = 1; m <= 2; m= m+1)
begin
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "0");
end
end
else
begin
// get the data bytes
for(m = 1; m <= 2; m= m+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "%h", hex);
dd = (dd * 16) + hex;
if(m % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
end
end
$fwrite(ofp, "\n");
i = i + k;
aaaa = aaaa + 1;
end // end of while (i < nn)
end
// last record
8'h01:
begin
last_rec = `LPM_TRUE;
done = `LPM_TRUE;
end
// address base record
8'h02:
begin
off_addr= 0;
// get the extended segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10;
end
// address base record
8'h03:
// get the start segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
// address base record
8'h04:
begin
off_addr= 0;
// get the extended linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10000;
end
// address base record
8'h05:
// get the start linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
default:
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
endcase
// get the checksum bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
cc = (cc * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
cc = 10 + (cc * 16) + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
cc = 10 + (cc * 16) + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// Perform check sum.
if(((~sum+1)& `LPM_MASK15) != cc)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
end
else if (r == `LPM_SPACE)
begin
// continue to next character;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_hex2ver
task convert_to_ver_file;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
integer width;
begin
if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") ||
(in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
convert_hex2ver(in_file, width, out_file);
else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF"))
convert_mif2ver(in_file, width, out_file);
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file);
$display("Time: %0t Instance: %m", $time);
end
end
endtask // convert_to_ver_file
endmodule // LPM_MEMORY_INITIALIZATION
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_HINT_EVALUATION
//
// Description : Common function to grep the value of altera specific parameters
// within the lpm_hint parameter.
//
// Limitation : No error checking to check whether the content of the lpm_hint
// is valid or not.
//
// Results expected: If the target parameter found, return the value of the parameter.
// Otherwise, return empty string.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_HINT_EVALUATION;
// FUNCTON DECLARATION
// This function will search through the string (given string) to look for a match for the
// a given parameter(compare_param_name). It will return the value for the given parameter.
function [8*200:1] GET_PARAMETER_VALUE;
input [8*200:1] given_string; // string to be searched
input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string.
integer param_value_char_count; // to indicate current character count in the param_value
integer param_name_char_count; // to indicate current character count in the param_name
integer white_space_count;
reg extract_param_value; // if 1 mean extracting parameters value from given string
reg extract_param_name; // if 1 mean extracting parameters name from given string
reg param_found; // to indicate whether compare_param_name have been found in the given_string
reg include_white_space; // if 1, include white space in the parameter value
reg [8*200:1] reg_string; // to store the value of the given string
reg [8*50:1] param_name; // to store parameter name
reg [8*20:1] param_value; // to store parameter value
reg [8:1] tmp; // to get the value of the current byte
begin
reg_string = given_string;
param_value_char_count = 0;
param_name_char_count =0;
extract_param_value = 1;
extract_param_name = 0;
param_found = 0;
include_white_space = 0;
white_space_count = 0;
tmp = reg_string[8:1];
// checking every bytes of the reg_string from right to left.
while ((tmp != 0 ) && (param_found != 1))
begin
tmp = reg_string[8:1];
//if tmp != ' ' or should include white space (trailing white space are ignored)
if((tmp != 32) || (include_white_space == 1))
begin
if(tmp == 32)
begin
white_space_count = 1;
end
else if(tmp == 61) // if tmp = '='
begin
extract_param_value = 0;
extract_param_name = 1; // subsequent bytes should be part of param_name
include_white_space = 0; // ignore the white space (if any) between param_name and '='
white_space_count = 0;
param_value = param_value >> (8 * (20 - param_value_char_count));
param_value_char_count = 0;
end
else if (tmp == 44) // if tmp = ','
begin
extract_param_value = 1; // subsequent bytes should be part of param_value
extract_param_name = 0;
param_name = param_name >> (8 * (50 - param_name_char_count));
param_name_char_count = 0;
if(param_name == compare_param_name)
param_found = 1; // the compare_param_name have been found in the reg_string
end
else
begin
if(extract_param_value == 1)
begin
param_value_char_count = param_value_char_count + white_space_count + 1;
include_white_space = 1;
if(white_space_count > 0)
begin
param_value = {8'b100000, param_value[20*8:9]};
white_space_count = 0;
end
param_value = {tmp, param_value[20*8:9]};
end
else if(extract_param_name == 1)
begin
param_name = {tmp, param_name[50*8:9]};
param_name_char_count = param_name_char_count + 1;
end
end
end
reg_string = reg_string >> 8; // shift 1 byte to the right
end
// for the case whether param_name is the left most part of the reg_string
if(extract_param_name == 1)
begin
param_name = param_name >> (8 * (50 - param_name_char_count));
if(param_name == compare_param_name)
param_found = 1;
end
if (param_found == 1)
GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
else
GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
end
endfunction
endmodule // LPM_HINT_EVALUATION
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_DEVICE_FAMILIES;
function IS_FAMILY_CYCLONE;
input[8*20:1] device;
reg is_cyclone;
begin
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
is_cyclone = 1;
else
is_cyclone = 0;
IS_FAMILY_CYCLONE = is_cyclone;
end
endfunction //IS_FAMILY_CYCLONE
function IS_FAMILY_MAX3000A;
input[8*20:1] device;
reg is_max3000a;
begin
if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
is_max3000a = 1;
else
is_max3000a = 0;
IS_FAMILY_MAX3000A = is_max3000a;
end
endfunction //IS_FAMILY_MAX3000A
function IS_FAMILY_MAX7000A;
input[8*20:1] device;
reg is_max7000a;
begin
if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
is_max7000a = 1;
else
is_max7000a = 0;
IS_FAMILY_MAX7000A = is_max7000a;
end
endfunction //IS_FAMILY_MAX7000A
function IS_FAMILY_MAX7000AE;
input[8*20:1] device;
reg is_max7000ae;
begin
if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
is_max7000ae = 1;
else
is_max7000ae = 0;
IS_FAMILY_MAX7000AE = is_max7000ae;
end
endfunction //IS_FAMILY_MAX7000AE
function IS_FAMILY_MAX7000B;
input[8*20:1] device;
reg is_max7000b;
begin
if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
is_max7000b = 1;
else
is_max7000b = 0;
IS_FAMILY_MAX7000B = is_max7000b;
end
endfunction //IS_FAMILY_MAX7000B
function IS_FAMILY_MAX7000S;
input[8*20:1] device;
reg is_max7000s;
begin
if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
is_max7000s = 1;
else
is_max7000s = 0;
IS_FAMILY_MAX7000S = is_max7000s;
end
endfunction //IS_FAMILY_MAX7000S
function IS_FAMILY_STRATIXGX;
input[8*20:1] device;
reg is_stratixgx;
begin
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
is_stratixgx = 1;
else
is_stratixgx = 0;
IS_FAMILY_STRATIXGX = is_stratixgx;
end
endfunction //IS_FAMILY_STRATIXGX
function IS_FAMILY_STRATIX;
input[8*20:1] device;
reg is_stratix;
begin
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
is_stratix = 1;
else
is_stratix = 0;
IS_FAMILY_STRATIX = is_stratix;
end
endfunction //IS_FAMILY_STRATIX
function FEATURE_FAMILY_BASE_STRATIX;
input[8*20:1] device;
reg var_family_base_stratix;
begin
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
var_family_base_stratix = 1;
else
var_family_base_stratix = 0;
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
end
endfunction //FEATURE_FAMILY_BASE_STRATIX
function FEATURE_FAMILY_BASE_CYCLONE;
input[8*20:1] device;
reg var_family_base_cyclone;
begin
if (IS_FAMILY_CYCLONE(device) )
var_family_base_cyclone = 1;
else
var_family_base_cyclone = 0;
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
end
endfunction //FEATURE_FAMILY_BASE_CYCLONE
function FEATURE_FAMILY_MAX;
input[8*20:1] device;
reg var_family_max;
begin
if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") )
var_family_max = 1;
else
var_family_max = 0;
FEATURE_FAMILY_MAX = var_family_max;
end
endfunction //FEATURE_FAMILY_MAX
function IS_VALID_FAMILY;
input[8*20:1] device;
reg is_valid;
begin
if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)"))
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|| ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|| ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz"))
|| ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)"))
|| ((device == "BS") || (device == "bs"))
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii"))
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|| ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|| ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|| ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)"))
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|| ((device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10FPGA") || (device == "max10fpga") || (device == "MAX 10 FPGA (DA/DF/DC/SF/SC)") || (device == "max 10 fpga (da/df/dc/sf/sc)") || (device == "MAX10FPGA(DA/DF/DC/SF/SC)") || (device == "max10fpga(da/df/dc/sf/sc)") || (device == "MAX 10 FPGA (DA)") || (device == "max 10 fpga (da)") || (device == "MAX10FPGA(DA)") || (device == "max10fpga(da)") || (device == "MAX 10 FPGA (DF)") || (device == "max 10 fpga (df)") || (device == "MAX10FPGA(DF)") || (device == "max10fpga(df)") || (device == "MAX 10 FPGA (DC)") || (device == "max 10 fpga (dc)") || (device == "MAX10FPGA(DC)") || (device == "max10fpga(dc)") || (device == "MAX 10 FPGA (SF)") || (device == "max 10 fpga (sf)") || (device == "MAX10FPGA(SF)") || (device == "max10fpga(sf)") || (device == "MAX 10 FPGA (SC)") || (device == "max 10 fpga (sc)") || (device == "MAX10FPGA(SC)") || (device == "max10fpga(sc)"))
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|| ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|| ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|| ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|| ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)"))
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|| ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock")))
is_valid = 1;
else
is_valid = 0;
IS_VALID_FAMILY = is_valid;
end
endfunction // IS_VALID_FAMILY
endmodule // LPM_DEVICE_FAMILIES
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_constant
//
// Description : Parameterized constant generator megafunction. lpm_constant
// may be useful for convert a parameter into a constant.
//
// Limitation : n/a
//
// Results expected: Value specified by the argument to LPM_CVALUE.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_constant (
result // Value specified by the argument to LPM_CVALUE. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the result[] port. (Required)
parameter lpm_cvalue = 0; // Constant value to be driven out on the
// result[] port. (Required)
parameter lpm_strength = "UNUSED";
parameter lpm_type = "lpm_constant";
parameter lpm_hint = "UNUSED";
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg[32:0] int_value;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
int_value = lpm_cvalue;
end
// CONTINOUS ASSIGNMENT
assign result = int_value[lpm_width-1:0];
endmodule // lpm_constant
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inv
//
// Description : Parameterized inverter megafunction.
//
// Limitation : n/a
//
// Results expected: Inverted value of input data
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inv (
data, // Data input to the lpm_inv. (Required)
result // inverted result. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required)
parameter lpm_type = "lpm_inv";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
result = ~data;
endmodule // lpm_inv
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_and
//
// Description : Parameterized AND gate. This megafunction takes in data inputs
// for a number of AND gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each AND gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_and (
data, // Data input to the AND gate. (Required)
result // Result of the AND operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[][] and result[] ports. Number of AND gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each AND gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_and";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b1;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] & data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_and
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_or
//
// Description : Parameterized OR gate megafunction. This megafunction takes in
// data inputs for a number of OR gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each OR gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_or (
data, // Data input to the OR gates. (Required)
result // Result of OR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of OR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each OR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_or";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] | data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_or
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_xor
//
// Description : Parameterized XOR gate megafunction. This megafunction takes in
// data inputs for a number of XOR gates.
//
// Limitation : n/a.
//
// Results expected: Each result[] bit is the result of each XOR gates.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_xor (
data, // Data input to the XOR gates. (Required)
result // Result of XOR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of XOR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each XOR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_xor";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] ^ data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_xor
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bustri
//
// Description : Parameterized tri-state buffer. lpm_bustri is useful for
// controlling both unidirectional and bidirectional I/O bus
// controllers.
//
// Limitation : n/a
//
// Results expected: Belows are the three configurations which are valid:
//
// 1) Only the input ports data[LPM_WIDTH-1..0] and enabledt are
// present, and only the output ports tridata[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabledt | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | DATA[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 2) Only the input ports tridata[LPM_WIDTH-1..0] and enabletr
// are present, and only the output ports result[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabletr | result[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | tridata[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 3) All ports are present: input ports data[LPM_WIDTH-1..0],
// enabledt, and enabletr; output ports result[LPM_WIDTH-1..0];
// and bidirectional ports tridata[LPM_WIDTH-1..0].
//
// ----------------------------------------------------------------------------
// | Input | Bidirectional | Output |
// |----------------------------------------------------------------------------|
// | enabledt | enabletr | tridata[LPM_WIDTH-1..0] | result[LPM_WIDTH-1..0] |
// |============================================================================|
// | 0 | 0 | Z (input) | Z |
// |----------------------------------------------------------------------------|
// | 0 | 1 | Z (input) | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------------------------------|
// | 1 | 0 | data[LPM_WIDTH-1..0] | Z |
// |----------------------------------------------------------------------------|
// | 1 | 1 | data[LPM_WIDTH-1..0] | data[LPM_WIDTH-1..0] |
// ----------------------------------------------------------------------------
//
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bustri (
tridata, // Bidirectional bus signal. (Required)
data, // Data input to the tridata[] bus. (Required)
enabletr, // If high, enables tridata[] onto the result bus.
enabledt, // If high, enables data onto the tridata[] bus.
result // Output from the tridata[] bus.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bustri";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enabletr;
input enabledt;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] tridata;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INTERNAL TRI DECLARATION
tri1 enabletr;
tri1 enabledt;
wire i_enabledt;
wire i_enabletr;
buf (i_enabledt, enabledt);
buf (i_enabletr, enabletr);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or tridata or i_enabletr or i_enabledt)
begin
if ((i_enabledt == 1'b0) && (i_enabletr == 1'b1))
begin
result = tridata;
end
else if ((i_enabledt == 1'b1) && (i_enabletr == 1'b1))
begin
result = data;
end
else
begin
result = {lpm_width{1'bz}};
end
end
// CONTINOUS ASSIGNMENT
assign tridata = (i_enabledt == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bustri
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_mux
//
// Description : Parameterized multiplexer megafunctions.
//
// Limitation : n/a
//
// Results expected: Selected input port.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_mux (
data, // Data input. (Required)
sel, // Selects one of the input buses. (Required)
clock, // Clock for pipelined usage
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result // Selected input port. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[][] and result[] ports. (Required)
parameter lpm_size = 2; // Number of input buses to the multiplexer. (Required)
parameter lpm_widths = 1; // Width of the sel[] input port. (Required)
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the result[] output.
parameter lpm_type = "lpm_mux";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
input [lpm_widths-1:0] sel;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [lpm_pipeline+1:0];
reg [lpm_width-1:0] tmp_result;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 1)
begin
$display("Value of lpm_size parameter must be greater than 1 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widths <= 0)
begin
$display("Value of lpm_widths parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must NOT less than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or sel)
begin
tmp_result = 0;
if (sel < lpm_size)
begin
for (i = 0; i < lpm_width; i = i + 1)
tmp_result[i] = data[(sel * lpm_width) + i];
end
else
tmp_result = {lpm_width{1'bx}};
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
result_pipe[i] <= 1'b0;
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
endmodule // lpm_mux
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_decode
//
// Description : Parameterized decoder megafunction.
//
// Limitation : n/a
//
// Results expected: Decoded output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_decode (
data, // Data input. Treated as an unsigned binary encoded number. (Required)
enable, // Enable. All outputs low when not active.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
eq // Decoded output. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] port, or the
// input value to be decoded. (Required)
parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required)
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_decode";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_decodes-1:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0];
reg [lpm_decodes-1:0] tmp_eq;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 enable;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_clock;
wire i_clken;
wire i_aclr;
wire i_enable;
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
buf (i_enable, enable);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes <= 0)
begin
$display("Value of lpm_decodes parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes > (1 << lpm_width))
begin
$display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_enable)
begin
tmp_eq = {lpm_decodes{1'b0}};
if (i_enable)
tmp_eq[data] = 1'b1;
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= lpm_pipeline; i = i + 1)
eq_pipe[i] <= {lpm_decodes{1'b0}};
pipe_ptr <= 0;
end
else if (clken == 1'b1)
begin
eq_pipe[pipe_ptr] <= tmp_eq;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq;
endmodule // lpm_decode
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_clshift
//
// Description : Parameterized combinatorial logic shifter or barrel shifter
// megafunction.
//
// Limitation : n/a
//
// Results expected: Return the shifted data and underflow/overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_clshift (
data, // Data to be shifted. (Required)
distance, // Number of positions to shift data[] in the direction specified
// by the direction port. (Required)
direction, // Direction of shift. Low = left (toward the MSB),
// high = right (toward the LSB).
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // Shifted data. (Required)
underflow, // Logical or arithmetic underflow.
overflow // Logical or arithmetic overflow.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be
// greater than 0 (Required)
parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required)
parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed.
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_clshift";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] distance;
input direction;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output underflow;
output overflow;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] ONES;
reg [lpm_width-1:0] ZEROS;
reg [lpm_width-1:0] tmp_result;
reg tmp_underflow;
reg tmp_overflow;
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] overflow_pipe;
reg [(lpm_pipeline+1):0] underflow_pipe;
// LOCAL INTEGER DECLARATION
integer i;
integer i1;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 direction;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_direction;
wire i_clock;
wire i_clken;
wire i_aclr;
buf (i_direction, direction);
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
// FUNCTON DECLARATION
// Perform logival shift operation
function [lpm_width+1:0] LogicShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if ((direction) && (shift_num > 0)) // shift right
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width)
|| ((data >> (lpm_width-shift_num)) != ZEROS)))
overflow = 1'b1;
end
LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // LogicShift
// Perform Arithmetic shift operation
function [lpm_width+1:0] ArithShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
integer i;
integer i1;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if (shift_num < lpm_width)
begin
if ((direction) && (shift_num > 0)) // shift right
begin
if (data[lpm_width-1] == 1'b0) // positive number
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else // negative number
begin
tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num));
if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES)))
underflow = 1'b1;
end
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1)
begin
if(data[i-1] != data[lpm_width-1])
overflow = 1'b1;
end
end
end
else // shift_num >= lpm_width
begin
if (direction)
begin
for (i=0; i < lpm_width; i=i+1)
tmp_buf[i] = data[lpm_width-1];
underflow = 1'b1;
end
else
begin
tmp_buf = {lpm_width{1'b0}};
if (data != ZEROS)
begin
overflow = 1'b1;
end
end
end
ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // ArithShift
// Perform rotate shift operation
function [lpm_width+1:0] RotateShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
begin
tmp_buf = data;
if ((direction) && (shift_num > 0)) // shift right
tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num));
else if (shift_num > 0) // shift left
tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num));
RotateShift = {2'bx, tmp_buf[lpm_width-1:0]};
end
endfunction // RotateShift
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_shifttype != "LOGICAL") &&
(lpm_shifttype != "ARITHMETIC") &&
(lpm_shifttype != "ROTATE") &&
(lpm_shifttype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\".");
$display("Time: %0t Instance: %m", $time);
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthdist <= 0)
begin
$display("Value of lpm_widthdist parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ONES[i] = 1'b1;
ZEROS[i] = 1'b0;
end
for (i = 0; i <= lpm_pipeline; i = i + 1)
begin
result_pipe[i] = ZEROS;
overflow_pipe[i] = 1'b0;
underflow_pipe[i] = 1'b0;
end
tmp_result = ZEROS;
tmp_underflow = 1'b0;
tmp_overflow = 1'b0;
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_direction or distance)
begin
if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED"))
{tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction);
else if (lpm_shifttype == "ARITHMETIC")
{tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction);
else if (lpm_shifttype == "ROTATE")
{tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction);
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1)
begin
result_pipe[i1] <= {lpm_width{1'b0}};
overflow_pipe[i1] <= 1'b0;
underflow_pipe[i1] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
overflow_pipe[pipe_ptr] <= tmp_overflow;
underflow_pipe[pipe_ptr] <= tmp_underflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow;
endmodule // lpm_clshift
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_add_sub
//
// Description : Parameterized adder/subtractor megafunction.
//
// Limitation : n/a
//
// Results expected: If performs as adder, the result will be dataa[]+datab[]+cin.
// If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
// Also returns carry out bit and overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_add_sub (
dataa, // Augend/Minuend
datab, // Addend/Subtrahend
cin, // Carry-in to the low-order bit.
add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin.
// If the signal is low, the operation = dataa[]-datab[]+cin-1.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1
cout, // Carry-out (borrow-in) of the MSB.
overflow // Result exceeds available precision.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports.
parameter lpm_representation = "SIGNED"; // Type of addition performed
parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_add_sub";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input cin;
input add_sub;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output cout;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] cout_pipe;
reg [(lpm_pipeline+1):0] overflow_pipe;
reg tmp_cout;
reg tmp_overflow;
reg [lpm_width-1:0] tmp_result;
reg i_cin;
// LOCAL INTEGER DECLARATION
integer borrow;
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 i_add_sub;
tri0 i_aclr;
tri1 i_clken;
tri0 i_clock;
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "ADD") &&
(lpm_direction != "SUB") &&
(lpm_direction != "UNUSED") && // non-LPM 220 standard
(lpm_direction != "DEFAULT")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Error! LPM_PIPELINE must be greater than or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] = 'b0;
cout_pipe[i] = 1'b0;
overflow_pipe[i] = 1'b0;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(cin or dataa or datab or i_add_sub)
begin
i_cin = 1'b0;
borrow = 1'b0;
// cout is the same for both signed and unsign representation.
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 0 : cin;
{tmp_cout, tmp_result} = dataa + datab + i_cin;
tmp_overflow = tmp_cout;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 1 : cin;
borrow = (~i_cin) ? 1 : 0;
{tmp_overflow, tmp_result} = dataa - datab - borrow;
tmp_cout = (dataa >= (datab+borrow))?1:0;
end
if (lpm_representation == "SIGNED")
begin
// perform the addtion or subtraction operation
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa + datab + i_cin;
tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa - datab - borrow;
tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] <= {lpm_width{1'b0}};
cout_pipe[i] <= 1'b0;
overflow_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
result_pipe[pipe_ptr] <= tmp_result;
cout_pipe[pipe_ptr] <= tmp_cout;
overflow_pipe[pipe_ptr] <= tmp_overflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign i_clock = clock;
assign i_aclr = aclr;
assign i_clken = clken;
assign i_add_sub = add_sub;
endmodule // lpm_add_sub
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_compare
//
// Description : Parameterized comparator megafunction. The comparator will
// compare between data[] and datab[] and return the status of
// comparation for the following operation.
// 1) dataa[] < datab[].
// 2) dataa[] == datab[].
// 3) dataa[] > datab[].
// 4) dataa[] >= datab[].
// 5) dataa[] != datab[].
// 6) dataa[] <= datab[].
//
// Limitation : n/a
//
// Results expected: Return status bits of the comparision between dataa[] and
// datab[].
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_compare (
dataa, // Value to be compared to datab[]. (Required)
datab, // Value to be compared to dataa[]. (Required)
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
// One of the following ports must be present.
alb, // High (1) if dataa[] < datab[].
aeb, // High (1) if dataa[] == datab[].
agb, // High (1) if dataa[] > datab[].
aleb, // High (1) if dataa[] <= datab[].
aneb, // High (1) if dataa[] != datab[].
ageb // High (1) if dataa[] >= datab[].
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required)
parameter lpm_representation = "UNSIGNED"; // Type of comparison performed:
// "SIGNED", "UNSIGNED"
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the alb, aeb, agb, ageb, aleb,
// or aneb output.
parameter lpm_type = "lpm_compare";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output alb;
output aeb;
output agb;
output aleb;
output aneb;
output ageb;
// INTERNAL REGISTERS DECLARATION
reg [lpm_pipeline+1:0] alb_pipe;
reg [lpm_pipeline+1:0] aeb_pipe;
reg [lpm_pipeline+1:0] agb_pipe;
reg [lpm_pipeline+1:0] aleb_pipe;
reg [lpm_pipeline+1:0] aneb_pipe;
reg [lpm_pipeline+1:0] ageb_pipe;
reg tmp_alb;
reg tmp_aeb;
reg tmp_agb;
reg tmp_aleb;
reg tmp_aneb;
reg tmp_ageb;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
// get the status of comparison
always @(dataa or datab)
begin
tmp_aeb = (dataa == datab);
tmp_aneb = (dataa != datab);
if ((lpm_representation == "SIGNED") &&
((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1))
begin
// create latency
tmp_alb = (dataa > datab);
tmp_agb = (dataa < datab);
tmp_aleb = (dataa >= datab);
tmp_ageb = (dataa <= datab);
end
else
begin
// create latency
tmp_alb = (dataa < datab);
tmp_agb = (dataa > datab);
tmp_aleb = (dataa <= datab);
tmp_ageb = (dataa >= datab);
end
end
// pipelining process
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr) // reset all variables
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
begin
aeb_pipe[i] <= 1'b0;
agb_pipe[i] <= 1'b0;
alb_pipe[i] <= 1'b0;
aleb_pipe[i] <= 1'b0;
aneb_pipe[i] <= 1'b0;
ageb_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
alb_pipe[pipe_ptr] <= tmp_alb;
aeb_pipe[pipe_ptr] <= tmp_aeb;
agb_pipe[pipe_ptr] <= tmp_agb;
aleb_pipe[pipe_ptr] <= tmp_aleb;
aneb_pipe[pipe_ptr] <= tmp_aneb;
ageb_pipe[pipe_ptr] <= tmp_ageb;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb;
assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb;
assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb;
assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb;
assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb;
assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb;
endmodule // lpm_compare
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_divide
//
// Description : Parameterized divider megafunction. This function performs a
// divide operation such that denom * quotient + remain = numer
// The function allows for all combinations of signed(two's
// complement) and unsigned inputs. If any of the inputs is
// signed, the output is signed. Otherwise the output is unsigned.
// The function also allows the remainder to be specified as
// always positive (in which case remain >= 0); otherwise remain
// is zero or the same sign as the numerator
// (this parameter is ignored in the case of purely unsigned
// division). Finally the function is also pipelinable.
//
// Limitation : n/a
//
// Results expected: Return quotient and remainder.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_divide (
numer, // The numerator (Required)
denom, // The denominator (Required)
clock, // Clock input for pipelined usage
aclr, // Asynchronous clear signal
clken, // Clock enable for pipelined usage.
quotient, // Quotient (Required)
remain // Remainder (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required)
parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required)
parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer
parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_divide";
parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
// INPUT PORT DECLARATION
input [lpm_widthn-1:0] numer;
input [lpm_widthd-1:0] denom;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthn-1:0] quotient;
output [lpm_widthd-1:0] remain;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0];
reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0];
reg [lpm_widthn-1:0] tmp_quotient;
reg [lpm_widthd-1:0] tmp_remain;
reg [lpm_widthn-1:0] not_numer;
reg [lpm_widthn-1:0] int_numer;
reg [lpm_widthd-1:0] not_denom;
reg [lpm_widthd-1:0] int_denom;
reg [lpm_widthn-1:0] t_numer;
reg [lpm_widthn-1:0] t_q;
reg [lpm_widthd-1:0] t_denom;
reg [lpm_widthd-1:0] t_r;
reg sign_q;
reg sign_r;
reg sign_n;
reg sign_d;
reg [8*5:1] lpm_remainderpositive;
// LOCAL INTEGER DECLARATION
integer i;
integer rsig;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widthn > 0
if (lpm_widthn <= 0)
begin
$display("Error! LPM_WIDTHN must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthd > 0
if (lpm_widthd <= 0)
begin
$display("Error! LPM_WIDTHD must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_nrepresentation value
if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED"))
begin
$display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_drepresentation value
if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED"))
begin
$display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_remainderpositive value
lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE");
if ((lpm_remainderpositive == "TRUE") &&
(lpm_remainderpositive == "FALSE"))
begin
$display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(numer or denom or lpm_remainderpositive)
begin
sign_q = 1'b0;
sign_r = 1'b0;
sign_n = 1'b0;
sign_d = 1'b0;
t_numer = numer;
t_denom = denom;
if (lpm_nrepresentation == "SIGNED")
if (numer[lpm_widthn-1] == 1'b1)
begin
t_numer = ~numer + 1; // numer is negative number
sign_n = 1'b1;
end
if (lpm_drepresentation == "SIGNED")
if (denom[lpm_widthd-1] == 1'b1)
begin
t_denom = ~denom + 1; // denom is negative numbrt
sign_d = 1'b1;
end
t_q = t_numer / t_denom; // get quotient
t_r = t_numer % t_denom; // get remainder
sign_q = sign_n ^ sign_d;
sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0;
// Pipeline the result
tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q;
tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r;
// Recalculate the quotient and remainder if remainder is negative number
// and LPM_REMAINDERPOSITIVE=TRUE.
if ((sign_r) && (lpm_remainderpositive == "TRUE"))
begin
tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 );
tmp_remain = tmp_remain + t_denom;
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr <= 0;
end
else if (i_clken)
begin
quotient_pipe[pipe_ptr] <= tmp_quotient;
remain_pipe[pipe_ptr] <= tmp_remain;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient;
assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain;
endmodule // lpm_divide
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_abs
//
// Description : Parameterized absolute value megafunction. This megafunction
// requires the input data to be signed number.
//
// Limitation : n/a
//
// Results expected: Return absolute value of data and the overflow status
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_abs (
data, // Signed number (Required)
result, // Absolute value of data[].
overflow // High if data = -2 ^ (LPM_WIDTH-1).
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required)
parameter lpm_type = "lpm_abs";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
reg overflow;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data;
overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0;
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_abs
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_counter
//
// Description : Parameterized counter megafunction. The lpm_counter
// megafunction is a binary counter that features an up,
// down, or up/down counter with optional synchronous or
// asynchronous clear, set, and load ports.
//
// Limitation : n/a
//
// Results expected: Data output from the counter and carry-out of the MSB.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_counter (
clock, // Positive-edge-triggered clock. (Required)
clk_en, // Clock enable input. Enables all synchronous activities.
cnt_en, // Count enable input. Disables the count when low (0) without
// affecting sload, sset, or sclr.
updown, // Controls the direction of the count. High (1) = count up.
// Low (0) = count down.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the counter with
// the value on the data input.
sclr, // Synchronous clear input. Clears the counter on the next active
// clock edge.
sset, // Synchronous set input. Sets the counter on the next active clock edge.
sload, // Synchronous load input. Loads the counter with data[] on the next
// active clock edge.
data, // Parallel data input to the counter.
cin, // Carry-in to the low-order bit.
q, // Data output from the counter.
cout, // Carry-out of the MSB.
eq // Counter decode output. Active high when the counter reaches the specified
// count value.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; //The number of bits in the count, or the width of the q[]
// and data[] ports, if they are used. (Required)
parameter lpm_direction = "UNUSED"; // Direction of the count.
parameter lpm_modulus = 0; // The maximum count, plus one.
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_port_updown = "PORT_CONNECTIVITY";
parameter lpm_type = "lpm_counter";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input clock;
input clk_en;
input cnt_en;
input updown;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload;
input [lpm_width-1:0] data;
input cin;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output cout;
output [15:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_count;
reg [lpm_width-1:0] adata;
reg use_adata;
reg tmp_updown;
reg [lpm_width:0] tmp_modulus;
reg [lpm_width:0] max_modulus;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire w_updown;
wire [lpm_width-1:0] final_count;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 clk_en;
tri1 cnt_en;
tri0 aclr;
tri0 aset;
tri0 aload;
tri0 sclr;
tri0 sset;
tri0 sload;
tri1 cin;
tri1 updown_z;
wire i_clk_en;
wire i_cnt_en;
wire i_aclr;
wire i_aset;
wire i_aload;
wire i_sclr;
wire i_sset;
wire i_sload;
wire i_cin;
wire i_updown;
buf (i_clk_en, clk_en);
buf (i_cnt_en, cnt_en);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_aload, aload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_sload, sload);
buf (i_cin, cin);
buf (i_updown, updown_z);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
max_modulus = 1 << lpm_width;
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus < 0
if (lpm_modulus < 0)
begin
$display("Error! LPM_MODULUS must be greater or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus > 1<<lpm_width
if (lpm_modulus > max_modulus)
begin
$display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") &&
(lpm_direction != "UP") && (lpm_direction != "DOWN"))
begin
$display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus))
? max_modulus : lpm_modulus;
tmp_count = pvalue;
use_adata = 1'b0;
end
// NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1
initial #0
begin
// // check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) &&
(lpm_port_updown == "PORT_CONNECTIVITY"))
begin
$display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin
if (i_clk_en)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_count <= 0;
else if (i_sset)
tmp_count <= svalue;
else if (i_sload)
tmp_count <= data;
else if (i_cnt_en && i_cin)
begin
if (w_updown)
tmp_count <= (final_count == tmp_modulus-1) ? 0
: final_count+1;
else
tmp_count <= (final_count == 0) ? tmp_modulus-1
: final_count-1;
end
else
tmp_count <= final_count;
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue)
begin
if (i_aclr)
begin
adata <= 0;
end
else if (i_aset)
begin
adata <= avalue;
end
else if (i_aload)
adata <= data;
end
// CONTINOUS ASSIGNMENT
assign q = final_count;
assign final_count = (use_adata == 1'b1) ? adata : tmp_count;
assign cout = (i_cin && (((w_updown==0) && (final_count==0)) ||
((w_updown==1) && ((final_count==tmp_modulus-1) ||
(final_count=={lpm_width{1'b1}}))) ))
? 1'b1 : 1'b0;
assign updown_z = updown;
assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown :
(lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) :
((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) ||
(lpm_direction == "UP"))
? 1'b1 : 1'b0;
assign eq = {16{1'b0}};
endmodule // lpm_counter
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_latch
//
// Description : Parameterized latch megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the latch.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_latch (
data, // Data input to the latch.
gate, // Latch enable input. High = flow-through, low = latch. (Required)
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aconst,
q // Data output from the latch.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_latch";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input gate;
input aclr;
input aset;
input aconst;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] q;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL TRI DECLARATION
tri0 [lpm_width-1:0] data;
tri0 aclr;
tri0 aset;
tri0 aconst;
wire i_aclr;
wire i_aset;
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pvalue != "UNUSED")
begin
string_to_reg(lpm_pvalue, pvalue);
q = pvalue;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
end
// ALWAYS CONSTRUCT BLOCK
always @(data or gate or i_aclr or i_aset or avalue)
begin
if (i_aclr)
q <= {lpm_width{1'b0}};
else if (i_aset)
q <= avalue;
else if (gate)
q <= data;
end
endmodule // lpm_latch
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ff
//
// Description : Parameterized flipflop megafunction. The lpm_ff function
// contains features that are not available in the DFF, DFFE,
// DFFEA, TFF, and TFFE primitives, such as synchronous or
// asynchronous set, clear, and load inputs.
//
// Limitation : n/a
//
// Results expected: Data output from D or T flipflops.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ff (
data, // T-type flipflop: Toggle enable
// D-type flipflop: Data input
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the flipflop with
// the value on the data input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
sload, // Synchronous load input. Loads the flipflop with the value on the
// data input on the next active clock edge.
q // Data output from D or T flipflops. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_fftype = "DFF"; // Type of flipflop
parameter lpm_type = "lpm_ff";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload ;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] adata;
reg use_adata;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] final_q;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 [lpm_width-1:0] data;
tri1 enable;
tri0 sload;
tri0 sclr;
tri0 sset;
tri0 aload;
tri0 aclr;
tri0 aset;
wire i_enable;
wire i_sload;
wire i_sclr;
wire i_sset;
wire i_aload;
wire i_aclr;
wire i_aset;
buf (i_enable, enable);
buf (i_sload, sload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_aload, aload);
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_fftype != "DFF") &&
(lpm_fftype != "TFF") &&
(lpm_fftype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
use_adata = 1'b0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin // Asynchronous process
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin // Synchronous process
if (i_enable)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_q <= 0;
else if (i_sset)
tmp_q <= svalue;
else if (i_sload) // Load data
tmp_q <= data;
else
begin
if (lpm_fftype == "TFF") // toggle
begin
for (i = 0; i < lpm_width; i=i+1)
if (data[i] == 1'b1)
tmp_q[i] <= ~final_q[i];
else
tmp_q[i] <= final_q[i];
end
else // DFF, load data
tmp_q <= data;
end
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue or pvalue)
begin
if (i_aclr === 1'b1)
adata <= {lpm_width{1'b0}};
else if (i_aclr === 1'bx)
adata <= {lpm_width{1'bx}};
else if (i_aset)
adata <= avalue;
else if (i_aload)
adata <= data;
else if ((i_aclr === 1'b0) && ($time == 0))
adata <= pvalue;
end
// CONTINOUS ASSIGNMENT
assign q = final_q;
assign final_q = (use_adata == 1'b1) ? adata : tmp_q;
endmodule // lpm_ff
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_shiftreg
//
// Description : Parameterized shift register megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the shift register and the Serial shift data output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_shiftreg (
data, // Data input to the shift register.
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input
shiftin, // Serial shift data input.
load, // Synchronous parallel load. High (1): load operation;
// low (0): shift operation.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
q, // Data output from the shift register.
shiftout // Serial shift data output.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q ports. (Required)
parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED".
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_shiftreg";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input shiftin;
input load;
input aclr;
input aset;
input sclr;
input sset;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output shiftout;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg abit;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL WIRE DECLARATION
wire tmp_shiftout;
// INTERNAL TRI DECLARATION
tri1 enable;
tri1 shiftin;
tri0 load;
tri0 aclr;
tri0 aset;
tri0 sclr;
tri0 sset;
wire i_enable;
wire i_shiftin;
wire i_load;
wire i_aclr;
wire i_aset;
wire i_sclr;
wire i_sset;
buf (i_enable, enable);
buf (i_shiftin, shiftin);
buf (i_load, load);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_sclr, sclr);
buf (i_sset, sset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "LEFT") &&
(lpm_direction != "RIGHT") &&
(lpm_direction != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
end
// ALWAYS CONSTRUCT BLOCK
always @(i_aclr or i_aset or avalue)
begin
if (i_aclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
end
always @(posedge clock)
begin
if (i_aclr)
tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
else
begin
if (i_enable)
begin
if (i_sclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_sset)
tmp_q <= svalue;
else if (i_load)
tmp_q <= data;
else if (!i_load)
begin
if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED"))
{abit,tmp_q} <= {tmp_q,i_shiftin};
else if (lpm_direction == "RIGHT")
{tmp_q,abit} <= {i_shiftin,tmp_q};
end
end
end
end
// CONTINOUS ASSIGNMENT
assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0]
: tmp_q[lpm_width-1];
assign q = tmp_q;
assign shiftout = tmp_shiftout;
endmodule // lpm_shiftreg
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dq
//
// Description : Parameterized RAM with separate input and output ports megafunction.
// lpm_ram_dq implement asynchronous memory or memory with synchronous
// inputs and/or outputs.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dq (
data, // Data input to the memory. (Required)
address, // Address input to the memory. (Required)
inclock, // Synchronizes memory loading.
outclock, // Synchronizes q outputs from memory.
we, // Write enable input. Enables write operations to the memory when high. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the address port. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered.
parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered.
parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dq";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input we;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdata;
reg [lpm_width-1:0] in_data;
reg [lpm_widthad-1:0] paddress;
reg pwe;
reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN;
reg [8*256:1] ram_initf;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
wire i_inclock;
wire i_outclock;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize the internal data register.
pdata = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
pwe = 1'b0;
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad)) ||
(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ZEROS[i] = 1'b0;
ONES[i] = 1'b1;
UNKNOWN[i] = 1'bX;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
tmp_q = ZEROS;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
begin
if ((we) && (use_eab != "ON") &&
(lpm_hint != "USE_EAB=ON"))
begin
if (lpm_indata == "REGISTERED")
mem_data[address] <= data;
else
mem_data[address] <= pdata;
end
paddress <= address;
pwe <= we;
end
if (lpm_indata == "REGISTERED")
pdata <= data;
end
always @(data)
begin
if (lpm_indata == "UNREGISTERED")
pdata <= data;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(pdata or paddress or pwe)
begin :UNREGISTERED_INCLOCK
if (ValidAddress(paddress))
begin
if ((lpm_address_control == "UNREGISTERED") && (pwe))
mem_data[paddress] <= pdata;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(paddress))
tmp_q <= mem_data[paddress];
else
tmp_q <= {lpm_width{1'bx}};
end
end
always @(i_inclock or pwe or paddress or pdata)
begin
if ((lpm_address_control == "REGISTERED") && (pwe))
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
if (i_inclock == 1'b0)
mem_data[paddress] = pdata;
end
end
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q;
endmodule // lpm_ram_dq
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dp
//
// Description : Parameterized dual-port RAM megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dp (
data, // Data input to the memory. (Required)
rdaddress, // Read address input to the memory. (Required)
wraddress, // Write address input to the memory. (Required)
rdclock, // Positive-edge-triggered clock for read operation.
rdclken, // Clock enable for rdclock.
wrclock, // Positive-edge-triggered clock for write operation.
wrclken, // Clock enable for wrclock.
rden, // Read enable input. Disables reading when low (0).
wren, // Write enable input. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port.
parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports.
parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports.
parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter rden_used = "TRUE"; // Specified whether to use the rden port or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dp";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] rdaddress;
input [lpm_widthad-1:0] wraddress;
input rdclock;
input rdclken;
input wrclock;
input wrclken;
input rden;
input wren;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthad)-1:0];
reg [lpm_width-1:0] i_data_reg, i_data_tmp, i_q_reg, i_q_tmp;
reg [lpm_widthad-1:0] i_wraddress_reg, i_wraddress_tmp;
reg [lpm_widthad-1:0] i_rdaddress_reg, i_rdaddress_tmp;
reg i_wren_reg, i_wren_tmp, i_rden_reg, i_rden_tmp;
reg [8*256:1] ram_initf;
// LOCAL INTEGER DECLARATION
integer i, i_numwords;
// INTERNAL TRI DECLARATION
tri0 wrclock;
tri1 wrclken;
tri0 rdclock;
tri1 rdclken;
tri0 wren;
tri1 rden;
wire i_inclock;
wire i_inclocken;
wire i_outclock;
wire i_outclocken;
wire i_wren;
wire i_rden;
buf (i_inclock, wrclock);
buf (i_inclocken, wrclken);
buf (i_outclock, rdclock);
buf (i_outclocken, rdclken);
buf (i_wren, wren);
buf (i_rden, rden);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Check for invalid parameters
if (lpm_width < 1)
begin
$display("Error! lpm_width parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad < 1)
begin
$display("Error! lpm_widthad parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
end
if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
// Initialize mem_data
i_numwords = (lpm_numwords) ? lpm_numwords : (1<<lpm_widthad);
if (lpm_file == "UNUSED")
for (i=0; i<i_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
// Initialize registers
i_data_reg = {lpm_width{1'b0}};
i_wraddress_reg = {lpm_widthad{1'b0}};
i_rdaddress_reg = {lpm_widthad{1'b0}};
i_wren_reg = 1'b0;
if (rden_used == "TRUE")
i_rden_reg = 1'b0;
else
i_rden_reg = 1'b1;
// Initialize output
i_q_reg = {lpm_width{1'b0}};
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
i_q_tmp = {lpm_width{1'b1}};
end
else
i_q_tmp = {lpm_width{1'b0}};
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
i_data_reg <= data;
if (lpm_wraddress_control == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
begin
i_wraddress_reg <= wraddress;
i_wren_reg <= i_wren;
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_q_reg <= i_q_tmp;
end
if (lpm_rdaddress_control == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_rdaddress_reg <= rdaddress;
i_rden_reg <= i_rden;
end
end
//=========
// Memory
//=========
always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock)
begin
if (i_wren_tmp == 1'b1)
if (ValidAddress(i_wraddress_tmp))
begin
if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) &&
(lpm_wraddress_control == "REGISTERED"))
begin
if (i_inclock == 1'b0)
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
else
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
end
always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp])
begin
if (i_rden_tmp == 1'b1)
i_q_tmp = (ValidAddress(i_rdaddress_tmp))
? mem_data[i_rdaddress_tmp]
: {lpm_width{1'bx}};
end
//=======
// Sync
//=======
always @(wraddress or i_wraddress_reg)
i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wraddress_reg
: wraddress;
always @(rdaddress or i_rdaddress_reg)
i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rdaddress_reg
: rdaddress;
always @(i_wren or i_wren_reg)
i_wren_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wren_reg
: i_wren;
always @(i_rden or i_rden_reg)
i_rden_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rden_reg
: i_rden;
always @(data or i_data_reg)
i_data_tmp = (lpm_indata == "REGISTERED")
? i_data_reg
: data;
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp;
endmodule // lpm_ram_dp
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_io
//
// Description : Parameterized RAM with a single I/O port megafunction
//
// Limitation : This megafunction is provided only for backward
// compatibility in Cyclone, Stratix, and Stratix GX designs;
// instead, Altera recommends using the altsyncram
// megafunction
//
// Results expected: Output of RAM content at bi-directional DIO.
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address );
// PARAMETER DECLARATION
parameter lpm_type = "lpm_ram_io";
parameter lpm_width = 1;
parameter lpm_widthad = 1;
parameter lpm_numwords = 1<< lpm_widthad;
parameter lpm_indata = "REGISTERED";
parameter lpm_address_control = "REGISTERED";
parameter lpm_outdata = "REGISTERED";
parameter lpm_file = "UNUSED";
parameter lpm_hint = "UNUSED";
parameter use_eab = "ON";
parameter intended_device_family = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock, outclock, we;
input memenab;
input outenab;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] dio;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_io;
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdio;
reg [lpm_widthad-1:0] paddress;
reg [lpm_widthad-1:0] paddress_tmp;
reg pwe;
reg [8*256:1] ram_initf;
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
wire i_outenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
tri1 outenab;
// INTERNAL BUF DECLARATION
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
buf (i_outenab, outenab);
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error: Address out of bound on RAM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// COMPONENT INSTANTIATIONS
LPM_MEMORY_INITIALIZATION mem ();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad))
||(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// Initialize input/output
pwe = 1'b0;
pdio = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
paddress_tmp = {lpm_widthad{1'b0}};
tmp_io = {lpm_width{1'b0}};
tmp_q = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
end
// ALWAYS CONSTRUCT BLOCK
always @(dio)
begin
if (lpm_indata == "UNREGISTERED")
pdio <= dio;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
pdio <= dio;
if (lpm_address_control == "REGISTERED")
begin
paddress <= address;
pwe <= we;
end
end
always @(pdio or paddress or pwe or i_memenab)
begin
if (ValidAddress(paddress))
begin
paddress_tmp <= paddress;
if (lpm_address_control == "UNREGISTERED")
if (pwe && i_memenab)
mem_data[paddress] <= pdio;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(read_data)
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= read_data;
end
always @(negedge i_inclock or pdio)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
if (pwe && i_memenab && (i_inclock == 1'b0))
mem_data[paddress] = pdio;
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "OFF") && pwe && i_memenab)
mem_data[paddress] <= pdio;
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
tmp_q <= mem_data[paddress];
end
always @(i_memenab or i_outenab or tmp_q)
begin
if (i_memenab && i_outenab)
tmp_io = tmp_q;
else if ((!i_memenab) || (i_memenab && (!i_outenab)))
tmp_io = {lpm_width{1'bz}};
end
// CONTINOUS ASSIGNMENT
assign dio = tmp_io;
assign read_data = mem_data[paddress_tmp];
endmodule // lpm_ram_io
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_rom
//
// Description : Parameterized ROM megafunction. This megafunction is provided
// only for backward compatibility in Cyclone, Stratix, and
// Stratix GX designs; instead, Altera recommends using the
// altsyncram megafunction.
//
// Limitation : This option is available for all Altera devices supported by
// the Quartus II software except MAX 3000 and MAX 7000 devices.
//
// Results expected: Output of memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_rom (
address, // Address input to the memory. (Required)
inclock, // Clock for input registers.
outclock, // Clock for output registers.
memenab, // Memory enable input.
q // Output of memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the q[] port. (Required)
parameter lpm_widthad = 1; // Width of the address[] port. (Required)
parameter lpm_numwords = 0; // Number of words stored in memory.
parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered.
parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered.
parameter lpm_file = ""; // Name of the memory file containing ROM initialization data
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_rom";
parameter lpm_hint = "UNUSED";
// LOCAL_PARAMETERS_BEGIN
parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords;
// LOCAL_PARAMETERS_END
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input memenab;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1];
reg [lpm_widthad-1:0] address_reg;
reg [lpm_width-1:0] tmp_q_reg;
reg [8*256:1] rom_initf;
// INTERNAL WIRE DECLARATION
wire [lpm_widthad-1:0] w_address;
wire [lpm_width-1:0] w_read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] address;
begin
ValidAddress = 1'b0;
if (^address == {lpm_widthad{1'bx}})
begin
$display("%d:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (address >= NUM_WORDS)
begin
$display("%d:Error: Address out of bound on ROM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize output
tmp_q_reg = {lpm_width{1'b0}};
address_reg = {lpm_widthad{1'b0}};
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((NUM_WORDS > (1 << lpm_widthad)) ||
(NUM_WORDS <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") &&
(lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1)
begin
$display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < NUM_WORDS; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the ROM
if ((lpm_file == "") || (lpm_file == "UNUSED"))
begin
$display("Warning: LPM_ROM must have data file for initialization.\n");
$display ("Time: %0t Instance: %m", $time);
end
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf);
$readmemh(rom_initf, mem_data);
end
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
address_reg <= address; // address port is registered
end
always @(w_address or w_read_data)
begin
if (ValidAddress(w_address))
begin
if (lpm_outdata == "UNREGISTERED")
// Load the output register with the contents of the memory location
// pointed to by address[].
tmp_q_reg <= w_read_data;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q_reg <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(w_address))
tmp_q_reg <= w_read_data;
else
tmp_q_reg <= {lpm_width{1'bx}};
end
end
// CONTINOUS ASSIGNMENT
assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address;
assign w_read_data = mem_data[w_address];
assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}};
endmodule // lpm_rom
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
module lpm_fifo ( data,
clock,
wrreq,
rdreq,
aclr,
sclr,
q,
usedw,
full,
empty );
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter lpm_type = "lpm_fifo";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input wrreq;
input rdreq;
input aclr;
input sclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output [lpm_widthu-1:0] usedw;
output full;
output empty;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
reg [lpm_width-1:0] tmp_data;
reg [lpm_widthu-1:0] count_id;
reg [lpm_widthu-1:0] read_id;
reg [lpm_widthu-1:0] write_id;
reg write_flag;
reg full_flag;
reg empty_flag;
reg [lpm_width-1:0] tmp_q;
reg [8*5:1] overflow_checking;
reg [8*5:1] underflow_checking;
reg [8*20:1] allow_rwcycle_when_full;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire valid_rreq;
wire valid_wreq;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display ("Error! LPM_WIDTH must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= 1)
begin
$display ("Error! LPM_NUMWORDS must be greater than or equal to 2.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
begin
$display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= (1 << (lpm_widthu - 1)))
begin
$display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if(overflow_checking == "")
overflow_checking = "ON";
else if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(underflow_checking == "")
underflow_checking = "ON";
else if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL");
if (allow_rwcycle_when_full == "")
allow_rwcycle_when_full = "OFF";
else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF"))
begin
$display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1<<lpm_widthu); i = i + 1)
begin
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
mem_data[i] <= {lpm_width{1'bx}};
else
mem_data[i] <= {lpm_width{1'b0}};
end
tmp_data <= 0;
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
tmp_q <= {lpm_width{1'bx}};
else
tmp_q <= {lpm_width{1'b0}};
write_flag <= 1'b0;
count_id <= 0;
read_id <= 0;
write_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr)
begin
if (aclr)
begin
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= {lpm_width{1'b0}};
end
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq && (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else if (sclr)
begin
if ((lpm_showahead == "ON") || (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else
begin
// Both WRITE and READ operations
if (valid_wreq && valid_rreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
empty_flag <= 1'b0;
if (allow_rwcycle_when_full == "OFF")
begin
full_flag <= 1'b0;
end
if (read_id >= ((1 << lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end
// WRITE operation only
else if (valid_wreq)
begin
tmp_data <= data;
empty_flag <= 1'b0;
write_flag <= 1'b1;
if (count_id >= (1 << lpm_widthu) - 1)
count_id <= 0;
else
count_id <= count_id + 1;
if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
full_flag <= 1'b1;
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id];
end
// READ operation only
else if (valid_rreq)
begin
full_flag <= 1'b0;
if (count_id <= 0)
count_id <= {lpm_widthu{1'b1}};
else
count_id <= count_id - 1;
if ((count_id == 1) && (full_flag == 1'b0))
empty_flag <= 1'b1;
if (read_id >= ((1<<lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end // if Both WRITE and READ operations
end // if aclr
end // @(posedge clock)
always @(negedge clock)
begin
if (write_flag)
begin
write_flag <= 1'b0;
mem_data[write_id] <= tmp_data;
if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
write_id <= 0;
else
write_id <= write_id + 1;
end
if ((lpm_showahead == "ON") && ($time > 0))
tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ?
tmp_data : mem_data[read_id];
end // @(negedge clock)
// CONTINOUS ASSIGNMENT
assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag;
assign valid_wreq = (overflow_checking == "OFF") ? wrreq :
(allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) :
wrreq && !full_flag;
assign q = tmp_q;
assign full = full_flag;
assign empty = empty_flag;
assign usedw = count_id;
endmodule // lpm_fifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_dffpipe
//
// Description : Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_dffpipe (d,
clock,
aclr,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] dffpipe [lpm_delay:0];
reg [lpm_width-1:0] q;
// LOCAL INTEGER DECLARATION
integer delay;
integer i;
// INITIAL CONSTRUCT BLOCK
initial
begin
delay <= lpm_delay - 1;
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr or posedge clock)
begin
if (aclr)
begin
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
else if (clock)
begin
if ((lpm_delay > 0) && ($time > 0))
begin
if (delay > 0)
begin
for (i = delay; i > 0; i = i - 1)
dffpipe[i] <= dffpipe[i - 1];
q <= dffpipe[delay - 1];
end
else
q <= d;
dffpipe[0] <= d;
end
end
end // @(posedge aclr or posedge clock)
always @(d)
begin
if (lpm_delay == 0)
q <= d;
end // @(d)
endmodule // lpm_fifo_dc_dffpipe
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_fefifo
//
// Description : Dual Clock FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_fefifo ( usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] usedw_in;
input wreq;
input rreq;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output empty;
output full;
// INTERNAL REGISTERS DECLARATION
reg [1:0] sm_empty;
reg lrreq;
reg i_empty;
reg i_full;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
// LOCAL INTEGER DECLARATION
integer almostfull;
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
begin
$display ("Error! LPM_MODE must be READ or WRITE.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
if (lpm_numwords >= 3)
almostfull <= lpm_numwords - 3;
else
almostfull <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
end // @(posedge aclr)
always @(posedge clock)
begin
if (i_underflow_checking == "OFF")
lrreq <= rreq;
else
lrreq <= rreq && ~i_empty;
if (~aclr && ($time > 0))
begin
if (lpm_mode == "READ")
begin
casex (sm_empty)
// state_empty
2'b00:
if (usedw_in != 0)
sm_empty <= 2'b01;
// state_non_empty
2'b01:
if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
sm_empty <= 2'b10;
// state_emptywait
2'b10:
if (usedw_in > 1)
sm_empty <= 2'b01;
else
sm_empty <= 2'b00;
default:
begin
$display ("Error! Invalid sm_empty state in read mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "READ")
else if (lpm_mode == "WRITE")
begin
casex (sm_empty)
// state_empty
2'b00:
if (wreq)
sm_empty <= 2'b01;
// state_one
2'b01:
if (!wreq)
sm_empty <= 2'b11;
// state_non_empty
2'b11:
if (wreq)
sm_empty <= 2'b01;
else if (usedw_in == 0)
sm_empty <= 2'b00;
default:
begin
$display ("Error! Invalid sm_empty state in write mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "WRITE")
if (~aclr && (usedw_in >= almostfull) && ($time > 0))
i_full <= 1'b1;
else
i_full <= 1'b0;
end // if (~aclr && $time > 0)
end // @(posedge clock)
always @(sm_empty)
begin
i_empty <= !sm_empty[0];
end
// @(sm_empty)
// CONTINOUS ASSIGNMENT
assign empty = i_empty;
assign full = i_full;
endmodule // lpm_fifo_dc_fefifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_async
//
// Description : Asynchronous Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_async ( data,
rdclk,
wrclk,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclk;
input wrclk;
input aclr;
input wrreq;
input rdreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
reg [lpm_width-1:0] i_data_tmp;
reg [lpm_widthu-1:0] i_rdptr;
reg [lpm_widthu-1:0] i_wrptr;
reg [lpm_widthu-1:0] i_wrptr_tmp;
reg i_rdenclock;
reg i_wren_tmp;
reg [lpm_widthu-1:0] i_wr_udwn;
reg [lpm_widthu-1:0] i_rd_udwn;
reg i_showahead_flag;
reg i_showahead_flag1;
reg [lpm_widthu:0] i_rdusedw;
reg [lpm_widthu-1:0] i_wrusedw;
reg [lpm_width-1:0] i_q_tmp;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
reg [8*10:1] use_eab;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire w_rden;
wire w_wren;
wire w_rdempty;
wire w_wrempty;
wire w_rdfull;
wire w_wrfull;
wire [lpm_widthu-1:0] w_rdptrrg;
wire [lpm_widthu-1:0] w_wrdelaycycle;
wire [lpm_widthu-1:0] w_ws_nbrp;
wire [lpm_widthu-1:0] w_rs_nbwp;
wire [lpm_widthu-1:0] w_ws_dbrp;
wire [lpm_widthu-1:0] w_rs_dbwp;
wire [lpm_widthu-1:0] w_rd_dbuw;
wire [lpm_widthu-1:0] w_wr_dbuw;
wire [lpm_widthu-1:0] w_rdusedw;
wire [lpm_widthu-1:0] w_wrusedw;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
begin
$display ("Error! lpm_showahead must be ON or OFF.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
use_eab = eva.GET_PARAMETER_VALUE(lpm_hint, "USE_EAB");
if(use_eab == "")
use_eab = "ON";
else if ((use_eab != "ON") && (use_eab != "OFF"))
begin
$display ("Error! USE_EAB must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
mem_data[i] <= 0;
i_data_tmp <= 0;
i_rdptr <= 0;
i_wrptr <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
i_wr_udwn <= 0;
i_rd_udwn <= 0;
i_rdusedw <= 0;
i_wrusedw <= 0;
i_q_tmp <= 0;
end
// COMPONENT INSTANTIATIONS
// Delays & DFF Pipes
lpm_fifo_dc_dffpipe DP_RDPTR_D (
.d (i_rdptr),
.clock (i_rdenclock),
.aclr (aclr),
.q (w_rdptrrg));
lpm_fifo_dc_dffpipe DP_WRPTR_D (
.d (i_wrptr),
.clock (wrclk),
.aclr (aclr),
.q (w_wrdelaycycle));
defparam
DP_RDPTR_D.lpm_delay = 0,
DP_RDPTR_D.lpm_width = lpm_widthu,
DP_WRPTR_D.lpm_delay = 1,
DP_WRPTR_D.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WS_NBRP (
.d (w_rdptrrg),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_nbrp));
lpm_fifo_dc_dffpipe DP_RS_NBWP (
.d (w_wrdelaycycle),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_nbwp));
lpm_fifo_dc_dffpipe DP_WS_DBRP (
.d (w_ws_nbrp),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_dbrp));
lpm_fifo_dc_dffpipe DP_RS_DBWP (
.d (w_rs_nbwp),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_dbwp));
defparam
DP_WS_NBRP.lpm_delay = wrsync_delaypipe,
DP_WS_NBRP.lpm_width = lpm_widthu,
DP_RS_NBWP.lpm_delay = rdsync_delaypipe,
DP_RS_NBWP.lpm_width = lpm_widthu,
DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe
DP_WS_DBRP.lpm_width = lpm_widthu,
DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe
DP_RS_DBWP.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WRUSEDW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wrusedw));
lpm_fifo_dc_dffpipe DP_RDUSEDW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rdusedw));
lpm_fifo_dc_dffpipe DP_WR_DBUW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wr_dbuw));
lpm_fifo_dc_dffpipe DP_RD_DBUW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rd_dbuw));
defparam
DP_WRUSEDW.lpm_delay = delay_wrusedw,
DP_WRUSEDW.lpm_width = lpm_widthu,
DP_RDUSEDW.lpm_delay = delay_rdusedw,
DP_RDUSEDW.lpm_width = lpm_widthu,
DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe
DP_WR_DBUW.lpm_width = lpm_widthu,
DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe
DP_RD_DBUW.lpm_width = lpm_widthu;
// Empty/Full
lpm_fifo_dc_fefifo WR_FE (
.usedw_in (w_wr_dbuw),
.wreq (wrreq),
.rreq (rdreq),
.clock (wrclk),
.aclr (aclr),
.empty (w_wrempty),
.full (w_wrfull));
lpm_fifo_dc_fefifo RD_FE (
.usedw_in (w_rd_dbuw),
.rreq (rdreq),
.wreq(wrreq),
.clock (rdclk),
.aclr (aclr),
.empty (w_rdempty),
.full (w_rdfull));
defparam
WR_FE.lpm_widthad = lpm_widthu,
WR_FE.lpm_numwords = lpm_numwords,
WR_FE.underflow_checking = underflow_checking,
WR_FE.overflow_checking = overflow_checking,
WR_FE.lpm_mode = "WRITE",
WR_FE.lpm_hint = lpm_hint,
RD_FE.lpm_widthad = lpm_widthu,
RD_FE.lpm_numwords = lpm_numwords,
RD_FE.underflow_checking = underflow_checking,
RD_FE.overflow_checking = overflow_checking,
RD_FE.lpm_mode = "READ",
RD_FE.lpm_hint = lpm_hint;
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
i_rdptr <= 0;
i_wrptr <= 0;
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF"))
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end // @(posedge aclr)
// FIFOram
always @(posedge wrclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
i_data_tmp <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
end
else if (wrclk && ($time > 0))
begin
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= w_wren;
if (w_wren)
begin
if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (i_overflow_checking == "OFF")))
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= 0;
if (use_eab == "OFF")
begin
mem_data[i_wrptr] <= data;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end
end
end // @(posedge wrclk)
always @(negedge wrclk)
begin
if ((~wrclk && (use_eab == "ON")) && ($time > 0))
begin
if (i_wren_tmp)
begin
mem_data[i_wrptr_tmp] <= i_data_tmp;
end
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end // @(negedge wrclk)
always @(posedge rdclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end
else if (rdclk && w_rden && ($time > 0))
begin
if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (i_underflow_checking == "OFF")))
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= 0;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
else
i_q_tmp <= mem_data[i_rdptr];
end
end // @(rdclk)
always @(posedge i_showahead_flag)
begin
i_q_tmp <= mem_data[i_rdptr];
i_showahead_flag1 <= 1'b0;
end // @(posedge i_showahead_flag)
always @(i_showahead_flag1)
begin
i_showahead_flag <= i_showahead_flag1;
end // @(i_showahead_flag1)
// Delays & DFF Pipes
always @(negedge rdclk)
begin
i_rdenclock <= 0;
end // @(negedge rdclk)
always @(posedge rdclk)
begin
if (w_rden)
i_rdenclock <= 1;
end // @(posedge rdclk)
always @(i_wrptr or w_ws_dbrp)
begin
i_wr_udwn <= i_wrptr - w_ws_dbrp;
end // @(i_wrptr or w_ws_dbrp)
always @(i_rdptr or w_rs_dbwp)
begin
i_rd_udwn <= w_rs_dbwp - i_rdptr;
end // @(i_rdptr or w_rs_dbwp)
// CONTINOUS ASSIGNMENT
assign w_rden = (i_underflow_checking == "OFF") ? rdreq : rdreq && !w_rdempty;
assign w_wren = (i_overflow_checking == "OFF") ? wrreq : wrreq && !w_wrfull;
assign q = i_q_tmp;
assign wrfull = w_wrfull;
assign rdfull = w_rdfull;
assign wrempty = w_wrempty;
assign rdempty = w_rdempty;
assign wrusedw = w_wrusedw;
assign rdusedw = w_rdusedw;
endmodule // lpm_fifo_dc_async
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc (data,
rdclock,
wrclock,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "";
parameter lpm_type = "lpm_fifo_dc";
// LOCAL PARAMETER DECLARATION
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclock;
input wrclock;
input aclr;
input rdreq;
input wrreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// internal reg
wire w_rdfull_s;
wire w_wrfull_s;
wire w_rdempty_s;
wire w_wrempty_s;
wire w_rdfull_a;
wire w_wrfull_a;
wire w_rdempty_a;
wire w_wrempty_a;
wire [lpm_widthu-1:0] w_rdusedw_s;
wire [lpm_widthu-1:0] w_wrusedw_s;
wire [lpm_widthu-1:0] w_rdusedw_a;
wire [lpm_widthu-1:0] w_wrusedw_a;
wire [lpm_width-1:0] w_q_s;
wire [lpm_width-1:0] w_q_a;
wire i_aclr;
// INTERNAL TRI DECLARATION
tri0 aclr;
buf (i_aclr, aclr);
// COMPONENT INSTANTIATIONS
lpm_fifo_dc_async ASYNC (
.data (data),
.rdclk (rdclock),
.wrclk (wrclock),
.aclr (i_aclr),
.rdreq (rdreq),
.wrreq (wrreq),
.rdfull (w_rdfull_a),
.wrfull (w_wrfull_a),
.rdempty (w_rdempty_a),
.wrempty (w_wrempty_a),
.rdusedw (w_rdusedw_a),
.wrusedw (w_wrusedw_a),
.q (w_q_a) );
defparam
ASYNC.lpm_width = lpm_width,
ASYNC.lpm_widthu = lpm_widthu,
ASYNC.lpm_numwords = lpm_numwords,
ASYNC.delay_rdusedw = delay_rdusedw,
ASYNC.delay_wrusedw = delay_wrusedw,
ASYNC.rdsync_delaypipe = rdsync_delaypipe,
ASYNC.wrsync_delaypipe = wrsync_delaypipe,
ASYNC.lpm_showahead = lpm_showahead,
ASYNC.underflow_checking = underflow_checking,
ASYNC.overflow_checking = overflow_checking,
ASYNC.lpm_hint = lpm_hint;
// CONTINOUS ASSIGNMENT
assign rdfull = w_rdfull_a;
assign wrfull = w_wrfull_a;
assign rdempty = w_rdempty_a;
assign wrempty = w_wrempty_a;
assign rdusedw = w_rdusedw_a;
assign wrusedw = w_wrusedw_a;
assign q = w_q_a;
endmodule // lpm_fifo_dc
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inpad (
pad,
result
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_inpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] pad;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(pad)
begin
result = pad;
end
endmodule // lpm_inpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_outpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_outpad (
data,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_outpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] pad;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
pad = data;
end
endmodule // lpm_outpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bipad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bipad (
data,
enable,
result,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bipad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or pad or enable)
begin
if (enable == 1)
begin
result = {lpm_width{1'bz}};
end
else if (enable == 0)
begin
result = pad;
end
end
// CONTINOUS ASSIGNMENT
assign pad = (enable == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bipad
// END OF MODULE
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430_fpga;
//
// Wire & Register definition
//------------------------------
// Clock & Reset
reg CLK_40MHz;
reg CLK_66MHz;
reg CLK_100MHz;
reg USER_RESET;
// Slide Switches
reg SW4;
reg SW3;
reg SW2;
reg SW1;
// LEDs
wire LED4;
wire LED3;
wire LED2;
wire LED1;
// UART
reg UART_RXD;
wire UART_TXD;
// UART
wire PMOD1_P1;
reg PMOD1_P4;
// Core debug signals
wire [8*32-1:0] omsp0_i_state;
wire [8*32-1:0] omsp0_e_state;
wire [31:0] omsp0_inst_cycle;
wire [8*32-1:0] omsp0_inst_full;
wire [31:0] omsp0_inst_number;
wire [15:0] omsp0_inst_pc;
wire [8*32-1:0] omsp0_inst_short;
wire [8*32-1:0] omsp1_i_state;
wire [8*32-1:0] omsp1_e_state;
wire [31:0] omsp1_inst_cycle;
wire [8*32-1:0] omsp1_inst_full;
wire [31:0] omsp1_inst_number;
wire [15:0] omsp1_inst_pc;
wire [8*32-1:0] omsp1_inst_short;
// Testbench variables
integer i;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers_omsp0.v"
`include "registers_omsp1.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Program Memory
//------------------------------
initial
begin
// Read memory file
#10 $readmemh("./pmem.mem", pmem);
// Update Xilinx memory banks
for (i=0; i<8192; i=i+1)
begin
dut.ram_16x8k_dp_pmem_shared.ram_dp_inst.mem[i] = pmem[i];
end
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
CLK_40MHz = 1'b0;
forever #12.5 CLK_40MHz <= ~CLK_40MHz; // 40 MHz
end
initial
begin
CLK_66MHz = 1'b0;
forever #7.57 CLK_66MHz <= ~CLK_66MHz; // 66 MHz
end
initial
begin
CLK_100MHz = 1'b0;
forever #5 CLK_100MHz <= ~CLK_100MHz; // 100 MHz
end
initial
begin
USER_RESET = 1'b0;
#100 USER_RESET = 1'b1;
#600 USER_RESET = 1'b0;
end
//
// Global initialization
//------------------------------
initial
begin
error = 0;
stimulus_done = 1;
SW4 = 1'b0; // Slide Switches
SW3 = 1'b0;
SW2 = 1'b0;
SW1 = 1'b0;
UART_RXD = 1'b1; // UART
PMOD1_P4 = 1'b1;
end
//
// openMSP430 FPGA Instance
//----------------------------------
openMSP430_fpga dut (
//----------------------------------------------
// User Reset Push Button
//----------------------------------------------
.USER_RESET (USER_RESET),
//----------------------------------------------
// Micron N25Q128 SPI Flash
// This is a Multi-I/O Flash. Several pins
// have dual purposes depending on the mode.
//----------------------------------------------
.SPI_SCK (),
.SPI_CS_n (),
.SPI_MOSI_MISO0 (),
.SPI_MISO_MISO1 (),
.SPI_Wn_MISO2 (),
.SPI_HOLDn_MISO3 (),
//----------------------------------------------
// TI CDCE913 Triple-Output PLL Clock Chip
// Y1: 40 MHz, USER_CLOCK can be used as
// external configuration clock
// Y2: 66.667 MHz
// Y3: 100 MHz
//----------------------------------------------
.USER_CLOCK (CLK_40MHz),
.CLOCK_Y2 (CLK_66MHz),
.CLOCK_Y3 (CLK_100MHz),
//----------------------------------------------
// The following oscillator is not populated
// in production but the footprint is compatible
// with the Maxim DS1088LU
//----------------------------------------------
.BACKUP_CLK (1'b0),
//----------------------------------------------
// User DIP Switch x4
//----------------------------------------------
.GPIO_DIP1 (SW1),
.GPIO_DIP2 (SW2),
.GPIO_DIP3 (SW3),
.GPIO_DIP4 (SW4),
//----------------------------------------------
// User LEDs
//----------------------------------------------
.GPIO_LED1 (LED1),
.GPIO_LED2 (LED2),
.GPIO_LED3 (LED3),
.GPIO_LED4 (LED4),
//----------------------------------------------
// Silicon Labs CP2102 USB-to-UART Bridge Chip
//----------------------------------------------
.USB_RS232_RXD (UART_RXD),
.USB_RS232_TXD (UART_TXD),
//----------------------------------------------
// Texas Instruments CDCE913 programming port
//----------------------------------------------
.SCL (),
.SDA (),
//----------------------------------------------
// Micron MT46H32M16LFBF-5 LPDDR
//----------------------------------------------
// Addresses
.LPDDR_A0 (),
.LPDDR_A1 (),
.LPDDR_A2 (),
.LPDDR_A3 (),
.LPDDR_A4 (),
.LPDDR_A5 (),
.LPDDR_A6 (),
.LPDDR_A7 (),
.LPDDR_A8 (),
.LPDDR_A9 (),
.LPDDR_A10 (),
.LPDDR_A11 (),
.LPDDR_A12 (),
.LPDDR_BA0 (),
.LPDDR_BA1 (),
// Data
.LPDDR_DQ0 (),
.LPDDR_DQ1 (),
.LPDDR_DQ2 (),
.LPDDR_DQ3 (),
.LPDDR_DQ4 (),
.LPDDR_DQ5 (),
.LPDDR_DQ6 (),
.LPDDR_DQ7 (),
.LPDDR_DQ8 (),
.LPDDR_DQ9 (),
.LPDDR_DQ10 (),
.LPDDR_DQ11 (),
.LPDDR_DQ12 (),
.LPDDR_DQ13 (),
.LPDDR_DQ14 (),
.LPDDR_DQ15 (),
.LPDDR_LDM (),
.LPDDR_UDM (),
.LPDDR_LDQS (),
.LPDDR_UDQS (),
// Clock
.LPDDR_CK_N (),
.LPDDR_CK_P (),
.LPDDR_CKE (),
// Control
.LPDDR_CAS_n (),
.LPDDR_RAS_n (),
.LPDDR_WE_n (),
.LPDDR_RZQ (),
//----------------------------------------------
// National Semiconductor DP83848J 10/100 Ethernet PHY
// Pull-ups on RXD are necessary to set the PHY AD to 11110b.
// Must keep the PHY from defaulting to PHY AD = 00000b
// because this is Isolate Mode
//----------------------------------------------
.ETH_COL (1'b0),
.ETH_CRS (1'b0),
.ETH_MDC (),
.ETH_MDIO (),
.ETH_RESET_n (),
.ETH_RX_CLK (1'b0),
.ETH_RX_D0 (1'b0),
.ETH_RX_D1 (1'b0),
.ETH_RX_D2 (1'b0),
.ETH_RX_D3 (1'b0),
.ETH_RX_DV (1'b0),
.ETH_RX_ER (1'b0),
.ETH_TX_CLK (1'b0),
.ETH_TX_D0 (),
.ETH_TX_D1 (),
.ETH_TX_D2 (),
.ETH_TX_D3 (),
.ETH_TX_EN (),
//----------------------------------------------
// Peripheral Modules (PMODs) and GPIO
// https://www.digilentinc.com/PMODs
//----------------------------------------------
// Connector J5
.PMOD1_P1 (PMOD1_P1), // Serial Debug Interface TX
.PMOD1_P2 (),
.PMOD1_P3 (),
.PMOD1_P4 (PMOD1_P4), // Serial Debug Interface RX
.PMOD1_P7 (),
.PMOD1_P8 (),
.PMOD1_P9 (),
.PMOD1_P10 (),
// Connector J4
.PMOD2_P1 (),
.PMOD2_P2 (),
.PMOD2_P3 (),
.PMOD2_P4 (),
.PMOD2_P7 (),
.PMOD2_P8 (),
.PMOD2_P9 (),
.PMOD2_P10 ()
);
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_omsp0 (
// OUTPUTs
.e_state (omsp0_e_state), // Execution state
.i_state (omsp0_i_state), // Instruction fetch state
.inst_cycle (omsp0_inst_cycle), // Cycle number within current instruction
.inst_full (omsp0_inst_full), // Currently executed instruction (full version)
.inst_number (omsp0_inst_number), // Instruction number since last system reset
.inst_pc (omsp0_inst_pc), // Instruction Program counter
.inst_short (omsp0_inst_short), // Currently executed instruction (short version)
// INPUTs
.core_select (1'b0) // Core selection
);
msp_debug msp_debug_omsp1 (
// OUTPUTs
.e_state (omsp1_e_state), // Execution state
.i_state (omsp1_i_state), // Instruction fetch state
.inst_cycle (omsp1_inst_cycle), // Cycle number within current instruction
.inst_full (omsp1_inst_full), // Currently executed instruction (full version)
.inst_number (omsp1_inst_number), // Instruction number since last system reset
.inst_pc (omsp1_inst_pc), // Instruction Program counter
.inst_short (omsp1_inst_short), // Currently executed instruction (short version)
// INPUTs
.core_select (1'b1) // Core selection
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
#500000;
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
end
initial // Normal end of test
begin
@(omsp0_inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule
|
module ghrd_10as066n2_emif_hps (
input wire global_reset_n, // global_reset_reset_sink.reset_n
input wire [4095:0] hps_to_emif, // hps_emif_conduit_end.hps_to_emif
output wire [4095:0] emif_to_hps, // .emif_to_hps
input wire [1:0] hps_to_emif_gp, // .gp_to_emif
output wire [0:0] emif_to_hps_gp, // .emif_to_gp
output wire [0:0] mem_ck, // mem_conduit_end.mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [16:0] mem_a, // .mem_a
output wire [0:0] mem_act_n, // .mem_act_n
output wire [1:0] mem_ba, // .mem_ba
output wire [0:0] mem_bg, // .mem_bg
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [0:0] mem_odt, // .mem_odt
output wire [0:0] mem_reset_n, // .mem_reset_n
output wire [0:0] mem_par, // .mem_par
input wire [0:0] mem_alert_n, // .mem_alert_n
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dbi_n, // .mem_dbi_n
input wire oct_rzqin, // oct_conduit_end.oct_rzqin
input wire pll_ref_clk // pll_ref_clk_clock_sink.clk
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
|
module SPI_FSM (
input Reset_n_i,
input Clk_i,
input SPI_FSM_Start,
input SPI_Transmission_i,
output reg MAX6682CS_n_o,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg SPI_FSM_Done,
input [7:0] SPI_Data_i,
output reg [7:0] Byte0,
output reg [7:0] Byte1
);
localparam stIdleSPI = 3'b000;
localparam stWrite1 = 3'b001;
localparam stWrite2 = 3'b010;
localparam stWait = 3'b011;
localparam stRead1 = 3'b100;
localparam stRead2 = 3'b101;
localparam stPause = 3'b110;
reg [2:0] SPI_FSM_State;
reg [2:0] SPI_FSM_NextState;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// SPI FSM //////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdleSPI;
end
else
begin // rising clock edge
SPI_FSM_State <= SPI_FSM_NextState;
end
end
// Note: There is a possible infinite zero-delay loop between this always-
// block and that of the SensorFSM with SPI_FSM_Start and SPI_FSM_Done.
// Previously (and in the VHDL code) SPI_FSM_Done is set '1' as default
// value and then set to '0' in nearly each case below, e.g. in stIdleSPI.
// In the simulation, this changes the value of that signal each time this
// always-block is executed, which then triggers the below always-block too.
// Therefore this code was changed to set the default value '0' and only set
// the signal '1' in stRead2 and stPause.
always @(SPI_FSM_State, SPI_FSM_Start, SPI_Transmission_i)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
MAX6682CS_n_o = 1'b1;
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
SPI_FSM_Done = 1'b0;
// next state and output logic
case (SPI_FSM_State)
stIdleSPI: begin
if (SPI_FSM_Start == 1'b1)
begin
SPI_FSM_NextState = stWrite1;
MAX6682CS_n_o = 1'b0;
SPI_Write_o = 1'b1;
end
end
stWrite1: begin
SPI_FSM_NextState = stWrite2;
MAX6682CS_n_o = 1'b0;
SPI_Write_o = 1'b1;
end
stWrite2: begin
SPI_FSM_NextState = stWait;
MAX6682CS_n_o = 1'b0;
end
stWait: begin
MAX6682CS_n_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead1;
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
end
end
stRead1: begin
SPI_FSM_NextState = stRead2;
MAX6682CS_n_o = 1'b0;
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
end
stRead2: begin
SPI_FSM_Done = 1'b1;
// be really quick here and allow to immediately issue a new transfer
if (SPI_FSM_Start == 1'b1)
begin
SPI_FSM_NextState = stWrite1;
MAX6682CS_n_o = 1'b0;
SPI_Write_o = 1'b1;
end
else
begin
SPI_FSM_NextState = stIdleSPI;
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0 <= 8'd0;
Byte1 <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0 <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1 <= SPI_Data_i;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$P_pp$PKG$s: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$s (
Q ,
D ,
CLK ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_BLACKBOX_V
`define SKY130_FD_SC_LP__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_4_V
`define SKY130_FD_SC_LS__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_4_V
|
module lc3_pipeline_stage1(
input reset,
input clk,
input stall,
input [5:0] state,
input [15:0] I_inst,
input [15:0] I_npc,
input [15:0] I_Forcast_pc,
input [19:0] I_WBctl,
input [19:0] fsm_regctl,
output reg [15:0] O_npc,
output reg [19:0] O_SR1,
output reg [19:0] O_SR2,
output reg [19:0] O_DR, //in this O_DR a data was passed to the later stages ,it can be data to be written to memory or written back to regfile
output reg [1:0] O_WBtype, //this indicate where the writeback data is from :passed data or pipeline result
output reg [1:0] O_ALUopr,
output reg O_SetCC,
output reg [4:0] O_BRtype,
output reg [15:0] O_Forcast_pc,
output reg [2:0] O_Memtype,
output reg [1:0] O_Errtype,
output [15:0] SP
);
reg [15:0] REGin;
reg [2:0] DR;
reg LD_REG;
reg [2:0] SR1,SR2;
wire [15:0] SR1out,SR2out,SR1out_tmp,SR2out_tmp;
LC3_REGFILE rf0(
.clk(clk),
.REGin(REGin),
.DR(DR),
.LD_REG(LD_REG),
.SR1(SR1),
.SR2(SR2),
.SR1out(SR1out_tmp),
.SR2out(SR2out_tmp),
.SP(SP)
);
assign SR1out= ( (LD_REG&(SR1==DR))?REGin:SR1out_tmp);
assign SR2out= ( (LD_REG&(SR2==DR))?REGin:SR2out_tmp);
always@(*) begin
if(fsm_regctl[19]) begin
{LD_REG,DR,REGin}=fsm_regctl;
end else
{LD_REG,DR,REGin}=I_WBctl;
end
reg [15:0] IR;
always@(negedge clk or posedge reset) begin
if(reset) begin
//seems nothing to do
end else begin
if(!stall) begin
IR<=I_inst;
O_npc<=I_npc;
O_Forcast_pc<=I_Forcast_pc;
end
end
end
always@(*) begin
case(IR[15:12])
4'h1:begin //ADD
SR1 = IR[8:6];
SR2 = IR[2:0];
O_SR1 = {1'b1,IR[8:6],SR1out};
if(IR[5]==0)
O_SR2 = {1'b1,IR[2:0],SR2out};
else
O_SR2 = {1'b0,IR[2:0],{11{IR[4]}},IR[4:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b00;
O_SetCC = 1;
O_BRtype = 5'b00xxx;
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'h5:begin //AND
SR1 = IR[8:6];
SR2 = IR[2:0];
O_SR1 = {1'b1,IR[8:6],SR1out};
if(IR[5]==0)
O_SR2 = {1'b1,IR[2:0],SR2out};
else
O_SR2 = {1'b0,IR[2:0],{11{IR[4]}},IR[4:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b01;
O_SetCC = 1;
O_BRtype = 5'b00xxx;
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'h9:begin //NOT
SR1 = IR[8:6];
SR2 = 3'bxxx;
O_SR1 = {1'b1,IR[8:6],SR1out};
O_SR2 = {1'b0,18'bx};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b10;
O_SetCC = 1;
O_BRtype = 5'b00xxx;
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'hd:begin //UND
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,18'bx};
O_SR2 = {1'b0,18'bx};
O_DR = {1'b0,18'bx};
O_WBtype = 2'b0x;
O_ALUopr = 2'bxx;
O_SetCC = 0;
O_BRtype = 5'b00xxx;
O_Memtype= 3'b0xx;
O_Errtype= 2'b11; //UND INST EXCEPTION
end
4'h0:begin //BR
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b0,3'bxxx,16'bxxx};
O_WBtype = 2'b0x;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b01,IR[11:9]};
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'hc:begin //JMP RET
SR1 = IR[8:6];
SR2 = 3'bxxx;
O_SR1 = {1'b1,IR[8:6],SR1out};
O_SR2 = {1'b0,3'bxxx,16'b0};
O_DR = {1'b0,19'bx};
O_WBtype = 2'b0x;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b10,3'bxxx};
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'h4:begin //JSR JSRR
SR1 = IR[8:6];
SR2 = 3'bxxx;
if(IR[11]==1) begin
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{5{IR[10]}},IR[10:0]};
end else begin
O_SR1 = {1'b1,IR[8:6],SR1out};
O_SR2 = {1'b0,3'bxxx,16'b0};
end
O_DR = {1'b0,3'b111,O_npc};
O_WBtype = 2'b11;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b10,3'bxxx};
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'h8:begin //RTI
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,19'bxxx};
O_SR2 = {1'b0,19'bxxx};
O_DR = {1'b0,19'bxxx};
O_WBtype = 2'b0x;
O_ALUopr = 2'bxx;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b0xx;
O_Errtype= 2'b10;
end
4'he:begin //LEA
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b00;
O_SetCC = 1;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b0xx;
O_Errtype= 2'b00;
end
4'h2:begin //LD
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b100;
O_Errtype= 2'b00;
end
4'ha:begin //LDI
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b110;
O_Errtype= 2'b00;
end
4'h6:begin //LDR
SR1 = IR[8:6];
SR2 = 3'bxxx;
O_SR1 = {1'b1,IR[8:6],SR1out};
O_SR2 = {1'b0,3'bxxx,{10{IR[5]}},IR[5:0]};
O_DR = {1'b0,IR[11:9],16'bx};
O_WBtype = 2'b10;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b100;
O_Errtype= 2'b00;
end
4'h3:begin //ST
SR1 = 3'bxxx;
SR2 = IR[11:9];
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b1,IR[11:9],SR2out};
O_WBtype = 2'b0x;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b101;
O_Errtype= 2'b00;
end
4'hb:begin //STI
SR1 = 3'bxxx;
SR2 = IR[11:9];
O_SR1 = {1'b0,3'bxxx,O_npc};
O_SR2 = {1'b0,3'bxxx,{7{IR[8]}},IR[8:0]};
O_DR = {1'b1,IR[11:9],SR2out};
O_WBtype = 2'b0x;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b111;
O_Errtype= 2'b00;
end
4'h7:begin //STR
SR1 = IR[8:6];
SR2 = IR[11:9];
O_SR1 = {1'b1,IR[8:6],SR1out};
O_SR2 = {1'b0,3'bxxx,{10{IR[5]}},IR[5:0]};
O_DR = {1'b1,IR[11:9],SR2out};
O_WBtype = 2'b0x;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b101;
O_Errtype= 2'b00;
end
4'hf:begin //TRAP
SR1 = 3'bxxx;
SR2 = 3'bxxx;
O_SR1 = {1'b0,3'bxxx,8'b0,IR[7:0]};
O_SR2 = {1'b0,3'bxxx,16'b0};
O_DR = {1'b0,3'b111,O_npc};
O_WBtype = 2'b11;
O_ALUopr = 2'b00;
O_SetCC = 0;
O_BRtype = {2'b00,3'bxxx};
O_Memtype= 3'b0xx;
O_Errtype= 2'b01;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:image_capture_manager:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_image_capture_manager_0_0 (
image_capture_enabled,
clear_memory,
reset,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
output wire image_capture_enabled;
output wire clear_memory;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
output wire reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
image_capture_manager #(
.START_IMAGE_CAPTURE_COMMAND(1),
.STOP_IMAGE_CAPTURE_COMMAND(2),
.RESET_IMAGE_CAPTURE_COMMAND(3),
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.image_capture_enabled(image_capture_enabled),
.clear_memory(clear_memory),
.reset(reset),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 74941
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 74941;
parameter REF_CLOCK_TICK_IN_PS = 30303;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
`timescale 1ns / 1ps
`define POP 2'b01
`define PUSH 2'b10
`define DO_NOTHING 2'b00
`define INVALID 2'b11
`define DATA_VALID 1'b1
`define DATA_INVALID 1'b0
`define LIFO_FULL 1'b1
`define LIFO_NOT_FULL 1'b0
`define LIFO_EMPTY 1'b1
`define LIFO_NOT_EMPTY 1'b0
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:25:36 03/26/2015
// Design Name:
// Module Name: lifo_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lifo_top(
data_out, empty_flag, full_flag,
vector_in, reset,
clk
);
parameter DATA_WIDTH = 4;
parameter NUM_ENTRIES = 4;
parameter OPCODE_WIDTH = 2;
parameter LINE_WIDTH = DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
parameter INITIAL_VALUE = 'b0;
parameter NUM_ENTRIES_BIT = `LOG2(NUM_ENTRIES);
output reg [DATA_WIDTH-1:0]data_out;
output reg empty_flag;
output reg full_flag;
input [OPCODE_WIDTH+DATA_WIDTH-1:0]vector_in;
input reset;
input clk;
reg [DATA_WIDTH-1:0]lifo_data[NUM_ENTRIES-1:0];
reg [NUM_ENTRIES-1:0]lifo_valid_invalid_bit;
reg [OPCODE_WIDTH-1:0]control_in; // control bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]data_in; // data bits for the module obtained from the input vector
reg [NUM_ENTRIES_BIT-1:0]lifo_head_pos;
reg [NUM_ENTRIES_BIT-1:0]lifo_tail_pos;
reg [NUM_ENTRIES_BIT-1:0]loop_variable;
always@(posedge clk)
begin
if(reset)
begin
data_out = INITIAL_VALUE;
lifo_head_pos = INITIAL_VALUE;
lifo_tail_pos = INITIAL_VALUE;
loop_variable = INITIAL_VALUE;
control_in = INITIAL_VALUE;
data_in = INITIAL_VALUE;
lifo_valid_invalid_bit = INITIAL_VALUE;
empty_flag = `LIFO_NOT_EMPTY;
full_flag = `LIFO_NOT_FULL;
end else
begin
// if the tail and head are at the same location
if(lifo_head_pos == INITIAL_VALUE && lifo_tail_pos == INITIAL_VALUE)
begin
// if INVALID, fifo empty
// $display("INVALID, EMPTY");
empty_flag = `LIFO_EMPTY;
full_flag = `LIFO_NOT_FULL;
end else
begin
if(lifo_head_pos == NUM_ENTRIES-1 && lifo_tail_pos == NUM_ENTRIES-1)
begin
// else, fifo full
// $display("VALID, FULL");
empty_flag = `LIFO_NOT_EMPTY;
full_flag = `LIFO_FULL;
end else
begin
// $display("DIFFERENT LOCATIONS");
empty_flag = `LIFO_EMPTY;
full_flag = `LIFO_NOT_FULL;
end
end
// $display("lifo_head_pos:%d, lifo_tail_pos:%d, empty_flag:%d, full_flag:%d", lifo_head_pos, lifo_tail_pos, empty_flag,full_flag);
control_in = vector_in[LINE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH];
data_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-DATA_WIDTH];
// $display("control: %d,data_in: %d",control_in, data_in);
case(control_in)
`POP:
begin
// $display("POP");
if(lifo_valid_invalid_bit[lifo_tail_pos] == `DATA_VALID)
begin
data_out = lifo_data[lifo_tail_pos];
lifo_valid_invalid_bit[lifo_tail_pos] = `DATA_INVALID;
if(lifo_tail_pos == INITIAL_VALUE)
begin
lifo_tail_pos = INITIAL_VALUE;
lifo_head_pos = lifo_head_pos - 1'b1;
end else
begin
if(empty_flag == `LIFO_NOT_EMPTY && full_flag == `LIFO_FULL)
lifo_tail_pos = lifo_tail_pos - 1'b1;
else begin
lifo_tail_pos = lifo_tail_pos - 1'b1;
lifo_head_pos = lifo_head_pos - 1'b1;
end
end
end else
begin
data_out = 'bx;
end
end
`PUSH:
begin
// $display("PUSH");
if(empty_flag == `LIFO_EMPTY && full_flag == `LIFO_NOT_FULL)
begin
lifo_data[lifo_head_pos] = data_in;
lifo_valid_invalid_bit[lifo_head_pos] = `DATA_VALID;
if(lifo_head_pos == NUM_ENTRIES-1)
begin
lifo_tail_pos = lifo_tail_pos + 1'b1;;
lifo_head_pos = NUM_ENTRIES-1;
end else begin
lifo_tail_pos = lifo_head_pos;
lifo_head_pos = lifo_head_pos + 1'b1;
end
end
// else
// $display("CACHE FULL, empty_flag:%d, full_flag:%d",empty_flag,full_flag);
end
// `INVALID: $display("INVLAID");
// `DO_NOTHING:
// begin
// repeat(NUM_ENTRIES)
// begin
// $display("loop_variable:%d, fifo_valid_invalid_bit:%d, fifo_data:%d", loop_variable, lifo_valid_invalid_bit[loop_variable], lifo_data[loop_variable]);
// loop_variable = loop_variable + 1'b1;
// end
// end
default: data_out = 'bx;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s4s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s4s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Tue Oct 25 02:12:16 2016
// Host : jorge-pc running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -mode funcsim -nolib -force -file
// /home/jorge/Documents/1Proyectos_TesisdeGraduacion_ASIC/my_sourcefiles/Source_Files/Multipliers/Karatsubas/Karatsubas.sim/sim_1/synth/func/tb_multiplier_func_synth.v
// Design : Recursive_KOA
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* SW = "24" *) (* half = "12" *)
(* NotValidForBitStream *)
module Recursive_KOA
(Data_A_i,
Data_B_i,
sgf_result_o);
input [23:0]Data_A_i;
input [23:0]Data_B_i;
output [47:0]sgf_result_o;
wire [23:0]Data_A_i;
wire [23:0]Data_A_i_IBUF;
wire [23:0]Data_B_i;
wire [23:0]Data_B_i_IBUF;
wire \EVEN1.left_high_n_0 ;
wire \EVEN1.left_high_n_1 ;
wire \EVEN1.left_high_n_10 ;
wire \EVEN1.left_high_n_11 ;
wire \EVEN1.left_high_n_12 ;
wire \EVEN1.left_high_n_13 ;
wire \EVEN1.left_high_n_14 ;
wire \EVEN1.left_high_n_15 ;
wire \EVEN1.left_high_n_16 ;
wire \EVEN1.left_high_n_17 ;
wire \EVEN1.left_high_n_18 ;
wire \EVEN1.left_high_n_19 ;
wire \EVEN1.left_high_n_2 ;
wire \EVEN1.left_high_n_20 ;
wire \EVEN1.left_high_n_21 ;
wire \EVEN1.left_high_n_22 ;
wire \EVEN1.left_high_n_23 ;
wire \EVEN1.left_high_n_24 ;
wire \EVEN1.left_high_n_25 ;
wire \EVEN1.left_high_n_26 ;
wire \EVEN1.left_high_n_27 ;
wire \EVEN1.left_high_n_3 ;
wire \EVEN1.left_high_n_4 ;
wire \EVEN1.left_high_n_5 ;
wire \EVEN1.left_high_n_6 ;
wire \EVEN1.left_high_n_7 ;
wire \EVEN1.left_high_n_8 ;
wire \EVEN1.left_high_n_9 ;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_11 ;
wire \EVEN1.middle_n_12 ;
wire \EVEN1.middle_n_13 ;
wire \EVEN1.middle_n_3 ;
wire \EVEN1.middle_n_33 ;
wire \EVEN1.middle_n_4 ;
wire \EVEN1.middle_n_5 ;
wire \EVEN1.middle_n_6 ;
wire \EVEN1.middle_n_7 ;
wire \EVEN1.middle_n_8 ;
wire \EVEN1.middle_n_9 ;
wire \EVEN1.right_lower_n_10 ;
wire \EVEN1.right_lower_n_11 ;
wire \EVEN1.right_lower_n_12 ;
wire \EVEN1.right_lower_n_13 ;
wire \EVEN1.right_lower_n_14 ;
wire \EVEN1.right_lower_n_15 ;
wire \EVEN1.right_lower_n_16 ;
wire \EVEN1.right_lower_n_17 ;
wire \EVEN1.right_lower_n_18 ;
wire \EVEN1.right_lower_n_19 ;
wire \EVEN1.right_lower_n_20 ;
wire \EVEN1.right_lower_n_21 ;
wire \EVEN1.right_lower_n_22 ;
wire \EVEN1.right_lower_n_23 ;
wire \EVEN1.right_lower_n_24 ;
wire \EVEN1.right_lower_n_25 ;
wire \EVEN1.right_lower_n_26 ;
wire \EVEN1.right_lower_n_27 ;
wire [24:6]Q_middle_temp__6;
wire S_B0__30_carry__1_i_11__0_n_0;
wire S_B0__30_carry__1_i_11_n_0;
wire [2:0]p_0_in0_in;
wire [47:0]sgf_result_o;
wire sgf_result_o1__35_carry_i_10_n_0;
wire sgf_result_o1__35_carry_i_12_n_0;
wire [47:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[22]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_8_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_9_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_8_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_9_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_8_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_9_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_15_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_16_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_17_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_18_n_0 ;
IBUF \Data_A_i_IBUF[0]_inst
(.I(Data_A_i[0]),
.O(Data_A_i_IBUF[0]));
IBUF \Data_A_i_IBUF[10]_inst
(.I(Data_A_i[10]),
.O(Data_A_i_IBUF[10]));
IBUF \Data_A_i_IBUF[11]_inst
(.I(Data_A_i[11]),
.O(Data_A_i_IBUF[11]));
IBUF \Data_A_i_IBUF[12]_inst
(.I(Data_A_i[12]),
.O(Data_A_i_IBUF[12]));
IBUF \Data_A_i_IBUF[13]_inst
(.I(Data_A_i[13]),
.O(Data_A_i_IBUF[13]));
IBUF \Data_A_i_IBUF[14]_inst
(.I(Data_A_i[14]),
.O(Data_A_i_IBUF[14]));
IBUF \Data_A_i_IBUF[15]_inst
(.I(Data_A_i[15]),
.O(Data_A_i_IBUF[15]));
IBUF \Data_A_i_IBUF[16]_inst
(.I(Data_A_i[16]),
.O(Data_A_i_IBUF[16]));
IBUF \Data_A_i_IBUF[17]_inst
(.I(Data_A_i[17]),
.O(Data_A_i_IBUF[17]));
IBUF \Data_A_i_IBUF[18]_inst
(.I(Data_A_i[18]),
.O(Data_A_i_IBUF[18]));
IBUF \Data_A_i_IBUF[19]_inst
(.I(Data_A_i[19]),
.O(Data_A_i_IBUF[19]));
IBUF \Data_A_i_IBUF[1]_inst
(.I(Data_A_i[1]),
.O(Data_A_i_IBUF[1]));
IBUF \Data_A_i_IBUF[20]_inst
(.I(Data_A_i[20]),
.O(Data_A_i_IBUF[20]));
IBUF \Data_A_i_IBUF[21]_inst
(.I(Data_A_i[21]),
.O(Data_A_i_IBUF[21]));
IBUF \Data_A_i_IBUF[22]_inst
(.I(Data_A_i[22]),
.O(Data_A_i_IBUF[22]));
IBUF \Data_A_i_IBUF[23]_inst
(.I(Data_A_i[23]),
.O(Data_A_i_IBUF[23]));
IBUF \Data_A_i_IBUF[2]_inst
(.I(Data_A_i[2]),
.O(Data_A_i_IBUF[2]));
IBUF \Data_A_i_IBUF[3]_inst
(.I(Data_A_i[3]),
.O(Data_A_i_IBUF[3]));
IBUF \Data_A_i_IBUF[4]_inst
(.I(Data_A_i[4]),
.O(Data_A_i_IBUF[4]));
IBUF \Data_A_i_IBUF[5]_inst
(.I(Data_A_i[5]),
.O(Data_A_i_IBUF[5]));
IBUF \Data_A_i_IBUF[6]_inst
(.I(Data_A_i[6]),
.O(Data_A_i_IBUF[6]));
IBUF \Data_A_i_IBUF[7]_inst
(.I(Data_A_i[7]),
.O(Data_A_i_IBUF[7]));
IBUF \Data_A_i_IBUF[8]_inst
(.I(Data_A_i[8]),
.O(Data_A_i_IBUF[8]));
IBUF \Data_A_i_IBUF[9]_inst
(.I(Data_A_i[9]),
.O(Data_A_i_IBUF[9]));
IBUF \Data_B_i_IBUF[0]_inst
(.I(Data_B_i[0]),
.O(Data_B_i_IBUF[0]));
IBUF \Data_B_i_IBUF[10]_inst
(.I(Data_B_i[10]),
.O(Data_B_i_IBUF[10]));
IBUF \Data_B_i_IBUF[11]_inst
(.I(Data_B_i[11]),
.O(Data_B_i_IBUF[11]));
IBUF \Data_B_i_IBUF[12]_inst
(.I(Data_B_i[12]),
.O(Data_B_i_IBUF[12]));
IBUF \Data_B_i_IBUF[13]_inst
(.I(Data_B_i[13]),
.O(Data_B_i_IBUF[13]));
IBUF \Data_B_i_IBUF[14]_inst
(.I(Data_B_i[14]),
.O(Data_B_i_IBUF[14]));
IBUF \Data_B_i_IBUF[15]_inst
(.I(Data_B_i[15]),
.O(Data_B_i_IBUF[15]));
IBUF \Data_B_i_IBUF[16]_inst
(.I(Data_B_i[16]),
.O(Data_B_i_IBUF[16]));
IBUF \Data_B_i_IBUF[17]_inst
(.I(Data_B_i[17]),
.O(Data_B_i_IBUF[17]));
IBUF \Data_B_i_IBUF[18]_inst
(.I(Data_B_i[18]),
.O(Data_B_i_IBUF[18]));
IBUF \Data_B_i_IBUF[19]_inst
(.I(Data_B_i[19]),
.O(Data_B_i_IBUF[19]));
IBUF \Data_B_i_IBUF[1]_inst
(.I(Data_B_i[1]),
.O(Data_B_i_IBUF[1]));
IBUF \Data_B_i_IBUF[20]_inst
(.I(Data_B_i[20]),
.O(Data_B_i_IBUF[20]));
IBUF \Data_B_i_IBUF[21]_inst
(.I(Data_B_i[21]),
.O(Data_B_i_IBUF[21]));
IBUF \Data_B_i_IBUF[22]_inst
(.I(Data_B_i[22]),
.O(Data_B_i_IBUF[22]));
IBUF \Data_B_i_IBUF[23]_inst
(.I(Data_B_i[23]),
.O(Data_B_i_IBUF[23]));
IBUF \Data_B_i_IBUF[2]_inst
(.I(Data_B_i[2]),
.O(Data_B_i_IBUF[2]));
IBUF \Data_B_i_IBUF[3]_inst
(.I(Data_B_i[3]),
.O(Data_B_i_IBUF[3]));
IBUF \Data_B_i_IBUF[4]_inst
(.I(Data_B_i[4]),
.O(Data_B_i_IBUF[4]));
IBUF \Data_B_i_IBUF[5]_inst
(.I(Data_B_i[5]),
.O(Data_B_i_IBUF[5]));
IBUF \Data_B_i_IBUF[6]_inst
(.I(Data_B_i[6]),
.O(Data_B_i_IBUF[6]));
IBUF \Data_B_i_IBUF[7]_inst
(.I(Data_B_i[7]),
.O(Data_B_i_IBUF[7]));
IBUF \Data_B_i_IBUF[8]_inst
(.I(Data_B_i[8]),
.O(Data_B_i_IBUF[8]));
IBUF \Data_B_i_IBUF[9]_inst
(.I(Data_B_i[9]),
.O(Data_B_i_IBUF[9]));
Recursive_KOA__parameterized0 \EVEN1.left_high
(.\Data_A_i[17] (\EVEN1.left_high_n_3 ),
.\Data_A_i[20] ({\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 ,\EVEN1.left_high_n_7 }),
.\Data_A_i[23] (\EVEN1.left_high_n_8 ),
.Data_A_i_IBUF(Data_A_i_IBUF[23:12]),
.Data_B_i_IBUF(Data_B_i_IBUF[23:12]),
.O({\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 }),
.S(S_B0__30_carry__1_i_11__0_n_0),
.\sgf_result_o[23] ({\EVEN1.left_high_n_7 ,\EVEN1.left_high_n_8 }),
.\sgf_result_o[39] ({\EVEN1.left_high_n_21 ,\EVEN1.left_high_n_22 ,\EVEN1.left_high_n_23 ,\EVEN1.left_high_n_24 }),
.\sgf_result_o[43] ({\EVEN1.left_high_n_25 ,\EVEN1.left_high_n_26 ,\EVEN1.left_high_n_27 }),
.\sgf_result_o[47] (\EVEN1.left_high_n_0 ),
.\sgf_result_o[47]_0 ({\EVEN1.left_high_n_3 ,\EVEN1.left_high_n_4 ,\EVEN1.left_high_n_5 ,\EVEN1.left_high_n_6 }),
.\sgf_result_o[47]_1 ({\EVEN1.left_high_n_9 ,\EVEN1.left_high_n_10 ,\EVEN1.left_high_n_11 ,\EVEN1.left_high_n_12 }),
.\sgf_result_o[47]_2 ({\EVEN1.left_high_n_13 ,\EVEN1.left_high_n_14 ,\EVEN1.left_high_n_15 ,\EVEN1.left_high_n_16 }),
.\sgf_result_o[47]_3 ({\EVEN1.left_high_n_17 ,\EVEN1.left_high_n_18 ,\EVEN1.left_high_n_19 ,\EVEN1.left_high_n_20 }));
Recursive_KOA__parameterized32 \EVEN1.middle
(.CO(p_0_in0_in[2]),
.DI(\sgf_result_o_OBUF[22]_inst_i_7_n_0 ),
.\Data_A_i[11] (\EVEN1.right_lower_n_16 ),
.\Data_A_i[11]_0 (\EVEN1.right_lower_n_15 ),
.\Data_A_i[12] (sgf_result_o1__35_carry_i_10_n_0),
.\Data_A_i[12]_0 ({\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 ,\EVEN1.middle_n_33 }),
.\Data_A_i[13] ({\sgf_result_o_OBUF[30]_inst_i_7_n_0 ,\sgf_result_o_OBUF[30]_inst_i_8_n_0 ,\sgf_result_o_OBUF[30]_inst_i_9_n_0 ,\sgf_result_o_OBUF[30]_inst_i_10_n_0 }),
.\Data_A_i[13]_0 ({\sgf_result_o_OBUF[30]_inst_i_11_n_0 ,\sgf_result_o_OBUF[30]_inst_i_12_n_0 ,\sgf_result_o_OBUF[30]_inst_i_13_n_0 ,\sgf_result_o_OBUF[30]_inst_i_14_n_0 }),
.\Data_A_i[13]_1 ({\sgf_result_o_OBUF[34]_inst_i_7_n_0 ,\sgf_result_o_OBUF[34]_inst_i_8_n_0 ,\sgf_result_o_OBUF[34]_inst_i_9_n_0 ,\sgf_result_o_OBUF[34]_inst_i_10_n_0 }),
.\Data_A_i[13]_2 ({\sgf_result_o_OBUF[34]_inst_i_11_n_0 ,\sgf_result_o_OBUF[34]_inst_i_12_n_0 ,\sgf_result_o_OBUF[34]_inst_i_13_n_0 ,\sgf_result_o_OBUF[34]_inst_i_14_n_0 }),
.\Data_A_i[13]_3 ({\sgf_result_o_OBUF[38]_inst_i_11_n_0 ,\sgf_result_o_OBUF[38]_inst_i_12_n_0 ,\sgf_result_o_OBUF[38]_inst_i_13_n_0 ,\sgf_result_o_OBUF[38]_inst_i_14_n_0 }),
.\Data_A_i[13]_4 ({\sgf_result_o_OBUF[38]_inst_i_15_n_0 ,\sgf_result_o_OBUF[38]_inst_i_16_n_0 ,\sgf_result_o_OBUF[38]_inst_i_17_n_0 ,\sgf_result_o_OBUF[38]_inst_i_18_n_0 }),
.\Data_A_i[14] ({\sgf_result_o_OBUF[26]_inst_i_7_n_0 ,\sgf_result_o_OBUF[26]_inst_i_8_n_0 ,\sgf_result_o_OBUF[26]_inst_i_9_n_0 ,\sgf_result_o_OBUF[26]_inst_i_10_n_0 }),
.\Data_A_i[14]_0 ({\sgf_result_o_OBUF[26]_inst_i_11_n_0 ,\sgf_result_o_OBUF[26]_inst_i_12_n_0 ,\sgf_result_o_OBUF[26]_inst_i_13_n_0 ,\sgf_result_o_OBUF[26]_inst_i_14_n_0 }),
.\Data_A_i[14]_1 (\sgf_result_o_OBUF[38]_inst_i_10_n_0 ),
.\Data_A_i[14]_2 (\EVEN1.left_high_n_19 ),
.\Data_A_i[14]_3 ({\EVEN1.left_high_n_23 ,\EVEN1.left_high_n_24 ,\EVEN1.left_high_n_17 ,\EVEN1.left_high_n_18 }),
.\Data_A_i[14]_4 ({\EVEN1.left_high_n_26 ,\EVEN1.left_high_n_27 ,\EVEN1.left_high_n_21 ,\EVEN1.left_high_n_22 }),
.\Data_A_i[14]_5 (\EVEN1.left_high_n_25 ),
.\Data_A_i[14]_6 (\EVEN1.left_high_n_20 ),
.\Data_A_i[17] ({\EVEN1.left_high_n_4 ,\EVEN1.left_high_n_5 ,\EVEN1.left_high_n_6 }),
.\Data_A_i[23] ({\EVEN1.left_high_n_9 ,\EVEN1.left_high_n_10 ,\EVEN1.left_high_n_11 ,\EVEN1.left_high_n_12 }),
.\Data_A_i[23]_0 ({\EVEN1.left_high_n_13 ,\EVEN1.left_high_n_14 ,\EVEN1.left_high_n_15 ,\EVEN1.left_high_n_16 }),
.\Data_A_i[2] ({\EVEN1.right_lower_n_17 ,\EVEN1.right_lower_n_18 ,\EVEN1.right_lower_n_19 ,\EVEN1.right_lower_n_20 }),
.\Data_A_i[2]_0 ({\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 ,\EVEN1.right_lower_n_23 ,\EVEN1.right_lower_n_24 }),
.\Data_A_i[2]_1 ({\EVEN1.right_lower_n_25 ,\EVEN1.right_lower_n_26 ,\EVEN1.right_lower_n_27 }),
.Data_A_i_IBUF(Data_A_i_IBUF),
.\Data_B_i[12] (\EVEN1.left_high_n_0 ),
.\Data_B_i[17] (\sgf_result_o_OBUF[22]_inst_i_11_n_0 ),
.Data_B_i_IBUF(Data_B_i_IBUF),
.O(\EVEN1.middle_n_0 ),
.S(sgf_result_o1__35_carry_i_12_n_0),
.\sgf_result_o[15] ({p_0_in0_in[1:0],\EVEN1.middle_n_3 ,\EVEN1.middle_n_4 }),
.\sgf_result_o[15]_0 ({\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 ,\EVEN1.middle_n_8 ,\EVEN1.middle_n_9 }),
.\sgf_result_o[15]_1 (\EVEN1.middle_n_11 ),
.\sgf_result_o[47] (\EVEN1.middle_n_5 ),
.\sgf_result_o[47]_0 ({\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 }),
.\sgf_result_o[47]_1 (Q_middle_temp__6),
.\sgf_result_o[47]_2 (\EVEN1.middle_n_33 ),
.\sgf_result_o[47]_3 (sgf_result_o_OBUF[47:11]),
.sgf_result_o_OBUF(sgf_result_o_OBUF[6:1]));
Recursive_KOA__parameterized16 \EVEN1.right_lower
(.\Data_A_i[11] (\EVEN1.right_lower_n_14 ),
.\Data_A_i[5] (\EVEN1.right_lower_n_12 ),
.\Data_A_i[8] ({\EVEN1.right_lower_n_10 ,\EVEN1.right_lower_n_11 ,\EVEN1.right_lower_n_13 }),
.Data_A_i_IBUF(Data_A_i_IBUF[11:0]),
.Data_B_i_IBUF(Data_B_i_IBUF[11:0]),
.O({\EVEN1.right_lower_n_10 ,\EVEN1.right_lower_n_11 }),
.S(S_B0__30_carry__1_i_11_n_0),
.\sgf_result_o[47] (\EVEN1.right_lower_n_12 ),
.\sgf_result_o[47]_0 ({\EVEN1.right_lower_n_13 ,\EVEN1.right_lower_n_14 }),
.\sgf_result_o[47]_1 ({\EVEN1.right_lower_n_15 ,\EVEN1.right_lower_n_16 }),
.\sgf_result_o[47]_2 ({\EVEN1.right_lower_n_17 ,\EVEN1.right_lower_n_18 ,\EVEN1.right_lower_n_19 ,\EVEN1.right_lower_n_20 }),
.\sgf_result_o[47]_3 ({\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 ,\EVEN1.right_lower_n_23 ,\EVEN1.right_lower_n_24 }),
.\sgf_result_o[47]_4 ({\EVEN1.right_lower_n_25 ,\EVEN1.right_lower_n_26 ,\EVEN1.right_lower_n_27 }),
.sgf_result_o_OBUF(sgf_result_o_OBUF[10:1]));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__30_carry__1_i_11
(.I0(Data_A_i_IBUF[11]),
.I1(Data_B_i_IBUF[9]),
.I2(Data_A_i_IBUF[9]),
.I3(Data_B_i_IBUF[11]),
.I4(Data_A_i_IBUF[10]),
.I5(Data_B_i_IBUF[10]),
.O(S_B0__30_carry__1_i_11_n_0));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__30_carry__1_i_11__0
(.I0(Data_A_i_IBUF[23]),
.I1(Data_B_i_IBUF[21]),
.I2(Data_A_i_IBUF[21]),
.I3(Data_B_i_IBUF[23]),
.I4(Data_A_i_IBUF[22]),
.I5(Data_B_i_IBUF[22]),
.O(S_B0__30_carry__1_i_11__0_n_0));
LUT6 #(
.INIT(64'hAA00800080000000))
sgf_result_o1__35_carry_i_10
(.I0(p_0_in0_in[2]),
.I1(\EVEN1.middle_n_7 ),
.I2(p_0_in0_in[0]),
.I3(\EVEN1.middle_n_11 ),
.I4(p_0_in0_in[1]),
.I5(\EVEN1.middle_n_6 ),
.O(sgf_result_o1__35_carry_i_10_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
sgf_result_o1__35_carry_i_12
(.I0(\EVEN1.middle_n_9 ),
.I1(\EVEN1.middle_n_4 ),
.I2(\EVEN1.middle_n_8 ),
.I3(\EVEN1.middle_n_0 ),
.I4(\EVEN1.middle_n_5 ),
.I5(\EVEN1.middle_n_3 ),
.O(sgf_result_o1__35_carry_i_12_n_0));
OBUF \sgf_result_o_OBUF[0]_inst
(.I(sgf_result_o_OBUF[0]),
.O(sgf_result_o[0]));
LUT2 #(
.INIT(4'h8))
\sgf_result_o_OBUF[0]_inst_i_1
(.I0(Data_B_i_IBUF[0]),
.I1(Data_A_i_IBUF[0]),
.O(sgf_result_o_OBUF[0]));
OBUF \sgf_result_o_OBUF[10]_inst
(.I(sgf_result_o_OBUF[10]),
.O(sgf_result_o[10]));
OBUF \sgf_result_o_OBUF[11]_inst
(.I(sgf_result_o_OBUF[11]),
.O(sgf_result_o[11]));
OBUF \sgf_result_o_OBUF[12]_inst
(.I(sgf_result_o_OBUF[12]),
.O(sgf_result_o[12]));
OBUF \sgf_result_o_OBUF[13]_inst
(.I(sgf_result_o_OBUF[13]),
.O(sgf_result_o[13]));
OBUF \sgf_result_o_OBUF[14]_inst
(.I(sgf_result_o_OBUF[14]),
.O(sgf_result_o[14]));
OBUF \sgf_result_o_OBUF[15]_inst
(.I(sgf_result_o_OBUF[15]),
.O(sgf_result_o[15]));
OBUF \sgf_result_o_OBUF[16]_inst
(.I(sgf_result_o_OBUF[16]),
.O(sgf_result_o[16]));
OBUF \sgf_result_o_OBUF[17]_inst
(.I(sgf_result_o_OBUF[17]),
.O(sgf_result_o[17]));
OBUF \sgf_result_o_OBUF[18]_inst
(.I(sgf_result_o_OBUF[18]),
.O(sgf_result_o[18]));
OBUF \sgf_result_o_OBUF[19]_inst
(.I(sgf_result_o_OBUF[19]),
.O(sgf_result_o[19]));
OBUF \sgf_result_o_OBUF[1]_inst
(.I(sgf_result_o_OBUF[1]),
.O(sgf_result_o[1]));
OBUF \sgf_result_o_OBUF[20]_inst
(.I(sgf_result_o_OBUF[20]),
.O(sgf_result_o[20]));
OBUF \sgf_result_o_OBUF[21]_inst
(.I(sgf_result_o_OBUF[21]),
.O(sgf_result_o[21]));
OBUF \sgf_result_o_OBUF[22]_inst
(.I(sgf_result_o_OBUF[22]),
.O(sgf_result_o[22]));
(* HLUTNM = "lutpair65" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[22]_inst_i_11
(.I0(Q_middle_temp__6[7]),
.I1(\EVEN1.left_high_n_10 ),
.I2(sgf_result_o_OBUF[7]),
.I3(\sgf_result_o_OBUF[22]_inst_i_7_n_0 ),
.O(\sgf_result_o_OBUF[22]_inst_i_11_n_0 ));
(* HLUTNM = "lutpair64" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[22]_inst_i_7
(.I0(Q_middle_temp__6[6]),
.I1(\EVEN1.left_high_n_11 ),
.I2(sgf_result_o_OBUF[6]),
.O(\sgf_result_o_OBUF[22]_inst_i_7_n_0 ));
OBUF \sgf_result_o_OBUF[23]_inst
(.I(sgf_result_o_OBUF[23]),
.O(sgf_result_o[23]));
OBUF \sgf_result_o_OBUF[24]_inst
(.I(sgf_result_o_OBUF[24]),
.O(sgf_result_o[24]));
OBUF \sgf_result_o_OBUF[25]_inst
(.I(sgf_result_o_OBUF[25]),
.O(sgf_result_o[25]));
OBUF \sgf_result_o_OBUF[26]_inst
(.I(sgf_result_o_OBUF[26]),
.O(sgf_result_o[26]));
(* HLUTNM = "lutpair65" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[26]_inst_i_10
(.I0(Q_middle_temp__6[7]),
.I1(\EVEN1.left_high_n_10 ),
.I2(sgf_result_o_OBUF[7]),
.O(\sgf_result_o_OBUF[26]_inst_i_10_n_0 ));
(* HLUTNM = "lutpair69" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[26]_inst_i_11
(.I0(Q_middle_temp__6[11]),
.I1(\EVEN1.left_high_n_14 ),
.I2(\EVEN1.right_lower_n_16 ),
.I3(\sgf_result_o_OBUF[26]_inst_i_7_n_0 ),
.O(\sgf_result_o_OBUF[26]_inst_i_11_n_0 ));
(* HLUTNM = "lutpair68" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[26]_inst_i_12
(.I0(Q_middle_temp__6[10]),
.I1(\EVEN1.left_high_n_15 ),
.I2(sgf_result_o_OBUF[10]),
.I3(\sgf_result_o_OBUF[26]_inst_i_8_n_0 ),
.O(\sgf_result_o_OBUF[26]_inst_i_12_n_0 ));
(* HLUTNM = "lutpair67" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[26]_inst_i_13
(.I0(Q_middle_temp__6[9]),
.I1(\EVEN1.left_high_n_16 ),
.I2(sgf_result_o_OBUF[9]),
.I3(\sgf_result_o_OBUF[26]_inst_i_9_n_0 ),
.O(\sgf_result_o_OBUF[26]_inst_i_13_n_0 ));
(* HLUTNM = "lutpair66" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[26]_inst_i_14
(.I0(Q_middle_temp__6[8]),
.I1(\EVEN1.left_high_n_9 ),
.I2(sgf_result_o_OBUF[8]),
.I3(\sgf_result_o_OBUF[26]_inst_i_10_n_0 ),
.O(\sgf_result_o_OBUF[26]_inst_i_14_n_0 ));
(* HLUTNM = "lutpair68" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[26]_inst_i_7
(.I0(Q_middle_temp__6[10]),
.I1(\EVEN1.left_high_n_15 ),
.I2(sgf_result_o_OBUF[10]),
.O(\sgf_result_o_OBUF[26]_inst_i_7_n_0 ));
(* HLUTNM = "lutpair67" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[26]_inst_i_8
(.I0(Q_middle_temp__6[9]),
.I1(\EVEN1.left_high_n_16 ),
.I2(sgf_result_o_OBUF[9]),
.O(\sgf_result_o_OBUF[26]_inst_i_8_n_0 ));
(* HLUTNM = "lutpair66" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[26]_inst_i_9
(.I0(Q_middle_temp__6[8]),
.I1(\EVEN1.left_high_n_9 ),
.I2(sgf_result_o_OBUF[8]),
.O(\sgf_result_o_OBUF[26]_inst_i_9_n_0 ));
OBUF \sgf_result_o_OBUF[27]_inst
(.I(sgf_result_o_OBUF[27]),
.O(sgf_result_o[27]));
OBUF \sgf_result_o_OBUF[28]_inst
(.I(sgf_result_o_OBUF[28]),
.O(sgf_result_o[28]));
OBUF \sgf_result_o_OBUF[29]_inst
(.I(sgf_result_o_OBUF[29]),
.O(sgf_result_o[29]));
OBUF \sgf_result_o_OBUF[2]_inst
(.I(sgf_result_o_OBUF[2]),
.O(sgf_result_o[2]));
OBUF \sgf_result_o_OBUF[30]_inst
(.I(sgf_result_o_OBUF[30]),
.O(sgf_result_o[30]));
(* HLUTNM = "lutpair69" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[30]_inst_i_10
(.I0(Q_middle_temp__6[11]),
.I1(\EVEN1.left_high_n_14 ),
.I2(\EVEN1.right_lower_n_16 ),
.O(\sgf_result_o_OBUF[30]_inst_i_10_n_0 ));
(* HLUTNM = "lutpair73" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[30]_inst_i_11
(.I0(Q_middle_temp__6[15]),
.I1(\EVEN1.left_high_n_18 ),
.I2(\EVEN1.right_lower_n_18 ),
.I3(\sgf_result_o_OBUF[30]_inst_i_7_n_0 ),
.O(\sgf_result_o_OBUF[30]_inst_i_11_n_0 ));
(* HLUTNM = "lutpair72" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[30]_inst_i_12
(.I0(Q_middle_temp__6[14]),
.I1(\EVEN1.left_high_n_19 ),
.I2(\EVEN1.right_lower_n_19 ),
.I3(\sgf_result_o_OBUF[30]_inst_i_8_n_0 ),
.O(\sgf_result_o_OBUF[30]_inst_i_12_n_0 ));
(* HLUTNM = "lutpair71" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[30]_inst_i_13
(.I0(Q_middle_temp__6[13]),
.I1(\EVEN1.left_high_n_20 ),
.I2(\EVEN1.right_lower_n_20 ),
.I3(\sgf_result_o_OBUF[30]_inst_i_9_n_0 ),
.O(\sgf_result_o_OBUF[30]_inst_i_13_n_0 ));
(* HLUTNM = "lutpair70" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[30]_inst_i_14
(.I0(Q_middle_temp__6[12]),
.I1(\EVEN1.left_high_n_13 ),
.I2(\EVEN1.right_lower_n_15 ),
.I3(\sgf_result_o_OBUF[30]_inst_i_10_n_0 ),
.O(\sgf_result_o_OBUF[30]_inst_i_14_n_0 ));
(* HLUTNM = "lutpair72" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[30]_inst_i_7
(.I0(Q_middle_temp__6[14]),
.I1(\EVEN1.left_high_n_19 ),
.I2(\EVEN1.right_lower_n_19 ),
.O(\sgf_result_o_OBUF[30]_inst_i_7_n_0 ));
(* HLUTNM = "lutpair71" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[30]_inst_i_8
(.I0(Q_middle_temp__6[13]),
.I1(\EVEN1.left_high_n_20 ),
.I2(\EVEN1.right_lower_n_20 ),
.O(\sgf_result_o_OBUF[30]_inst_i_8_n_0 ));
(* HLUTNM = "lutpair70" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[30]_inst_i_9
(.I0(Q_middle_temp__6[12]),
.I1(\EVEN1.left_high_n_13 ),
.I2(\EVEN1.right_lower_n_15 ),
.O(\sgf_result_o_OBUF[30]_inst_i_9_n_0 ));
OBUF \sgf_result_o_OBUF[31]_inst
(.I(sgf_result_o_OBUF[31]),
.O(sgf_result_o[31]));
OBUF \sgf_result_o_OBUF[32]_inst
(.I(sgf_result_o_OBUF[32]),
.O(sgf_result_o[32]));
OBUF \sgf_result_o_OBUF[33]_inst
(.I(sgf_result_o_OBUF[33]),
.O(sgf_result_o[33]));
OBUF \sgf_result_o_OBUF[34]_inst
(.I(sgf_result_o_OBUF[34]),
.O(sgf_result_o[34]));
(* HLUTNM = "lutpair73" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[34]_inst_i_10
(.I0(Q_middle_temp__6[15]),
.I1(\EVEN1.left_high_n_18 ),
.I2(\EVEN1.right_lower_n_18 ),
.O(\sgf_result_o_OBUF[34]_inst_i_10_n_0 ));
(* HLUTNM = "lutpair77" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[34]_inst_i_11
(.I0(Q_middle_temp__6[19]),
.I1(\EVEN1.left_high_n_22 ),
.I2(\EVEN1.right_lower_n_22 ),
.I3(\sgf_result_o_OBUF[34]_inst_i_7_n_0 ),
.O(\sgf_result_o_OBUF[34]_inst_i_11_n_0 ));
(* HLUTNM = "lutpair76" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[34]_inst_i_12
(.I0(Q_middle_temp__6[18]),
.I1(\EVEN1.left_high_n_23 ),
.I2(\EVEN1.right_lower_n_23 ),
.I3(\sgf_result_o_OBUF[34]_inst_i_8_n_0 ),
.O(\sgf_result_o_OBUF[34]_inst_i_12_n_0 ));
(* HLUTNM = "lutpair75" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[34]_inst_i_13
(.I0(Q_middle_temp__6[17]),
.I1(\EVEN1.left_high_n_24 ),
.I2(\EVEN1.right_lower_n_24 ),
.I3(\sgf_result_o_OBUF[34]_inst_i_9_n_0 ),
.O(\sgf_result_o_OBUF[34]_inst_i_13_n_0 ));
(* HLUTNM = "lutpair74" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[34]_inst_i_14
(.I0(Q_middle_temp__6[16]),
.I1(\EVEN1.left_high_n_17 ),
.I2(\EVEN1.right_lower_n_17 ),
.I3(\sgf_result_o_OBUF[34]_inst_i_10_n_0 ),
.O(\sgf_result_o_OBUF[34]_inst_i_14_n_0 ));
(* HLUTNM = "lutpair76" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[34]_inst_i_7
(.I0(Q_middle_temp__6[18]),
.I1(\EVEN1.left_high_n_23 ),
.I2(\EVEN1.right_lower_n_23 ),
.O(\sgf_result_o_OBUF[34]_inst_i_7_n_0 ));
(* HLUTNM = "lutpair75" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[34]_inst_i_8
(.I0(Q_middle_temp__6[17]),
.I1(\EVEN1.left_high_n_24 ),
.I2(\EVEN1.right_lower_n_24 ),
.O(\sgf_result_o_OBUF[34]_inst_i_8_n_0 ));
(* HLUTNM = "lutpair74" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[34]_inst_i_9
(.I0(Q_middle_temp__6[16]),
.I1(\EVEN1.left_high_n_17 ),
.I2(\EVEN1.right_lower_n_17 ),
.O(\sgf_result_o_OBUF[34]_inst_i_9_n_0 ));
OBUF \sgf_result_o_OBUF[35]_inst
(.I(sgf_result_o_OBUF[35]),
.O(sgf_result_o[35]));
OBUF \sgf_result_o_OBUF[36]_inst
(.I(sgf_result_o_OBUF[36]),
.O(sgf_result_o[36]));
OBUF \sgf_result_o_OBUF[37]_inst
(.I(sgf_result_o_OBUF[37]),
.O(sgf_result_o[37]));
OBUF \sgf_result_o_OBUF[38]_inst
(.I(sgf_result_o_OBUF[38]),
.O(sgf_result_o[38]));
LUT4 #(
.INIT(16'h8E71))
\sgf_result_o_OBUF[38]_inst_i_10
(.I0(\EVEN1.right_lower_n_25 ),
.I1(\EVEN1.left_high_n_25 ),
.I2(Q_middle_temp__6[23]),
.I3(Q_middle_temp__6[24]),
.O(\sgf_result_o_OBUF[38]_inst_i_10_n_0 ));
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[38]_inst_i_11
(.I0(Q_middle_temp__6[22]),
.I1(\EVEN1.left_high_n_26 ),
.I2(\EVEN1.right_lower_n_26 ),
.O(\sgf_result_o_OBUF[38]_inst_i_11_n_0 ));
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[38]_inst_i_12
(.I0(Q_middle_temp__6[21]),
.I1(\EVEN1.left_high_n_27 ),
.I2(\EVEN1.right_lower_n_27 ),
.O(\sgf_result_o_OBUF[38]_inst_i_12_n_0 ));
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[38]_inst_i_13
(.I0(Q_middle_temp__6[20]),
.I1(\EVEN1.left_high_n_21 ),
.I2(\EVEN1.right_lower_n_21 ),
.O(\sgf_result_o_OBUF[38]_inst_i_13_n_0 ));
(* HLUTNM = "lutpair77" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[38]_inst_i_14
(.I0(Q_middle_temp__6[19]),
.I1(\EVEN1.left_high_n_22 ),
.I2(\EVEN1.right_lower_n_22 ),
.O(\sgf_result_o_OBUF[38]_inst_i_14_n_0 ));
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[38]_inst_i_15
(.I0(\sgf_result_o_OBUF[38]_inst_i_11_n_0 ),
.I1(Q_middle_temp__6[23]),
.I2(\EVEN1.left_high_n_25 ),
.I3(\EVEN1.right_lower_n_25 ),
.O(\sgf_result_o_OBUF[38]_inst_i_15_n_0 ));
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[38]_inst_i_16
(.I0(Q_middle_temp__6[22]),
.I1(\EVEN1.left_high_n_26 ),
.I2(\EVEN1.right_lower_n_26 ),
.I3(\sgf_result_o_OBUF[38]_inst_i_12_n_0 ),
.O(\sgf_result_o_OBUF[38]_inst_i_16_n_0 ));
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[38]_inst_i_17
(.I0(Q_middle_temp__6[21]),
.I1(\EVEN1.left_high_n_27 ),
.I2(\EVEN1.right_lower_n_27 ),
.I3(\sgf_result_o_OBUF[38]_inst_i_13_n_0 ),
.O(\sgf_result_o_OBUF[38]_inst_i_17_n_0 ));
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[38]_inst_i_18
(.I0(Q_middle_temp__6[20]),
.I1(\EVEN1.left_high_n_21 ),
.I2(\EVEN1.right_lower_n_21 ),
.I3(\sgf_result_o_OBUF[38]_inst_i_14_n_0 ),
.O(\sgf_result_o_OBUF[38]_inst_i_18_n_0 ));
OBUF \sgf_result_o_OBUF[39]_inst
(.I(sgf_result_o_OBUF[39]),
.O(sgf_result_o[39]));
OBUF \sgf_result_o_OBUF[3]_inst
(.I(sgf_result_o_OBUF[3]),
.O(sgf_result_o[3]));
OBUF \sgf_result_o_OBUF[40]_inst
(.I(sgf_result_o_OBUF[40]),
.O(sgf_result_o[40]));
OBUF \sgf_result_o_OBUF[41]_inst
(.I(sgf_result_o_OBUF[41]),
.O(sgf_result_o[41]));
OBUF \sgf_result_o_OBUF[42]_inst
(.I(sgf_result_o_OBUF[42]),
.O(sgf_result_o[42]));
OBUF \sgf_result_o_OBUF[43]_inst
(.I(sgf_result_o_OBUF[43]),
.O(sgf_result_o[43]));
OBUF \sgf_result_o_OBUF[44]_inst
(.I(sgf_result_o_OBUF[44]),
.O(sgf_result_o[44]));
OBUF \sgf_result_o_OBUF[45]_inst
(.I(sgf_result_o_OBUF[45]),
.O(sgf_result_o[45]));
OBUF \sgf_result_o_OBUF[46]_inst
(.I(sgf_result_o_OBUF[46]),
.O(sgf_result_o[46]));
OBUF \sgf_result_o_OBUF[47]_inst
(.I(sgf_result_o_OBUF[47]),
.O(sgf_result_o[47]));
OBUF \sgf_result_o_OBUF[4]_inst
(.I(sgf_result_o_OBUF[4]),
.O(sgf_result_o[4]));
OBUF \sgf_result_o_OBUF[5]_inst
(.I(sgf_result_o_OBUF[5]),
.O(sgf_result_o[5]));
OBUF \sgf_result_o_OBUF[6]_inst
(.I(sgf_result_o_OBUF[6]),
.O(sgf_result_o[6]));
OBUF \sgf_result_o_OBUF[7]_inst
(.I(sgf_result_o_OBUF[7]),
.O(sgf_result_o[7]));
OBUF \sgf_result_o_OBUF[8]_inst
(.I(sgf_result_o_OBUF[8]),
.O(sgf_result_o[8]));
OBUF \sgf_result_o_OBUF[9]_inst
(.I(sgf_result_o_OBUF[9]),
.O(sgf_result_o[9]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized0
(\sgf_result_o[47] ,
O,
\sgf_result_o[47]_0 ,
\sgf_result_o[23] ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[39] ,
\sgf_result_o[43] ,
Data_A_i_IBUF,
Data_B_i_IBUF,
S,
\Data_A_i[17] ,
\Data_A_i[23] ,
\Data_A_i[20] );
output \sgf_result_o[47] ;
output [1:0]O;
output [3:0]\sgf_result_o[47]_0 ;
output [1:0]\sgf_result_o[23] ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[39] ;
output [2:0]\sgf_result_o[43] ;
input [11:0]Data_A_i_IBUF;
input [11:0]Data_B_i_IBUF;
input [0:0]S;
input [0:0]\Data_A_i[17] ;
input [0:0]\Data_A_i[23] ;
input [2:0]\Data_A_i[20] ;
wire [0:0]\Data_A_i[17] ;
wire [2:0]\Data_A_i[20] ;
wire [0:0]\Data_A_i[23] ;
wire [11:0]Data_A_i_IBUF;
wire [11:0]Data_B_i_IBUF;
wire \EVEN1.left_high_n_11 ;
wire \EVEN1.left_high_n_12 ;
wire \EVEN1.left_high_n_13 ;
wire \EVEN1.left_high_n_14 ;
wire \EVEN1.left_high_n_15 ;
wire \EVEN1.left_high_n_16 ;
wire \EVEN1.left_high_n_17 ;
wire \EVEN1.left_high_n_18 ;
wire \EVEN1.left_high_n_19 ;
wire \EVEN1.left_high_n_20 ;
wire \EVEN1.left_high_n_21 ;
wire \EVEN1.left_high_n_22 ;
wire \EVEN1.left_high_n_23 ;
wire \EVEN1.left_high_n_24 ;
wire \EVEN1.left_high_n_25 ;
wire \EVEN1.left_high_n_26 ;
wire \EVEN1.left_high_n_27 ;
wire \EVEN1.left_high_n_28 ;
wire \EVEN1.left_high_n_29 ;
wire \EVEN1.left_high_n_32 ;
wire \EVEN1.left_high_n_33 ;
wire \EVEN1.left_high_n_36 ;
wire \EVEN1.left_high_n_37 ;
wire \EVEN1.left_high_n_38 ;
wire \EVEN1.left_high_n_39 ;
wire \EVEN1.left_high_n_40 ;
wire \EVEN1.left_high_n_41 ;
wire \EVEN1.left_high_n_42 ;
wire \EVEN1.left_high_n_43 ;
wire \EVEN1.left_high_n_44 ;
wire \EVEN1.left_high_n_45 ;
wire \EVEN1.left_high_n_46 ;
wire \EVEN1.left_high_n_47 ;
wire \EVEN1.left_high_n_48 ;
wire \EVEN1.left_high_n_49 ;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_10 ;
wire \EVEN1.middle_n_11 ;
wire \EVEN1.middle_n_12 ;
wire \EVEN1.middle_n_13 ;
wire \EVEN1.middle_n_14 ;
wire \EVEN1.middle_n_15 ;
wire \EVEN1.middle_n_16 ;
wire \EVEN1.middle_n_17 ;
wire \EVEN1.middle_n_18 ;
wire \EVEN1.middle_n_19 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_20 ;
wire \EVEN1.middle_n_21 ;
wire \EVEN1.middle_n_22 ;
wire \EVEN1.middle_n_23 ;
wire \EVEN1.middle_n_24 ;
wire \EVEN1.middle_n_25 ;
wire \EVEN1.middle_n_26 ;
wire \EVEN1.middle_n_27 ;
wire \EVEN1.middle_n_28 ;
wire \EVEN1.middle_n_29 ;
wire \EVEN1.middle_n_3 ;
wire \EVEN1.middle_n_30 ;
wire \EVEN1.middle_n_4 ;
wire \EVEN1.middle_n_5 ;
wire \EVEN1.middle_n_6 ;
wire \EVEN1.middle_n_7 ;
wire \EVEN1.middle_n_8 ;
wire \EVEN1.middle_n_9 ;
wire \EVEN1.right_lower_n_4 ;
wire \EVEN1.right_lower_n_5 ;
wire \EVEN1.right_lower_n_6 ;
wire \EVEN1.right_lower_n_7 ;
wire \EVEN1.right_lower_n_8 ;
wire \EVEN1.right_lower_n_9 ;
wire [1:0]O;
wire [13:3]Q_middle_temp__2;
wire [0:0]S;
wire S_B0__0_carry__0_i_10__1_n_0;
wire S_B0__0_carry__0_i_7__1_n_0;
wire S_B0__0_carry__0_i_8__1_n_0;
wire S_B0__0_carry__0_i_9__1_n_0;
wire S_B0__0_carry_i_11__1_n_0;
wire S_B0__0_carry_i_12__1_n_0;
wire S_B0__0_carry_i_13__0_n_0;
wire S_B0__0_carry_i_8__1_n_0;
wire S_B0__0_carry_i_9__1_n_0;
wire S_B0__30_carry__0_i_1__0_n_0;
wire S_B0__30_carry__0_i_2__0_n_0;
wire S_B0__30_carry__0_i_3__0_n_0;
wire S_B0__30_carry__0_i_4__0_n_0;
wire S_B0__30_carry__0_i_5__0_n_0;
wire S_B0__30_carry__0_i_6__0_n_0;
wire S_B0__30_carry__0_i_7__0_n_0;
wire S_B0__30_carry__0_i_8__0_n_0;
wire S_B0__30_carry__1_i_13__0_n_0;
wire S_B0__30_carry__1_i_1__0_n_0;
wire S_B0__30_carry__1_i_2__0_n_0;
wire S_B0__30_carry__1_i_3__0_n_0;
wire S_B0__30_carry__1_i_4__0_n_0;
wire S_B0__30_carry__1_i_5__0_n_0;
wire S_B0__30_carry__1_i_6__0_n_0;
wire S_B0__30_carry__1_i_7__0_n_0;
wire S_B0__30_carry__1_i_8__0_n_0;
wire S_B0__30_carry__2_i_1__0_n_0;
wire S_B0__30_carry__2_i_2__0_n_0;
wire S_B0__30_carry_i_13_n_0;
wire S_B0__30_carry_i_17_n_0;
wire S_B0_carry__0_i_5__0_n_0;
wire [2:0]p_0_in;
wire sgf_result_o0__1_carry__0_i_1__5_n_0;
wire sgf_result_o0__1_carry__0_i_2__4_n_0;
wire sgf_result_o0__1_carry__0_i_3__6_n_0;
wire sgf_result_o0__1_carry__0_i_4__5_n_0;
wire sgf_result_o0__1_carry__0_i_5__7_n_0;
wire sgf_result_o0__1_carry__0_i_6__5_n_0;
wire sgf_result_o0__1_carry__0_i_7__2_n_0;
wire sgf_result_o0__1_carry__0_i_8__4_n_0;
wire sgf_result_o0__1_carry__0_i_9__2_n_0;
wire sgf_result_o0__1_carry_i_10__1_n_0;
wire sgf_result_o0__1_carry_i_11__5_n_0;
wire sgf_result_o0__1_carry_i_12_n_0;
wire sgf_result_o0__1_carry_i_13_n_0;
wire sgf_result_o0__1_carry_i_14_n_0;
wire sgf_result_o0__1_carry_i_15_n_0;
wire sgf_result_o0__1_carry_i_16_n_0;
wire sgf_result_o0__1_carry_i_17_n_0;
wire sgf_result_o0__1_carry_i_18_n_0;
wire sgf_result_o0__1_carry_i_19_n_0;
wire sgf_result_o0__1_carry_i_1__5_n_0;
wire sgf_result_o0__1_carry_i_2__5_n_0;
wire sgf_result_o0__1_carry_i_3__5_n_0;
wire sgf_result_o0__1_carry_i_4__5_n_0;
wire sgf_result_o0__1_carry_i_5__5_n_0;
wire sgf_result_o0__1_carry_i_6__4_n_0;
wire sgf_result_o0__1_carry_i_7__5_n_0;
wire sgf_result_o0__1_carry_i_8__9_n_0;
wire sgf_result_o0__1_carry_i_8__9_n_1;
wire sgf_result_o0__1_carry_i_8__9_n_2;
wire sgf_result_o0__1_carry_i_8__9_n_3;
wire sgf_result_o0__1_carry_i_8__9_n_4;
wire sgf_result_o0__1_carry_i_8__9_n_5;
wire sgf_result_o0__1_carry_i_8__9_n_6;
wire sgf_result_o0__1_carry_i_8__9_n_7;
wire sgf_result_o0__1_carry_i_9__4_n_0;
wire sgf_result_o0__1_carry_i_9__4_n_1;
wire sgf_result_o0__1_carry_i_9__4_n_2;
wire sgf_result_o0__1_carry_i_9__4_n_3;
wire sgf_result_o0__1_carry_i_9__4_n_4;
wire sgf_result_o0__1_carry_i_9__4_n_5;
wire sgf_result_o0__1_carry_i_9__4_n_6;
wire sgf_result_o0__1_carry_i_9__4_n_7;
wire sgf_result_o1__0_carry_i_13__1_n_1;
wire sgf_result_o1__0_carry_i_13__1_n_3;
wire sgf_result_o1__0_carry_i_13__1_n_6;
wire sgf_result_o1__0_carry_i_13__1_n_7;
wire sgf_result_o1__0_carry_i_18__0_n_3;
wire sgf_result_o1__0_carry_i_20_n_0;
wire sgf_result_o1__0_carry_i_21_n_0;
wire sgf_result_o1__0_carry_i_22_n_0;
wire sgf_result_o1__0_carry_i_23_n_0;
wire sgf_result_o1__21_carry__0_i_10__0_n_0;
wire sgf_result_o1__21_carry__0_i_9__0_n_0;
wire sgf_result_o1__21_carry_i_10__0_n_0;
wire sgf_result_o1__21_carry_i_8__0_n_0;
wire sgf_result_o1__21_carry_i_9__0_n_0;
wire sgf_result_o1_carry_i_4__0_n_0;
wire [1:0]\sgf_result_o[23] ;
wire [3:0]\sgf_result_o[39] ;
wire [2:0]\sgf_result_o[43] ;
wire \sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:1]NLW_sgf_result_o1__0_carry_i_13__1_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__0_carry_i_13__1_O_UNCONNECTED;
wire [3:1]NLW_sgf_result_o1__0_carry_i_18__0_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__0_carry_i_18__0_O_UNCONNECTED;
Recursive_KOA__parameterized1 \EVEN1.left_high
(.DI({\EVEN1.middle_n_9 ,\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 }),
.\Data_A_i[14] ({S_B0__30_carry__0_i_5__0_n_0,S_B0__30_carry__0_i_6__0_n_0,S_B0__30_carry__0_i_7__0_n_0,S_B0__30_carry__0_i_8__0_n_0}),
.\Data_A_i[14]_0 ({S_B0__30_carry__1_i_5__0_n_0,S_B0__30_carry__1_i_6__0_n_0,S_B0__30_carry__1_i_7__0_n_0,S_B0__30_carry__1_i_8__0_n_0}),
.\Data_A_i[14]_1 ({\EVEN1.right_lower_n_8 ,\EVEN1.right_lower_n_9 }),
.\Data_A_i[17] ({S_B0__30_carry__0_i_1__0_n_0,S_B0__30_carry__0_i_2__0_n_0,S_B0__30_carry__0_i_3__0_n_0,S_B0__30_carry__0_i_4__0_n_0}),
.\Data_A_i[17]_0 ({\EVEN1.right_lower_n_4 ,\EVEN1.right_lower_n_5 ,\EVEN1.right_lower_n_6 ,\EVEN1.right_lower_n_7 }),
.\Data_A_i[18] ({\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 }),
.\Data_A_i[18]_0 (\EVEN1.middle_n_8 ),
.\Data_A_i[18]_1 ({S_B0__30_carry__2_i_1__0_n_0,S_B0__30_carry__2_i_2__0_n_0}),
.\Data_A_i[20] ({S_B0__30_carry__1_i_1__0_n_0,S_B0__30_carry__1_i_2__0_n_0,S_B0__30_carry__1_i_3__0_n_0,S_B0__30_carry__1_i_4__0_n_0}),
.\Data_A_i[20]_0 (S_B0__30_carry_i_13_n_0),
.\Data_A_i[23] ({\EVEN1.middle_n_27 ,\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.Data_A_i_IBUF(Data_A_i_IBUF[11:6]),
.\Data_B_i[18] ({\EVEN1.middle_n_23 ,\EVEN1.middle_n_24 ,\EVEN1.middle_n_25 ,\EVEN1.middle_n_26 }),
.\Data_B_i[18]_0 ({\EVEN1.middle_n_16 ,\EVEN1.middle_n_17 ,\EVEN1.middle_n_18 }),
.\Data_B_i[22] (S),
.Data_B_i_IBUF(Data_B_i_IBUF[11:6]),
.O({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 ,\EVEN1.middle_n_3 }),
.Q_middle_temp__2(Q_middle_temp__2),
.S({\EVEN1.middle_n_19 ,\EVEN1.middle_n_20 ,\EVEN1.middle_n_21 ,\EVEN1.middle_n_22 }),
.\sgf_result_o[19] ({\EVEN1.left_high_n_26 ,\EVEN1.left_high_n_27 ,\EVEN1.left_high_n_28 ,\EVEN1.left_high_n_29 }),
.\sgf_result_o[23] ({\sgf_result_o[23] ,\EVEN1.left_high_n_32 ,\EVEN1.left_high_n_33 }),
.\sgf_result_o[23]_0 (O),
.\sgf_result_o[27] ({\EVEN1.left_high_n_19 ,\EVEN1.left_high_n_20 ,\EVEN1.left_high_n_21 ,\EVEN1.left_high_n_22 }),
.\sgf_result_o[27]_0 ({\EVEN1.left_high_n_23 ,\EVEN1.left_high_n_24 }),
.\sgf_result_o[27]_1 ({\EVEN1.left_high_n_47 ,\EVEN1.left_high_n_48 ,\EVEN1.left_high_n_49 }),
.\sgf_result_o[43] (\EVEN1.left_high_n_25 ),
.\sgf_result_o[47] ({\EVEN1.left_high_n_11 ,\EVEN1.left_high_n_12 ,\EVEN1.left_high_n_13 ,\EVEN1.left_high_n_14 }),
.\sgf_result_o[47]_0 ({\EVEN1.left_high_n_15 ,\EVEN1.left_high_n_16 ,\EVEN1.left_high_n_17 ,\EVEN1.left_high_n_18 }),
.\sgf_result_o[47]_1 ({\EVEN1.left_high_n_36 ,\EVEN1.left_high_n_37 ,\EVEN1.left_high_n_38 }),
.\sgf_result_o[47]_2 ({\EVEN1.left_high_n_39 ,\EVEN1.left_high_n_40 ,\EVEN1.left_high_n_41 ,\EVEN1.left_high_n_42 }),
.\sgf_result_o[47]_3 ({\EVEN1.left_high_n_43 ,\EVEN1.left_high_n_44 ,\EVEN1.left_high_n_45 ,\EVEN1.left_high_n_46 }));
Recursive_KOA__parameterized9 \EVEN1.middle
(.CO(sgf_result_o1__0_carry_i_13__1_n_1),
.DI({sgf_result_o0__1_carry_i_1__5_n_0,sgf_result_o0__1_carry_i_2__5_n_0,sgf_result_o0__1_carry_i_3__5_n_0}),
.\Data_A_i[14] ({\EVEN1.left_high_n_19 ,\EVEN1.left_high_n_20 ,\EVEN1.left_high_n_21 ,\EVEN1.left_high_n_22 }),
.\Data_A_i[14]_0 ({\EVEN1.left_high_n_43 ,\EVEN1.left_high_n_44 ,\EVEN1.left_high_n_45 ,\EVEN1.left_high_n_46 }),
.\Data_A_i[14]_1 ({\EVEN1.left_high_n_23 ,\EVEN1.left_high_n_24 }),
.\Data_A_i[17] (\sgf_result_o[47]_0 [1:0]),
.\Data_A_i[17]_0 ({\EVEN1.left_high_n_11 ,\EVEN1.left_high_n_12 ,\EVEN1.left_high_n_13 ,\EVEN1.left_high_n_14 }),
.\Data_A_i[17]_1 ({\EVEN1.left_high_n_15 ,\EVEN1.left_high_n_16 ,\EVEN1.left_high_n_17 ,\EVEN1.left_high_n_18 }),
.\Data_A_i[17]_2 ({\EVEN1.left_high_n_39 ,\EVEN1.left_high_n_40 ,\EVEN1.left_high_n_41 ,\EVEN1.left_high_n_42 }),
.\Data_A_i[18] ({sgf_result_o0__1_carry__0_i_4__5_n_0,sgf_result_o0__1_carry__0_i_5__7_n_0,sgf_result_o0__1_carry__0_i_6__5_n_0}),
.\Data_A_i[18]_0 ({sgf_result_o0__1_carry_i_9__4_n_4,sgf_result_o0__1_carry_i_9__4_n_5,sgf_result_o0__1_carry_i_9__4_n_6,sgf_result_o0__1_carry_i_9__4_n_7}),
.\Data_A_i[18]_1 (sgf_result_o1__21_carry_i_10__0_n_0),
.\Data_A_i[18]_2 (sgf_result_o1__21_carry__0_i_10__0_n_0),
.\Data_A_i[18]_3 (sgf_result_o1__21_carry_i_8__0_n_0),
.\Data_A_i[18]_4 (sgf_result_o1__21_carry_i_9__0_n_0),
.\Data_A_i[20] (\Data_A_i[20] ),
.\Data_A_i[22] (sgf_result_o1_carry_i_4__0_n_0),
.\Data_A_i[23] ({\EVEN1.left_high_n_28 ,\EVEN1.left_high_n_29 }),
.\Data_A_i[23]_0 ({\EVEN1.left_high_n_36 ,\EVEN1.left_high_n_37 ,\EVEN1.left_high_n_38 ,\Data_A_i[17] }),
.\Data_A_i[23]_1 ({\Data_A_i[23] ,\EVEN1.left_high_n_47 ,\EVEN1.left_high_n_48 ,\EVEN1.left_high_n_49 }),
.Data_A_i_IBUF({Data_A_i_IBUF[7:6],Data_A_i_IBUF[0]}),
.\Data_B_i[12] (\sgf_result_o[47] ),
.\Data_B_i[18] ({sgf_result_o0__1_carry__0_i_1__5_n_0,sgf_result_o0__1_carry__0_i_2__4_n_0,sgf_result_o0__1_carry__0_i_3__6_n_0}),
.\Data_B_i[18]_0 ({sgf_result_o0__1_carry_i_8__9_n_4,sgf_result_o0__1_carry_i_8__9_n_5,sgf_result_o0__1_carry_i_8__9_n_6,sgf_result_o0__1_carry_i_8__9_n_7}),
.\Data_B_i[18]_1 ({sgf_result_o1__0_carry_i_13__1_n_6,sgf_result_o1__0_carry_i_13__1_n_7}),
.\Data_B_i[18]_2 (sgf_result_o1__21_carry__0_i_9__0_n_0),
.\Data_B_i[18]_3 (S_B0_carry__0_i_5__0_n_0),
.\Data_B_i[18]_4 (\EVEN1.left_high_n_25 ),
.Data_B_i_IBUF({Data_B_i_IBUF[7:6],Data_B_i_IBUF[0]}),
.O({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 ,\EVEN1.middle_n_3 }),
.Q_middle_temp__2(Q_middle_temp__2[3]),
.S({sgf_result_o0__1_carry_i_4__5_n_0,sgf_result_o0__1_carry_i_5__5_n_0,sgf_result_o0__1_carry_i_6__4_n_0,sgf_result_o0__1_carry_i_7__5_n_0}),
.p_0_in(p_0_in),
.\sgf_result_o[15] (\EVEN1.middle_n_12 ),
.\sgf_result_o[15]_0 (\EVEN1.middle_n_13 ),
.\sgf_result_o[15]_1 (\EVEN1.middle_n_14 ),
.\sgf_result_o[15]_2 (\EVEN1.middle_n_15 ),
.\sgf_result_o[19] ({\EVEN1.middle_n_23 ,\EVEN1.middle_n_24 ,\EVEN1.middle_n_25 ,\EVEN1.middle_n_26 }),
.\sgf_result_o[23] ({\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 }),
.\sgf_result_o[23]_0 (\EVEN1.middle_n_8 ),
.\sgf_result_o[23]_1 ({\EVEN1.middle_n_16 ,\EVEN1.middle_n_17 ,\EVEN1.middle_n_18 }),
.\sgf_result_o[39] (\sgf_result_o[39] ),
.\sgf_result_o[43] (\sgf_result_o[43] ),
.\sgf_result_o[47] ({\EVEN1.middle_n_9 ,\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 }),
.\sgf_result_o[47]_0 ({\EVEN1.middle_n_19 ,\EVEN1.middle_n_20 ,\EVEN1.middle_n_21 ,\EVEN1.middle_n_22 }),
.\sgf_result_o[47]_1 ({\EVEN1.middle_n_27 ,\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_3 ));
Recursive_KOA__parameterized5 \EVEN1.right_lower
(.\Data_A_i[14] (S_B0__0_carry_i_8__1_n_0),
.\Data_A_i[14]_0 (S_B0__0_carry_i_12__1_n_0),
.\Data_A_i[14]_1 (S_B0__0_carry__0_i_7__1_n_0),
.\Data_A_i[17] (S_B0__0_carry_i_9__1_n_0),
.\Data_A_i[17]_0 (S_B0__0_carry_i_11__1_n_0),
.\Data_A_i[17]_1 (S_B0__0_carry__0_i_8__1_n_0),
.Data_A_i_IBUF(Data_A_i_IBUF[5:0]),
.\Data_B_i[12] (\sgf_result_o[47] ),
.\Data_B_i[13] (S_B0__0_carry__0_i_9__1_n_0),
.\Data_B_i[15] (S_B0__0_carry_i_13__0_n_0),
.\Data_B_i[16] (S_B0__0_carry__0_i_10__1_n_0),
.\Data_B_i[16]_0 (S_B0__30_carry__1_i_13__0_n_0),
.Data_B_i_IBUF(Data_B_i_IBUF[5:0]),
.S(S_B0__30_carry_i_17_n_0),
.\sgf_result_o[47] (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_0 ({\EVEN1.right_lower_n_4 ,\EVEN1.right_lower_n_5 ,\EVEN1.right_lower_n_6 ,\EVEN1.right_lower_n_7 }),
.\sgf_result_o[47]_1 ({\EVEN1.right_lower_n_8 ,\EVEN1.right_lower_n_9 }));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__0_carry__0_i_10__1
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__0_carry__0_i_10__1_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_7__1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry__0_i_7__1_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_8__1
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry__0_i_8__1_n_0));
LUT6 #(
.INIT(64'h55FF7FFF7FFFFFFF))
S_B0__0_carry__0_i_9__1
(.I0(Data_A_i_IBUF[2]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_B_i_IBUF[2]),
.I4(Data_A_i_IBUF[1]),
.I5(Data_B_i_IBUF[1]),
.O(S_B0__0_carry__0_i_9__1_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_10__0
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[0]),
.O(\sgf_result_o[47] ));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_11__1
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_11__1_n_0));
LUT6 #(
.INIT(64'h12E2EA6A48C040C0))
S_B0__0_carry_i_12__1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_12__1_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_13__0
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_B_i_IBUF[3]),
.O(S_B0__0_carry_i_13__0_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_8__1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_8__1_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_9__1
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_9__1_n_0));
(* HLUTNM = "lutpair35" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_1__0
(.I0(Q_middle_temp__2[6]),
.I1(\EVEN1.left_high_n_33 ),
.I2(\EVEN1.right_lower_n_7 ),
.O(S_B0__30_carry__0_i_1__0_n_0));
(* HLUTNM = "lutpair34" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_2__0
(.I0(Q_middle_temp__2[5]),
.I1(\EVEN1.left_high_n_26 ),
.I2(\sgf_result_o[47]_0 [3]),
.O(S_B0__30_carry__0_i_2__0_n_0));
(* HLUTNM = "lutpair33" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_3__0
(.I0(Q_middle_temp__2[4]),
.I1(\EVEN1.left_high_n_27 ),
.I2(\sgf_result_o[47]_0 [2]),
.O(S_B0__30_carry__0_i_3__0_n_0));
(* HLUTNM = "lutpair32" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_4__0
(.I0(Q_middle_temp__2[3]),
.I1(\EVEN1.left_high_n_28 ),
.I2(\sgf_result_o[47]_0 [1]),
.O(S_B0__30_carry__0_i_4__0_n_0));
(* HLUTNM = "lutpair36" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_5__0
(.I0(Q_middle_temp__2[7]),
.I1(\EVEN1.left_high_n_32 ),
.I2(\EVEN1.right_lower_n_6 ),
.I3(S_B0__30_carry__0_i_1__0_n_0),
.O(S_B0__30_carry__0_i_5__0_n_0));
(* HLUTNM = "lutpair35" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_6__0
(.I0(Q_middle_temp__2[6]),
.I1(\EVEN1.left_high_n_33 ),
.I2(\EVEN1.right_lower_n_7 ),
.I3(S_B0__30_carry__0_i_2__0_n_0),
.O(S_B0__30_carry__0_i_6__0_n_0));
(* HLUTNM = "lutpair34" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_7__0
(.I0(Q_middle_temp__2[5]),
.I1(\EVEN1.left_high_n_26 ),
.I2(\sgf_result_o[47]_0 [3]),
.I3(S_B0__30_carry__0_i_3__0_n_0),
.O(S_B0__30_carry__0_i_7__0_n_0));
(* HLUTNM = "lutpair33" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_8__0
(.I0(Q_middle_temp__2[4]),
.I1(\EVEN1.left_high_n_27 ),
.I2(\sgf_result_o[47]_0 [2]),
.I3(S_B0__30_carry__0_i_4__0_n_0),
.O(S_B0__30_carry__0_i_8__0_n_0));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__30_carry__1_i_13__0
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__1_i_13__0_n_0));
(* HLUTNM = "lutpair39" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_1__0
(.I0(Q_middle_temp__2[10]),
.I1(O[0]),
.I2(\EVEN1.right_lower_n_9 ),
.O(S_B0__30_carry__1_i_1__0_n_0));
(* HLUTNM = "lutpair38" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_2__0
(.I0(Q_middle_temp__2[9]),
.I1(\sgf_result_o[23] [1]),
.I2(\EVEN1.right_lower_n_4 ),
.O(S_B0__30_carry__1_i_2__0_n_0));
(* HLUTNM = "lutpair37" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_3__0
(.I0(Q_middle_temp__2[8]),
.I1(\sgf_result_o[23] [0]),
.I2(\EVEN1.right_lower_n_5 ),
.O(S_B0__30_carry__1_i_3__0_n_0));
(* HLUTNM = "lutpair36" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_4__0
(.I0(Q_middle_temp__2[7]),
.I1(\EVEN1.left_high_n_32 ),
.I2(\EVEN1.right_lower_n_6 ),
.O(S_B0__30_carry__1_i_4__0_n_0));
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_5__0
(.I0(S_B0__30_carry__1_i_1__0_n_0),
.I1(Q_middle_temp__2[11]),
.I2(O[1]),
.I3(\EVEN1.right_lower_n_8 ),
.O(S_B0__30_carry__1_i_5__0_n_0));
(* HLUTNM = "lutpair39" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_6__0
(.I0(Q_middle_temp__2[10]),
.I1(O[0]),
.I2(\EVEN1.right_lower_n_9 ),
.I3(S_B0__30_carry__1_i_2__0_n_0),
.O(S_B0__30_carry__1_i_6__0_n_0));
(* HLUTNM = "lutpair38" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_7__0
(.I0(Q_middle_temp__2[9]),
.I1(\sgf_result_o[23] [1]),
.I2(\EVEN1.right_lower_n_4 ),
.I3(S_B0__30_carry__1_i_3__0_n_0),
.O(S_B0__30_carry__1_i_7__0_n_0));
(* HLUTNM = "lutpair37" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_8__0
(.I0(Q_middle_temp__2[8]),
.I1(\sgf_result_o[23] [0]),
.I2(\EVEN1.right_lower_n_5 ),
.I3(S_B0__30_carry__1_i_4__0_n_0),
.O(S_B0__30_carry__1_i_8__0_n_0));
LUT1 #(
.INIT(2'h1))
S_B0__30_carry__2_i_1__0
(.I0(Q_middle_temp__2[13]),
.O(S_B0__30_carry__2_i_1__0_n_0));
LUT4 #(
.INIT(16'h8E71))
S_B0__30_carry__2_i_2__0
(.I0(\EVEN1.right_lower_n_8 ),
.I1(O[1]),
.I2(Q_middle_temp__2[11]),
.I3(Q_middle_temp__2[12]),
.O(S_B0__30_carry__2_i_2__0_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__30_carry_i_13
(.I0(Data_B_i_IBUF[7]),
.I1(Data_A_i_IBUF[7]),
.I2(Data_B_i_IBUF[8]),
.I3(Data_A_i_IBUF[6]),
.I4(Data_B_i_IBUF[6]),
.I5(Data_A_i_IBUF[8]),
.O(S_B0__30_carry_i_13_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__30_carry_i_17
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__30_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
S_B0_carry__0_i_5__0
(.I0(p_0_in[1]),
.I1(sgf_result_o1__0_carry_i_13__1_n_6),
.O(S_B0_carry__0_i_5__0_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_1__5
(.I0(sgf_result_o0__1_carry_i_9__4_n_4),
.I1(sgf_result_o0__1_carry_i_8__9_n_4),
.O(sgf_result_o0__1_carry__0_i_1__5_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
sgf_result_o0__1_carry__0_i_2__4
(.I0(sgf_result_o0__1_carry_i_10__1_n_0),
.I1(sgf_result_o0__1_carry_i_8__9_n_6),
.I2(sgf_result_o0__1_carry_i_9__4_n_7),
.I3(sgf_result_o0__1_carry_i_8__9_n_7),
.I4(sgf_result_o0__1_carry_i_9__4_n_4),
.I5(sgf_result_o0__1_carry__0_i_7__2_n_0),
.O(sgf_result_o0__1_carry__0_i_2__4_n_0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
sgf_result_o0__1_carry__0_i_3__6
(.I0(sgf_result_o0__1_carry_i_10__1_n_0),
.I1(sgf_result_o0__1_carry_i_8__9_n_6),
.I2(sgf_result_o0__1_carry_i_9__4_n_7),
.I3(sgf_result_o0__1_carry_i_8__9_n_7),
.I4(sgf_result_o0__1_carry_i_9__4_n_4),
.I5(sgf_result_o0__1_carry__0_i_7__2_n_0),
.O(sgf_result_o0__1_carry__0_i_3__6_n_0));
LUT6 #(
.INIT(64'h173F8080C0000000))
sgf_result_o0__1_carry__0_i_4__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_6),
.I1(sgf_result_o0__1_carry_i_9__4_n_5),
.I2(sgf_result_o0__1_carry_i_8__9_n_5),
.I3(sgf_result_o0__1_carry_i_9__4_n_6),
.I4(sgf_result_o0__1_carry_i_8__9_n_4),
.I5(sgf_result_o0__1_carry_i_9__4_n_4),
.O(sgf_result_o0__1_carry__0_i_4__5_n_0));
LUT6 #(
.INIT(64'h9666699969996999))
sgf_result_o0__1_carry__0_i_5__7
(.I0(sgf_result_o0__1_carry__0_i_2__4_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__4_n_0),
.I2(sgf_result_o0__1_carry_i_9__4_n_4),
.I3(sgf_result_o0__1_carry_i_8__9_n_5),
.I4(sgf_result_o0__1_carry_i_9__4_n_5),
.I5(sgf_result_o0__1_carry_i_8__9_n_4),
.O(sgf_result_o0__1_carry__0_i_5__7_n_0));
LUT6 #(
.INIT(64'h56666AAA6AAA6AAA))
sgf_result_o0__1_carry__0_i_6__5
(.I0(sgf_result_o0__1_carry__0_i_3__6_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__2_n_0),
.I2(sgf_result_o0__1_carry_i_9__4_n_6),
.I3(sgf_result_o0__1_carry_i_8__9_n_5),
.I4(sgf_result_o0__1_carry_i_9__4_n_7),
.I5(sgf_result_o0__1_carry_i_8__9_n_4),
.O(sgf_result_o0__1_carry__0_i_6__5_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry__0_i_7__2
(.I0(sgf_result_o0__1_carry_i_8__9_n_6),
.I1(sgf_result_o0__1_carry_i_9__4_n_4),
.I2(sgf_result_o0__1_carry_i_9__4_n_5),
.I3(sgf_result_o0__1_carry_i_8__9_n_5),
.I4(sgf_result_o0__1_carry_i_9__4_n_6),
.I5(sgf_result_o0__1_carry_i_8__9_n_4),
.O(sgf_result_o0__1_carry__0_i_7__2_n_0));
LUT6 #(
.INIT(64'h07777FFF7FFF7FFF))
sgf_result_o0__1_carry__0_i_8__4
(.I0(sgf_result_o0__1_carry_i_8__9_n_4),
.I1(sgf_result_o0__1_carry_i_9__4_n_6),
.I2(sgf_result_o0__1_carry_i_8__9_n_5),
.I3(sgf_result_o0__1_carry_i_9__4_n_5),
.I4(sgf_result_o0__1_carry_i_9__4_n_4),
.I5(sgf_result_o0__1_carry_i_8__9_n_6),
.O(sgf_result_o0__1_carry__0_i_8__4_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_9__2
(.I0(sgf_result_o0__1_carry_i_9__4_n_5),
.I1(sgf_result_o0__1_carry_i_8__9_n_6),
.O(sgf_result_o0__1_carry__0_i_9__2_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_10__1
(.I0(sgf_result_o0__1_carry_i_9__4_n_6),
.I1(sgf_result_o0__1_carry_i_8__9_n_5),
.O(sgf_result_o0__1_carry_i_10__1_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_11__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_7),
.I1(sgf_result_o0__1_carry_i_9__4_n_4),
.O(sgf_result_o0__1_carry_i_11__5_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_12
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[9]),
.O(sgf_result_o0__1_carry_i_12_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_13
(.I0(Data_B_i_IBUF[2]),
.I1(Data_B_i_IBUF[8]),
.O(sgf_result_o0__1_carry_i_13_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_14
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[7]),
.O(sgf_result_o0__1_carry_i_14_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_15
(.I0(Data_B_i_IBUF[0]),
.I1(Data_B_i_IBUF[6]),
.O(sgf_result_o0__1_carry_i_15_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_16
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[9]),
.O(sgf_result_o0__1_carry_i_16_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_17
(.I0(Data_A_i_IBUF[2]),
.I1(Data_A_i_IBUF[8]),
.O(sgf_result_o0__1_carry_i_17_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_18
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[7]),
.O(sgf_result_o0__1_carry_i_18_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_19
(.I0(Data_A_i_IBUF[0]),
.I1(Data_A_i_IBUF[6]),
.O(sgf_result_o0__1_carry_i_19_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_1__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_6),
.I1(sgf_result_o0__1_carry_i_9__4_n_5),
.I2(sgf_result_o0__1_carry_i_9__4_n_6),
.I3(sgf_result_o0__1_carry_i_8__9_n_5),
.I4(sgf_result_o0__1_carry_i_9__4_n_7),
.I5(sgf_result_o0__1_carry_i_8__9_n_4),
.O(sgf_result_o0__1_carry_i_1__5_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_2__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_6),
.I1(sgf_result_o0__1_carry_i_9__4_n_6),
.I2(sgf_result_o0__1_carry_i_8__9_n_5),
.I3(sgf_result_o0__1_carry_i_9__4_n_7),
.O(sgf_result_o0__1_carry_i_2__5_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_3__5
(.I0(sgf_result_o0__1_carry_i_9__4_n_7),
.I1(sgf_result_o0__1_carry_i_8__9_n_6),
.O(sgf_result_o0__1_carry_i_3__5_n_0));
LUT6 #(
.INIT(64'h99A5C30F665A3CF0))
sgf_result_o0__1_carry_i_4__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_4),
.I1(sgf_result_o0__1_carry_i_9__4_n_5),
.I2(sgf_result_o0__1_carry_i_10__1_n_0),
.I3(sgf_result_o0__1_carry_i_8__9_n_6),
.I4(sgf_result_o0__1_carry_i_9__4_n_7),
.I5(sgf_result_o0__1_carry_i_11__5_n_0),
.O(sgf_result_o0__1_carry_i_4__5_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_5__5
(.I0(sgf_result_o0__1_carry_i_9__4_n_7),
.I1(sgf_result_o0__1_carry_i_8__9_n_5),
.I2(sgf_result_o0__1_carry_i_9__4_n_6),
.I3(sgf_result_o0__1_carry_i_8__9_n_6),
.I4(sgf_result_o0__1_carry_i_9__4_n_5),
.I5(sgf_result_o0__1_carry_i_8__9_n_7),
.O(sgf_result_o0__1_carry_i_5__5_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_6__4
(.I0(sgf_result_o0__1_carry_i_9__4_n_6),
.I1(sgf_result_o0__1_carry_i_8__9_n_7),
.I2(sgf_result_o0__1_carry_i_8__9_n_6),
.I3(sgf_result_o0__1_carry_i_9__4_n_7),
.O(sgf_result_o0__1_carry_i_6__4_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_7__5
(.I0(sgf_result_o0__1_carry_i_8__9_n_7),
.I1(sgf_result_o0__1_carry_i_9__4_n_7),
.O(sgf_result_o0__1_carry_i_7__5_n_0));
CARRY4 sgf_result_o0__1_carry_i_8__9
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_8__9_n_0,sgf_result_o0__1_carry_i_8__9_n_1,sgf_result_o0__1_carry_i_8__9_n_2,sgf_result_o0__1_carry_i_8__9_n_3}),
.CYINIT(1'b0),
.DI(Data_B_i_IBUF[3:0]),
.O({sgf_result_o0__1_carry_i_8__9_n_4,sgf_result_o0__1_carry_i_8__9_n_5,sgf_result_o0__1_carry_i_8__9_n_6,sgf_result_o0__1_carry_i_8__9_n_7}),
.S({sgf_result_o0__1_carry_i_12_n_0,sgf_result_o0__1_carry_i_13_n_0,sgf_result_o0__1_carry_i_14_n_0,sgf_result_o0__1_carry_i_15_n_0}));
CARRY4 sgf_result_o0__1_carry_i_9__4
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_9__4_n_0,sgf_result_o0__1_carry_i_9__4_n_1,sgf_result_o0__1_carry_i_9__4_n_2,sgf_result_o0__1_carry_i_9__4_n_3}),
.CYINIT(1'b0),
.DI(Data_A_i_IBUF[3:0]),
.O({sgf_result_o0__1_carry_i_9__4_n_4,sgf_result_o0__1_carry_i_9__4_n_5,sgf_result_o0__1_carry_i_9__4_n_6,sgf_result_o0__1_carry_i_9__4_n_7}),
.S({sgf_result_o0__1_carry_i_16_n_0,sgf_result_o0__1_carry_i_17_n_0,sgf_result_o0__1_carry_i_18_n_0,sgf_result_o0__1_carry_i_19_n_0}));
CARRY4 sgf_result_o1__0_carry_i_13__1
(.CI(sgf_result_o0__1_carry_i_8__9_n_0),
.CO({NLW_sgf_result_o1__0_carry_i_13__1_CO_UNCONNECTED[3],sgf_result_o1__0_carry_i_13__1_n_1,NLW_sgf_result_o1__0_carry_i_13__1_CO_UNCONNECTED[1],sgf_result_o1__0_carry_i_13__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_B_i_IBUF[5:4]}),
.O({NLW_sgf_result_o1__0_carry_i_13__1_O_UNCONNECTED[3:2],sgf_result_o1__0_carry_i_13__1_n_6,sgf_result_o1__0_carry_i_13__1_n_7}),
.S({1'b0,1'b1,sgf_result_o1__0_carry_i_20_n_0,sgf_result_o1__0_carry_i_21_n_0}));
CARRY4 sgf_result_o1__0_carry_i_18__0
(.CI(sgf_result_o0__1_carry_i_9__4_n_0),
.CO({NLW_sgf_result_o1__0_carry_i_18__0_CO_UNCONNECTED[3],p_0_in[2],NLW_sgf_result_o1__0_carry_i_18__0_CO_UNCONNECTED[1],sgf_result_o1__0_carry_i_18__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_A_i_IBUF[5:4]}),
.O({NLW_sgf_result_o1__0_carry_i_18__0_O_UNCONNECTED[3:2],p_0_in[1:0]}),
.S({1'b0,1'b1,sgf_result_o1__0_carry_i_22_n_0,sgf_result_o1__0_carry_i_23_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_20
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[11]),
.O(sgf_result_o1__0_carry_i_20_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_21
(.I0(Data_B_i_IBUF[4]),
.I1(Data_B_i_IBUF[10]),
.O(sgf_result_o1__0_carry_i_21_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_22
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[11]),
.O(sgf_result_o1__0_carry_i_22_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_23
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[10]),
.O(sgf_result_o1__0_carry_i_23_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
sgf_result_o1__21_carry__0_i_10__0
(.I0(sgf_result_o1__0_carry_i_13__1_n_6),
.I1(p_0_in[1]),
.I2(sgf_result_o1__0_carry_i_13__1_n_1),
.I3(p_0_in[0]),
.I4(sgf_result_o1__0_carry_i_13__1_n_7),
.I5(p_0_in[2]),
.O(sgf_result_o1__21_carry__0_i_10__0_n_0));
LUT6 #(
.INIT(64'hAA00800080000000))
sgf_result_o1__21_carry__0_i_9__0
(.I0(p_0_in[2]),
.I1(sgf_result_o1__0_carry_i_13__1_n_7),
.I2(p_0_in[0]),
.I3(sgf_result_o1__0_carry_i_13__1_n_1),
.I4(p_0_in[1]),
.I5(sgf_result_o1__0_carry_i_13__1_n_6),
.O(sgf_result_o1__21_carry__0_i_9__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7888))
sgf_result_o1__21_carry_i_10__0
(.I0(sgf_result_o1__0_carry_i_13__1_n_6),
.I1(p_0_in[0]),
.I2(p_0_in[1]),
.I3(sgf_result_o1__0_carry_i_13__1_n_7),
.O(sgf_result_o1__21_carry_i_10__0_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
sgf_result_o1__21_carry_i_8__0
(.I0(sgf_result_o1__0_carry_i_13__1_n_6),
.I1(p_0_in[1]),
.I2(sgf_result_o1__0_carry_i_13__1_n_1),
.I3(p_0_in[0]),
.I4(sgf_result_o1__0_carry_i_13__1_n_7),
.I5(p_0_in[2]),
.O(sgf_result_o1__21_carry_i_8__0_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
sgf_result_o1__21_carry_i_9__0
(.I0(sgf_result_o1__0_carry_i_13__1_n_6),
.I1(p_0_in[1]),
.I2(sgf_result_o1__0_carry_i_13__1_n_1),
.I3(p_0_in[0]),
.I4(sgf_result_o1__0_carry_i_13__1_n_7),
.I5(p_0_in[2]),
.O(sgf_result_o1__21_carry_i_9__0_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1_carry_i_4__0
(.I0(\EVEN1.middle_n_15 ),
.I1(\EVEN1.middle_n_12 ),
.I2(\EVEN1.middle_n_14 ),
.I3(\EVEN1.middle_n_13 ),
.I4(sgf_result_o1__0_carry_i_13__1_n_7),
.I5(sgf_result_o0__1_carry_i_8__9_n_7),
.O(sgf_result_o1_carry_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized1
(Q_middle_temp__2,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[27] ,
\sgf_result_o[27]_0 ,
\sgf_result_o[43] ,
\sgf_result_o[19] ,
\sgf_result_o[23] ,
\sgf_result_o[23]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[27]_1 ,
O,
S,
\Data_A_i[18] ,
\Data_B_i[18] ,
\Data_A_i[18]_0 ,
\Data_B_i[18]_0 ,
DI,
\Data_A_i[23] ,
\Data_A_i[17] ,
\Data_A_i[14] ,
\Data_A_i[20] ,
\Data_A_i[14]_0 ,
\Data_A_i[18]_1 ,
Data_A_i_IBUF,
Data_B_i_IBUF,
\Data_A_i[20]_0 ,
\Data_B_i[22] ,
\Data_A_i[17]_0 ,
\Data_A_i[14]_1 );
output [10:0]Q_middle_temp__2;
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[27] ;
output [1:0]\sgf_result_o[27]_0 ;
output \sgf_result_o[43] ;
output [3:0]\sgf_result_o[19] ;
output [3:0]\sgf_result_o[23] ;
output [1:0]\sgf_result_o[23]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [2:0]\sgf_result_o[27]_1 ;
input [3:0]O;
input [3:0]S;
input [3:0]\Data_A_i[18] ;
input [3:0]\Data_B_i[18] ;
input [0:0]\Data_A_i[18]_0 ;
input [2:0]\Data_B_i[18]_0 ;
input [2:0]DI;
input [3:0]\Data_A_i[23] ;
input [3:0]\Data_A_i[17] ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[20] ;
input [3:0]\Data_A_i[14]_0 ;
input [1:0]\Data_A_i[18]_1 ;
input [5:0]Data_A_i_IBUF;
input [5:0]Data_B_i_IBUF;
input [0:0]\Data_A_i[20]_0 ;
input [0:0]\Data_B_i[22] ;
input [3:0]\Data_A_i[17]_0 ;
input [1:0]\Data_A_i[14]_1 ;
wire [2:0]DI;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [1:0]\Data_A_i[14]_1 ;
wire [3:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[17]_0 ;
wire [3:0]\Data_A_i[18] ;
wire [0:0]\Data_A_i[18]_0 ;
wire [1:0]\Data_A_i[18]_1 ;
wire [3:0]\Data_A_i[20] ;
wire [0:0]\Data_A_i[20]_0 ;
wire [3:0]\Data_A_i[23] ;
wire [5:0]Data_A_i_IBUF;
wire [3:0]\Data_B_i[18] ;
wire [2:0]\Data_B_i[18]_0 ;
wire [0:0]\Data_B_i[22] ;
wire [5:0]Data_B_i_IBUF;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_28 ;
wire \EVEN1.middle_n_29 ;
wire \EVEN1.middle_n_30 ;
wire \EVEN1.middle_n_31 ;
wire \EVEN1.middle_n_32 ;
wire \EVEN1.middle_n_33 ;
wire \EVEN1.middle_n_34 ;
wire \EVEN1.middle_n_35 ;
wire \EVEN1.middle_n_36 ;
wire \EVEN1.middle_n_37 ;
wire \EVEN1.middle_n_38 ;
wire [3:0]O;
wire [10:0]Q_middle_temp__2;
wire [3:0]S;
wire S_B0__0_carry__0_i_10__2_n_0;
wire S_B0__0_carry__0_i_7__2_n_0;
wire S_B0__0_carry__0_i_8__2_n_0;
wire S_B0__0_carry__0_i_9__2_n_0;
wire S_B0__0_carry__0_n_1;
wire S_B0__0_carry__0_n_2;
wire S_B0__0_carry__0_n_3;
wire S_B0__0_carry__0_n_4;
wire S_B0__0_carry__0_n_5;
wire S_B0__0_carry__0_n_6;
wire S_B0__0_carry__0_n_7;
wire S_B0__0_carry_i_11__2_n_0;
wire S_B0__0_carry_i_12__2_n_0;
wire S_B0__0_carry_i_13__1_n_0;
wire S_B0__0_carry_i_8__2_n_0;
wire S_B0__0_carry_i_9__2_n_0;
wire S_B0__0_carry_n_0;
wire S_B0__0_carry_n_1;
wire S_B0__0_carry_n_2;
wire S_B0__0_carry_n_3;
wire S_B0__0_carry_n_4;
wire S_B0__0_carry_n_5;
wire S_B0__0_carry_n_6;
wire S_B0__0_carry_n_7;
wire S_B0__30_carry__0_i_11__0_n_0;
wire S_B0__30_carry__0_i_12_n_0;
wire S_B0__30_carry__0_i_13_n_0;
wire S_B0__30_carry__0_i_14_n_0;
wire S_B0__30_carry__1_i_12_n_0;
wire S_B0__30_carry_i_10_n_0;
wire S_B0__30_carry_i_11_n_0;
wire S_B0__30_carry_i_12__0_n_0;
wire sgf_result_o0__1_carry__0_i_1__4_n_0;
wire sgf_result_o0__1_carry__0_i_2__3_n_0;
wire sgf_result_o0__1_carry__0_i_3__5_n_0;
wire sgf_result_o0__1_carry__0_i_4__4_n_0;
wire sgf_result_o0__1_carry__0_i_5__6_n_0;
wire sgf_result_o0__1_carry__0_i_6__4_n_0;
wire sgf_result_o0__1_carry__0_i_7__1_n_0;
wire sgf_result_o0__1_carry__0_i_8__3_n_0;
wire sgf_result_o0__1_carry__0_i_9__7_n_0;
wire sgf_result_o0__1_carry_i_10__9_n_0;
wire sgf_result_o0__1_carry_i_11__4_n_0;
wire sgf_result_o0__1_carry_i_12__4_n_0;
wire sgf_result_o0__1_carry_i_13__3_n_0;
wire sgf_result_o0__1_carry_i_14__6_n_0;
wire sgf_result_o0__1_carry_i_1__4_n_0;
wire sgf_result_o0__1_carry_i_2__4_n_0;
wire sgf_result_o0__1_carry_i_3__4_n_0;
wire sgf_result_o0__1_carry_i_4__4_n_0;
wire sgf_result_o0__1_carry_i_5__4_n_0;
wire sgf_result_o0__1_carry_i_6__3_n_0;
wire sgf_result_o0__1_carry_i_7__4_n_0;
wire sgf_result_o0__1_carry_i_8__3_n_0;
wire sgf_result_o0__1_carry_i_9__11_n_0;
wire [3:0]\sgf_result_o[19] ;
wire [3:0]\sgf_result_o[23] ;
wire [1:0]\sgf_result_o[23]_0 ;
wire [3:0]\sgf_result_o[27] ;
wire [1:0]\sgf_result_o[27]_0 ;
wire [2:0]\sgf_result_o[27]_1 ;
wire \sgf_result_o[43] ;
wire [3:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:3]NLW_S_B0__0_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized4 \EVEN1.middle
(.DI({sgf_result_o0__1_carry_i_1__4_n_0,sgf_result_o0__1_carry_i_2__4_n_0,sgf_result_o0__1_carry_i_3__4_n_0}),
.\Data_A_i[14] (\Data_A_i[14] ),
.\Data_A_i[14]_0 (\Data_A_i[14]_0 ),
.\Data_A_i[14]_1 (\Data_A_i[14]_1 ),
.\Data_A_i[17] (DI),
.\Data_A_i[17]_0 (\Data_A_i[17] ),
.\Data_A_i[17]_1 (\Data_A_i[17]_0 ),
.\Data_A_i[18] (S),
.\Data_A_i[18]_0 (\Data_A_i[18] ),
.\Data_A_i[18]_1 (\Data_A_i[18]_0 ),
.\Data_A_i[18]_2 (\Data_A_i[18]_1 ),
.\Data_A_i[19] ({sgf_result_o0__1_carry__0_i_4__4_n_0,sgf_result_o0__1_carry__0_i_5__6_n_0,sgf_result_o0__1_carry__0_i_6__4_n_0}),
.\Data_A_i[20] (\Data_A_i[20] ),
.\Data_A_i[20]_0 (S_B0__0_carry_i_8__2_n_0),
.\Data_A_i[20]_1 (S_B0__0_carry_i_11__2_n_0),
.\Data_A_i[20]_2 (S_B0__0_carry__0_i_7__2_n_0),
.\Data_A_i[20]_3 ({S_B0__30_carry__0_i_11__0_n_0,S_B0__30_carry__0_i_12_n_0,S_B0__30_carry__0_i_13_n_0,S_B0__30_carry__0_i_14_n_0}),
.\Data_A_i[23] ({sgf_result_o0__1_carry__0_i_1__4_n_0,sgf_result_o0__1_carry__0_i_2__3_n_0,sgf_result_o0__1_carry__0_i_3__5_n_0}),
.\Data_A_i[23]_0 (\Data_A_i[23] ),
.\Data_A_i[23]_1 (S_B0__0_carry_i_9__2_n_0),
.\Data_A_i[23]_2 (S_B0__0_carry_i_12__2_n_0),
.\Data_A_i[23]_3 (S_B0__0_carry__0_i_8__2_n_0),
.\Data_A_i[23]_4 ({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.\Data_A_i[23]_5 ({S_B0__30_carry_i_10_n_0,S_B0__30_carry_i_11_n_0,S_B0__30_carry_i_12__0_n_0,\Data_A_i[20]_0 }),
.\Data_A_i[23]_6 ({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.Data_A_i_IBUF({Data_A_i_IBUF[4:3],Data_A_i_IBUF[1:0]}),
.\Data_B_i[18] (\Data_B_i[18] ),
.\Data_B_i[18]_0 (\Data_B_i[18]_0 ),
.\Data_B_i[18]_1 (\sgf_result_o[43] ),
.\Data_B_i[19] (S_B0__0_carry__0_i_9__2_n_0),
.\Data_B_i[21] (S_B0__0_carry_i_13__1_n_0),
.\Data_B_i[22] (S_B0__0_carry__0_i_10__2_n_0),
.\Data_B_i[22]_0 ({\Data_B_i[22] ,S_B0__30_carry__1_i_12_n_0}),
.Data_B_i_IBUF({Data_B_i_IBUF[4:3],Data_B_i_IBUF[1:0]}),
.O(O),
.Q_middle_temp__2(Q_middle_temp__2),
.S({sgf_result_o0__1_carry_i_4__4_n_0,sgf_result_o0__1_carry_i_5__4_n_0,sgf_result_o0__1_carry_i_6__3_n_0,sgf_result_o0__1_carry_i_7__4_n_0}),
.\sgf_result_o[15] ({\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.\sgf_result_o[15]_0 ({\EVEN1.middle_n_31 ,\EVEN1.middle_n_32 ,\EVEN1.middle_n_33 ,\EVEN1.middle_n_34 }),
.\sgf_result_o[19] ({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.\sgf_result_o[19]_0 ({\EVEN1.middle_n_35 ,\EVEN1.middle_n_36 ,\EVEN1.middle_n_37 ,\EVEN1.middle_n_38 }),
.\sgf_result_o[19]_1 (\sgf_result_o[19] ),
.\sgf_result_o[23] (\sgf_result_o[23] ),
.\sgf_result_o[23]_0 (\sgf_result_o[23]_0 ),
.\sgf_result_o[27] (\sgf_result_o[27] ),
.\sgf_result_o[27]_0 (\sgf_result_o[27]_0 ),
.\sgf_result_o[27]_1 (\sgf_result_o[27]_1 ),
.\sgf_result_o[47] (\sgf_result_o[47] ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_3 ));
CARRY4 S_B0__0_carry
(.CI(1'b0),
.CO({S_B0__0_carry_n_0,S_B0__0_carry_n_1,S_B0__0_carry_n_2,S_B0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 ,1'b1}),
.O({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.S({\EVEN1.middle_n_31 ,\EVEN1.middle_n_32 ,\EVEN1.middle_n_33 ,\EVEN1.middle_n_34 }));
CARRY4 S_B0__0_carry__0
(.CI(S_B0__0_carry_n_0),
.CO({NLW_S_B0__0_carry__0_CO_UNCONNECTED[3],S_B0__0_carry__0_n_1,S_B0__0_carry__0_n_2,S_B0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.O({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.S({\EVEN1.middle_n_35 ,\EVEN1.middle_n_36 ,\EVEN1.middle_n_37 ,\EVEN1.middle_n_38 }));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__0_carry__0_i_10__2
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__0_carry__0_i_10__2_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_7__2
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry__0_i_7__2_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_8__2
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry__0_i_8__2_n_0));
LUT6 #(
.INIT(64'h55FF7FFF7FFFFFFF))
S_B0__0_carry__0_i_9__2
(.I0(Data_A_i_IBUF[2]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_B_i_IBUF[2]),
.I4(Data_A_i_IBUF[1]),
.I5(Data_B_i_IBUF[1]),
.O(S_B0__0_carry__0_i_9__2_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_10__1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[0]),
.O(\sgf_result_o[43] ));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_11__2
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_11__2_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_12__2
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_12__2_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_13__1
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_B_i_IBUF[3]),
.O(S_B0__0_carry_i_13__1_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_8__2
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_8__2_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_9__2
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_9__2_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry__0_i_11__0
(.I0(S_B0__0_carry__0_n_5),
.I1(S_B0__0_carry_i_12__2_n_0),
.O(S_B0__30_carry__0_i_11__0_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__0_i_12
(.I0(S_B0__0_carry__0_n_6),
.I1(S_B0__0_carry_i_9__2_n_0),
.O(S_B0__30_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0__30_carry__0_i_13
(.I0(S_B0__0_carry__0_n_7),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__0_i_13_n_0));
LUT3 #(
.INIT(8'h6A))
S_B0__30_carry__0_i_14
(.I0(S_B0__0_carry_n_4),
.I1(Data_A_i_IBUF[3]),
.I2(Data_B_i_IBUF[3]),
.O(S_B0__30_carry__0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__1_i_12
(.I0(S_B0__0_carry__0_n_4),
.I1(S_B0__0_carry__0_i_8__2_n_0),
.O(S_B0__30_carry__1_i_12_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry_i_10
(.I0(S_B0__0_carry_n_5),
.I1(S_B0__0_carry__0_i_9__2_n_0),
.O(S_B0__30_carry_i_10_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry_i_11
(.I0(S_B0__0_carry_n_6),
.I1(S_B0__0_carry__0_i_7__2_n_0),
.O(S_B0__30_carry_i_11_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry_i_12__0
(.I0(S_B0__0_carry_n_7),
.I1(S_B0__0_carry_i_11__2_n_0),
.O(S_B0__30_carry_i_12__0_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_1__4
(.I0(sgf_result_o0__1_carry_i_11__4_n_0),
.I1(sgf_result_o0__1_carry_i_13__3_n_0),
.O(sgf_result_o0__1_carry__0_i_1__4_n_0));
LUT5 #(
.INIT(32'h14000000))
sgf_result_o0__1_carry__0_i_2__3
(.I0(sgf_result_o0__1_carry_i_13__3_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_3__4_n_0),
.I4(sgf_result_o0__1_carry_i_10__9_n_0),
.O(sgf_result_o0__1_carry__0_i_2__3_n_0));
LUT6 #(
.INIT(64'h56A956A956A9A956))
sgf_result_o0__1_carry__0_i_3__5
(.I0(sgf_result_o0__1_carry__0_i_2__3_n_0),
.I1(sgf_result_o0__1_carry_i_11__4_n_0),
.I2(sgf_result_o0__1_carry_i_14__6_n_0),
.I3(sgf_result_o0__1_carry__0_i_7__1_n_0),
.I4(sgf_result_o0__1_carry_i_9__11_n_0),
.I5(sgf_result_o0__1_carry_i_13__3_n_0),
.O(sgf_result_o0__1_carry__0_i_3__5_n_0));
LUT6 #(
.INIT(64'h000001010003FCE8))
sgf_result_o0__1_carry__0_i_4__4
(.I0(sgf_result_o0__1_carry_i_9__11_n_0),
.I1(sgf_result_o0__1_carry_i_12__4_n_0),
.I2(sgf_result_o0__1_carry_i_8__3_n_0),
.I3(sgf_result_o0__1_carry_i_14__6_n_0),
.I4(sgf_result_o0__1_carry_i_13__3_n_0),
.I5(sgf_result_o0__1_carry_i_11__4_n_0),
.O(sgf_result_o0__1_carry__0_i_4__4_n_0));
LUT6 #(
.INIT(64'h9996999699966669))
sgf_result_o0__1_carry__0_i_5__6
(.I0(sgf_result_o0__1_carry__0_i_2__3_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__3_n_0),
.I2(sgf_result_o0__1_carry_i_12__4_n_0),
.I3(sgf_result_o0__1_carry_i_13__3_n_0),
.I4(sgf_result_o0__1_carry_i_8__3_n_0),
.I5(sgf_result_o0__1_carry_i_11__4_n_0),
.O(sgf_result_o0__1_carry__0_i_5__6_n_0));
LUT6 #(
.INIT(64'h66666556AAAAA66A))
sgf_result_o0__1_carry__0_i_6__4
(.I0(sgf_result_o0__1_carry__0_i_3__5_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__7_n_0),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(sgf_result_o0__1_carry_i_11__4_n_0),
.I5(sgf_result_o0__1_carry_i_10__9_n_0),
.O(sgf_result_o0__1_carry__0_i_6__4_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_7__1
(.I0(sgf_result_o0__1_carry_i_12__4_n_0),
.I1(sgf_result_o0__1_carry_i_8__3_n_0),
.O(sgf_result_o0__1_carry__0_i_7__1_n_0));
LUT6 #(
.INIT(64'hFFFEFFFEFFFEEEE0))
sgf_result_o0__1_carry__0_i_8__3
(.I0(sgf_result_o0__1_carry_i_11__4_n_0),
.I1(sgf_result_o0__1_carry_i_14__6_n_0),
.I2(sgf_result_o0__1_carry_i_8__3_n_0),
.I3(sgf_result_o0__1_carry_i_12__4_n_0),
.I4(sgf_result_o0__1_carry_i_9__11_n_0),
.I5(sgf_result_o0__1_carry_i_13__3_n_0),
.O(sgf_result_o0__1_carry__0_i_8__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_9__7
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_8__3_n_0),
.O(sgf_result_o0__1_carry__0_i_9__7_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry_i_10__9
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_12__4_n_0),
.O(sgf_result_o0__1_carry_i_10__9_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_11__4
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[2]),
.I5(Data_B_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_11__4_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_12__4
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[2]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.I4(Data_B_i_IBUF[4]),
.I5(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_12__4_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_13__3
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[2]),
.I5(Data_A_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_13__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_14__6
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_14__6_n_0));
LUT6 #(
.INIT(64'hE1E1E1E1E11E1EE1))
sgf_result_o0__1_carry_i_1__4
(.I0(sgf_result_o0__1_carry_i_8__3_n_0),
.I1(sgf_result_o0__1_carry_i_9__11_n_0),
.I2(sgf_result_o0__1_carry_i_10__9_n_0),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_11__4_n_0),
.O(sgf_result_o0__1_carry_i_1__4_n_0));
LUT6 #(
.INIT(64'h0906060609F9F906))
sgf_result_o0__1_carry_i_2__4
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[1]),
.I2(sgf_result_o0__1_carry_i_9__11_n_0),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[3]),
.I5(sgf_result_o0__1_carry_i_12__4_n_0),
.O(sgf_result_o0__1_carry_i_2__4_n_0));
LUT6 #(
.INIT(64'h6006066006600660))
sgf_result_o0__1_carry_i_3__4
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[1]),
.I3(Data_B_i_IBUF[4]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_3__4_n_0));
LUT6 #(
.INIT(64'h6A6A6A6A6A95956A))
sgf_result_o0__1_carry_i_4__4
(.I0(sgf_result_o0__1_carry_i_1__4_n_0),
.I1(sgf_result_o0__1_carry_i_10__9_n_0),
.I2(sgf_result_o0__1_carry_i_3__4_n_0),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_13__3_n_0),
.O(sgf_result_o0__1_carry_i_4__4_n_0));
LUT4 #(
.INIT(16'hA99A))
sgf_result_o0__1_carry_i_5__4
(.I0(sgf_result_o0__1_carry_i_2__4_n_0),
.I1(sgf_result_o0__1_carry_i_8__3_n_0),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_5__4_n_0));
LUT6 #(
.INIT(64'h141414EB14EB1414))
sgf_result_o0__1_carry_i_6__3
(.I0(sgf_result_o0__1_carry_i_14__6_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_9__11_n_0),
.I4(Data_A_i_IBUF[0]),
.I5(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_6__3_n_0));
LUT4 #(
.INIT(16'h0660))
sgf_result_o0__1_carry_i_7__4
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.O(sgf_result_o0__1_carry_i_7__4_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_8__3
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_8__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_9__11
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[4]),
.I3(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_9__11_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized11
(\sgf_result_o[19] ,
\sgf_result_o[47] ,
\sgf_result_o[15] ,
\sgf_result_o[19]_0 ,
\sgf_result_o[15]_0 ,
\sgf_result_o[19]_1 ,
\sgf_result_o[47]_0 ,
\sgf_result_o[19]_2 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[39] ,
\sgf_result_o[43] ,
DI,
S,
\Data_B_i[18] ,
\Data_A_i[18] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12] ,
\Data_B_i[22] ,
\Data_B_i[18]_0 ,
p_0_in,
Q_middle_temp__1,
\Data_B_i[18]_1 ,
\Data_A_i[18]_0 ,
O,
\Data_B_i[18]_2 ,
\Data_A_i[18]_1 ,
\Data_A_i[18]_2 ,
\Data_A_i[18]_3 ,
\Data_A_i[23] ,
\Data_A_i[17] ,
Q_middle_temp__2,
\Data_A_i[17]_0 ,
\Data_A_i[23]_0 ,
\Data_A_i[17]_1 ,
\Data_A_i[17]_2 ,
\Data_A_i[14] ,
\Data_A_i[14]_0 ,
\Data_A_i[14]_1 ,
\Data_A_i[23]_1 ,
\Data_A_i[20] ,
\Data_B_i[18]_3 ,
\Data_A_i[18]_4 );
output [0:0]\sgf_result_o[19] ;
output [2:0]\sgf_result_o[47] ;
output [2:0]\sgf_result_o[15] ;
output [3:0]\sgf_result_o[19]_0 ;
output [3:0]\sgf_result_o[15]_0 ;
output [3:0]\sgf_result_o[19]_1 ;
output [3:0]\sgf_result_o[47]_0 ;
output [0:0]\sgf_result_o[19]_2 ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [3:0]\sgf_result_o[39] ;
output [2:0]\sgf_result_o[43] ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[18] ;
input [2:0]\Data_A_i[18] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[12] ;
input \Data_B_i[22] ;
input [1:0]\Data_B_i[18]_0 ;
input [1:0]p_0_in;
input [5:0]Q_middle_temp__1;
input \Data_B_i[18]_1 ;
input \Data_A_i[18]_0 ;
input [3:0]O;
input \Data_B_i[18]_2 ;
input \Data_A_i[18]_1 ;
input \Data_A_i[18]_2 ;
input \Data_A_i[18]_3 ;
input [1:0]\Data_A_i[23] ;
input [1:0]\Data_A_i[17] ;
input [0:0]Q_middle_temp__2;
input [3:0]\Data_A_i[17]_0 ;
input [3:0]\Data_A_i[23]_0 ;
input [3:0]\Data_A_i[17]_1 ;
input [3:0]\Data_A_i[17]_2 ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[14]_0 ;
input [1:0]\Data_A_i[14]_1 ;
input [3:0]\Data_A_i[23]_1 ;
input [2:0]\Data_A_i[20] ;
input [0:0]\Data_B_i[18]_3 ;
input [0:0]\Data_A_i[18]_4 ;
wire [2:0]DI;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [1:0]\Data_A_i[14]_1 ;
wire [1:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[17]_0 ;
wire [3:0]\Data_A_i[17]_1 ;
wire [3:0]\Data_A_i[17]_2 ;
wire [2:0]\Data_A_i[18] ;
wire \Data_A_i[18]_0 ;
wire \Data_A_i[18]_1 ;
wire \Data_A_i[18]_2 ;
wire \Data_A_i[18]_3 ;
wire [0:0]\Data_A_i[18]_4 ;
wire [2:0]\Data_A_i[20] ;
wire [1:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire [3:0]\Data_A_i[23]_1 ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire [2:0]\Data_B_i[18] ;
wire [1:0]\Data_B_i[18]_0 ;
wire \Data_B_i[18]_1 ;
wire \Data_B_i[18]_2 ;
wire [0:0]\Data_B_i[18]_3 ;
wire \Data_B_i[22] ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire [5:0]Q_middle_temp__1;
wire [0:0]Q_middle_temp__2;
wire [3:0]S;
wire [1:0]p_0_in;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [2:0]\sgf_result_o[15] ;
wire [3:0]\sgf_result_o[15]_0 ;
wire [0:0]\sgf_result_o[19] ;
wire [3:0]\sgf_result_o[19]_0 ;
wire [3:0]\sgf_result_o[19]_1 ;
wire [0:0]\sgf_result_o[19]_2 ;
wire [3:0]\sgf_result_o[39] ;
wire [2:0]\sgf_result_o[43] ;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\^sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire \sgf_result_o_OBUF[34]_inst_i_15_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_15_n_1 ;
wire \sgf_result_o_OBUF[34]_inst_i_15_n_2 ;
wire \sgf_result_o_OBUF[34]_inst_i_15_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_19_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_19_n_1 ;
wire \sgf_result_o_OBUF[38]_inst_i_19_n_2 ;
wire \sgf_result_o_OBUF[38]_inst_i_19_n_3 ;
wire \sgf_result_o_OBUF[42]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[42]_inst_i_6_n_1 ;
wire \sgf_result_o_OBUF[42]_inst_i_6_n_2 ;
wire \sgf_result_o_OBUF[42]_inst_i_6_n_3 ;
wire \sgf_result_o_OBUF[46]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[46]_inst_i_6_n_1 ;
wire \sgf_result_o_OBUF[46]_inst_i_6_n_2 ;
wire \sgf_result_o_OBUF[46]_inst_i_6_n_3 ;
wire \sgf_result_o_OBUF[47]_inst_i_3_n_2 ;
wire \sgf_result_o_OBUF[47]_inst_i_3_n_3 ;
wire [2:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
wire [3:2]\NLW_sgf_result_o_OBUF[47]_inst_i_3_CO_UNCONNECTED ;
wire [3:3]\NLW_sgf_result_o_OBUF[47]_inst_i_3_O_UNCONNECTED ;
assign \sgf_result_o[47]_0 [3:1] = \^sgf_result_o[47]_0 [3:1];
assign \sgf_result_o[47]_0 [0] = sgf_result_o0__1_carry_n_4;
(* HLUTNM = "lutpair31" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry_i_1__0
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[23] [0]),
.I2(\Data_A_i[17] [0]),
.O(\sgf_result_o[47] [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__30_carry_i_2__0
(.I0(Data_B_i_IBUF[2]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[12] ),
.O(\sgf_result_o[47] [1]));
(* HLUTNM = "lutpair85" *)
LUT5 #(
.INIT(32'h7FFF0777))
S_B0__30_carry_i_3__0
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_7),
.O(\sgf_result_o[47] [0]));
(* HLUTNM = "lutpair32" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_4__0
(.I0(Q_middle_temp__2),
.I1(\Data_A_i[23] [1]),
.I2(\Data_A_i[17] [1]),
.I3(\sgf_result_o[47] [2]),
.O(\sgf_result_o[47]_1 [3]));
(* HLUTNM = "lutpair31" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_5__0
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[23] [0]),
.I2(\Data_A_i[17] [0]),
.I3(\sgf_result_o[47] [1]),
.O(\sgf_result_o[47]_1 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_6__0
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_B_i[12] ),
.I2(\Data_B_i[18]_2 ),
.I3(sgf_result_o0__1_carry_n_6),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair85" *)
LUT5 #(
.INIT(32'h78888777))
S_B0__30_carry_i_7__0
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_7),
.O(\sgf_result_o[47]_1 [0]));
LUT2 #(
.INIT(4'h6))
S_B0_carry__0_i_4__0
(.I0(O[3]),
.I1(\sgf_result_o[19] ),
.O(\sgf_result_o[19]_2 ));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_1__0
(.I0(O[2]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\^sgf_result_o[47]_0 [3]));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_2__0
(.I0(O[1]),
.I1(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_0 [2]));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_3__0
(.I0(O[0]),
.I1(sgf_result_o0__1_carry__0_n_7),
.O(\^sgf_result_o[47]_0 [1]));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({\sgf_result_o[19] ,NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_B_i[18] }),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[18] }));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__21_carry__0_i_1__0
(.I0(Q_middle_temp__1[4]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\sgf_result_o[19]_0 [3]));
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__21_carry__0_i_2__0
(.I0(Q_middle_temp__1[3]),
.I1(sgf_result_o0__1_carry__0_n_6),
.I2(\Data_B_i[18]_1 ),
.O(\sgf_result_o[19]_0 [2]));
(* HLUTNM = "lutpair30" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__21_carry__0_i_3__0
(.I0(Q_middle_temp__1[2]),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[18]_3 ),
.O(\sgf_result_o[19]_0 [1]));
(* HLUTNM = "lutpair29" *)
LUT3 #(
.INIT(8'hD4))
sgf_result_o1__21_carry__0_i_4__0
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[18]_2 ),
.I2(Q_middle_temp__1[1]),
.O(\sgf_result_o[19]_0 [0]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__21_carry__0_i_5__0
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(Q_middle_temp__1[4]),
.I2(\sgf_result_o[19] ),
.I3(Q_middle_temp__1[5]),
.O(\sgf_result_o[19]_1 [3]));
LUT5 #(
.INIT(32'h718E8E71))
sgf_result_o1__21_carry__0_i_6__0
(.I0(\Data_B_i[18]_1 ),
.I1(sgf_result_o0__1_carry__0_n_6),
.I2(Q_middle_temp__1[3]),
.I3(sgf_result_o0__1_carry__0_n_5),
.I4(Q_middle_temp__1[4]),
.O(\sgf_result_o[19]_1 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry__0_i_7__0
(.I0(\sgf_result_o[19]_0 [1]),
.I1(sgf_result_o0__1_carry__0_n_6),
.I2(\Data_B_i[18]_1 ),
.I3(Q_middle_temp__1[3]),
.O(\sgf_result_o[19]_1 [1]));
(* HLUTNM = "lutpair30" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry__0_i_8__0
(.I0(Q_middle_temp__1[2]),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[18]_3 ),
.I3(\sgf_result_o[19]_0 [0]),
.O(\sgf_result_o[19]_1 [0]));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__21_carry_i_1__0
(.I0(Q_middle_temp__1[0]),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[18]_1 ),
.O(\sgf_result_o[15] [2]));
LUT6 #(
.INIT(64'hB2222BBB2BBB2BBB))
sgf_result_o1__21_carry_i_2__0
(.I0(\Data_B_i[22] ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[18]_0 [0]),
.I3(p_0_in[1]),
.I4(p_0_in[0]),
.I5(\Data_B_i[18]_0 [1]),
.O(\sgf_result_o[15] [1]));
(* HLUTNM = "lutpair84" *)
LUT5 #(
.INIT(32'h1747270F))
sgf_result_o1__21_carry_i_3__0
(.I0(p_0_in[0]),
.I1(\Data_B_i[18]_0 [0]),
.I2(sgf_result_o0__1_carry_n_7),
.I3(\Data_B_i[18]_3 ),
.I4(\Data_A_i[18]_4 ),
.O(\sgf_result_o[15] [0]));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__21_carry_i_4__0
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[18]_2 ),
.I2(Q_middle_temp__1[1]),
.I3(\sgf_result_o[15] [2]),
.O(\sgf_result_o[15]_0 [3]));
(* HLUTNM = "lutpair28" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_5__0
(.I0(Q_middle_temp__1[0]),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[18]_1 ),
.I3(\sgf_result_o[15] [1]),
.O(\sgf_result_o[15]_0 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_6__0
(.I0(\sgf_result_o[15] [0]),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_A_i[18]_0 ),
.I3(\Data_B_i[22] ),
.O(\sgf_result_o[15]_0 [1]));
(* HLUTNM = "lutpair84" *)
LUT5 #(
.INIT(32'h96C3A50F))
sgf_result_o1__21_carry_i_7__0
(.I0(p_0_in[0]),
.I1(\Data_B_i[18]_0 [0]),
.I2(sgf_result_o0__1_carry_n_7),
.I3(\Data_B_i[18]_3 ),
.I4(\Data_A_i[18]_4 ),
.O(\sgf_result_o[15]_0 [0]));
CARRY4 \sgf_result_o_OBUF[34]_inst_i_15
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[34]_inst_i_15_n_0 ,\sgf_result_o_OBUF[34]_inst_i_15_n_1 ,\sgf_result_o_OBUF[34]_inst_i_15_n_2 ,\sgf_result_o_OBUF[34]_inst_i_15_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[17]_0 [2:0],1'b0}),
.O(\sgf_result_o[47]_2 ),
.S(\Data_A_i[23]_0 ));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_19
(.CI(\sgf_result_o_OBUF[34]_inst_i_15_n_0 ),
.CO({\sgf_result_o_OBUF[38]_inst_i_19_n_0 ,\sgf_result_o_OBUF[38]_inst_i_19_n_1 ,\sgf_result_o_OBUF[38]_inst_i_19_n_2 ,\sgf_result_o_OBUF[38]_inst_i_19_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[17]_1 [2:0],\Data_A_i[17]_0 [3]}),
.O(\sgf_result_o[47]_3 ),
.S(\Data_A_i[17]_2 ));
CARRY4 \sgf_result_o_OBUF[42]_inst_i_6
(.CI(\sgf_result_o_OBUF[38]_inst_i_19_n_0 ),
.CO({\sgf_result_o_OBUF[42]_inst_i_6_n_0 ,\sgf_result_o_OBUF[42]_inst_i_6_n_1 ,\sgf_result_o_OBUF[42]_inst_i_6_n_2 ,\sgf_result_o_OBUF[42]_inst_i_6_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[14] [2:0],\Data_A_i[17]_1 [3]}),
.O(\sgf_result_o[47]_4 ),
.S(\Data_A_i[14]_0 ));
CARRY4 \sgf_result_o_OBUF[46]_inst_i_6
(.CI(\sgf_result_o_OBUF[42]_inst_i_6_n_0 ),
.CO({\sgf_result_o_OBUF[46]_inst_i_6_n_0 ,\sgf_result_o_OBUF[46]_inst_i_6_n_1 ,\sgf_result_o_OBUF[46]_inst_i_6_n_2 ,\sgf_result_o_OBUF[46]_inst_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[14]_1 ,\Data_A_i[14] [3]}),
.O(\sgf_result_o[39] ),
.S(\Data_A_i[23]_1 ));
CARRY4 \sgf_result_o_OBUF[47]_inst_i_3
(.CI(\sgf_result_o_OBUF[46]_inst_i_6_n_0 ),
.CO({\NLW_sgf_result_o_OBUF[47]_inst_i_3_CO_UNCONNECTED [3:2],\sgf_result_o_OBUF[47]_inst_i_3_n_2 ,\sgf_result_o_OBUF[47]_inst_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_sgf_result_o_OBUF[47]_inst_i_3_O_UNCONNECTED [3],\sgf_result_o[43] }),
.S({1'b0,\Data_A_i[20] }));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized12
(O,
\sgf_result_o[19] ,
\sgf_result_o[15] ,
\sgf_result_o[15]_0 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[15]_3 ,
\sgf_result_o[15]_4 ,
\sgf_result_o[15]_5 ,
\sgf_result_o[15]_6 ,
\sgf_result_o[15]_7 ,
S,
\sgf_result_o[19]_0 ,
\sgf_result_o[23] ,
\Data_A_i[18] ,
p_0_in,
\Data_B_i[18] ,
\Data_B_i[18]_0 ,
\Data_A_i[22] ,
\Data_B_i[22] ,
\Data_A_i[22]_0 ,
\Data_B_i[18]_1 ,
\Data_A_i[22]_1 ,
\Data_A_i[22]_2 ,
CO,
\Data_A_i[22]_3 ,
\Data_A_i[22]_4 ,
\Data_B_i[18]_2 ,
\Data_A_i[18]_0 ,
\Data_B_i[22]_0 ,
\Data_B_i[18]_3 );
output [3:0]O;
output [1:0]\sgf_result_o[19] ;
output \sgf_result_o[15] ;
output \sgf_result_o[15]_0 ;
output \sgf_result_o[15]_1 ;
output \sgf_result_o[15]_2 ;
output \sgf_result_o[15]_3 ;
output \sgf_result_o[15]_4 ;
output \sgf_result_o[15]_5 ;
output \sgf_result_o[15]_6 ;
output \sgf_result_o[15]_7 ;
output [2:0]S;
output [3:0]\sgf_result_o[19]_0 ;
output [0:0]\sgf_result_o[23] ;
input [3:0]\Data_A_i[18] ;
input [2:0]p_0_in;
input [3:0]\Data_B_i[18] ;
input [1:0]\Data_B_i[18]_0 ;
input \Data_A_i[22] ;
input \Data_B_i[22] ;
input \Data_A_i[22]_0 ;
input \Data_B_i[18]_1 ;
input \Data_A_i[22]_1 ;
input \Data_A_i[22]_2 ;
input [0:0]CO;
input \Data_A_i[22]_3 ;
input \Data_A_i[22]_4 ;
input [0:0]\Data_B_i[18]_2 ;
input [1:0]\Data_A_i[18]_0 ;
input \Data_B_i[22]_0 ;
input \Data_B_i[18]_3 ;
wire [0:0]CO;
wire [3:0]\Data_A_i[18] ;
wire [1:0]\Data_A_i[18]_0 ;
wire \Data_A_i[22] ;
wire \Data_A_i[22]_0 ;
wire \Data_A_i[22]_1 ;
wire \Data_A_i[22]_2 ;
wire \Data_A_i[22]_3 ;
wire \Data_A_i[22]_4 ;
wire [3:0]\Data_B_i[18] ;
wire [1:0]\Data_B_i[18]_0 ;
wire \Data_B_i[18]_1 ;
wire [0:0]\Data_B_i[18]_2 ;
wire \Data_B_i[18]_3 ;
wire \Data_B_i[22] ;
wire \Data_B_i[22]_0 ;
wire [3:0]O;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_11 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_20 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_8 ;
wire \ODD1.middle_n_9 ;
wire [2:0]S;
wire [2:0]p_0_in;
wire sgf_result_o1__0_carry__0_n_2;
wire sgf_result_o1__0_carry__0_n_3;
wire sgf_result_o1__0_carry__0_n_5;
wire sgf_result_o1__0_carry_n_0;
wire sgf_result_o1__0_carry_n_1;
wire sgf_result_o1__0_carry_n_2;
wire sgf_result_o1__0_carry_n_3;
wire \sgf_result_o[15] ;
wire \sgf_result_o[15]_0 ;
wire \sgf_result_o[15]_1 ;
wire \sgf_result_o[15]_2 ;
wire \sgf_result_o[15]_3 ;
wire \sgf_result_o[15]_4 ;
wire \sgf_result_o[15]_5 ;
wire \sgf_result_o[15]_6 ;
wire \sgf_result_o[15]_7 ;
wire [1:0]\sgf_result_o[19] ;
wire [3:0]\^sgf_result_o[19]_0 ;
wire [0:0]\sgf_result_o[23] ;
wire [3:2]NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED;
assign \sgf_result_o[19]_0 [3] = sgf_result_o1__0_carry__0_n_5;
assign \sgf_result_o[19]_0 [2:0] = \^sgf_result_o[19]_0 [2:0];
Recursive_KOA__parameterized15 \ODD1.middle
(.CO(CO),
.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 }),
.\Data_A_i[18] (\Data_A_i[18] ),
.\Data_A_i[22] (\Data_A_i[22] ),
.\Data_A_i[22]_0 (\Data_A_i[22]_0 ),
.\Data_A_i[22]_1 (\Data_A_i[22]_1 ),
.\Data_A_i[22]_2 (\Data_A_i[22]_2 ),
.\Data_A_i[22]_3 (\Data_A_i[22]_4 ),
.\Data_A_i[22]_4 (\Data_A_i[22]_3 ),
.\Data_B_i[18] (\Data_B_i[18] ),
.\Data_B_i[18]_0 (\Data_B_i[18]_0 ),
.\Data_B_i[18]_1 (\Data_B_i[18]_1 ),
.\Data_B_i[18]_2 (\Data_B_i[18]_3 ),
.\Data_B_i[22] (\Data_B_i[22] ),
.\Data_B_i[22]_0 (\Data_B_i[22]_0 ),
.S({\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }),
.p_0_in(p_0_in),
.\sgf_result_o[15] (\sgf_result_o[15] ),
.\sgf_result_o[15]_0 (\sgf_result_o[15]_0 ),
.\sgf_result_o[15]_1 (\sgf_result_o[15]_1 ),
.\sgf_result_o[15]_2 (\sgf_result_o[15]_2 ),
.\sgf_result_o[15]_3 (\sgf_result_o[15]_3 ),
.\sgf_result_o[15]_4 (\sgf_result_o[15]_4 ),
.\sgf_result_o[15]_5 (\sgf_result_o[15]_5 ),
.\sgf_result_o[15]_6 (\sgf_result_o[15]_6 ),
.\sgf_result_o[15]_7 (\sgf_result_o[15]_7 ),
.\sgf_result_o[15]_8 ({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }),
.\sgf_result_o[19] ({\ODD1.middle_n_13 ,\ODD1.middle_n_14 }));
CARRY4 sgf_result_o1__0_carry
(.CI(1'b0),
.CO({sgf_result_o1__0_carry_n_0,sgf_result_o1__0_carry_n_1,sgf_result_o1__0_carry_n_2,sgf_result_o1__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 ,1'b1}),
.O(O),
.S({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }));
CARRY4 sgf_result_o1__0_carry__0
(.CI(sgf_result_o1__0_carry_n_0),
.CO({NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED[3:2],sgf_result_o1__0_carry__0_n_2,sgf_result_o1__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\ODD1.middle_n_13 ,\ODD1.middle_n_14 }),
.O({NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED[3],sgf_result_o1__0_carry__0_n_5,\sgf_result_o[19] }),
.S({1'b0,\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }));
LUT3 #(
.INIT(8'h2D))
sgf_result_o1__21_carry__1_i_2__0
(.I0(\Data_B_i[18]_2 ),
.I1(\Data_A_i[18]_0 [0]),
.I2(\Data_A_i[18]_0 [1]),
.O(\sgf_result_o[23] ));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_2__0
(.I0(\sgf_result_o[19] [1]),
.I1(\Data_A_i[22]_2 ),
.O(\^sgf_result_o[19]_0 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_3__0
(.I0(\sgf_result_o[19] [0]),
.I1(\Data_A_i[22]_4 ),
.O(\^sgf_result_o[19]_0 [1]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_4__0
(.I0(O[3]),
.I1(\Data_A_i[22]_3 ),
.O(\^sgf_result_o[19]_0 [0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_1__0
(.I0(O[2]),
.I1(\Data_A_i[22]_0 ),
.O(S[2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_2__0
(.I0(O[1]),
.I1(\Data_B_i[18]_1 ),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
sgf_result_o1_carry_i_3__1
(.I0(O[0]),
.I1(\Data_B_i[18]_3 ),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized15
(\sgf_result_o[15] ,
\sgf_result_o[15]_0 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[15]_3 ,
\sgf_result_o[15]_4 ,
\sgf_result_o[15]_5 ,
DI,
S,
\sgf_result_o[19] ,
\sgf_result_o[15]_6 ,
\sgf_result_o[15]_7 ,
\sgf_result_o[15]_8 ,
\Data_A_i[18] ,
p_0_in,
\Data_B_i[18] ,
\Data_B_i[18]_0 ,
\Data_A_i[22] ,
\Data_B_i[22] ,
\Data_A_i[22]_0 ,
\Data_B_i[18]_1 ,
\Data_A_i[22]_1 ,
\Data_A_i[22]_2 ,
CO,
\Data_B_i[22]_0 ,
\Data_A_i[22]_3 ,
\Data_B_i[18]_2 ,
\Data_A_i[22]_4 );
output \sgf_result_o[15] ;
output \sgf_result_o[15]_0 ;
output \sgf_result_o[15]_1 ;
output \sgf_result_o[15]_2 ;
output \sgf_result_o[15]_3 ;
output \sgf_result_o[15]_4 ;
output \sgf_result_o[15]_5 ;
output [2:0]DI;
output [2:0]S;
output [1:0]\sgf_result_o[19] ;
output \sgf_result_o[15]_6 ;
output \sgf_result_o[15]_7 ;
output [3:0]\sgf_result_o[15]_8 ;
input [3:0]\Data_A_i[18] ;
input [2:0]p_0_in;
input [3:0]\Data_B_i[18] ;
input [1:0]\Data_B_i[18]_0 ;
input \Data_A_i[22] ;
input \Data_B_i[22] ;
input \Data_A_i[22]_0 ;
input \Data_B_i[18]_1 ;
input \Data_A_i[22]_1 ;
input \Data_A_i[22]_2 ;
input [0:0]CO;
input \Data_B_i[22]_0 ;
input \Data_A_i[22]_3 ;
input \Data_B_i[18]_2 ;
input \Data_A_i[22]_4 ;
wire [0:0]CO;
wire [2:0]DI;
wire [3:0]\Data_A_i[18] ;
wire \Data_A_i[22] ;
wire \Data_A_i[22]_0 ;
wire \Data_A_i[22]_1 ;
wire \Data_A_i[22]_2 ;
wire \Data_A_i[22]_3 ;
wire \Data_A_i[22]_4 ;
wire [3:0]\Data_B_i[18] ;
wire [1:0]\Data_B_i[18]_0 ;
wire \Data_B_i[18]_1 ;
wire \Data_B_i[18]_2 ;
wire \Data_B_i[22] ;
wire \Data_B_i[22]_0 ;
wire [2:0]S;
wire [2:0]p_0_in;
wire sgf_result_o0__1_carry__0_i_1__6_n_0;
wire sgf_result_o0__1_carry__0_i_2__5_n_0;
wire sgf_result_o0__1_carry__0_i_3__0_n_0;
wire sgf_result_o0__1_carry__0_i_4__6_n_0;
wire sgf_result_o0__1_carry__0_i_7__10_n_0;
wire sgf_result_o0__1_carry__0_i_8__5_n_0;
wire sgf_result_o0__1_carry__0_i_9__8_n_0;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_i_10__10_n_0;
wire sgf_result_o0__1_carry_i_11__6_n_0;
wire sgf_result_o0__1_carry_i_13__4_n_0;
wire sgf_result_o0__1_carry_i_14__7_n_0;
wire sgf_result_o0__1_carry_i_15__1_n_0;
wire sgf_result_o0__1_carry_i_16__2_n_0;
wire sgf_result_o0__1_carry_i_17__1_n_0;
wire sgf_result_o0__1_carry_i_1__6_n_0;
wire sgf_result_o0__1_carry_i_21__1_n_0;
wire sgf_result_o0__1_carry_i_22_n_0;
wire sgf_result_o0__1_carry_i_2__6_n_0;
wire sgf_result_o0__1_carry_i_3__6_n_0;
wire sgf_result_o0__1_carry_i_4__6_n_0;
wire sgf_result_o0__1_carry_i_5__6_n_0;
wire sgf_result_o0__1_carry_i_6__11_n_0;
wire sgf_result_o0__1_carry_i_7__6_n_0;
wire sgf_result_o0__1_carry_i_8__4_n_0;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire \sgf_result_o[15] ;
wire \sgf_result_o[15]_0 ;
wire \sgf_result_o[15]_1 ;
wire \sgf_result_o[15]_2 ;
wire \sgf_result_o[15]_3 ;
wire \sgf_result_o[15]_4 ;
wire \sgf_result_o[15]_5 ;
wire \sgf_result_o[15]_6 ;
wire \sgf_result_o[15]_7 ;
wire [3:0]\sgf_result_o[15]_8 ;
wire [1:0]\sgf_result_o[19] ;
wire [3:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o0__1_carry_i_1__6_n_0,sgf_result_o0__1_carry_i_2__6_n_0,sgf_result_o0__1_carry_i_3__6_n_0,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S({sgf_result_o0__1_carry_i_4__6_n_0,sgf_result_o0__1_carry_i_5__6_n_0,sgf_result_o0__1_carry_i_6__11_n_0,sgf_result_o0__1_carry_i_7__6_n_0}));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3:2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sgf_result_o0__1_carry__0_i_1__6_n_0}),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b0,sgf_result_o0__1_carry__0_i_2__5_n_0,sgf_result_o0__1_carry__0_i_3__0_n_0,sgf_result_o0__1_carry__0_i_4__6_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry__0_i_10
(.I0(\Data_B_i[18] [0]),
.I1(\Data_B_i[18]_0 [0]),
.O(\sgf_result_o[15]_6 ));
LUT6 #(
.INIT(64'h00651075107565C3))
sgf_result_o0__1_carry__0_i_1__6
(.I0(\sgf_result_o[15] ),
.I1(sgf_result_o0__1_carry_i_13__4_n_0),
.I2(\sgf_result_o[15]_0 ),
.I3(\sgf_result_o[15]_1 ),
.I4(\sgf_result_o[15]_2 ),
.I5(sgf_result_o0__1_carry__0_i_7__10_n_0),
.O(sgf_result_o0__1_carry__0_i_1__6_n_0));
LUT2 #(
.INIT(4'h2))
sgf_result_o0__1_carry__0_i_2__5
(.I0(sgf_result_o0__1_carry__0_i_8__5_n_0),
.I1(sgf_result_o0__1_carry_i_17__1_n_0),
.O(sgf_result_o0__1_carry__0_i_2__5_n_0));
LUT4 #(
.INIT(16'h0335))
sgf_result_o0__1_carry__0_i_3__0
(.I0(sgf_result_o0__1_carry_i_11__6_n_0),
.I1(sgf_result_o0__1_carry_i_17__1_n_0),
.I2(sgf_result_o0__1_carry__0_i_9__8_n_0),
.I3(\sgf_result_o[15] ),
.O(sgf_result_o0__1_carry__0_i_3__0_n_0));
LUT6 #(
.INIT(64'h040404490B4646B9))
sgf_result_o0__1_carry__0_i_4__6
(.I0(sgf_result_o0__1_carry_i_13__4_n_0),
.I1(\sgf_result_o[15]_0 ),
.I2(\sgf_result_o[15]_1 ),
.I3(\sgf_result_o[15]_2 ),
.I4(sgf_result_o0__1_carry__0_i_7__10_n_0),
.I5(\sgf_result_o[15] ),
.O(sgf_result_o0__1_carry__0_i_4__6_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry__0_i_5__0
(.I0(\Data_A_i[18] [0]),
.I1(p_0_in[0]),
.I2(\Data_A_i[18] [1]),
.I3(p_0_in[1]),
.I4(p_0_in[2]),
.I5(\Data_A_i[18] [2]),
.O(\sgf_result_o[15]_1 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry__0_i_6__11
(.I0(p_0_in[0]),
.I1(\Data_A_i[18] [0]),
.I2(p_0_in[1]),
.I3(\Data_A_i[18] [1]),
.O(\sgf_result_o[15]_2 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry__0_i_7__10
(.I0(\Data_A_i[18] [0]),
.I1(p_0_in[0]),
.I2(\Data_A_i[18] [3]),
.I3(\Data_A_i[18] [2]),
.I4(\sgf_result_o[15]_5 ),
.I5(p_0_in[2]),
.O(sgf_result_o0__1_carry__0_i_7__10_n_0));
LUT6 #(
.INIT(64'hE000008000808000))
sgf_result_o0__1_carry__0_i_8__5
(.I0(\Data_B_i[18] [3]),
.I1(\sgf_result_o[15]_6 ),
.I2(\sgf_result_o[15]_0 ),
.I3(\Data_B_i[18] [2]),
.I4(CO),
.I5(\sgf_result_o[15]_7 ),
.O(sgf_result_o0__1_carry__0_i_8__5_n_0));
LUT6 #(
.INIT(64'h7FF7F11FF11FF77F))
sgf_result_o0__1_carry__0_i_9__8
(.I0(sgf_result_o0__1_carry_i_22_n_0),
.I1(\Data_B_i[18] [3]),
.I2(\Data_B_i[18] [1]),
.I3(\Data_B_i[18]_0 [1]),
.I4(\Data_B_i[18] [0]),
.I5(\Data_B_i[18]_0 [0]),
.O(sgf_result_o0__1_carry__0_i_9__8_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_10__10
(.I0(p_0_in[2]),
.I1(\sgf_result_o[15]_5 ),
.I2(\Data_A_i[18] [2]),
.I3(\Data_A_i[18] [3]),
.I4(p_0_in[0]),
.I5(\Data_A_i[18] [0]),
.O(sgf_result_o0__1_carry_i_10__10_n_0));
LUT6 #(
.INIT(64'h0EF1F108F10808F7))
sgf_result_o0__1_carry_i_11__6
(.I0(\sgf_result_o[15]_4 ),
.I1(\Data_A_i[18] [3]),
.I2(\sgf_result_o[15]_2 ),
.I3(\Data_A_i[18] [2]),
.I4(p_0_in[2]),
.I5(\sgf_result_o[15]_5 ),
.O(sgf_result_o0__1_carry_i_11__6_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h8778))
sgf_result_o0__1_carry_i_12__5
(.I0(\Data_B_i[18]_0 [0]),
.I1(\Data_B_i[18] [0]),
.I2(\Data_B_i[18]_0 [1]),
.I3(\Data_B_i[18] [1]),
.O(\sgf_result_o[15]_0 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry_i_13__4
(.I0(\Data_B_i[18] [0]),
.I1(\Data_B_i[18]_0 [0]),
.I2(\Data_B_i[18] [3]),
.I3(\Data_B_i[18] [2]),
.I4(\sgf_result_o[15]_7 ),
.I5(CO),
.O(sgf_result_o0__1_carry_i_13__4_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_14__7
(.I0(CO),
.I1(\sgf_result_o[15]_7 ),
.I2(\Data_B_i[18] [2]),
.I3(\Data_B_i[18] [3]),
.I4(\Data_B_i[18]_0 [0]),
.I5(\Data_B_i[18] [0]),
.O(sgf_result_o0__1_carry_i_14__7_n_0));
LUT2 #(
.INIT(4'h2))
sgf_result_o0__1_carry_i_15__1
(.I0(sgf_result_o0__1_carry_i_8__4_n_0),
.I1(sgf_result_o0__1_carry_i_21__1_n_0),
.O(sgf_result_o0__1_carry_i_15__1_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
sgf_result_o0__1_carry_i_16__2
(.I0(\Data_B_i[18] [1]),
.I1(\Data_B_i[18]_0 [1]),
.I2(sgf_result_o0__1_carry_i_22_n_0),
.I3(\Data_B_i[18] [3]),
.I4(\Data_B_i[18]_0 [0]),
.I5(\Data_B_i[18] [0]),
.O(sgf_result_o0__1_carry_i_16__2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF1FF7F77F))
sgf_result_o0__1_carry_i_17__1
(.I0(\sgf_result_o[15]_4 ),
.I1(\Data_A_i[18] [3]),
.I2(\Data_A_i[18] [2]),
.I3(\sgf_result_o[15]_5 ),
.I4(p_0_in[2]),
.I5(\sgf_result_o[15]_2 ),
.O(sgf_result_o0__1_carry_i_17__1_n_0));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_18__2
(.I0(p_0_in[2]),
.I1(p_0_in[1]),
.I2(\Data_A_i[18] [1]),
.I3(p_0_in[0]),
.I4(\Data_A_i[18] [0]),
.I5(\Data_A_i[18] [2]),
.O(\sgf_result_o[15]_3 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_19__2
(.I0(p_0_in[1]),
.I1(\Data_A_i[18] [1]),
.I2(p_0_in[0]),
.I3(\Data_A_i[18] [0]),
.O(\sgf_result_o[15]_5 ));
LUT6 #(
.INIT(64'h22DD22228B8B22DD))
sgf_result_o0__1_carry_i_1__6
(.I0(sgf_result_o0__1_carry_i_8__4_n_0),
.I1(\sgf_result_o[15] ),
.I2(sgf_result_o0__1_carry_i_10__10_n_0),
.I3(sgf_result_o0__1_carry_i_11__6_n_0),
.I4(\sgf_result_o[15]_0 ),
.I5(sgf_result_o0__1_carry_i_13__4_n_0),
.O(sgf_result_o0__1_carry_i_1__6_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_20__1
(.I0(\Data_B_i[18]_0 [1]),
.I1(\Data_B_i[18] [1]),
.I2(\Data_B_i[18]_0 [0]),
.I3(\Data_B_i[18] [0]),
.O(\sgf_result_o[15]_7 ));
LUT6 #(
.INIT(64'hE01F1F801F80807F))
sgf_result_o0__1_carry_i_21__1
(.I0(\Data_B_i[18] [3]),
.I1(\sgf_result_o[15]_6 ),
.I2(\sgf_result_o[15]_0 ),
.I3(\Data_B_i[18] [2]),
.I4(CO),
.I5(\sgf_result_o[15]_7 ),
.O(sgf_result_o0__1_carry_i_21__1_n_0));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_22
(.I0(CO),
.I1(\Data_B_i[18]_0 [1]),
.I2(\Data_B_i[18] [1]),
.I3(\Data_B_i[18]_0 [0]),
.I4(\Data_B_i[18] [0]),
.I5(\Data_B_i[18] [2]),
.O(sgf_result_o0__1_carry_i_22_n_0));
LUT5 #(
.INIT(32'hA30A9039))
sgf_result_o0__1_carry_i_2__6
(.I0(sgf_result_o0__1_carry_i_8__4_n_0),
.I1(sgf_result_o0__1_carry_i_10__10_n_0),
.I2(sgf_result_o0__1_carry_i_13__4_n_0),
.I3(\sgf_result_o[15]_0 ),
.I4(\sgf_result_o[15] ),
.O(sgf_result_o0__1_carry_i_2__6_n_0));
LUT2 #(
.INIT(4'h2))
sgf_result_o0__1_carry_i_3__6
(.I0(sgf_result_o0__1_carry_i_8__4_n_0),
.I1(sgf_result_o0__1_carry_i_14__7_n_0),
.O(sgf_result_o0__1_carry_i_3__6_n_0));
LUT6 #(
.INIT(64'hAA6AAA6AAA6A5555))
sgf_result_o0__1_carry_i_4__6
(.I0(sgf_result_o0__1_carry_i_1__6_n_0),
.I1(sgf_result_o0__1_carry_i_15__1_n_0),
.I2(sgf_result_o0__1_carry_i_16__2_n_0),
.I3(sgf_result_o0__1_carry_i_10__10_n_0),
.I4(sgf_result_o0__1_carry_i_17__1_n_0),
.I5(sgf_result_o0__1_carry_i_14__7_n_0),
.O(sgf_result_o0__1_carry_i_4__6_n_0));
LUT3 #(
.INIT(8'hA9))
sgf_result_o0__1_carry_i_5__6
(.I0(sgf_result_o0__1_carry_i_2__6_n_0),
.I1(sgf_result_o0__1_carry_i_14__7_n_0),
.I2(sgf_result_o0__1_carry_i_11__6_n_0),
.O(sgf_result_o0__1_carry_i_5__6_n_0));
LUT4 #(
.INIT(16'h44B4))
sgf_result_o0__1_carry_i_6__11
(.I0(sgf_result_o0__1_carry_i_14__7_n_0),
.I1(sgf_result_o0__1_carry_i_8__4_n_0),
.I2(sgf_result_o0__1_carry_i_16__2_n_0),
.I3(sgf_result_o0__1_carry_i_10__10_n_0),
.O(sgf_result_o0__1_carry_i_6__11_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry_i_7__6
(.I0(sgf_result_o0__1_carry_i_10__10_n_0),
.I1(sgf_result_o0__1_carry_i_14__7_n_0),
.O(sgf_result_o0__1_carry_i_7__6_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
sgf_result_o0__1_carry_i_8__4
(.I0(\Data_A_i[18] [1]),
.I1(p_0_in[1]),
.I2(\sgf_result_o[15]_3 ),
.I3(\Data_A_i[18] [3]),
.I4(p_0_in[0]),
.I5(\Data_A_i[18] [0]),
.O(sgf_result_o0__1_carry_i_8__4_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry_i_9__0
(.I0(\Data_B_i[18] [0]),
.I1(\Data_B_i[18]_0 [0]),
.I2(\Data_B_i[18] [1]),
.I3(\Data_B_i[18]_0 [1]),
.I4(CO),
.I5(\Data_B_i[18] [2]),
.O(\sgf_result_o[15] ));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__0_carry__0_i_1__0
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_B_i[18]_1 ),
.O(\sgf_result_o[19] [1]));
(* HLUTNM = "lutpair27" *)
LUT2 #(
.INIT(4'hE))
sgf_result_o1__0_carry__0_i_2__0
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[18]_2 ),
.O(\sgf_result_o[19] [0]));
LUT3 #(
.INIT(8'h59))
sgf_result_o1__0_carry__0_i_3__0
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(\Data_A_i[22]_0 ),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(S[2]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__0_carry__0_i_4__0
(.I0(\Data_B_i[18]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[22]_0 ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(S[1]));
LUT3 #(
.INIT(8'h96))
sgf_result_o1__0_carry__0_i_5__0
(.I0(\sgf_result_o[19] [0]),
.I1(\Data_B_i[18]_1 ),
.I2(sgf_result_o0__1_carry__0_n_7),
.O(S[0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_12__0
(.I0(\Data_A_i[18] [0]),
.I1(p_0_in[0]),
.O(\sgf_result_o[15]_4 ));
LUT3 #(
.INIT(8'h71))
sgf_result_o1__0_carry_i_1__0
(.I0(\Data_A_i[22]_1 ),
.I1(\Data_A_i[22]_2 ),
.I2(sgf_result_o0__1_carry_n_5),
.O(DI[2]));
(* HLUTNM = "lutpair26" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__0_carry_i_2__0
(.I0(sgf_result_o0__1_carry_n_6),
.I1(\Data_B_i[22]_0 ),
.I2(\Data_A_i[22]_3 ),
.O(DI[1]));
LUT6 #(
.INIT(64'hA22AFBBFFBBFFBBF))
sgf_result_o1__0_carry_i_3__0
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\sgf_result_o[15]_4 ),
.I2(\Data_B_i[18] [0]),
.I3(\Data_B_i[18]_0 [0]),
.I4(\Data_A_i[22] ),
.I5(\Data_B_i[22] ),
.O(DI[0]));
(* HLUTNM = "lutpair27" *)
LUT5 #(
.INIT(32'h99696966))
sgf_result_o1__0_carry_i_4__0
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[18]_2 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[22]_2 ),
.I4(\Data_A_i[22]_1 ),
.O(\sgf_result_o[15]_8 [3]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_5__0
(.I0(DI[1]),
.I1(\Data_A_i[22]_1 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[22]_2 ),
.O(\sgf_result_o[15]_8 [2]));
(* HLUTNM = "lutpair26" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_6__0
(.I0(sgf_result_o0__1_carry_n_6),
.I1(\Data_B_i[22]_0 ),
.I2(\Data_A_i[22]_3 ),
.I3(DI[0]),
.O(\sgf_result_o[15]_8 [1]));
LUT6 #(
.INIT(64'h9999966996699999))
sgf_result_o1__0_carry_i_7__0
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[22]_4 ),
.I2(\Data_B_i[18]_0 [0]),
.I3(\Data_B_i[18] [0]),
.I4(p_0_in[0]),
.I5(\Data_A_i[18] [0]),
.O(\sgf_result_o[15]_8 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized16
(sgf_result_o_OBUF,
O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
Data_A_i_IBUF,
Data_B_i_IBUF,
S,
\Data_A_i[5] ,
\Data_A_i[11] ,
\Data_A_i[8] );
output [9:0]sgf_result_o_OBUF;
output [1:0]O;
output [0:0]\sgf_result_o[47] ;
output [1:0]\sgf_result_o[47]_0 ;
output [1:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [2:0]\sgf_result_o[47]_4 ;
input [11:0]Data_A_i_IBUF;
input [11:0]Data_B_i_IBUF;
input [0:0]S;
input [0:0]\Data_A_i[5] ;
input [0:0]\Data_A_i[11] ;
input [2:0]\Data_A_i[8] ;
wire [0:0]\Data_A_i[11] ;
wire [0:0]\Data_A_i[5] ;
wire [2:0]\Data_A_i[8] ;
wire [11:0]Data_A_i_IBUF;
wire [11:0]Data_B_i_IBUF;
wire \EVEN1.left_high_n_0 ;
wire \EVEN1.left_high_n_1 ;
wire \EVEN1.left_high_n_2 ;
wire \EVEN1.left_high_n_3 ;
wire \EVEN1.left_high_n_4 ;
wire \EVEN1.left_high_n_7 ;
wire \EVEN1.left_high_n_8 ;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_10 ;
wire \EVEN1.middle_n_11 ;
wire \EVEN1.middle_n_12 ;
wire \EVEN1.middle_n_13 ;
wire \EVEN1.middle_n_14 ;
wire \EVEN1.middle_n_15 ;
wire \EVEN1.middle_n_16 ;
wire \EVEN1.middle_n_17 ;
wire \EVEN1.middle_n_18 ;
wire \EVEN1.middle_n_19 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_20 ;
wire \EVEN1.middle_n_21 ;
wire \EVEN1.middle_n_22 ;
wire \EVEN1.middle_n_23 ;
wire \EVEN1.middle_n_24 ;
wire \EVEN1.middle_n_25 ;
wire \EVEN1.middle_n_26 ;
wire \EVEN1.middle_n_27 ;
wire \EVEN1.middle_n_28 ;
wire \EVEN1.middle_n_29 ;
wire \EVEN1.middle_n_3 ;
wire \EVEN1.middle_n_30 ;
wire \EVEN1.middle_n_4 ;
wire \EVEN1.middle_n_5 ;
wire \EVEN1.middle_n_6 ;
wire \EVEN1.middle_n_7 ;
wire \EVEN1.middle_n_8 ;
wire \EVEN1.middle_n_9 ;
wire \EVEN1.right_lower_n_11 ;
wire \EVEN1.right_lower_n_12 ;
wire \EVEN1.right_lower_n_13 ;
wire \EVEN1.right_lower_n_14 ;
wire \EVEN1.right_lower_n_15 ;
wire \EVEN1.right_lower_n_16 ;
wire \EVEN1.right_lower_n_17 ;
wire \EVEN1.right_lower_n_18 ;
wire \EVEN1.right_lower_n_19 ;
wire \EVEN1.right_lower_n_20 ;
wire \EVEN1.right_lower_n_21 ;
wire \EVEN1.right_lower_n_22 ;
wire \EVEN1.right_lower_n_23 ;
wire \EVEN1.right_lower_n_24 ;
wire \EVEN1.right_lower_n_29 ;
wire \EVEN1.right_lower_n_30 ;
wire \EVEN1.right_lower_n_31 ;
wire \EVEN1.right_lower_n_32 ;
wire \EVEN1.right_lower_n_33 ;
wire \EVEN1.right_lower_n_34 ;
wire \EVEN1.right_lower_n_35 ;
wire \EVEN1.right_lower_n_36 ;
wire \EVEN1.right_lower_n_37 ;
wire \EVEN1.right_lower_n_38 ;
wire \EVEN1.right_lower_n_39 ;
wire \EVEN1.right_lower_n_40 ;
wire \EVEN1.right_lower_n_41 ;
wire \EVEN1.right_lower_n_42 ;
wire \EVEN1.right_lower_n_43 ;
wire \EVEN1.right_lower_n_44 ;
wire \EVEN1.right_lower_n_45 ;
wire \EVEN1.right_lower_n_46 ;
wire \EVEN1.right_lower_n_47 ;
wire \EVEN1.right_lower_n_48 ;
wire [1:0]O;
wire [13:3]Q_middle_temp__0;
wire [0:0]S;
wire S_B0__0_carry__0_i_10_n_0;
wire S_B0__0_carry__0_i_7_n_0;
wire S_B0__0_carry__0_i_8_n_0;
wire S_B0__0_carry__0_i_9_n_0;
wire S_B0__0_carry_i_10__3_n_0;
wire S_B0__0_carry_i_11_n_0;
wire S_B0__0_carry_i_12_n_0;
wire S_B0__0_carry_i_8_n_0;
wire S_B0__0_carry_i_9_n_0;
wire S_B0__30_carry__0_i_1_n_0;
wire S_B0__30_carry__0_i_2_n_0;
wire S_B0__30_carry__0_i_3_n_0;
wire S_B0__30_carry__0_i_4_n_0;
wire S_B0__30_carry__0_i_5_n_0;
wire S_B0__30_carry__0_i_6_n_0;
wire S_B0__30_carry__0_i_7_n_0;
wire S_B0__30_carry__0_i_8_n_0;
wire S_B0__30_carry__1_i_13_n_0;
wire S_B0__30_carry__1_i_1_n_0;
wire S_B0__30_carry__1_i_2_n_0;
wire S_B0__30_carry__1_i_3_n_0;
wire S_B0__30_carry__1_i_4_n_0;
wire S_B0__30_carry__1_i_5_n_0;
wire S_B0__30_carry__1_i_6_n_0;
wire S_B0__30_carry__1_i_7_n_0;
wire S_B0__30_carry__1_i_8_n_0;
wire S_B0__30_carry__2_i_1_n_0;
wire S_B0__30_carry__2_i_2_n_0;
wire S_B0__30_carry_i_12_n_0;
wire S_B0_carry__0_i_5_n_0;
wire sgf_result_o0__1_carry__0_i_1__1_n_0;
wire sgf_result_o0__1_carry__0_i_2__1_n_0;
wire sgf_result_o0__1_carry__0_i_3__4_n_0;
wire sgf_result_o0__1_carry__0_i_4__1_n_0;
wire sgf_result_o0__1_carry__0_i_5__4_n_0;
wire sgf_result_o0__1_carry__0_i_6__2_n_0;
wire sgf_result_o0__1_carry__0_i_7__0_n_0;
wire sgf_result_o0__1_carry__0_i_8__1_n_0;
wire sgf_result_o0__1_carry__0_i_9__0_n_0;
wire sgf_result_o0__1_carry_i_10_n_0;
wire sgf_result_o0__1_carry_i_11__1_n_0;
wire sgf_result_o0__1_carry_i_12_n_0;
wire sgf_result_o0__1_carry_i_13_n_0;
wire sgf_result_o0__1_carry_i_14_n_0;
wire sgf_result_o0__1_carry_i_15_n_0;
wire sgf_result_o0__1_carry_i_16_n_0;
wire sgf_result_o0__1_carry_i_17_n_0;
wire sgf_result_o0__1_carry_i_18_n_0;
wire sgf_result_o0__1_carry_i_19_n_0;
wire sgf_result_o0__1_carry_i_1__1_n_0;
wire sgf_result_o0__1_carry_i_2__1_n_0;
wire sgf_result_o0__1_carry_i_3__1_n_0;
wire sgf_result_o0__1_carry_i_4__1_n_0;
wire sgf_result_o0__1_carry_i_5__1_n_0;
wire sgf_result_o0__1_carry_i_6__1_n_0;
wire sgf_result_o0__1_carry_i_7__1_n_0;
wire sgf_result_o0__1_carry_i_8__8_n_0;
wire sgf_result_o0__1_carry_i_8__8_n_1;
wire sgf_result_o0__1_carry_i_8__8_n_2;
wire sgf_result_o0__1_carry_i_8__8_n_3;
wire sgf_result_o0__1_carry_i_8__8_n_4;
wire sgf_result_o0__1_carry_i_8__8_n_5;
wire sgf_result_o0__1_carry_i_8__8_n_6;
wire sgf_result_o0__1_carry_i_8__8_n_7;
wire sgf_result_o0__1_carry_i_9__3_n_0;
wire sgf_result_o0__1_carry_i_9__3_n_1;
wire sgf_result_o0__1_carry_i_9__3_n_2;
wire sgf_result_o0__1_carry_i_9__3_n_3;
wire sgf_result_o0__1_carry_i_9__3_n_4;
wire sgf_result_o0__1_carry_i_9__3_n_5;
wire sgf_result_o0__1_carry_i_9__3_n_6;
wire sgf_result_o0__1_carry_i_9__3_n_7;
wire sgf_result_o1__0_carry_i_13__0_n_1;
wire sgf_result_o1__0_carry_i_13__0_n_3;
wire sgf_result_o1__0_carry_i_13__0_n_6;
wire sgf_result_o1__0_carry_i_13__0_n_7;
wire sgf_result_o1__0_carry_i_18_n_1;
wire sgf_result_o1__0_carry_i_18_n_3;
wire sgf_result_o1__0_carry_i_18_n_6;
wire sgf_result_o1__0_carry_i_18_n_7;
wire sgf_result_o1__0_carry_i_20_n_0;
wire sgf_result_o1__0_carry_i_21_n_0;
wire sgf_result_o1__0_carry_i_23_n_0;
wire sgf_result_o1__0_carry_i_24_n_0;
wire sgf_result_o1__21_carry__0_i_10_n_0;
wire sgf_result_o1__21_carry__0_i_9_n_0;
wire sgf_result_o1__21_carry_i_10_n_0;
wire sgf_result_o1__21_carry_i_8_n_0;
wire sgf_result_o1__21_carry_i_9_n_0;
wire sgf_result_o1_carry_i_4_n_0;
wire [0:0]\sgf_result_o[47] ;
wire [1:0]\sgf_result_o[47]_0 ;
wire [1:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [2:0]\sgf_result_o[47]_4 ;
wire [9:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[4]_inst_i_5_n_0 ;
wire [3:1]NLW_sgf_result_o1__0_carry_i_13__0_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__0_carry_i_13__0_O_UNCONNECTED;
wire [3:1]NLW_sgf_result_o1__0_carry_i_18_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__0_carry_i_18_O_UNCONNECTED;
Recursive_KOA__parameterized17 \EVEN1.left_high
(.Data_A_i_IBUF(Data_A_i_IBUF[11:6]),
.\Data_B_i[10] (S),
.Data_B_i_IBUF(Data_B_i_IBUF[11:6]),
.O({\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 ,\EVEN1.left_high_n_3 ,\EVEN1.left_high_n_4 }),
.S(S_B0__30_carry_i_12_n_0),
.\sgf_result_o[47] (\EVEN1.left_high_n_0 ),
.\sgf_result_o[47]_0 ({\sgf_result_o[47]_0 ,\EVEN1.left_high_n_7 ,\EVEN1.left_high_n_8 }),
.\sgf_result_o[47]_1 (O));
Recursive_KOA__parameterized25 \EVEN1.middle
(.CO(sgf_result_o1__0_carry_i_18_n_1),
.DI({sgf_result_o0__1_carry_i_1__1_n_0,sgf_result_o0__1_carry_i_2__1_n_0,sgf_result_o0__1_carry_i_3__1_n_0}),
.\Data_A_i[10] (sgf_result_o1_carry_i_4_n_0),
.\Data_A_i[11] ({\EVEN1.left_high_n_3 ,\EVEN1.left_high_n_4 }),
.\Data_A_i[11]_0 ({\EVEN1.right_lower_n_35 ,\EVEN1.right_lower_n_36 ,\EVEN1.right_lower_n_37 ,\Data_A_i[5] }),
.\Data_A_i[11]_1 ({\Data_A_i[11] ,\EVEN1.right_lower_n_46 ,\EVEN1.right_lower_n_47 ,\EVEN1.right_lower_n_48 }),
.\Data_A_i[2] ({\EVEN1.right_lower_n_19 ,\EVEN1.right_lower_n_20 ,\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 }),
.\Data_A_i[2]_0 ({\EVEN1.right_lower_n_42 ,\EVEN1.right_lower_n_43 ,\EVEN1.right_lower_n_44 ,\EVEN1.right_lower_n_45 }),
.\Data_A_i[2]_1 ({\EVEN1.right_lower_n_23 ,\EVEN1.right_lower_n_24 }),
.\Data_A_i[5] ({\EVEN1.right_lower_n_11 ,\EVEN1.right_lower_n_12 ,\EVEN1.right_lower_n_13 ,\EVEN1.right_lower_n_14 }),
.\Data_A_i[5]_0 ({\EVEN1.right_lower_n_15 ,\EVEN1.right_lower_n_16 ,\EVEN1.right_lower_n_17 ,\EVEN1.right_lower_n_18 }),
.\Data_A_i[5]_1 ({\EVEN1.right_lower_n_38 ,\EVEN1.right_lower_n_39 ,\EVEN1.right_lower_n_40 ,\EVEN1.right_lower_n_41 }),
.\Data_A_i[6] ({sgf_result_o0__1_carry__0_i_4__1_n_0,sgf_result_o0__1_carry__0_i_5__4_n_0,sgf_result_o0__1_carry__0_i_6__2_n_0}),
.\Data_A_i[6]_0 ({sgf_result_o0__1_carry_i_9__3_n_4,sgf_result_o0__1_carry_i_9__3_n_5,sgf_result_o0__1_carry_i_9__3_n_6,sgf_result_o0__1_carry_i_9__3_n_7}),
.\Data_A_i[6]_1 ({sgf_result_o1__0_carry_i_18_n_6,sgf_result_o1__0_carry_i_18_n_7}),
.\Data_A_i[6]_2 (sgf_result_o1__21_carry_i_10_n_0),
.\Data_A_i[6]_3 (sgf_result_o1__21_carry_i_8_n_0),
.\Data_A_i[6]_4 (sgf_result_o1__21_carry_i_9_n_0),
.\Data_A_i[6]_5 (sgf_result_o1__21_carry__0_i_10_n_0),
.\Data_A_i[6]_6 (Q_middle_temp__0[3]),
.\Data_A_i[8] (\Data_A_i[8] ),
.Data_A_i_IBUF({Data_A_i_IBUF[7:6],Data_A_i_IBUF[0]}),
.\Data_B_i[0] (sgf_result_o_OBUF[0]),
.\Data_B_i[6] ({sgf_result_o0__1_carry__0_i_1__1_n_0,sgf_result_o0__1_carry__0_i_2__1_n_0,sgf_result_o0__1_carry__0_i_3__4_n_0}),
.\Data_B_i[6]_0 ({sgf_result_o0__1_carry_i_8__8_n_4,sgf_result_o0__1_carry_i_8__8_n_5,sgf_result_o0__1_carry_i_8__8_n_6,sgf_result_o0__1_carry_i_8__8_n_7}),
.\Data_B_i[6]_1 ({sgf_result_o1__0_carry_i_13__0_n_6,sgf_result_o1__0_carry_i_13__0_n_7}),
.\Data_B_i[6]_2 (sgf_result_o1__0_carry_i_13__0_n_1),
.\Data_B_i[6]_3 (sgf_result_o1__21_carry__0_i_9_n_0),
.\Data_B_i[6]_4 (S_B0_carry__0_i_5_n_0),
.\Data_B_i[6]_5 (\EVEN1.left_high_n_0 ),
.Data_B_i_IBUF({Data_B_i_IBUF[7:6],Data_B_i_IBUF[0]}),
.O({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 ,\EVEN1.middle_n_3 }),
.S({sgf_result_o0__1_carry_i_4__1_n_0,sgf_result_o0__1_carry_i_5__1_n_0,sgf_result_o0__1_carry_i_6__1_n_0,sgf_result_o0__1_carry_i_7__1_n_0}),
.\sgf_result_o[47] ({\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 }),
.\sgf_result_o[47]_0 (\EVEN1.middle_n_8 ),
.\sgf_result_o[47]_1 ({\EVEN1.middle_n_9 ,\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 }),
.\sgf_result_o[47]_10 (sgf_result_o_OBUF[9:4]),
.\sgf_result_o[47]_11 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_12 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_13 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_14 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_2 (\EVEN1.middle_n_12 ),
.\sgf_result_o[47]_3 (\EVEN1.middle_n_13 ),
.\sgf_result_o[47]_4 (\EVEN1.middle_n_14 ),
.\sgf_result_o[47]_5 (\EVEN1.middle_n_15 ),
.\sgf_result_o[47]_6 ({\EVEN1.middle_n_16 ,\EVEN1.middle_n_17 ,\EVEN1.middle_n_18 }),
.\sgf_result_o[47]_7 ({\EVEN1.middle_n_19 ,\EVEN1.middle_n_20 ,\EVEN1.middle_n_21 ,\EVEN1.middle_n_22 }),
.\sgf_result_o[47]_8 ({\EVEN1.middle_n_23 ,\EVEN1.middle_n_24 ,\EVEN1.middle_n_25 ,\EVEN1.middle_n_26 }),
.\sgf_result_o[47]_9 ({\EVEN1.middle_n_27 ,\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.sgf_result_o_OBUF(sgf_result_o_OBUF[2:1]));
Recursive_KOA__parameterized21 \EVEN1.right_lower
(.DI({S_B0__30_carry__0_i_1_n_0,S_B0__30_carry__0_i_2_n_0,S_B0__30_carry__0_i_3_n_0,S_B0__30_carry__0_i_4_n_0}),
.\Data_A_i[11] ({\EVEN1.middle_n_27 ,\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.\Data_A_i[11]_0 ({\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 ,\EVEN1.left_high_n_3 ,\EVEN1.left_high_n_4 }),
.\Data_A_i[11]_1 ({\EVEN1.left_high_n_7 ,\EVEN1.left_high_n_8 }),
.\Data_A_i[2] ({S_B0__30_carry__1_i_5_n_0,S_B0__30_carry__1_i_6_n_0,S_B0__30_carry__1_i_7_n_0,S_B0__30_carry__1_i_8_n_0}),
.\Data_A_i[2]_0 (S_B0__0_carry_i_8_n_0),
.\Data_A_i[2]_1 (S_B0__0_carry_i_10__3_n_0),
.\Data_A_i[2]_2 (S_B0__0_carry__0_i_8_n_0),
.\Data_A_i[2]_3 (\sgf_result_o_OBUF[4]_inst_i_5_n_0 ),
.\Data_A_i[5] ({\EVEN1.middle_n_9 ,\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 }),
.\Data_A_i[5]_0 (S_B0__0_carry_i_9_n_0),
.\Data_A_i[5]_1 (S_B0__0_carry_i_11_n_0),
.\Data_A_i[5]_2 (S_B0__0_carry__0_i_7_n_0),
.\Data_A_i[6] ({\EVEN1.middle_n_19 ,\EVEN1.middle_n_20 ,\EVEN1.middle_n_21 ,\EVEN1.middle_n_22 }),
.\Data_A_i[6]_0 ({\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 }),
.\Data_A_i[6]_1 (\EVEN1.middle_n_8 ),
.\Data_A_i[6]_2 ({S_B0__30_carry__2_i_1_n_0,S_B0__30_carry__2_i_2_n_0}),
.\Data_A_i[8] ({S_B0__30_carry__1_i_1_n_0,S_B0__30_carry__1_i_2_n_0,S_B0__30_carry__1_i_3_n_0,S_B0__30_carry__1_i_4_n_0}),
.Data_A_i_IBUF(Data_A_i_IBUF[7:0]),
.\Data_B_i[0] (sgf_result_o_OBUF[0]),
.\Data_B_i[1] (S_B0__0_carry__0_i_9_n_0),
.\Data_B_i[3] (S_B0__0_carry_i_12_n_0),
.\Data_B_i[4] (S_B0__0_carry__0_i_10_n_0),
.\Data_B_i[4]_0 (S_B0__30_carry__1_i_13_n_0),
.\Data_B_i[6] ({\EVEN1.middle_n_23 ,\EVEN1.middle_n_24 ,\EVEN1.middle_n_25 ,\EVEN1.middle_n_26 }),
.\Data_B_i[6]_0 ({\EVEN1.middle_n_16 ,\EVEN1.middle_n_17 ,\EVEN1.middle_n_18 }),
.Data_B_i_IBUF(Data_B_i_IBUF[7:0]),
.O({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 ,\EVEN1.middle_n_3 }),
.Q_middle_temp__0(Q_middle_temp__0),
.S({S_B0__30_carry__0_i_5_n_0,S_B0__30_carry__0_i_6_n_0,S_B0__30_carry__0_i_7_n_0,S_B0__30_carry__0_i_8_n_0}),
.\sgf_result_o[47] ({\EVEN1.right_lower_n_11 ,\EVEN1.right_lower_n_12 ,\EVEN1.right_lower_n_13 ,\EVEN1.right_lower_n_14 }),
.\sgf_result_o[47]_0 ({\EVEN1.right_lower_n_15 ,\EVEN1.right_lower_n_16 ,\EVEN1.right_lower_n_17 ,\EVEN1.right_lower_n_18 }),
.\sgf_result_o[47]_1 ({\EVEN1.right_lower_n_19 ,\EVEN1.right_lower_n_20 ,\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 }),
.\sgf_result_o[47]_2 ({\EVEN1.right_lower_n_23 ,\EVEN1.right_lower_n_24 }),
.\sgf_result_o[47]_3 ({\sgf_result_o[47] ,sgf_result_o_OBUF[3:1]}),
.\sgf_result_o[47]_4 ({\EVEN1.right_lower_n_29 ,\EVEN1.right_lower_n_30 ,\EVEN1.right_lower_n_31 ,\EVEN1.right_lower_n_32 }),
.\sgf_result_o[47]_5 ({\EVEN1.right_lower_n_33 ,\EVEN1.right_lower_n_34 }),
.\sgf_result_o[47]_6 ({\EVEN1.right_lower_n_35 ,\EVEN1.right_lower_n_36 ,\EVEN1.right_lower_n_37 }),
.\sgf_result_o[47]_7 ({\EVEN1.right_lower_n_38 ,\EVEN1.right_lower_n_39 ,\EVEN1.right_lower_n_40 ,\EVEN1.right_lower_n_41 }),
.\sgf_result_o[47]_8 ({\EVEN1.right_lower_n_42 ,\EVEN1.right_lower_n_43 ,\EVEN1.right_lower_n_44 ,\EVEN1.right_lower_n_45 }),
.\sgf_result_o[47]_9 ({\EVEN1.right_lower_n_46 ,\EVEN1.right_lower_n_47 ,\EVEN1.right_lower_n_48 }));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__0_carry__0_i_10
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__0_carry__0_i_10_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_7
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_8
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry__0_i_8_n_0));
LUT6 #(
.INIT(64'h55FF7FFF7FFFFFFF))
S_B0__0_carry__0_i_9
(.I0(Data_A_i_IBUF[2]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_B_i_IBUF[2]),
.I4(Data_A_i_IBUF[1]),
.I5(Data_B_i_IBUF[1]),
.O(S_B0__0_carry__0_i_9_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_10__3
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_10__3_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_11
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_11_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_12
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_B_i_IBUF[3]),
.O(S_B0__0_carry_i_12_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_8
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_8_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_9
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_9_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_1
(.I0(Q_middle_temp__0[6]),
.I1(\EVEN1.left_high_n_8 ),
.I2(\EVEN1.right_lower_n_32 ),
.O(S_B0__30_carry__0_i_1_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_2
(.I0(Q_middle_temp__0[5]),
.I1(\EVEN1.left_high_n_1 ),
.I2(\sgf_result_o[47] ),
.O(S_B0__30_carry__0_i_2_n_0));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_3
(.I0(Q_middle_temp__0[4]),
.I1(\EVEN1.left_high_n_2 ),
.I2(sgf_result_o_OBUF[3]),
.O(S_B0__30_carry__0_i_3_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__0_i_4
(.I0(Q_middle_temp__0[3]),
.I1(\EVEN1.left_high_n_3 ),
.I2(sgf_result_o_OBUF[2]),
.O(S_B0__30_carry__0_i_4_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_5
(.I0(Q_middle_temp__0[7]),
.I1(\EVEN1.left_high_n_7 ),
.I2(\EVEN1.right_lower_n_31 ),
.I3(S_B0__30_carry__0_i_1_n_0),
.O(S_B0__30_carry__0_i_5_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_6
(.I0(Q_middle_temp__0[6]),
.I1(\EVEN1.left_high_n_8 ),
.I2(\EVEN1.right_lower_n_32 ),
.I3(S_B0__30_carry__0_i_2_n_0),
.O(S_B0__30_carry__0_i_6_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_7
(.I0(Q_middle_temp__0[5]),
.I1(\EVEN1.left_high_n_1 ),
.I2(\sgf_result_o[47] ),
.I3(S_B0__30_carry__0_i_3_n_0),
.O(S_B0__30_carry__0_i_7_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__0_i_8
(.I0(Q_middle_temp__0[4]),
.I1(\EVEN1.left_high_n_2 ),
.I2(sgf_result_o_OBUF[3]),
.I3(S_B0__30_carry__0_i_4_n_0),
.O(S_B0__30_carry__0_i_8_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_1
(.I0(Q_middle_temp__0[10]),
.I1(O[0]),
.I2(\EVEN1.right_lower_n_34 ),
.O(S_B0__30_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__30_carry__1_i_13
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__1_i_13_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_2
(.I0(Q_middle_temp__0[9]),
.I1(\sgf_result_o[47]_0 [1]),
.I2(\EVEN1.right_lower_n_29 ),
.O(S_B0__30_carry__1_i_2_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_3
(.I0(Q_middle_temp__0[8]),
.I1(\sgf_result_o[47]_0 [0]),
.I2(\EVEN1.right_lower_n_30 ),
.O(S_B0__30_carry__1_i_3_n_0));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry__1_i_4
(.I0(Q_middle_temp__0[7]),
.I1(\EVEN1.left_high_n_7 ),
.I2(\EVEN1.right_lower_n_31 ),
.O(S_B0__30_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_5
(.I0(S_B0__30_carry__1_i_1_n_0),
.I1(Q_middle_temp__0[11]),
.I2(O[1]),
.I3(\EVEN1.right_lower_n_33 ),
.O(S_B0__30_carry__1_i_5_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_6
(.I0(Q_middle_temp__0[10]),
.I1(O[0]),
.I2(\EVEN1.right_lower_n_34 ),
.I3(S_B0__30_carry__1_i_2_n_0),
.O(S_B0__30_carry__1_i_6_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_7
(.I0(Q_middle_temp__0[9]),
.I1(\sgf_result_o[47]_0 [1]),
.I2(\EVEN1.right_lower_n_29 ),
.I3(S_B0__30_carry__1_i_3_n_0),
.O(S_B0__30_carry__1_i_7_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry__1_i_8
(.I0(Q_middle_temp__0[8]),
.I1(\sgf_result_o[47]_0 [0]),
.I2(\EVEN1.right_lower_n_30 ),
.I3(S_B0__30_carry__1_i_4_n_0),
.O(S_B0__30_carry__1_i_8_n_0));
LUT1 #(
.INIT(2'h1))
S_B0__30_carry__2_i_1
(.I0(Q_middle_temp__0[13]),
.O(S_B0__30_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h8E71))
S_B0__30_carry__2_i_2
(.I0(\EVEN1.right_lower_n_33 ),
.I1(O[1]),
.I2(Q_middle_temp__0[11]),
.I3(Q_middle_temp__0[12]),
.O(S_B0__30_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__30_carry_i_12
(.I0(Data_B_i_IBUF[7]),
.I1(Data_A_i_IBUF[7]),
.I2(Data_B_i_IBUF[8]),
.I3(Data_A_i_IBUF[6]),
.I4(Data_B_i_IBUF[6]),
.I5(Data_A_i_IBUF[8]),
.O(S_B0__30_carry_i_12_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h8))
S_B0_carry__0_i_5
(.I0(sgf_result_o1__0_carry_i_18_n_6),
.I1(sgf_result_o1__0_carry_i_13__0_n_6),
.O(S_B0_carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_1__1
(.I0(sgf_result_o0__1_carry_i_9__3_n_4),
.I1(sgf_result_o0__1_carry_i_8__8_n_4),
.O(sgf_result_o0__1_carry__0_i_1__1_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
sgf_result_o0__1_carry__0_i_2__1
(.I0(sgf_result_o0__1_carry_i_10_n_0),
.I1(sgf_result_o0__1_carry_i_8__8_n_6),
.I2(sgf_result_o0__1_carry_i_9__3_n_7),
.I3(sgf_result_o0__1_carry_i_8__8_n_7),
.I4(sgf_result_o0__1_carry_i_9__3_n_4),
.I5(sgf_result_o0__1_carry__0_i_7__0_n_0),
.O(sgf_result_o0__1_carry__0_i_2__1_n_0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
sgf_result_o0__1_carry__0_i_3__4
(.I0(sgf_result_o0__1_carry_i_10_n_0),
.I1(sgf_result_o0__1_carry_i_8__8_n_6),
.I2(sgf_result_o0__1_carry_i_9__3_n_7),
.I3(sgf_result_o0__1_carry_i_8__8_n_7),
.I4(sgf_result_o0__1_carry_i_9__3_n_4),
.I5(sgf_result_o0__1_carry__0_i_7__0_n_0),
.O(sgf_result_o0__1_carry__0_i_3__4_n_0));
LUT6 #(
.INIT(64'h173F8080C0000000))
sgf_result_o0__1_carry__0_i_4__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_6),
.I1(sgf_result_o0__1_carry_i_9__3_n_5),
.I2(sgf_result_o0__1_carry_i_8__8_n_5),
.I3(sgf_result_o0__1_carry_i_9__3_n_6),
.I4(sgf_result_o0__1_carry_i_8__8_n_4),
.I5(sgf_result_o0__1_carry_i_9__3_n_4),
.O(sgf_result_o0__1_carry__0_i_4__1_n_0));
LUT6 #(
.INIT(64'h9666699969996999))
sgf_result_o0__1_carry__0_i_5__4
(.I0(sgf_result_o0__1_carry__0_i_2__1_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__1_n_0),
.I2(sgf_result_o0__1_carry_i_9__3_n_4),
.I3(sgf_result_o0__1_carry_i_8__8_n_5),
.I4(sgf_result_o0__1_carry_i_9__3_n_5),
.I5(sgf_result_o0__1_carry_i_8__8_n_4),
.O(sgf_result_o0__1_carry__0_i_5__4_n_0));
LUT6 #(
.INIT(64'h56666AAA6AAA6AAA))
sgf_result_o0__1_carry__0_i_6__2
(.I0(sgf_result_o0__1_carry__0_i_3__4_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__0_n_0),
.I2(sgf_result_o0__1_carry_i_9__3_n_6),
.I3(sgf_result_o0__1_carry_i_8__8_n_5),
.I4(sgf_result_o0__1_carry_i_9__3_n_7),
.I5(sgf_result_o0__1_carry_i_8__8_n_4),
.O(sgf_result_o0__1_carry__0_i_6__2_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry__0_i_7__0
(.I0(sgf_result_o0__1_carry_i_8__8_n_6),
.I1(sgf_result_o0__1_carry_i_9__3_n_4),
.I2(sgf_result_o0__1_carry_i_9__3_n_5),
.I3(sgf_result_o0__1_carry_i_8__8_n_5),
.I4(sgf_result_o0__1_carry_i_9__3_n_6),
.I5(sgf_result_o0__1_carry_i_8__8_n_4),
.O(sgf_result_o0__1_carry__0_i_7__0_n_0));
LUT6 #(
.INIT(64'h07777FFF7FFF7FFF))
sgf_result_o0__1_carry__0_i_8__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_4),
.I1(sgf_result_o0__1_carry_i_9__3_n_6),
.I2(sgf_result_o0__1_carry_i_8__8_n_5),
.I3(sgf_result_o0__1_carry_i_9__3_n_5),
.I4(sgf_result_o0__1_carry_i_9__3_n_4),
.I5(sgf_result_o0__1_carry_i_8__8_n_6),
.O(sgf_result_o0__1_carry__0_i_8__1_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_9__0
(.I0(sgf_result_o0__1_carry_i_9__3_n_5),
.I1(sgf_result_o0__1_carry_i_8__8_n_6),
.O(sgf_result_o0__1_carry__0_i_9__0_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_10
(.I0(sgf_result_o0__1_carry_i_9__3_n_6),
.I1(sgf_result_o0__1_carry_i_8__8_n_5),
.O(sgf_result_o0__1_carry_i_10_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_11__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_7),
.I1(sgf_result_o0__1_carry_i_9__3_n_4),
.O(sgf_result_o0__1_carry_i_11__1_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_12
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[9]),
.O(sgf_result_o0__1_carry_i_12_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_13
(.I0(Data_B_i_IBUF[2]),
.I1(Data_B_i_IBUF[8]),
.O(sgf_result_o0__1_carry_i_13_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_14
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[7]),
.O(sgf_result_o0__1_carry_i_14_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_15
(.I0(Data_B_i_IBUF[0]),
.I1(Data_B_i_IBUF[6]),
.O(sgf_result_o0__1_carry_i_15_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_16
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[9]),
.O(sgf_result_o0__1_carry_i_16_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_17
(.I0(Data_A_i_IBUF[2]),
.I1(Data_A_i_IBUF[8]),
.O(sgf_result_o0__1_carry_i_17_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_18
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[7]),
.O(sgf_result_o0__1_carry_i_18_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_19
(.I0(Data_A_i_IBUF[0]),
.I1(Data_A_i_IBUF[6]),
.O(sgf_result_o0__1_carry_i_19_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_1__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_6),
.I1(sgf_result_o0__1_carry_i_9__3_n_5),
.I2(sgf_result_o0__1_carry_i_9__3_n_6),
.I3(sgf_result_o0__1_carry_i_8__8_n_5),
.I4(sgf_result_o0__1_carry_i_9__3_n_7),
.I5(sgf_result_o0__1_carry_i_8__8_n_4),
.O(sgf_result_o0__1_carry_i_1__1_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_2__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_6),
.I1(sgf_result_o0__1_carry_i_9__3_n_6),
.I2(sgf_result_o0__1_carry_i_8__8_n_5),
.I3(sgf_result_o0__1_carry_i_9__3_n_7),
.O(sgf_result_o0__1_carry_i_2__1_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_3__1
(.I0(sgf_result_o0__1_carry_i_9__3_n_7),
.I1(sgf_result_o0__1_carry_i_8__8_n_6),
.O(sgf_result_o0__1_carry_i_3__1_n_0));
LUT6 #(
.INIT(64'h99A5C30F665A3CF0))
sgf_result_o0__1_carry_i_4__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_4),
.I1(sgf_result_o0__1_carry_i_9__3_n_5),
.I2(sgf_result_o0__1_carry_i_10_n_0),
.I3(sgf_result_o0__1_carry_i_8__8_n_6),
.I4(sgf_result_o0__1_carry_i_9__3_n_7),
.I5(sgf_result_o0__1_carry_i_11__1_n_0),
.O(sgf_result_o0__1_carry_i_4__1_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_5__1
(.I0(sgf_result_o0__1_carry_i_9__3_n_7),
.I1(sgf_result_o0__1_carry_i_8__8_n_5),
.I2(sgf_result_o0__1_carry_i_9__3_n_6),
.I3(sgf_result_o0__1_carry_i_8__8_n_6),
.I4(sgf_result_o0__1_carry_i_9__3_n_5),
.I5(sgf_result_o0__1_carry_i_8__8_n_7),
.O(sgf_result_o0__1_carry_i_5__1_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_6__1
(.I0(sgf_result_o0__1_carry_i_9__3_n_6),
.I1(sgf_result_o0__1_carry_i_8__8_n_7),
.I2(sgf_result_o0__1_carry_i_8__8_n_6),
.I3(sgf_result_o0__1_carry_i_9__3_n_7),
.O(sgf_result_o0__1_carry_i_6__1_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_7__1
(.I0(sgf_result_o0__1_carry_i_8__8_n_7),
.I1(sgf_result_o0__1_carry_i_9__3_n_7),
.O(sgf_result_o0__1_carry_i_7__1_n_0));
CARRY4 sgf_result_o0__1_carry_i_8__8
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_8__8_n_0,sgf_result_o0__1_carry_i_8__8_n_1,sgf_result_o0__1_carry_i_8__8_n_2,sgf_result_o0__1_carry_i_8__8_n_3}),
.CYINIT(1'b0),
.DI(Data_B_i_IBUF[3:0]),
.O({sgf_result_o0__1_carry_i_8__8_n_4,sgf_result_o0__1_carry_i_8__8_n_5,sgf_result_o0__1_carry_i_8__8_n_6,sgf_result_o0__1_carry_i_8__8_n_7}),
.S({sgf_result_o0__1_carry_i_12_n_0,sgf_result_o0__1_carry_i_13_n_0,sgf_result_o0__1_carry_i_14_n_0,sgf_result_o0__1_carry_i_15_n_0}));
CARRY4 sgf_result_o0__1_carry_i_9__3
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_9__3_n_0,sgf_result_o0__1_carry_i_9__3_n_1,sgf_result_o0__1_carry_i_9__3_n_2,sgf_result_o0__1_carry_i_9__3_n_3}),
.CYINIT(1'b0),
.DI(Data_A_i_IBUF[3:0]),
.O({sgf_result_o0__1_carry_i_9__3_n_4,sgf_result_o0__1_carry_i_9__3_n_5,sgf_result_o0__1_carry_i_9__3_n_6,sgf_result_o0__1_carry_i_9__3_n_7}),
.S({sgf_result_o0__1_carry_i_16_n_0,sgf_result_o0__1_carry_i_17_n_0,sgf_result_o0__1_carry_i_18_n_0,sgf_result_o0__1_carry_i_19_n_0}));
CARRY4 sgf_result_o1__0_carry_i_13__0
(.CI(sgf_result_o0__1_carry_i_8__8_n_0),
.CO({NLW_sgf_result_o1__0_carry_i_13__0_CO_UNCONNECTED[3],sgf_result_o1__0_carry_i_13__0_n_1,NLW_sgf_result_o1__0_carry_i_13__0_CO_UNCONNECTED[1],sgf_result_o1__0_carry_i_13__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_B_i_IBUF[5:4]}),
.O({NLW_sgf_result_o1__0_carry_i_13__0_O_UNCONNECTED[3:2],sgf_result_o1__0_carry_i_13__0_n_6,sgf_result_o1__0_carry_i_13__0_n_7}),
.S({1'b0,1'b1,sgf_result_o1__0_carry_i_20_n_0,sgf_result_o1__0_carry_i_21_n_0}));
CARRY4 sgf_result_o1__0_carry_i_18
(.CI(sgf_result_o0__1_carry_i_9__3_n_0),
.CO({NLW_sgf_result_o1__0_carry_i_18_CO_UNCONNECTED[3],sgf_result_o1__0_carry_i_18_n_1,NLW_sgf_result_o1__0_carry_i_18_CO_UNCONNECTED[1],sgf_result_o1__0_carry_i_18_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_A_i_IBUF[5:4]}),
.O({NLW_sgf_result_o1__0_carry_i_18_O_UNCONNECTED[3:2],sgf_result_o1__0_carry_i_18_n_6,sgf_result_o1__0_carry_i_18_n_7}),
.S({1'b0,1'b1,sgf_result_o1__0_carry_i_23_n_0,sgf_result_o1__0_carry_i_24_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_20
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[11]),
.O(sgf_result_o1__0_carry_i_20_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_21
(.I0(Data_B_i_IBUF[4]),
.I1(Data_B_i_IBUF[10]),
.O(sgf_result_o1__0_carry_i_21_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_23
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[11]),
.O(sgf_result_o1__0_carry_i_23_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_24
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[10]),
.O(sgf_result_o1__0_carry_i_24_n_0));
LUT6 #(
.INIT(64'h67878F8F7FFF7FFF))
sgf_result_o1__21_carry__0_i_10
(.I0(sgf_result_o1__0_carry_i_13__0_n_6),
.I1(sgf_result_o1__0_carry_i_18_n_6),
.I2(sgf_result_o1__0_carry_i_13__0_n_1),
.I3(sgf_result_o1__0_carry_i_18_n_7),
.I4(sgf_result_o1__0_carry_i_13__0_n_7),
.I5(sgf_result_o1__0_carry_i_18_n_1),
.O(sgf_result_o1__21_carry__0_i_10_n_0));
LUT6 #(
.INIT(64'hE080808000000000))
sgf_result_o1__21_carry__0_i_9
(.I0(sgf_result_o1__0_carry_i_18_n_6),
.I1(sgf_result_o1__0_carry_i_13__0_n_6),
.I2(sgf_result_o1__0_carry_i_18_n_1),
.I3(sgf_result_o1__0_carry_i_13__0_n_7),
.I4(sgf_result_o1__0_carry_i_18_n_7),
.I5(sgf_result_o1__0_carry_i_13__0_n_1),
.O(sgf_result_o1__21_carry__0_i_9_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'h7888))
sgf_result_o1__21_carry_i_10
(.I0(sgf_result_o1__0_carry_i_13__0_n_6),
.I1(sgf_result_o1__0_carry_i_18_n_7),
.I2(sgf_result_o1__0_carry_i_18_n_6),
.I3(sgf_result_o1__0_carry_i_13__0_n_7),
.O(sgf_result_o1__21_carry_i_10_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
sgf_result_o1__21_carry_i_8
(.I0(sgf_result_o1__0_carry_i_13__0_n_6),
.I1(sgf_result_o1__0_carry_i_18_n_6),
.I2(sgf_result_o1__0_carry_i_13__0_n_1),
.I3(sgf_result_o1__0_carry_i_18_n_7),
.I4(sgf_result_o1__0_carry_i_13__0_n_7),
.I5(sgf_result_o1__0_carry_i_18_n_1),
.O(sgf_result_o1__21_carry_i_8_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
sgf_result_o1__21_carry_i_9
(.I0(sgf_result_o1__0_carry_i_13__0_n_6),
.I1(sgf_result_o1__0_carry_i_18_n_6),
.I2(sgf_result_o1__0_carry_i_13__0_n_1),
.I3(sgf_result_o1__0_carry_i_18_n_7),
.I4(sgf_result_o1__0_carry_i_13__0_n_7),
.I5(sgf_result_o1__0_carry_i_18_n_1),
.O(sgf_result_o1__21_carry_i_9_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1_carry_i_4
(.I0(\EVEN1.middle_n_15 ),
.I1(\EVEN1.middle_n_12 ),
.I2(\EVEN1.middle_n_14 ),
.I3(\EVEN1.middle_n_13 ),
.I4(sgf_result_o1__0_carry_i_13__0_n_7),
.I5(sgf_result_o0__1_carry_i_8__8_n_7),
.O(sgf_result_o1_carry_i_4_n_0));
LUT4 #(
.INIT(16'h7888))
\sgf_result_o_OBUF[1]_inst_i_1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[0]),
.O(sgf_result_o_OBUF[0]));
LUT6 #(
.INIT(64'h0F777888F0887888))
\sgf_result_o_OBUF[4]_inst_i_5
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(\sgf_result_o_OBUF[4]_inst_i_5_n_0 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized17
(\sgf_result_o[47] ,
O,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
Data_A_i_IBUF,
Data_B_i_IBUF,
S,
\Data_B_i[10] );
output \sgf_result_o[47] ;
output [3:0]O;
output [3:0]\sgf_result_o[47]_0 ;
output [1:0]\sgf_result_o[47]_1 ;
input [5:0]Data_A_i_IBUF;
input [5:0]Data_B_i_IBUF;
input [0:0]S;
input [0:0]\Data_B_i[10] ;
wire [5:0]Data_A_i_IBUF;
wire [0:0]\Data_B_i[10] ;
wire [5:0]Data_B_i_IBUF;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_10 ;
wire \EVEN1.middle_n_11 ;
wire \EVEN1.middle_n_12 ;
wire \EVEN1.middle_n_13 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_3 ;
wire \EVEN1.middle_n_4 ;
wire \EVEN1.middle_n_5 ;
wire \EVEN1.middle_n_6 ;
wire \EVEN1.middle_n_7 ;
wire \EVEN1.middle_n_8 ;
wire \EVEN1.middle_n_9 ;
wire [3:0]O;
wire [0:0]S;
wire S_B0__0_carry__0_i_10__0_n_0;
wire S_B0__0_carry__0_i_7__0_n_0;
wire S_B0__0_carry__0_i_8__0_n_0;
wire S_B0__0_carry__0_i_9__0_n_0;
wire S_B0__0_carry__0_n_1;
wire S_B0__0_carry__0_n_2;
wire S_B0__0_carry__0_n_3;
wire S_B0__0_carry__0_n_4;
wire S_B0__0_carry__0_n_5;
wire S_B0__0_carry__0_n_6;
wire S_B0__0_carry__0_n_7;
wire S_B0__0_carry_i_11__0_n_0;
wire S_B0__0_carry_i_12__0_n_0;
wire S_B0__0_carry_i_13_n_0;
wire S_B0__0_carry_i_8__0_n_0;
wire S_B0__0_carry_i_9__0_n_0;
wire S_B0__0_carry_n_0;
wire S_B0__0_carry_n_1;
wire S_B0__0_carry_n_2;
wire S_B0__0_carry_n_3;
wire S_B0__0_carry_n_4;
wire S_B0__0_carry_n_5;
wire S_B0__0_carry_n_6;
wire S_B0__0_carry_n_7;
wire S_B0__30_carry__0_i_11_n_0;
wire S_B0__30_carry__0_i_12_n_0;
wire S_B0__30_carry__0_i_13_n_0;
wire S_B0__30_carry__0_i_14_n_0;
wire S_B0__30_carry__1_i_12_n_0;
wire S_B0__30_carry_i_10_n_0;
wire S_B0__30_carry_i_11_n_0;
wire S_B0__30_carry_i_9__0_n_0;
wire sgf_result_o0__1_carry__0_i_10__1_n_0;
wire sgf_result_o0__1_carry__0_i_1__0_n_0;
wire sgf_result_o0__1_carry__0_i_2__0_n_0;
wire sgf_result_o0__1_carry__0_i_3__11_n_0;
wire sgf_result_o0__1_carry__0_i_4__0_n_0;
wire sgf_result_o0__1_carry__0_i_5__3_n_0;
wire sgf_result_o0__1_carry__0_i_6__1_n_0;
wire sgf_result_o0__1_carry__0_i_7__7_n_0;
wire sgf_result_o0__1_carry__0_i_8__0_n_0;
wire sgf_result_o0__1_carry__0_i_9_n_0;
wire sgf_result_o0__1_carry_i_10__7_n_0;
wire sgf_result_o0__1_carry_i_11__0_n_0;
wire sgf_result_o0__1_carry_i_12__1_n_0;
wire sgf_result_o0__1_carry_i_13__1_n_0;
wire sgf_result_o0__1_carry_i_14__3_n_0;
wire sgf_result_o0__1_carry_i_1__0_n_0;
wire sgf_result_o0__1_carry_i_2__0_n_0;
wire sgf_result_o0__1_carry_i_3__0_n_0;
wire sgf_result_o0__1_carry_i_4__0_n_0;
wire sgf_result_o0__1_carry_i_5__0_n_0;
wire sgf_result_o0__1_carry_i_6__0_n_0;
wire sgf_result_o0__1_carry_i_7__0_n_0;
wire sgf_result_o0__1_carry_i_8__0_n_0;
wire sgf_result_o0__1_carry_i_9__9_n_0;
wire \sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [1:0]\sgf_result_o[47]_1 ;
wire [3:3]NLW_S_B0__0_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized20 \EVEN1.middle
(.DI({sgf_result_o0__1_carry_i_1__0_n_0,sgf_result_o0__1_carry_i_2__0_n_0,sgf_result_o0__1_carry_i_3__0_n_0}),
.\Data_A_i[11] ({sgf_result_o0__1_carry__0_i_1__0_n_0,sgf_result_o0__1_carry__0_i_2__0_n_0,sgf_result_o0__1_carry__0_i_3__11_n_0}),
.\Data_A_i[11]_0 (S_B0__0_carry_i_9__0_n_0),
.\Data_A_i[11]_1 (S_B0__0_carry_i_12__0_n_0),
.\Data_A_i[11]_2 (S_B0__0_carry__0_i_8__0_n_0),
.\Data_A_i[11]_3 ({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.\Data_A_i[11]_4 ({S_B0__30_carry_i_9__0_n_0,S_B0__30_carry_i_10_n_0,S_B0__30_carry_i_11_n_0,S}),
.\Data_A_i[11]_5 ({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.\Data_A_i[7] ({sgf_result_o0__1_carry__0_i_4__0_n_0,sgf_result_o0__1_carry__0_i_5__3_n_0,sgf_result_o0__1_carry__0_i_6__1_n_0}),
.\Data_A_i[8] (S_B0__0_carry_i_8__0_n_0),
.\Data_A_i[8]_0 (S_B0__0_carry_i_11__0_n_0),
.\Data_A_i[8]_1 (S_B0__0_carry__0_i_7__0_n_0),
.\Data_A_i[8]_2 ({S_B0__30_carry__0_i_11_n_0,S_B0__30_carry__0_i_12_n_0,S_B0__30_carry__0_i_13_n_0,S_B0__30_carry__0_i_14_n_0}),
.Data_A_i_IBUF({Data_A_i_IBUF[4:3],Data_A_i_IBUF[0]}),
.\Data_B_i[10] (S_B0__0_carry__0_i_10__0_n_0),
.\Data_B_i[10]_0 ({\Data_B_i[10] ,S_B0__30_carry__1_i_12_n_0}),
.\Data_B_i[6] (\sgf_result_o[47] ),
.\Data_B_i[7] (S_B0__0_carry__0_i_9__0_n_0),
.\Data_B_i[9] (S_B0__0_carry_i_13_n_0),
.Data_B_i_IBUF({Data_B_i_IBUF[4:3],Data_B_i_IBUF[0]}),
.O(O),
.S({sgf_result_o0__1_carry_i_4__0_n_0,sgf_result_o0__1_carry_i_5__0_n_0,sgf_result_o0__1_carry_i_6__0_n_0,sgf_result_o0__1_carry_i_7__0_n_0}),
.\sgf_result_o[47] ({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.\sgf_result_o[47]_0 ({\EVEN1.middle_n_3 ,\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 }),
.\sgf_result_o[47]_1 ({\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 ,\EVEN1.middle_n_8 ,\EVEN1.middle_n_9 }),
.\sgf_result_o[47]_2 ({\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 ,\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 }),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_1 ));
CARRY4 S_B0__0_carry
(.CI(1'b0),
.CO({S_B0__0_carry_n_0,S_B0__0_carry_n_1,S_B0__0_carry_n_2,S_B0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\EVEN1.middle_n_3 ,\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,1'b1}),
.O({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.S({\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 ,\EVEN1.middle_n_8 ,\EVEN1.middle_n_9 }));
CARRY4 S_B0__0_carry__0
(.CI(S_B0__0_carry_n_0),
.CO({NLW_S_B0__0_carry__0_CO_UNCONNECTED[3],S_B0__0_carry__0_n_1,S_B0__0_carry__0_n_2,S_B0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.O({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.S({\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 ,\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 }));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__0_carry__0_i_10__0
(.I0(Data_A_i_IBUF[5]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[5]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_B_i_IBUF[4]),
.O(S_B0__0_carry__0_i_10__0_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_7__0
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry__0_i_7__0_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_8__0
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry__0_i_8__0_n_0));
LUT6 #(
.INIT(64'h55FF7FFF7FFFFFFF))
S_B0__0_carry__0_i_9__0
(.I0(Data_A_i_IBUF[2]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_B_i_IBUF[2]),
.I4(Data_A_i_IBUF[1]),
.I5(Data_B_i_IBUF[1]),
.O(S_B0__0_carry__0_i_9__0_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_10
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[0]),
.O(\sgf_result_o[47] ));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_11__0
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_11__0_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_12__0
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_12__0_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_13
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_B_i_IBUF[3]),
.O(S_B0__0_carry_i_13_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_8__0
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_B_i_IBUF[2]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_A_i_IBUF[2]),
.O(S_B0__0_carry_i_8__0_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_9__0
(.I0(Data_B_i_IBUF[4]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_B_i_IBUF[5]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[3]),
.I5(Data_A_i_IBUF[5]),
.O(S_B0__0_carry_i_9__0_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry__0_i_11
(.I0(S_B0__0_carry__0_n_5),
.I1(S_B0__0_carry_i_12__0_n_0),
.O(S_B0__30_carry__0_i_11_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__0_i_12
(.I0(S_B0__0_carry__0_n_6),
.I1(S_B0__0_carry_i_9__0_n_0),
.O(S_B0__30_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0__30_carry__0_i_13
(.I0(S_B0__0_carry__0_n_7),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__0_i_13_n_0));
LUT3 #(
.INIT(8'h6A))
S_B0__30_carry__0_i_14
(.I0(S_B0__0_carry_n_4),
.I1(Data_A_i_IBUF[3]),
.I2(Data_B_i_IBUF[3]),
.O(S_B0__30_carry__0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__1_i_12
(.I0(S_B0__0_carry__0_n_4),
.I1(S_B0__0_carry__0_i_8__0_n_0),
.O(S_B0__30_carry__1_i_12_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry_i_10
(.I0(S_B0__0_carry_n_6),
.I1(S_B0__0_carry__0_i_7__0_n_0),
.O(S_B0__30_carry_i_10_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry_i_11
(.I0(S_B0__0_carry_n_7),
.I1(S_B0__0_carry_i_11__0_n_0),
.O(S_B0__30_carry_i_11_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry_i_9__0
(.I0(S_B0__0_carry_n_5),
.I1(S_B0__0_carry__0_i_9__0_n_0),
.O(S_B0__30_carry_i_9__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_10__1
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_8__0_n_0),
.O(sgf_result_o0__1_carry__0_i_10__1_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_1__0
(.I0(sgf_result_o0__1_carry_i_11__0_n_0),
.I1(sgf_result_o0__1_carry_i_13__1_n_0),
.O(sgf_result_o0__1_carry__0_i_1__0_n_0));
LUT5 #(
.INIT(32'h14000000))
sgf_result_o0__1_carry__0_i_2__0
(.I0(sgf_result_o0__1_carry_i_13__1_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_3__0_n_0),
.I4(sgf_result_o0__1_carry_i_10__7_n_0),
.O(sgf_result_o0__1_carry__0_i_2__0_n_0));
LUT6 #(
.INIT(64'h1EE11EE11EE1E11E))
sgf_result_o0__1_carry__0_i_3__11
(.I0(sgf_result_o0__1_carry_i_12__1_n_0),
.I1(sgf_result_o0__1_carry_i_8__0_n_0),
.I2(sgf_result_o0__1_carry__0_i_2__0_n_0),
.I3(sgf_result_o0__1_carry__0_i_7__7_n_0),
.I4(sgf_result_o0__1_carry_i_9__9_n_0),
.I5(sgf_result_o0__1_carry_i_13__1_n_0),
.O(sgf_result_o0__1_carry__0_i_3__11_n_0));
LUT6 #(
.INIT(64'h000001010003FCE8))
sgf_result_o0__1_carry__0_i_4__0
(.I0(sgf_result_o0__1_carry_i_9__9_n_0),
.I1(sgf_result_o0__1_carry_i_12__1_n_0),
.I2(sgf_result_o0__1_carry_i_8__0_n_0),
.I3(sgf_result_o0__1_carry_i_14__3_n_0),
.I4(sgf_result_o0__1_carry_i_13__1_n_0),
.I5(sgf_result_o0__1_carry_i_11__0_n_0),
.O(sgf_result_o0__1_carry__0_i_4__0_n_0));
LUT6 #(
.INIT(64'h9996999699966669))
sgf_result_o0__1_carry__0_i_5__3
(.I0(sgf_result_o0__1_carry__0_i_2__0_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__0_n_0),
.I2(sgf_result_o0__1_carry_i_12__1_n_0),
.I3(sgf_result_o0__1_carry_i_13__1_n_0),
.I4(sgf_result_o0__1_carry_i_8__0_n_0),
.I5(sgf_result_o0__1_carry_i_11__0_n_0),
.O(sgf_result_o0__1_carry__0_i_5__3_n_0));
LUT6 #(
.INIT(64'hA595AA99AAA9AAAA))
sgf_result_o0__1_carry__0_i_6__1
(.I0(sgf_result_o0__1_carry__0_i_3__11_n_0),
.I1(sgf_result_o0__1_carry_i_14__3_n_0),
.I2(sgf_result_o0__1_carry_i_11__0_n_0),
.I3(sgf_result_o0__1_carry_i_12__1_n_0),
.I4(sgf_result_o0__1_carry__0_i_9_n_0),
.I5(sgf_result_o0__1_carry__0_i_10__1_n_0),
.O(sgf_result_o0__1_carry__0_i_6__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_7__7
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_11__0_n_0),
.O(sgf_result_o0__1_carry__0_i_7__7_n_0));
LUT6 #(
.INIT(64'hFFFEFFFEFFFEEEE0))
sgf_result_o0__1_carry__0_i_8__0
(.I0(sgf_result_o0__1_carry_i_11__0_n_0),
.I1(sgf_result_o0__1_carry_i_14__3_n_0),
.I2(sgf_result_o0__1_carry_i_8__0_n_0),
.I3(sgf_result_o0__1_carry_i_12__1_n_0),
.I4(sgf_result_o0__1_carry_i_9__9_n_0),
.I5(sgf_result_o0__1_carry_i_13__1_n_0),
.O(sgf_result_o0__1_carry__0_i_8__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry__0_i_9
(.I0(Data_A_i_IBUF[0]),
.I1(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry__0_i_9_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry_i_10__7
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_12__1_n_0),
.O(sgf_result_o0__1_carry_i_10__7_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_11__0
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[2]),
.I5(Data_B_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_11__0_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_12__1
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[2]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.I4(Data_B_i_IBUF[4]),
.I5(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_12__1_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_13__1
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[2]),
.I5(Data_A_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_13__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_14__3
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_14__3_n_0));
LUT6 #(
.INIT(64'hE1E1E1E1E11E1EE1))
sgf_result_o0__1_carry_i_1__0
(.I0(sgf_result_o0__1_carry_i_8__0_n_0),
.I1(sgf_result_o0__1_carry_i_9__9_n_0),
.I2(sgf_result_o0__1_carry_i_10__7_n_0),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_11__0_n_0),
.O(sgf_result_o0__1_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h0906060609F9F906))
sgf_result_o0__1_carry_i_2__0
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[1]),
.I2(sgf_result_o0__1_carry_i_9__9_n_0),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[3]),
.I5(sgf_result_o0__1_carry_i_12__1_n_0),
.O(sgf_result_o0__1_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h6006066006600660))
sgf_result_o0__1_carry_i_3__0
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[1]),
.I3(Data_B_i_IBUF[4]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h6A6A6A6A6A95956A))
sgf_result_o0__1_carry_i_4__0
(.I0(sgf_result_o0__1_carry_i_1__0_n_0),
.I1(sgf_result_o0__1_carry_i_10__7_n_0),
.I2(sgf_result_o0__1_carry_i_3__0_n_0),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_13__1_n_0),
.O(sgf_result_o0__1_carry_i_4__0_n_0));
LUT4 #(
.INIT(16'hA99A))
sgf_result_o0__1_carry_i_5__0
(.I0(sgf_result_o0__1_carry_i_2__0_n_0),
.I1(sgf_result_o0__1_carry_i_8__0_n_0),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_5__0_n_0));
LUT6 #(
.INIT(64'h141414EB14EB1414))
sgf_result_o0__1_carry_i_6__0
(.I0(sgf_result_o0__1_carry_i_14__3_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_9__9_n_0),
.I4(Data_A_i_IBUF[0]),
.I5(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_6__0_n_0));
LUT4 #(
.INIT(16'h0660))
sgf_result_o0__1_carry_i_7__0
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.O(sgf_result_o0__1_carry_i_7__0_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_8__0
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_8__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_9__9
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[4]),
.I3(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_9__9_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized20
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
O,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
DI,
S,
\Data_A_i[11] ,
\Data_A_i[7] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[6] ,
\Data_B_i[9] ,
\Data_B_i[7] ,
\Data_B_i[10] ,
\Data_A_i[8] ,
\Data_A_i[11]_0 ,
\Data_A_i[8]_0 ,
\Data_A_i[11]_1 ,
\Data_A_i[8]_1 ,
\Data_A_i[11]_2 ,
\Data_A_i[11]_3 ,
\Data_A_i[11]_4 ,
\Data_A_i[11]_5 ,
\Data_A_i[8]_2 ,
\Data_B_i[10]_0 );
output [2:0]\sgf_result_o[47] ;
output [2:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]O;
output [3:0]\sgf_result_o[47]_3 ;
output [1:0]\sgf_result_o[47]_4 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_A_i[11] ;
input [2:0]\Data_A_i[7] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[6] ;
input \Data_B_i[9] ;
input \Data_B_i[7] ;
input \Data_B_i[10] ;
input \Data_A_i[8] ;
input \Data_A_i[11]_0 ;
input \Data_A_i[8]_0 ;
input \Data_A_i[11]_1 ;
input \Data_A_i[8]_1 ;
input \Data_A_i[11]_2 ;
input [3:0]\Data_A_i[11]_3 ;
input [3:0]\Data_A_i[11]_4 ;
input [3:0]\Data_A_i[11]_5 ;
input [3:0]\Data_A_i[8]_2 ;
input [1:0]\Data_B_i[10]_0 ;
wire [2:0]DI;
wire [2:0]\Data_A_i[11] ;
wire \Data_A_i[11]_0 ;
wire \Data_A_i[11]_1 ;
wire \Data_A_i[11]_2 ;
wire [3:0]\Data_A_i[11]_3 ;
wire [3:0]\Data_A_i[11]_4 ;
wire [3:0]\Data_A_i[11]_5 ;
wire [2:0]\Data_A_i[7] ;
wire \Data_A_i[8] ;
wire \Data_A_i[8]_0 ;
wire \Data_A_i[8]_1 ;
wire [3:0]\Data_A_i[8]_2 ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[10] ;
wire [1:0]\Data_B_i[10]_0 ;
wire \Data_B_i[6] ;
wire \Data_B_i[7] ;
wire \Data_B_i[9] ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire [3:0]S;
wire S_B0__30_carry__0_i_9_n_0;
wire S_B0__30_carry__0_i_9_n_1;
wire S_B0__30_carry__0_i_9_n_2;
wire S_B0__30_carry__0_i_9_n_3;
wire S_B0__30_carry__1_i_9_n_3;
wire S_B0__30_carry_i_8_n_0;
wire S_B0__30_carry_i_8_n_1;
wire S_B0__30_carry_i_8_n_2;
wire S_B0__30_carry_i_8_n_3;
wire sgf_result_o0__1_carry__0_n_1;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_4;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [2:0]\sgf_result_o[47] ;
wire [2:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\^sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [1:0]\sgf_result_o[47]_4 ;
wire [3:1]NLW_S_B0__30_carry__1_i_9_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__1_i_9_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
assign \sgf_result_o[47]_2 [3] = sgf_result_o0__1_carry__0_n_4;
assign \sgf_result_o[47]_2 [2:0] = \^sgf_result_o[47]_2 [2:0];
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry__0_i_1__0
(.I0(\Data_A_i[8]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[11]_2 ),
.O(\sgf_result_o[47] [1]));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
S_B0__0_carry__0_i_2__0
(.I0(\Data_A_i[8]_0 ),
.I1(\Data_A_i[11]_1 ),
.I2(sgf_result_o0__1_carry_n_4),
.O(\sgf_result_o[47] [0]));
LUT4 #(
.INIT(16'h4DB2))
S_B0__0_carry__0_i_4__0
(.I0(\Data_B_i[7] ),
.I1(\Data_B_i[10] ),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\sgf_result_o[47] [2]),
.O(\^sgf_result_o[47]_2 [2]));
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry__0_i_5__0
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[7] ),
.I2(\Data_B_i[10] ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry__0_i_6__0
(.I0(\Data_A_i[8]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[11]_2 ),
.I3(\sgf_result_o[47] [0]),
.O(\^sgf_result_o[47]_2 [0]));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry_i_1__0
(.I0(\Data_A_i[8] ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[11]_0 ),
.O(\sgf_result_o[47]_0 [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__0_carry_i_2__0
(.I0(Data_B_i_IBUF[2]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[6] ),
.O(\sgf_result_o[47]_0 [1]));
(* HLUTNM = "lutpair79" *)
LUT5 #(
.INIT(32'h2ABFBFBF))
S_B0__0_carry_i_3__0
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_0 [0]));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_4__0
(.I0(\Data_A_i[8]_0 ),
.I1(\Data_A_i[11]_1 ),
.I2(sgf_result_o0__1_carry_n_4),
.I3(\sgf_result_o[47]_0 [2]),
.O(\sgf_result_o[47]_1 [3]));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_5__0
(.I0(\Data_A_i[8] ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[11]_0 ),
.I3(\sgf_result_o[47]_0 [1]),
.O(\sgf_result_o[47]_1 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_6__0
(.I0(\sgf_result_o[47]_0 [0]),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[6] ),
.I3(\Data_B_i[9] ),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair79" *)
LUT5 #(
.INIT(32'h6A959595))
S_B0__0_carry_i_7__0
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_1 [0]));
CARRY4 S_B0__30_carry__0_i_9
(.CI(S_B0__30_carry_i_8_n_0),
.CO({S_B0__30_carry__0_i_9_n_0,S_B0__30_carry__0_i_9_n_1,S_B0__30_carry__0_i_9_n_2,S_B0__30_carry__0_i_9_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[11]_5 [2:0],\Data_A_i[11]_3 [3]}),
.O(\sgf_result_o[47]_3 ),
.S(\Data_A_i[8]_2 ));
CARRY4 S_B0__30_carry__1_i_9
(.CI(S_B0__30_carry__0_i_9_n_0),
.CO({NLW_S_B0__30_carry__1_i_9_CO_UNCONNECTED[3:1],S_B0__30_carry__1_i_9_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Data_A_i[11]_5 [3]}),
.O({NLW_S_B0__30_carry__1_i_9_O_UNCONNECTED[3:2],\sgf_result_o[47]_4 }),
.S({1'b0,1'b0,\Data_B_i[10]_0 }));
CARRY4 S_B0__30_carry_i_8
(.CI(1'b0),
.CO({S_B0__30_carry_i_8_n_0,S_B0__30_carry_i_8_n_1,S_B0__30_carry_i_8_n_2,S_B0__30_carry_i_8_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[11]_3 [2:0],1'b0}),
.O(O),
.S(\Data_A_i[11]_4 ));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_1,sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[11] }),
.O({sgf_result_o0__1_carry__0_n_4,\sgf_result_o[47] [2],sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[7] }));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized21
(Q_middle_temp__0,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
O,
\Data_A_i[6] ,
\Data_A_i[6]_0 ,
\Data_B_i[6] ,
\Data_A_i[6]_1 ,
\Data_B_i[6]_0 ,
\Data_A_i[5] ,
\Data_A_i[11] ,
DI,
S,
\Data_A_i[8] ,
\Data_A_i[2] ,
\Data_A_i[6]_2 ,
Data_A_i_IBUF,
Data_B_i_IBUF,
\Data_B_i[0] ,
\Data_B_i[3] ,
\Data_B_i[1] ,
\Data_B_i[4] ,
\Data_A_i[2]_0 ,
\Data_A_i[5]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[5]_1 ,
\Data_A_i[5]_2 ,
\Data_A_i[2]_2 ,
\Data_A_i[2]_3 ,
\Data_B_i[4]_0 ,
\Data_A_i[11]_0 ,
\Data_A_i[11]_1 );
output [10:0]Q_middle_temp__0;
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [1:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [1:0]\sgf_result_o[47]_5 ;
output [2:0]\sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
output [2:0]\sgf_result_o[47]_9 ;
input [3:0]O;
input [3:0]\Data_A_i[6] ;
input [3:0]\Data_A_i[6]_0 ;
input [3:0]\Data_B_i[6] ;
input [0:0]\Data_A_i[6]_1 ;
input [2:0]\Data_B_i[6]_0 ;
input [2:0]\Data_A_i[5] ;
input [3:0]\Data_A_i[11] ;
input [3:0]DI;
input [3:0]S;
input [3:0]\Data_A_i[8] ;
input [3:0]\Data_A_i[2] ;
input [1:0]\Data_A_i[6]_2 ;
input [7:0]Data_A_i_IBUF;
input [7:0]Data_B_i_IBUF;
input \Data_B_i[0] ;
input \Data_B_i[3] ;
input \Data_B_i[1] ;
input \Data_B_i[4] ;
input \Data_A_i[2]_0 ;
input \Data_A_i[5]_0 ;
input \Data_A_i[2]_1 ;
input \Data_A_i[5]_1 ;
input \Data_A_i[5]_2 ;
input \Data_A_i[2]_2 ;
input [0:0]\Data_A_i[2]_3 ;
input [0:0]\Data_B_i[4]_0 ;
input [3:0]\Data_A_i[11]_0 ;
input [1:0]\Data_A_i[11]_1 ;
wire [3:0]DI;
wire [3:0]\Data_A_i[11] ;
wire [3:0]\Data_A_i[11]_0 ;
wire [1:0]\Data_A_i[11]_1 ;
wire [3:0]\Data_A_i[2] ;
wire \Data_A_i[2]_0 ;
wire \Data_A_i[2]_1 ;
wire \Data_A_i[2]_2 ;
wire [0:0]\Data_A_i[2]_3 ;
wire [2:0]\Data_A_i[5] ;
wire \Data_A_i[5]_0 ;
wire \Data_A_i[5]_1 ;
wire \Data_A_i[5]_2 ;
wire [3:0]\Data_A_i[6] ;
wire [3:0]\Data_A_i[6]_0 ;
wire [0:0]\Data_A_i[6]_1 ;
wire [1:0]\Data_A_i[6]_2 ;
wire [3:0]\Data_A_i[8] ;
wire [7:0]Data_A_i_IBUF;
wire \Data_B_i[0] ;
wire \Data_B_i[1] ;
wire \Data_B_i[3] ;
wire \Data_B_i[4] ;
wire [0:0]\Data_B_i[4]_0 ;
wire [3:0]\Data_B_i[6] ;
wire [2:0]\Data_B_i[6]_0 ;
wire [7:0]Data_B_i_IBUF;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_28 ;
wire \EVEN1.middle_n_29 ;
wire \EVEN1.middle_n_30 ;
wire \EVEN1.middle_n_31 ;
wire \EVEN1.middle_n_32 ;
wire \EVEN1.middle_n_33 ;
wire \EVEN1.middle_n_34 ;
wire \EVEN1.middle_n_35 ;
wire \EVEN1.middle_n_36 ;
wire \EVEN1.middle_n_37 ;
wire \EVEN1.middle_n_38 ;
wire [3:0]O;
wire [10:0]Q_middle_temp__0;
wire [3:0]S;
wire S_B0__0_carry__0_n_1;
wire S_B0__0_carry__0_n_2;
wire S_B0__0_carry__0_n_3;
wire S_B0__0_carry__0_n_4;
wire S_B0__0_carry__0_n_5;
wire S_B0__0_carry__0_n_6;
wire S_B0__0_carry__0_n_7;
wire S_B0__0_carry_n_0;
wire S_B0__0_carry_n_1;
wire S_B0__0_carry_n_2;
wire S_B0__0_carry_n_3;
wire S_B0__0_carry_n_4;
wire S_B0__0_carry_n_5;
wire S_B0__0_carry_n_6;
wire S_B0__0_carry_n_7;
wire S_B0__30_carry__0_i_15_n_0;
wire S_B0__30_carry__0_i_16_n_0;
wire S_B0__30_carry__0_i_17_n_0;
wire S_B0__30_carry__0_i_18_n_0;
wire S_B0__30_carry__1_i_14_n_0;
wire sgf_result_o0__1_carry__0_i_1_n_0;
wire sgf_result_o0__1_carry__0_i_2_n_0;
wire sgf_result_o0__1_carry__0_i_3__3_n_0;
wire sgf_result_o0__1_carry__0_i_4_n_0;
wire sgf_result_o0__1_carry__0_i_5__2_n_0;
wire sgf_result_o0__1_carry__0_i_6__0_n_0;
wire sgf_result_o0__1_carry__0_i_7_n_0;
wire sgf_result_o0__1_carry__0_i_8_n_0;
wire sgf_result_o0__1_carry__0_i_9__6_n_0;
wire sgf_result_o0__1_carry_i_10__6_n_0;
wire sgf_result_o0__1_carry_i_11_n_0;
wire sgf_result_o0__1_carry_i_12__0_n_0;
wire sgf_result_o0__1_carry_i_13__0_n_0;
wire sgf_result_o0__1_carry_i_14__2_n_0;
wire sgf_result_o0__1_carry_i_1_n_0;
wire sgf_result_o0__1_carry_i_2_n_0;
wire sgf_result_o0__1_carry_i_3_n_0;
wire sgf_result_o0__1_carry_i_4_n_0;
wire sgf_result_o0__1_carry_i_5_n_0;
wire sgf_result_o0__1_carry_i_6_n_0;
wire sgf_result_o0__1_carry_i_7_n_0;
wire sgf_result_o0__1_carry_i_8_n_0;
wire sgf_result_o0__1_carry_i_9__8_n_0;
wire [3:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [1:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [1:0]\sgf_result_o[47]_5 ;
wire [2:0]\sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [2:0]\sgf_result_o[47]_9 ;
wire \sgf_result_o_OBUF[4]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[4]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[4]_inst_i_4_n_0 ;
wire [3:3]NLW_S_B0__0_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized24 \EVEN1.middle
(.DI({sgf_result_o0__1_carry_i_1_n_0,sgf_result_o0__1_carry_i_2_n_0,sgf_result_o0__1_carry_i_3_n_0}),
.\Data_A_i[11] (\Data_A_i[11] ),
.\Data_A_i[11]_0 (\Data_A_i[11]_0 ),
.\Data_A_i[11]_1 (\Data_A_i[11]_1 ),
.\Data_A_i[1] ({sgf_result_o0__1_carry__0_i_4_n_0,sgf_result_o0__1_carry__0_i_5__2_n_0,sgf_result_o0__1_carry__0_i_6__0_n_0}),
.\Data_A_i[2] (S),
.\Data_A_i[2]_0 (\Data_A_i[2] ),
.\Data_A_i[2]_1 (\Data_A_i[2]_0 ),
.\Data_A_i[2]_2 (\Data_A_i[2]_1 ),
.\Data_A_i[2]_3 (\Data_A_i[2]_2 ),
.\Data_A_i[2]_4 ({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.\Data_A_i[2]_5 ({S_B0__30_carry__0_i_15_n_0,S_B0__30_carry__0_i_16_n_0,S_B0__30_carry__0_i_17_n_0,S_B0__30_carry__0_i_18_n_0}),
.\Data_A_i[5] ({sgf_result_o0__1_carry__0_i_1_n_0,sgf_result_o0__1_carry__0_i_2_n_0,sgf_result_o0__1_carry__0_i_3__3_n_0}),
.\Data_A_i[5]_0 (\Data_A_i[5] ),
.\Data_A_i[5]_1 (DI),
.\Data_A_i[5]_2 (\Data_A_i[5]_0 ),
.\Data_A_i[5]_3 (\Data_A_i[5]_1 ),
.\Data_A_i[5]_4 (\Data_A_i[5]_2 ),
.\Data_A_i[5]_5 ({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.\Data_A_i[5]_6 ({\sgf_result_o_OBUF[4]_inst_i_2_n_0 ,\sgf_result_o_OBUF[4]_inst_i_3_n_0 ,\sgf_result_o_OBUF[4]_inst_i_4_n_0 ,\Data_A_i[2]_3 }),
.\Data_A_i[6] (\Data_A_i[6] ),
.\Data_A_i[6]_0 (\Data_A_i[6]_0 ),
.\Data_A_i[6]_1 (\Data_A_i[6]_1 ),
.\Data_A_i[6]_2 (\Data_A_i[6]_2 ),
.\Data_A_i[8] (\Data_A_i[8] ),
.Data_A_i_IBUF({Data_A_i_IBUF[7:6],Data_A_i_IBUF[4:3],Data_A_i_IBUF[0]}),
.\Data_B_i[0] (\Data_B_i[0] ),
.\Data_B_i[1] (\Data_B_i[1] ),
.\Data_B_i[3] (\Data_B_i[3] ),
.\Data_B_i[4] (\Data_B_i[4] ),
.\Data_B_i[4]_0 ({\Data_B_i[4]_0 ,S_B0__30_carry__1_i_14_n_0}),
.\Data_B_i[6] (\Data_B_i[6] ),
.\Data_B_i[6]_0 (\Data_B_i[6]_0 ),
.Data_B_i_IBUF({Data_B_i_IBUF[7:6],Data_B_i_IBUF[4:3],Data_B_i_IBUF[0]}),
.O(O),
.Q_middle_temp__0(Q_middle_temp__0),
.S({sgf_result_o0__1_carry_i_4_n_0,sgf_result_o0__1_carry_i_5_n_0,sgf_result_o0__1_carry_i_6_n_0,sgf_result_o0__1_carry_i_7_n_0}),
.\sgf_result_o[47] ({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.\sgf_result_o[47]_0 (\sgf_result_o[47] ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_10 (\sgf_result_o[47]_6 ),
.\sgf_result_o[47]_11 (\sgf_result_o[47]_7 ),
.\sgf_result_o[47]_12 (\sgf_result_o[47]_8 ),
.\sgf_result_o[47]_13 (\sgf_result_o[47]_9 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_4 ({\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 }),
.\sgf_result_o[47]_5 ({\EVEN1.middle_n_31 ,\EVEN1.middle_n_32 ,\EVEN1.middle_n_33 ,\EVEN1.middle_n_34 }),
.\sgf_result_o[47]_6 ({\EVEN1.middle_n_35 ,\EVEN1.middle_n_36 ,\EVEN1.middle_n_37 ,\EVEN1.middle_n_38 }),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_8 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_9 (\sgf_result_o[47]_5 ));
CARRY4 S_B0__0_carry
(.CI(1'b0),
.CO({S_B0__0_carry_n_0,S_B0__0_carry_n_1,S_B0__0_carry_n_2,S_B0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\EVEN1.middle_n_28 ,\EVEN1.middle_n_29 ,\EVEN1.middle_n_30 ,1'b1}),
.O({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.S({\EVEN1.middle_n_31 ,\EVEN1.middle_n_32 ,\EVEN1.middle_n_33 ,\EVEN1.middle_n_34 }));
CARRY4 S_B0__0_carry__0
(.CI(S_B0__0_carry_n_0),
.CO({NLW_S_B0__0_carry__0_CO_UNCONNECTED[3],S_B0__0_carry__0_n_1,S_B0__0_carry__0_n_2,S_B0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.O({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.S({\EVEN1.middle_n_35 ,\EVEN1.middle_n_36 ,\EVEN1.middle_n_37 ,\EVEN1.middle_n_38 }));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry__0_i_15
(.I0(S_B0__0_carry__0_n_5),
.I1(\Data_A_i[5]_1 ),
.O(S_B0__30_carry__0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__0_i_16
(.I0(S_B0__0_carry__0_n_6),
.I1(\Data_A_i[5]_0 ),
.O(S_B0__30_carry__0_i_16_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0__30_carry__0_i_17
(.I0(S_B0__0_carry__0_n_7),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__0_i_17_n_0));
LUT3 #(
.INIT(8'h6A))
S_B0__30_carry__0_i_18
(.I0(S_B0__0_carry_n_4),
.I1(Data_A_i_IBUF[3]),
.I2(Data_B_i_IBUF[3]),
.O(S_B0__30_carry__0_i_18_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__1_i_14
(.I0(S_B0__0_carry__0_n_4),
.I1(\Data_A_i[5]_2 ),
.O(S_B0__30_carry__1_i_14_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_1
(.I0(sgf_result_o0__1_carry_i_11_n_0),
.I1(sgf_result_o0__1_carry_i_13__0_n_0),
.O(sgf_result_o0__1_carry__0_i_1_n_0));
LUT5 #(
.INIT(32'h14000000))
sgf_result_o0__1_carry__0_i_2
(.I0(sgf_result_o0__1_carry_i_13__0_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_3_n_0),
.I4(sgf_result_o0__1_carry_i_10__6_n_0),
.O(sgf_result_o0__1_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h56A956A956A9A956))
sgf_result_o0__1_carry__0_i_3__3
(.I0(sgf_result_o0__1_carry__0_i_2_n_0),
.I1(sgf_result_o0__1_carry_i_11_n_0),
.I2(sgf_result_o0__1_carry_i_14__2_n_0),
.I3(sgf_result_o0__1_carry__0_i_7_n_0),
.I4(sgf_result_o0__1_carry_i_9__8_n_0),
.I5(sgf_result_o0__1_carry_i_13__0_n_0),
.O(sgf_result_o0__1_carry__0_i_3__3_n_0));
LUT6 #(
.INIT(64'h000001010003FCE8))
sgf_result_o0__1_carry__0_i_4
(.I0(sgf_result_o0__1_carry_i_9__8_n_0),
.I1(sgf_result_o0__1_carry_i_12__0_n_0),
.I2(sgf_result_o0__1_carry_i_8_n_0),
.I3(sgf_result_o0__1_carry_i_14__2_n_0),
.I4(sgf_result_o0__1_carry_i_13__0_n_0),
.I5(sgf_result_o0__1_carry_i_11_n_0),
.O(sgf_result_o0__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9996999699966669))
sgf_result_o0__1_carry__0_i_5__2
(.I0(sgf_result_o0__1_carry__0_i_2_n_0),
.I1(sgf_result_o0__1_carry__0_i_8_n_0),
.I2(sgf_result_o0__1_carry_i_12__0_n_0),
.I3(sgf_result_o0__1_carry_i_13__0_n_0),
.I4(sgf_result_o0__1_carry_i_8_n_0),
.I5(sgf_result_o0__1_carry_i_11_n_0),
.O(sgf_result_o0__1_carry__0_i_5__2_n_0));
LUT6 #(
.INIT(64'h66666556AAAAA66A))
sgf_result_o0__1_carry__0_i_6__0
(.I0(sgf_result_o0__1_carry__0_i_3__3_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__6_n_0),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(sgf_result_o0__1_carry_i_11_n_0),
.I5(sgf_result_o0__1_carry_i_10__6_n_0),
.O(sgf_result_o0__1_carry__0_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_7
(.I0(sgf_result_o0__1_carry_i_12__0_n_0),
.I1(sgf_result_o0__1_carry_i_8_n_0),
.O(sgf_result_o0__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hFFFEFFFEFFFEEEE0))
sgf_result_o0__1_carry__0_i_8
(.I0(sgf_result_o0__1_carry_i_11_n_0),
.I1(sgf_result_o0__1_carry_i_14__2_n_0),
.I2(sgf_result_o0__1_carry_i_8_n_0),
.I3(sgf_result_o0__1_carry_i_12__0_n_0),
.I4(sgf_result_o0__1_carry_i_9__8_n_0),
.I5(sgf_result_o0__1_carry_i_13__0_n_0),
.O(sgf_result_o0__1_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_9__6
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_8_n_0),
.O(sgf_result_o0__1_carry__0_i_9__6_n_0));
LUT6 #(
.INIT(64'hE1E1E1E1E11E1EE1))
sgf_result_o0__1_carry_i_1
(.I0(sgf_result_o0__1_carry_i_8_n_0),
.I1(sgf_result_o0__1_carry_i_9__8_n_0),
.I2(sgf_result_o0__1_carry_i_10__6_n_0),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_11_n_0),
.O(sgf_result_o0__1_carry_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry_i_10__6
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_12__0_n_0),
.O(sgf_result_o0__1_carry_i_10__6_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_11
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[2]),
.I5(Data_B_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_11_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_12__0
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[2]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.I4(Data_B_i_IBUF[4]),
.I5(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_12__0_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_13__0
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[2]),
.I5(Data_A_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_13__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_14__2
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_14__2_n_0));
LUT6 #(
.INIT(64'h0906060609F9F906))
sgf_result_o0__1_carry_i_2
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[1]),
.I2(sgf_result_o0__1_carry_i_9__8_n_0),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[3]),
.I5(sgf_result_o0__1_carry_i_12__0_n_0),
.O(sgf_result_o0__1_carry_i_2_n_0));
LUT6 #(
.INIT(64'h6006066006600660))
sgf_result_o0__1_carry_i_3
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[1]),
.I3(Data_B_i_IBUF[4]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h6A6A6A6A6A95956A))
sgf_result_o0__1_carry_i_4
(.I0(sgf_result_o0__1_carry_i_1_n_0),
.I1(sgf_result_o0__1_carry_i_10__6_n_0),
.I2(sgf_result_o0__1_carry_i_3_n_0),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_13__0_n_0),
.O(sgf_result_o0__1_carry_i_4_n_0));
LUT4 #(
.INIT(16'hA99A))
sgf_result_o0__1_carry_i_5
(.I0(sgf_result_o0__1_carry_i_2_n_0),
.I1(sgf_result_o0__1_carry_i_8_n_0),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_5_n_0));
LUT6 #(
.INIT(64'h141414EB14EB1414))
sgf_result_o0__1_carry_i_6
(.I0(sgf_result_o0__1_carry_i_14__2_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_9__8_n_0),
.I4(Data_A_i_IBUF[0]),
.I5(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h0660))
sgf_result_o0__1_carry_i_7
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.O(sgf_result_o0__1_carry_i_7_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_8
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_9__8
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[4]),
.I3(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_9__8_n_0));
LUT2 #(
.INIT(4'h9))
\sgf_result_o_OBUF[4]_inst_i_2
(.I0(S_B0__0_carry_n_5),
.I1(\Data_B_i[1] ),
.O(\sgf_result_o_OBUF[4]_inst_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[4]_inst_i_3
(.I0(S_B0__0_carry_n_6),
.I1(\Data_A_i[2]_2 ),
.O(\sgf_result_o_OBUF[4]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\sgf_result_o_OBUF[4]_inst_i_4
(.I0(S_B0__0_carry_n_7),
.I1(\Data_A_i[2]_1 ),
.O(\sgf_result_o_OBUF[4]_inst_i_4_n_0 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized24
(\sgf_result_o[47] ,
Q_middle_temp__0,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\sgf_result_o[47]_10 ,
\sgf_result_o[47]_11 ,
\sgf_result_o[47]_12 ,
\sgf_result_o[47]_13 ,
DI,
S,
\Data_A_i[5] ,
\Data_A_i[1] ,
O,
\Data_A_i[6] ,
\Data_A_i[6]_0 ,
\Data_B_i[6] ,
\Data_A_i[6]_1 ,
\Data_B_i[6]_0 ,
\Data_A_i[5]_0 ,
\Data_A_i[11] ,
\Data_A_i[5]_1 ,
\Data_A_i[2] ,
\Data_A_i[8] ,
\Data_A_i[2]_0 ,
\Data_A_i[6]_2 ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[0] ,
\Data_B_i[3] ,
\Data_B_i[1] ,
\Data_B_i[4] ,
\Data_A_i[2]_1 ,
\Data_A_i[5]_2 ,
\Data_A_i[2]_2 ,
\Data_A_i[5]_3 ,
\Data_A_i[5]_4 ,
\Data_A_i[2]_3 ,
\Data_A_i[5]_5 ,
\Data_A_i[5]_6 ,
\Data_A_i[2]_4 ,
\Data_A_i[2]_5 ,
\Data_B_i[4]_0 ,
\Data_A_i[11]_0 ,
\Data_A_i[11]_1 );
output [2:0]\sgf_result_o[47] ;
output [10:0]Q_middle_temp__0;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [1:0]\sgf_result_o[47]_3 ;
output [2:0]\sgf_result_o[47]_4 ;
output [3:0]\sgf_result_o[47]_5 ;
output [3:0]\sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
output [1:0]\sgf_result_o[47]_9 ;
output [2:0]\sgf_result_o[47]_10 ;
output [3:0]\sgf_result_o[47]_11 ;
output [3:0]\sgf_result_o[47]_12 ;
output [2:0]\sgf_result_o[47]_13 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_A_i[5] ;
input [2:0]\Data_A_i[1] ;
input [3:0]O;
input [3:0]\Data_A_i[6] ;
input [3:0]\Data_A_i[6]_0 ;
input [3:0]\Data_B_i[6] ;
input [0:0]\Data_A_i[6]_1 ;
input [2:0]\Data_B_i[6]_0 ;
input [2:0]\Data_A_i[5]_0 ;
input [3:0]\Data_A_i[11] ;
input [3:0]\Data_A_i[5]_1 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[8] ;
input [3:0]\Data_A_i[2]_0 ;
input [1:0]\Data_A_i[6]_2 ;
input [4:0]Data_B_i_IBUF;
input [4:0]Data_A_i_IBUF;
input \Data_B_i[0] ;
input \Data_B_i[3] ;
input \Data_B_i[1] ;
input \Data_B_i[4] ;
input \Data_A_i[2]_1 ;
input \Data_A_i[5]_2 ;
input \Data_A_i[2]_2 ;
input \Data_A_i[5]_3 ;
input \Data_A_i[5]_4 ;
input \Data_A_i[2]_3 ;
input [3:0]\Data_A_i[5]_5 ;
input [3:0]\Data_A_i[5]_6 ;
input [3:0]\Data_A_i[2]_4 ;
input [3:0]\Data_A_i[2]_5 ;
input [1:0]\Data_B_i[4]_0 ;
input [3:0]\Data_A_i[11]_0 ;
input [1:0]\Data_A_i[11]_1 ;
wire [2:0]DI;
wire [3:0]\Data_A_i[11] ;
wire [3:0]\Data_A_i[11]_0 ;
wire [1:0]\Data_A_i[11]_1 ;
wire [2:0]\Data_A_i[1] ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire \Data_A_i[2]_1 ;
wire \Data_A_i[2]_2 ;
wire \Data_A_i[2]_3 ;
wire [3:0]\Data_A_i[2]_4 ;
wire [3:0]\Data_A_i[2]_5 ;
wire [2:0]\Data_A_i[5] ;
wire [2:0]\Data_A_i[5]_0 ;
wire [3:0]\Data_A_i[5]_1 ;
wire \Data_A_i[5]_2 ;
wire \Data_A_i[5]_3 ;
wire \Data_A_i[5]_4 ;
wire [3:0]\Data_A_i[5]_5 ;
wire [3:0]\Data_A_i[5]_6 ;
wire [3:0]\Data_A_i[6] ;
wire [3:0]\Data_A_i[6]_0 ;
wire [0:0]\Data_A_i[6]_1 ;
wire [1:0]\Data_A_i[6]_2 ;
wire [3:0]\Data_A_i[8] ;
wire [4:0]Data_A_i_IBUF;
wire \Data_B_i[0] ;
wire \Data_B_i[1] ;
wire \Data_B_i[3] ;
wire \Data_B_i[4] ;
wire [1:0]\Data_B_i[4]_0 ;
wire [3:0]\Data_B_i[6] ;
wire [2:0]\Data_B_i[6]_0 ;
wire [4:0]Data_B_i_IBUF;
wire [3:0]O;
wire [10:0]Q_middle_temp__0;
wire [3:0]S;
wire S_B0__30_carry__0_i_10_n_0;
wire S_B0__30_carry__0_i_10_n_1;
wire S_B0__30_carry__0_i_10_n_2;
wire S_B0__30_carry__0_i_10_n_3;
wire S_B0__30_carry__0_n_0;
wire S_B0__30_carry__0_n_1;
wire S_B0__30_carry__0_n_2;
wire S_B0__30_carry__0_n_3;
wire S_B0__30_carry__1_i_10_n_3;
wire S_B0__30_carry__1_n_0;
wire S_B0__30_carry__1_n_1;
wire S_B0__30_carry__1_n_2;
wire S_B0__30_carry__1_n_3;
wire S_B0__30_carry__2_n_3;
wire S_B0__30_carry_n_0;
wire S_B0__30_carry_n_1;
wire S_B0__30_carry_n_2;
wire S_B0__30_carry_n_3;
wire S_B0_carry__0_n_0;
wire S_B0_carry__0_n_1;
wire S_B0_carry__0_n_2;
wire S_B0_carry__0_n_3;
wire S_B0_carry__1_n_2;
wire S_B0_carry__1_n_3;
wire S_B0_carry_n_0;
wire S_B0_carry_n_1;
wire S_B0_carry_n_2;
wire S_B0_carry_n_3;
wire sgf_result_o0__1_carry__0_n_1;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_4;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [2:0]\sgf_result_o[47]_10 ;
wire [3:0]\sgf_result_o[47]_11 ;
wire [3:0]\sgf_result_o[47]_12 ;
wire [2:0]\sgf_result_o[47]_13 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [1:0]\sgf_result_o[47]_3 ;
wire [2:0]\sgf_result_o[47]_4 ;
wire [3:0]\sgf_result_o[47]_5 ;
wire [3:0]\^sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [1:0]\sgf_result_o[47]_9 ;
wire \sgf_result_o_OBUF[4]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[4]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[4]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[4]_inst_i_1_n_3 ;
wire [3:1]NLW_S_B0__30_carry__1_i_10_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__1_i_10_O_UNCONNECTED;
wire [3:1]NLW_S_B0__30_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__2_O_UNCONNECTED;
wire [3:2]NLW_S_B0_carry__1_CO_UNCONNECTED;
wire [3:3]NLW_S_B0_carry__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
assign \sgf_result_o[47]_6 [3] = sgf_result_o0__1_carry__0_n_4;
assign \sgf_result_o[47]_6 [2:0] = \^sgf_result_o[47]_6 [2:0];
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'h2B))
S_B0__0_carry__0_i_1
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_A_i[5]_4 ),
.I2(\Data_A_i[2]_3 ),
.O(\sgf_result_o[47] [1]));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
S_B0__0_carry__0_i_2
(.I0(\Data_A_i[2]_2 ),
.I1(\Data_A_i[5]_3 ),
.I2(sgf_result_o0__1_carry_n_4),
.O(\sgf_result_o[47] [0]));
LUT4 #(
.INIT(16'h4DB2))
S_B0__0_carry__0_i_4
(.I0(\Data_B_i[1] ),
.I1(\Data_B_i[4] ),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\sgf_result_o[47] [2]),
.O(\^sgf_result_o[47]_6 [2]));
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry__0_i_5
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[1] ),
.I2(\Data_B_i[4] ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_6 [1]));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry__0_i_6
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_A_i[5]_4 ),
.I2(\Data_A_i[2]_3 ),
.I3(\sgf_result_o[47] [0]),
.O(\^sgf_result_o[47]_6 [0]));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry_i_1
(.I0(\Data_A_i[2]_1 ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[5]_2 ),
.O(\sgf_result_o[47]_4 [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__0_carry_i_2
(.I0(Data_B_i_IBUF[2]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[0] ),
.O(\sgf_result_o[47]_4 [1]));
(* HLUTNM = "lutpair78" *)
LUT5 #(
.INIT(32'h2ABFBFBF))
S_B0__0_carry_i_3
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_4 [0]));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_4
(.I0(\Data_A_i[2]_2 ),
.I1(\Data_A_i[5]_3 ),
.I2(sgf_result_o0__1_carry_n_4),
.I3(\sgf_result_o[47]_4 [2]),
.O(\sgf_result_o[47]_5 [3]));
(* HLUTNM = "lutpair0" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_5
(.I0(\Data_A_i[2]_1 ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[5]_2 ),
.I3(\sgf_result_o[47]_4 [1]),
.O(\sgf_result_o[47]_5 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_6
(.I0(\sgf_result_o[47]_4 [0]),
.I1(\Data_B_i[3] ),
.I2(\Data_B_i[0] ),
.I3(sgf_result_o0__1_carry_n_6),
.O(\sgf_result_o[47]_5 [1]));
(* HLUTNM = "lutpair78" *)
LUT5 #(
.INIT(32'h6A959595))
S_B0__0_carry_i_7
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_5 [0]));
CARRY4 S_B0__30_carry
(.CI(1'b0),
.CO({S_B0__30_carry_n_0,S_B0__30_carry_n_1,S_B0__30_carry_n_2,S_B0__30_carry_n_3}),
.CYINIT(1'b1),
.DI({\Data_A_i[5]_0 ,1'b1}),
.O(\sgf_result_o[47]_0 ),
.S(\Data_A_i[11] ));
CARRY4 S_B0__30_carry__0
(.CI(S_B0__30_carry_n_0),
.CO({S_B0__30_carry__0_n_0,S_B0__30_carry__0_n_1,S_B0__30_carry__0_n_2,S_B0__30_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Data_A_i[5]_1 ),
.O(\sgf_result_o[47]_1 ),
.S(\Data_A_i[2] ));
CARRY4 S_B0__30_carry__0_i_10
(.CI(\sgf_result_o_OBUF[4]_inst_i_1_n_0 ),
.CO({S_B0__30_carry__0_i_10_n_0,S_B0__30_carry__0_i_10_n_1,S_B0__30_carry__0_i_10_n_2,S_B0__30_carry__0_i_10_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[2]_4 [2:0],\Data_A_i[5]_5 [3]}),
.O(\sgf_result_o[47]_8 ),
.S(\Data_A_i[2]_5 ));
CARRY4 S_B0__30_carry__1
(.CI(S_B0__30_carry__0_n_0),
.CO({S_B0__30_carry__1_n_0,S_B0__30_carry__1_n_1,S_B0__30_carry__1_n_2,S_B0__30_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Data_A_i[8] ),
.O(\sgf_result_o[47]_2 ),
.S(\Data_A_i[2]_0 ));
CARRY4 S_B0__30_carry__1_i_10
(.CI(S_B0__30_carry__0_i_10_n_0),
.CO({NLW_S_B0__30_carry__1_i_10_CO_UNCONNECTED[3:1],S_B0__30_carry__1_i_10_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Data_A_i[2]_4 [3]}),
.O({NLW_S_B0__30_carry__1_i_10_O_UNCONNECTED[3:2],\sgf_result_o[47]_9 }),
.S({1'b0,1'b0,\Data_B_i[4]_0 }));
CARRY4 S_B0__30_carry__2
(.CI(S_B0__30_carry__1_n_0),
.CO({NLW_S_B0__30_carry__2_CO_UNCONNECTED[3:1],S_B0__30_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp__0[9]}),
.O({NLW_S_B0__30_carry__2_O_UNCONNECTED[3:2],\sgf_result_o[47]_3 }),
.S({1'b0,1'b0,\Data_A_i[6]_2 }));
CARRY4 S_B0_carry
(.CI(1'b0),
.CO({S_B0_carry_n_0,S_B0_carry_n_1,S_B0_carry_n_2,S_B0_carry_n_3}),
.CYINIT(1'b0),
.DI({O[2:0],1'b0}),
.O(Q_middle_temp__0[3:0]),
.S(\Data_A_i[6] ));
CARRY4 S_B0_carry__0
(.CI(S_B0_carry_n_0),
.CO({S_B0_carry__0_n_0,S_B0_carry__0_n_1,S_B0_carry__0_n_2,S_B0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[6]_0 [2:0],O[3]}),
.O(Q_middle_temp__0[7:4]),
.S(\Data_B_i[6] ));
CARRY4 S_B0_carry__1
(.CI(S_B0_carry__0_n_0),
.CO({NLW_S_B0_carry__1_CO_UNCONNECTED[3:2],S_B0_carry__1_n_2,S_B0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Data_A_i[6]_1 ,\Data_A_i[6]_0 [3]}),
.O({NLW_S_B0_carry__1_O_UNCONNECTED[3],Q_middle_temp__0[10:8]}),
.S({1'b0,\Data_B_i[6]_0 }));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_1,sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[5] }),
.O({sgf_result_o0__1_carry__0_n_4,\sgf_result_o[47] [2],sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[1] }));
LUT3 #(
.INIT(8'h6A))
\sgf_result_o_OBUF[10]_inst_i_2
(.I0(\sgf_result_o[47]_1 [2]),
.I1(Data_A_i_IBUF[3]),
.I2(Data_B_i_IBUF[3]),
.O(\sgf_result_o[47]_11 [3]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[10]_inst_i_3
(.I0(\sgf_result_o[47]_1 [1]),
.I1(\sgf_result_o[47]_9 [1]),
.O(\sgf_result_o[47]_11 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[10]_inst_i_4
(.I0(\sgf_result_o[47]_1 [0]),
.I1(\sgf_result_o[47]_9 [0]),
.O(\sgf_result_o[47]_11 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[10]_inst_i_5
(.I0(\sgf_result_o[47]_0 [3]),
.I1(\sgf_result_o[47]_8 [3]),
.O(\sgf_result_o[47]_11 [0]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_15
(.I0(\sgf_result_o[47]_2 [2]),
.I1(\Data_A_i[11]_0 [2]),
.O(\sgf_result_o[47]_12 [3]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_16
(.I0(\sgf_result_o[47]_2 [1]),
.I1(\Data_A_i[11]_0 [1]),
.O(\sgf_result_o[47]_12 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_17
(.I0(\sgf_result_o[47]_2 [0]),
.I1(\Data_A_i[11]_0 [0]),
.O(\sgf_result_o[47]_12 [1]));
LUT5 #(
.INIT(32'h956A6A6A))
\sgf_result_o_OBUF[18]_inst_i_18
(.I0(\sgf_result_o[47]_1 [3]),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[4]),
.O(\sgf_result_o[47]_12 [0]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_17
(.I0(\sgf_result_o[47]_3 [1]),
.I1(\Data_A_i[11]_1 [1]),
.O(\sgf_result_o[47]_13 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_18
(.I0(\sgf_result_o[47]_3 [0]),
.I1(\Data_A_i[11]_1 [0]),
.O(\sgf_result_o[47]_13 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_19
(.I0(\sgf_result_o[47]_2 [3]),
.I1(\Data_A_i[11]_0 [3]),
.O(\sgf_result_o[47]_13 [0]));
CARRY4 \sgf_result_o_OBUF[4]_inst_i_1
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[4]_inst_i_1_n_0 ,\sgf_result_o_OBUF[4]_inst_i_1_n_1 ,\sgf_result_o_OBUF[4]_inst_i_1_n_2 ,\sgf_result_o_OBUF[4]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[5]_5 [2:0],1'b0}),
.O(\sgf_result_o[47]_7 ),
.S(\Data_A_i[5]_6 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[8]_inst_i_2
(.I0(\sgf_result_o[47]_0 [2]),
.I1(\sgf_result_o[47]_8 [2]),
.O(\sgf_result_o[47]_10 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[8]_inst_i_3
(.I0(\sgf_result_o[47]_0 [1]),
.I1(\sgf_result_o[47]_8 [1]),
.O(\sgf_result_o[47]_10 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[8]_inst_i_4
(.I0(\sgf_result_o[47]_0 [0]),
.I1(\sgf_result_o[47]_8 [0]),
.O(\sgf_result_o[47]_10 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized25
(O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\sgf_result_o[47]_10 ,
\sgf_result_o[47]_11 ,
\sgf_result_o[47]_12 ,
\sgf_result_o[47]_13 ,
\sgf_result_o[47]_14 ,
DI,
S,
\Data_B_i[6] ,
\Data_A_i[6] ,
\Data_A_i[10] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[0] ,
\Data_A_i[6]_0 ,
\Data_A_i[6]_1 ,
CO,
\Data_B_i[6]_0 ,
\Data_B_i[6]_1 ,
\Data_B_i[6]_2 ,
\Data_B_i[6]_3 ,
\Data_A_i[6]_2 ,
\Data_B_i[6]_4 ,
\Data_B_i[6]_5 ,
\Data_A_i[6]_3 ,
\Data_A_i[6]_4 ,
\Data_A_i[6]_5 ,
\Data_A_i[11] ,
sgf_result_o_OBUF,
\Data_A_i[6]_6 ,
\Data_A_i[5] ,
\Data_A_i[11]_0 ,
\Data_A_i[5]_0 ,
\Data_A_i[5]_1 ,
\Data_A_i[2] ,
\Data_A_i[2]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[11]_1 ,
\Data_A_i[8] );
output [3:0]O;
output [3:0]\sgf_result_o[47] ;
output [0:0]\sgf_result_o[47]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output \sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output [2:0]\sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
output [3:0]\sgf_result_o[47]_9 ;
output [5:0]\sgf_result_o[47]_10 ;
output [1:0]\sgf_result_o[47]_11 ;
output [3:0]\sgf_result_o[47]_12 ;
output [3:0]\sgf_result_o[47]_13 ;
output [2:0]\sgf_result_o[47]_14 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[6] ;
input [2:0]\Data_A_i[6] ;
input [0:0]\Data_A_i[10] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[0] ;
input [3:0]\Data_A_i[6]_0 ;
input [1:0]\Data_A_i[6]_1 ;
input [0:0]CO;
input [3:0]\Data_B_i[6]_0 ;
input [1:0]\Data_B_i[6]_1 ;
input [0:0]\Data_B_i[6]_2 ;
input \Data_B_i[6]_3 ;
input \Data_A_i[6]_2 ;
input \Data_B_i[6]_4 ;
input \Data_B_i[6]_5 ;
input \Data_A_i[6]_3 ;
input \Data_A_i[6]_4 ;
input \Data_A_i[6]_5 ;
input [1:0]\Data_A_i[11] ;
input [1:0]sgf_result_o_OBUF;
input [0:0]\Data_A_i[6]_6 ;
input [3:0]\Data_A_i[5] ;
input [3:0]\Data_A_i[11]_0 ;
input [3:0]\Data_A_i[5]_0 ;
input [3:0]\Data_A_i[5]_1 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[2]_0 ;
input [1:0]\Data_A_i[2]_1 ;
input [3:0]\Data_A_i[11]_1 ;
input [2:0]\Data_A_i[8] ;
wire [0:0]CO;
wire [2:0]DI;
wire [0:0]\Data_A_i[10] ;
wire [1:0]\Data_A_i[11] ;
wire [3:0]\Data_A_i[11]_0 ;
wire [3:0]\Data_A_i[11]_1 ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire [1:0]\Data_A_i[2]_1 ;
wire [3:0]\Data_A_i[5] ;
wire [3:0]\Data_A_i[5]_0 ;
wire [3:0]\Data_A_i[5]_1 ;
wire [2:0]\Data_A_i[6] ;
wire [3:0]\Data_A_i[6]_0 ;
wire [1:0]\Data_A_i[6]_1 ;
wire \Data_A_i[6]_2 ;
wire \Data_A_i[6]_3 ;
wire \Data_A_i[6]_4 ;
wire \Data_A_i[6]_5 ;
wire [0:0]\Data_A_i[6]_6 ;
wire [2:0]\Data_A_i[8] ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[0] ;
wire [2:0]\Data_B_i[6] ;
wire [3:0]\Data_B_i[6]_0 ;
wire [1:0]\Data_B_i[6]_1 ;
wire [0:0]\Data_B_i[6]_2 ;
wire \Data_B_i[6]_3 ;
wire \Data_B_i[6]_4 ;
wire \Data_B_i[6]_5 ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire \ODD1.middle_n_0 ;
wire \ODD1.middle_n_1 ;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_15 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_2 ;
wire \ODD1.middle_n_20 ;
wire \ODD1.middle_n_21 ;
wire \ODD1.middle_n_3 ;
wire \ODD1.middle_n_4 ;
wire \ODD1.middle_n_5 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_9 ;
wire \ODD1.right_lower_n_0 ;
wire \ODD1.right_lower_n_10 ;
wire \ODD1.right_lower_n_11 ;
wire \ODD1.right_lower_n_12 ;
wire \ODD1.right_lower_n_13 ;
wire \ODD1.right_lower_n_14 ;
wire \ODD1.right_lower_n_15 ;
wire \ODD1.right_lower_n_16 ;
wire \ODD1.right_lower_n_17 ;
wire \ODD1.right_lower_n_18 ;
wire \ODD1.right_lower_n_4 ;
wire \ODD1.right_lower_n_5 ;
wire \ODD1.right_lower_n_6 ;
wire \ODD1.right_lower_n_7 ;
wire \ODD1.right_lower_n_8 ;
wire \ODD1.right_lower_n_9 ;
wire [9:2]Q_middle_temp;
wire [3:0]S;
wire sgf_result_o1__0_carry__0_i_6_n_0;
wire sgf_result_o1__0_carry__0_i_7_n_0;
wire sgf_result_o1__0_carry_i_10_n_0;
wire sgf_result_o1__0_carry_i_11_n_0;
wire sgf_result_o1__0_carry_i_14_n_0;
wire sgf_result_o1__0_carry_i_15_n_0;
wire sgf_result_o1__0_carry_i_16_n_0;
wire sgf_result_o1__0_carry_i_17_n_0;
wire sgf_result_o1__0_carry_i_19_n_0;
wire sgf_result_o1__0_carry_i_22__0_n_0;
wire sgf_result_o1__0_carry_i_8_n_0;
wire sgf_result_o1__0_carry_i_9_n_0;
wire sgf_result_o1__21_carry__0_n_0;
wire sgf_result_o1__21_carry__0_n_1;
wire sgf_result_o1__21_carry__0_n_2;
wire sgf_result_o1__21_carry__0_n_3;
wire sgf_result_o1__21_carry__1_i_1_n_0;
wire sgf_result_o1__21_carry__1_n_3;
wire sgf_result_o1__21_carry__1_n_6;
wire sgf_result_o1__21_carry_n_0;
wire sgf_result_o1__21_carry_n_1;
wire sgf_result_o1__21_carry_n_2;
wire sgf_result_o1__21_carry_n_3;
wire sgf_result_o1_carry__0_n_1;
wire sgf_result_o1_carry__0_n_2;
wire sgf_result_o1_carry__0_n_3;
wire sgf_result_o1_carry_n_0;
wire sgf_result_o1_carry_n_1;
wire sgf_result_o1_carry_n_2;
wire sgf_result_o1_carry_n_3;
wire [3:0]\sgf_result_o[47] ;
wire [0:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [5:0]\sgf_result_o[47]_10 ;
wire [1:0]\sgf_result_o[47]_11 ;
wire [3:0]\sgf_result_o[47]_12 ;
wire [3:0]\sgf_result_o[47]_13 ;
wire [2:0]\sgf_result_o[47]_14 ;
wire \sgf_result_o[47]_2 ;
wire \sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire [2:0]\sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [3:0]\sgf_result_o[47]_9 ;
wire [1:0]sgf_result_o_OBUF;
wire [3:1]NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized28 \ODD1.middle
(.CO(CO),
.\Data_A_i[10] (sgf_result_o1__0_carry_i_14_n_0),
.\Data_A_i[10]_0 (sgf_result_o1__0_carry__0_i_7_n_0),
.\Data_A_i[10]_1 (sgf_result_o1__0_carry_i_8_n_0),
.\Data_A_i[10]_2 (sgf_result_o1__0_carry_i_9_n_0),
.\Data_A_i[10]_3 (sgf_result_o1__0_carry_i_17_n_0),
.\Data_A_i[10]_4 (sgf_result_o1__0_carry_i_10_n_0),
.\Data_A_i[6] (\Data_A_i[6]_0 ),
.\Data_A_i[6]_0 (\Data_A_i[6]_1 ),
.\Data_A_i[6]_1 (Q_middle_temp[8:7]),
.\Data_B_i[10] (sgf_result_o1__0_carry_i_15_n_0),
.\Data_B_i[10]_0 (sgf_result_o1__0_carry_i_11_n_0),
.\Data_B_i[6] (\Data_B_i[6]_0 ),
.\Data_B_i[6]_0 (\Data_B_i[6]_1 ),
.\Data_B_i[6]_1 (sgf_result_o1__0_carry__0_i_6_n_0),
.\Data_B_i[6]_2 (\Data_B_i[6]_2 ),
.\Data_B_i[6]_3 (\ODD1.right_lower_n_0 ),
.\Data_B_i[6]_4 (sgf_result_o1__0_carry_i_16_n_0),
.O({\ODD1.middle_n_0 ,\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 }),
.S({\ODD1.middle_n_14 ,\ODD1.middle_n_15 ,\ODD1.middle_n_16 }),
.\sgf_result_o[47] ({\ODD1.middle_n_4 ,\ODD1.middle_n_5 }),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_1 (\ODD1.middle_n_7 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_3 (\ODD1.middle_n_9 ),
.\sgf_result_o[47]_4 (\ODD1.middle_n_10 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_6 (\ODD1.middle_n_12 ),
.\sgf_result_o[47]_7 (\ODD1.middle_n_13 ),
.\sgf_result_o[47]_8 ({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }),
.\sgf_result_o[47]_9 (\ODD1.middle_n_21 ));
Recursive_KOA__parameterized27 \ODD1.right_lower
(.DI(DI),
.\Data_A_i[11] (\Data_A_i[11] ),
.\Data_A_i[11]_0 (\Data_A_i[11]_0 ),
.\Data_A_i[11]_1 (\Data_A_i[11]_1 ),
.\Data_A_i[2] (\Data_A_i[2] ),
.\Data_A_i[2]_0 (\Data_A_i[2]_0 ),
.\Data_A_i[2]_1 (\Data_A_i[2]_1 ),
.\Data_A_i[5] (\Data_A_i[5] ),
.\Data_A_i[5]_0 (\Data_A_i[5]_0 ),
.\Data_A_i[5]_1 (\Data_A_i[5]_1 ),
.\Data_A_i[6] (\Data_A_i[6] ),
.\Data_A_i[6]_0 (\Data_A_i[6]_1 ),
.\Data_A_i[6]_1 (\Data_A_i[6]_2 ),
.\Data_A_i[6]_2 (\Data_A_i[6]_3 ),
.\Data_A_i[6]_3 (\Data_A_i[6]_4 ),
.\Data_A_i[6]_4 (\Data_A_i[6]_5 ),
.\Data_A_i[6]_5 (\Data_A_i[6]_6 ),
.\Data_A_i[6]_6 (\Data_A_i[6]_0 [0]),
.\Data_A_i[8] (\Data_A_i[8] ),
.Data_A_i_IBUF(Data_A_i_IBUF),
.\Data_B_i[0] (\Data_B_i[0] ),
.\Data_B_i[10] (sgf_result_o1__0_carry_i_11_n_0),
.\Data_B_i[6] (\Data_B_i[6] ),
.\Data_B_i[6]_0 (\Data_B_i[6]_1 ),
.\Data_B_i[6]_1 (\Data_B_i[6]_3 ),
.\Data_B_i[6]_2 (\Data_B_i[6]_5 ),
.\Data_B_i[6]_3 (\Data_B_i[6]_0 [0]),
.Data_B_i_IBUF(Data_B_i_IBUF),
.O(O),
.Q_middle_temp(Q_middle_temp[7:2]),
.S(S),
.\sgf_result_o[47] (\ODD1.right_lower_n_0 ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_1 ({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 }),
.\sgf_result_o[47]_10 (\sgf_result_o[47]_12 ),
.\sgf_result_o[47]_11 (\sgf_result_o[47]_13 ),
.\sgf_result_o[47]_12 (\sgf_result_o[47]_14 ),
.\sgf_result_o[47]_2 ({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.\sgf_result_o[47]_3 ({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }),
.\sgf_result_o[47]_4 ({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_7 ),
.\sgf_result_o[47]_6 (\sgf_result_o[47]_8 [0]),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_9 ),
.\sgf_result_o[47]_8 (\sgf_result_o[47]_10 ),
.\sgf_result_o[47]_9 (\sgf_result_o[47]_11 ),
.sgf_result_o_OBUF(sgf_result_o_OBUF));
LUT6 #(
.INIT(64'h9A956595956A6A6A))
S_B0_carry__0_i_1__0
(.I0(\sgf_result_o[47] [2]),
.I1(CO),
.I2(\Data_B_i[6]_1 [0]),
.I3(\Data_A_i[6]_1 [0]),
.I4(\Data_B_i[6]_2 ),
.I5(\Data_B_i[6]_4 ),
.O(\sgf_result_o[47]_8 [3]));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0_carry__0_i_2
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[6]_1 [0]),
.I2(\Data_A_i[6]_1 [1]),
.I3(\Data_A_i[6]_1 [0]),
.I4(\Data_B_i[6]_1 [1]),
.O(\sgf_result_o[47]_8 [2]));
LUT3 #(
.INIT(8'h6A))
S_B0_carry__0_i_3
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[6]_1 [0]),
.I2(\Data_B_i[6]_1 [0]),
.O(\sgf_result_o[47]_8 [1]));
LUT2 #(
.INIT(4'h6))
S_B0_carry__1_i_1
(.I0(sgf_result_o1__21_carry__1_n_6),
.I1(\Data_B_i[6]_3 ),
.O(\sgf_result_o[47]_6 [2]));
LUT2 #(
.INIT(4'h9))
S_B0_carry__1_i_2__0
(.I0(\sgf_result_o[47]_0 ),
.I1(\Data_A_i[6]_5 ),
.O(\sgf_result_o[47]_6 [1]));
LUT2 #(
.INIT(4'h9))
S_B0_carry__1_i_3
(.I0(\sgf_result_o[47] [3]),
.I1(\Data_A_i[6]_4 ),
.O(\sgf_result_o[47]_6 [0]));
LUT6 #(
.INIT(64'h0400464B04000B0B))
sgf_result_o1__0_carry__0_i_6
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\sgf_result_o[47]_2 ),
.I3(\sgf_result_o[47]_4 ),
.I4(\sgf_result_o[47]_3 ),
.I5(sgf_result_o1__0_carry_i_22__0_n_0),
.O(sgf_result_o1__0_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h0020000000330020))
sgf_result_o1__0_carry__0_i_7
(.I0(sgf_result_o1__0_carry_i_22__0_n_0),
.I1(\sgf_result_o[47]_3 ),
.I2(\sgf_result_o[47]_4 ),
.I3(\sgf_result_o[47]_2 ),
.I4(\ODD1.middle_n_7 ),
.I5(\ODD1.middle_n_9 ),
.O(sgf_result_o1__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6868688068808080))
sgf_result_o1__0_carry_i_10
(.I0(\Data_A_i[6]_0 [3]),
.I1(\ODD1.middle_n_10 ),
.I2(\Data_B_i[6]_0 [3]),
.I3(\Data_B_i[6]_0 [2]),
.I4(\ODD1.middle_n_13 ),
.I5(\Data_B_i[6]_2 ),
.O(sgf_result_o1__0_carry_i_10_n_0));
LUT6 #(
.INIT(64'h6060609F609F6060))
sgf_result_o1__0_carry_i_11
(.I0(\Data_A_i[6]_0 [0]),
.I1(\Data_A_i[6]_1 [0]),
.I2(\ODD1.middle_n_7 ),
.I3(\ODD1.middle_n_9 ),
.I4(\Data_B_i[6]_0 [0]),
.I5(\Data_B_i[6]_1 [0]),
.O(sgf_result_o1__0_carry_i_11_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_14
(.I0(\Data_A_i[6]_0 [3]),
.I1(\Data_A_i[6]_0 [2]),
.I2(\ODD1.middle_n_12 ),
.I3(CO),
.O(sgf_result_o1__0_carry_i_14_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_15
(.I0(\Data_B_i[6]_0 [3]),
.I1(\Data_B_i[6]_0 [2]),
.I2(\ODD1.middle_n_13 ),
.I3(\Data_B_i[6]_2 ),
.O(sgf_result_o1__0_carry_i_15_n_0));
LUT6 #(
.INIT(64'hBEFA7D72FEFA3236))
sgf_result_o1__0_carry_i_16
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\sgf_result_o[47]_2 ),
.I3(\sgf_result_o[47]_4 ),
.I4(\sgf_result_o[47]_3 ),
.I5(sgf_result_o1__0_carry_i_22__0_n_0),
.O(sgf_result_o1__0_carry_i_16_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o1__0_carry_i_17
(.I0(sgf_result_o1__0_carry_i_15_n_0),
.I1(sgf_result_o1__0_carry_i_14_n_0),
.O(sgf_result_o1__0_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'hA880))
sgf_result_o1__0_carry_i_19
(.I0(\Data_A_i[6]_0 [3]),
.I1(\Data_A_i[6]_0 [2]),
.I2(\ODD1.middle_n_12 ),
.I3(CO),
.O(sgf_result_o1__0_carry_i_19_n_0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_22__0
(.I0(\Data_B_i[6]_0 [0]),
.I1(\Data_B_i[6]_1 [0]),
.O(sgf_result_o1__0_carry_i_22__0_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1__0_carry_i_8
(.I0(\sgf_result_o[47]_5 ),
.I1(\sgf_result_o[47]_2 ),
.I2(\sgf_result_o[47]_4 ),
.I3(\sgf_result_o[47]_3 ),
.I4(\Data_B_i[6]_1 [0]),
.I5(\Data_B_i[6]_0 [0]),
.O(sgf_result_o1__0_carry_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'hE8000000))
sgf_result_o1__0_carry_i_9
(.I0(\Data_B_i[6]_2 ),
.I1(\ODD1.middle_n_13 ),
.I2(\Data_B_i[6]_0 [2]),
.I3(\Data_B_i[6]_0 [3]),
.I4(sgf_result_o1__0_carry_i_19_n_0),
.O(sgf_result_o1__0_carry_i_9_n_0));
CARRY4 sgf_result_o1__21_carry
(.CI(1'b0),
.CO({sgf_result_o1__21_carry_n_0,sgf_result_o1__21_carry_n_1,sgf_result_o1__21_carry_n_2,sgf_result_o1__21_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 ,1'b1}),
.O(O),
.S({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }));
CARRY4 sgf_result_o1__21_carry__0
(.CI(sgf_result_o1__21_carry_n_0),
.CO({sgf_result_o1__21_carry__0_n_0,sgf_result_o1__21_carry__0_n_1,sgf_result_o1__21_carry__0_n_2,sgf_result_o1__21_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.O(\sgf_result_o[47] ),
.S({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }));
CARRY4 sgf_result_o1__21_carry__1
(.CI(sgf_result_o1__21_carry__0_n_0),
.CO({NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED[3:1],sgf_result_o1__21_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp[8]}),
.O({NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED[3:2],sgf_result_o1__21_carry__1_n_6,\sgf_result_o[47]_0 }),
.S({1'b0,1'b0,sgf_result_o1__21_carry__1_i_1_n_0,\ODD1.middle_n_21 }));
LUT1 #(
.INIT(2'h1))
sgf_result_o1__21_carry__1_i_1
(.I0(Q_middle_temp[9]),
.O(sgf_result_o1__21_carry__1_i_1_n_0));
CARRY4 sgf_result_o1_carry
(.CI(1'b0),
.CO({sgf_result_o1_carry_n_0,sgf_result_o1_carry_n_1,sgf_result_o1_carry_n_2,sgf_result_o1_carry_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 ,1'b0}),
.O(Q_middle_temp[5:2]),
.S({\ODD1.middle_n_14 ,\ODD1.middle_n_15 ,\ODD1.middle_n_16 ,\Data_A_i[10] }));
CARRY4 sgf_result_o1_carry__0
(.CI(sgf_result_o1_carry_n_0),
.CO({NLW_sgf_result_o1_carry__0_CO_UNCONNECTED[3],sgf_result_o1_carry__0_n_1,sgf_result_o1_carry__0_n_2,sgf_result_o1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\ODD1.middle_n_4 ,\ODD1.middle_n_5 ,\ODD1.middle_n_0 }),
.O(Q_middle_temp[9:6]),
.S({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o1_carry_i_5
(.I0(\Data_B_i[6]_0 [1]),
.I1(\Data_B_i[6]_1 [1]),
.I2(\Data_B_i[6]_0 [0]),
.I3(\Data_B_i[6]_1 [0]),
.I4(\ODD1.middle_n_9 ),
.O(\sgf_result_o[47]_5 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized27
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\sgf_result_o[47]_10 ,
\sgf_result_o[47]_11 ,
\sgf_result_o[47]_12 ,
DI,
S,
\Data_B_i[6] ,
\Data_A_i[6] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[0] ,
\Data_B_i[10] ,
\Data_B_i[6]_0 ,
\Data_A_i[6]_0 ,
\Data_B_i[6]_1 ,
Q_middle_temp,
\Data_A_i[6]_1 ,
O,
\Data_B_i[6]_2 ,
\Data_A_i[6]_2 ,
\Data_A_i[6]_3 ,
\Data_A_i[6]_4 ,
\Data_A_i[11] ,
sgf_result_o_OBUF,
\Data_A_i[6]_5 ,
\Data_A_i[5] ,
\Data_A_i[11]_0 ,
\Data_A_i[5]_0 ,
\Data_A_i[5]_1 ,
\Data_A_i[2] ,
\Data_A_i[2]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[11]_1 ,
\Data_A_i[8] ,
\Data_B_i[6]_3 ,
\Data_A_i[6]_6 );
output [0:0]\sgf_result_o[47] ;
output [2:0]\sgf_result_o[47]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [3:0]\sgf_result_o[47]_5 ;
output [0:0]\sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [5:0]\sgf_result_o[47]_8 ;
output [1:0]\sgf_result_o[47]_9 ;
output [3:0]\sgf_result_o[47]_10 ;
output [3:0]\sgf_result_o[47]_11 ;
output [2:0]\sgf_result_o[47]_12 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[6] ;
input [2:0]\Data_A_i[6] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[0] ;
input \Data_B_i[10] ;
input [1:0]\Data_B_i[6]_0 ;
input [1:0]\Data_A_i[6]_0 ;
input \Data_B_i[6]_1 ;
input [5:0]Q_middle_temp;
input \Data_A_i[6]_1 ;
input [3:0]O;
input \Data_B_i[6]_2 ;
input \Data_A_i[6]_2 ;
input \Data_A_i[6]_3 ;
input \Data_A_i[6]_4 ;
input [1:0]\Data_A_i[11] ;
input [1:0]sgf_result_o_OBUF;
input [0:0]\Data_A_i[6]_5 ;
input [3:0]\Data_A_i[5] ;
input [3:0]\Data_A_i[11]_0 ;
input [3:0]\Data_A_i[5]_0 ;
input [3:0]\Data_A_i[5]_1 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[2]_0 ;
input [1:0]\Data_A_i[2]_1 ;
input [3:0]\Data_A_i[11]_1 ;
input [2:0]\Data_A_i[8] ;
input [0:0]\Data_B_i[6]_3 ;
input [0:0]\Data_A_i[6]_6 ;
wire [2:0]DI;
wire [1:0]\Data_A_i[11] ;
wire [3:0]\Data_A_i[11]_0 ;
wire [3:0]\Data_A_i[11]_1 ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire [1:0]\Data_A_i[2]_1 ;
wire [3:0]\Data_A_i[5] ;
wire [3:0]\Data_A_i[5]_0 ;
wire [3:0]\Data_A_i[5]_1 ;
wire [2:0]\Data_A_i[6] ;
wire [1:0]\Data_A_i[6]_0 ;
wire \Data_A_i[6]_1 ;
wire \Data_A_i[6]_2 ;
wire \Data_A_i[6]_3 ;
wire \Data_A_i[6]_4 ;
wire [0:0]\Data_A_i[6]_5 ;
wire [0:0]\Data_A_i[6]_6 ;
wire [2:0]\Data_A_i[8] ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[0] ;
wire \Data_B_i[10] ;
wire [2:0]\Data_B_i[6] ;
wire [1:0]\Data_B_i[6]_0 ;
wire \Data_B_i[6]_1 ;
wire \Data_B_i[6]_2 ;
wire [0:0]\Data_B_i[6]_3 ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire [5:0]Q_middle_temp;
wire [3:0]S;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [0:0]\sgf_result_o[47] ;
wire [2:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_10 ;
wire [3:0]\sgf_result_o[47]_11 ;
wire [2:0]\sgf_result_o[47]_12 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [3:0]\^sgf_result_o[47]_5 ;
wire [0:0]\sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [5:0]\sgf_result_o[47]_8 ;
wire [1:0]\sgf_result_o[47]_9 ;
wire [1:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[10]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[10]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[10]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[10]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[18]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_14_n_1 ;
wire \sgf_result_o_OBUF[18]_inst_i_14_n_2 ;
wire \sgf_result_o_OBUF[18]_inst_i_14_n_3 ;
wire \sgf_result_o_OBUF[22]_inst_i_15_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_15_n_1 ;
wire \sgf_result_o_OBUF[22]_inst_i_15_n_2 ;
wire \sgf_result_o_OBUF[22]_inst_i_15_n_3 ;
wire \sgf_result_o_OBUF[26]_inst_i_15_n_2 ;
wire \sgf_result_o_OBUF[26]_inst_i_15_n_3 ;
wire \sgf_result_o_OBUF[8]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[8]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[8]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[8]_inst_i_1_n_3 ;
wire [2:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
wire [3:2]\NLW_sgf_result_o_OBUF[26]_inst_i_15_CO_UNCONNECTED ;
wire [3:3]\NLW_sgf_result_o_OBUF[26]_inst_i_15_O_UNCONNECTED ;
assign \sgf_result_o[47]_5 [3:1] = \^sgf_result_o[47]_5 [3:1];
assign \sgf_result_o[47]_5 [0] = sgf_result_o0__1_carry_n_4;
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'h2B))
S_B0__30_carry_i_1
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[11] [0]),
.I2(sgf_result_o_OBUF[0]),
.O(\sgf_result_o[47]_0 [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__30_carry_i_2
(.I0(Data_B_i_IBUF[2]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[0] ),
.O(\sgf_result_o[47]_0 [1]));
(* HLUTNM = "lutpair81" *)
LUT5 #(
.INIT(32'h7FFF0777))
S_B0__30_carry_i_3
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_7),
.O(\sgf_result_o[47]_0 [0]));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_4
(.I0(\Data_A_i[6]_5 ),
.I1(\Data_A_i[11] [1]),
.I2(sgf_result_o_OBUF[1]),
.I3(\sgf_result_o[47]_0 [2]),
.O(\sgf_result_o[47]_7 [3]));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_5
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[11] [0]),
.I2(sgf_result_o_OBUF[0]),
.I3(\sgf_result_o[47]_0 [1]),
.O(\sgf_result_o[47]_7 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__30_carry_i_6
(.I0(\sgf_result_o[47]_0 [0]),
.I1(\Data_B_i[0] ),
.I2(\Data_B_i[6]_2 ),
.I3(sgf_result_o0__1_carry_n_6),
.O(\sgf_result_o[47]_7 [1]));
(* HLUTNM = "lutpair81" *)
LUT5 #(
.INIT(32'h78888777))
S_B0__30_carry_i_7
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_7),
.O(\sgf_result_o[47]_7 [0]));
LUT2 #(
.INIT(4'h6))
S_B0_carry__0_i_4
(.I0(O[3]),
.I1(\sgf_result_o[47] ),
.O(\sgf_result_o[47]_6 ));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_1
(.I0(O[2]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\^sgf_result_o[47]_5 [3]));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_2
(.I0(O[1]),
.I1(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_5 [2]));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_3
(.I0(O[0]),
.I1(sgf_result_o0__1_carry__0_n_7),
.O(\^sgf_result_o[47]_5 [1]));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({\sgf_result_o[47] ,NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_B_i[6] }),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[6] }));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__21_carry__0_i_1
(.I0(Q_middle_temp[4]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\sgf_result_o[47]_2 [3]));
LUT3 #(
.INIT(8'h4D))
sgf_result_o1__21_carry__0_i_2
(.I0(\Data_B_i[6]_1 ),
.I1(Q_middle_temp[3]),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(\sgf_result_o[47]_2 [2]));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hB2))
sgf_result_o1__21_carry__0_i_3
(.I0(\Data_A_i[6]_4 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(Q_middle_temp[2]),
.O(\sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hD4))
sgf_result_o1__21_carry__0_i_4
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[6]_3 ),
.I2(Q_middle_temp[1]),
.O(\sgf_result_o[47]_2 [0]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__21_carry__0_i_5
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(Q_middle_temp[4]),
.I2(\sgf_result_o[47] ),
.I3(Q_middle_temp[5]),
.O(\sgf_result_o[47]_4 [3]));
LUT5 #(
.INIT(32'h4DB2B24D))
sgf_result_o1__21_carry__0_i_6
(.I0(sgf_result_o0__1_carry__0_n_6),
.I1(Q_middle_temp[3]),
.I2(\Data_B_i[6]_1 ),
.I3(sgf_result_o0__1_carry__0_n_5),
.I4(Q_middle_temp[4]),
.O(\sgf_result_o[47]_4 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry__0_i_7
(.I0(\sgf_result_o[47]_2 [1]),
.I1(Q_middle_temp[3]),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\Data_B_i[6]_1 ),
.O(\sgf_result_o[47]_4 [1]));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__21_carry__0_i_8
(.I0(\Data_A_i[6]_4 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(Q_middle_temp[2]),
.I3(\sgf_result_o[47]_2 [0]),
.O(\sgf_result_o[47]_4 [0]));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__21_carry_i_1
(.I0(Q_middle_temp[0]),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[6]_2 ),
.O(\sgf_result_o[47]_1 [2]));
LUT6 #(
.INIT(64'hB2222BBB2BBB2BBB))
sgf_result_o1__21_carry_i_2
(.I0(\Data_B_i[10] ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[6]_0 [0]),
.I3(\Data_A_i[6]_0 [1]),
.I4(\Data_A_i[6]_0 [0]),
.I5(\Data_B_i[6]_0 [1]),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair80" *)
LUT5 #(
.INIT(32'h1747270F))
sgf_result_o1__21_carry_i_3
(.I0(\Data_A_i[6]_0 [0]),
.I1(\Data_B_i[6]_0 [0]),
.I2(sgf_result_o0__1_carry_n_7),
.I3(\Data_B_i[6]_3 ),
.I4(\Data_A_i[6]_6 ),
.O(\sgf_result_o[47]_1 [0]));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__21_carry_i_4
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[6]_3 ),
.I2(Q_middle_temp[1]),
.I3(\sgf_result_o[47]_1 [2]),
.O(\sgf_result_o[47]_3 [3]));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_5
(.I0(Q_middle_temp[0]),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[6]_2 ),
.I3(\sgf_result_o[47]_1 [1]),
.O(\sgf_result_o[47]_3 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_6
(.I0(\sgf_result_o[47]_1 [0]),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_A_i[6]_1 ),
.I3(\Data_B_i[10] ),
.O(\sgf_result_o[47]_3 [1]));
(* HLUTNM = "lutpair80" *)
LUT5 #(
.INIT(32'h96C3A50F))
sgf_result_o1__21_carry_i_7
(.I0(\Data_A_i[6]_0 [0]),
.I1(\Data_B_i[6]_0 [0]),
.I2(sgf_result_o0__1_carry_n_7),
.I3(\Data_B_i[6]_3 ),
.I4(\Data_A_i[6]_6 ),
.O(\sgf_result_o[47]_3 [0]));
CARRY4 \sgf_result_o_OBUF[10]_inst_i_1
(.CI(\sgf_result_o_OBUF[8]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[10]_inst_i_1_n_0 ,\sgf_result_o_OBUF[10]_inst_i_1_n_1 ,\sgf_result_o_OBUF[10]_inst_i_1_n_2 ,\sgf_result_o_OBUF[10]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[5]_0 [2:0],\Data_A_i[5] [3]}),
.O({\sgf_result_o[47]_9 ,\sgf_result_o[47]_8 [5:4]}),
.S(\Data_A_i[5]_1 ));
CARRY4 \sgf_result_o_OBUF[18]_inst_i_14
(.CI(\sgf_result_o_OBUF[10]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[18]_inst_i_14_n_0 ,\sgf_result_o_OBUF[18]_inst_i_14_n_1 ,\sgf_result_o_OBUF[18]_inst_i_14_n_2 ,\sgf_result_o_OBUF[18]_inst_i_14_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[2] [2:0],\Data_A_i[5]_0 [3]}),
.O(\sgf_result_o[47]_10 ),
.S(\Data_A_i[2]_0 ));
CARRY4 \sgf_result_o_OBUF[22]_inst_i_15
(.CI(\sgf_result_o_OBUF[18]_inst_i_14_n_0 ),
.CO({\sgf_result_o_OBUF[22]_inst_i_15_n_0 ,\sgf_result_o_OBUF[22]_inst_i_15_n_1 ,\sgf_result_o_OBUF[22]_inst_i_15_n_2 ,\sgf_result_o_OBUF[22]_inst_i_15_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[2]_1 ,\Data_A_i[2] [3]}),
.O(\sgf_result_o[47]_11 ),
.S(\Data_A_i[11]_1 ));
CARRY4 \sgf_result_o_OBUF[26]_inst_i_15
(.CI(\sgf_result_o_OBUF[22]_inst_i_15_n_0 ),
.CO({\NLW_sgf_result_o_OBUF[26]_inst_i_15_CO_UNCONNECTED [3:2],\sgf_result_o_OBUF[26]_inst_i_15_n_2 ,\sgf_result_o_OBUF[26]_inst_i_15_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_sgf_result_o_OBUF[26]_inst_i_15_O_UNCONNECTED [3],\sgf_result_o[47]_12 }),
.S({1'b0,\Data_A_i[8] }));
CARRY4 \sgf_result_o_OBUF[8]_inst_i_1
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[8]_inst_i_1_n_0 ,\sgf_result_o_OBUF[8]_inst_i_1_n_1 ,\sgf_result_o_OBUF[8]_inst_i_1_n_2 ,\sgf_result_o_OBUF[8]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\Data_A_i[5] [2:0],1'b0}),
.O(\sgf_result_o[47]_8 [3:0]),
.S(\Data_A_i[11]_0 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized28
(O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
S,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\Data_A_i[6] ,
\Data_A_i[6]_0 ,
CO,
\Data_B_i[6] ,
\Data_B_i[6]_0 ,
\Data_A_i[10] ,
\Data_B_i[10] ,
\Data_A_i[10]_0 ,
\Data_B_i[6]_1 ,
\Data_A_i[10]_1 ,
\Data_A_i[10]_2 ,
\Data_B_i[6]_2 ,
\Data_A_i[10]_3 ,
\Data_A_i[10]_4 ,
\Data_B_i[6]_3 ,
\Data_A_i[6]_1 ,
\Data_B_i[10]_0 ,
\Data_B_i[6]_4 );
output [3:0]O;
output [1:0]\sgf_result_o[47] ;
output \sgf_result_o[47]_0 ;
output \sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output \sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output \sgf_result_o[47]_6 ;
output \sgf_result_o[47]_7 ;
output [2:0]S;
output [3:0]\sgf_result_o[47]_8 ;
output [0:0]\sgf_result_o[47]_9 ;
input [3:0]\Data_A_i[6] ;
input [1:0]\Data_A_i[6]_0 ;
input [0:0]CO;
input [3:0]\Data_B_i[6] ;
input [1:0]\Data_B_i[6]_0 ;
input \Data_A_i[10] ;
input \Data_B_i[10] ;
input \Data_A_i[10]_0 ;
input \Data_B_i[6]_1 ;
input \Data_A_i[10]_1 ;
input \Data_A_i[10]_2 ;
input [0:0]\Data_B_i[6]_2 ;
input \Data_A_i[10]_3 ;
input \Data_A_i[10]_4 ;
input [0:0]\Data_B_i[6]_3 ;
input [1:0]\Data_A_i[6]_1 ;
input \Data_B_i[10]_0 ;
input \Data_B_i[6]_4 ;
wire [0:0]CO;
wire \Data_A_i[10] ;
wire \Data_A_i[10]_0 ;
wire \Data_A_i[10]_1 ;
wire \Data_A_i[10]_2 ;
wire \Data_A_i[10]_3 ;
wire \Data_A_i[10]_4 ;
wire [3:0]\Data_A_i[6] ;
wire [1:0]\Data_A_i[6]_0 ;
wire [1:0]\Data_A_i[6]_1 ;
wire \Data_B_i[10] ;
wire \Data_B_i[10]_0 ;
wire [3:0]\Data_B_i[6] ;
wire [1:0]\Data_B_i[6]_0 ;
wire \Data_B_i[6]_1 ;
wire [0:0]\Data_B_i[6]_2 ;
wire [0:0]\Data_B_i[6]_3 ;
wire \Data_B_i[6]_4 ;
wire [3:0]O;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_11 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_8 ;
wire \ODD1.middle_n_9 ;
wire [2:0]S;
wire sgf_result_o1__0_carry__0_n_2;
wire sgf_result_o1__0_carry__0_n_3;
wire sgf_result_o1__0_carry__0_n_5;
wire sgf_result_o1__0_carry_n_0;
wire sgf_result_o1__0_carry_n_1;
wire sgf_result_o1__0_carry_n_2;
wire sgf_result_o1__0_carry_n_3;
wire [1:0]\sgf_result_o[47] ;
wire \sgf_result_o[47]_0 ;
wire \sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_2 ;
wire \sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire \sgf_result_o[47]_6 ;
wire \sgf_result_o[47]_7 ;
wire [3:0]\^sgf_result_o[47]_8 ;
wire [0:0]\sgf_result_o[47]_9 ;
wire [3:2]NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED;
assign \sgf_result_o[47]_8 [3] = sgf_result_o1__0_carry__0_n_5;
assign \sgf_result_o[47]_8 [2:0] = \^sgf_result_o[47]_8 [2:0];
Recursive_KOA__parameterized31 \ODD1.middle
(.CO(CO),
.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 }),
.\Data_A_i[10] (\Data_A_i[10] ),
.\Data_A_i[10]_0 (\Data_A_i[10]_0 ),
.\Data_A_i[10]_1 (\Data_A_i[10]_1 ),
.\Data_A_i[10]_2 (\Data_A_i[10]_2 ),
.\Data_A_i[10]_3 (\Data_A_i[10]_4 ),
.\Data_A_i[10]_4 (\Data_A_i[10]_3 ),
.\Data_A_i[6] (\Data_A_i[6] ),
.\Data_A_i[6]_0 (\Data_A_i[6]_0 ),
.\Data_B_i[10] (\Data_B_i[10] ),
.\Data_B_i[10]_0 (\Data_B_i[10]_0 ),
.\Data_B_i[6] (\Data_B_i[6] ),
.\Data_B_i[6]_0 (\Data_B_i[6]_0 ),
.\Data_B_i[6]_1 (\Data_B_i[6]_1 ),
.\Data_B_i[6]_2 (\Data_B_i[6]_2 ),
.\Data_B_i[6]_3 (\Data_B_i[6]_4 ),
.S({\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }),
.\sgf_result_o[47] (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_5 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_6 ),
.\sgf_result_o[47]_6 ({\ODD1.middle_n_13 ,\ODD1.middle_n_14 }),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_7 ),
.\sgf_result_o[47]_8 ({\ODD1.middle_n_16 ,\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 }));
CARRY4 sgf_result_o1__0_carry
(.CI(1'b0),
.CO({sgf_result_o1__0_carry_n_0,sgf_result_o1__0_carry_n_1,sgf_result_o1__0_carry_n_2,sgf_result_o1__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 ,1'b1}),
.O(O),
.S({\ODD1.middle_n_16 ,\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 }));
CARRY4 sgf_result_o1__0_carry__0
(.CI(sgf_result_o1__0_carry_n_0),
.CO({NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED[3:2],sgf_result_o1__0_carry__0_n_2,sgf_result_o1__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\ODD1.middle_n_13 ,\ODD1.middle_n_14 }),
.O({NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED[3],sgf_result_o1__0_carry__0_n_5,\sgf_result_o[47] }),
.S({1'b0,\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }));
LUT3 #(
.INIT(8'h2D))
sgf_result_o1__21_carry__1_i_2
(.I0(\Data_B_i[6]_3 ),
.I1(\Data_A_i[6]_1 [0]),
.I2(\Data_A_i[6]_1 [1]),
.O(\sgf_result_o[47]_9 ));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_2
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_A_i[10]_2 ),
.O(\^sgf_result_o[47]_8 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_3
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[10]_4 ),
.O(\^sgf_result_o[47]_8 [1]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_4
(.I0(O[3]),
.I1(\Data_A_i[10]_3 ),
.O(\^sgf_result_o[47]_8 [0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_1
(.I0(O[2]),
.I1(\Data_A_i[10]_0 ),
.O(S[2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_2
(.I0(O[1]),
.I1(\Data_B_i[6]_1 ),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
sgf_result_o1_carry_i_3__0
(.I0(O[0]),
.I1(\Data_B_i[6]_4 ),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized31
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
DI,
S,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\Data_A_i[6] ,
\Data_A_i[6]_0 ,
CO,
\Data_B_i[6] ,
\Data_B_i[6]_0 ,
\Data_A_i[10] ,
\Data_B_i[10] ,
\Data_A_i[10]_0 ,
\Data_B_i[6]_1 ,
\Data_A_i[10]_1 ,
\Data_A_i[10]_2 ,
\Data_B_i[6]_2 ,
\Data_A_i[10]_3 ,
\Data_B_i[10]_0 ,
\Data_B_i[6]_3 ,
\Data_A_i[10]_4 );
output \sgf_result_o[47] ;
output \sgf_result_o[47]_0 ;
output \sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output \sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output [2:0]DI;
output [2:0]S;
output [1:0]\sgf_result_o[47]_6 ;
output \sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
input [3:0]\Data_A_i[6] ;
input [1:0]\Data_A_i[6]_0 ;
input [0:0]CO;
input [3:0]\Data_B_i[6] ;
input [1:0]\Data_B_i[6]_0 ;
input \Data_A_i[10] ;
input \Data_B_i[10] ;
input \Data_A_i[10]_0 ;
input \Data_B_i[6]_1 ;
input \Data_A_i[10]_1 ;
input \Data_A_i[10]_2 ;
input [0:0]\Data_B_i[6]_2 ;
input \Data_A_i[10]_3 ;
input \Data_B_i[10]_0 ;
input \Data_B_i[6]_3 ;
input \Data_A_i[10]_4 ;
wire [0:0]CO;
wire [2:0]DI;
wire \Data_A_i[10] ;
wire \Data_A_i[10]_0 ;
wire \Data_A_i[10]_1 ;
wire \Data_A_i[10]_2 ;
wire \Data_A_i[10]_3 ;
wire \Data_A_i[10]_4 ;
wire [3:0]\Data_A_i[6] ;
wire [1:0]\Data_A_i[6]_0 ;
wire \Data_B_i[10] ;
wire \Data_B_i[10]_0 ;
wire [3:0]\Data_B_i[6] ;
wire [1:0]\Data_B_i[6]_0 ;
wire \Data_B_i[6]_1 ;
wire [0:0]\Data_B_i[6]_2 ;
wire \Data_B_i[6]_3 ;
wire [2:0]S;
wire sgf_result_o0__1_carry__0_i_1__2_n_0;
wire sgf_result_o0__1_carry__0_i_2__11_n_0;
wire sgf_result_o0__1_carry__0_i_3_n_0;
wire sgf_result_o0__1_carry__0_i_4__2_n_0;
wire sgf_result_o0__1_carry__0_i_7__8_n_0;
wire sgf_result_o0__1_carry__0_i_8__11_n_0;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_i_12__2_n_0;
wire sgf_result_o0__1_carry_i_13__8_n_0;
wire sgf_result_o0__1_carry_i_14__4_n_0;
wire sgf_result_o0__1_carry_i_15__0_n_0;
wire sgf_result_o0__1_carry_i_16__0_n_0;
wire sgf_result_o0__1_carry_i_17__0_n_0;
wire sgf_result_o0__1_carry_i_1__2_n_0;
wire sgf_result_o0__1_carry_i_21__0_n_0;
wire sgf_result_o0__1_carry_i_2__2_n_0;
wire sgf_result_o0__1_carry_i_3__2_n_0;
wire sgf_result_o0__1_carry_i_4__2_n_0;
wire sgf_result_o0__1_carry_i_5__2_n_0;
wire sgf_result_o0__1_carry_i_6__10_n_0;
wire sgf_result_o0__1_carry_i_7__2_n_0;
wire sgf_result_o0__1_carry_i_8__1_n_0;
wire sgf_result_o0__1_carry_i_9_n_0;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire \sgf_result_o[47] ;
wire \sgf_result_o[47]_0 ;
wire \sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_2 ;
wire \sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire [1:0]\sgf_result_o[47]_6 ;
wire \sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [3:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o0__1_carry_i_1__2_n_0,sgf_result_o0__1_carry_i_2__2_n_0,sgf_result_o0__1_carry_i_3__2_n_0,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S({sgf_result_o0__1_carry_i_4__2_n_0,sgf_result_o0__1_carry_i_5__2_n_0,sgf_result_o0__1_carry_i_6__10_n_0,sgf_result_o0__1_carry_i_7__2_n_0}));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3:2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sgf_result_o0__1_carry__0_i_1__2_n_0}),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b0,sgf_result_o0__1_carry__0_i_2__11_n_0,sgf_result_o0__1_carry__0_i_3_n_0,sgf_result_o0__1_carry__0_i_4__2_n_0}));
LUT6 #(
.INIT(64'h00651075107565C3))
sgf_result_o0__1_carry__0_i_1__2
(.I0(\sgf_result_o[47] ),
.I1(sgf_result_o0__1_carry_i_12__2_n_0),
.I2(\sgf_result_o[47]_0 ),
.I3(\sgf_result_o[47]_1 ),
.I4(\sgf_result_o[47]_2 ),
.I5(sgf_result_o0__1_carry__0_i_7__8_n_0),
.O(sgf_result_o0__1_carry__0_i_1__2_n_0));
LUT3 #(
.INIT(8'h01))
sgf_result_o0__1_carry__0_i_2__11
(.I0(sgf_result_o0__1_carry__0_i_8__11_n_0),
.I1(\sgf_result_o[47] ),
.I2(sgf_result_o0__1_carry_i_17__0_n_0),
.O(sgf_result_o0__1_carry__0_i_2__11_n_0));
LUT4 #(
.INIT(16'h0553))
sgf_result_o0__1_carry__0_i_3
(.I0(sgf_result_o0__1_carry_i_17__0_n_0),
.I1(sgf_result_o0__1_carry_i_8__1_n_0),
.I2(sgf_result_o0__1_carry__0_i_8__11_n_0),
.I3(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h040404490B4646B9))
sgf_result_o0__1_carry__0_i_4__2
(.I0(sgf_result_o0__1_carry_i_12__2_n_0),
.I1(\sgf_result_o[47]_0 ),
.I2(\sgf_result_o[47]_1 ),
.I3(\sgf_result_o[47]_2 ),
.I4(sgf_result_o0__1_carry__0_i_7__8_n_0),
.I5(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry__0_i_4__2_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry__0_i_5
(.I0(\Data_A_i[6] [0]),
.I1(\Data_A_i[6]_0 [0]),
.I2(\Data_A_i[6] [1]),
.I3(\Data_A_i[6]_0 [1]),
.I4(CO),
.I5(\Data_A_i[6] [2]),
.O(\sgf_result_o[47]_1 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry__0_i_6__10
(.I0(\Data_A_i[6]_0 [0]),
.I1(\Data_A_i[6] [0]),
.I2(\Data_A_i[6]_0 [1]),
.I3(\Data_A_i[6] [1]),
.O(\sgf_result_o[47]_2 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry__0_i_7__8
(.I0(\Data_A_i[6] [0]),
.I1(\Data_A_i[6]_0 [0]),
.I2(\Data_A_i[6] [3]),
.I3(\Data_A_i[6] [2]),
.I4(\sgf_result_o[47]_5 ),
.I5(CO),
.O(sgf_result_o0__1_carry__0_i_7__8_n_0));
LUT6 #(
.INIT(64'h7FF7F11FF11FF77F))
sgf_result_o0__1_carry__0_i_8__11
(.I0(sgf_result_o0__1_carry_i_21__0_n_0),
.I1(\Data_B_i[6] [3]),
.I2(\Data_B_i[6] [1]),
.I3(\Data_B_i[6]_0 [1]),
.I4(\Data_B_i[6] [0]),
.I5(\Data_B_i[6]_0 [0]),
.O(sgf_result_o0__1_carry__0_i_8__11_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry_i_10__0
(.I0(\Data_B_i[6] [0]),
.I1(\Data_B_i[6]_0 [0]),
.I2(\Data_B_i[6] [1]),
.I3(\Data_B_i[6]_0 [1]),
.I4(\Data_B_i[6]_2 ),
.I5(\Data_B_i[6] [2]),
.O(\sgf_result_o[47] ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h8778))
sgf_result_o0__1_carry_i_11__2
(.I0(\Data_B_i[6]_0 [0]),
.I1(\Data_B_i[6] [0]),
.I2(\Data_B_i[6]_0 [1]),
.I3(\Data_B_i[6] [1]),
.O(\sgf_result_o[47]_0 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry_i_12__2
(.I0(\Data_B_i[6] [0]),
.I1(\Data_B_i[6]_0 [0]),
.I2(\Data_B_i[6] [3]),
.I3(\Data_B_i[6] [2]),
.I4(\sgf_result_o[47]_7 ),
.I5(\Data_B_i[6]_2 ),
.O(sgf_result_o0__1_carry_i_12__2_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_13__8
(.I0(CO),
.I1(\sgf_result_o[47]_5 ),
.I2(\Data_A_i[6] [2]),
.I3(\Data_A_i[6] [3]),
.I4(\Data_A_i[6]_0 [0]),
.I5(\Data_A_i[6] [0]),
.O(sgf_result_o0__1_carry_i_13__8_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_14__4
(.I0(\Data_B_i[6]_2 ),
.I1(\sgf_result_o[47]_7 ),
.I2(\Data_B_i[6] [2]),
.I3(\Data_B_i[6] [3]),
.I4(\Data_B_i[6]_0 [0]),
.I5(\Data_B_i[6] [0]),
.O(sgf_result_o0__1_carry_i_14__4_n_0));
LUT3 #(
.INIT(8'h28))
sgf_result_o0__1_carry_i_15__0
(.I0(sgf_result_o0__1_carry_i_9_n_0),
.I1(\sgf_result_o[47] ),
.I2(sgf_result_o0__1_carry__0_i_8__11_n_0),
.O(sgf_result_o0__1_carry_i_15__0_n_0));
LUT6 #(
.INIT(64'h9666666966696999))
sgf_result_o0__1_carry_i_16__0
(.I0(\Data_B_i[6] [1]),
.I1(\Data_B_i[6]_0 [1]),
.I2(sgf_result_o0__1_carry_i_21__0_n_0),
.I3(\Data_B_i[6] [3]),
.I4(\Data_B_i[6]_0 [0]),
.I5(\Data_B_i[6] [0]),
.O(sgf_result_o0__1_carry_i_16__0_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF1FF7F77F))
sgf_result_o0__1_carry_i_17__0
(.I0(\sgf_result_o[47]_4 ),
.I1(\Data_A_i[6] [3]),
.I2(\Data_A_i[6] [2]),
.I3(\sgf_result_o[47]_5 ),
.I4(CO),
.I5(\sgf_result_o[47]_2 ),
.O(sgf_result_o0__1_carry_i_17__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_18__1
(.I0(\Data_A_i[6]_0 [1]),
.I1(\Data_A_i[6] [1]),
.I2(\Data_A_i[6]_0 [0]),
.I3(\Data_A_i[6] [0]),
.O(\sgf_result_o[47]_5 ));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_19__1
(.I0(CO),
.I1(\Data_A_i[6]_0 [1]),
.I2(\Data_A_i[6] [1]),
.I3(\Data_A_i[6]_0 [0]),
.I4(\Data_A_i[6] [0]),
.I5(\Data_A_i[6] [2]),
.O(\sgf_result_o[47]_3 ));
LUT6 #(
.INIT(64'h590CC059590CCF59))
sgf_result_o0__1_carry_i_1__2
(.I0(sgf_result_o0__1_carry_i_8__1_n_0),
.I1(sgf_result_o0__1_carry_i_9_n_0),
.I2(\sgf_result_o[47] ),
.I3(\sgf_result_o[47]_0 ),
.I4(sgf_result_o0__1_carry_i_12__2_n_0),
.I5(sgf_result_o0__1_carry_i_13__8_n_0),
.O(sgf_result_o0__1_carry_i_1__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_20__0
(.I0(\Data_B_i[6]_0 [1]),
.I1(\Data_B_i[6] [1]),
.I2(\Data_B_i[6]_0 [0]),
.I3(\Data_B_i[6] [0]),
.O(\sgf_result_o[47]_7 ));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_21__0
(.I0(\Data_B_i[6]_2 ),
.I1(\Data_B_i[6]_0 [1]),
.I2(\Data_B_i[6] [1]),
.I3(\Data_B_i[6]_0 [0]),
.I4(\Data_B_i[6] [0]),
.I5(\Data_B_i[6] [2]),
.O(sgf_result_o0__1_carry_i_21__0_n_0));
LUT5 #(
.INIT(32'hA30A9039))
sgf_result_o0__1_carry_i_2__2
(.I0(sgf_result_o0__1_carry_i_9_n_0),
.I1(sgf_result_o0__1_carry_i_13__8_n_0),
.I2(sgf_result_o0__1_carry_i_12__2_n_0),
.I3(\sgf_result_o[47]_0 ),
.I4(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry_i_2__2_n_0));
LUT2 #(
.INIT(4'h2))
sgf_result_o0__1_carry_i_3__2
(.I0(sgf_result_o0__1_carry_i_9_n_0),
.I1(sgf_result_o0__1_carry_i_14__4_n_0),
.O(sgf_result_o0__1_carry_i_3__2_n_0));
LUT6 #(
.INIT(64'hAAA6AAA6AAA65555))
sgf_result_o0__1_carry_i_4__2
(.I0(sgf_result_o0__1_carry_i_1__2_n_0),
.I1(sgf_result_o0__1_carry_i_15__0_n_0),
.I2(sgf_result_o0__1_carry_i_13__8_n_0),
.I3(sgf_result_o0__1_carry_i_16__0_n_0),
.I4(sgf_result_o0__1_carry_i_17__0_n_0),
.I5(sgf_result_o0__1_carry_i_14__4_n_0),
.O(sgf_result_o0__1_carry_i_4__2_n_0));
LUT3 #(
.INIT(8'hA9))
sgf_result_o0__1_carry_i_5__2
(.I0(sgf_result_o0__1_carry_i_2__2_n_0),
.I1(sgf_result_o0__1_carry_i_14__4_n_0),
.I2(sgf_result_o0__1_carry_i_8__1_n_0),
.O(sgf_result_o0__1_carry_i_5__2_n_0));
LUT4 #(
.INIT(16'h444B))
sgf_result_o0__1_carry_i_6__10
(.I0(sgf_result_o0__1_carry_i_14__4_n_0),
.I1(sgf_result_o0__1_carry_i_9_n_0),
.I2(sgf_result_o0__1_carry_i_13__8_n_0),
.I3(sgf_result_o0__1_carry_i_16__0_n_0),
.O(sgf_result_o0__1_carry_i_6__10_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry_i_7__2
(.I0(sgf_result_o0__1_carry_i_13__8_n_0),
.I1(sgf_result_o0__1_carry_i_14__4_n_0),
.O(sgf_result_o0__1_carry_i_7__2_n_0));
LUT6 #(
.INIT(64'h0EF1F108F10808F7))
sgf_result_o0__1_carry_i_8__1
(.I0(\sgf_result_o[47]_4 ),
.I1(\Data_A_i[6] [3]),
.I2(\sgf_result_o[47]_2 ),
.I3(\Data_A_i[6] [2]),
.I4(CO),
.I5(\sgf_result_o[47]_5 ),
.O(sgf_result_o0__1_carry_i_8__1_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
sgf_result_o0__1_carry_i_9
(.I0(\Data_A_i[6] [1]),
.I1(\Data_A_i[6]_0 [1]),
.I2(\sgf_result_o[47]_3 ),
.I3(\Data_A_i[6] [3]),
.I4(\Data_A_i[6]_0 [0]),
.I5(\Data_A_i[6] [0]),
.O(sgf_result_o0__1_carry_i_9_n_0));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__0_carry__0_i_1
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_B_i[6]_1 ),
.O(\sgf_result_o[47]_6 [1]));
(* HLUTNM = "lutpair7" *)
LUT2 #(
.INIT(4'hE))
sgf_result_o1__0_carry__0_i_2
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[6]_3 ),
.O(\sgf_result_o[47]_6 [0]));
LUT3 #(
.INIT(8'h59))
sgf_result_o1__0_carry__0_i_3
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(\Data_A_i[10]_0 ),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(S[2]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__0_carry__0_i_4
(.I0(\Data_B_i[6]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[10]_0 ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(S[1]));
LUT3 #(
.INIT(8'h96))
sgf_result_o1__0_carry__0_i_5
(.I0(\sgf_result_o[47]_6 [0]),
.I1(\Data_B_i[6]_1 ),
.I2(sgf_result_o0__1_carry__0_n_7),
.O(S[0]));
LUT3 #(
.INIT(8'h71))
sgf_result_o1__0_carry_i_1
(.I0(\Data_A_i[10]_1 ),
.I1(\Data_A_i[10]_2 ),
.I2(sgf_result_o0__1_carry_n_5),
.O(DI[2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_12
(.I0(\Data_A_i[6] [0]),
.I1(\Data_A_i[6]_0 [0]),
.O(\sgf_result_o[47]_4 ));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'h71))
sgf_result_o1__0_carry_i_2
(.I0(\Data_A_i[10]_3 ),
.I1(\Data_B_i[10]_0 ),
.I2(sgf_result_o0__1_carry_n_6),
.O(DI[1]));
LUT6 #(
.INIT(64'hA22AFBBFFBBFFBBF))
sgf_result_o1__0_carry_i_3
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\sgf_result_o[47]_4 ),
.I2(\Data_B_i[6] [0]),
.I3(\Data_B_i[6]_0 [0]),
.I4(\Data_A_i[10] ),
.I5(\Data_B_i[10] ),
.O(DI[0]));
(* HLUTNM = "lutpair7" *)
LUT5 #(
.INIT(32'h99696966))
sgf_result_o1__0_carry_i_4
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[6]_3 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[10]_2 ),
.I4(\Data_A_i[10]_1 ),
.O(\sgf_result_o[47]_8 [3]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_5
(.I0(DI[1]),
.I1(\Data_A_i[10]_1 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[10]_2 ),
.O(\sgf_result_o[47]_8 [2]));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_6
(.I0(\Data_A_i[10]_3 ),
.I1(\Data_B_i[10]_0 ),
.I2(sgf_result_o0__1_carry_n_6),
.I3(DI[0]),
.O(\sgf_result_o[47]_8 [1]));
LUT6 #(
.INIT(64'h9999966996699999))
sgf_result_o1__0_carry_i_7
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[10]_4 ),
.I2(\Data_B_i[6]_0 [0]),
.I3(\Data_B_i[6] [0]),
.I4(\Data_A_i[6]_0 [0]),
.I5(\Data_A_i[6] [0]),
.O(\sgf_result_o[47]_8 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized32
(O,
\sgf_result_o[15] ,
\sgf_result_o[47] ,
\sgf_result_o[15]_0 ,
CO,
\sgf_result_o[15]_1 ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12] ,
sgf_result_o_OBUF,
\Data_A_i[17] ,
\Data_A_i[23] ,
S,
\Data_A_i[12] ,
\Data_A_i[12]_0 ,
DI,
\Data_B_i[17] ,
\Data_A_i[14] ,
\Data_A_i[14]_0 ,
\Data_A_i[13] ,
\Data_A_i[13]_0 ,
\Data_A_i[13]_1 ,
\Data_A_i[13]_2 ,
\Data_A_i[13]_3 ,
\Data_A_i[13]_4 ,
\Data_A_i[14]_1 ,
\Data_A_i[11] ,
\Data_A_i[14]_2 ,
\Data_A_i[14]_3 ,
\Data_A_i[14]_4 ,
\Data_A_i[14]_5 ,
\Data_A_i[11]_0 ,
\Data_A_i[2] ,
\Data_A_i[2]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[23]_0 ,
\Data_A_i[14]_6 );
output [0:0]O;
output [3:0]\sgf_result_o[15] ;
output [0:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[15]_0 ;
output [0:0]CO;
output [0:0]\sgf_result_o[15]_1 ;
output [1:0]\sgf_result_o[47]_0 ;
output [18:0]\sgf_result_o[47]_1 ;
output [0:0]\sgf_result_o[47]_2 ;
output [36:0]\sgf_result_o[47]_3 ;
input [23:0]Data_B_i_IBUF;
input [23:0]Data_A_i_IBUF;
input \Data_B_i[12] ;
input [5:0]sgf_result_o_OBUF;
input [2:0]\Data_A_i[17] ;
input [3:0]\Data_A_i[23] ;
input [0:0]S;
input [0:0]\Data_A_i[12] ;
input [2:0]\Data_A_i[12]_0 ;
input [0:0]DI;
input [0:0]\Data_B_i[17] ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[14]_0 ;
input [3:0]\Data_A_i[13] ;
input [3:0]\Data_A_i[13]_0 ;
input [3:0]\Data_A_i[13]_1 ;
input [3:0]\Data_A_i[13]_2 ;
input [3:0]\Data_A_i[13]_3 ;
input [3:0]\Data_A_i[13]_4 ;
input [0:0]\Data_A_i[14]_1 ;
input [0:0]\Data_A_i[11] ;
input [0:0]\Data_A_i[14]_2 ;
input [3:0]\Data_A_i[14]_3 ;
input [3:0]\Data_A_i[14]_4 ;
input [0:0]\Data_A_i[14]_5 ;
input [0:0]\Data_A_i[11]_0 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[2]_0 ;
input [2:0]\Data_A_i[2]_1 ;
input [3:0]\Data_A_i[23]_0 ;
input [0:0]\Data_A_i[14]_6 ;
wire [0:0]CO;
wire [0:0]DI;
wire [0:0]\Data_A_i[11] ;
wire [0:0]\Data_A_i[11]_0 ;
wire [0:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire [3:0]\Data_A_i[13] ;
wire [3:0]\Data_A_i[13]_0 ;
wire [3:0]\Data_A_i[13]_1 ;
wire [3:0]\Data_A_i[13]_2 ;
wire [3:0]\Data_A_i[13]_3 ;
wire [3:0]\Data_A_i[13]_4 ;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [0:0]\Data_A_i[14]_1 ;
wire [0:0]\Data_A_i[14]_2 ;
wire [3:0]\Data_A_i[14]_3 ;
wire [3:0]\Data_A_i[14]_4 ;
wire [0:0]\Data_A_i[14]_5 ;
wire [0:0]\Data_A_i[14]_6 ;
wire [2:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire [2:0]\Data_A_i[2]_1 ;
wire [23:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire [0:0]\Data_B_i[17] ;
wire [23:0]Data_B_i_IBUF;
wire [0:0]O;
wire \ODD1.left_high_n_1 ;
wire \ODD1.left_high_n_10 ;
wire \ODD1.left_high_n_11 ;
wire \ODD1.left_high_n_16 ;
wire \ODD1.left_high_n_17 ;
wire \ODD1.left_high_n_18 ;
wire \ODD1.left_high_n_19 ;
wire \ODD1.left_high_n_2 ;
wire \ODD1.left_high_n_20 ;
wire \ODD1.left_high_n_21 ;
wire \ODD1.left_high_n_22 ;
wire \ODD1.left_high_n_23 ;
wire \ODD1.left_high_n_24 ;
wire \ODD1.left_high_n_25 ;
wire \ODD1.left_high_n_26 ;
wire \ODD1.left_high_n_27 ;
wire \ODD1.left_high_n_28 ;
wire \ODD1.left_high_n_29 ;
wire \ODD1.left_high_n_3 ;
wire \ODD1.left_high_n_30 ;
wire \ODD1.left_high_n_32 ;
wire \ODD1.left_high_n_33 ;
wire \ODD1.left_high_n_34 ;
wire \ODD1.left_high_n_9 ;
wire \ODD1.middle_n_0 ;
wire \ODD1.middle_n_1 ;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_11 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_15 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_2 ;
wire \ODD1.middle_n_20 ;
wire \ODD1.middle_n_21 ;
wire \ODD1.middle_n_22 ;
wire \ODD1.middle_n_23 ;
wire \ODD1.middle_n_24 ;
wire \ODD1.middle_n_25 ;
wire \ODD1.middle_n_26 ;
wire \ODD1.middle_n_27 ;
wire \ODD1.middle_n_28 ;
wire \ODD1.middle_n_29 ;
wire \ODD1.middle_n_3 ;
wire \ODD1.middle_n_30 ;
wire \ODD1.middle_n_31 ;
wire \ODD1.middle_n_32 ;
wire \ODD1.middle_n_33 ;
wire \ODD1.middle_n_34 ;
wire \ODD1.middle_n_35 ;
wire \ODD1.middle_n_36 ;
wire \ODD1.middle_n_37 ;
wire \ODD1.middle_n_38 ;
wire \ODD1.middle_n_39 ;
wire \ODD1.middle_n_4 ;
wire \ODD1.middle_n_40 ;
wire \ODD1.middle_n_41 ;
wire \ODD1.middle_n_42 ;
wire \ODD1.middle_n_43 ;
wire \ODD1.middle_n_44 ;
wire \ODD1.middle_n_5 ;
wire \ODD1.middle_n_6 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_8 ;
wire \ODD1.middle_n_9 ;
wire \ODD1.right_lower_n_0 ;
wire \ODD1.right_lower_n_1 ;
wire \ODD1.right_lower_n_10 ;
wire \ODD1.right_lower_n_11 ;
wire \ODD1.right_lower_n_12 ;
wire \ODD1.right_lower_n_13 ;
wire \ODD1.right_lower_n_14 ;
wire \ODD1.right_lower_n_15 ;
wire \ODD1.right_lower_n_16 ;
wire \ODD1.right_lower_n_17 ;
wire \ODD1.right_lower_n_18 ;
wire \ODD1.right_lower_n_19 ;
wire \ODD1.right_lower_n_2 ;
wire \ODD1.right_lower_n_20 ;
wire \ODD1.right_lower_n_21 ;
wire \ODD1.right_lower_n_22 ;
wire \ODD1.right_lower_n_23 ;
wire \ODD1.right_lower_n_24 ;
wire \ODD1.right_lower_n_3 ;
wire \ODD1.right_lower_n_4 ;
wire \ODD1.right_lower_n_5 ;
wire \ODD1.right_lower_n_6 ;
wire \ODD1.right_lower_n_7 ;
wire \ODD1.right_lower_n_8 ;
wire \ODD1.right_lower_n_9 ;
wire [15:3]Q_middle_temp__5;
wire [0:0]S;
wire sgf_result_o0__1_carry__0_i_1__10_n_0;
wire sgf_result_o0__1_carry__0_i_1__11_n_0;
wire sgf_result_o0__1_carry__0_i_2__8_n_0;
wire sgf_result_o0__1_carry__0_i_2__9_n_0;
wire sgf_result_o0__1_carry__0_i_3__10_n_0;
wire sgf_result_o0__1_carry__0_i_3__9_n_0;
wire sgf_result_o0__1_carry__0_i_4__10_n_0;
wire sgf_result_o0__1_carry__0_i_4__11_n_0;
wire sgf_result_o0__1_carry__0_i_5__10_n_0;
wire sgf_result_o0__1_carry__0_i_5__11_n_0;
wire sgf_result_o0__1_carry__0_i_6__8_n_0;
wire sgf_result_o0__1_carry__0_i_6__9_n_0;
wire sgf_result_o0__1_carry__0_i_7__5_n_0;
wire sgf_result_o0__1_carry__0_i_7__6_n_0;
wire sgf_result_o0__1_carry__0_i_8__10_n_0;
wire sgf_result_o0__1_carry__0_i_8__9_n_0;
wire sgf_result_o0__1_carry__0_i_9__4_n_0;
wire sgf_result_o0__1_carry__0_i_9__5_n_0;
wire sgf_result_o0__1_carry_i_10__3_n_0;
wire sgf_result_o0__1_carry_i_10__4_n_0;
wire sgf_result_o0__1_carry_i_11__10_n_0;
wire sgf_result_o0__1_carry_i_11__9_n_0;
wire sgf_result_o0__1_carry_i_12_n_0;
wire sgf_result_o0__1_carry_i_13__0_n_0;
wire sgf_result_o0__1_carry_i_13_n_0;
wire sgf_result_o0__1_carry_i_14__0__0_n_0;
wire sgf_result_o0__1_carry_i_14_n_0;
wire sgf_result_o0__1_carry_i_15_n_0;
wire sgf_result_o0__1_carry_i_16__0_n_0;
wire sgf_result_o0__1_carry_i_16_n_0;
wire sgf_result_o0__1_carry_i_17__0_n_0;
wire sgf_result_o0__1_carry_i_17_n_0;
wire sgf_result_o0__1_carry_i_18_n_0;
wire sgf_result_o0__1_carry_i_19_n_0;
wire sgf_result_o0__1_carry_i_1__10_n_0;
wire sgf_result_o0__1_carry_i_1__11_n_0;
wire sgf_result_o0__1_carry_i_2__10_n_0;
wire sgf_result_o0__1_carry_i_2__11_n_0;
wire sgf_result_o0__1_carry_i_3__10_n_0;
wire sgf_result_o0__1_carry_i_3__11_n_0;
wire sgf_result_o0__1_carry_i_4__10_n_0;
wire sgf_result_o0__1_carry_i_4__11_n_0;
wire sgf_result_o0__1_carry_i_5__10_n_0;
wire sgf_result_o0__1_carry_i_5__11_n_0;
wire sgf_result_o0__1_carry_i_6__7_n_0;
wire sgf_result_o0__1_carry_i_6__8_n_0;
wire sgf_result_o0__1_carry_i_7__10_n_0;
wire sgf_result_o0__1_carry_i_7__11_n_0;
wire [15:0]sgf_result_o1;
wire sgf_result_o1__35_carry__0_n_0;
wire sgf_result_o1__35_carry__0_n_1;
wire sgf_result_o1__35_carry__0_n_2;
wire sgf_result_o1__35_carry__0_n_3;
wire sgf_result_o1__35_carry__1_n_0;
wire sgf_result_o1__35_carry__1_n_1;
wire sgf_result_o1__35_carry__1_n_2;
wire sgf_result_o1__35_carry__1_n_3;
wire sgf_result_o1__35_carry__2_n_1;
wire sgf_result_o1__35_carry__2_n_2;
wire sgf_result_o1__35_carry__2_n_3;
wire sgf_result_o1__35_carry_i_3_n_0;
wire sgf_result_o1__35_carry_n_0;
wire sgf_result_o1__35_carry_n_1;
wire sgf_result_o1__35_carry_n_2;
wire sgf_result_o1__35_carry_n_3;
wire sgf_result_o1_carry__0_n_0;
wire sgf_result_o1_carry__0_n_1;
wire sgf_result_o1_carry__0_n_2;
wire sgf_result_o1_carry__0_n_3;
wire sgf_result_o1_carry__1_n_0;
wire sgf_result_o1_carry__1_n_1;
wire sgf_result_o1_carry__1_n_2;
wire sgf_result_o1_carry__1_n_3;
wire sgf_result_o1_carry_n_0;
wire sgf_result_o1_carry_n_1;
wire sgf_result_o1_carry_n_2;
wire sgf_result_o1_carry_n_3;
wire [3:0]\sgf_result_o[15] ;
wire [3:0]\sgf_result_o[15]_0 ;
wire [0:0]\sgf_result_o[15]_1 ;
wire [0:0]\sgf_result_o[47] ;
wire [1:0]\sgf_result_o[47]_0 ;
wire [18:0]\sgf_result_o[47]_1 ;
wire [0:0]\sgf_result_o[47]_2 ;
wire [36:0]\sgf_result_o[47]_3 ;
wire [5:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[34]_inst_i_21_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_22_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_23_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_24_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_24_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_29_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_30_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_31_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_32_n_0 ;
wire [3:1]NLW_sgf_result_o0__1_carry_i_17__4_CO_UNCONNECTED;
wire [3:0]NLW_sgf_result_o0__1_carry_i_17__4_O_UNCONNECTED;
wire [3:1]NLW_sgf_result_o0__1_carry_i_22__1_CO_UNCONNECTED;
wire [3:0]NLW_sgf_result_o0__1_carry_i_22__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1__35_carry__2_CO_UNCONNECTED;
wire [3:0]NLW_sgf_result_o1_carry__2_CO_UNCONNECTED;
wire [3:1]NLW_sgf_result_o1_carry__2_O_UNCONNECTED;
Recursive_KOA__parameterized33 \ODD1.left_high
(.CO(CO),
.\Data_A_i[12] (\Data_A_i[12] ),
.Data_A_i_IBUF(Data_A_i_IBUF),
.\Data_B_i[12] (\sgf_result_o[15]_1 ),
.Data_B_i_IBUF(Data_B_i_IBUF),
.O({O,\ODD1.left_high_n_1 ,\ODD1.left_high_n_2 ,\ODD1.left_high_n_3 }),
.S(S),
.\sgf_result_o[15] (\sgf_result_o[15] ),
.\sgf_result_o[15]_0 (\sgf_result_o[15]_0 ),
.\sgf_result_o[15]_1 (\ODD1.left_high_n_21 ),
.\sgf_result_o[15]_2 (\ODD1.left_high_n_26 ),
.\sgf_result_o[47] ({\sgf_result_o[47] ,\ODD1.left_high_n_9 ,\ODD1.left_high_n_10 ,\ODD1.left_high_n_11 }),
.\sgf_result_o[47]_0 (\ODD1.left_high_n_16 ),
.\sgf_result_o[47]_1 ({\ODD1.left_high_n_17 ,\ODD1.left_high_n_18 ,\ODD1.left_high_n_19 ,\ODD1.left_high_n_20 }),
.\sgf_result_o[47]_2 ({\ODD1.left_high_n_22 ,\ODD1.left_high_n_23 ,\ODD1.left_high_n_24 ,\ODD1.left_high_n_25 }),
.\sgf_result_o[47]_3 ({\ODD1.left_high_n_27 ,\ODD1.left_high_n_28 ,\ODD1.left_high_n_29 ,\ODD1.left_high_n_30 }),
.\sgf_result_o[47]_4 ({\sgf_result_o[47]_2 ,\ODD1.left_high_n_32 ,\ODD1.left_high_n_33 ,\ODD1.left_high_n_34 }),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_0 ));
Recursive_KOA__parameterized44 \ODD1.middle
(.CO(\ODD1.middle_n_0 ),
.DI({sgf_result_o0__1_carry_i_1__10_n_0,sgf_result_o0__1_carry_i_2__10_n_0,sgf_result_o0__1_carry_i_3__10_n_0}),
.\Data_A_i[12] ({\ODD1.right_lower_n_0 ,\ODD1.right_lower_n_1 ,\ODD1.right_lower_n_2 }),
.\Data_A_i[12]_0 ({O,\ODD1.left_high_n_1 ,\ODD1.left_high_n_2 ,\ODD1.left_high_n_3 }),
.\Data_A_i[12]_1 (\sgf_result_o[15] [0]),
.\Data_A_i[12]_2 ({\ODD1.left_high_n_22 ,\ODD1.left_high_n_23 ,\ODD1.left_high_n_24 ,\ODD1.left_high_n_25 }),
.\Data_A_i[16] ({sgf_result_o0__1_carry__0_i_4__10_n_0,sgf_result_o0__1_carry__0_i_5__10_n_0,sgf_result_o0__1_carry__0_i_6__8_n_0}),
.\Data_A_i[16]_0 ({sgf_result_o0__1_carry_i_16_n_0,sgf_result_o0__1_carry_i_17_n_0,sgf_result_o0__1_carry_i_18_n_0,sgf_result_o0__1_carry_i_19_n_0}),
.\Data_A_i[20] ({sgf_result_o0__1_carry_i_1__11_n_0,sgf_result_o0__1_carry_i_2__11_n_0,sgf_result_o0__1_carry_i_3__11_n_0}),
.\Data_A_i[20]_0 ({sgf_result_o0__1_carry_i_4__11_n_0,sgf_result_o0__1_carry_i_5__11_n_0,sgf_result_o0__1_carry_i_6__8_n_0,sgf_result_o0__1_carry_i_7__11_n_0}),
.\Data_A_i[20]_1 ({sgf_result_o0__1_carry__0_i_4__11_n_0,sgf_result_o0__1_carry__0_i_5__11_n_0,sgf_result_o0__1_carry__0_i_6__9_n_0}),
.\Data_A_i[20]_2 ({sgf_result_o0__1_carry_i_16__0_n_0,sgf_result_o0__1_carry_i_17__0_n_0}),
.\Data_B_i[12] (\sgf_result_o[15]_0 [0]),
.\Data_B_i[12]_0 ({\sgf_result_o[47] ,\ODD1.left_high_n_9 ,\ODD1.left_high_n_10 ,\ODD1.left_high_n_11 }),
.\Data_B_i[12]_1 (\ODD1.left_high_n_16 ),
.\Data_B_i[12]_2 (\ODD1.left_high_n_30 ),
.\Data_B_i[12]_3 ({\ODD1.left_high_n_17 ,\ODD1.left_high_n_18 ,\ODD1.left_high_n_19 ,\ODD1.left_high_n_20 }),
.\Data_B_i[16] ({sgf_result_o0__1_carry__0_i_1__10_n_0,sgf_result_o0__1_carry__0_i_2__8_n_0,sgf_result_o0__1_carry__0_i_3__9_n_0}),
.\Data_B_i[16]_0 ({sgf_result_o0__1_carry_i_12_n_0,sgf_result_o0__1_carry_i_13_n_0,sgf_result_o0__1_carry_i_14_n_0,sgf_result_o0__1_carry_i_15_n_0}),
.\Data_B_i[20] ({sgf_result_o0__1_carry__0_i_1__11_n_0,sgf_result_o0__1_carry__0_i_2__9_n_0,sgf_result_o0__1_carry__0_i_3__10_n_0}),
.\Data_B_i[20]_0 ({sgf_result_o0__1_carry_i_13__0_n_0,sgf_result_o0__1_carry_i_14__0__0_n_0}),
.O({\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 ,\ODD1.middle_n_4 }),
.S({sgf_result_o0__1_carry_i_4__10_n_0,sgf_result_o0__1_carry_i_5__10_n_0,sgf_result_o0__1_carry_i_6__7_n_0,sgf_result_o0__1_carry_i_7__10_n_0}),
.\sgf_result_o[15] (\ODD1.middle_n_21 ),
.\sgf_result_o[15]_0 (\ODD1.middle_n_29 ),
.\sgf_result_o[47] ({\ODD1.middle_n_5 ,\ODD1.middle_n_6 ,\ODD1.middle_n_7 ,\ODD1.middle_n_8 }),
.\sgf_result_o[47]_0 ({\ODD1.middle_n_9 ,\ODD1.middle_n_10 }),
.\sgf_result_o[47]_1 ({\ODD1.middle_n_11 ,\ODD1.middle_n_12 ,\ODD1.middle_n_13 }),
.\sgf_result_o[47]_2 ({\ODD1.middle_n_14 ,\ODD1.middle_n_15 ,\ODD1.middle_n_16 ,\ODD1.middle_n_17 }),
.\sgf_result_o[47]_3 ({\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }),
.\sgf_result_o[47]_4 ({\ODD1.middle_n_22 ,\ODD1.middle_n_23 ,\ODD1.middle_n_24 ,\ODD1.middle_n_25 }),
.\sgf_result_o[47]_5 ({\ODD1.middle_n_26 ,\ODD1.middle_n_27 ,\ODD1.middle_n_28 }),
.\sgf_result_o[47]_6 ({\ODD1.middle_n_30 ,\ODD1.middle_n_31 ,\ODD1.middle_n_32 ,\ODD1.middle_n_33 }),
.\sgf_result_o[47]_7 ({\ODD1.middle_n_34 ,\ODD1.middle_n_35 ,\ODD1.middle_n_36 ,\ODD1.middle_n_37 }),
.\sgf_result_o[47]_8 ({\ODD1.middle_n_38 ,\ODD1.middle_n_39 ,\ODD1.middle_n_40 ,\ODD1.middle_n_41 }),
.\sgf_result_o[47]_9 ({\ODD1.middle_n_42 ,\ODD1.middle_n_43 ,\ODD1.middle_n_44 }));
Recursive_KOA__parameterized37 \ODD1.right_lower
(.DI({\ODD1.right_lower_n_3 ,\ODD1.right_lower_n_4 }),
.\Data_A_i[11] (\Data_A_i[11] ),
.\Data_A_i[11]_0 (\Data_A_i[11]_0 ),
.\Data_A_i[12] ({\ODD1.left_high_n_22 ,\ODD1.left_high_n_23 ,\ODD1.left_high_n_24 ,\ODD1.left_high_n_25 }),
.\Data_A_i[12]_0 (\sgf_result_o[47]_0 ),
.\Data_A_i[12]_1 (\ODD1.middle_n_11 ),
.\Data_A_i[12]_2 ({\Data_A_i[12]_0 ,\sgf_result_o_OBUF[38]_inst_i_24_n_0 }),
.\Data_A_i[13] (\Data_A_i[13] ),
.\Data_A_i[13]_0 (\Data_A_i[13]_0 ),
.\Data_A_i[13]_1 (\Data_A_i[13]_1 ),
.\Data_A_i[13]_2 (\Data_A_i[13]_2 ),
.\Data_A_i[13]_3 (\Data_A_i[13]_3 ),
.\Data_A_i[13]_4 (\Data_A_i[13]_4 ),
.\Data_A_i[14] (\Data_A_i[14] ),
.\Data_A_i[14]_0 (\Data_A_i[14]_0 ),
.\Data_A_i[14]_1 (\Data_A_i[14]_1 ),
.\Data_A_i[14]_2 (\Data_A_i[14]_2 ),
.\Data_A_i[14]_3 (\Data_A_i[14]_3 ),
.\Data_A_i[14]_4 (\Data_A_i[14]_4 ),
.\Data_A_i[14]_5 (\Data_A_i[14]_5 ),
.\Data_A_i[14]_6 (\Data_A_i[14]_6 ),
.\Data_A_i[17] (\Data_A_i[17] ),
.\Data_A_i[23] (\Data_A_i[23] ),
.\Data_A_i[23]_0 (\Data_A_i[23]_0 ),
.\Data_A_i[2] (\Data_A_i[2] ),
.\Data_A_i[2]_0 (\Data_A_i[2]_0 ),
.\Data_A_i[2]_1 (\Data_A_i[2]_1 ),
.Data_A_i_IBUF({Data_A_i_IBUF[13:12],Data_A_i_IBUF[1:0]}),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[12]_0 ({\ODD1.left_high_n_17 ,\ODD1.left_high_n_18 ,\ODD1.left_high_n_19 ,\ODD1.left_high_n_20 }),
.\Data_B_i[12]_1 ({\ODD1.left_high_n_9 ,\ODD1.left_high_n_10 ,\ODD1.left_high_n_11 }),
.\Data_B_i[12]_2 ({\ODD1.left_high_n_27 ,\ODD1.left_high_n_28 ,\ODD1.left_high_n_29 }),
.\Data_B_i[12]_3 ({\sgf_result_o[47]_2 ,\ODD1.left_high_n_32 ,\ODD1.left_high_n_33 ,\ODD1.left_high_n_34 }),
.\Data_B_i[12]_4 ({\sgf_result_o_OBUF[34]_inst_i_21_n_0 ,\sgf_result_o_OBUF[34]_inst_i_22_n_0 ,\sgf_result_o_OBUF[34]_inst_i_23_n_0 ,\sgf_result_o_OBUF[34]_inst_i_24_n_0 }),
.\Data_B_i[12]_5 ({\sgf_result_o_OBUF[38]_inst_i_29_n_0 ,\sgf_result_o_OBUF[38]_inst_i_30_n_0 ,\sgf_result_o_OBUF[38]_inst_i_31_n_0 ,\sgf_result_o_OBUF[38]_inst_i_32_n_0 }),
.\Data_B_i[17] (DI),
.\Data_B_i[17]_0 (\Data_B_i[17] ),
.Data_B_i_IBUF({Data_B_i_IBUF[13:12],Data_B_i_IBUF[1:0]}),
.O({\ODD1.left_high_n_1 ,\ODD1.left_high_n_2 ,\ODD1.left_high_n_3 }),
.Q_middle_temp__5(Q_middle_temp__5[14:3]),
.S({\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 ,\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 }),
.sgf_result_o1(sgf_result_o1),
.\sgf_result_o[47] ({\ODD1.right_lower_n_0 ,\ODD1.right_lower_n_1 ,\ODD1.right_lower_n_2 }),
.\sgf_result_o[47]_0 ({\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 ,\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 }),
.\sgf_result_o[47]_1 ({\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 ,\ODD1.right_lower_n_15 }),
.\sgf_result_o[47]_2 ({\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 ,\ODD1.right_lower_n_19 }),
.\sgf_result_o[47]_3 (\ODD1.right_lower_n_20 ),
.\sgf_result_o[47]_4 ({\ODD1.right_lower_n_21 ,\ODD1.right_lower_n_22 ,\ODD1.right_lower_n_23 ,\ODD1.right_lower_n_24 }),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_6 (\sgf_result_o[47]_3 ),
.sgf_result_o_OBUF(sgf_result_o_OBUF));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_1__10
(.I0(\ODD1.middle_n_14 ),
.I1(\ODD1.middle_n_22 ),
.O(sgf_result_o0__1_carry__0_i_1__10_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_1__11
(.I0(\ODD1.middle_n_21 ),
.I1(\ODD1.middle_n_29 ),
.O(sgf_result_o0__1_carry__0_i_1__11_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
sgf_result_o0__1_carry__0_i_2__8
(.I0(sgf_result_o0__1_carry_i_10__3_n_0),
.I1(\ODD1.middle_n_24 ),
.I2(\ODD1.middle_n_17 ),
.I3(\ODD1.middle_n_25 ),
.I4(\ODD1.middle_n_14 ),
.I5(sgf_result_o0__1_carry__0_i_7__5_n_0),
.O(sgf_result_o0__1_carry__0_i_2__8_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
sgf_result_o0__1_carry__0_i_2__9
(.I0(sgf_result_o0__1_carry_i_10__4_n_0),
.I1(\ODD1.middle_n_27 ),
.I2(\ODD1.middle_n_20 ),
.I3(\ODD1.middle_n_28 ),
.I4(\ODD1.middle_n_21 ),
.I5(sgf_result_o0__1_carry__0_i_7__6_n_0),
.O(sgf_result_o0__1_carry__0_i_2__9_n_0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
sgf_result_o0__1_carry__0_i_3__10
(.I0(sgf_result_o0__1_carry_i_10__4_n_0),
.I1(\ODD1.middle_n_27 ),
.I2(\ODD1.middle_n_20 ),
.I3(\ODD1.middle_n_28 ),
.I4(\ODD1.middle_n_21 ),
.I5(sgf_result_o0__1_carry__0_i_7__6_n_0),
.O(sgf_result_o0__1_carry__0_i_3__10_n_0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
sgf_result_o0__1_carry__0_i_3__9
(.I0(sgf_result_o0__1_carry_i_10__3_n_0),
.I1(\ODD1.middle_n_24 ),
.I2(\ODD1.middle_n_17 ),
.I3(\ODD1.middle_n_25 ),
.I4(\ODD1.middle_n_14 ),
.I5(sgf_result_o0__1_carry__0_i_7__5_n_0),
.O(sgf_result_o0__1_carry__0_i_3__9_n_0));
LUT6 #(
.INIT(64'h173F8080C0000000))
sgf_result_o0__1_carry__0_i_4__10
(.I0(\ODD1.middle_n_24 ),
.I1(\ODD1.middle_n_15 ),
.I2(\ODD1.middle_n_23 ),
.I3(\ODD1.middle_n_16 ),
.I4(\ODD1.middle_n_22 ),
.I5(\ODD1.middle_n_14 ),
.O(sgf_result_o0__1_carry__0_i_4__10_n_0));
LUT6 #(
.INIT(64'h173F8080C0000000))
sgf_result_o0__1_carry__0_i_4__11
(.I0(\ODD1.middle_n_27 ),
.I1(\ODD1.middle_n_18 ),
.I2(\ODD1.middle_n_26 ),
.I3(\ODD1.middle_n_19 ),
.I4(\ODD1.middle_n_29 ),
.I5(\ODD1.middle_n_21 ),
.O(sgf_result_o0__1_carry__0_i_4__11_n_0));
LUT6 #(
.INIT(64'h9666699969996999))
sgf_result_o0__1_carry__0_i_5__10
(.I0(sgf_result_o0__1_carry__0_i_2__8_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__9_n_0),
.I2(\ODD1.middle_n_14 ),
.I3(\ODD1.middle_n_23 ),
.I4(\ODD1.middle_n_15 ),
.I5(\ODD1.middle_n_22 ),
.O(sgf_result_o0__1_carry__0_i_5__10_n_0));
LUT6 #(
.INIT(64'h9666699969996999))
sgf_result_o0__1_carry__0_i_5__11
(.I0(sgf_result_o0__1_carry__0_i_2__9_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__10_n_0),
.I2(\ODD1.middle_n_21 ),
.I3(\ODD1.middle_n_26 ),
.I4(\ODD1.middle_n_18 ),
.I5(\ODD1.middle_n_29 ),
.O(sgf_result_o0__1_carry__0_i_5__11_n_0));
LUT6 #(
.INIT(64'h56666AAA6AAA6AAA))
sgf_result_o0__1_carry__0_i_6__8
(.I0(sgf_result_o0__1_carry__0_i_3__9_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__4_n_0),
.I2(\ODD1.middle_n_16 ),
.I3(\ODD1.middle_n_23 ),
.I4(\ODD1.middle_n_17 ),
.I5(\ODD1.middle_n_22 ),
.O(sgf_result_o0__1_carry__0_i_6__8_n_0));
LUT6 #(
.INIT(64'h56666AAA6AAA6AAA))
sgf_result_o0__1_carry__0_i_6__9
(.I0(sgf_result_o0__1_carry__0_i_3__10_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__5_n_0),
.I2(\ODD1.middle_n_19 ),
.I3(\ODD1.middle_n_26 ),
.I4(\ODD1.middle_n_20 ),
.I5(\ODD1.middle_n_29 ),
.O(sgf_result_o0__1_carry__0_i_6__9_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry__0_i_7__5
(.I0(\ODD1.middle_n_24 ),
.I1(\ODD1.middle_n_14 ),
.I2(\ODD1.middle_n_15 ),
.I3(\ODD1.middle_n_23 ),
.I4(\ODD1.middle_n_16 ),
.I5(\ODD1.middle_n_22 ),
.O(sgf_result_o0__1_carry__0_i_7__5_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry__0_i_7__6
(.I0(\ODD1.middle_n_27 ),
.I1(\ODD1.middle_n_21 ),
.I2(\ODD1.middle_n_18 ),
.I3(\ODD1.middle_n_26 ),
.I4(\ODD1.middle_n_19 ),
.I5(\ODD1.middle_n_29 ),
.O(sgf_result_o0__1_carry__0_i_7__6_n_0));
LUT6 #(
.INIT(64'h07777FFF7FFF7FFF))
sgf_result_o0__1_carry__0_i_8__10
(.I0(\ODD1.middle_n_29 ),
.I1(\ODD1.middle_n_19 ),
.I2(\ODD1.middle_n_26 ),
.I3(\ODD1.middle_n_18 ),
.I4(\ODD1.middle_n_21 ),
.I5(\ODD1.middle_n_27 ),
.O(sgf_result_o0__1_carry__0_i_8__10_n_0));
LUT6 #(
.INIT(64'h07777FFF7FFF7FFF))
sgf_result_o0__1_carry__0_i_8__9
(.I0(\ODD1.middle_n_22 ),
.I1(\ODD1.middle_n_16 ),
.I2(\ODD1.middle_n_23 ),
.I3(\ODD1.middle_n_15 ),
.I4(\ODD1.middle_n_14 ),
.I5(\ODD1.middle_n_24 ),
.O(sgf_result_o0__1_carry__0_i_8__9_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_9__4
(.I0(\ODD1.middle_n_15 ),
.I1(\ODD1.middle_n_24 ),
.O(sgf_result_o0__1_carry__0_i_9__4_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_9__5
(.I0(\ODD1.middle_n_18 ),
.I1(\ODD1.middle_n_27 ),
.O(sgf_result_o0__1_carry__0_i_9__5_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_10__3
(.I0(\ODD1.middle_n_16 ),
.I1(\ODD1.middle_n_23 ),
.O(sgf_result_o0__1_carry_i_10__3_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_10__4
(.I0(\ODD1.middle_n_19 ),
.I1(\ODD1.middle_n_26 ),
.O(sgf_result_o0__1_carry_i_10__4_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_11__10
(.I0(\ODD1.middle_n_28 ),
.I1(\ODD1.middle_n_21 ),
.O(sgf_result_o0__1_carry_i_11__10_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_11__9
(.I0(\ODD1.middle_n_25 ),
.I1(\ODD1.middle_n_14 ),
.O(sgf_result_o0__1_carry_i_11__9_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_12
(.I0(\ODD1.left_high_n_17 ),
.I1(\sgf_result_o[15]_0 [2]),
.O(sgf_result_o0__1_carry_i_12_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_13
(.I0(\ODD1.left_high_n_18 ),
.I1(\sgf_result_o[15]_0 [1]),
.O(sgf_result_o0__1_carry_i_13_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_13__0
(.I0(\ODD1.left_high_n_10 ),
.I1(\sgf_result_o[15]_1 ),
.O(sgf_result_o0__1_carry_i_13__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_14
(.I0(\ODD1.left_high_n_19 ),
.I1(\sgf_result_o[15]_0 [0]),
.O(sgf_result_o0__1_carry_i_14_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_14__0__0
(.I0(\ODD1.left_high_n_11 ),
.I1(\sgf_result_o[15]_0 [3]),
.O(sgf_result_o0__1_carry_i_14__0__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_15
(.I0(\ODD1.left_high_n_20 ),
.I1(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry_i_15_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_16
(.I0(\ODD1.left_high_n_22 ),
.I1(\sgf_result_o[15] [2]),
.O(sgf_result_o0__1_carry_i_16_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_16__0
(.I0(\ODD1.left_high_n_2 ),
.I1(CO),
.O(sgf_result_o0__1_carry_i_16__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_17
(.I0(\ODD1.left_high_n_23 ),
.I1(\sgf_result_o[15] [1]),
.O(sgf_result_o0__1_carry_i_17_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_17__0
(.I0(\ODD1.left_high_n_3 ),
.I1(\sgf_result_o[15] [3]),
.O(sgf_result_o0__1_carry_i_17__0_n_0));
CARRY4 sgf_result_o0__1_carry_i_17__4
(.CI(\ODD1.left_high_n_26 ),
.CO({NLW_sgf_result_o0__1_carry_i_17__4_CO_UNCONNECTED[3:1],CO}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_sgf_result_o0__1_carry_i_17__4_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_18
(.I0(\ODD1.left_high_n_24 ),
.I1(\sgf_result_o[15] [0]),
.O(sgf_result_o0__1_carry_i_18_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_19
(.I0(\ODD1.left_high_n_25 ),
.I1(O),
.O(sgf_result_o0__1_carry_i_19_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_1__10
(.I0(\ODD1.middle_n_24 ),
.I1(\ODD1.middle_n_15 ),
.I2(\ODD1.middle_n_16 ),
.I3(\ODD1.middle_n_23 ),
.I4(\ODD1.middle_n_17 ),
.I5(\ODD1.middle_n_22 ),
.O(sgf_result_o0__1_carry_i_1__10_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_1__11
(.I0(\ODD1.middle_n_27 ),
.I1(\ODD1.middle_n_18 ),
.I2(\ODD1.middle_n_19 ),
.I3(\ODD1.middle_n_26 ),
.I4(\ODD1.middle_n_20 ),
.I5(\ODD1.middle_n_29 ),
.O(sgf_result_o0__1_carry_i_1__11_n_0));
CARRY4 sgf_result_o0__1_carry_i_22__1
(.CI(\ODD1.left_high_n_21 ),
.CO({NLW_sgf_result_o0__1_carry_i_22__1_CO_UNCONNECTED[3:1],\sgf_result_o[15]_1 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_sgf_result_o0__1_carry_i_22__1_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_2__10
(.I0(\ODD1.middle_n_24 ),
.I1(\ODD1.middle_n_16 ),
.I2(\ODD1.middle_n_23 ),
.I3(\ODD1.middle_n_17 ),
.O(sgf_result_o0__1_carry_i_2__10_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_2__11
(.I0(\ODD1.middle_n_27 ),
.I1(\ODD1.middle_n_19 ),
.I2(\ODD1.middle_n_26 ),
.I3(\ODD1.middle_n_20 ),
.O(sgf_result_o0__1_carry_i_2__11_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_3__10
(.I0(\ODD1.middle_n_17 ),
.I1(\ODD1.middle_n_24 ),
.O(sgf_result_o0__1_carry_i_3__10_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_3__11
(.I0(\ODD1.middle_n_20 ),
.I1(\ODD1.middle_n_27 ),
.O(sgf_result_o0__1_carry_i_3__11_n_0));
LUT6 #(
.INIT(64'h99A5C30F665A3CF0))
sgf_result_o0__1_carry_i_4__10
(.I0(\ODD1.middle_n_22 ),
.I1(\ODD1.middle_n_15 ),
.I2(sgf_result_o0__1_carry_i_10__3_n_0),
.I3(\ODD1.middle_n_24 ),
.I4(\ODD1.middle_n_17 ),
.I5(sgf_result_o0__1_carry_i_11__9_n_0),
.O(sgf_result_o0__1_carry_i_4__10_n_0));
LUT6 #(
.INIT(64'h99A5C30F665A3CF0))
sgf_result_o0__1_carry_i_4__11
(.I0(\ODD1.middle_n_29 ),
.I1(\ODD1.middle_n_18 ),
.I2(sgf_result_o0__1_carry_i_10__4_n_0),
.I3(\ODD1.middle_n_27 ),
.I4(\ODD1.middle_n_20 ),
.I5(sgf_result_o0__1_carry_i_11__10_n_0),
.O(sgf_result_o0__1_carry_i_4__11_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_5__10
(.I0(\ODD1.middle_n_17 ),
.I1(\ODD1.middle_n_23 ),
.I2(\ODD1.middle_n_16 ),
.I3(\ODD1.middle_n_24 ),
.I4(\ODD1.middle_n_15 ),
.I5(\ODD1.middle_n_25 ),
.O(sgf_result_o0__1_carry_i_5__10_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_5__11
(.I0(\ODD1.middle_n_20 ),
.I1(\ODD1.middle_n_26 ),
.I2(\ODD1.middle_n_19 ),
.I3(\ODD1.middle_n_27 ),
.I4(\ODD1.middle_n_18 ),
.I5(\ODD1.middle_n_28 ),
.O(sgf_result_o0__1_carry_i_5__11_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_6__7
(.I0(\ODD1.middle_n_16 ),
.I1(\ODD1.middle_n_25 ),
.I2(\ODD1.middle_n_24 ),
.I3(\ODD1.middle_n_17 ),
.O(sgf_result_o0__1_carry_i_6__7_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_6__8
(.I0(\ODD1.middle_n_19 ),
.I1(\ODD1.middle_n_28 ),
.I2(\ODD1.middle_n_27 ),
.I3(\ODD1.middle_n_20 ),
.O(sgf_result_o0__1_carry_i_6__8_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_7__10
(.I0(\ODD1.middle_n_25 ),
.I1(\ODD1.middle_n_17 ),
.O(sgf_result_o0__1_carry_i_7__10_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_7__11
(.I0(\ODD1.middle_n_28 ),
.I1(\ODD1.middle_n_20 ),
.O(sgf_result_o0__1_carry_i_7__11_n_0));
CARRY4 sgf_result_o1__35_carry
(.CI(1'b0),
.CO({sgf_result_o1__35_carry_n_0,sgf_result_o1__35_carry_n_1,sgf_result_o1__35_carry_n_2,sgf_result_o1__35_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.middle_n_11 ,\ODD1.middle_n_12 ,\ODD1.middle_n_13 ,1'b1}),
.O(sgf_result_o1[3:0]),
.S({\ODD1.right_lower_n_20 ,\ODD1.middle_n_42 ,\ODD1.middle_n_43 ,\ODD1.middle_n_44 }));
CARRY4 sgf_result_o1__35_carry__0
(.CI(sgf_result_o1__35_carry_n_0),
.CO({sgf_result_o1__35_carry__0_n_0,sgf_result_o1__35_carry__0_n_1,sgf_result_o1__35_carry__0_n_2,sgf_result_o1__35_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 ,\ODD1.right_lower_n_19 }),
.O(sgf_result_o1[7:4]),
.S({\ODD1.right_lower_n_21 ,\ODD1.right_lower_n_22 ,\ODD1.right_lower_n_23 ,\ODD1.right_lower_n_24 }));
CARRY4 sgf_result_o1__35_carry__1
(.CI(sgf_result_o1__35_carry__0_n_0),
.CO({sgf_result_o1__35_carry__1_n_0,sgf_result_o1__35_carry__1_n_1,sgf_result_o1__35_carry__1_n_2,sgf_result_o1__35_carry__1_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 ,\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 }),
.O(sgf_result_o1[11:8]),
.S({\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 ,\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 }));
CARRY4 sgf_result_o1__35_carry__2
(.CI(sgf_result_o1__35_carry__1_n_0),
.CO({NLW_sgf_result_o1__35_carry__2_CO_UNCONNECTED[3],sgf_result_o1__35_carry__2_n_1,sgf_result_o1__35_carry__2_n_2,sgf_result_o1__35_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q_middle_temp__5[14],\ODD1.right_lower_n_3 ,\ODD1.right_lower_n_4 }),
.O(sgf_result_o1[15:12]),
.S({sgf_result_o1__35_carry_i_3_n_0,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 ,\ODD1.right_lower_n_15 }));
LUT1 #(
.INIT(2'h1))
sgf_result_o1__35_carry_i_3
(.I0(Q_middle_temp__5[15]),
.O(sgf_result_o1__35_carry_i_3_n_0));
CARRY4 sgf_result_o1_carry
(.CI(1'b0),
.CO({sgf_result_o1_carry_n_0,sgf_result_o1_carry_n_1,sgf_result_o1_carry_n_2,sgf_result_o1_carry_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.middle_n_2 ,\ODD1.middle_n_3 ,\ODD1.middle_n_4 ,1'b0}),
.O(Q_middle_temp__5[6:3]),
.S({\ODD1.middle_n_30 ,\ODD1.middle_n_31 ,\ODD1.middle_n_32 ,\ODD1.middle_n_33 }));
CARRY4 sgf_result_o1_carry__0
(.CI(sgf_result_o1_carry_n_0),
.CO({sgf_result_o1_carry__0_n_0,sgf_result_o1_carry__0_n_1,sgf_result_o1_carry__0_n_2,sgf_result_o1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.middle_n_6 ,\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_1 }),
.O(Q_middle_temp__5[10:7]),
.S({\ODD1.middle_n_34 ,\ODD1.middle_n_35 ,\ODD1.middle_n_36 ,\ODD1.middle_n_37 }));
CARRY4 sgf_result_o1_carry__1
(.CI(sgf_result_o1_carry__0_n_0),
.CO({sgf_result_o1_carry__1_n_0,sgf_result_o1_carry__1_n_1,sgf_result_o1_carry__1_n_2,sgf_result_o1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\ODD1.middle_n_9 ,\ODD1.middle_n_10 ,\ODD1.middle_n_5 }),
.O(Q_middle_temp__5[14:11]),
.S({\ODD1.middle_n_38 ,\ODD1.middle_n_39 ,\ODD1.middle_n_40 ,\ODD1.middle_n_41 }));
CARRY4 sgf_result_o1_carry__2
(.CI(sgf_result_o1_carry__1_n_0),
.CO(NLW_sgf_result_o1_carry__2_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_sgf_result_o1_carry__2_O_UNCONNECTED[3:1],Q_middle_temp__5[15]}),
.S({1'b0,1'b0,1'b0,\ODD1.middle_n_0 }));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_21
(.I0(sgf_result_o1[10]),
.I1(\ODD1.left_high_n_29 ),
.O(\sgf_result_o_OBUF[34]_inst_i_21_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_22
(.I0(sgf_result_o1[9]),
.I1(\ODD1.left_high_n_30 ),
.O(\sgf_result_o_OBUF[34]_inst_i_22_n_0 ));
LUT5 #(
.INIT(32'h956A6A6A))
\sgf_result_o_OBUF[34]_inst_i_23
(.I0(sgf_result_o1[8]),
.I1(\sgf_result_o[47] ),
.I2(\sgf_result_o[15] [0]),
.I3(O),
.I4(\sgf_result_o[15]_0 [0]),
.O(\sgf_result_o_OBUF[34]_inst_i_23_n_0 ));
LUT3 #(
.INIT(8'h6A))
\sgf_result_o_OBUF[34]_inst_i_24
(.I0(sgf_result_o1[7]),
.I1(O),
.I2(\sgf_result_o[47] ),
.O(\sgf_result_o_OBUF[34]_inst_i_24_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_24
(.I0(sgf_result_o1[15]),
.I1(\ODD1.left_high_n_32 ),
.O(\sgf_result_o_OBUF[38]_inst_i_24_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_29
(.I0(sgf_result_o1[14]),
.I1(\ODD1.left_high_n_33 ),
.O(\sgf_result_o_OBUF[38]_inst_i_29_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_30
(.I0(sgf_result_o1[13]),
.I1(\ODD1.left_high_n_34 ),
.O(\sgf_result_o_OBUF[38]_inst_i_30_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_31
(.I0(sgf_result_o1[12]),
.I1(\ODD1.left_high_n_27 ),
.O(\sgf_result_o_OBUF[38]_inst_i_31_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_32
(.I0(sgf_result_o1[11]),
.I1(\ODD1.left_high_n_28 ),
.O(\sgf_result_o_OBUF[38]_inst_i_32_n_0 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized33
(O,
\sgf_result_o[15] ,
\sgf_result_o[47] ,
\sgf_result_o[15]_0 ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
CO,
\Data_B_i[12] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
S,
\Data_A_i[12] );
output [3:0]O;
output [3:0]\sgf_result_o[15] ;
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[15]_0 ;
output \sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [0:0]\sgf_result_o[15]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [0:0]\sgf_result_o[15]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [1:0]\sgf_result_o[47]_5 ;
input [0:0]CO;
input [0:0]\Data_B_i[12] ;
input [23:0]Data_B_i_IBUF;
input [23:0]Data_A_i_IBUF;
input [0:0]S;
input [0:0]\Data_A_i[12] ;
wire [0:0]CO;
wire [0:0]\Data_A_i[12] ;
wire [23:0]Data_A_i_IBUF;
wire [0:0]\Data_B_i[12] ;
wire [23:0]Data_B_i_IBUF;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_2 ;
wire [3:0]O;
wire [0:0]S;
wire S_B0__0_carry__0_i_10__3_n_0;
wire S_B0__0_carry__0_i_7__3_n_0;
wire S_B0__0_carry__0_i_8__3_n_0;
wire S_B0__0_carry__0_i_9__3_n_0;
wire S_B0__0_carry_i_11__3_n_0;
wire S_B0__0_carry_i_12__3_n_0;
wire S_B0__0_carry_i_13__2_n_0;
wire S_B0__0_carry_i_8__3_n_0;
wire S_B0__0_carry_i_9__3_n_0;
wire sgf_result_o0__1_carry__0_i_10__0_n_0;
wire sgf_result_o0__1_carry__0_i_1__9_n_0;
wire sgf_result_o0__1_carry__0_i_2__7_n_0;
wire sgf_result_o0__1_carry__0_i_3__8_n_0;
wire sgf_result_o0__1_carry__0_i_4__9_n_0;
wire sgf_result_o0__1_carry__0_i_5__9_n_0;
wire sgf_result_o0__1_carry__0_i_6__7_n_0;
wire sgf_result_o0__1_carry__0_i_7__4_n_0;
wire sgf_result_o0__1_carry__0_i_8__8_n_0;
wire sgf_result_o0__1_carry__0_i_9__9_n_0;
wire sgf_result_o0__1_carry_i_10__12_n_0;
wire sgf_result_o0__1_carry_i_11__12_n_1;
wire sgf_result_o0__1_carry_i_11__12_n_2;
wire sgf_result_o0__1_carry_i_11__12_n_3;
wire sgf_result_o0__1_carry_i_12__0_n_0;
wire sgf_result_o0__1_carry_i_12__7_n_0;
wire sgf_result_o0__1_carry_i_13__1_n_0;
wire sgf_result_o0__1_carry_i_13__6_n_0;
wire sgf_result_o0__1_carry_i_14__1_n_1;
wire sgf_result_o0__1_carry_i_14__1_n_2;
wire sgf_result_o0__1_carry_i_14__1_n_3;
wire sgf_result_o0__1_carry_i_14__2_n_0;
wire sgf_result_o0__1_carry_i_15__0_n_0;
wire sgf_result_o0__1_carry_i_15__3_n_0;
wire sgf_result_o0__1_carry_i_16__2_n_0;
wire sgf_result_o0__1_carry_i_16__4_n_0;
wire sgf_result_o0__1_carry_i_17__1_n_0;
wire sgf_result_o0__1_carry_i_18__0__0_n_0;
wire sgf_result_o0__1_carry_i_18__0_n_0;
wire sgf_result_o0__1_carry_i_19__0__0_n_0;
wire sgf_result_o0__1_carry_i_19__0_n_0;
wire sgf_result_o0__1_carry_i_1__9_n_0;
wire sgf_result_o0__1_carry_i_20_n_0;
wire sgf_result_o0__1_carry_i_21_n_0;
wire sgf_result_o0__1_carry_i_23_n_0;
wire sgf_result_o0__1_carry_i_24_n_0;
wire sgf_result_o0__1_carry_i_25_n_0;
wire sgf_result_o0__1_carry_i_26_n_0;
wire sgf_result_o0__1_carry_i_2__9_n_0;
wire sgf_result_o0__1_carry_i_3__9_n_0;
wire sgf_result_o0__1_carry_i_4__9_n_0;
wire sgf_result_o0__1_carry_i_5__9_n_0;
wire sgf_result_o0__1_carry_i_6__6_n_0;
wire sgf_result_o0__1_carry_i_7__9_n_0;
wire sgf_result_o0__1_carry_i_8__10_n_0;
wire sgf_result_o0__1_carry_i_8__10_n_1;
wire sgf_result_o0__1_carry_i_8__10_n_2;
wire sgf_result_o0__1_carry_i_8__10_n_3;
wire sgf_result_o0__1_carry_i_8__6_n_0;
wire sgf_result_o0__1_carry_i_9__12_n_0;
wire sgf_result_o0__1_carry_i_9__5_n_0;
wire sgf_result_o0__1_carry_i_9__5_n_1;
wire sgf_result_o0__1_carry_i_9__5_n_2;
wire sgf_result_o0__1_carry_i_9__5_n_3;
wire sgf_result_o1__0_carry_i_13__2_n_0;
wire sgf_result_o1__0_carry_i_13__2_n_1;
wire sgf_result_o1__0_carry_i_13__2_n_2;
wire sgf_result_o1__0_carry_i_13__2_n_3;
wire sgf_result_o1__0_carry_i_18__1_n_0;
wire sgf_result_o1__0_carry_i_18__1_n_1;
wire sgf_result_o1__0_carry_i_18__1_n_2;
wire sgf_result_o1__0_carry_i_18__1_n_3;
wire sgf_result_o1__0_carry_i_20_n_0;
wire sgf_result_o1__0_carry_i_21_n_0;
wire sgf_result_o1__0_carry_i_22_n_0;
wire sgf_result_o1__0_carry_i_23_n_0;
wire sgf_result_o1__0_carry_i_25_n_0;
wire sgf_result_o1__0_carry_i_26_n_0;
wire sgf_result_o1__0_carry_i_27_n_0;
wire sgf_result_o1__0_carry_i_28_n_0;
wire sgf_result_o1__35_carry_i_10__0_n_0;
wire sgf_result_o1__35_carry_i_11_n_0;
wire sgf_result_o1__35_carry_i_9__1_n_0;
wire [3:0]\sgf_result_o[15] ;
wire [3:0]\sgf_result_o[15]_0 ;
wire [0:0]\sgf_result_o[15]_1 ;
wire [0:0]\sgf_result_o[15]_2 ;
wire [3:0]\sgf_result_o[47] ;
wire \sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [1:0]\sgf_result_o[47]_5 ;
Recursive_KOA__parameterized36 \EVEN1.middle
(.DI({sgf_result_o0__1_carry_i_1__9_n_0,sgf_result_o0__1_carry_i_2__9_n_0,sgf_result_o0__1_carry_i_3__9_n_0}),
.\Data_A_i[12] ({sgf_result_o0__1_carry__0_i_1__9_n_0,sgf_result_o0__1_carry__0_i_2__7_n_0,sgf_result_o0__1_carry__0_i_3__8_n_0}),
.\Data_A_i[12]_0 ({sgf_result_o0__1_carry__0_i_4__9_n_0,sgf_result_o0__1_carry__0_i_5__9_n_0,sgf_result_o0__1_carry__0_i_6__7_n_0}),
.\Data_A_i[12]_1 (\sgf_result_o[15] [3:2]),
.\Data_A_i[12]_10 (\Data_A_i[12] ),
.\Data_A_i[12]_11 (O[3]),
.\Data_A_i[12]_2 (S_B0__0_carry_i_13__2_n_0),
.\Data_A_i[12]_3 (S_B0__0_carry__0_i_9__3_n_0),
.\Data_A_i[12]_4 (S_B0__0_carry__0_i_10__3_n_0),
.\Data_A_i[12]_5 (S_B0__0_carry_i_9__3_n_0),
.\Data_A_i[12]_6 (S_B0__0_carry_i_12__3_n_0),
.\Data_A_i[12]_7 (S_B0__0_carry__0_i_8__3_n_0),
.\Data_A_i[12]_8 ({sgf_result_o1__35_carry_i_9__1_n_0,sgf_result_o1__35_carry_i_11_n_0,S}),
.\Data_A_i[12]_9 (sgf_result_o1__35_carry_i_10__0_n_0),
.\Data_B_i[12] (\sgf_result_o[15]_0 [3:2]),
.\Data_B_i[12]_0 (\sgf_result_o[47]_0 ),
.\Data_B_i[12]_1 (S_B0__0_carry_i_8__3_n_0),
.\Data_B_i[12]_2 (S_B0__0_carry_i_11__3_n_0),
.\Data_B_i[12]_3 (S_B0__0_carry__0_i_7__3_n_0),
.\Data_B_i[12]_4 (\sgf_result_o[47] [3]),
.O({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 }),
.S({sgf_result_o0__1_carry_i_4__9_n_0,sgf_result_o0__1_carry_i_5__9_n_0,sgf_result_o0__1_carry_i_6__6_n_0,sgf_result_o0__1_carry_i_7__9_n_0}),
.\sgf_result_o[47] (\EVEN1.middle_n_2 ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_5 ));
LUT6 #(
.INIT(64'hAA00800080000000))
S_B0__0_carry__0_i_10__3
(.I0(CO),
.I1(\sgf_result_o[15]_0 [2]),
.I2(\sgf_result_o[15] [2]),
.I3(\Data_B_i[12] ),
.I4(\sgf_result_o[15] [3]),
.I5(\sgf_result_o[15]_0 [3]),
.O(S_B0__0_carry__0_i_10__3_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_7__3
(.I0(\sgf_result_o[15]_0 [0]),
.I1(\sgf_result_o[15] [0]),
.I2(\sgf_result_o[15]_0 [1]),
.I3(O[3]),
.I4(\sgf_result_o[47] [3]),
.I5(\sgf_result_o[15] [1]),
.O(S_B0__0_carry__0_i_7__3_n_0));
LUT6 #(
.INIT(64'h9878707080008000))
S_B0__0_carry__0_i_8__3
(.I0(\sgf_result_o[15]_0 [3]),
.I1(\sgf_result_o[15] [3]),
.I2(\Data_B_i[12] ),
.I3(\sgf_result_o[15] [2]),
.I4(\sgf_result_o[15]_0 [2]),
.I5(CO),
.O(S_B0__0_carry__0_i_8__3_n_0));
LUT6 #(
.INIT(64'h55FF7FFF7FFFFFFF))
S_B0__0_carry__0_i_9__3
(.I0(\sgf_result_o[15] [1]),
.I1(\sgf_result_o[47] [3]),
.I2(O[3]),
.I3(\sgf_result_o[15]_0 [1]),
.I4(\sgf_result_o[15] [0]),
.I5(\sgf_result_o[15]_0 [0]),
.O(S_B0__0_carry__0_i_9__3_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_10__2
(.I0(\sgf_result_o[15]_0 [0]),
.I1(O[3]),
.I2(\sgf_result_o[15] [0]),
.I3(\sgf_result_o[47] [3]),
.O(\sgf_result_o[47]_0 ));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_11__3
(.I0(\sgf_result_o[15]_0 [0]),
.I1(\sgf_result_o[15] [0]),
.I2(\sgf_result_o[15]_0 [1]),
.I3(O[3]),
.I4(\sgf_result_o[47] [3]),
.I5(\sgf_result_o[15] [1]),
.O(S_B0__0_carry_i_11__3_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
S_B0__0_carry_i_12__3
(.I0(\sgf_result_o[15]_0 [3]),
.I1(\sgf_result_o[15] [3]),
.I2(\Data_B_i[12] ),
.I3(\sgf_result_o[15] [2]),
.I4(\sgf_result_o[15]_0 [2]),
.I5(CO),
.O(S_B0__0_carry_i_12__3_n_0));
LUT4 #(
.INIT(16'h7888))
S_B0__0_carry_i_13__2
(.I0(\sgf_result_o[15]_0 [3]),
.I1(\sgf_result_o[15] [2]),
.I2(\sgf_result_o[15] [3]),
.I3(\sgf_result_o[15]_0 [2]),
.O(S_B0__0_carry_i_13__2_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_8__3
(.I0(\sgf_result_o[15]_0 [0]),
.I1(\sgf_result_o[15] [0]),
.I2(\sgf_result_o[15]_0 [1]),
.I3(O[3]),
.I4(\sgf_result_o[47] [3]),
.I5(\sgf_result_o[15] [1]),
.O(S_B0__0_carry_i_8__3_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
S_B0__0_carry_i_9__3
(.I0(\sgf_result_o[15]_0 [3]),
.I1(\sgf_result_o[15] [3]),
.I2(\Data_B_i[12] ),
.I3(\sgf_result_o[15] [2]),
.I4(\sgf_result_o[15]_0 [2]),
.I5(CO),
.O(S_B0__0_carry_i_9__3_n_0));
LUT6 #(
.INIT(64'h022002200220ABBA))
sgf_result_o0__1_carry__0_i_10__0
(.I0(sgf_result_o0__1_carry_i_10__12_n_0),
.I1(sgf_result_o0__1_carry_i_12__7_n_0),
.I2(O[3]),
.I3(\sgf_result_o[15] [2]),
.I4(sgf_result_o0__1_carry_i_9__12_n_0),
.I5(sgf_result_o0__1_carry_i_8__6_n_0),
.O(sgf_result_o0__1_carry__0_i_10__0_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_1__9
(.I0(sgf_result_o0__1_carry_i_12__7_n_0),
.I1(sgf_result_o0__1_carry_i_15__3_n_0),
.O(sgf_result_o0__1_carry__0_i_1__9_n_0));
LUT5 #(
.INIT(32'h14000000))
sgf_result_o0__1_carry__0_i_2__7
(.I0(sgf_result_o0__1_carry_i_15__3_n_0),
.I1(\sgf_result_o[47] [3]),
.I2(\sgf_result_o[15]_0 [2]),
.I3(sgf_result_o0__1_carry_i_3__9_n_0),
.I4(sgf_result_o0__1_carry_i_10__12_n_0),
.O(sgf_result_o0__1_carry__0_i_2__7_n_0));
LUT6 #(
.INIT(64'h56A956A956A9A956))
sgf_result_o0__1_carry__0_i_3__8
(.I0(sgf_result_o0__1_carry__0_i_2__7_n_0),
.I1(sgf_result_o0__1_carry_i_12__7_n_0),
.I2(sgf_result_o0__1_carry_i_16__4_n_0),
.I3(sgf_result_o0__1_carry__0_i_7__4_n_0),
.I4(sgf_result_o0__1_carry_i_9__12_n_0),
.I5(sgf_result_o0__1_carry_i_15__3_n_0),
.O(sgf_result_o0__1_carry__0_i_3__8_n_0));
LUT6 #(
.INIT(64'h000001010003FCE8))
sgf_result_o0__1_carry__0_i_4__9
(.I0(sgf_result_o0__1_carry_i_9__12_n_0),
.I1(sgf_result_o0__1_carry_i_13__6_n_0),
.I2(sgf_result_o0__1_carry_i_8__6_n_0),
.I3(sgf_result_o0__1_carry_i_16__4_n_0),
.I4(sgf_result_o0__1_carry_i_15__3_n_0),
.I5(sgf_result_o0__1_carry_i_12__7_n_0),
.O(sgf_result_o0__1_carry__0_i_4__9_n_0));
LUT6 #(
.INIT(64'h9996999699966669))
sgf_result_o0__1_carry__0_i_5__9
(.I0(sgf_result_o0__1_carry__0_i_2__7_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__8_n_0),
.I2(sgf_result_o0__1_carry_i_13__6_n_0),
.I3(sgf_result_o0__1_carry_i_15__3_n_0),
.I4(sgf_result_o0__1_carry_i_8__6_n_0),
.I5(sgf_result_o0__1_carry_i_12__7_n_0),
.O(sgf_result_o0__1_carry__0_i_5__9_n_0));
LUT6 #(
.INIT(64'h1EE1E11EE11E1EE1))
sgf_result_o0__1_carry__0_i_6__7
(.I0(sgf_result_o0__1_carry_i_15__3_n_0),
.I1(sgf_result_o0__1_carry_i_9__12_n_0),
.I2(sgf_result_o0__1_carry__0_i_7__4_n_0),
.I3(sgf_result_o0__1_carry__0_i_9__9_n_0),
.I4(sgf_result_o0__1_carry__0_i_2__7_n_0),
.I5(sgf_result_o0__1_carry__0_i_10__0_n_0),
.O(sgf_result_o0__1_carry__0_i_6__7_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_7__4
(.I0(sgf_result_o0__1_carry_i_13__6_n_0),
.I1(sgf_result_o0__1_carry_i_8__6_n_0),
.O(sgf_result_o0__1_carry__0_i_7__4_n_0));
LUT6 #(
.INIT(64'hFFFEFFFEFFFEEEE0))
sgf_result_o0__1_carry__0_i_8__8
(.I0(sgf_result_o0__1_carry_i_12__7_n_0),
.I1(sgf_result_o0__1_carry_i_16__4_n_0),
.I2(sgf_result_o0__1_carry_i_8__6_n_0),
.I3(sgf_result_o0__1_carry_i_13__6_n_0),
.I4(sgf_result_o0__1_carry_i_9__12_n_0),
.I5(sgf_result_o0__1_carry_i_15__3_n_0),
.O(sgf_result_o0__1_carry__0_i_8__8_n_0));
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_9__9
(.I0(\sgf_result_o[15] [0]),
.I1(\sgf_result_o[15] [3]),
.I2(O[3]),
.I3(\sgf_result_o[15] [2]),
.I4(sgf_result_o0__1_carry_i_12__7_n_0),
.O(sgf_result_o0__1_carry__0_i_9__9_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry_i_10__12
(.I0(\sgf_result_o[15] [0]),
.I1(\sgf_result_o[15] [3]),
.I2(O[3]),
.I3(\sgf_result_o[15] [2]),
.I4(sgf_result_o0__1_carry_i_13__6_n_0),
.O(sgf_result_o0__1_carry_i_10__12_n_0));
CARRY4 sgf_result_o0__1_carry_i_11__12
(.CI(sgf_result_o1__0_carry_i_18__1_n_0),
.CO({\sgf_result_o[15]_2 ,sgf_result_o0__1_carry_i_11__12_n_1,sgf_result_o0__1_carry_i_11__12_n_2,sgf_result_o0__1_carry_i_11__12_n_3}),
.CYINIT(1'b0),
.DI(Data_A_i_IBUF[11:8]),
.O(\sgf_result_o[15] ),
.S({sgf_result_o0__1_carry_i_18__0__0_n_0,sgf_result_o0__1_carry_i_19__0__0_n_0,sgf_result_o0__1_carry_i_20_n_0,sgf_result_o0__1_carry_i_21_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_12__0
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[15]),
.O(sgf_result_o0__1_carry_i_12__0_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_12__7
(.I0(\sgf_result_o[15]_0 [0]),
.I1(\sgf_result_o[15]_0 [3]),
.I2(\sgf_result_o[47] [3]),
.I3(\sgf_result_o[15]_0 [2]),
.I4(\sgf_result_o[15]_0 [1]),
.I5(\Data_B_i[12] ),
.O(sgf_result_o0__1_carry_i_12__7_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_13__1
(.I0(Data_B_i_IBUF[2]),
.I1(Data_B_i_IBUF[14]),
.O(sgf_result_o0__1_carry_i_13__1_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_13__6
(.I0(\Data_B_i[12] ),
.I1(\sgf_result_o[15]_0 [1]),
.I2(\sgf_result_o[15]_0 [2]),
.I3(\sgf_result_o[47] [3]),
.I4(\sgf_result_o[15]_0 [3]),
.I5(\sgf_result_o[15]_0 [0]),
.O(sgf_result_o0__1_carry_i_13__6_n_0));
CARRY4 sgf_result_o0__1_carry_i_14__1
(.CI(sgf_result_o1__0_carry_i_13__2_n_0),
.CO({\sgf_result_o[15]_1 ,sgf_result_o0__1_carry_i_14__1_n_1,sgf_result_o0__1_carry_i_14__1_n_2,sgf_result_o0__1_carry_i_14__1_n_3}),
.CYINIT(1'b0),
.DI(Data_B_i_IBUF[11:8]),
.O(\sgf_result_o[15]_0 ),
.S({sgf_result_o0__1_carry_i_23_n_0,sgf_result_o0__1_carry_i_24_n_0,sgf_result_o0__1_carry_i_25_n_0,sgf_result_o0__1_carry_i_26_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_14__2
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[13]),
.O(sgf_result_o0__1_carry_i_14__2_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_15__0
(.I0(Data_B_i_IBUF[0]),
.I1(Data_B_i_IBUF[12]),
.O(sgf_result_o0__1_carry_i_15__0_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_15__3
(.I0(\sgf_result_o[15] [0]),
.I1(\sgf_result_o[15] [3]),
.I2(O[3]),
.I3(\sgf_result_o[15] [2]),
.I4(\sgf_result_o[15] [1]),
.I5(CO),
.O(sgf_result_o0__1_carry_i_15__3_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_16__2
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[15]),
.O(sgf_result_o0__1_carry_i_16__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_16__4
(.I0(\sgf_result_o[15] [2]),
.I1(O[3]),
.I2(\sgf_result_o[15] [3]),
.I3(\sgf_result_o[15] [0]),
.O(sgf_result_o0__1_carry_i_16__4_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_17__1
(.I0(Data_A_i_IBUF[2]),
.I1(Data_A_i_IBUF[14]),
.O(sgf_result_o0__1_carry_i_17__1_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_18__0
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[13]),
.O(sgf_result_o0__1_carry_i_18__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_18__0__0
(.I0(Data_A_i_IBUF[11]),
.I1(Data_A_i_IBUF[23]),
.O(sgf_result_o0__1_carry_i_18__0__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_19__0
(.I0(Data_A_i_IBUF[0]),
.I1(Data_A_i_IBUF[12]),
.O(sgf_result_o0__1_carry_i_19__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_19__0__0
(.I0(Data_A_i_IBUF[10]),
.I1(Data_A_i_IBUF[22]),
.O(sgf_result_o0__1_carry_i_19__0__0_n_0));
LUT6 #(
.INIT(64'hE1E1E1E1E11E1EE1))
sgf_result_o0__1_carry_i_1__9
(.I0(sgf_result_o0__1_carry_i_8__6_n_0),
.I1(sgf_result_o0__1_carry_i_9__12_n_0),
.I2(sgf_result_o0__1_carry_i_10__12_n_0),
.I3(\sgf_result_o[15] [2]),
.I4(O[3]),
.I5(sgf_result_o0__1_carry_i_12__7_n_0),
.O(sgf_result_o0__1_carry_i_1__9_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_20
(.I0(Data_A_i_IBUF[9]),
.I1(Data_A_i_IBUF[21]),
.O(sgf_result_o0__1_carry_i_20_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_21
(.I0(Data_A_i_IBUF[8]),
.I1(Data_A_i_IBUF[20]),
.O(sgf_result_o0__1_carry_i_21_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_23
(.I0(Data_B_i_IBUF[11]),
.I1(Data_B_i_IBUF[23]),
.O(sgf_result_o0__1_carry_i_23_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_24
(.I0(Data_B_i_IBUF[10]),
.I1(Data_B_i_IBUF[22]),
.O(sgf_result_o0__1_carry_i_24_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_25
(.I0(Data_B_i_IBUF[9]),
.I1(Data_B_i_IBUF[21]),
.O(sgf_result_o0__1_carry_i_25_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_26
(.I0(Data_B_i_IBUF[8]),
.I1(Data_B_i_IBUF[20]),
.O(sgf_result_o0__1_carry_i_26_n_0));
LUT6 #(
.INIT(64'h0906060609F9F906))
sgf_result_o0__1_carry_i_2__9
(.I0(\sgf_result_o[15] [3]),
.I1(\sgf_result_o[15] [0]),
.I2(sgf_result_o0__1_carry_i_9__12_n_0),
.I3(O[3]),
.I4(\sgf_result_o[15] [2]),
.I5(sgf_result_o0__1_carry_i_13__6_n_0),
.O(sgf_result_o0__1_carry_i_2__9_n_0));
LUT6 #(
.INIT(64'h6006066006600660))
sgf_result_o0__1_carry_i_3__9
(.I0(\sgf_result_o[15] [2]),
.I1(O[3]),
.I2(\sgf_result_o[15]_0 [0]),
.I3(\sgf_result_o[15]_0 [3]),
.I4(\sgf_result_o[47] [3]),
.I5(\sgf_result_o[15]_0 [2]),
.O(sgf_result_o0__1_carry_i_3__9_n_0));
LUT6 #(
.INIT(64'h6A6A6A6A6A95956A))
sgf_result_o0__1_carry_i_4__9
(.I0(sgf_result_o0__1_carry_i_1__9_n_0),
.I1(sgf_result_o0__1_carry_i_10__12_n_0),
.I2(sgf_result_o0__1_carry_i_3__9_n_0),
.I3(\sgf_result_o[15]_0 [2]),
.I4(\sgf_result_o[47] [3]),
.I5(sgf_result_o0__1_carry_i_15__3_n_0),
.O(sgf_result_o0__1_carry_i_4__9_n_0));
LUT4 #(
.INIT(16'hA99A))
sgf_result_o0__1_carry_i_5__9
(.I0(sgf_result_o0__1_carry_i_2__9_n_0),
.I1(sgf_result_o0__1_carry_i_8__6_n_0),
.I2(\sgf_result_o[47] [3]),
.I3(\sgf_result_o[15]_0 [2]),
.O(sgf_result_o0__1_carry_i_5__9_n_0));
LUT6 #(
.INIT(64'h141414EB14EB1414))
sgf_result_o0__1_carry_i_6__6
(.I0(sgf_result_o0__1_carry_i_16__4_n_0),
.I1(\sgf_result_o[47] [3]),
.I2(\sgf_result_o[15]_0 [2]),
.I3(sgf_result_o0__1_carry_i_9__12_n_0),
.I4(O[3]),
.I5(\sgf_result_o[15] [2]),
.O(sgf_result_o0__1_carry_i_6__6_n_0));
LUT4 #(
.INIT(16'h0660))
sgf_result_o0__1_carry_i_7__9
(.I0(\sgf_result_o[15] [2]),
.I1(O[3]),
.I2(\sgf_result_o[15]_0 [2]),
.I3(\sgf_result_o[47] [3]),
.O(sgf_result_o0__1_carry_i_7__9_n_0));
CARRY4 sgf_result_o0__1_carry_i_8__10
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_8__10_n_0,sgf_result_o0__1_carry_i_8__10_n_1,sgf_result_o0__1_carry_i_8__10_n_2,sgf_result_o0__1_carry_i_8__10_n_3}),
.CYINIT(1'b0),
.DI(Data_B_i_IBUF[3:0]),
.O(\sgf_result_o[47]_1 ),
.S({sgf_result_o0__1_carry_i_12__0_n_0,sgf_result_o0__1_carry_i_13__1_n_0,sgf_result_o0__1_carry_i_14__2_n_0,sgf_result_o0__1_carry_i_15__0_n_0}));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_8__6
(.I0(CO),
.I1(\sgf_result_o[15] [1]),
.I2(\sgf_result_o[15] [2]),
.I3(O[3]),
.I4(\sgf_result_o[15] [3]),
.I5(\sgf_result_o[15] [0]),
.O(sgf_result_o0__1_carry_i_8__6_n_0));
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_9__12
(.I0(\sgf_result_o[15]_0 [2]),
.I1(\sgf_result_o[47] [3]),
.I2(\sgf_result_o[15]_0 [3]),
.I3(\sgf_result_o[15]_0 [0]),
.O(sgf_result_o0__1_carry_i_9__12_n_0));
CARRY4 sgf_result_o0__1_carry_i_9__5
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_9__5_n_0,sgf_result_o0__1_carry_i_9__5_n_1,sgf_result_o0__1_carry_i_9__5_n_2,sgf_result_o0__1_carry_i_9__5_n_3}),
.CYINIT(1'b0),
.DI(Data_A_i_IBUF[3:0]),
.O(\sgf_result_o[47]_2 ),
.S({sgf_result_o0__1_carry_i_16__2_n_0,sgf_result_o0__1_carry_i_17__1_n_0,sgf_result_o0__1_carry_i_18__0_n_0,sgf_result_o0__1_carry_i_19__0_n_0}));
CARRY4 sgf_result_o1__0_carry_i_13__2
(.CI(sgf_result_o0__1_carry_i_8__10_n_0),
.CO({sgf_result_o1__0_carry_i_13__2_n_0,sgf_result_o1__0_carry_i_13__2_n_1,sgf_result_o1__0_carry_i_13__2_n_2,sgf_result_o1__0_carry_i_13__2_n_3}),
.CYINIT(1'b0),
.DI(Data_B_i_IBUF[7:4]),
.O(\sgf_result_o[47] ),
.S({sgf_result_o1__0_carry_i_20_n_0,sgf_result_o1__0_carry_i_21_n_0,sgf_result_o1__0_carry_i_22_n_0,sgf_result_o1__0_carry_i_23_n_0}));
CARRY4 sgf_result_o1__0_carry_i_18__1
(.CI(sgf_result_o0__1_carry_i_9__5_n_0),
.CO({sgf_result_o1__0_carry_i_18__1_n_0,sgf_result_o1__0_carry_i_18__1_n_1,sgf_result_o1__0_carry_i_18__1_n_2,sgf_result_o1__0_carry_i_18__1_n_3}),
.CYINIT(1'b0),
.DI(Data_A_i_IBUF[7:4]),
.O(O),
.S({sgf_result_o1__0_carry_i_25_n_0,sgf_result_o1__0_carry_i_26_n_0,sgf_result_o1__0_carry_i_27_n_0,sgf_result_o1__0_carry_i_28_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_20
(.I0(Data_B_i_IBUF[7]),
.I1(Data_B_i_IBUF[19]),
.O(sgf_result_o1__0_carry_i_20_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_21
(.I0(Data_B_i_IBUF[6]),
.I1(Data_B_i_IBUF[18]),
.O(sgf_result_o1__0_carry_i_21_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_22
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[17]),
.O(sgf_result_o1__0_carry_i_22_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_23
(.I0(Data_B_i_IBUF[4]),
.I1(Data_B_i_IBUF[16]),
.O(sgf_result_o1__0_carry_i_23_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_25
(.I0(Data_A_i_IBUF[7]),
.I1(Data_A_i_IBUF[19]),
.O(sgf_result_o1__0_carry_i_25_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_26
(.I0(Data_A_i_IBUF[6]),
.I1(Data_A_i_IBUF[18]),
.O(sgf_result_o1__0_carry_i_26_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_27
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[17]),
.O(sgf_result_o1__0_carry_i_27_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_28
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[16]),
.O(sgf_result_o1__0_carry_i_28_n_0));
LUT2 #(
.INIT(4'h9))
sgf_result_o1__35_carry_i_10__0
(.I0(\EVEN1.middle_n_2 ),
.I1(S_B0__0_carry_i_12__3_n_0),
.O(sgf_result_o1__35_carry_i_10__0_n_0));
LUT2 #(
.INIT(4'h9))
sgf_result_o1__35_carry_i_11
(.I0(\EVEN1.middle_n_1 ),
.I1(S_B0__0_carry_i_11__3_n_0),
.O(sgf_result_o1__35_carry_i_11_n_0));
LUT2 #(
.INIT(4'h9))
sgf_result_o1__35_carry_i_9__1
(.I0(\EVEN1.middle_n_0 ),
.I1(S_B0__0_carry__0_i_9__3_n_0),
.O(sgf_result_o1__35_carry_i_9__1_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized36
(O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
DI,
S,
\Data_A_i[12] ,
\Data_A_i[12]_0 ,
\Data_B_i[12] ,
\Data_A_i[12]_1 ,
\Data_B_i[12]_0 ,
\Data_A_i[12]_2 ,
\Data_A_i[12]_3 ,
\Data_A_i[12]_4 ,
\Data_B_i[12]_1 ,
\Data_A_i[12]_5 ,
\Data_B_i[12]_2 ,
\Data_A_i[12]_6 ,
\Data_B_i[12]_3 ,
\Data_A_i[12]_7 ,
\Data_A_i[12]_8 ,
\Data_A_i[12]_9 ,
\Data_A_i[12]_10 ,
\Data_A_i[12]_11 ,
\Data_B_i[12]_4 );
output [1:0]O;
output [0:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [1:0]\sgf_result_o[47]_2 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_A_i[12] ;
input [2:0]\Data_A_i[12]_0 ;
input [1:0]\Data_B_i[12] ;
input [1:0]\Data_A_i[12]_1 ;
input \Data_B_i[12]_0 ;
input \Data_A_i[12]_2 ;
input \Data_A_i[12]_3 ;
input \Data_A_i[12]_4 ;
input \Data_B_i[12]_1 ;
input \Data_A_i[12]_5 ;
input \Data_B_i[12]_2 ;
input \Data_A_i[12]_6 ;
input \Data_B_i[12]_3 ;
input \Data_A_i[12]_7 ;
input [2:0]\Data_A_i[12]_8 ;
input [0:0]\Data_A_i[12]_9 ;
input [0:0]\Data_A_i[12]_10 ;
input [0:0]\Data_A_i[12]_11 ;
input [0:0]\Data_B_i[12]_4 ;
wire [2:0]DI;
wire [2:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire [1:0]\Data_A_i[12]_1 ;
wire [0:0]\Data_A_i[12]_10 ;
wire [0:0]\Data_A_i[12]_11 ;
wire \Data_A_i[12]_2 ;
wire \Data_A_i[12]_3 ;
wire \Data_A_i[12]_4 ;
wire \Data_A_i[12]_5 ;
wire \Data_A_i[12]_6 ;
wire \Data_A_i[12]_7 ;
wire [2:0]\Data_A_i[12]_8 ;
wire [0:0]\Data_A_i[12]_9 ;
wire [1:0]\Data_B_i[12] ;
wire \Data_B_i[12]_0 ;
wire \Data_B_i[12]_1 ;
wire \Data_B_i[12]_2 ;
wire \Data_B_i[12]_3 ;
wire [0:0]\Data_B_i[12]_4 ;
wire [1:0]O;
wire [3:0]S;
wire S_B0__0_carry__0_i_1__3_n_0;
wire S_B0__0_carry__0_i_2__3_n_0;
wire S_B0__0_carry__0_i_4__3_n_0;
wire S_B0__0_carry__0_i_5__3_n_0;
wire S_B0__0_carry__0_i_6__3_n_0;
wire S_B0__0_carry__0_n_1;
wire S_B0__0_carry__0_n_2;
wire S_B0__0_carry__0_n_3;
wire S_B0__0_carry__0_n_4;
wire S_B0__0_carry__0_n_6;
wire S_B0__0_carry__0_n_7;
wire S_B0__0_carry_i_1__3_n_0;
wire S_B0__0_carry_i_2__3_n_0;
wire S_B0__0_carry_i_3__3_n_0;
wire S_B0__0_carry_i_4__3_n_0;
wire S_B0__0_carry_i_5__3_n_0;
wire S_B0__0_carry_i_6__3_n_0;
wire S_B0__0_carry_i_7__3_n_0;
wire S_B0__0_carry_n_0;
wire S_B0__0_carry_n_1;
wire S_B0__0_carry_n_2;
wire S_B0__0_carry_n_3;
wire S_B0__0_carry_n_4;
wire S_B0__0_carry_n_6;
wire sgf_result_o0__1_carry__0_n_1;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_4;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire sgf_result_o1__35_carry_i_10_n_0;
wire sgf_result_o1__35_carry_i_11__0__0_n_0;
wire sgf_result_o1__35_carry_i_11__0_n_0;
wire sgf_result_o1__35_carry_i_12_n_0;
wire sgf_result_o1__35_carry_i_13_n_0;
wire sgf_result_o1__35_carry_i_8__1_n_0;
wire sgf_result_o1__35_carry_i_8__1_n_1;
wire sgf_result_o1__35_carry_i_8__1_n_2;
wire sgf_result_o1__35_carry_i_8__1_n_3;
wire sgf_result_o1__35_carry_i_9__0_n_3;
wire sgf_result_o1__35_carry_i_9_n_0;
wire sgf_result_o1__35_carry_i_9_n_1;
wire sgf_result_o1__35_carry_i_9_n_2;
wire sgf_result_o1__35_carry_i_9_n_3;
wire [0:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [1:0]\sgf_result_o[47]_2 ;
wire [3:3]NLW_S_B0__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:1]NLW_sgf_result_o1__35_carry_i_9__0_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__35_carry_i_9__0_O_UNCONNECTED;
CARRY4 S_B0__0_carry
(.CI(1'b0),
.CO({S_B0__0_carry_n_0,S_B0__0_carry_n_1,S_B0__0_carry_n_2,S_B0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({S_B0__0_carry_i_1__3_n_0,S_B0__0_carry_i_2__3_n_0,S_B0__0_carry_i_3__3_n_0,1'b1}),
.O({S_B0__0_carry_n_4,O[1],S_B0__0_carry_n_6,O[0]}),
.S({S_B0__0_carry_i_4__3_n_0,S_B0__0_carry_i_5__3_n_0,S_B0__0_carry_i_6__3_n_0,S_B0__0_carry_i_7__3_n_0}));
CARRY4 S_B0__0_carry__0
(.CI(S_B0__0_carry_n_0),
.CO({NLW_S_B0__0_carry__0_CO_UNCONNECTED[3],S_B0__0_carry__0_n_1,S_B0__0_carry__0_n_2,S_B0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,sgf_result_o0__1_carry__0_n_5,S_B0__0_carry__0_i_1__3_n_0,S_B0__0_carry__0_i_2__3_n_0}),
.O({S_B0__0_carry__0_n_4,\sgf_result_o[47] ,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.S({sgf_result_o0__1_carry__0_n_4,S_B0__0_carry__0_i_4__3_n_0,S_B0__0_carry__0_i_5__3_n_0,S_B0__0_carry__0_i_6__3_n_0}));
(* HLUTNM = "lutpair47" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry__0_i_1__3
(.I0(\Data_B_i[12]_3 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[12]_7 ),
.O(S_B0__0_carry__0_i_1__3_n_0));
(* HLUTNM = "lutpair46" *)
LUT3 #(
.INIT(8'hE8))
S_B0__0_carry__0_i_2__3
(.I0(\Data_B_i[12]_2 ),
.I1(\Data_A_i[12]_6 ),
.I2(sgf_result_o0__1_carry_n_4),
.O(S_B0__0_carry__0_i_2__3_n_0));
LUT4 #(
.INIT(16'h4DB2))
S_B0__0_carry__0_i_4__3
(.I0(\Data_A_i[12]_3 ),
.I1(\Data_A_i[12]_4 ),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(sgf_result_o0__1_carry__0_n_5),
.O(S_B0__0_carry__0_i_4__3_n_0));
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry__0_i_5__3
(.I0(S_B0__0_carry__0_i_1__3_n_0),
.I1(\Data_A_i[12]_3 ),
.I2(\Data_A_i[12]_4 ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(S_B0__0_carry__0_i_5__3_n_0));
(* HLUTNM = "lutpair47" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry__0_i_6__3
(.I0(\Data_B_i[12]_3 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[12]_7 ),
.I3(S_B0__0_carry__0_i_2__3_n_0),
.O(S_B0__0_carry__0_i_6__3_n_0));
(* HLUTNM = "lutpair45" *)
LUT3 #(
.INIT(8'h71))
S_B0__0_carry_i_1__3
(.I0(\Data_B_i[12]_1 ),
.I1(\Data_A_i[12]_5 ),
.I2(sgf_result_o0__1_carry_n_5),
.O(S_B0__0_carry_i_1__3_n_0));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__0_carry_i_2__3
(.I0(\Data_B_i[12] [1]),
.I1(\Data_A_i[12]_1 [0]),
.I2(\Data_A_i[12]_1 [1]),
.I3(\Data_B_i[12] [0]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[12]_0 ),
.O(S_B0__0_carry_i_2__3_n_0));
(* HLUTNM = "lutpair87" *)
LUT5 #(
.INIT(32'h2ABFBFBF))
S_B0__0_carry_i_3__3
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[12]_11 ),
.I2(\Data_B_i[12]_4 ),
.I3(\Data_A_i[12]_1 [0]),
.I4(\Data_B_i[12] [0]),
.O(S_B0__0_carry_i_3__3_n_0));
(* HLUTNM = "lutpair46" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_4__3
(.I0(\Data_B_i[12]_2 ),
.I1(\Data_A_i[12]_6 ),
.I2(sgf_result_o0__1_carry_n_4),
.I3(S_B0__0_carry_i_1__3_n_0),
.O(S_B0__0_carry_i_4__3_n_0));
(* HLUTNM = "lutpair45" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_5__3
(.I0(\Data_B_i[12]_1 ),
.I1(\Data_A_i[12]_5 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(S_B0__0_carry_i_2__3_n_0),
.O(S_B0__0_carry_i_5__3_n_0));
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_6__3
(.I0(S_B0__0_carry_i_3__3_n_0),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[12]_0 ),
.I3(\Data_A_i[12]_2 ),
.O(S_B0__0_carry_i_6__3_n_0));
(* HLUTNM = "lutpair87" *)
LUT5 #(
.INIT(32'h6A959595))
S_B0__0_carry_i_7__3
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[12]_11 ),
.I2(\Data_B_i[12]_4 ),
.I3(\Data_A_i[12]_1 [0]),
.I4(\Data_B_i[12] [0]),
.O(S_B0__0_carry_i_7__3_n_0));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_1,sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[12] }),
.O({sgf_result_o0__1_carry__0_n_4,sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[12]_0 }));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__35_carry_i_10
(.I0(S_B0__0_carry_n_6),
.I1(\Data_B_i[12]_3 ),
.O(sgf_result_o1__35_carry_i_10_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__35_carry_i_11__0
(.I0(S_B0__0_carry__0_n_6),
.I1(\Data_A_i[12]_5 ),
.O(sgf_result_o1__35_carry_i_11__0_n_0));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__35_carry_i_11__0__0
(.I0(S_B0__0_carry__0_n_4),
.I1(\Data_A_i[12]_7 ),
.O(sgf_result_o1__35_carry_i_11__0__0_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
sgf_result_o1__35_carry_i_12
(.I0(S_B0__0_carry__0_n_7),
.I1(\Data_B_i[12] [0]),
.I2(\Data_A_i[12]_1 [1]),
.I3(\Data_A_i[12]_1 [0]),
.I4(\Data_B_i[12] [1]),
.O(sgf_result_o1__35_carry_i_12_n_0));
LUT3 #(
.INIT(8'h6A))
sgf_result_o1__35_carry_i_13
(.I0(S_B0__0_carry_n_4),
.I1(\Data_A_i[12]_1 [0]),
.I2(\Data_B_i[12] [0]),
.O(sgf_result_o1__35_carry_i_13_n_0));
CARRY4 sgf_result_o1__35_carry_i_8__1
(.CI(1'b0),
.CO({sgf_result_o1__35_carry_i_8__1_n_0,sgf_result_o1__35_carry_i_8__1_n_1,sgf_result_o1__35_carry_i_8__1_n_2,sgf_result_o1__35_carry_i_8__1_n_3}),
.CYINIT(1'b0),
.DI({O[1],S_B0__0_carry_n_6,O[0],1'b0}),
.O(\sgf_result_o[47]_0 ),
.S({\Data_A_i[12]_8 [2],sgf_result_o1__35_carry_i_10_n_0,\Data_A_i[12]_8 [1:0]}));
CARRY4 sgf_result_o1__35_carry_i_9
(.CI(sgf_result_o1__35_carry_i_8__1_n_0),
.CO({sgf_result_o1__35_carry_i_9_n_0,sgf_result_o1__35_carry_i_9_n_1,sgf_result_o1__35_carry_i_9_n_2,sgf_result_o1__35_carry_i_9_n_3}),
.CYINIT(1'b0),
.DI({\sgf_result_o[47] ,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7,S_B0__0_carry_n_4}),
.O(\sgf_result_o[47]_1 ),
.S({\Data_A_i[12]_9 ,sgf_result_o1__35_carry_i_11__0_n_0,sgf_result_o1__35_carry_i_12_n_0,sgf_result_o1__35_carry_i_13_n_0}));
CARRY4 sgf_result_o1__35_carry_i_9__0
(.CI(sgf_result_o1__35_carry_i_9_n_0),
.CO({NLW_sgf_result_o1__35_carry_i_9__0_CO_UNCONNECTED[3:1],sgf_result_o1__35_carry_i_9__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,S_B0__0_carry__0_n_4}),
.O({NLW_sgf_result_o1__35_carry_i_9__0_O_UNCONNECTED[3:2],\sgf_result_o[47]_2 }),
.S({1'b0,1'b0,\Data_A_i[12]_10 ,sgf_result_o1__35_carry_i_11__0__0_n_0}));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized37
(\sgf_result_o[47] ,
DI,
S,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12] ,
\Data_B_i[12]_0 ,
\Data_A_i[12] ,
O,
\Data_B_i[12]_1 ,
Q_middle_temp__5,
\Data_A_i[12]_0 ,
sgf_result_o1,
sgf_result_o_OBUF,
\Data_B_i[12]_2 ,
\Data_A_i[12]_1 ,
\Data_B_i[12]_3 ,
\Data_A_i[17] ,
\Data_A_i[23] ,
\Data_B_i[12]_4 ,
\Data_B_i[12]_5 ,
\Data_A_i[12]_2 ,
\Data_B_i[17] ,
\Data_B_i[17]_0 ,
\Data_A_i[14] ,
\Data_A_i[14]_0 ,
\Data_A_i[13] ,
\Data_A_i[13]_0 ,
\Data_A_i[13]_1 ,
\Data_A_i[13]_2 ,
\Data_A_i[13]_3 ,
\Data_A_i[13]_4 ,
\Data_A_i[14]_1 ,
\Data_A_i[11] ,
\Data_A_i[14]_2 ,
\Data_A_i[14]_3 ,
\Data_A_i[14]_4 ,
\Data_A_i[14]_5 ,
\Data_A_i[11]_0 ,
\Data_A_i[2] ,
\Data_A_i[2]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[23]_0 ,
\Data_A_i[14]_6 );
output [2:0]\sgf_result_o[47] ;
output [1:0]DI;
output [3:0]S;
output [3:0]\sgf_result_o[47]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [0:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [18:0]\sgf_result_o[47]_5 ;
output [36:0]\sgf_result_o[47]_6 ;
input [3:0]Data_B_i_IBUF;
input [3:0]Data_A_i_IBUF;
input \Data_B_i[12] ;
input [3:0]\Data_B_i[12]_0 ;
input [3:0]\Data_A_i[12] ;
input [2:0]O;
input [2:0]\Data_B_i[12]_1 ;
input [11:0]Q_middle_temp__5;
input [1:0]\Data_A_i[12]_0 ;
input [15:0]sgf_result_o1;
input [5:0]sgf_result_o_OBUF;
input [2:0]\Data_B_i[12]_2 ;
input [0:0]\Data_A_i[12]_1 ;
input [3:0]\Data_B_i[12]_3 ;
input [2:0]\Data_A_i[17] ;
input [3:0]\Data_A_i[23] ;
input [3:0]\Data_B_i[12]_4 ;
input [3:0]\Data_B_i[12]_5 ;
input [3:0]\Data_A_i[12]_2 ;
input [0:0]\Data_B_i[17] ;
input [0:0]\Data_B_i[17]_0 ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[14]_0 ;
input [3:0]\Data_A_i[13] ;
input [3:0]\Data_A_i[13]_0 ;
input [3:0]\Data_A_i[13]_1 ;
input [3:0]\Data_A_i[13]_2 ;
input [3:0]\Data_A_i[13]_3 ;
input [3:0]\Data_A_i[13]_4 ;
input [0:0]\Data_A_i[14]_1 ;
input [0:0]\Data_A_i[11] ;
input [0:0]\Data_A_i[14]_2 ;
input [3:0]\Data_A_i[14]_3 ;
input [3:0]\Data_A_i[14]_4 ;
input [0:0]\Data_A_i[14]_5 ;
input [0:0]\Data_A_i[11]_0 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[2]_0 ;
input [2:0]\Data_A_i[2]_1 ;
input [3:0]\Data_A_i[23]_0 ;
input [0:0]\Data_A_i[14]_6 ;
wire [1:0]DI;
wire [0:0]\Data_A_i[11] ;
wire [0:0]\Data_A_i[11]_0 ;
wire [3:0]\Data_A_i[12] ;
wire [1:0]\Data_A_i[12]_0 ;
wire [0:0]\Data_A_i[12]_1 ;
wire [3:0]\Data_A_i[12]_2 ;
wire [3:0]\Data_A_i[13] ;
wire [3:0]\Data_A_i[13]_0 ;
wire [3:0]\Data_A_i[13]_1 ;
wire [3:0]\Data_A_i[13]_2 ;
wire [3:0]\Data_A_i[13]_3 ;
wire [3:0]\Data_A_i[13]_4 ;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [0:0]\Data_A_i[14]_1 ;
wire [0:0]\Data_A_i[14]_2 ;
wire [3:0]\Data_A_i[14]_3 ;
wire [3:0]\Data_A_i[14]_4 ;
wire [0:0]\Data_A_i[14]_5 ;
wire [0:0]\Data_A_i[14]_6 ;
wire [2:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire [2:0]\Data_A_i[2]_1 ;
wire [3:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire [3:0]\Data_B_i[12]_0 ;
wire [2:0]\Data_B_i[12]_1 ;
wire [2:0]\Data_B_i[12]_2 ;
wire [3:0]\Data_B_i[12]_3 ;
wire [3:0]\Data_B_i[12]_4 ;
wire [3:0]\Data_B_i[12]_5 ;
wire [0:0]\Data_B_i[17] ;
wire [0:0]\Data_B_i[17]_0 ;
wire [3:0]Data_B_i_IBUF;
wire [2:0]O;
wire \ODD1.middle_n_0 ;
wire \ODD1.middle_n_1 ;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_11 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_15 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_2 ;
wire \ODD1.middle_n_20 ;
wire \ODD1.middle_n_21 ;
wire \ODD1.middle_n_3 ;
wire \ODD1.middle_n_4 ;
wire \ODD1.middle_n_5 ;
wire \ODD1.middle_n_6 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_8 ;
wire \ODD1.middle_n_9 ;
wire \ODD1.right_lower_n_10 ;
wire \ODD1.right_lower_n_11 ;
wire \ODD1.right_lower_n_12 ;
wire \ODD1.right_lower_n_13 ;
wire \ODD1.right_lower_n_14 ;
wire \ODD1.right_lower_n_15 ;
wire \ODD1.right_lower_n_16 ;
wire \ODD1.right_lower_n_17 ;
wire \ODD1.right_lower_n_18 ;
wire \ODD1.right_lower_n_19 ;
wire \ODD1.right_lower_n_20 ;
wire \ODD1.right_lower_n_21 ;
wire \ODD1.right_lower_n_22 ;
wire \ODD1.right_lower_n_23 ;
wire \ODD1.right_lower_n_3 ;
wire \ODD1.right_lower_n_4 ;
wire \ODD1.right_lower_n_5 ;
wire \ODD1.right_lower_n_6 ;
wire \ODD1.right_lower_n_7 ;
wire \ODD1.right_lower_n_8 ;
wire \ODD1.right_lower_n_9 ;
wire [9:2]Q_middle_temp__3;
wire [11:0]Q_middle_temp__5;
wire [25:25]Q_middle_temp__6;
wire [3:0]S;
wire sgf_result_o0__1_carry__0_i_1__7_n_0;
wire sgf_result_o0__1_carry__0_i_2__6_n_0;
wire sgf_result_o0__1_carry__0_i_3__7_n_0;
wire sgf_result_o0__1_carry__0_i_4__7_n_0;
wire sgf_result_o0__1_carry__0_i_5__8_n_0;
wire sgf_result_o0__1_carry__0_i_6__6_n_0;
wire sgf_result_o0__1_carry__0_i_7__3_n_0;
wire sgf_result_o0__1_carry__0_i_8__6_n_0;
wire sgf_result_o0__1_carry__0_i_9__3_n_0;
wire sgf_result_o0__1_carry_i_10__2_n_0;
wire sgf_result_o0__1_carry_i_11__7_n_0;
wire sgf_result_o0__1_carry_i_1__7_n_0;
wire sgf_result_o0__1_carry_i_2__7_n_0;
wire sgf_result_o0__1_carry_i_3__7_n_0;
wire sgf_result_o0__1_carry_i_4__7_n_0;
wire sgf_result_o0__1_carry_i_5__7_n_0;
wire sgf_result_o0__1_carry_i_6__5_n_0;
wire sgf_result_o0__1_carry_i_7__7_n_0;
wire sgf_result_o0_carry__0_i_1_n_0;
wire sgf_result_o0_carry__0_i_2_n_0;
wire sgf_result_o0_carry__0_i_3_n_0;
wire sgf_result_o0_carry__0_i_5_n_0;
wire sgf_result_o0_carry__0_n_0;
wire sgf_result_o0_carry__0_n_1;
wire sgf_result_o0_carry__0_n_2;
wire sgf_result_o0_carry__0_n_3;
wire sgf_result_o0_carry__0_n_4;
wire sgf_result_o0_carry__0_n_5;
wire sgf_result_o0_carry__0_n_6;
wire sgf_result_o0_carry__0_n_7;
wire sgf_result_o0_carry__1_i_1_n_0;
wire sgf_result_o0_carry__1_i_2_n_0;
wire sgf_result_o0_carry__1_i_3_n_0;
wire sgf_result_o0_carry__1_n_2;
wire sgf_result_o0_carry__1_n_3;
wire sgf_result_o0_carry__1_n_5;
wire sgf_result_o0_carry__1_n_6;
wire sgf_result_o0_carry__1_n_7;
wire sgf_result_o0_carry_n_0;
wire sgf_result_o0_carry_n_1;
wire sgf_result_o0_carry_n_2;
wire sgf_result_o0_carry_n_3;
wire sgf_result_o0_carry_n_4;
wire sgf_result_o0_carry_n_5;
wire sgf_result_o0_carry_n_6;
wire sgf_result_o0_carry_n_7;
wire [15:0]sgf_result_o1;
wire sgf_result_o1__0_carry__0_i_6__1_n_0;
wire sgf_result_o1__0_carry__0_i_7__1_n_0;
wire sgf_result_o1__0_carry_i_10__1_n_0;
wire sgf_result_o1__0_carry_i_11__1_n_0;
wire sgf_result_o1__0_carry_i_14__1_n_0;
wire sgf_result_o1__0_carry_i_15__1_n_0;
wire sgf_result_o1__0_carry_i_16__1_n_0;
wire sgf_result_o1__0_carry_i_17__1_n_0;
wire sgf_result_o1__0_carry_i_19__1_n_0;
wire sgf_result_o1__0_carry_i_24_n_0;
wire sgf_result_o1__0_carry_i_8__1_n_0;
wire sgf_result_o1__0_carry_i_9__1_n_0;
wire sgf_result_o1__21_carry__0_i_10__1_n_0;
wire sgf_result_o1__21_carry__0_i_9__1_n_0;
wire sgf_result_o1__21_carry__0_n_0;
wire sgf_result_o1__21_carry__0_n_1;
wire sgf_result_o1__21_carry__0_n_2;
wire sgf_result_o1__21_carry__0_n_3;
wire sgf_result_o1__21_carry__0_n_4;
wire sgf_result_o1__21_carry__0_n_5;
wire sgf_result_o1__21_carry__0_n_6;
wire sgf_result_o1__21_carry__0_n_7;
wire sgf_result_o1__21_carry__1_i_1__1_n_0;
wire sgf_result_o1__21_carry__1_n_3;
wire sgf_result_o1__21_carry__1_n_6;
wire sgf_result_o1__21_carry__1_n_7;
wire sgf_result_o1__21_carry_i_10__1_n_0;
wire sgf_result_o1__21_carry_i_8__1_n_0;
wire sgf_result_o1__21_carry_i_9__1_n_0;
wire sgf_result_o1__21_carry_n_0;
wire sgf_result_o1__21_carry_n_1;
wire sgf_result_o1__21_carry_n_2;
wire sgf_result_o1__21_carry_n_3;
wire sgf_result_o1__21_carry_n_4;
wire sgf_result_o1__21_carry_n_5;
wire sgf_result_o1__21_carry_n_6;
wire sgf_result_o1__21_carry_n_7;
wire sgf_result_o1_carry__0_n_1;
wire sgf_result_o1_carry__0_n_2;
wire sgf_result_o1_carry__0_n_3;
wire sgf_result_o1_carry_i_4__1_n_0;
wire sgf_result_o1_carry_i_5__1_n_0;
wire sgf_result_o1_carry_n_0;
wire sgf_result_o1_carry_n_1;
wire sgf_result_o1_carry_n_2;
wire sgf_result_o1_carry_n_3;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [0:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [18:0]\sgf_result_o[47]_5 ;
wire [36:0]\sgf_result_o[47]_6 ;
wire [5:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[22]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_14_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_8_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_9_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_16_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_16_n_1 ;
wire \sgf_result_o_OBUF[26]_inst_i_16_n_2 ;
wire \sgf_result_o_OBUF[26]_inst_i_16_n_3 ;
wire \sgf_result_o_OBUF[26]_inst_i_20_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_21_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_22_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_15_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_15_n_1 ;
wire \sgf_result_o_OBUF[30]_inst_i_15_n_2 ;
wire \sgf_result_o_OBUF[30]_inst_i_15_n_3 ;
wire \sgf_result_o_OBUF[30]_inst_i_16_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_17_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_18_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_19_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_16_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_16_n_1 ;
wire \sgf_result_o_OBUF[34]_inst_i_16_n_2 ;
wire \sgf_result_o_OBUF[34]_inst_i_16_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_20_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_20_n_1 ;
wire \sgf_result_o_OBUF[38]_inst_i_20_n_2 ;
wire \sgf_result_o_OBUF[38]_inst_i_20_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_8_n_1 ;
wire \sgf_result_o_OBUF[38]_inst_i_8_n_2 ;
wire \sgf_result_o_OBUF[38]_inst_i_8_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_9_n_0 ;
wire [3:2]NLW_sgf_result_o0_carry__1_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0_carry__1_O_UNCONNECTED;
wire [3:1]NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1_carry__0_CO_UNCONNECTED;
wire [3:3]\NLW_sgf_result_o_OBUF[38]_inst_i_8_CO_UNCONNECTED ;
Recursive_KOA__parameterized40 \ODD1.middle
(.CO(\ODD1.right_lower_n_3 ),
.\Data_A_i[12] (\Data_A_i[12] ),
.\Data_A_i[12]_0 (O),
.\Data_A_i[12]_1 (Q_middle_temp__3[8:7]),
.\Data_A_i[16] (sgf_result_o1__0_carry_i_14__1_n_0),
.\Data_A_i[16]_0 (sgf_result_o1__0_carry__0_i_7__1_n_0),
.\Data_A_i[16]_1 (sgf_result_o1__0_carry_i_8__1_n_0),
.\Data_A_i[16]_2 (sgf_result_o1__0_carry_i_9__1_n_0),
.\Data_A_i[16]_3 (sgf_result_o1__0_carry_i_17__1_n_0),
.\Data_A_i[16]_4 (sgf_result_o1__0_carry_i_10__1_n_0),
.\Data_B_i[12] (\Data_B_i[12]_0 ),
.\Data_B_i[12]_0 (\Data_B_i[12]_1 ),
.\Data_B_i[12]_1 (sgf_result_o1__0_carry__0_i_6__1_n_0),
.\Data_B_i[12]_2 (sgf_result_o1__0_carry_i_16__1_n_0),
.\Data_B_i[16] (sgf_result_o1__0_carry_i_15__1_n_0),
.\Data_B_i[16]_0 (sgf_result_o1__0_carry_i_11__1_n_0),
.O({\ODD1.middle_n_0 ,\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 }),
.S({\ODD1.middle_n_14 ,\ODD1.middle_n_15 ,\ODD1.middle_n_16 }),
.\sgf_result_o[47] ({\ODD1.middle_n_4 ,\ODD1.middle_n_5 }),
.\sgf_result_o[47]_0 (\ODD1.middle_n_6 ),
.\sgf_result_o[47]_1 (\ODD1.middle_n_7 ),
.\sgf_result_o[47]_2 (\ODD1.middle_n_8 ),
.\sgf_result_o[47]_3 (\ODD1.middle_n_9 ),
.\sgf_result_o[47]_4 (\ODD1.middle_n_10 ),
.\sgf_result_o[47]_5 (\ODD1.middle_n_11 ),
.\sgf_result_o[47]_6 (\ODD1.middle_n_12 ),
.\sgf_result_o[47]_7 (\ODD1.middle_n_13 ),
.\sgf_result_o[47]_8 ({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }),
.\sgf_result_o[47]_9 (\ODD1.middle_n_21 ));
Recursive_KOA__parameterized39 \ODD1.right_lower
(.CO(\ODD1.right_lower_n_3 ),
.DI({sgf_result_o0__1_carry_i_1__7_n_0,sgf_result_o0__1_carry_i_2__7_n_0,sgf_result_o0__1_carry_i_3__7_n_0}),
.\Data_A_i[11] (\Data_A_i[11] ),
.\Data_A_i[11]_0 (\Data_A_i[11]_0 ),
.\Data_A_i[12] ({sgf_result_o0__1_carry__0_i_4__7_n_0,sgf_result_o0__1_carry__0_i_5__8_n_0,sgf_result_o0__1_carry__0_i_6__6_n_0}),
.\Data_A_i[12]_0 (O[1:0]),
.\Data_A_i[12]_1 (sgf_result_o1__21_carry_i_10__1_n_0),
.\Data_A_i[12]_2 ({sgf_result_o1__21_carry_n_4,sgf_result_o1__21_carry_n_5,sgf_result_o1__21_carry_n_6,sgf_result_o1__21_carry_n_7}),
.\Data_A_i[12]_3 (sgf_result_o1__21_carry_i_8__1_n_0),
.\Data_A_i[12]_4 (sgf_result_o1__21_carry_i_9__1_n_0),
.\Data_A_i[12]_5 (sgf_result_o1__21_carry__0_i_10__1_n_0),
.\Data_A_i[12]_6 (sgf_result_o0_carry_n_7),
.\Data_A_i[12]_7 (\sgf_result_o[47]_5 [18]),
.\Data_A_i[12]_8 ({\sgf_result_o_OBUF[38]_inst_i_9_n_0 ,\Data_A_i[14]_1 }),
.\Data_A_i[12]_9 (\Data_A_i[12] [0]),
.\Data_A_i[13] (\Data_A_i[13] ),
.\Data_A_i[13]_0 (\Data_A_i[13]_0 ),
.\Data_A_i[13]_1 (\Data_A_i[13]_1 ),
.\Data_A_i[13]_2 (\Data_A_i[13]_2 ),
.\Data_A_i[13]_3 (\Data_A_i[13]_3 ),
.\Data_A_i[13]_4 (\Data_A_i[13]_4 ),
.\Data_A_i[14] (\Data_A_i[14] ),
.\Data_A_i[14]_0 (\Data_A_i[14]_0 ),
.\Data_A_i[14]_1 (\Data_A_i[14]_2 ),
.\Data_A_i[14]_2 (\Data_A_i[14]_3 ),
.\Data_A_i[14]_3 (\Data_A_i[14]_4 ),
.\Data_A_i[14]_4 (\Data_A_i[14]_5 ),
.\Data_A_i[14]_5 (\Data_A_i[14]_6 ),
.\Data_A_i[17] (\Data_A_i[17] ),
.\Data_A_i[23] (\Data_A_i[23] ),
.\Data_A_i[23]_0 (\Data_A_i[23]_0 ),
.\Data_A_i[2] (\Data_A_i[2] ),
.\Data_A_i[2]_0 (\Data_A_i[2]_0 ),
.\Data_A_i[2]_1 (\Data_A_i[2]_1 ),
.Data_A_i_IBUF(Data_A_i_IBUF),
.\Data_B_i[12] ({sgf_result_o0__1_carry__0_i_1__7_n_0,sgf_result_o0__1_carry__0_i_2__6_n_0,sgf_result_o0__1_carry__0_i_3__7_n_0}),
.\Data_B_i[12]_0 (\Data_B_i[12] ),
.\Data_B_i[12]_1 (\Data_B_i[12]_1 [1:0]),
.\Data_B_i[12]_2 (sgf_result_o1__21_carry__0_i_9__1_n_0),
.\Data_B_i[12]_3 (\Data_B_i[12]_0 [0]),
.\Data_B_i[16] (sgf_result_o1__0_carry_i_11__1_n_0),
.\Data_B_i[17] ({\Data_B_i[17] ,\sgf_result_o_OBUF[22]_inst_i_8_n_0 ,\sgf_result_o_OBUF[22]_inst_i_9_n_0 ,\sgf_result_o_OBUF[22]_inst_i_10_n_0 }),
.\Data_B_i[17]_0 ({\Data_B_i[17]_0 ,\sgf_result_o_OBUF[22]_inst_i_12_n_0 ,\sgf_result_o_OBUF[22]_inst_i_13_n_0 ,\sgf_result_o_OBUF[22]_inst_i_14_n_0 }),
.Data_B_i_IBUF(Data_B_i_IBUF),
.O(\sgf_result_o[47] ),
.Q_middle_temp__3(Q_middle_temp__3[7:2]),
.S({sgf_result_o0__1_carry_i_4__7_n_0,sgf_result_o0__1_carry_i_5__7_n_0,sgf_result_o0__1_carry_i_6__5_n_0,sgf_result_o0__1_carry_i_7__7_n_0}),
.\sgf_result_o[47] ({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 }),
.\sgf_result_o[47]_0 ({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.\sgf_result_o[47]_1 ({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }),
.\sgf_result_o[47]_2 ({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }),
.\sgf_result_o[47]_3 ({\ODD1.right_lower_n_19 ,\ODD1.right_lower_n_20 ,\ODD1.right_lower_n_21 ,\ODD1.right_lower_n_22 }),
.\sgf_result_o[47]_4 (\ODD1.right_lower_n_23 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_6 ),
.sgf_result_o_OBUF(sgf_result_o_OBUF[2:0]));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_1__7
(.I0(\Data_A_i[12] [3]),
.I1(\Data_B_i[12]_0 [3]),
.O(sgf_result_o0__1_carry__0_i_1__7_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
sgf_result_o0__1_carry__0_i_2__6
(.I0(sgf_result_o0__1_carry_i_10__2_n_0),
.I1(\Data_B_i[12]_0 [1]),
.I2(\Data_A_i[12] [0]),
.I3(\Data_B_i[12]_0 [0]),
.I4(\Data_A_i[12] [3]),
.I5(sgf_result_o0__1_carry__0_i_7__3_n_0),
.O(sgf_result_o0__1_carry__0_i_2__6_n_0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
sgf_result_o0__1_carry__0_i_3__7
(.I0(sgf_result_o0__1_carry_i_10__2_n_0),
.I1(\Data_B_i[12]_0 [1]),
.I2(\Data_A_i[12] [0]),
.I3(\Data_B_i[12]_0 [0]),
.I4(\Data_A_i[12] [3]),
.I5(sgf_result_o0__1_carry__0_i_7__3_n_0),
.O(sgf_result_o0__1_carry__0_i_3__7_n_0));
LUT6 #(
.INIT(64'h173F8080C0000000))
sgf_result_o0__1_carry__0_i_4__7
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_A_i[12] [2]),
.I2(\Data_B_i[12]_0 [2]),
.I3(\Data_A_i[12] [1]),
.I4(\Data_B_i[12]_0 [3]),
.I5(\Data_A_i[12] [3]),
.O(sgf_result_o0__1_carry__0_i_4__7_n_0));
LUT6 #(
.INIT(64'h9666699969996999))
sgf_result_o0__1_carry__0_i_5__8
(.I0(sgf_result_o0__1_carry__0_i_2__6_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__6_n_0),
.I2(\Data_A_i[12] [3]),
.I3(\Data_B_i[12]_0 [2]),
.I4(\Data_A_i[12] [2]),
.I5(\Data_B_i[12]_0 [3]),
.O(sgf_result_o0__1_carry__0_i_5__8_n_0));
LUT6 #(
.INIT(64'h56666AAA6AAA6AAA))
sgf_result_o0__1_carry__0_i_6__6
(.I0(sgf_result_o0__1_carry__0_i_3__7_n_0),
.I1(sgf_result_o0__1_carry__0_i_9__3_n_0),
.I2(\Data_A_i[12] [1]),
.I3(\Data_B_i[12]_0 [2]),
.I4(\Data_A_i[12] [0]),
.I5(\Data_B_i[12]_0 [3]),
.O(sgf_result_o0__1_carry__0_i_6__6_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry__0_i_7__3
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_A_i[12] [3]),
.I2(\Data_A_i[12] [2]),
.I3(\Data_B_i[12]_0 [2]),
.I4(\Data_A_i[12] [1]),
.I5(\Data_B_i[12]_0 [3]),
.O(sgf_result_o0__1_carry__0_i_7__3_n_0));
LUT6 #(
.INIT(64'h07777FFF7FFF7FFF))
sgf_result_o0__1_carry__0_i_8__6
(.I0(\Data_B_i[12]_0 [3]),
.I1(\Data_A_i[12] [1]),
.I2(\Data_B_i[12]_0 [2]),
.I3(\Data_A_i[12] [2]),
.I4(\Data_A_i[12] [3]),
.I5(\Data_B_i[12]_0 [1]),
.O(sgf_result_o0__1_carry__0_i_8__6_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry__0_i_9__3
(.I0(\Data_A_i[12] [2]),
.I1(\Data_B_i[12]_0 [1]),
.O(sgf_result_o0__1_carry__0_i_9__3_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_10__2
(.I0(\Data_A_i[12] [1]),
.I1(\Data_B_i[12]_0 [2]),
.O(sgf_result_o0__1_carry_i_10__2_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_11__7
(.I0(\Data_B_i[12]_0 [0]),
.I1(\Data_A_i[12] [3]),
.O(sgf_result_o0__1_carry_i_11__7_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_1__7
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_A_i[12] [2]),
.I2(\Data_A_i[12] [1]),
.I3(\Data_B_i[12]_0 [2]),
.I4(\Data_A_i[12] [0]),
.I5(\Data_B_i[12]_0 [3]),
.O(sgf_result_o0__1_carry_i_1__7_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_2__7
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_A_i[12] [1]),
.I2(\Data_B_i[12]_0 [2]),
.I3(\Data_A_i[12] [0]),
.O(sgf_result_o0__1_carry_i_2__7_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_3__7
(.I0(\Data_A_i[12] [0]),
.I1(\Data_B_i[12]_0 [1]),
.O(sgf_result_o0__1_carry_i_3__7_n_0));
LUT6 #(
.INIT(64'h99A5C30F665A3CF0))
sgf_result_o0__1_carry_i_4__7
(.I0(\Data_B_i[12]_0 [3]),
.I1(\Data_A_i[12] [2]),
.I2(sgf_result_o0__1_carry_i_10__2_n_0),
.I3(\Data_B_i[12]_0 [1]),
.I4(\Data_A_i[12] [0]),
.I5(sgf_result_o0__1_carry_i_11__7_n_0),
.O(sgf_result_o0__1_carry_i_4__7_n_0));
LUT6 #(
.INIT(64'h8777788878887888))
sgf_result_o0__1_carry_i_5__7
(.I0(\Data_A_i[12] [0]),
.I1(\Data_B_i[12]_0 [2]),
.I2(\Data_A_i[12] [1]),
.I3(\Data_B_i[12]_0 [1]),
.I4(\Data_A_i[12] [2]),
.I5(\Data_B_i[12]_0 [0]),
.O(sgf_result_o0__1_carry_i_5__7_n_0));
LUT4 #(
.INIT(16'h7888))
sgf_result_o0__1_carry_i_6__5
(.I0(\Data_A_i[12] [1]),
.I1(\Data_B_i[12]_0 [0]),
.I2(\Data_B_i[12]_0 [1]),
.I3(\Data_A_i[12] [0]),
.O(sgf_result_o0__1_carry_i_6__5_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o0__1_carry_i_7__7
(.I0(\Data_B_i[12]_0 [0]),
.I1(\Data_A_i[12] [0]),
.O(sgf_result_o0__1_carry_i_7__7_n_0));
CARRY4 sgf_result_o0_carry
(.CI(1'b0),
.CO({sgf_result_o0_carry_n_0,sgf_result_o0_carry_n_1,sgf_result_o0_carry_n_2,sgf_result_o0_carry_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o1__21_carry_n_5,sgf_result_o1__21_carry_n_6,sgf_result_o1__21_carry_n_7,1'b0}),
.O({sgf_result_o0_carry_n_4,sgf_result_o0_carry_n_5,sgf_result_o0_carry_n_6,sgf_result_o0_carry_n_7}),
.S({\ODD1.right_lower_n_19 ,\ODD1.right_lower_n_20 ,\ODD1.right_lower_n_21 ,\ODD1.right_lower_n_22 }));
CARRY4 sgf_result_o0_carry__0
(.CI(sgf_result_o0_carry_n_0),
.CO({sgf_result_o0_carry__0_n_0,sgf_result_o0_carry__0_n_1,sgf_result_o0_carry__0_n_2,sgf_result_o0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o1__21_carry__0_n_5,sgf_result_o1__21_carry__0_n_6,sgf_result_o1__21_carry__0_n_7,sgf_result_o1__21_carry_n_4}),
.O({sgf_result_o0_carry__0_n_4,sgf_result_o0_carry__0_n_5,sgf_result_o0_carry__0_n_6,sgf_result_o0_carry__0_n_7}),
.S({sgf_result_o0_carry__0_i_1_n_0,sgf_result_o0_carry__0_i_2_n_0,sgf_result_o0_carry__0_i_3_n_0,\ODD1.right_lower_n_23 }));
LUT6 #(
.INIT(64'h9A956595956A6A6A))
sgf_result_o0_carry__0_i_1
(.I0(sgf_result_o1__21_carry__0_n_5),
.I1(O[2]),
.I2(\Data_B_i[12]_1 [0]),
.I3(O[0]),
.I4(\Data_B_i[12]_1 [2]),
.I5(sgf_result_o0_carry__0_i_5_n_0),
.O(sgf_result_o0_carry__0_i_1_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
sgf_result_o0_carry__0_i_2
(.I0(sgf_result_o1__21_carry__0_n_6),
.I1(\Data_B_i[12]_1 [0]),
.I2(O[1]),
.I3(O[0]),
.I4(\Data_B_i[12]_1 [1]),
.O(sgf_result_o0_carry__0_i_2_n_0));
LUT3 #(
.INIT(8'h6A))
sgf_result_o0_carry__0_i_3
(.I0(sgf_result_o1__21_carry__0_n_7),
.I1(O[0]),
.I2(\Data_B_i[12]_1 [0]),
.O(sgf_result_o0_carry__0_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
sgf_result_o0_carry__0_i_5
(.I0(O[1]),
.I1(\Data_B_i[12]_1 [1]),
.O(sgf_result_o0_carry__0_i_5_n_0));
CARRY4 sgf_result_o0_carry__1
(.CI(sgf_result_o0_carry__0_n_0),
.CO({NLW_sgf_result_o0_carry__1_CO_UNCONNECTED[3:2],sgf_result_o0_carry__1_n_2,sgf_result_o0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,sgf_result_o1__21_carry__1_n_7,sgf_result_o1__21_carry__0_n_4}),
.O({NLW_sgf_result_o0_carry__1_O_UNCONNECTED[3],sgf_result_o0_carry__1_n_5,sgf_result_o0_carry__1_n_6,sgf_result_o0_carry__1_n_7}),
.S({1'b0,sgf_result_o0_carry__1_i_1_n_0,sgf_result_o0_carry__1_i_2_n_0,sgf_result_o0_carry__1_i_3_n_0}));
LUT2 #(
.INIT(4'h6))
sgf_result_o0_carry__1_i_1
(.I0(sgf_result_o1__21_carry__1_n_6),
.I1(sgf_result_o1__21_carry__0_i_9__1_n_0),
.O(sgf_result_o0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
sgf_result_o0_carry__1_i_2
(.I0(sgf_result_o1__21_carry__1_n_7),
.I1(sgf_result_o1__21_carry__0_i_10__1_n_0),
.O(sgf_result_o0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
sgf_result_o0_carry__1_i_3
(.I0(sgf_result_o1__21_carry__0_n_4),
.I1(sgf_result_o1__21_carry_i_9__1_n_0),
.O(sgf_result_o0_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h0400464B04000B0B))
sgf_result_o1__0_carry__0_i_6__1
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\ODD1.middle_n_6 ),
.I3(\ODD1.middle_n_11 ),
.I4(\ODD1.middle_n_8 ),
.I5(sgf_result_o1__0_carry_i_24_n_0),
.O(sgf_result_o1__0_carry__0_i_6__1_n_0));
LUT6 #(
.INIT(64'h0020000000330020))
sgf_result_o1__0_carry__0_i_7__1
(.I0(sgf_result_o1__0_carry_i_24_n_0),
.I1(\ODD1.middle_n_8 ),
.I2(\ODD1.middle_n_11 ),
.I3(\ODD1.middle_n_6 ),
.I4(\ODD1.middle_n_7 ),
.I5(\ODD1.middle_n_9 ),
.O(sgf_result_o1__0_carry__0_i_7__1_n_0));
LUT6 #(
.INIT(64'h6868688068808080))
sgf_result_o1__0_carry_i_10__1
(.I0(\Data_A_i[12] [3]),
.I1(\ODD1.middle_n_10 ),
.I2(\Data_B_i[12]_0 [3]),
.I3(\Data_B_i[12]_0 [2]),
.I4(\ODD1.middle_n_13 ),
.I5(\Data_B_i[12]_1 [2]),
.O(sgf_result_o1__0_carry_i_10__1_n_0));
LUT6 #(
.INIT(64'h6060609F609F6060))
sgf_result_o1__0_carry_i_11__1
(.I0(\Data_A_i[12] [0]),
.I1(O[0]),
.I2(\ODD1.middle_n_7 ),
.I3(\ODD1.middle_n_9 ),
.I4(\Data_B_i[12]_0 [0]),
.I5(\Data_B_i[12]_1 [0]),
.O(sgf_result_o1__0_carry_i_11__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_14__1
(.I0(\Data_A_i[12] [3]),
.I1(\Data_A_i[12] [2]),
.I2(\ODD1.middle_n_12 ),
.I3(O[2]),
.O(sgf_result_o1__0_carry_i_14__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_15__1
(.I0(\Data_B_i[12]_0 [3]),
.I1(\Data_B_i[12]_0 [2]),
.I2(\ODD1.middle_n_13 ),
.I3(\Data_B_i[12]_1 [2]),
.O(sgf_result_o1__0_carry_i_15__1_n_0));
LUT6 #(
.INIT(64'hBEFA7D72FEFA3236))
sgf_result_o1__0_carry_i_16__1
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\ODD1.middle_n_6 ),
.I3(\ODD1.middle_n_11 ),
.I4(\ODD1.middle_n_8 ),
.I5(sgf_result_o1__0_carry_i_24_n_0),
.O(sgf_result_o1__0_carry_i_16__1_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o1__0_carry_i_17__1
(.I0(sgf_result_o1__0_carry_i_15__1_n_0),
.I1(sgf_result_o1__0_carry_i_14__1_n_0),
.O(sgf_result_o1__0_carry_i_17__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hA880))
sgf_result_o1__0_carry_i_19__1
(.I0(\Data_A_i[12] [3]),
.I1(\Data_A_i[12] [2]),
.I2(\ODD1.middle_n_12 ),
.I3(O[2]),
.O(sgf_result_o1__0_carry_i_19__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_24
(.I0(\Data_B_i[12]_0 [0]),
.I1(\Data_B_i[12]_1 [0]),
.O(sgf_result_o1__0_carry_i_24_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1__0_carry_i_8__1
(.I0(sgf_result_o1_carry_i_5__1_n_0),
.I1(\ODD1.middle_n_6 ),
.I2(\ODD1.middle_n_11 ),
.I3(\ODD1.middle_n_8 ),
.I4(\Data_B_i[12]_1 [0]),
.I5(\Data_B_i[12]_0 [0]),
.O(sgf_result_o1__0_carry_i_8__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hE8000000))
sgf_result_o1__0_carry_i_9__1
(.I0(\Data_B_i[12]_1 [2]),
.I1(\ODD1.middle_n_13 ),
.I2(\Data_B_i[12]_0 [2]),
.I3(\Data_B_i[12]_0 [3]),
.I4(sgf_result_o1__0_carry_i_19__1_n_0),
.O(sgf_result_o1__0_carry_i_9__1_n_0));
CARRY4 sgf_result_o1__21_carry
(.CI(1'b0),
.CO({sgf_result_o1__21_carry_n_0,sgf_result_o1__21_carry_n_1,sgf_result_o1__21_carry_n_2,sgf_result_o1__21_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 ,1'b1}),
.O({sgf_result_o1__21_carry_n_4,sgf_result_o1__21_carry_n_5,sgf_result_o1__21_carry_n_6,sgf_result_o1__21_carry_n_7}),
.S({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }));
CARRY4 sgf_result_o1__21_carry__0
(.CI(sgf_result_o1__21_carry_n_0),
.CO({sgf_result_o1__21_carry__0_n_0,sgf_result_o1__21_carry__0_n_1,sgf_result_o1__21_carry__0_n_2,sgf_result_o1__21_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.O({sgf_result_o1__21_carry__0_n_4,sgf_result_o1__21_carry__0_n_5,sgf_result_o1__21_carry__0_n_6,sgf_result_o1__21_carry__0_n_7}),
.S({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }));
LUT6 #(
.INIT(64'h67878F8F7FFF7FFF))
sgf_result_o1__21_carry__0_i_10__1
(.I0(\Data_B_i[12]_1 [1]),
.I1(O[1]),
.I2(\Data_B_i[12]_1 [2]),
.I3(O[0]),
.I4(\Data_B_i[12]_1 [0]),
.I5(O[2]),
.O(sgf_result_o1__21_carry__0_i_10__1_n_0));
LUT6 #(
.INIT(64'hE080808000000000))
sgf_result_o1__21_carry__0_i_9__1
(.I0(O[1]),
.I1(\Data_B_i[12]_1 [1]),
.I2(O[2]),
.I3(\Data_B_i[12]_1 [0]),
.I4(O[0]),
.I5(\Data_B_i[12]_1 [2]),
.O(sgf_result_o1__21_carry__0_i_9__1_n_0));
CARRY4 sgf_result_o1__21_carry__1
(.CI(sgf_result_o1__21_carry__0_n_0),
.CO({NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED[3:1],sgf_result_o1__21_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp__3[8]}),
.O({NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED[3:2],sgf_result_o1__21_carry__1_n_6,sgf_result_o1__21_carry__1_n_7}),
.S({1'b0,1'b0,sgf_result_o1__21_carry__1_i_1__1_n_0,\ODD1.middle_n_21 }));
LUT1 #(
.INIT(2'h1))
sgf_result_o1__21_carry__1_i_1__1
(.I0(Q_middle_temp__3[9]),
.O(sgf_result_o1__21_carry__1_i_1__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h7888))
sgf_result_o1__21_carry_i_10__1
(.I0(\Data_B_i[12]_1 [1]),
.I1(O[0]),
.I2(O[1]),
.I3(\Data_B_i[12]_1 [0]),
.O(sgf_result_o1__21_carry_i_10__1_n_0));
LUT6 #(
.INIT(64'h0F777888F0887888))
sgf_result_o1__21_carry_i_8__1
(.I0(\Data_B_i[12]_1 [1]),
.I1(O[1]),
.I2(\Data_B_i[12]_1 [2]),
.I3(O[0]),
.I4(\Data_B_i[12]_1 [0]),
.I5(O[2]),
.O(sgf_result_o1__21_carry_i_8__1_n_0));
LUT6 #(
.INIT(64'hED1D1595B73FBF3F))
sgf_result_o1__21_carry_i_9__1
(.I0(\Data_B_i[12]_1 [1]),
.I1(O[1]),
.I2(\Data_B_i[12]_1 [2]),
.I3(O[0]),
.I4(\Data_B_i[12]_1 [0]),
.I5(O[2]),
.O(sgf_result_o1__21_carry_i_9__1_n_0));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__35_carry_i_1
(.I0(Q_middle_temp__5[9]),
.I1(sgf_result_o0_carry__1_n_6),
.O(DI[1]));
(* HLUTNM = "lutpair56" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_1__1
(.I0(Q_middle_temp__5[3]),
.I1(\Data_B_i[12]_3 [0]),
.I2(sgf_result_o0_carry_n_4),
.O(\sgf_result_o[47]_2 [3]));
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_1__2
(.I0(Q_middle_temp__5[7]),
.I1(\Data_A_i[12]_0 [0]),
.I2(sgf_result_o0_carry__0_n_4),
.O(\sgf_result_o[47]_0 [3]));
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_2__0
(.I0(Q_middle_temp__5[8]),
.I1(\Data_A_i[12]_0 [1]),
.I2(sgf_result_o0_carry__1_n_7),
.O(DI[0]));
(* HLUTNM = "lutpair55" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_2__1
(.I0(Q_middle_temp__5[2]),
.I1(\Data_B_i[12]_2 [2]),
.I2(sgf_result_o0_carry_n_5),
.O(\sgf_result_o[47]_2 [2]));
(* HLUTNM = "lutpair59" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_2__2
(.I0(Q_middle_temp__5[6]),
.I1(\Data_B_i[12]_3 [3]),
.I2(sgf_result_o0_carry__0_n_5),
.O(\sgf_result_o[47]_0 [2]));
(* HLUTNM = "lutpair54" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_3__0
(.I0(Q_middle_temp__5[1]),
.I1(\Data_B_i[12]_2 [1]),
.I2(sgf_result_o0_carry_n_6),
.O(\sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair58" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_3__1
(.I0(Q_middle_temp__5[5]),
.I1(\Data_B_i[12]_3 [2]),
.I2(sgf_result_o0_carry__0_n_6),
.O(\sgf_result_o[47]_0 [1]));
LUT3 #(
.INIT(8'h2D))
sgf_result_o1__35_carry_i_4
(.I0(sgf_result_o0_carry__1_n_5),
.I1(Q_middle_temp__5[10]),
.I2(Q_middle_temp__5[11]),
.O(\sgf_result_o[47]_1 [2]));
(* HLUTNM = "lutpair53" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_4__0
(.I0(Q_middle_temp__5[0]),
.I1(\Data_B_i[12]_2 [0]),
.I2(sgf_result_o0_carry_n_7),
.O(\sgf_result_o[47]_2 [0]));
(* HLUTNM = "lutpair53" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_4__1
(.I0(Q_middle_temp__5[0]),
.I1(\Data_B_i[12]_2 [0]),
.I2(sgf_result_o0_carry_n_7),
.I3(\Data_A_i[12]_1 ),
.O(\sgf_result_o[47]_3 ));
(* HLUTNM = "lutpair57" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_4__2
(.I0(Q_middle_temp__5[4]),
.I1(\Data_B_i[12]_3 [1]),
.I2(sgf_result_o0_carry__0_n_7),
.O(\sgf_result_o[47]_0 [0]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_5
(.I0(\sgf_result_o[47]_0 [3]),
.I1(Q_middle_temp__5[8]),
.I2(\Data_A_i[12]_0 [1]),
.I3(sgf_result_o0_carry__1_n_7),
.O(S[3]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__35_carry_i_5__0
(.I0(sgf_result_o0_carry__1_n_6),
.I1(Q_middle_temp__5[9]),
.I2(sgf_result_o0_carry__1_n_5),
.I3(Q_middle_temp__5[10]),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair57" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_5__2
(.I0(Q_middle_temp__5[4]),
.I1(\Data_B_i[12]_3 [1]),
.I2(sgf_result_o0_carry__0_n_7),
.I3(\sgf_result_o[47]_2 [3]),
.O(\sgf_result_o[47]_4 [3]));
LUT5 #(
.INIT(32'h718E8E71))
sgf_result_o1__35_carry_i_6__0
(.I0(sgf_result_o0_carry__1_n_7),
.I1(\Data_A_i[12]_0 [1]),
.I2(Q_middle_temp__5[8]),
.I3(sgf_result_o0_carry__1_n_6),
.I4(Q_middle_temp__5[9]),
.O(\sgf_result_o[47]_1 [0]));
(* HLUTNM = "lutpair56" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_6__1
(.I0(Q_middle_temp__5[3]),
.I1(\Data_B_i[12]_3 [0]),
.I2(sgf_result_o0_carry_n_4),
.I3(\sgf_result_o[47]_2 [2]),
.O(\sgf_result_o[47]_4 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_6__2
(.I0(Q_middle_temp__5[7]),
.I1(\Data_A_i[12]_0 [0]),
.I2(sgf_result_o0_carry__0_n_4),
.I3(\sgf_result_o[47]_0 [2]),
.O(S[2]));
(* HLUTNM = "lutpair55" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_7
(.I0(Q_middle_temp__5[2]),
.I1(\Data_B_i[12]_2 [2]),
.I2(sgf_result_o0_carry_n_5),
.I3(\sgf_result_o[47]_2 [1]),
.O(\sgf_result_o[47]_4 [1]));
(* HLUTNM = "lutpair59" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_7__0
(.I0(Q_middle_temp__5[6]),
.I1(\Data_B_i[12]_3 [3]),
.I2(sgf_result_o0_carry__0_n_5),
.I3(\sgf_result_o[47]_0 [1]),
.O(S[1]));
(* HLUTNM = "lutpair54" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_8
(.I0(Q_middle_temp__5[1]),
.I1(\Data_B_i[12]_2 [1]),
.I2(sgf_result_o0_carry_n_6),
.I3(\sgf_result_o[47]_2 [0]),
.O(\sgf_result_o[47]_4 [0]));
(* HLUTNM = "lutpair58" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_8__0
(.I0(Q_middle_temp__5[5]),
.I1(\Data_B_i[12]_3 [2]),
.I2(sgf_result_o0_carry__0_n_6),
.I3(\sgf_result_o[47]_0 [0]),
.O(S[0]));
CARRY4 sgf_result_o1_carry
(.CI(1'b0),
.CO({sgf_result_o1_carry_n_0,sgf_result_o1_carry_n_1,sgf_result_o1_carry_n_2,sgf_result_o1_carry_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 ,1'b0}),
.O(Q_middle_temp__3[5:2]),
.S({\ODD1.middle_n_14 ,\ODD1.middle_n_15 ,\ODD1.middle_n_16 ,sgf_result_o1_carry_i_4__1_n_0}));
CARRY4 sgf_result_o1_carry__0
(.CI(sgf_result_o1_carry_n_0),
.CO({NLW_sgf_result_o1_carry__0_CO_UNCONNECTED[3],sgf_result_o1_carry__0_n_1,sgf_result_o1_carry__0_n_2,sgf_result_o1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\ODD1.middle_n_4 ,\ODD1.middle_n_5 ,\ODD1.middle_n_0 }),
.O(Q_middle_temp__3[9:6]),
.S({\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 }));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1_carry_i_4__1
(.I0(sgf_result_o1_carry_i_5__1_n_0),
.I1(\ODD1.middle_n_6 ),
.I2(\ODD1.middle_n_11 ),
.I3(\ODD1.middle_n_8 ),
.I4(\Data_B_i[12]_1 [0]),
.I5(\Data_B_i[12]_0 [0]),
.O(sgf_result_o1_carry_i_4__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o1_carry_i_5__1
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_B_i[12]_1 [1]),
.I2(\Data_B_i[12]_0 [0]),
.I3(\Data_B_i[12]_1 [0]),
.I4(\ODD1.middle_n_9 ),
.O(sgf_result_o1_carry_i_5__1_n_0));
(* HLUTNM = "lutpair61" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[22]_inst_i_10
(.I0(sgf_result_o0_carry_n_7),
.I1(\Data_A_i[17] [1]),
.I2(sgf_result_o_OBUF[2]),
.O(\sgf_result_o_OBUF[22]_inst_i_10_n_0 ));
(* HLUTNM = "lutpair64" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[22]_inst_i_12
(.I0(\sgf_result_o[47]_5 [0]),
.I1(\Data_A_i[23] [1]),
.I2(sgf_result_o_OBUF[5]),
.I3(\sgf_result_o_OBUF[22]_inst_i_8_n_0 ),
.O(\sgf_result_o_OBUF[22]_inst_i_12_n_0 ));
(* HLUTNM = "lutpair63" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[22]_inst_i_13
(.I0(sgf_result_o0_carry_n_5),
.I1(\Data_A_i[23] [0]),
.I2(sgf_result_o_OBUF[4]),
.I3(\sgf_result_o_OBUF[22]_inst_i_9_n_0 ),
.O(\sgf_result_o_OBUF[22]_inst_i_13_n_0 ));
(* HLUTNM = "lutpair62" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[22]_inst_i_14
(.I0(sgf_result_o0_carry_n_6),
.I1(\Data_A_i[17] [2]),
.I2(sgf_result_o_OBUF[3]),
.I3(\sgf_result_o_OBUF[22]_inst_i_10_n_0 ),
.O(\sgf_result_o_OBUF[22]_inst_i_14_n_0 ));
(* HLUTNM = "lutpair63" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[22]_inst_i_8
(.I0(sgf_result_o0_carry_n_5),
.I1(\Data_A_i[23] [0]),
.I2(sgf_result_o_OBUF[4]),
.O(\sgf_result_o_OBUF[22]_inst_i_8_n_0 ));
(* HLUTNM = "lutpair62" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[22]_inst_i_9
(.I0(sgf_result_o0_carry_n_6),
.I1(\Data_A_i[17] [2]),
.I2(sgf_result_o_OBUF[3]),
.O(\sgf_result_o_OBUF[22]_inst_i_9_n_0 ));
CARRY4 \sgf_result_o_OBUF[26]_inst_i_16
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[26]_inst_i_16_n_0 ,\sgf_result_o_OBUF[26]_inst_i_16_n_1 ,\sgf_result_o_OBUF[26]_inst_i_16_n_2 ,\sgf_result_o_OBUF[26]_inst_i_16_n_3 }),
.CYINIT(1'b0),
.DI({sgf_result_o1[2:0],1'b0}),
.O(\sgf_result_o[47]_5 [3:0]),
.S({\sgf_result_o_OBUF[26]_inst_i_20_n_0 ,\sgf_result_o_OBUF[26]_inst_i_21_n_0 ,\sgf_result_o_OBUF[26]_inst_i_22_n_0 ,sgf_result_o0_carry_n_4}));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[26]_inst_i_20
(.I0(sgf_result_o1[2]),
.I1(sgf_result_o0_carry__0_n_5),
.O(\sgf_result_o_OBUF[26]_inst_i_20_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[26]_inst_i_21
(.I0(sgf_result_o1[1]),
.I1(sgf_result_o0_carry__0_n_6),
.O(\sgf_result_o_OBUF[26]_inst_i_21_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[26]_inst_i_22
(.I0(sgf_result_o1[0]),
.I1(sgf_result_o0_carry__0_n_7),
.O(\sgf_result_o_OBUF[26]_inst_i_22_n_0 ));
CARRY4 \sgf_result_o_OBUF[30]_inst_i_15
(.CI(\sgf_result_o_OBUF[26]_inst_i_16_n_0 ),
.CO({\sgf_result_o_OBUF[30]_inst_i_15_n_0 ,\sgf_result_o_OBUF[30]_inst_i_15_n_1 ,\sgf_result_o_OBUF[30]_inst_i_15_n_2 ,\sgf_result_o_OBUF[30]_inst_i_15_n_3 }),
.CYINIT(1'b0),
.DI(sgf_result_o1[6:3]),
.O(\sgf_result_o[47]_5 [7:4]),
.S({\sgf_result_o_OBUF[30]_inst_i_16_n_0 ,\sgf_result_o_OBUF[30]_inst_i_17_n_0 ,\sgf_result_o_OBUF[30]_inst_i_18_n_0 ,\sgf_result_o_OBUF[30]_inst_i_19_n_0 }));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_16
(.I0(sgf_result_o1[6]),
.I1(sgf_result_o0_carry__1_n_5),
.O(\sgf_result_o_OBUF[30]_inst_i_16_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_17
(.I0(sgf_result_o1[5]),
.I1(sgf_result_o0_carry__1_n_6),
.O(\sgf_result_o_OBUF[30]_inst_i_17_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_18
(.I0(sgf_result_o1[4]),
.I1(sgf_result_o0_carry__1_n_7),
.O(\sgf_result_o_OBUF[30]_inst_i_18_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_19
(.I0(sgf_result_o1[3]),
.I1(sgf_result_o0_carry__0_n_4),
.O(\sgf_result_o_OBUF[30]_inst_i_19_n_0 ));
CARRY4 \sgf_result_o_OBUF[34]_inst_i_16
(.CI(\sgf_result_o_OBUF[30]_inst_i_15_n_0 ),
.CO({\sgf_result_o_OBUF[34]_inst_i_16_n_0 ,\sgf_result_o_OBUF[34]_inst_i_16_n_1 ,\sgf_result_o_OBUF[34]_inst_i_16_n_2 ,\sgf_result_o_OBUF[34]_inst_i_16_n_3 }),
.CYINIT(1'b0),
.DI(sgf_result_o1[10:7]),
.O(\sgf_result_o[47]_5 [11:8]),
.S(\Data_B_i[12]_4 ));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_20
(.CI(\sgf_result_o_OBUF[34]_inst_i_16_n_0 ),
.CO({\sgf_result_o_OBUF[38]_inst_i_20_n_0 ,\sgf_result_o_OBUF[38]_inst_i_20_n_1 ,\sgf_result_o_OBUF[38]_inst_i_20_n_2 ,\sgf_result_o_OBUF[38]_inst_i_20_n_3 }),
.CYINIT(1'b0),
.DI(sgf_result_o1[14:11]),
.O(\sgf_result_o[47]_5 [15:12]),
.S(\Data_B_i[12]_5 ));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_8
(.CI(\sgf_result_o_OBUF[38]_inst_i_20_n_0 ),
.CO({\NLW_sgf_result_o_OBUF[38]_inst_i_8_CO_UNCONNECTED [3],\sgf_result_o_OBUF[38]_inst_i_8_n_1 ,\sgf_result_o_OBUF[38]_inst_i_8_n_2 ,\sgf_result_o_OBUF[38]_inst_i_8_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sgf_result_o1[15]}),
.O({Q_middle_temp__6,\sgf_result_o[47]_5 [18:16]}),
.S(\Data_A_i[12]_2 ));
LUT1 #(
.INIT(2'h1))
\sgf_result_o_OBUF[38]_inst_i_9
(.I0(Q_middle_temp__6),
.O(\sgf_result_o_OBUF[38]_inst_i_9_n_0 ));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized39
(O,
CO,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
DI,
S,
\Data_B_i[12] ,
\Data_A_i[12] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12]_0 ,
\Data_B_i[16] ,
\Data_B_i[12]_1 ,
\Data_A_i[12]_0 ,
\Data_B_i[12]_2 ,
Q_middle_temp__3,
\Data_A_i[12]_1 ,
\Data_A_i[12]_2 ,
sgf_result_o_OBUF,
\Data_A_i[12]_3 ,
\Data_A_i[12]_4 ,
\Data_A_i[12]_5 ,
\Data_A_i[17] ,
\Data_A_i[12]_6 ,
\Data_B_i[17] ,
\Data_B_i[17]_0 ,
\Data_A_i[14] ,
\Data_A_i[14]_0 ,
\Data_A_i[13] ,
\Data_A_i[13]_0 ,
\Data_A_i[13]_1 ,
\Data_A_i[13]_2 ,
\Data_A_i[13]_3 ,
\Data_A_i[13]_4 ,
\Data_A_i[12]_7 ,
\Data_A_i[12]_8 ,
\Data_A_i[11] ,
\Data_A_i[14]_1 ,
\Data_A_i[14]_2 ,
\Data_A_i[14]_3 ,
\Data_A_i[14]_4 ,
\Data_B_i[12]_3 ,
\Data_A_i[12]_9 ,
\Data_A_i[11]_0 ,
\Data_A_i[2] ,
\Data_A_i[2]_0 ,
\Data_A_i[2]_1 ,
\Data_A_i[23] ,
\Data_A_i[23]_0 ,
\Data_A_i[14]_5 );
output [2:0]O;
output [0:0]CO;
output [2:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [0:0]\sgf_result_o[47]_4 ;
output [36:0]\sgf_result_o[47]_5 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[12] ;
input [2:0]\Data_A_i[12] ;
input [3:0]Data_B_i_IBUF;
input [3:0]Data_A_i_IBUF;
input \Data_B_i[12]_0 ;
input \Data_B_i[16] ;
input [1:0]\Data_B_i[12]_1 ;
input [1:0]\Data_A_i[12]_0 ;
input \Data_B_i[12]_2 ;
input [5:0]Q_middle_temp__3;
input \Data_A_i[12]_1 ;
input [3:0]\Data_A_i[12]_2 ;
input [2:0]sgf_result_o_OBUF;
input \Data_A_i[12]_3 ;
input \Data_A_i[12]_4 ;
input \Data_A_i[12]_5 ;
input [2:0]\Data_A_i[17] ;
input [0:0]\Data_A_i[12]_6 ;
input [3:0]\Data_B_i[17] ;
input [3:0]\Data_B_i[17]_0 ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[14]_0 ;
input [3:0]\Data_A_i[13] ;
input [3:0]\Data_A_i[13]_0 ;
input [3:0]\Data_A_i[13]_1 ;
input [3:0]\Data_A_i[13]_2 ;
input [3:0]\Data_A_i[13]_3 ;
input [3:0]\Data_A_i[13]_4 ;
input [0:0]\Data_A_i[12]_7 ;
input [1:0]\Data_A_i[12]_8 ;
input [0:0]\Data_A_i[11] ;
input [0:0]\Data_A_i[14]_1 ;
input [3:0]\Data_A_i[14]_2 ;
input [3:0]\Data_A_i[14]_3 ;
input [0:0]\Data_A_i[14]_4 ;
input [0:0]\Data_B_i[12]_3 ;
input [0:0]\Data_A_i[12]_9 ;
input [0:0]\Data_A_i[11]_0 ;
input [3:0]\Data_A_i[2] ;
input [3:0]\Data_A_i[2]_0 ;
input [2:0]\Data_A_i[2]_1 ;
input [3:0]\Data_A_i[23] ;
input [3:0]\Data_A_i[23]_0 ;
input [0:0]\Data_A_i[14]_5 ;
wire [0:0]CO;
wire [2:0]DI;
wire [0:0]\Data_A_i[11] ;
wire [0:0]\Data_A_i[11]_0 ;
wire [2:0]\Data_A_i[12] ;
wire [1:0]\Data_A_i[12]_0 ;
wire \Data_A_i[12]_1 ;
wire [3:0]\Data_A_i[12]_2 ;
wire \Data_A_i[12]_3 ;
wire \Data_A_i[12]_4 ;
wire \Data_A_i[12]_5 ;
wire [0:0]\Data_A_i[12]_6 ;
wire [0:0]\Data_A_i[12]_7 ;
wire [1:0]\Data_A_i[12]_8 ;
wire [0:0]\Data_A_i[12]_9 ;
wire [3:0]\Data_A_i[13] ;
wire [3:0]\Data_A_i[13]_0 ;
wire [3:0]\Data_A_i[13]_1 ;
wire [3:0]\Data_A_i[13]_2 ;
wire [3:0]\Data_A_i[13]_3 ;
wire [3:0]\Data_A_i[13]_4 ;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [0:0]\Data_A_i[14]_1 ;
wire [3:0]\Data_A_i[14]_2 ;
wire [3:0]\Data_A_i[14]_3 ;
wire [0:0]\Data_A_i[14]_4 ;
wire [0:0]\Data_A_i[14]_5 ;
wire [2:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire [3:0]\Data_A_i[2] ;
wire [3:0]\Data_A_i[2]_0 ;
wire [2:0]\Data_A_i[2]_1 ;
wire [3:0]Data_A_i_IBUF;
wire [2:0]\Data_B_i[12] ;
wire \Data_B_i[12]_0 ;
wire [1:0]\Data_B_i[12]_1 ;
wire \Data_B_i[12]_2 ;
wire [0:0]\Data_B_i[12]_3 ;
wire \Data_B_i[16] ;
wire [3:0]\Data_B_i[17] ;
wire [3:0]\Data_B_i[17]_0 ;
wire [3:0]Data_B_i_IBUF;
wire [2:0]O;
wire [5:0]Q_middle_temp__3;
wire [3:0]S;
wire [37:12]p_1_in;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\^sgf_result_o[47]_3 ;
wire [0:0]\sgf_result_o[47]_4 ;
wire [36:0]\sgf_result_o[47]_5 ;
wire [2:0]sgf_result_o_OBUF;
wire \sgf_result_o_OBUF[14]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[14]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[14]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[14]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[14]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[14]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[14]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_10_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_11_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_12_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_13_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[18]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[18]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[18]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_2_n_1 ;
wire \sgf_result_o_OBUF[18]_inst_i_2_n_2 ;
wire \sgf_result_o_OBUF[18]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[18]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_8_n_0 ;
wire \sgf_result_o_OBUF[18]_inst_i_9_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[22]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[22]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[22]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_2_n_1 ;
wire \sgf_result_o_OBUF[22]_inst_i_2_n_2 ;
wire \sgf_result_o_OBUF[22]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[22]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[22]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[26]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[26]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[26]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_2_n_1 ;
wire \sgf_result_o_OBUF[26]_inst_i_2_n_2 ;
wire \sgf_result_o_OBUF[26]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[26]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[26]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[30]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[30]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[30]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_2_n_1 ;
wire \sgf_result_o_OBUF[30]_inst_i_2_n_2 ;
wire \sgf_result_o_OBUF[30]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[30]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[30]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[34]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[34]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[34]_inst_i_2_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_2_n_1 ;
wire \sgf_result_o_OBUF[34]_inst_i_2_n_2 ;
wire \sgf_result_o_OBUF[34]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[34]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_4_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[34]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[38]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[38]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_2_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_3_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_3_n_1 ;
wire \sgf_result_o_OBUF[38]_inst_i_3_n_2 ;
wire \sgf_result_o_OBUF[38]_inst_i_3_n_3 ;
wire \sgf_result_o_OBUF[38]_inst_i_5_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_6_n_0 ;
wire \sgf_result_o_OBUF[38]_inst_i_7_n_0 ;
wire \sgf_result_o_OBUF[42]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[42]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[42]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[42]_inst_i_1_n_3 ;
wire \sgf_result_o_OBUF[46]_inst_i_1_n_0 ;
wire \sgf_result_o_OBUF[46]_inst_i_1_n_1 ;
wire \sgf_result_o_OBUF[46]_inst_i_1_n_2 ;
wire \sgf_result_o_OBUF[46]_inst_i_1_n_3 ;
wire [2:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
wire [3:1]\NLW_sgf_result_o_OBUF[38]_inst_i_2_CO_UNCONNECTED ;
wire [3:2]\NLW_sgf_result_o_OBUF[38]_inst_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_sgf_result_o_OBUF[47]_inst_i_1_CO_UNCONNECTED ;
wire [3:1]\NLW_sgf_result_o_OBUF[47]_inst_i_1_O_UNCONNECTED ;
assign \sgf_result_o[47]_3 [3:1] = \^sgf_result_o[47]_3 [3:1];
assign \sgf_result_o[47]_3 [0] = sgf_result_o0__1_carry_n_4;
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,O}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({CO,NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_B_i[12] }),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[12] }));
LUT2 #(
.INIT(4'h6))
sgf_result_o0_carry__0_i_4
(.I0(\Data_A_i[12]_2 [3]),
.I1(CO),
.O(\sgf_result_o[47]_4 ));
LUT2 #(
.INIT(4'h6))
sgf_result_o0_carry_i_1
(.I0(\Data_A_i[12]_2 [2]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\^sgf_result_o[47]_3 [3]));
LUT2 #(
.INIT(4'h6))
sgf_result_o0_carry_i_2
(.I0(\Data_A_i[12]_2 [1]),
.I1(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_3 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o0_carry_i_3
(.I0(\Data_A_i[12]_2 [0]),
.I1(sgf_result_o0__1_carry__0_n_7),
.O(\^sgf_result_o[47]_3 [1]));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__21_carry__0_i_1__1
(.I0(Q_middle_temp__3[4]),
.I1(sgf_result_o0__1_carry__0_n_5),
.O(\sgf_result_o[47]_0 [3]));
LUT3 #(
.INIT(8'h4D))
sgf_result_o1__21_carry__0_i_2__1
(.I0(\Data_B_i[12]_2 ),
.I1(Q_middle_temp__3[3]),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(\sgf_result_o[47]_0 [2]));
(* HLUTNM = "lutpair44" *)
LUT3 #(
.INIT(8'hB2))
sgf_result_o1__21_carry__0_i_3__1
(.I0(\Data_A_i[12]_5 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(Q_middle_temp__3[2]),
.O(\sgf_result_o[47]_0 [1]));
(* HLUTNM = "lutpair43" *)
LUT3 #(
.INIT(8'hD4))
sgf_result_o1__21_carry__0_i_4__1
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[12]_4 ),
.I2(Q_middle_temp__3[1]),
.O(\sgf_result_o[47]_0 [0]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__21_carry__0_i_5__1
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(Q_middle_temp__3[4]),
.I2(CO),
.I3(Q_middle_temp__3[5]),
.O(\sgf_result_o[47]_2 [3]));
LUT5 #(
.INIT(32'h4DB2B24D))
sgf_result_o1__21_carry__0_i_6__1
(.I0(sgf_result_o0__1_carry__0_n_6),
.I1(Q_middle_temp__3[3]),
.I2(\Data_B_i[12]_2 ),
.I3(sgf_result_o0__1_carry__0_n_5),
.I4(Q_middle_temp__3[4]),
.O(\sgf_result_o[47]_2 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry__0_i_7__1
(.I0(\sgf_result_o[47]_0 [1]),
.I1(Q_middle_temp__3[3]),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\Data_B_i[12]_2 ),
.O(\sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair44" *)
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__21_carry__0_i_8__1
(.I0(\Data_A_i[12]_5 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(Q_middle_temp__3[2]),
.I3(\sgf_result_o[47]_0 [0]),
.O(\sgf_result_o[47]_2 [0]));
(* HLUTNM = "lutpair42" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__21_carry_i_1__1
(.I0(Q_middle_temp__3[0]),
.I1(O[2]),
.I2(\Data_A_i[12]_3 ),
.O(\sgf_result_o[47] [2]));
LUT6 #(
.INIT(64'hB2222BBB2BBB2BBB))
sgf_result_o1__21_carry_i_2__1
(.I0(\Data_B_i[16] ),
.I1(O[1]),
.I2(\Data_B_i[12]_1 [0]),
.I3(\Data_A_i[12]_0 [1]),
.I4(\Data_A_i[12]_0 [0]),
.I5(\Data_B_i[12]_1 [1]),
.O(\sgf_result_o[47] [1]));
(* HLUTNM = "lutpair86" *)
LUT5 #(
.INIT(32'h1747270F))
sgf_result_o1__21_carry_i_3__1
(.I0(\Data_A_i[12]_0 [0]),
.I1(\Data_B_i[12]_1 [0]),
.I2(O[0]),
.I3(\Data_B_i[12]_3 ),
.I4(\Data_A_i[12]_9 ),
.O(\sgf_result_o[47] [0]));
(* HLUTNM = "lutpair43" *)
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__21_carry_i_4__1
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[12]_4 ),
.I2(Q_middle_temp__3[1]),
.I3(\sgf_result_o[47] [2]),
.O(\sgf_result_o[47]_1 [3]));
(* HLUTNM = "lutpair42" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_5__1
(.I0(Q_middle_temp__3[0]),
.I1(O[2]),
.I2(\Data_A_i[12]_3 ),
.I3(\sgf_result_o[47] [1]),
.O(\sgf_result_o[47]_1 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__21_carry_i_6__1
(.I0(\sgf_result_o[47] [0]),
.I1(O[1]),
.I2(\Data_A_i[12]_1 ),
.I3(\Data_B_i[16] ),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair86" *)
LUT5 #(
.INIT(32'h96C3A50F))
sgf_result_o1__21_carry_i_7__1
(.I0(\Data_A_i[12]_0 [0]),
.I1(\Data_B_i[12]_1 [0]),
.I2(O[0]),
.I3(\Data_B_i[12]_3 ),
.I4(\Data_A_i[12]_9 ),
.O(\sgf_result_o[47]_1 [0]));
CARRY4 \sgf_result_o_OBUF[14]_inst_i_1
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[14]_inst_i_1_n_0 ,\sgf_result_o_OBUF[14]_inst_i_1_n_1 ,\sgf_result_o_OBUF[14]_inst_i_1_n_2 ,\sgf_result_o_OBUF[14]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({p_1_in[14:12],1'b0}),
.O(\sgf_result_o[47]_5 [3:0]),
.S({\sgf_result_o_OBUF[14]_inst_i_2_n_0 ,\sgf_result_o_OBUF[14]_inst_i_3_n_0 ,\sgf_result_o_OBUF[14]_inst_i_4_n_0 ,\Data_A_i[11] }));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[14]_inst_i_2
(.I0(p_1_in[14]),
.I1(\Data_A_i[2] [1]),
.O(\sgf_result_o_OBUF[14]_inst_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[14]_inst_i_3
(.I0(p_1_in[13]),
.I1(\Data_A_i[2] [0]),
.O(\sgf_result_o_OBUF[14]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[14]_inst_i_4
(.I0(p_1_in[12]),
.I1(\Data_A_i[11]_0 ),
.O(\sgf_result_o_OBUF[14]_inst_i_4_n_0 ));
CARRY4 \sgf_result_o_OBUF[18]_inst_i_1
(.CI(\sgf_result_o_OBUF[14]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[18]_inst_i_1_n_0 ,\sgf_result_o_OBUF[18]_inst_i_1_n_1 ,\sgf_result_o_OBUF[18]_inst_i_1_n_2 ,\sgf_result_o_OBUF[18]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_1_in[18:15]),
.O(\sgf_result_o[47]_5 [7:4]),
.S({\sgf_result_o_OBUF[18]_inst_i_3_n_0 ,\sgf_result_o_OBUF[18]_inst_i_4_n_0 ,\sgf_result_o_OBUF[18]_inst_i_5_n_0 ,\sgf_result_o_OBUF[18]_inst_i_6_n_0 }));
(* HLUTNM = "lutpair61" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[18]_inst_i_10
(.I0(\Data_A_i[12]_6 ),
.I1(\Data_A_i[17] [1]),
.I2(sgf_result_o_OBUF[2]),
.I3(\sgf_result_o_OBUF[18]_inst_i_7_n_0 ),
.O(\sgf_result_o_OBUF[18]_inst_i_10_n_0 ));
(* HLUTNM = "lutpair60" *)
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[18]_inst_i_11
(.I0(O[2]),
.I1(\Data_A_i[17] [0]),
.I2(sgf_result_o_OBUF[1]),
.I3(\sgf_result_o_OBUF[18]_inst_i_8_n_0 ),
.O(\sgf_result_o_OBUF[18]_inst_i_11_n_0 ));
LUT4 #(
.INIT(16'h6996))
\sgf_result_o_OBUF[18]_inst_i_12
(.I0(\sgf_result_o_OBUF[18]_inst_i_9_n_0 ),
.I1(sgf_result_o_OBUF[0]),
.I2(\Data_B_i[12]_0 ),
.I3(O[1]),
.O(\sgf_result_o_OBUF[18]_inst_i_12_n_0 ));
(* HLUTNM = "lutpair89" *)
LUT5 #(
.INIT(32'h78888777))
\sgf_result_o_OBUF[18]_inst_i_13
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[2]),
.I4(O[0]),
.O(\sgf_result_o_OBUF[18]_inst_i_13_n_0 ));
CARRY4 \sgf_result_o_OBUF[18]_inst_i_2
(.CI(1'b0),
.CO({\sgf_result_o_OBUF[18]_inst_i_2_n_0 ,\sgf_result_o_OBUF[18]_inst_i_2_n_1 ,\sgf_result_o_OBUF[18]_inst_i_2_n_2 ,\sgf_result_o_OBUF[18]_inst_i_2_n_3 }),
.CYINIT(1'b1),
.DI({\sgf_result_o_OBUF[18]_inst_i_7_n_0 ,\sgf_result_o_OBUF[18]_inst_i_8_n_0 ,\sgf_result_o_OBUF[18]_inst_i_9_n_0 ,1'b1}),
.O(p_1_in[15:12]),
.S({\sgf_result_o_OBUF[18]_inst_i_10_n_0 ,\sgf_result_o_OBUF[18]_inst_i_11_n_0 ,\sgf_result_o_OBUF[18]_inst_i_12_n_0 ,\sgf_result_o_OBUF[18]_inst_i_13_n_0 }));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_3
(.I0(p_1_in[18]),
.I1(\Data_A_i[2]_0 [1]),
.O(\sgf_result_o_OBUF[18]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_4
(.I0(p_1_in[17]),
.I1(\Data_A_i[2]_0 [0]),
.O(\sgf_result_o_OBUF[18]_inst_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_5
(.I0(p_1_in[16]),
.I1(\Data_A_i[2] [3]),
.O(\sgf_result_o_OBUF[18]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[18]_inst_i_6
(.I0(p_1_in[15]),
.I1(\Data_A_i[2] [2]),
.O(\sgf_result_o_OBUF[18]_inst_i_6_n_0 ));
(* HLUTNM = "lutpair60" *)
LUT3 #(
.INIT(8'h2B))
\sgf_result_o_OBUF[18]_inst_i_7
(.I0(O[2]),
.I1(\Data_A_i[17] [0]),
.I2(sgf_result_o_OBUF[1]),
.O(\sgf_result_o_OBUF[18]_inst_i_7_n_0 ));
LUT6 #(
.INIT(64'h87770000FFFF8777))
\sgf_result_o_OBUF[18]_inst_i_8
(.I0(Data_B_i_IBUF[1]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_B_i_IBUF[0]),
.I4(O[1]),
.I5(\Data_B_i[12]_0 ),
.O(\sgf_result_o_OBUF[18]_inst_i_8_n_0 ));
(* HLUTNM = "lutpair89" *)
LUT5 #(
.INIT(32'h7FFF0777))
\sgf_result_o_OBUF[18]_inst_i_9
(.I0(Data_A_i_IBUF[0]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[2]),
.I4(O[0]),
.O(\sgf_result_o_OBUF[18]_inst_i_9_n_0 ));
CARRY4 \sgf_result_o_OBUF[22]_inst_i_1
(.CI(\sgf_result_o_OBUF[18]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[22]_inst_i_1_n_0 ,\sgf_result_o_OBUF[22]_inst_i_1_n_1 ,\sgf_result_o_OBUF[22]_inst_i_1_n_2 ,\sgf_result_o_OBUF[22]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_1_in[22:19]),
.O(\sgf_result_o[47]_5 [11:8]),
.S({\sgf_result_o_OBUF[22]_inst_i_3_n_0 ,\sgf_result_o_OBUF[22]_inst_i_4_n_0 ,\sgf_result_o_OBUF[22]_inst_i_5_n_0 ,\sgf_result_o_OBUF[22]_inst_i_6_n_0 }));
CARRY4 \sgf_result_o_OBUF[22]_inst_i_2
(.CI(\sgf_result_o_OBUF[18]_inst_i_2_n_0 ),
.CO({\sgf_result_o_OBUF[22]_inst_i_2_n_0 ,\sgf_result_o_OBUF[22]_inst_i_2_n_1 ,\sgf_result_o_OBUF[22]_inst_i_2_n_2 ,\sgf_result_o_OBUF[22]_inst_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Data_B_i[17] ),
.O(p_1_in[19:16]),
.S(\Data_B_i[17]_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_3
(.I0(p_1_in[22]),
.I1(\Data_A_i[2]_1 [1]),
.O(\sgf_result_o_OBUF[22]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_4
(.I0(p_1_in[21]),
.I1(\Data_A_i[2]_1 [0]),
.O(\sgf_result_o_OBUF[22]_inst_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_5
(.I0(p_1_in[20]),
.I1(\Data_A_i[2]_0 [3]),
.O(\sgf_result_o_OBUF[22]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[22]_inst_i_6
(.I0(p_1_in[19]),
.I1(\Data_A_i[2]_0 [2]),
.O(\sgf_result_o_OBUF[22]_inst_i_6_n_0 ));
CARRY4 \sgf_result_o_OBUF[26]_inst_i_1
(.CI(\sgf_result_o_OBUF[22]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[26]_inst_i_1_n_0 ,\sgf_result_o_OBUF[26]_inst_i_1_n_1 ,\sgf_result_o_OBUF[26]_inst_i_1_n_2 ,\sgf_result_o_OBUF[26]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_1_in[26:23]),
.O(\sgf_result_o[47]_5 [15:12]),
.S({\sgf_result_o_OBUF[26]_inst_i_3_n_0 ,\sgf_result_o_OBUF[26]_inst_i_4_n_0 ,\sgf_result_o_OBUF[26]_inst_i_5_n_0 ,\sgf_result_o_OBUF[26]_inst_i_6_n_0 }));
CARRY4 \sgf_result_o_OBUF[26]_inst_i_2
(.CI(\sgf_result_o_OBUF[22]_inst_i_2_n_0 ),
.CO({\sgf_result_o_OBUF[26]_inst_i_2_n_0 ,\sgf_result_o_OBUF[26]_inst_i_2_n_1 ,\sgf_result_o_OBUF[26]_inst_i_2_n_2 ,\sgf_result_o_OBUF[26]_inst_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Data_A_i[14] ),
.O(p_1_in[23:20]),
.S(\Data_A_i[14]_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[26]_inst_i_3
(.I0(p_1_in[26]),
.I1(\Data_A_i[17] [0]),
.O(\sgf_result_o_OBUF[26]_inst_i_3_n_0 ));
LUT5 #(
.INIT(32'h956A6A6A))
\sgf_result_o_OBUF[26]_inst_i_4
(.I0(p_1_in[25]),
.I1(Data_B_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[2]),
.I4(Data_B_i_IBUF[3]),
.O(\sgf_result_o_OBUF[26]_inst_i_4_n_0 ));
LUT3 #(
.INIT(8'h6A))
\sgf_result_o_OBUF[26]_inst_i_5
(.I0(p_1_in[24]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_B_i_IBUF[2]),
.O(\sgf_result_o_OBUF[26]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[26]_inst_i_6
(.I0(p_1_in[23]),
.I1(\Data_A_i[2]_1 [2]),
.O(\sgf_result_o_OBUF[26]_inst_i_6_n_0 ));
CARRY4 \sgf_result_o_OBUF[30]_inst_i_1
(.CI(\sgf_result_o_OBUF[26]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[30]_inst_i_1_n_0 ,\sgf_result_o_OBUF[30]_inst_i_1_n_1 ,\sgf_result_o_OBUF[30]_inst_i_1_n_2 ,\sgf_result_o_OBUF[30]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_1_in[30:27]),
.O(\sgf_result_o[47]_5 [19:16]),
.S({\sgf_result_o_OBUF[30]_inst_i_3_n_0 ,\sgf_result_o_OBUF[30]_inst_i_4_n_0 ,\sgf_result_o_OBUF[30]_inst_i_5_n_0 ,\sgf_result_o_OBUF[30]_inst_i_6_n_0 }));
CARRY4 \sgf_result_o_OBUF[30]_inst_i_2
(.CI(\sgf_result_o_OBUF[26]_inst_i_2_n_0 ),
.CO({\sgf_result_o_OBUF[30]_inst_i_2_n_0 ,\sgf_result_o_OBUF[30]_inst_i_2_n_1 ,\sgf_result_o_OBUF[30]_inst_i_2_n_2 ,\sgf_result_o_OBUF[30]_inst_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Data_A_i[13] ),
.O(p_1_in[27:24]),
.S(\Data_A_i[13]_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_3
(.I0(p_1_in[30]),
.I1(\Data_A_i[23] [1]),
.O(\sgf_result_o_OBUF[30]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_4
(.I0(p_1_in[29]),
.I1(\Data_A_i[23] [0]),
.O(\sgf_result_o_OBUF[30]_inst_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_5
(.I0(p_1_in[28]),
.I1(\Data_A_i[17] [2]),
.O(\sgf_result_o_OBUF[30]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[30]_inst_i_6
(.I0(p_1_in[27]),
.I1(\Data_A_i[17] [1]),
.O(\sgf_result_o_OBUF[30]_inst_i_6_n_0 ));
CARRY4 \sgf_result_o_OBUF[34]_inst_i_1
(.CI(\sgf_result_o_OBUF[30]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[34]_inst_i_1_n_0 ,\sgf_result_o_OBUF[34]_inst_i_1_n_1 ,\sgf_result_o_OBUF[34]_inst_i_1_n_2 ,\sgf_result_o_OBUF[34]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_1_in[34:31]),
.O(\sgf_result_o[47]_5 [23:20]),
.S({\sgf_result_o_OBUF[34]_inst_i_3_n_0 ,\sgf_result_o_OBUF[34]_inst_i_4_n_0 ,\sgf_result_o_OBUF[34]_inst_i_5_n_0 ,\sgf_result_o_OBUF[34]_inst_i_6_n_0 }));
CARRY4 \sgf_result_o_OBUF[34]_inst_i_2
(.CI(\sgf_result_o_OBUF[30]_inst_i_2_n_0 ),
.CO({\sgf_result_o_OBUF[34]_inst_i_2_n_0 ,\sgf_result_o_OBUF[34]_inst_i_2_n_1 ,\sgf_result_o_OBUF[34]_inst_i_2_n_2 ,\sgf_result_o_OBUF[34]_inst_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Data_A_i[13]_1 ),
.O(p_1_in[31:28]),
.S(\Data_A_i[13]_2 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_3
(.I0(p_1_in[34]),
.I1(\Data_A_i[23]_0 [1]),
.O(\sgf_result_o_OBUF[34]_inst_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_4
(.I0(p_1_in[33]),
.I1(\Data_A_i[23]_0 [0]),
.O(\sgf_result_o_OBUF[34]_inst_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_5
(.I0(p_1_in[32]),
.I1(\Data_A_i[23] [3]),
.O(\sgf_result_o_OBUF[34]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_6
(.I0(p_1_in[31]),
.I1(\Data_A_i[23] [2]),
.O(\sgf_result_o_OBUF[34]_inst_i_6_n_0 ));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_1
(.CI(\sgf_result_o_OBUF[34]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[38]_inst_i_1_n_0 ,\sgf_result_o_OBUF[38]_inst_i_1_n_1 ,\sgf_result_o_OBUF[38]_inst_i_1_n_2 ,\sgf_result_o_OBUF[38]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,p_1_in[37:35]}),
.O(\sgf_result_o[47]_5 [27:24]),
.S({\Data_A_i[14]_1 ,\sgf_result_o_OBUF[38]_inst_i_5_n_0 ,\sgf_result_o_OBUF[38]_inst_i_6_n_0 ,\sgf_result_o_OBUF[38]_inst_i_7_n_0 }));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_2
(.CI(\sgf_result_o_OBUF[38]_inst_i_3_n_0 ),
.CO({\NLW_sgf_result_o_OBUF[38]_inst_i_2_CO_UNCONNECTED [3:1],\sgf_result_o_OBUF[38]_inst_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Data_A_i[12]_7 }),
.O({\NLW_sgf_result_o_OBUF[38]_inst_i_2_O_UNCONNECTED [3:2],p_1_in[37:36]}),
.S({1'b0,1'b0,\Data_A_i[12]_8 }));
CARRY4 \sgf_result_o_OBUF[38]_inst_i_3
(.CI(\sgf_result_o_OBUF[34]_inst_i_2_n_0 ),
.CO({\sgf_result_o_OBUF[38]_inst_i_3_n_0 ,\sgf_result_o_OBUF[38]_inst_i_3_n_1 ,\sgf_result_o_OBUF[38]_inst_i_3_n_2 ,\sgf_result_o_OBUF[38]_inst_i_3_n_3 }),
.CYINIT(1'b0),
.DI(\Data_A_i[13]_3 ),
.O(p_1_in[35:32]),
.S(\Data_A_i[13]_4 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_5
(.I0(p_1_in[37]),
.I1(\Data_A_i[14]_5 ),
.O(\sgf_result_o_OBUF[38]_inst_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_6
(.I0(p_1_in[36]),
.I1(\Data_A_i[23]_0 [3]),
.O(\sgf_result_o_OBUF[38]_inst_i_6_n_0 ));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_7
(.I0(p_1_in[35]),
.I1(\Data_A_i[23]_0 [2]),
.O(\sgf_result_o_OBUF[38]_inst_i_7_n_0 ));
CARRY4 \sgf_result_o_OBUF[42]_inst_i_1
(.CI(\sgf_result_o_OBUF[38]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[42]_inst_i_1_n_0 ,\sgf_result_o_OBUF[42]_inst_i_1_n_1 ,\sgf_result_o_OBUF[42]_inst_i_1_n_2 ,\sgf_result_o_OBUF[42]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\sgf_result_o[47]_5 [31:28]),
.S(\Data_A_i[14]_2 ));
CARRY4 \sgf_result_o_OBUF[46]_inst_i_1
(.CI(\sgf_result_o_OBUF[42]_inst_i_1_n_0 ),
.CO({\sgf_result_o_OBUF[46]_inst_i_1_n_0 ,\sgf_result_o_OBUF[46]_inst_i_1_n_1 ,\sgf_result_o_OBUF[46]_inst_i_1_n_2 ,\sgf_result_o_OBUF[46]_inst_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\sgf_result_o[47]_5 [35:32]),
.S(\Data_A_i[14]_3 ));
CARRY4 \sgf_result_o_OBUF[47]_inst_i_1
(.CI(\sgf_result_o_OBUF[46]_inst_i_1_n_0 ),
.CO(\NLW_sgf_result_o_OBUF[47]_inst_i_1_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_sgf_result_o_OBUF[47]_inst_i_1_O_UNCONNECTED [3:1],\sgf_result_o[47]_5 [36]}),
.S({1'b0,1'b0,1'b0,\Data_A_i[14]_4 }));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized4
(\sgf_result_o[19] ,
Q_middle_temp__2,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[27] ,
\sgf_result_o[27]_0 ,
\sgf_result_o[15] ,
\sgf_result_o[15]_0 ,
\sgf_result_o[19]_0 ,
\sgf_result_o[19]_1 ,
\sgf_result_o[23] ,
\sgf_result_o[23]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[27]_1 ,
DI,
S,
\Data_A_i[23] ,
\Data_A_i[19] ,
O,
\Data_A_i[18] ,
\Data_A_i[18]_0 ,
\Data_B_i[18] ,
\Data_A_i[18]_1 ,
\Data_B_i[18]_0 ,
\Data_A_i[17] ,
\Data_A_i[23]_0 ,
\Data_A_i[17]_0 ,
\Data_A_i[14] ,
\Data_A_i[20] ,
\Data_A_i[14]_0 ,
\Data_A_i[18]_2 ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[18]_1 ,
\Data_B_i[21] ,
\Data_B_i[19] ,
\Data_B_i[22] ,
\Data_A_i[20]_0 ,
\Data_A_i[23]_1 ,
\Data_A_i[20]_1 ,
\Data_A_i[23]_2 ,
\Data_A_i[20]_2 ,
\Data_A_i[23]_3 ,
\Data_A_i[23]_4 ,
\Data_A_i[23]_5 ,
\Data_A_i[23]_6 ,
\Data_A_i[20]_3 ,
\Data_B_i[22]_0 ,
\Data_A_i[17]_1 ,
\Data_A_i[14]_1 );
output [2:0]\sgf_result_o[19] ;
output [10:0]Q_middle_temp__2;
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[27] ;
output [1:0]\sgf_result_o[27]_0 ;
output [2:0]\sgf_result_o[15] ;
output [3:0]\sgf_result_o[15]_0 ;
output [3:0]\sgf_result_o[19]_0 ;
output [3:0]\sgf_result_o[19]_1 ;
output [3:0]\sgf_result_o[23] ;
output [1:0]\sgf_result_o[23]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [2:0]\sgf_result_o[27]_1 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_A_i[23] ;
input [2:0]\Data_A_i[19] ;
input [3:0]O;
input [3:0]\Data_A_i[18] ;
input [3:0]\Data_A_i[18]_0 ;
input [3:0]\Data_B_i[18] ;
input [0:0]\Data_A_i[18]_1 ;
input [2:0]\Data_B_i[18]_0 ;
input [2:0]\Data_A_i[17] ;
input [3:0]\Data_A_i[23]_0 ;
input [3:0]\Data_A_i[17]_0 ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[20] ;
input [3:0]\Data_A_i[14]_0 ;
input [1:0]\Data_A_i[18]_2 ;
input [3:0]Data_B_i_IBUF;
input [3:0]Data_A_i_IBUF;
input \Data_B_i[18]_1 ;
input \Data_B_i[21] ;
input \Data_B_i[19] ;
input \Data_B_i[22] ;
input \Data_A_i[20]_0 ;
input \Data_A_i[23]_1 ;
input \Data_A_i[20]_1 ;
input \Data_A_i[23]_2 ;
input \Data_A_i[20]_2 ;
input \Data_A_i[23]_3 ;
input [3:0]\Data_A_i[23]_4 ;
input [3:0]\Data_A_i[23]_5 ;
input [3:0]\Data_A_i[23]_6 ;
input [3:0]\Data_A_i[20]_3 ;
input [1:0]\Data_B_i[22]_0 ;
input [3:0]\Data_A_i[17]_1 ;
input [1:0]\Data_A_i[14]_1 ;
wire [2:0]DI;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [1:0]\Data_A_i[14]_1 ;
wire [2:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[17]_0 ;
wire [3:0]\Data_A_i[17]_1 ;
wire [3:0]\Data_A_i[18] ;
wire [3:0]\Data_A_i[18]_0 ;
wire [0:0]\Data_A_i[18]_1 ;
wire [1:0]\Data_A_i[18]_2 ;
wire [2:0]\Data_A_i[19] ;
wire [3:0]\Data_A_i[20] ;
wire \Data_A_i[20]_0 ;
wire \Data_A_i[20]_1 ;
wire \Data_A_i[20]_2 ;
wire [3:0]\Data_A_i[20]_3 ;
wire [2:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire \Data_A_i[23]_1 ;
wire \Data_A_i[23]_2 ;
wire \Data_A_i[23]_3 ;
wire [3:0]\Data_A_i[23]_4 ;
wire [3:0]\Data_A_i[23]_5 ;
wire [3:0]\Data_A_i[23]_6 ;
wire [3:0]Data_A_i_IBUF;
wire [3:0]\Data_B_i[18] ;
wire [2:0]\Data_B_i[18]_0 ;
wire \Data_B_i[18]_1 ;
wire \Data_B_i[19] ;
wire \Data_B_i[21] ;
wire \Data_B_i[22] ;
wire [1:0]\Data_B_i[22]_0 ;
wire [3:0]Data_B_i_IBUF;
wire [3:0]O;
wire [10:0]Q_middle_temp__2;
wire [3:0]S;
wire S_B0__30_carry__0_i_9__0_n_0;
wire S_B0__30_carry__0_i_9__0_n_1;
wire S_B0__30_carry__0_i_9__0_n_2;
wire S_B0__30_carry__0_i_9__0_n_3;
wire S_B0__30_carry__0_n_0;
wire S_B0__30_carry__0_n_1;
wire S_B0__30_carry__0_n_2;
wire S_B0__30_carry__0_n_3;
wire S_B0__30_carry__1_i_9__0_n_3;
wire S_B0__30_carry__1_n_0;
wire S_B0__30_carry__1_n_1;
wire S_B0__30_carry__1_n_2;
wire S_B0__30_carry__1_n_3;
wire S_B0__30_carry__2_n_3;
wire S_B0__30_carry_i_8__0_n_0;
wire S_B0__30_carry_i_8__0_n_1;
wire S_B0__30_carry_i_8__0_n_2;
wire S_B0__30_carry_i_8__0_n_3;
wire S_B0__30_carry_n_0;
wire S_B0__30_carry_n_1;
wire S_B0__30_carry_n_2;
wire S_B0__30_carry_n_3;
wire S_B0_carry__0_n_0;
wire S_B0_carry__0_n_1;
wire S_B0_carry__0_n_2;
wire S_B0_carry__0_n_3;
wire S_B0_carry__1_n_2;
wire S_B0_carry__1_n_3;
wire S_B0_carry_n_0;
wire S_B0_carry_n_1;
wire S_B0_carry_n_2;
wire S_B0_carry_n_3;
wire sgf_result_o0__1_carry__0_n_1;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_4;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [2:0]\sgf_result_o[15] ;
wire [3:0]\sgf_result_o[15]_0 ;
wire [2:0]\sgf_result_o[19] ;
wire [3:0]\^sgf_result_o[19]_0 ;
wire [3:0]\sgf_result_o[19]_1 ;
wire [3:0]\sgf_result_o[23] ;
wire [1:0]\sgf_result_o[23]_0 ;
wire [3:0]\sgf_result_o[27] ;
wire [1:0]\sgf_result_o[27]_0 ;
wire [2:0]\sgf_result_o[27]_1 ;
wire [3:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:1]NLW_S_B0__30_carry__1_i_9__0_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__1_i_9__0_O_UNCONNECTED;
wire [3:1]NLW_S_B0__30_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__2_O_UNCONNECTED;
wire [3:2]NLW_S_B0_carry__1_CO_UNCONNECTED;
wire [3:3]NLW_S_B0_carry__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
assign \sgf_result_o[19]_0 [3] = sgf_result_o0__1_carry__0_n_4;
assign \sgf_result_o[19]_0 [2:0] = \^sgf_result_o[19]_0 [2:0];
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry__0_i_1__2
(.I0(\Data_A_i[20]_2 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[23]_3 ),
.O(\sgf_result_o[19] [1]));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hE8))
S_B0__0_carry__0_i_2__2
(.I0(\Data_A_i[20]_1 ),
.I1(\Data_A_i[23]_2 ),
.I2(sgf_result_o0__1_carry_n_4),
.O(\sgf_result_o[19] [0]));
LUT4 #(
.INIT(16'h4DB2))
S_B0__0_carry__0_i_4__2
(.I0(\Data_B_i[19] ),
.I1(\Data_B_i[22] ),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\sgf_result_o[19] [2]),
.O(\^sgf_result_o[19]_0 [2]));
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry__0_i_5__2
(.I0(\sgf_result_o[19] [1]),
.I1(\Data_B_i[19] ),
.I2(\Data_B_i[22] ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[19]_0 [1]));
(* HLUTNM = "lutpair25" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry__0_i_6__2
(.I0(\Data_A_i[20]_2 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[23]_3 ),
.I3(\sgf_result_o[19] [0]),
.O(\^sgf_result_o[19]_0 [0]));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry_i_1__2
(.I0(\Data_A_i[20]_0 ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[23]_1 ),
.O(\sgf_result_o[15] [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__0_carry_i_2__2
(.I0(Data_B_i_IBUF[3]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_B_i_IBUF[2]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[18]_1 ),
.O(\sgf_result_o[15] [1]));
(* HLUTNM = "lutpair83" *)
LUT5 #(
.INIT(32'h2ABFBFBF))
S_B0__0_carry_i_3__2
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[2]),
.I4(Data_B_i_IBUF[2]),
.O(\sgf_result_o[15] [0]));
(* HLUTNM = "lutpair24" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_4__2
(.I0(\Data_A_i[20]_1 ),
.I1(\Data_A_i[23]_2 ),
.I2(sgf_result_o0__1_carry_n_4),
.I3(\sgf_result_o[15] [2]),
.O(\sgf_result_o[15]_0 [3]));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_5__2
(.I0(\Data_A_i[20]_0 ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[23]_1 ),
.I3(\sgf_result_o[15] [1]),
.O(\sgf_result_o[15]_0 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_6__2
(.I0(\sgf_result_o[15] [0]),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[18]_1 ),
.I3(\Data_B_i[21] ),
.O(\sgf_result_o[15]_0 [1]));
(* HLUTNM = "lutpair83" *)
LUT5 #(
.INIT(32'h6A959595))
S_B0__0_carry_i_7__2
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[2]),
.I4(Data_B_i_IBUF[2]),
.O(\sgf_result_o[15]_0 [0]));
CARRY4 S_B0__30_carry
(.CI(1'b0),
.CO({S_B0__30_carry_n_0,S_B0__30_carry_n_1,S_B0__30_carry_n_2,S_B0__30_carry_n_3}),
.CYINIT(1'b1),
.DI({\Data_A_i[17] ,1'b1}),
.O(\sgf_result_o[47] ),
.S(\Data_A_i[23]_0 ));
CARRY4 S_B0__30_carry__0
(.CI(S_B0__30_carry_n_0),
.CO({S_B0__30_carry__0_n_0,S_B0__30_carry__0_n_1,S_B0__30_carry__0_n_2,S_B0__30_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Data_A_i[17]_0 ),
.O(\sgf_result_o[47]_0 ),
.S(\Data_A_i[14] ));
CARRY4 S_B0__30_carry__0_i_9__0
(.CI(S_B0__30_carry_i_8__0_n_0),
.CO({S_B0__30_carry__0_i_9__0_n_0,S_B0__30_carry__0_i_9__0_n_1,S_B0__30_carry__0_i_9__0_n_2,S_B0__30_carry__0_i_9__0_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[23]_6 [2:0],\Data_A_i[23]_4 [3]}),
.O(\sgf_result_o[23] ),
.S(\Data_A_i[20]_3 ));
CARRY4 S_B0__30_carry__1
(.CI(S_B0__30_carry__0_n_0),
.CO({S_B0__30_carry__1_n_0,S_B0__30_carry__1_n_1,S_B0__30_carry__1_n_2,S_B0__30_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Data_A_i[20] ),
.O(\sgf_result_o[27] ),
.S(\Data_A_i[14]_0 ));
CARRY4 S_B0__30_carry__1_i_9__0
(.CI(S_B0__30_carry__0_i_9__0_n_0),
.CO({NLW_S_B0__30_carry__1_i_9__0_CO_UNCONNECTED[3:1],S_B0__30_carry__1_i_9__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Data_A_i[23]_6 [3]}),
.O({NLW_S_B0__30_carry__1_i_9__0_O_UNCONNECTED[3:2],\sgf_result_o[23]_0 }),
.S({1'b0,1'b0,\Data_B_i[22]_0 }));
CARRY4 S_B0__30_carry__2
(.CI(S_B0__30_carry__1_n_0),
.CO({NLW_S_B0__30_carry__2_CO_UNCONNECTED[3:1],S_B0__30_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp__2[9]}),
.O({NLW_S_B0__30_carry__2_O_UNCONNECTED[3:2],\sgf_result_o[27]_0 }),
.S({1'b0,1'b0,\Data_A_i[18]_2 }));
CARRY4 S_B0__30_carry_i_8__0
(.CI(1'b0),
.CO({S_B0__30_carry_i_8__0_n_0,S_B0__30_carry_i_8__0_n_1,S_B0__30_carry_i_8__0_n_2,S_B0__30_carry_i_8__0_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[23]_4 [2:0],1'b0}),
.O(\sgf_result_o[19]_1 ),
.S(\Data_A_i[23]_5 ));
CARRY4 S_B0_carry
(.CI(1'b0),
.CO({S_B0_carry_n_0,S_B0_carry_n_1,S_B0_carry_n_2,S_B0_carry_n_3}),
.CYINIT(1'b0),
.DI({O[2:0],1'b0}),
.O(Q_middle_temp__2[3:0]),
.S(\Data_A_i[18] ));
CARRY4 S_B0_carry__0
(.CI(S_B0_carry_n_0),
.CO({S_B0_carry__0_n_0,S_B0_carry__0_n_1,S_B0_carry__0_n_2,S_B0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[18]_0 [2:0],O[3]}),
.O(Q_middle_temp__2[7:4]),
.S(\Data_B_i[18] ));
CARRY4 S_B0_carry__1
(.CI(S_B0_carry__0_n_0),
.CO({NLW_S_B0_carry__1_CO_UNCONNECTED[3:2],S_B0_carry__1_n_2,S_B0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Data_A_i[18]_1 ,\Data_A_i[18]_0 [3]}),
.O({NLW_S_B0_carry__1_O_UNCONNECTED[3],Q_middle_temp__2[10:8]}),
.S({1'b0,\Data_B_i[18]_0 }));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_1,sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[23] }),
.O({sgf_result_o0__1_carry__0_n_4,\sgf_result_o[19] [2],sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[19] }));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_17
(.I0(\sgf_result_o[47] [2]),
.I1(\Data_A_i[17]_1 [2]),
.O(\sgf_result_o[47]_1 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_18
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_A_i[17]_1 [1]),
.O(\sgf_result_o[47]_1 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[34]_inst_i_19
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[17]_1 [0]),
.O(\sgf_result_o[47]_1 [0]));
LUT3 #(
.INIT(8'h6A))
\sgf_result_o_OBUF[38]_inst_i_25
(.I0(\sgf_result_o[47]_0 [2]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.O(\sgf_result_o[47]_2 [3]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_26
(.I0(\sgf_result_o[47]_0 [1]),
.I1(\Data_A_i[14]_1 [1]),
.O(\sgf_result_o[47]_2 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_27
(.I0(\sgf_result_o[47]_0 [0]),
.I1(\Data_A_i[14]_1 [0]),
.O(\sgf_result_o[47]_2 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[38]_inst_i_28
(.I0(\sgf_result_o[47] [3]),
.I1(\Data_A_i[17]_1 [3]),
.O(\sgf_result_o[47]_2 [0]));
LUT5 #(
.INIT(32'h956A6A6A))
\sgf_result_o_OBUF[42]_inst_i_10
(.I0(\sgf_result_o[47]_0 [3]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_A_i_IBUF[1]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_3 [0]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[42]_inst_i_7
(.I0(\sgf_result_o[27] [2]),
.I1(\sgf_result_o[19]_1 [2]),
.O(\sgf_result_o[47]_3 [3]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[42]_inst_i_8
(.I0(\sgf_result_o[27] [1]),
.I1(\sgf_result_o[19]_1 [1]),
.O(\sgf_result_o[47]_3 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[42]_inst_i_9
(.I0(\sgf_result_o[27] [0]),
.I1(\sgf_result_o[19]_1 [0]),
.O(\sgf_result_o[47]_3 [1]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[46]_inst_i_10
(.I0(\sgf_result_o[27] [3]),
.I1(\sgf_result_o[19]_1 [3]),
.O(\sgf_result_o[27]_1 [0]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[46]_inst_i_8
(.I0(\sgf_result_o[27]_0 [1]),
.I1(\sgf_result_o[23] [1]),
.O(\sgf_result_o[27]_1 [2]));
LUT2 #(
.INIT(4'h6))
\sgf_result_o_OBUF[46]_inst_i_9
(.I0(\sgf_result_o[27]_0 [0]),
.I1(\sgf_result_o[23] [0]),
.O(\sgf_result_o[27]_1 [1]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized40
(O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
S,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\Data_A_i[12] ,
\Data_A_i[12]_0 ,
\Data_B_i[12] ,
\Data_B_i[12]_0 ,
\Data_A_i[16] ,
\Data_B_i[16] ,
\Data_A_i[16]_0 ,
\Data_B_i[12]_1 ,
\Data_A_i[16]_1 ,
\Data_A_i[16]_2 ,
\Data_A_i[16]_3 ,
\Data_A_i[16]_4 ,
CO,
\Data_A_i[12]_1 ,
\Data_B_i[16]_0 ,
\Data_B_i[12]_2 );
output [3:0]O;
output [1:0]\sgf_result_o[47] ;
output \sgf_result_o[47]_0 ;
output \sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output \sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output \sgf_result_o[47]_6 ;
output \sgf_result_o[47]_7 ;
output [2:0]S;
output [3:0]\sgf_result_o[47]_8 ;
output [0:0]\sgf_result_o[47]_9 ;
input [3:0]\Data_A_i[12] ;
input [2:0]\Data_A_i[12]_0 ;
input [3:0]\Data_B_i[12] ;
input [2:0]\Data_B_i[12]_0 ;
input \Data_A_i[16] ;
input \Data_B_i[16] ;
input \Data_A_i[16]_0 ;
input \Data_B_i[12]_1 ;
input \Data_A_i[16]_1 ;
input \Data_A_i[16]_2 ;
input \Data_A_i[16]_3 ;
input \Data_A_i[16]_4 ;
input [0:0]CO;
input [1:0]\Data_A_i[12]_1 ;
input \Data_B_i[16]_0 ;
input \Data_B_i[12]_2 ;
wire [0:0]CO;
wire [3:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire [1:0]\Data_A_i[12]_1 ;
wire \Data_A_i[16] ;
wire \Data_A_i[16]_0 ;
wire \Data_A_i[16]_1 ;
wire \Data_A_i[16]_2 ;
wire \Data_A_i[16]_3 ;
wire \Data_A_i[16]_4 ;
wire [3:0]\Data_B_i[12] ;
wire [2:0]\Data_B_i[12]_0 ;
wire \Data_B_i[12]_1 ;
wire \Data_B_i[12]_2 ;
wire \Data_B_i[16] ;
wire \Data_B_i[16]_0 ;
wire [3:0]O;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_11 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_8 ;
wire \ODD1.middle_n_9 ;
wire [2:0]S;
wire sgf_result_o1__0_carry__0_n_2;
wire sgf_result_o1__0_carry__0_n_3;
wire sgf_result_o1__0_carry__0_n_5;
wire sgf_result_o1__0_carry_n_0;
wire sgf_result_o1__0_carry_n_1;
wire sgf_result_o1__0_carry_n_2;
wire sgf_result_o1__0_carry_n_3;
wire [1:0]\sgf_result_o[47] ;
wire \sgf_result_o[47]_0 ;
wire \sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_2 ;
wire \sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire \sgf_result_o[47]_6 ;
wire \sgf_result_o[47]_7 ;
wire [3:0]\^sgf_result_o[47]_8 ;
wire [0:0]\sgf_result_o[47]_9 ;
wire [3:2]NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED;
assign \sgf_result_o[47]_8 [3] = sgf_result_o1__0_carry__0_n_5;
assign \sgf_result_o[47]_8 [2:0] = \^sgf_result_o[47]_8 [2:0];
Recursive_KOA__parameterized43 \ODD1.middle
(.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 }),
.\Data_A_i[12] (\Data_A_i[12] ),
.\Data_A_i[12]_0 (\Data_A_i[12]_0 ),
.\Data_A_i[16] (\Data_A_i[16] ),
.\Data_A_i[16]_0 (\Data_A_i[16]_0 ),
.\Data_A_i[16]_1 (\Data_A_i[16]_1 ),
.\Data_A_i[16]_2 (\Data_A_i[16]_2 ),
.\Data_A_i[16]_3 (\Data_A_i[16]_4 ),
.\Data_A_i[16]_4 (\Data_A_i[16]_3 ),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[12]_0 (\Data_B_i[12]_0 ),
.\Data_B_i[12]_1 (\Data_B_i[12]_1 ),
.\Data_B_i[12]_2 (\Data_B_i[12]_2 ),
.\Data_B_i[16] (\Data_B_i[16] ),
.\Data_B_i[16]_0 (\Data_B_i[16]_0 ),
.S({\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }),
.\sgf_result_o[47] (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_5 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_6 ),
.\sgf_result_o[47]_6 ({\ODD1.middle_n_13 ,\ODD1.middle_n_14 }),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_7 ),
.\sgf_result_o[47]_8 ({\ODD1.middle_n_16 ,\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 }));
CARRY4 sgf_result_o1__0_carry
(.CI(1'b0),
.CO({sgf_result_o1__0_carry_n_0,sgf_result_o1__0_carry_n_1,sgf_result_o1__0_carry_n_2,sgf_result_o1__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.middle_n_7 ,\ODD1.middle_n_8 ,\ODD1.middle_n_9 ,1'b1}),
.O(O),
.S({\ODD1.middle_n_16 ,\ODD1.middle_n_17 ,\ODD1.middle_n_18 ,\ODD1.middle_n_19 }));
CARRY4 sgf_result_o1__0_carry__0
(.CI(sgf_result_o1__0_carry_n_0),
.CO({NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED[3:2],sgf_result_o1__0_carry__0_n_2,sgf_result_o1__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\ODD1.middle_n_13 ,\ODD1.middle_n_14 }),
.O({NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED[3],sgf_result_o1__0_carry__0_n_5,\sgf_result_o[47] }),
.S({1'b0,\ODD1.middle_n_10 ,\ODD1.middle_n_11 ,\ODD1.middle_n_12 }));
LUT3 #(
.INIT(8'h2D))
sgf_result_o1__21_carry__1_i_2__1
(.I0(CO),
.I1(\Data_A_i[12]_1 [0]),
.I2(\Data_A_i[12]_1 [1]),
.O(\sgf_result_o[47]_9 ));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_2__1
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_A_i[16]_2 ),
.O(\^sgf_result_o[47]_8 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_3__1
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[16]_4 ),
.O(\^sgf_result_o[47]_8 [1]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_4__1
(.I0(O[3]),
.I1(\Data_A_i[16]_3 ),
.O(\^sgf_result_o[47]_8 [0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_1__1
(.I0(O[2]),
.I1(\Data_A_i[16]_0 ),
.O(S[2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_2__1
(.I0(O[1]),
.I1(\Data_B_i[12]_1 ),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
sgf_result_o1_carry_i_3__2
(.I0(O[0]),
.I1(\Data_B_i[12]_2 ),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized43
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
DI,
S,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\Data_A_i[12] ,
\Data_A_i[12]_0 ,
\Data_B_i[12] ,
\Data_B_i[12]_0 ,
\Data_A_i[16] ,
\Data_B_i[16] ,
\Data_A_i[16]_0 ,
\Data_B_i[12]_1 ,
\Data_A_i[16]_1 ,
\Data_A_i[16]_2 ,
\Data_A_i[16]_3 ,
\Data_B_i[16]_0 ,
\Data_B_i[12]_2 ,
\Data_A_i[16]_4 );
output \sgf_result_o[47] ;
output \sgf_result_o[47]_0 ;
output \sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output \sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output [2:0]DI;
output [2:0]S;
output [1:0]\sgf_result_o[47]_6 ;
output \sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
input [3:0]\Data_A_i[12] ;
input [2:0]\Data_A_i[12]_0 ;
input [3:0]\Data_B_i[12] ;
input [2:0]\Data_B_i[12]_0 ;
input \Data_A_i[16] ;
input \Data_B_i[16] ;
input \Data_A_i[16]_0 ;
input \Data_B_i[12]_1 ;
input \Data_A_i[16]_1 ;
input \Data_A_i[16]_2 ;
input \Data_A_i[16]_3 ;
input \Data_B_i[16]_0 ;
input \Data_B_i[12]_2 ;
input \Data_A_i[16]_4 ;
wire [2:0]DI;
wire [3:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire \Data_A_i[16] ;
wire \Data_A_i[16]_0 ;
wire \Data_A_i[16]_1 ;
wire \Data_A_i[16]_2 ;
wire \Data_A_i[16]_3 ;
wire \Data_A_i[16]_4 ;
wire [3:0]\Data_B_i[12] ;
wire [2:0]\Data_B_i[12]_0 ;
wire \Data_B_i[12]_1 ;
wire \Data_B_i[12]_2 ;
wire \Data_B_i[16] ;
wire \Data_B_i[16]_0 ;
wire [2:0]S;
wire sgf_result_o0__1_carry__0_i_1__8_n_0;
wire sgf_result_o0__1_carry__0_i_2__12_n_0;
wire sgf_result_o0__1_carry__0_i_3__1_n_0;
wire sgf_result_o0__1_carry__0_i_4__8_n_0;
wire sgf_result_o0__1_carry__0_i_7__11_n_0;
wire sgf_result_o0__1_carry__0_i_8__7_n_0;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_i_10__11_n_0;
wire sgf_result_o0__1_carry_i_11__8_n_0;
wire sgf_result_o0__1_carry_i_13__5_n_0;
wire sgf_result_o0__1_carry_i_14__8_n_0;
wire sgf_result_o0__1_carry_i_15__2_n_0;
wire sgf_result_o0__1_carry_i_16__3_n_0;
wire sgf_result_o0__1_carry_i_17__2_n_0;
wire sgf_result_o0__1_carry_i_1__8_n_0;
wire sgf_result_o0__1_carry_i_21__2_n_0;
wire sgf_result_o0__1_carry_i_2__8_n_0;
wire sgf_result_o0__1_carry_i_3__8_n_0;
wire sgf_result_o0__1_carry_i_4__8_n_0;
wire sgf_result_o0__1_carry_i_5__8_n_0;
wire sgf_result_o0__1_carry_i_6__12_n_0;
wire sgf_result_o0__1_carry_i_7__8_n_0;
wire sgf_result_o0__1_carry_i_8__5_n_0;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire \sgf_result_o[47] ;
wire \sgf_result_o[47]_0 ;
wire \sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_2 ;
wire \sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire [1:0]\sgf_result_o[47]_6 ;
wire \sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [3:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o0__1_carry_i_1__8_n_0,sgf_result_o0__1_carry_i_2__8_n_0,sgf_result_o0__1_carry_i_3__8_n_0,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S({sgf_result_o0__1_carry_i_4__8_n_0,sgf_result_o0__1_carry_i_5__8_n_0,sgf_result_o0__1_carry_i_6__12_n_0,sgf_result_o0__1_carry_i_7__8_n_0}));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3:2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sgf_result_o0__1_carry__0_i_1__8_n_0}),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b0,sgf_result_o0__1_carry__0_i_2__12_n_0,sgf_result_o0__1_carry__0_i_3__1_n_0,sgf_result_o0__1_carry__0_i_4__8_n_0}));
LUT6 #(
.INIT(64'h00651075107565C3))
sgf_result_o0__1_carry__0_i_1__8
(.I0(\sgf_result_o[47] ),
.I1(sgf_result_o0__1_carry_i_13__5_n_0),
.I2(\sgf_result_o[47]_0 ),
.I3(\sgf_result_o[47]_1 ),
.I4(\sgf_result_o[47]_2 ),
.I5(sgf_result_o0__1_carry__0_i_7__11_n_0),
.O(sgf_result_o0__1_carry__0_i_1__8_n_0));
LUT3 #(
.INIT(8'h02))
sgf_result_o0__1_carry__0_i_2__12
(.I0(sgf_result_o0__1_carry__0_i_8__7_n_0),
.I1(\sgf_result_o[47] ),
.I2(sgf_result_o0__1_carry_i_17__2_n_0),
.O(sgf_result_o0__1_carry__0_i_2__12_n_0));
LUT4 #(
.INIT(16'h5035))
sgf_result_o0__1_carry__0_i_3__1
(.I0(sgf_result_o0__1_carry_i_17__2_n_0),
.I1(sgf_result_o0__1_carry_i_11__8_n_0),
.I2(sgf_result_o0__1_carry__0_i_8__7_n_0),
.I3(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry__0_i_3__1_n_0));
LUT6 #(
.INIT(64'h040404490B4646B9))
sgf_result_o0__1_carry__0_i_4__8
(.I0(sgf_result_o0__1_carry_i_13__5_n_0),
.I1(\sgf_result_o[47]_0 ),
.I2(\sgf_result_o[47]_1 ),
.I3(\sgf_result_o[47]_2 ),
.I4(sgf_result_o0__1_carry__0_i_7__11_n_0),
.I5(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry__0_i_4__8_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry__0_i_5__1
(.I0(\Data_A_i[12] [0]),
.I1(\Data_A_i[12]_0 [0]),
.I2(\Data_A_i[12] [1]),
.I3(\Data_A_i[12]_0 [1]),
.I4(\Data_A_i[12]_0 [2]),
.I5(\Data_A_i[12] [2]),
.O(\sgf_result_o[47]_1 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry__0_i_6__12
(.I0(\Data_A_i[12]_0 [0]),
.I1(\Data_A_i[12] [0]),
.I2(\Data_A_i[12]_0 [1]),
.I3(\Data_A_i[12] [1]),
.O(\sgf_result_o[47]_2 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry__0_i_7__11
(.I0(\Data_A_i[12] [0]),
.I1(\Data_A_i[12]_0 [0]),
.I2(\Data_A_i[12] [3]),
.I3(\Data_A_i[12] [2]),
.I4(\sgf_result_o[47]_5 ),
.I5(\Data_A_i[12]_0 [2]),
.O(sgf_result_o0__1_carry__0_i_7__11_n_0));
LUT6 #(
.INIT(64'h9000666066606000))
sgf_result_o0__1_carry__0_i_8__7
(.I0(\Data_B_i[12] [1]),
.I1(\Data_B_i[12]_0 [1]),
.I2(sgf_result_o0__1_carry_i_21__2_n_0),
.I3(\Data_B_i[12] [3]),
.I4(\Data_B_i[12]_0 [0]),
.I5(\Data_B_i[12] [0]),
.O(sgf_result_o0__1_carry__0_i_8__7_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_10__11
(.I0(\Data_A_i[12]_0 [2]),
.I1(\sgf_result_o[47]_5 ),
.I2(\Data_A_i[12] [2]),
.I3(\Data_A_i[12] [3]),
.I4(\Data_A_i[12]_0 [0]),
.I5(\Data_A_i[12] [0]),
.O(sgf_result_o0__1_carry_i_10__11_n_0));
LUT6 #(
.INIT(64'h0EF1F108F10808F7))
sgf_result_o0__1_carry_i_11__8
(.I0(\sgf_result_o[47]_4 ),
.I1(\Data_A_i[12] [3]),
.I2(\sgf_result_o[47]_2 ),
.I3(\Data_A_i[12] [2]),
.I4(\Data_A_i[12]_0 [2]),
.I5(\sgf_result_o[47]_5 ),
.O(sgf_result_o0__1_carry_i_11__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h8778))
sgf_result_o0__1_carry_i_12__6
(.I0(\Data_B_i[12]_0 [0]),
.I1(\Data_B_i[12] [0]),
.I2(\Data_B_i[12]_0 [1]),
.I3(\Data_B_i[12] [1]),
.O(\sgf_result_o[47]_0 ));
LUT6 #(
.INIT(64'h0909099F099F9F9F))
sgf_result_o0__1_carry_i_13__5
(.I0(\Data_B_i[12] [0]),
.I1(\Data_B_i[12]_0 [0]),
.I2(\Data_B_i[12] [3]),
.I3(\Data_B_i[12] [2]),
.I4(\sgf_result_o[47]_7 ),
.I5(\Data_B_i[12]_0 [2]),
.O(sgf_result_o0__1_carry_i_13__5_n_0));
LUT6 #(
.INIT(64'hE81717E817E8E817))
sgf_result_o0__1_carry_i_14__8
(.I0(\Data_B_i[12]_0 [2]),
.I1(\sgf_result_o[47]_7 ),
.I2(\Data_B_i[12] [2]),
.I3(\Data_B_i[12] [3]),
.I4(\Data_B_i[12]_0 [0]),
.I5(\Data_B_i[12] [0]),
.O(sgf_result_o0__1_carry_i_14__8_n_0));
LUT3 #(
.INIT(8'h82))
sgf_result_o0__1_carry_i_15__2
(.I0(sgf_result_o0__1_carry_i_8__5_n_0),
.I1(\sgf_result_o[47] ),
.I2(sgf_result_o0__1_carry__0_i_8__7_n_0),
.O(sgf_result_o0__1_carry_i_15__2_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
sgf_result_o0__1_carry_i_16__3
(.I0(\Data_B_i[12] [1]),
.I1(\Data_B_i[12]_0 [1]),
.I2(sgf_result_o0__1_carry_i_21__2_n_0),
.I3(\Data_B_i[12] [3]),
.I4(\Data_B_i[12]_0 [0]),
.I5(\Data_B_i[12] [0]),
.O(sgf_result_o0__1_carry_i_16__3_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF1FF7F77F))
sgf_result_o0__1_carry_i_17__2
(.I0(\sgf_result_o[47]_4 ),
.I1(\Data_A_i[12] [3]),
.I2(\Data_A_i[12] [2]),
.I3(\sgf_result_o[47]_5 ),
.I4(\Data_A_i[12]_0 [2]),
.I5(\sgf_result_o[47]_2 ),
.O(sgf_result_o0__1_carry_i_17__2_n_0));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_18__3
(.I0(\Data_A_i[12]_0 [2]),
.I1(\Data_A_i[12]_0 [1]),
.I2(\Data_A_i[12] [1]),
.I3(\Data_A_i[12]_0 [0]),
.I4(\Data_A_i[12] [0]),
.I5(\Data_A_i[12] [2]),
.O(\sgf_result_o[47]_3 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_19__3
(.I0(\Data_A_i[12]_0 [1]),
.I1(\Data_A_i[12] [1]),
.I2(\Data_A_i[12]_0 [0]),
.I3(\Data_A_i[12] [0]),
.O(\sgf_result_o[47]_5 ));
LUT6 #(
.INIT(64'h22DD22228B8B22DD))
sgf_result_o0__1_carry_i_1__8
(.I0(sgf_result_o0__1_carry_i_8__5_n_0),
.I1(\sgf_result_o[47] ),
.I2(sgf_result_o0__1_carry_i_10__11_n_0),
.I3(sgf_result_o0__1_carry_i_11__8_n_0),
.I4(\sgf_result_o[47]_0 ),
.I5(sgf_result_o0__1_carry_i_13__5_n_0),
.O(sgf_result_o0__1_carry_i_1__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_20__2
(.I0(\Data_B_i[12]_0 [1]),
.I1(\Data_B_i[12] [1]),
.I2(\Data_B_i[12]_0 [0]),
.I3(\Data_B_i[12] [0]),
.O(\sgf_result_o[47]_7 ));
LUT6 #(
.INIT(64'hFEEAEAEAA8808080))
sgf_result_o0__1_carry_i_21__2
(.I0(\Data_B_i[12]_0 [2]),
.I1(\Data_B_i[12]_0 [1]),
.I2(\Data_B_i[12] [1]),
.I3(\Data_B_i[12]_0 [0]),
.I4(\Data_B_i[12] [0]),
.I5(\Data_B_i[12] [2]),
.O(sgf_result_o0__1_carry_i_21__2_n_0));
LUT5 #(
.INIT(32'hA30A9039))
sgf_result_o0__1_carry_i_2__8
(.I0(sgf_result_o0__1_carry_i_8__5_n_0),
.I1(sgf_result_o0__1_carry_i_10__11_n_0),
.I2(sgf_result_o0__1_carry_i_13__5_n_0),
.I3(\sgf_result_o[47]_0 ),
.I4(\sgf_result_o[47] ),
.O(sgf_result_o0__1_carry_i_2__8_n_0));
LUT2 #(
.INIT(4'h2))
sgf_result_o0__1_carry_i_3__8
(.I0(sgf_result_o0__1_carry_i_8__5_n_0),
.I1(sgf_result_o0__1_carry_i_14__8_n_0),
.O(sgf_result_o0__1_carry_i_3__8_n_0));
LUT6 #(
.INIT(64'hAA6AAA6AAA6A5555))
sgf_result_o0__1_carry_i_4__8
(.I0(sgf_result_o0__1_carry_i_1__8_n_0),
.I1(sgf_result_o0__1_carry_i_15__2_n_0),
.I2(sgf_result_o0__1_carry_i_16__3_n_0),
.I3(sgf_result_o0__1_carry_i_10__11_n_0),
.I4(sgf_result_o0__1_carry_i_17__2_n_0),
.I5(sgf_result_o0__1_carry_i_14__8_n_0),
.O(sgf_result_o0__1_carry_i_4__8_n_0));
LUT3 #(
.INIT(8'hA9))
sgf_result_o0__1_carry_i_5__8
(.I0(sgf_result_o0__1_carry_i_2__8_n_0),
.I1(sgf_result_o0__1_carry_i_14__8_n_0),
.I2(sgf_result_o0__1_carry_i_11__8_n_0),
.O(sgf_result_o0__1_carry_i_5__8_n_0));
LUT4 #(
.INIT(16'h44B4))
sgf_result_o0__1_carry_i_6__12
(.I0(sgf_result_o0__1_carry_i_14__8_n_0),
.I1(sgf_result_o0__1_carry_i_8__5_n_0),
.I2(sgf_result_o0__1_carry_i_16__3_n_0),
.I3(sgf_result_o0__1_carry_i_10__11_n_0),
.O(sgf_result_o0__1_carry_i_6__12_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry_i_7__8
(.I0(sgf_result_o0__1_carry_i_10__11_n_0),
.I1(sgf_result_o0__1_carry_i_14__8_n_0),
.O(sgf_result_o0__1_carry_i_7__8_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
sgf_result_o0__1_carry_i_8__5
(.I0(\Data_A_i[12] [1]),
.I1(\Data_A_i[12]_0 [1]),
.I2(\sgf_result_o[47]_3 ),
.I3(\Data_A_i[12] [3]),
.I4(\Data_A_i[12]_0 [0]),
.I5(\Data_A_i[12] [0]),
.O(sgf_result_o0__1_carry_i_8__5_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry_i_9__1
(.I0(\Data_B_i[12] [0]),
.I1(\Data_B_i[12]_0 [0]),
.I2(\Data_B_i[12] [1]),
.I3(\Data_B_i[12]_0 [1]),
.I4(\Data_B_i[12]_0 [2]),
.I5(\Data_B_i[12] [2]),
.O(\sgf_result_o[47] ));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__0_carry__0_i_1__1
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_B_i[12]_1 ),
.O(\sgf_result_o[47]_6 [1]));
(* HLUTNM = "lutpair41" *)
LUT2 #(
.INIT(4'hE))
sgf_result_o1__0_carry__0_i_2__1
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[12]_2 ),
.O(\sgf_result_o[47]_6 [0]));
LUT3 #(
.INIT(8'h59))
sgf_result_o1__0_carry__0_i_3__1
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(\Data_A_i[16]_0 ),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(S[2]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__0_carry__0_i_4__1
(.I0(\Data_B_i[12]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[16]_0 ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(S[1]));
LUT3 #(
.INIT(8'h96))
sgf_result_o1__0_carry__0_i_5__1
(.I0(\sgf_result_o[47]_6 [0]),
.I1(\Data_B_i[12]_1 ),
.I2(sgf_result_o0__1_carry__0_n_7),
.O(S[0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_12__1
(.I0(\Data_A_i[12] [0]),
.I1(\Data_A_i[12]_0 [0]),
.O(\sgf_result_o[47]_4 ));
LUT3 #(
.INIT(8'h71))
sgf_result_o1__0_carry_i_1__1
(.I0(\Data_A_i[16]_1 ),
.I1(\Data_A_i[16]_2 ),
.I2(sgf_result_o0__1_carry_n_5),
.O(DI[2]));
(* HLUTNM = "lutpair40" *)
LUT3 #(
.INIT(8'h71))
sgf_result_o1__0_carry_i_2__1
(.I0(\Data_A_i[16]_3 ),
.I1(\Data_B_i[16]_0 ),
.I2(sgf_result_o0__1_carry_n_6),
.O(DI[1]));
LUT6 #(
.INIT(64'hA22AFBBFFBBFFBBF))
sgf_result_o1__0_carry_i_3__1
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\sgf_result_o[47]_4 ),
.I2(\Data_B_i[12] [0]),
.I3(\Data_B_i[12]_0 [0]),
.I4(\Data_A_i[16] ),
.I5(\Data_B_i[16] ),
.O(DI[0]));
(* HLUTNM = "lutpair41" *)
LUT5 #(
.INIT(32'h99696966))
sgf_result_o1__0_carry_i_4__1
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_B_i[12]_2 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[16]_2 ),
.I4(\Data_A_i[16]_1 ),
.O(\sgf_result_o[47]_8 [3]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_5__1
(.I0(DI[1]),
.I1(\Data_A_i[16]_1 ),
.I2(sgf_result_o0__1_carry_n_5),
.I3(\Data_A_i[16]_2 ),
.O(\sgf_result_o[47]_8 [2]));
(* HLUTNM = "lutpair40" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_6__1
(.I0(\Data_A_i[16]_3 ),
.I1(\Data_B_i[16]_0 ),
.I2(sgf_result_o0__1_carry_n_6),
.I3(DI[0]),
.O(\sgf_result_o[47]_8 [1]));
LUT6 #(
.INIT(64'h9999966996699999))
sgf_result_o1__0_carry_i_7__1
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[16]_4 ),
.I2(\Data_B_i[12]_0 [0]),
.I3(\Data_B_i[12] [0]),
.I4(\Data_A_i[12]_0 [0]),
.I5(\Data_A_i[12] [0]),
.O(\sgf_result_o[47]_8 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized44
(CO,
O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[15] ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[15]_0 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
DI,
S,
\Data_B_i[16] ,
\Data_A_i[16] ,
\Data_A_i[20] ,
\Data_A_i[20]_0 ,
\Data_B_i[20] ,
\Data_A_i[20]_1 ,
\Data_A_i[12] ,
\Data_B_i[12] ,
\Data_A_i[12]_0 ,
\Data_A_i[12]_1 ,
\Data_B_i[12]_0 ,
\Data_B_i[12]_1 ,
\Data_B_i[12]_2 ,
\Data_B_i[12]_3 ,
\Data_B_i[16]_0 ,
\Data_B_i[20]_0 ,
\Data_A_i[12]_2 ,
\Data_A_i[16]_0 ,
\Data_A_i[20]_2 );
output [0:0]CO;
output [3:0]O;
output [3:0]\sgf_result_o[47] ;
output [1:0]\sgf_result_o[47]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [2:0]\sgf_result_o[47]_3 ;
output [0:0]\sgf_result_o[15] ;
output [3:0]\sgf_result_o[47]_4 ;
output [2:0]\sgf_result_o[47]_5 ;
output [0:0]\sgf_result_o[15]_0 ;
output [3:0]\sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [3:0]\sgf_result_o[47]_8 ;
output [2:0]\sgf_result_o[47]_9 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[16] ;
input [2:0]\Data_A_i[16] ;
input [2:0]\Data_A_i[20] ;
input [3:0]\Data_A_i[20]_0 ;
input [2:0]\Data_B_i[20] ;
input [2:0]\Data_A_i[20]_1 ;
input [2:0]\Data_A_i[12] ;
input [0:0]\Data_B_i[12] ;
input [3:0]\Data_A_i[12]_0 ;
input [0:0]\Data_A_i[12]_1 ;
input [3:0]\Data_B_i[12]_0 ;
input \Data_B_i[12]_1 ;
input [0:0]\Data_B_i[12]_2 ;
input [3:0]\Data_B_i[12]_3 ;
input [3:0]\Data_B_i[16]_0 ;
input [1:0]\Data_B_i[20]_0 ;
input [3:0]\Data_A_i[12]_2 ;
input [3:0]\Data_A_i[16]_0 ;
input [1:0]\Data_A_i[20]_2 ;
wire [0:0]CO;
wire [2:0]DI;
wire [2:0]\Data_A_i[12] ;
wire [3:0]\Data_A_i[12]_0 ;
wire [0:0]\Data_A_i[12]_1 ;
wire [3:0]\Data_A_i[12]_2 ;
wire [2:0]\Data_A_i[16] ;
wire [3:0]\Data_A_i[16]_0 ;
wire [2:0]\Data_A_i[20] ;
wire [3:0]\Data_A_i[20]_0 ;
wire [2:0]\Data_A_i[20]_1 ;
wire [1:0]\Data_A_i[20]_2 ;
wire [0:0]\Data_B_i[12] ;
wire [3:0]\Data_B_i[12]_0 ;
wire \Data_B_i[12]_1 ;
wire [0:0]\Data_B_i[12]_2 ;
wire [3:0]\Data_B_i[12]_3 ;
wire [2:0]\Data_B_i[16] ;
wire [3:0]\Data_B_i[16]_0 ;
wire [2:0]\Data_B_i[20] ;
wire [1:0]\Data_B_i[20]_0 ;
wire \EVEN1.left_high_n_0 ;
wire \EVEN1.left_high_n_1 ;
wire \EVEN1.left_high_n_10 ;
wire \EVEN1.left_high_n_11 ;
wire \EVEN1.left_high_n_19 ;
wire \EVEN1.left_high_n_2 ;
wire \EVEN1.left_high_n_20 ;
wire \EVEN1.left_high_n_21 ;
wire \EVEN1.left_high_n_4 ;
wire \EVEN1.left_high_n_5 ;
wire \EVEN1.left_high_n_6 ;
wire \EVEN1.left_high_n_7 ;
wire \EVEN1.left_high_n_8 ;
wire \EVEN1.left_high_n_9 ;
wire \EVEN1.middle_n_18 ;
wire \EVEN1.middle_n_26 ;
wire \EVEN1.middle_n_28 ;
wire \EVEN1.middle_n_29 ;
wire \EVEN1.middle_n_30 ;
wire \EVEN1.middle_n_31 ;
wire \EVEN1.middle_n_39 ;
wire \EVEN1.middle_n_40 ;
wire \EVEN1.middle_n_42 ;
wire \EVEN1.middle_n_43 ;
wire \EVEN1.right_lower_n_0 ;
wire \EVEN1.right_lower_n_1 ;
wire \EVEN1.right_lower_n_10 ;
wire \EVEN1.right_lower_n_11 ;
wire \EVEN1.right_lower_n_12 ;
wire \EVEN1.right_lower_n_2 ;
wire \EVEN1.right_lower_n_21 ;
wire \EVEN1.right_lower_n_22 ;
wire \EVEN1.right_lower_n_3 ;
wire \EVEN1.right_lower_n_4 ;
wire \EVEN1.right_lower_n_5 ;
wire \EVEN1.right_lower_n_6 ;
wire [3:0]O;
wire [9:2]Q_middle_temp__4;
wire [3:0]S;
wire S_B0__21_carry__1_i_1_n_0;
wire S_B0_carry_i_4_n_0;
wire S_B0_carry_i_5_n_0;
wire sgf_result_o1__0_carry__0_i_6__2_n_0;
wire sgf_result_o1__0_carry__0_i_7__2_n_0;
wire sgf_result_o1__0_carry_i_10__2_n_0;
wire sgf_result_o1__0_carry_i_11__2_n_0;
wire sgf_result_o1__0_carry_i_13_n_0;
wire sgf_result_o1__0_carry_i_14__2_n_0;
wire sgf_result_o1__0_carry_i_15__2_n_0;
wire sgf_result_o1__0_carry_i_8__2_n_0;
wire sgf_result_o1__0_carry_i_9__2_n_0;
wire [0:0]\sgf_result_o[15] ;
wire [0:0]\sgf_result_o[15]_0 ;
wire [3:0]\sgf_result_o[47] ;
wire [1:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [2:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [2:0]\sgf_result_o[47]_5 ;
wire [3:0]\sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [2:0]\sgf_result_o[47]_9 ;
Recursive_KOA__parameterized45 \EVEN1.left_high
(.CO(CO),
.DI({\EVEN1.left_high_n_8 ,\EVEN1.left_high_n_9 ,\EVEN1.left_high_n_10 ,\EVEN1.left_high_n_11 }),
.\Data_A_i[16] ({\EVEN1.right_lower_n_0 ,\EVEN1.right_lower_n_1 ,\EVEN1.right_lower_n_2 }),
.\Data_A_i[16]_0 (\sgf_result_o[47]_2 [0]),
.\Data_A_i[20] (\Data_A_i[20] ),
.\Data_A_i[20]_0 (\Data_A_i[20]_0 ),
.\Data_A_i[20]_1 (\Data_A_i[20]_1 ),
.\Data_A_i[20]_2 (\sgf_result_o[47] ),
.\Data_A_i[20]_3 (\sgf_result_o[47]_0 ),
.\Data_A_i[20]_4 (\sgf_result_o[47]_3 [0]),
.\Data_B_i[16] (\EVEN1.right_lower_n_3 ),
.\Data_B_i[16]_0 ({\EVEN1.right_lower_n_4 ,\EVEN1.right_lower_n_5 ,\EVEN1.right_lower_n_6 }),
.\Data_B_i[16]_1 (\sgf_result_o[47]_4 [0]),
.\Data_B_i[20] (\Data_B_i[20] ),
.\Data_B_i[20]_0 (\sgf_result_o[47]_5 [0]),
.O({\EVEN1.left_high_n_0 ,\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 }),
.Q_middle_temp__4(Q_middle_temp__4[7:2]),
.S({\EVEN1.left_high_n_4 ,\EVEN1.left_high_n_5 ,\EVEN1.left_high_n_6 ,\EVEN1.left_high_n_7 }),
.\sgf_result_o[47] (\sgf_result_o[47]_7 [3:1]),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_8 ),
.\sgf_result_o[47]_1 (\EVEN1.left_high_n_19 ),
.\sgf_result_o[47]_2 ({\EVEN1.left_high_n_20 ,\EVEN1.left_high_n_21 }));
Recursive_KOA__parameterized47 \EVEN1.middle
(.CO(\sgf_result_o[15] ),
.DI({\EVEN1.left_high_n_19 ,\EVEN1.right_lower_n_10 ,\EVEN1.right_lower_n_11 }),
.\Data_A_i[12] (\Data_A_i[12]_2 ),
.\Data_A_i[12]_0 (\Data_A_i[12]_0 [2:0]),
.\Data_A_i[16] (\Data_A_i[16]_0 ),
.\Data_A_i[20] ({\EVEN1.left_high_n_20 ,\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 ,\EVEN1.left_high_n_21 }),
.\Data_A_i[20]_0 ({S_B0__21_carry__1_i_1_n_0,\EVEN1.right_lower_n_12 }),
.\Data_A_i[20]_1 (sgf_result_o1__0_carry__0_i_7__2_n_0),
.\Data_A_i[20]_2 (sgf_result_o1__0_carry_i_13_n_0),
.\Data_A_i[20]_3 (sgf_result_o1__0_carry_i_15__2_n_0),
.\Data_A_i[20]_4 (sgf_result_o1__0_carry_i_10__2_n_0),
.\Data_A_i[20]_5 (sgf_result_o1__0_carry_i_8__2_n_0),
.\Data_A_i[20]_6 (\Data_A_i[20]_2 ),
.\Data_B_i[12] (\Data_B_i[12]_3 ),
.\Data_B_i[12]_0 (\Data_B_i[12]_0 [2:0]),
.\Data_B_i[16] (\Data_B_i[16]_0 ),
.\Data_B_i[20] ({\EVEN1.left_high_n_8 ,\EVEN1.left_high_n_9 ,\EVEN1.left_high_n_10 ,\EVEN1.left_high_n_11 }),
.\Data_B_i[20]_0 ({\EVEN1.left_high_n_4 ,\EVEN1.left_high_n_5 ,\EVEN1.left_high_n_6 ,\EVEN1.left_high_n_7 }),
.\Data_B_i[20]_1 (sgf_result_o1__0_carry__0_i_6__2_n_0),
.\Data_B_i[20]_2 (sgf_result_o1__0_carry_i_11__2_n_0),
.\Data_B_i[20]_3 (sgf_result_o1__0_carry_i_9__2_n_0),
.\Data_B_i[20]_4 (sgf_result_o1__0_carry_i_14__2_n_0),
.\Data_B_i[20]_5 (\Data_B_i[20]_0 ),
.O(O),
.Q_middle_temp__4(Q_middle_temp__4),
.S(S_B0_carry_i_4_n_0),
.\sgf_result_o[15] (\EVEN1.middle_n_28 ),
.\sgf_result_o[15]_0 (\EVEN1.middle_n_30 ),
.\sgf_result_o[15]_1 (\EVEN1.middle_n_39 ),
.\sgf_result_o[15]_2 (\EVEN1.middle_n_40 ),
.\sgf_result_o[15]_3 (\sgf_result_o[15]_0 ),
.\sgf_result_o[47] (\sgf_result_o[47] ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_1 (\EVEN1.middle_n_18 ),
.\sgf_result_o[47]_10 (\EVEN1.middle_n_43 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_4 (\EVEN1.middle_n_26 ),
.\sgf_result_o[47]_5 (\EVEN1.middle_n_29 ),
.\sgf_result_o[47]_6 (\EVEN1.middle_n_31 ),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_8 (\sgf_result_o[47]_5 ),
.\sgf_result_o[47]_9 (\EVEN1.middle_n_42 ));
Recursive_KOA__parameterized46 \EVEN1.right_lower
(.CO(CO),
.DI(DI),
.\Data_A_i[12] (\Data_A_i[12] ),
.\Data_A_i[12]_0 (\Data_A_i[12]_0 [3]),
.\Data_A_i[12]_1 (\Data_A_i[12]_1 ),
.\Data_A_i[16] (\Data_A_i[16] ),
.\Data_A_i[16]_0 (\sgf_result_o[47]_2 [0]),
.\Data_A_i[20] (\sgf_result_o[47]_3 [0]),
.\Data_A_i[20]_0 (O),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[12]_0 (\Data_B_i[12]_0 [3]),
.\Data_B_i[12]_1 (\Data_B_i[12]_1 ),
.\Data_B_i[12]_2 (\Data_B_i[12]_2 ),
.\Data_B_i[16] (\Data_B_i[16] ),
.\Data_B_i[16]_0 (\sgf_result_o[47]_4 [0]),
.\Data_B_i[20] (\sgf_result_o[47]_5 [0]),
.\Data_B_i[20]_0 (sgf_result_o1__0_carry_i_11__2_n_0),
.O({\EVEN1.left_high_n_0 ,\EVEN1.left_high_n_1 ,\EVEN1.left_high_n_2 }),
.Q_middle_temp__4({Q_middle_temp__4[8:7],Q_middle_temp__4[2]}),
.S(S),
.\sgf_result_o[47] ({\EVEN1.right_lower_n_0 ,\EVEN1.right_lower_n_1 ,\EVEN1.right_lower_n_2 }),
.\sgf_result_o[47]_0 (\EVEN1.right_lower_n_3 ),
.\sgf_result_o[47]_1 ({\EVEN1.right_lower_n_4 ,\EVEN1.right_lower_n_5 ,\EVEN1.right_lower_n_6 }),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_3 ({\EVEN1.right_lower_n_10 ,\EVEN1.right_lower_n_11 }),
.\sgf_result_o[47]_4 (\EVEN1.right_lower_n_12 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_6 ),
.\sgf_result_o[47]_6 (\sgf_result_o[47]_7 [0]),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_9 ),
.\sgf_result_o[47]_8 ({\EVEN1.right_lower_n_21 ,\EVEN1.right_lower_n_22 }));
LUT1 #(
.INIT(2'h1))
S_B0__21_carry__1_i_1
(.I0(Q_middle_temp__4[9]),
.O(S_B0__21_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
S_B0_carry_i_4
(.I0(S_B0_carry_i_5_n_0),
.I1(\EVEN1.middle_n_18 ),
.I2(\EVEN1.middle_n_31 ),
.I3(\EVEN1.middle_n_29 ),
.I4(\sgf_result_o[47]_5 [0]),
.I5(\sgf_result_o[47]_4 [0]),
.O(S_B0_carry_i_4_n_0));
LUT5 #(
.INIT(32'h00009666))
S_B0_carry_i_5
(.I0(\sgf_result_o[47]_4 [1]),
.I1(\sgf_result_o[47]_5 [1]),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[47]_5 [0]),
.I4(\EVEN1.middle_n_26 ),
.O(S_B0_carry_i_5_n_0));
LUT6 #(
.INIT(64'h0400464B04000B0B))
sgf_result_o1__0_carry__0_i_6__2
(.I0(\EVEN1.middle_n_26 ),
.I1(\EVEN1.middle_n_42 ),
.I2(\EVEN1.middle_n_18 ),
.I3(\EVEN1.middle_n_31 ),
.I4(\EVEN1.middle_n_29 ),
.I5(\EVEN1.middle_n_43 ),
.O(sgf_result_o1__0_carry__0_i_6__2_n_0));
LUT6 #(
.INIT(64'h0020000000330020))
sgf_result_o1__0_carry__0_i_7__2
(.I0(\EVEN1.middle_n_43 ),
.I1(\EVEN1.middle_n_29 ),
.I2(\EVEN1.middle_n_31 ),
.I3(\EVEN1.middle_n_18 ),
.I4(\EVEN1.middle_n_42 ),
.I5(\EVEN1.middle_n_26 ),
.O(sgf_result_o1__0_carry__0_i_7__2_n_0));
LUT6 #(
.INIT(64'h698E8E00E769698E))
sgf_result_o1__0_carry_i_10__2
(.I0(\sgf_result_o[15]_0 ),
.I1(\sgf_result_o[47]_4 [3]),
.I2(\EVEN1.middle_n_40 ),
.I3(\sgf_result_o[47]_2 [3]),
.I4(\sgf_result_o[15] ),
.I5(\EVEN1.middle_n_28 ),
.O(sgf_result_o1__0_carry_i_10__2_n_0));
LUT6 #(
.INIT(64'h6060609F609F6060))
sgf_result_o1__0_carry_i_11__2
(.I0(\sgf_result_o[47]_2 [0]),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\EVEN1.middle_n_42 ),
.I3(\EVEN1.middle_n_26 ),
.I4(\sgf_result_o[47]_4 [0]),
.I5(\sgf_result_o[47]_5 [0]),
.O(sgf_result_o1__0_carry_i_11__2_n_0));
LUT6 #(
.INIT(64'h0000000008000000))
sgf_result_o1__0_carry_i_13
(.I0(\sgf_result_o[15]_0 ),
.I1(\sgf_result_o[47]_4 [3]),
.I2(\EVEN1.middle_n_40 ),
.I3(\sgf_result_o[47]_2 [3]),
.I4(\sgf_result_o[15] ),
.I5(\EVEN1.middle_n_28 ),
.O(sgf_result_o1__0_carry_i_13_n_0));
LUT6 #(
.INIT(64'hBEFA7D72FEFA3236))
sgf_result_o1__0_carry_i_14__2
(.I0(\EVEN1.middle_n_26 ),
.I1(\EVEN1.middle_n_42 ),
.I2(\EVEN1.middle_n_18 ),
.I3(\EVEN1.middle_n_31 ),
.I4(\EVEN1.middle_n_29 ),
.I5(\EVEN1.middle_n_43 ),
.O(sgf_result_o1__0_carry_i_14__2_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o1__0_carry_i_15__2
(.I0(\EVEN1.middle_n_39 ),
.I1(\EVEN1.middle_n_30 ),
.O(sgf_result_o1__0_carry_i_15__2_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1__0_carry_i_8__2
(.I0(S_B0_carry_i_5_n_0),
.I1(\EVEN1.middle_n_18 ),
.I2(\EVEN1.middle_n_31 ),
.I3(\EVEN1.middle_n_29 ),
.I4(\sgf_result_o[47]_5 [0]),
.I5(\sgf_result_o[47]_4 [0]),
.O(sgf_result_o1__0_carry_i_8__2_n_0));
LUT6 #(
.INIT(64'h71FFFFFF797171FF))
sgf_result_o1__0_carry_i_9__2
(.I0(\sgf_result_o[47]_2 [3]),
.I1(\sgf_result_o[15] ),
.I2(\EVEN1.middle_n_28 ),
.I3(\sgf_result_o[47]_4 [3]),
.I4(\sgf_result_o[15]_0 ),
.I5(\EVEN1.middle_n_40 ),
.O(sgf_result_o1__0_carry_i_9__2_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized45
(O,
CO,
S,
DI,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\Data_A_i[20] ,
\Data_A_i[20]_0 ,
\Data_B_i[20] ,
\Data_A_i[20]_1 ,
Q_middle_temp__4,
\Data_B_i[16] ,
\Data_A_i[20]_2 ,
\Data_A_i[20]_3 ,
\Data_A_i[16] ,
\Data_B_i[16]_0 ,
\Data_A_i[16]_0 ,
\Data_A_i[20]_4 ,
\Data_B_i[16]_1 ,
\Data_B_i[20]_0 );
output [2:0]O;
output [0:0]CO;
output [3:0]S;
output [3:0]DI;
output [2:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [0:0]\sgf_result_o[47]_1 ;
output [1:0]\sgf_result_o[47]_2 ;
input [2:0]\Data_A_i[20] ;
input [3:0]\Data_A_i[20]_0 ;
input [2:0]\Data_B_i[20] ;
input [2:0]\Data_A_i[20]_1 ;
input [5:0]Q_middle_temp__4;
input [0:0]\Data_B_i[16] ;
input [3:0]\Data_A_i[20]_2 ;
input [1:0]\Data_A_i[20]_3 ;
input [2:0]\Data_A_i[16] ;
input [2:0]\Data_B_i[16]_0 ;
input [0:0]\Data_A_i[16]_0 ;
input [0:0]\Data_A_i[20]_4 ;
input [0:0]\Data_B_i[16]_1 ;
input [0:0]\Data_B_i[20]_0 ;
wire [0:0]CO;
wire [3:0]DI;
wire [2:0]\Data_A_i[16] ;
wire [0:0]\Data_A_i[16]_0 ;
wire [2:0]\Data_A_i[20] ;
wire [3:0]\Data_A_i[20]_0 ;
wire [2:0]\Data_A_i[20]_1 ;
wire [3:0]\Data_A_i[20]_2 ;
wire [1:0]\Data_A_i[20]_3 ;
wire [0:0]\Data_A_i[20]_4 ;
wire [0:0]\Data_B_i[16] ;
wire [2:0]\Data_B_i[16]_0 ;
wire [0:0]\Data_B_i[16]_1 ;
wire [2:0]\Data_B_i[20] ;
wire [0:0]\Data_B_i[20]_0 ;
wire [2:0]O;
wire [5:0]Q_middle_temp__4;
wire [3:0]S;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\^sgf_result_o[47]_0 ;
wire [0:0]\sgf_result_o[47]_1 ;
wire [1:0]\sgf_result_o[47]_2 ;
wire [2:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
assign \sgf_result_o[47]_0 [3] = sgf_result_o0__1_carry__0_n_5;
assign \sgf_result_o[47]_0 [2:0] = \^sgf_result_o[47]_0 [2:0];
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry__0_i_1
(.I0(Q_middle_temp__4[4]),
.I1(sgf_result_o0__1_carry__0_n_5),
.I2(\Data_B_i[16]_0 [2]),
.O(DI[3]));
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry__0_i_2
(.I0(Q_middle_temp__4[3]),
.I1(sgf_result_o0__1_carry__0_n_6),
.I2(\Data_B_i[16]_0 [1]),
.O(DI[2]));
(* HLUTNM = "lutpair51" *)
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry__0_i_3
(.I0(Q_middle_temp__4[2]),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_B_i[16]_0 [0]),
.O(DI[1]));
(* HLUTNM = "lutpair50" *)
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry__0_i_4
(.I0(Q_middle_temp__4[1]),
.I1(sgf_result_o0__1_carry_n_4),
.I2(\Data_A_i[16] [2]),
.O(DI[0]));
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry__0_i_5
(.I0(DI[3]),
.I1(Q_middle_temp__4[5]),
.I2(CO),
.I3(\Data_B_i[16] ),
.O(S[3]));
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry__0_i_6
(.I0(Q_middle_temp__4[4]),
.I1(sgf_result_o0__1_carry__0_n_5),
.I2(\Data_B_i[16]_0 [2]),
.I3(DI[2]),
.O(S[2]));
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry__0_i_7
(.I0(Q_middle_temp__4[3]),
.I1(sgf_result_o0__1_carry__0_n_6),
.I2(\Data_B_i[16]_0 [1]),
.I3(DI[1]),
.O(S[1]));
(* HLUTNM = "lutpair51" *)
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry__0_i_8
(.I0(Q_middle_temp__4[2]),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_B_i[16]_0 [0]),
.I3(DI[0]),
.O(S[0]));
(* HLUTNM = "lutpair49" *)
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry_i_1
(.I0(Q_middle_temp__4[0]),
.I1(O[2]),
.I2(\Data_A_i[16] [1]),
.O(\sgf_result_o[47]_1 ));
(* HLUTNM = "lutpair50" *)
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry_i_4
(.I0(Q_middle_temp__4[1]),
.I1(sgf_result_o0__1_carry_n_4),
.I2(\Data_A_i[16] [2]),
.I3(\sgf_result_o[47]_1 ),
.O(\sgf_result_o[47]_2 [1]));
LUT6 #(
.INIT(64'hF99F06600660F99F))
S_B0__21_carry_i_7
(.I0(\Data_A_i[16]_0 ),
.I1(\Data_A_i[20]_4 ),
.I2(\Data_B_i[16]_1 ),
.I3(\Data_B_i[20]_0 ),
.I4(O[0]),
.I5(\Data_A_i[16] [0]),
.O(\sgf_result_o[47]_2 [0]));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[20] ,1'b0}),
.O({sgf_result_o0__1_carry_n_4,O}),
.S(\Data_A_i[20]_0 ));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({CO,NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_B_i[20] }),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[20]_1 }));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_1
(.I0(\Data_A_i[20]_2 [2]),
.I1(O[2]),
.O(\sgf_result_o[47] [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_2__2
(.I0(\Data_A_i[20]_2 [1]),
.I1(O[1]),
.O(\sgf_result_o[47] [1]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_3__2
(.I0(\Data_A_i[20]_2 [0]),
.I1(O[0]),
.O(\sgf_result_o[47] [0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__1_i_2
(.I0(\Data_A_i[20]_3 [1]),
.I1(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_0 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__1_i_3
(.I0(\Data_A_i[20]_3 [0]),
.I1(sgf_result_o0__1_carry__0_n_7),
.O(\^sgf_result_o[47]_0 [1]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__1_i_4
(.I0(\Data_A_i[20]_2 [3]),
.I1(sgf_result_o0__1_carry_n_4),
.O(\^sgf_result_o[47]_0 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized46
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
DI,
S,
\Data_B_i[16] ,
\Data_A_i[16] ,
\Data_A_i[12] ,
\Data_B_i[12] ,
\Data_A_i[12]_0 ,
\Data_A_i[12]_1 ,
\Data_B_i[12]_0 ,
\Data_B_i[20] ,
\Data_B_i[16]_0 ,
\Data_A_i[20] ,
\Data_A_i[16]_0 ,
O,
CO,
Q_middle_temp__4,
\Data_A_i[20]_0 ,
\Data_B_i[12]_1 ,
\Data_B_i[20]_0 ,
\Data_B_i[12]_2 );
output [2:0]\sgf_result_o[47] ;
output [0:0]\sgf_result_o[47]_0 ;
output [2:0]\sgf_result_o[47]_1 ;
output [2:0]\sgf_result_o[47]_2 ;
output [1:0]\sgf_result_o[47]_3 ;
output [0:0]\sgf_result_o[47]_4 ;
output [3:0]\sgf_result_o[47]_5 ;
output [0:0]\sgf_result_o[47]_6 ;
output [2:0]\sgf_result_o[47]_7 ;
output [1:0]\sgf_result_o[47]_8 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[16] ;
input [2:0]\Data_A_i[16] ;
input [2:0]\Data_A_i[12] ;
input [0:0]\Data_B_i[12] ;
input [0:0]\Data_A_i[12]_0 ;
input [0:0]\Data_A_i[12]_1 ;
input [0:0]\Data_B_i[12]_0 ;
input [0:0]\Data_B_i[20] ;
input [0:0]\Data_B_i[16]_0 ;
input [0:0]\Data_A_i[20] ;
input [0:0]\Data_A_i[16]_0 ;
input [2:0]O;
input [0:0]CO;
input [2:0]Q_middle_temp__4;
input [3:0]\Data_A_i[20]_0 ;
input \Data_B_i[12]_1 ;
input \Data_B_i[20]_0 ;
input [0:0]\Data_B_i[12]_2 ;
wire [0:0]CO;
wire [2:0]DI;
wire [2:0]\Data_A_i[12] ;
wire [0:0]\Data_A_i[12]_0 ;
wire [0:0]\Data_A_i[12]_1 ;
wire [2:0]\Data_A_i[16] ;
wire [0:0]\Data_A_i[16]_0 ;
wire [0:0]\Data_A_i[20] ;
wire [3:0]\Data_A_i[20]_0 ;
wire [0:0]\Data_B_i[12] ;
wire [0:0]\Data_B_i[12]_0 ;
wire \Data_B_i[12]_1 ;
wire [0:0]\Data_B_i[12]_2 ;
wire [2:0]\Data_B_i[16] ;
wire [0:0]\Data_B_i[16]_0 ;
wire [0:0]\Data_B_i[20] ;
wire \Data_B_i[20]_0 ;
wire [2:0]O;
wire [2:0]Q_middle_temp__4;
wire [3:0]S;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_6;
wire [2:0]\sgf_result_o[47] ;
wire [0:0]\sgf_result_o[47]_0 ;
wire [2:0]\sgf_result_o[47]_1 ;
wire [2:0]\sgf_result_o[47]_2 ;
wire [1:0]\sgf_result_o[47]_3 ;
wire [0:0]\sgf_result_o[47]_4 ;
wire [3:0]\^sgf_result_o[47]_5 ;
wire [0:0]\sgf_result_o[47]_6 ;
wire [2:0]\sgf_result_o[47]_7 ;
wire [1:0]\sgf_result_o[47]_8 ;
wire [2:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
assign \sgf_result_o[47]_5 [3:1] = \^sgf_result_o[47]_5 [3:1];
assign \sgf_result_o[47]_5 [0] = \sgf_result_o[47] [2];
LUT4 #(
.INIT(16'h8E71))
S_B0__21_carry__1_i_2
(.I0(\sgf_result_o[47]_0 ),
.I1(CO),
.I2(Q_middle_temp__4[1]),
.I3(Q_middle_temp__4[2]),
.O(\sgf_result_o[47]_4 ));
(* HLUTNM = "lutpair48" *)
LUT3 #(
.INIT(8'h2B))
S_B0__21_carry_i_2
(.I0(\Data_B_i[20]_0 ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(O[1]),
.O(\sgf_result_o[47]_3 [1]));
LUT6 #(
.INIT(64'h000006600660FFFF))
S_B0__21_carry_i_3
(.I0(\Data_B_i[20] ),
.I1(\Data_B_i[16]_0 ),
.I2(\Data_A_i[20] ),
.I3(\Data_A_i[16]_0 ),
.I4(\sgf_result_o[47] [0]),
.I5(O[0]),
.O(\sgf_result_o[47]_3 [0]));
(* HLUTNM = "lutpair49" *)
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry_i_5
(.I0(Q_middle_temp__4[0]),
.I1(O[2]),
.I2(\sgf_result_o[47] [1]),
.I3(\sgf_result_o[47]_3 [1]),
.O(\sgf_result_o[47]_8 [1]));
(* HLUTNM = "lutpair48" *)
LUT4 #(
.INIT(16'h6996))
S_B0__21_carry_i_6
(.I0(\Data_B_i[20]_0 ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(O[1]),
.I3(\sgf_result_o[47]_3 [0]),
.O(\sgf_result_o[47]_8 [0]));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({\sgf_result_o[47] [2:1],sgf_result_o0__1_carry_n_6,\sgf_result_o[47] [0]}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({\sgf_result_o[47]_0 ,NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_B_i[16] }),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],\sgf_result_o[47]_1 }),
.S({1'b1,\Data_A_i[16] }));
(* HLUTNM = "lutpair52" *)
LUT3 #(
.INIT(8'h2B))
sgf_result_o1__35_carry_i_1__0
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[12]_2 ),
.I2(\Data_A_i[12] [2]),
.O(\sgf_result_o[47]_2 [2]));
LUT6 #(
.INIT(64'hB2222BBB2BBB2BBB))
sgf_result_o1__35_carry_i_2
(.I0(sgf_result_o0__1_carry_n_6),
.I1(\Data_A_i[12] [1]),
.I2(\Data_B_i[12] ),
.I3(\Data_A_i[12]_0 ),
.I4(\Data_A_i[12]_1 ),
.I5(\Data_B_i[12]_0 ),
.O(\sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair88" *)
LUT4 #(
.INIT(16'h2BBB))
sgf_result_o1__35_carry_i_3__2
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[12] [0]),
.I2(\Data_A_i[12]_0 ),
.I3(\Data_B_i[12]_0 ),
.O(\sgf_result_o[47]_2 [0]));
(* HLUTNM = "lutpair52" *)
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_5__1
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[12]_2 ),
.I2(\Data_A_i[12] [2]),
.I3(\sgf_result_o[47]_2 [1]),
.O(\sgf_result_o[47]_7 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__35_carry_i_6
(.I0(\sgf_result_o[47]_2 [0]),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_A_i[12] [1]),
.I3(\Data_B_i[12]_1 ),
.O(\sgf_result_o[47]_7 [1]));
(* HLUTNM = "lutpair88" *)
LUT4 #(
.INIT(16'h6999))
sgf_result_o1__35_carry_i_7__1
(.I0(\sgf_result_o[47] [0]),
.I1(\Data_A_i[12] [0]),
.I2(\Data_A_i[12]_0 ),
.I3(\Data_B_i[12]_0 ),
.O(\sgf_result_o[47]_7 [0]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry__0_i_4__2
(.I0(\Data_A_i[20]_0 [3]),
.I1(\sgf_result_o[47]_0 ),
.O(\sgf_result_o[47]_6 ));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_1__2
(.I0(\Data_A_i[20]_0 [2]),
.I1(\sgf_result_o[47]_1 [2]),
.O(\^sgf_result_o[47]_5 [3]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_2__2
(.I0(\Data_A_i[20]_0 [1]),
.I1(\sgf_result_o[47]_1 [1]),
.O(\^sgf_result_o[47]_5 [2]));
LUT2 #(
.INIT(4'h6))
sgf_result_o1_carry_i_3
(.I0(\Data_A_i[20]_0 [0]),
.I1(\sgf_result_o[47]_1 [0]),
.O(\^sgf_result_o[47]_5 [1]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized47
(Q_middle_temp__4,
O,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
CO,
\sgf_result_o[15] ,
\sgf_result_o[47]_5 ,
\sgf_result_o[15]_0 ,
\sgf_result_o[47]_6 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[15]_3 ,
\sgf_result_o[47]_9 ,
\sgf_result_o[47]_10 ,
S,
DI,
\Data_A_i[20] ,
\Data_B_i[20] ,
\Data_B_i[20]_0 ,
\Data_A_i[20]_0 ,
\Data_B_i[20]_1 ,
\Data_A_i[20]_1 ,
\Data_A_i[20]_2 ,
\Data_A_i[20]_3 ,
\Data_A_i[20]_4 ,
\Data_B_i[20]_2 ,
\Data_A_i[20]_5 ,
\Data_B_i[20]_3 ,
\Data_B_i[20]_4 ,
\Data_B_i[12] ,
\Data_B_i[16] ,
\Data_B_i[12]_0 ,
\Data_B_i[20]_5 ,
\Data_A_i[12] ,
\Data_A_i[16] ,
\Data_A_i[12]_0 ,
\Data_A_i[20]_6 );
output [7:0]Q_middle_temp__4;
output [3:0]O;
output [3:0]\sgf_result_o[47] ;
output [1:0]\sgf_result_o[47]_0 ;
output \sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [2:0]\sgf_result_o[47]_3 ;
output \sgf_result_o[47]_4 ;
output [0:0]CO;
output \sgf_result_o[15] ;
output \sgf_result_o[47]_5 ;
output \sgf_result_o[15]_0 ;
output \sgf_result_o[47]_6 ;
output [3:0]\sgf_result_o[47]_7 ;
output [2:0]\sgf_result_o[47]_8 ;
output \sgf_result_o[15]_1 ;
output \sgf_result_o[15]_2 ;
output [0:0]\sgf_result_o[15]_3 ;
output \sgf_result_o[47]_9 ;
output \sgf_result_o[47]_10 ;
input [0:0]S;
input [2:0]DI;
input [3:0]\Data_A_i[20] ;
input [3:0]\Data_B_i[20] ;
input [3:0]\Data_B_i[20]_0 ;
input [1:0]\Data_A_i[20]_0 ;
input \Data_B_i[20]_1 ;
input \Data_A_i[20]_1 ;
input \Data_A_i[20]_2 ;
input \Data_A_i[20]_3 ;
input \Data_A_i[20]_4 ;
input \Data_B_i[20]_2 ;
input \Data_A_i[20]_5 ;
input \Data_B_i[20]_3 ;
input \Data_B_i[20]_4 ;
input [3:0]\Data_B_i[12] ;
input [3:0]\Data_B_i[16] ;
input [2:0]\Data_B_i[12]_0 ;
input [1:0]\Data_B_i[20]_5 ;
input [3:0]\Data_A_i[12] ;
input [3:0]\Data_A_i[16] ;
input [2:0]\Data_A_i[12]_0 ;
input [1:0]\Data_A_i[20]_6 ;
wire [0:0]CO;
wire [2:0]DI;
wire [3:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire [3:0]\Data_A_i[16] ;
wire [3:0]\Data_A_i[20] ;
wire [1:0]\Data_A_i[20]_0 ;
wire \Data_A_i[20]_1 ;
wire \Data_A_i[20]_2 ;
wire \Data_A_i[20]_3 ;
wire \Data_A_i[20]_4 ;
wire \Data_A_i[20]_5 ;
wire [1:0]\Data_A_i[20]_6 ;
wire [3:0]\Data_B_i[12] ;
wire [2:0]\Data_B_i[12]_0 ;
wire [3:0]\Data_B_i[16] ;
wire [3:0]\Data_B_i[20] ;
wire [3:0]\Data_B_i[20]_0 ;
wire \Data_B_i[20]_1 ;
wire \Data_B_i[20]_2 ;
wire \Data_B_i[20]_3 ;
wire \Data_B_i[20]_4 ;
wire [1:0]\Data_B_i[20]_5 ;
wire [3:0]O;
wire \ODD1.middle_n_32 ;
wire \ODD1.middle_n_33 ;
wire \ODD1.middle_n_34 ;
wire \ODD1.middle_n_35 ;
wire \ODD1.middle_n_36 ;
wire \ODD1.middle_n_37 ;
wire \ODD1.middle_n_38 ;
wire \ODD1.middle_n_39 ;
wire \ODD1.middle_n_52 ;
wire \ODD1.middle_n_53 ;
wire \ODD1.middle_n_54 ;
wire \ODD1.middle_n_55 ;
wire [7:0]Q_middle_temp__4;
wire [0:0]S;
wire S_B0_carry__0_i_1_n_0;
wire S_B0_carry__0_i_2__1_n_0;
wire S_B0_carry__0_i_3__1_n_0;
wire S_B0_carry__0_i_4__1_n_0;
wire S_B0_carry_i_1__1_n_0;
wire S_B0_carry_i_2__1_n_0;
wire S_B0_carry_i_3__1_n_0;
wire sgf_result_o1__0_carry__0_n_2;
wire sgf_result_o1__0_carry__0_n_3;
wire sgf_result_o1__0_carry__0_n_5;
wire sgf_result_o1__0_carry__0_n_6;
wire sgf_result_o1__0_carry__0_n_7;
wire sgf_result_o1__0_carry_n_0;
wire sgf_result_o1__0_carry_n_1;
wire sgf_result_o1__0_carry_n_2;
wire sgf_result_o1__0_carry_n_3;
wire sgf_result_o1__0_carry_n_4;
wire sgf_result_o1__0_carry_n_5;
wire sgf_result_o1__0_carry_n_6;
wire sgf_result_o1__0_carry_n_7;
wire \sgf_result_o[15] ;
wire \sgf_result_o[15]_0 ;
wire \sgf_result_o[15]_1 ;
wire \sgf_result_o[15]_2 ;
wire [0:0]\sgf_result_o[15]_3 ;
wire [3:0]\sgf_result_o[47] ;
wire [1:0]\sgf_result_o[47]_0 ;
wire \sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_10 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [2:0]\sgf_result_o[47]_3 ;
wire \sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire \sgf_result_o[47]_6 ;
wire [3:0]\sgf_result_o[47]_7 ;
wire [2:0]\sgf_result_o[47]_8 ;
wire \sgf_result_o[47]_9 ;
wire [3:2]NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED;
Recursive_KOA__parameterized50 \ODD1.middle
(.CO(CO),
.DI(DI),
.\Data_A_i[12] (\Data_A_i[12] ),
.\Data_A_i[12]_0 (\Data_A_i[12]_0 ),
.\Data_A_i[16] (\Data_A_i[16] ),
.\Data_A_i[20] ({sgf_result_o1__0_carry__0_n_6,sgf_result_o1__0_carry__0_n_7}),
.\Data_A_i[20]_0 ({S_B0_carry__0_i_1_n_0,S_B0_carry__0_i_2__1_n_0,S_B0_carry__0_i_3__1_n_0,S_B0_carry__0_i_4__1_n_0}),
.\Data_A_i[20]_1 (\Data_A_i[20] ),
.\Data_A_i[20]_2 (\Data_A_i[20]_0 ),
.\Data_A_i[20]_3 (\Data_A_i[20]_1 ),
.\Data_A_i[20]_4 (\Data_A_i[20]_4 ),
.\Data_A_i[20]_5 (\Data_A_i[20]_5 ),
.\Data_A_i[20]_6 (\Data_A_i[20]_2 ),
.\Data_A_i[20]_7 (\Data_A_i[20]_6 ),
.\Data_A_i[20]_8 (\Data_A_i[20]_3 ),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[12]_0 (\Data_B_i[12]_0 ),
.\Data_B_i[16] (\Data_B_i[16] ),
.\Data_B_i[20] (\Data_B_i[20] ),
.\Data_B_i[20]_0 (\Data_B_i[20]_0 ),
.\Data_B_i[20]_1 (\Data_B_i[20]_1 ),
.\Data_B_i[20]_2 (\Data_B_i[20]_2 ),
.\Data_B_i[20]_3 (\Data_B_i[20]_3 ),
.\Data_B_i[20]_4 (\Data_B_i[20]_4 ),
.\Data_B_i[20]_5 (\Data_B_i[20]_5 ),
.O({sgf_result_o1__0_carry_n_4,sgf_result_o1__0_carry_n_5,sgf_result_o1__0_carry_n_6,sgf_result_o1__0_carry_n_7}),
.Q_middle_temp__4(Q_middle_temp__4),
.S({S_B0_carry_i_1__1_n_0,S_B0_carry_i_2__1_n_0,S_B0_carry_i_3__1_n_0,S}),
.\sgf_result_o[15] (\sgf_result_o[15] ),
.\sgf_result_o[15]_0 (\sgf_result_o[15]_0 ),
.\sgf_result_o[15]_1 ({\ODD1.middle_n_37 ,\ODD1.middle_n_38 ,\ODD1.middle_n_39 }),
.\sgf_result_o[15]_2 (\sgf_result_o[15]_1 ),
.\sgf_result_o[15]_3 (\sgf_result_o[15]_2 ),
.\sgf_result_o[15]_4 (\sgf_result_o[15]_3 ),
.\sgf_result_o[15]_5 ({\ODD1.middle_n_52 ,\ODD1.middle_n_53 ,\ODD1.middle_n_54 ,\ODD1.middle_n_55 }),
.\sgf_result_o[19] ({\ODD1.middle_n_32 ,\ODD1.middle_n_33 }),
.\sgf_result_o[19]_0 ({\ODD1.middle_n_34 ,\ODD1.middle_n_35 ,\ODD1.middle_n_36 }),
.\sgf_result_o[47] (O),
.\sgf_result_o[47]_0 (\sgf_result_o[47] ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_10 (\sgf_result_o[47]_9 ),
.\sgf_result_o[47]_11 (\sgf_result_o[47]_10 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_4 ),
.\sgf_result_o[47]_6 (\sgf_result_o[47]_5 ),
.\sgf_result_o[47]_7 (\sgf_result_o[47]_6 ),
.\sgf_result_o[47]_8 (\sgf_result_o[47]_7 ),
.\sgf_result_o[47]_9 (\sgf_result_o[47]_8 ));
LUT2 #(
.INIT(4'h6))
S_B0_carry__0_i_1
(.I0(sgf_result_o1__0_carry__0_n_5),
.I1(\Data_A_i[20]_2 ),
.O(S_B0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
S_B0_carry__0_i_2__1
(.I0(sgf_result_o1__0_carry__0_n_6),
.I1(\Data_B_i[20]_3 ),
.O(S_B0_carry__0_i_2__1_n_0));
LUT2 #(
.INIT(4'h6))
S_B0_carry__0_i_3__1
(.I0(sgf_result_o1__0_carry__0_n_7),
.I1(\Data_A_i[20]_4 ),
.O(S_B0_carry__0_i_3__1_n_0));
LUT2 #(
.INIT(4'h6))
S_B0_carry__0_i_4__1
(.I0(sgf_result_o1__0_carry_n_4),
.I1(\Data_A_i[20]_3 ),
.O(S_B0_carry__0_i_4__1_n_0));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_1__1
(.I0(sgf_result_o1__0_carry_n_5),
.I1(\Data_A_i[20]_1 ),
.O(S_B0_carry_i_1__1_n_0));
LUT2 #(
.INIT(4'h6))
S_B0_carry_i_2__1
(.I0(sgf_result_o1__0_carry_n_6),
.I1(\Data_B_i[20]_1 ),
.O(S_B0_carry_i_2__1_n_0));
LUT2 #(
.INIT(4'h9))
S_B0_carry_i_3__1
(.I0(sgf_result_o1__0_carry_n_7),
.I1(\Data_B_i[20]_4 ),
.O(S_B0_carry_i_3__1_n_0));
CARRY4 sgf_result_o1__0_carry
(.CI(1'b0),
.CO({sgf_result_o1__0_carry_n_0,sgf_result_o1__0_carry_n_1,sgf_result_o1__0_carry_n_2,sgf_result_o1__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.middle_n_37 ,\ODD1.middle_n_38 ,\ODD1.middle_n_39 ,1'b1}),
.O({sgf_result_o1__0_carry_n_4,sgf_result_o1__0_carry_n_5,sgf_result_o1__0_carry_n_6,sgf_result_o1__0_carry_n_7}),
.S({\ODD1.middle_n_52 ,\ODD1.middle_n_53 ,\ODD1.middle_n_54 ,\ODD1.middle_n_55 }));
CARRY4 sgf_result_o1__0_carry__0
(.CI(sgf_result_o1__0_carry_n_0),
.CO({NLW_sgf_result_o1__0_carry__0_CO_UNCONNECTED[3:2],sgf_result_o1__0_carry__0_n_2,sgf_result_o1__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\ODD1.middle_n_32 ,\ODD1.middle_n_33 }),
.O({NLW_sgf_result_o1__0_carry__0_O_UNCONNECTED[3],sgf_result_o1__0_carry__0_n_5,sgf_result_o1__0_carry__0_n_6,sgf_result_o1__0_carry__0_n_7}),
.S({1'b0,\ODD1.middle_n_34 ,\ODD1.middle_n_35 ,\ODD1.middle_n_36 }));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized5
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
Data_A_i_IBUF,
Data_B_i_IBUF,
\Data_B_i[12] ,
\Data_B_i[15] ,
\Data_B_i[13] ,
\Data_B_i[16] ,
\Data_A_i[14] ,
\Data_A_i[17] ,
\Data_A_i[17]_0 ,
\Data_A_i[14]_0 ,
\Data_A_i[14]_1 ,
\Data_A_i[17]_1 ,
S,
\Data_B_i[16]_0 );
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [1:0]\sgf_result_o[47]_1 ;
input [5:0]Data_A_i_IBUF;
input [5:0]Data_B_i_IBUF;
input \Data_B_i[12] ;
input \Data_B_i[15] ;
input \Data_B_i[13] ;
input \Data_B_i[16] ;
input \Data_A_i[14] ;
input \Data_A_i[17] ;
input \Data_A_i[17]_0 ;
input \Data_A_i[14]_0 ;
input \Data_A_i[14]_1 ;
input \Data_A_i[17]_1 ;
input [0:0]S;
input [0:0]\Data_B_i[16]_0 ;
wire \Data_A_i[14] ;
wire \Data_A_i[14]_0 ;
wire \Data_A_i[14]_1 ;
wire \Data_A_i[17] ;
wire \Data_A_i[17]_0 ;
wire \Data_A_i[17]_1 ;
wire [5:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire \Data_B_i[13] ;
wire \Data_B_i[15] ;
wire \Data_B_i[16] ;
wire [0:0]\Data_B_i[16]_0 ;
wire [5:0]Data_B_i_IBUF;
wire \EVEN1.middle_n_0 ;
wire \EVEN1.middle_n_1 ;
wire \EVEN1.middle_n_10 ;
wire \EVEN1.middle_n_11 ;
wire \EVEN1.middle_n_12 ;
wire \EVEN1.middle_n_13 ;
wire \EVEN1.middle_n_2 ;
wire \EVEN1.middle_n_3 ;
wire \EVEN1.middle_n_4 ;
wire \EVEN1.middle_n_5 ;
wire \EVEN1.middle_n_6 ;
wire \EVEN1.middle_n_7 ;
wire \EVEN1.middle_n_8 ;
wire \EVEN1.middle_n_9 ;
wire [0:0]S;
wire S_B0__0_carry__0_n_1;
wire S_B0__0_carry__0_n_2;
wire S_B0__0_carry__0_n_3;
wire S_B0__0_carry__0_n_4;
wire S_B0__0_carry__0_n_5;
wire S_B0__0_carry__0_n_6;
wire S_B0__0_carry__0_n_7;
wire S_B0__0_carry_n_0;
wire S_B0__0_carry_n_1;
wire S_B0__0_carry_n_2;
wire S_B0__0_carry_n_3;
wire S_B0__0_carry_n_4;
wire S_B0__0_carry_n_5;
wire S_B0__0_carry_n_6;
wire S_B0__0_carry_n_7;
wire S_B0__30_carry__0_i_15__0_n_0;
wire S_B0__30_carry__0_i_16_n_0;
wire S_B0__30_carry__0_i_17_n_0;
wire S_B0__30_carry__0_i_18_n_0;
wire S_B0__30_carry__1_i_14_n_0;
wire S_B0__30_carry_i_14_n_0;
wire S_B0__30_carry_i_15_n_0;
wire S_B0__30_carry_i_16_n_0;
wire sgf_result_o0__1_carry__0_i_10__2_n_0;
wire sgf_result_o0__1_carry__0_i_1__3_n_0;
wire sgf_result_o0__1_carry__0_i_2__2_n_0;
wire sgf_result_o0__1_carry__0_i_3__12_n_0;
wire sgf_result_o0__1_carry__0_i_4__3_n_0;
wire sgf_result_o0__1_carry__0_i_5__5_n_0;
wire sgf_result_o0__1_carry__0_i_6__3_n_0;
wire sgf_result_o0__1_carry__0_i_7__9_n_0;
wire sgf_result_o0__1_carry__0_i_8__2_n_0;
wire sgf_result_o0__1_carry__0_i_9__1_n_0;
wire sgf_result_o0__1_carry_i_10__8_n_0;
wire sgf_result_o0__1_carry_i_11__3_n_0;
wire sgf_result_o0__1_carry_i_12__3_n_0;
wire sgf_result_o0__1_carry_i_13__2_n_0;
wire sgf_result_o0__1_carry_i_14__5_n_0;
wire sgf_result_o0__1_carry_i_1__3_n_0;
wire sgf_result_o0__1_carry_i_2__3_n_0;
wire sgf_result_o0__1_carry_i_3__3_n_0;
wire sgf_result_o0__1_carry_i_4__3_n_0;
wire sgf_result_o0__1_carry_i_5__3_n_0;
wire sgf_result_o0__1_carry_i_6__2_n_0;
wire sgf_result_o0__1_carry_i_7__3_n_0;
wire sgf_result_o0__1_carry_i_8__2_n_0;
wire sgf_result_o0__1_carry_i_9__10_n_0;
wire [3:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [1:0]\sgf_result_o[47]_1 ;
wire [3:3]NLW_S_B0__0_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized8 \EVEN1.middle
(.DI({sgf_result_o0__1_carry_i_1__3_n_0,sgf_result_o0__1_carry_i_2__3_n_0,sgf_result_o0__1_carry_i_3__3_n_0}),
.\Data_A_i[13] ({sgf_result_o0__1_carry__0_i_4__3_n_0,sgf_result_o0__1_carry__0_i_5__5_n_0,sgf_result_o0__1_carry__0_i_6__3_n_0}),
.\Data_A_i[14] (\Data_A_i[14] ),
.\Data_A_i[14]_0 (\Data_A_i[14]_0 ),
.\Data_A_i[14]_1 (\Data_A_i[14]_1 ),
.\Data_A_i[14]_2 ({S_B0__30_carry__0_i_15__0_n_0,S_B0__30_carry__0_i_16_n_0,S_B0__30_carry__0_i_17_n_0,S_B0__30_carry__0_i_18_n_0}),
.\Data_A_i[17] ({sgf_result_o0__1_carry__0_i_1__3_n_0,sgf_result_o0__1_carry__0_i_2__2_n_0,sgf_result_o0__1_carry__0_i_3__12_n_0}),
.\Data_A_i[17]_0 (\Data_A_i[17] ),
.\Data_A_i[17]_1 (\Data_A_i[17]_0 ),
.\Data_A_i[17]_2 (\Data_A_i[17]_1 ),
.\Data_A_i[17]_3 ({S_B0__30_carry_i_14_n_0,S_B0__30_carry_i_15_n_0,S_B0__30_carry_i_16_n_0,S}),
.\Data_A_i[17]_4 ({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.Data_A_i_IBUF({Data_A_i_IBUF[4:3],Data_A_i_IBUF[0]}),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[13] (\Data_B_i[13] ),
.\Data_B_i[15] (\Data_B_i[15] ),
.\Data_B_i[16] (\Data_B_i[16] ),
.\Data_B_i[16]_0 ({\Data_B_i[16]_0 ,S_B0__30_carry__1_i_14_n_0}),
.Data_B_i_IBUF({Data_B_i_IBUF[4:3],Data_B_i_IBUF[0]}),
.O({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.S({sgf_result_o0__1_carry_i_4__3_n_0,sgf_result_o0__1_carry_i_5__3_n_0,sgf_result_o0__1_carry_i_6__2_n_0,sgf_result_o0__1_carry_i_7__3_n_0}),
.\sgf_result_o[47] ({\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.\sgf_result_o[47]_0 ({\EVEN1.middle_n_3 ,\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 }),
.\sgf_result_o[47]_1 ({\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 ,\EVEN1.middle_n_8 ,\EVEN1.middle_n_9 }),
.\sgf_result_o[47]_2 ({\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 ,\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 }),
.\sgf_result_o[47]_3 (\sgf_result_o[47] ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_5 (\sgf_result_o[47]_1 ));
CARRY4 S_B0__0_carry
(.CI(1'b0),
.CO({S_B0__0_carry_n_0,S_B0__0_carry_n_1,S_B0__0_carry_n_2,S_B0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({\EVEN1.middle_n_3 ,\EVEN1.middle_n_4 ,\EVEN1.middle_n_5 ,1'b1}),
.O({S_B0__0_carry_n_4,S_B0__0_carry_n_5,S_B0__0_carry_n_6,S_B0__0_carry_n_7}),
.S({\EVEN1.middle_n_6 ,\EVEN1.middle_n_7 ,\EVEN1.middle_n_8 ,\EVEN1.middle_n_9 }));
CARRY4 S_B0__0_carry__0
(.CI(S_B0__0_carry_n_0),
.CO({NLW_S_B0__0_carry__0_CO_UNCONNECTED[3],S_B0__0_carry__0_n_1,S_B0__0_carry__0_n_2,S_B0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\EVEN1.middle_n_0 ,\EVEN1.middle_n_1 ,\EVEN1.middle_n_2 }),
.O({S_B0__0_carry__0_n_4,S_B0__0_carry__0_n_5,S_B0__0_carry__0_n_6,S_B0__0_carry__0_n_7}),
.S({\EVEN1.middle_n_10 ,\EVEN1.middle_n_11 ,\EVEN1.middle_n_12 ,\EVEN1.middle_n_13 }));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry__0_i_15__0
(.I0(S_B0__0_carry__0_n_5),
.I1(\Data_A_i[17]_0 ),
.O(S_B0__30_carry__0_i_15__0_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__0_i_16
(.I0(S_B0__0_carry__0_n_6),
.I1(\Data_A_i[17] ),
.O(S_B0__30_carry__0_i_16_n_0));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0__30_carry__0_i_17
(.I0(S_B0__0_carry__0_n_7),
.I1(Data_B_i_IBUF[3]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_B_i_IBUF[4]),
.O(S_B0__30_carry__0_i_17_n_0));
LUT3 #(
.INIT(8'h6A))
S_B0__30_carry__0_i_18
(.I0(S_B0__0_carry_n_4),
.I1(Data_A_i_IBUF[3]),
.I2(Data_B_i_IBUF[3]),
.O(S_B0__30_carry__0_i_18_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry__1_i_14
(.I0(S_B0__0_carry__0_n_4),
.I1(\Data_A_i[17]_1 ),
.O(S_B0__30_carry__1_i_14_n_0));
LUT2 #(
.INIT(4'h9))
S_B0__30_carry_i_14
(.I0(S_B0__0_carry_n_5),
.I1(\Data_B_i[13] ),
.O(S_B0__30_carry_i_14_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry_i_15
(.I0(S_B0__0_carry_n_6),
.I1(\Data_A_i[14]_1 ),
.O(S_B0__30_carry_i_15_n_0));
LUT2 #(
.INIT(4'h6))
S_B0__30_carry_i_16
(.I0(S_B0__0_carry_n_7),
.I1(\Data_A_i[14]_0 ),
.O(S_B0__30_carry_i_16_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_10__2
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_8__2_n_0),
.O(sgf_result_o0__1_carry__0_i_10__2_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_1__3
(.I0(sgf_result_o0__1_carry_i_11__3_n_0),
.I1(sgf_result_o0__1_carry_i_13__2_n_0),
.O(sgf_result_o0__1_carry__0_i_1__3_n_0));
LUT5 #(
.INIT(32'h14000000))
sgf_result_o0__1_carry__0_i_2__2
(.I0(sgf_result_o0__1_carry_i_13__2_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_3__3_n_0),
.I4(sgf_result_o0__1_carry_i_10__8_n_0),
.O(sgf_result_o0__1_carry__0_i_2__2_n_0));
LUT6 #(
.INIT(64'h1EE11EE11EE1E11E))
sgf_result_o0__1_carry__0_i_3__12
(.I0(sgf_result_o0__1_carry_i_12__3_n_0),
.I1(sgf_result_o0__1_carry_i_8__2_n_0),
.I2(sgf_result_o0__1_carry__0_i_2__2_n_0),
.I3(sgf_result_o0__1_carry__0_i_7__9_n_0),
.I4(sgf_result_o0__1_carry_i_9__10_n_0),
.I5(sgf_result_o0__1_carry_i_13__2_n_0),
.O(sgf_result_o0__1_carry__0_i_3__12_n_0));
LUT6 #(
.INIT(64'h000001010003FCE8))
sgf_result_o0__1_carry__0_i_4__3
(.I0(sgf_result_o0__1_carry_i_9__10_n_0),
.I1(sgf_result_o0__1_carry_i_12__3_n_0),
.I2(sgf_result_o0__1_carry_i_8__2_n_0),
.I3(sgf_result_o0__1_carry_i_14__5_n_0),
.I4(sgf_result_o0__1_carry_i_13__2_n_0),
.I5(sgf_result_o0__1_carry_i_11__3_n_0),
.O(sgf_result_o0__1_carry__0_i_4__3_n_0));
LUT6 #(
.INIT(64'h9996999699966669))
sgf_result_o0__1_carry__0_i_5__5
(.I0(sgf_result_o0__1_carry__0_i_2__2_n_0),
.I1(sgf_result_o0__1_carry__0_i_8__2_n_0),
.I2(sgf_result_o0__1_carry_i_12__3_n_0),
.I3(sgf_result_o0__1_carry_i_13__2_n_0),
.I4(sgf_result_o0__1_carry_i_8__2_n_0),
.I5(sgf_result_o0__1_carry_i_11__3_n_0),
.O(sgf_result_o0__1_carry__0_i_5__5_n_0));
LUT6 #(
.INIT(64'hA595AA99AAA9AAAA))
sgf_result_o0__1_carry__0_i_6__3
(.I0(sgf_result_o0__1_carry__0_i_3__12_n_0),
.I1(sgf_result_o0__1_carry_i_14__5_n_0),
.I2(sgf_result_o0__1_carry_i_11__3_n_0),
.I3(sgf_result_o0__1_carry_i_12__3_n_0),
.I4(sgf_result_o0__1_carry__0_i_9__1_n_0),
.I5(sgf_result_o0__1_carry__0_i_10__2_n_0),
.O(sgf_result_o0__1_carry__0_i_6__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry__0_i_7__9
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_11__3_n_0),
.O(sgf_result_o0__1_carry__0_i_7__9_n_0));
LUT6 #(
.INIT(64'hFFFEFFFEFFFEEEE0))
sgf_result_o0__1_carry__0_i_8__2
(.I0(sgf_result_o0__1_carry_i_11__3_n_0),
.I1(sgf_result_o0__1_carry_i_14__5_n_0),
.I2(sgf_result_o0__1_carry_i_8__2_n_0),
.I3(sgf_result_o0__1_carry_i_12__3_n_0),
.I4(sgf_result_o0__1_carry_i_9__10_n_0),
.I5(sgf_result_o0__1_carry_i_13__2_n_0),
.O(sgf_result_o0__1_carry__0_i_8__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry__0_i_9__1
(.I0(Data_A_i_IBUF[0]),
.I1(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry__0_i_9__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00009666))
sgf_result_o0__1_carry_i_10__8
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(sgf_result_o0__1_carry_i_12__3_n_0),
.O(sgf_result_o0__1_carry_i_10__8_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_11__3
(.I0(Data_B_i_IBUF[1]),
.I1(Data_B_i_IBUF[4]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[2]),
.I5(Data_B_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_11__3_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_12__3
(.I0(Data_B_i_IBUF[5]),
.I1(Data_B_i_IBUF[2]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.I4(Data_B_i_IBUF[4]),
.I5(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_12__3_n_0));
LUT6 #(
.INIT(64'h000017771777FFFF))
sgf_result_o0__1_carry_i_13__2
(.I0(Data_A_i_IBUF[1]),
.I1(Data_A_i_IBUF[4]),
.I2(Data_A_i_IBUF[0]),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[2]),
.I5(Data_A_i_IBUF[5]),
.O(sgf_result_o0__1_carry_i_13__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_14__5
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_A_i_IBUF[4]),
.I3(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_14__5_n_0));
LUT6 #(
.INIT(64'hE1E1E1E1E11E1EE1))
sgf_result_o0__1_carry_i_1__3
(.I0(sgf_result_o0__1_carry_i_8__2_n_0),
.I1(sgf_result_o0__1_carry_i_9__10_n_0),
.I2(sgf_result_o0__1_carry_i_10__8_n_0),
.I3(Data_A_i_IBUF[3]),
.I4(Data_A_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_11__3_n_0),
.O(sgf_result_o0__1_carry_i_1__3_n_0));
LUT6 #(
.INIT(64'h0906060609F9F906))
sgf_result_o0__1_carry_i_2__3
(.I0(Data_A_i_IBUF[4]),
.I1(Data_A_i_IBUF[1]),
.I2(sgf_result_o0__1_carry_i_9__10_n_0),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[3]),
.I5(sgf_result_o0__1_carry_i_12__3_n_0),
.O(sgf_result_o0__1_carry_i_2__3_n_0));
LUT6 #(
.INIT(64'h6006066006600660))
sgf_result_o0__1_carry_i_3__3
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[1]),
.I3(Data_B_i_IBUF[4]),
.I4(Data_B_i_IBUF[0]),
.I5(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_3__3_n_0));
LUT6 #(
.INIT(64'h6A6A6A6A6A95956A))
sgf_result_o0__1_carry_i_4__3
(.I0(sgf_result_o0__1_carry_i_1__3_n_0),
.I1(sgf_result_o0__1_carry_i_10__8_n_0),
.I2(sgf_result_o0__1_carry_i_3__3_n_0),
.I3(Data_B_i_IBUF[3]),
.I4(Data_B_i_IBUF[0]),
.I5(sgf_result_o0__1_carry_i_13__2_n_0),
.O(sgf_result_o0__1_carry_i_4__3_n_0));
LUT4 #(
.INIT(16'hA99A))
sgf_result_o0__1_carry_i_5__3
(.I0(sgf_result_o0__1_carry_i_2__3_n_0),
.I1(sgf_result_o0__1_carry_i_8__2_n_0),
.I2(Data_B_i_IBUF[0]),
.I3(Data_B_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_5__3_n_0));
LUT6 #(
.INIT(64'h141414EB14EB1414))
sgf_result_o0__1_carry_i_6__2
(.I0(sgf_result_o0__1_carry_i_14__5_n_0),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(sgf_result_o0__1_carry_i_9__10_n_0),
.I4(Data_A_i_IBUF[0]),
.I5(Data_A_i_IBUF[3]),
.O(sgf_result_o0__1_carry_i_6__2_n_0));
LUT4 #(
.INIT(16'h0660))
sgf_result_o0__1_carry_i_7__3
(.I0(Data_A_i_IBUF[3]),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[3]),
.I3(Data_B_i_IBUF[0]),
.O(sgf_result_o0__1_carry_i_7__3_n_0));
LUT6 #(
.INIT(64'h6666699969999999))
sgf_result_o0__1_carry_i_8__2
(.I0(Data_A_i_IBUF[5]),
.I1(Data_A_i_IBUF[2]),
.I2(Data_A_i_IBUF[3]),
.I3(Data_A_i_IBUF[0]),
.I4(Data_A_i_IBUF[4]),
.I5(Data_A_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_8__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_9__10
(.I0(Data_B_i_IBUF[3]),
.I1(Data_B_i_IBUF[0]),
.I2(Data_B_i_IBUF[4]),
.I3(Data_B_i_IBUF[1]),
.O(sgf_result_o0__1_carry_i_9__10_n_0));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized50
(Q_middle_temp__4,
\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
CO,
\sgf_result_o[15] ,
\sgf_result_o[47]_6 ,
\sgf_result_o[15]_0 ,
\sgf_result_o[47]_7 ,
\sgf_result_o[19] ,
\sgf_result_o[19]_0 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[47]_8 ,
\sgf_result_o[47]_9 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[15]_3 ,
\sgf_result_o[15]_4 ,
\sgf_result_o[47]_10 ,
\sgf_result_o[47]_11 ,
\sgf_result_o[15]_5 ,
O,
S,
\Data_A_i[20] ,
\Data_A_i[20]_0 ,
DI,
\Data_A_i[20]_1 ,
\Data_B_i[20] ,
\Data_B_i[20]_0 ,
\Data_A_i[20]_2 ,
\Data_B_i[20]_1 ,
\Data_A_i[20]_3 ,
\Data_A_i[20]_4 ,
\Data_B_i[20]_2 ,
\Data_A_i[20]_5 ,
\Data_B_i[20]_3 ,
\Data_A_i[20]_6 ,
\Data_B_i[20]_4 ,
\Data_B_i[12] ,
\Data_B_i[16] ,
\Data_B_i[12]_0 ,
\Data_B_i[20]_5 ,
\Data_A_i[12] ,
\Data_A_i[16] ,
\Data_A_i[12]_0 ,
\Data_A_i[20]_7 ,
\Data_A_i[20]_8 );
output [7:0]Q_middle_temp__4;
output [3:0]\sgf_result_o[47] ;
output [3:0]\sgf_result_o[47]_0 ;
output [1:0]\sgf_result_o[47]_1 ;
output \sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [2:0]\sgf_result_o[47]_4 ;
output \sgf_result_o[47]_5 ;
output [0:0]CO;
output \sgf_result_o[15] ;
output \sgf_result_o[47]_6 ;
output \sgf_result_o[15]_0 ;
output \sgf_result_o[47]_7 ;
output [1:0]\sgf_result_o[19] ;
output [2:0]\sgf_result_o[19]_0 ;
output [2:0]\sgf_result_o[15]_1 ;
output [3:0]\sgf_result_o[47]_8 ;
output [2:0]\sgf_result_o[47]_9 ;
output \sgf_result_o[15]_2 ;
output \sgf_result_o[15]_3 ;
output [0:0]\sgf_result_o[15]_4 ;
output \sgf_result_o[47]_10 ;
output \sgf_result_o[47]_11 ;
output [3:0]\sgf_result_o[15]_5 ;
input [3:0]O;
input [3:0]S;
input [1:0]\Data_A_i[20] ;
input [3:0]\Data_A_i[20]_0 ;
input [2:0]DI;
input [3:0]\Data_A_i[20]_1 ;
input [3:0]\Data_B_i[20] ;
input [3:0]\Data_B_i[20]_0 ;
input [1:0]\Data_A_i[20]_2 ;
input \Data_B_i[20]_1 ;
input \Data_A_i[20]_3 ;
input \Data_A_i[20]_4 ;
input \Data_B_i[20]_2 ;
input \Data_A_i[20]_5 ;
input \Data_B_i[20]_3 ;
input \Data_A_i[20]_6 ;
input \Data_B_i[20]_4 ;
input [3:0]\Data_B_i[12] ;
input [3:0]\Data_B_i[16] ;
input [2:0]\Data_B_i[12]_0 ;
input [1:0]\Data_B_i[20]_5 ;
input [3:0]\Data_A_i[12] ;
input [3:0]\Data_A_i[16] ;
input [2:0]\Data_A_i[12]_0 ;
input [1:0]\Data_A_i[20]_7 ;
input \Data_A_i[20]_8 ;
wire [0:0]CO;
wire [2:0]DI;
wire [3:0]\Data_A_i[12] ;
wire [2:0]\Data_A_i[12]_0 ;
wire [3:0]\Data_A_i[16] ;
wire [1:0]\Data_A_i[20] ;
wire [3:0]\Data_A_i[20]_0 ;
wire [3:0]\Data_A_i[20]_1 ;
wire [1:0]\Data_A_i[20]_2 ;
wire \Data_A_i[20]_3 ;
wire \Data_A_i[20]_4 ;
wire \Data_A_i[20]_5 ;
wire \Data_A_i[20]_6 ;
wire [1:0]\Data_A_i[20]_7 ;
wire \Data_A_i[20]_8 ;
wire [3:0]\Data_B_i[12] ;
wire [2:0]\Data_B_i[12]_0 ;
wire [3:0]\Data_B_i[16] ;
wire [3:0]\Data_B_i[20] ;
wire [3:0]\Data_B_i[20]_0 ;
wire \Data_B_i[20]_1 ;
wire \Data_B_i[20]_2 ;
wire \Data_B_i[20]_3 ;
wire \Data_B_i[20]_4 ;
wire [1:0]\Data_B_i[20]_5 ;
wire [3:0]O;
wire [7:0]Q_middle_temp__4;
wire [3:0]S;
wire S_B0__21_carry__0_n_0;
wire S_B0__21_carry__0_n_1;
wire S_B0__21_carry__0_n_2;
wire S_B0__21_carry__0_n_3;
wire S_B0__21_carry__1_n_3;
wire S_B0__21_carry_n_0;
wire S_B0__21_carry_n_1;
wire S_B0__21_carry_n_2;
wire S_B0__21_carry_n_3;
wire S_B0_carry__0_n_1;
wire S_B0_carry__0_n_2;
wire S_B0_carry__0_n_3;
wire S_B0_carry_n_0;
wire S_B0_carry_n_1;
wire S_B0_carry_n_2;
wire S_B0_carry_n_3;
wire sgf_result_o0__1_carry__0_i_1__12_n_0;
wire sgf_result_o0__1_carry__0_i_2__10_n_0;
wire sgf_result_o0__1_carry__0_i_3__2_n_0;
wire sgf_result_o0__1_carry__0_i_4__12_n_0;
wire sgf_result_o0__1_carry__0_i_5__12_n_0;
wire sgf_result_o0__1_carry__0_i_6_n_0;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_5;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_i_10__5_n_0;
wire sgf_result_o0__1_carry_i_12__8_n_0;
wire sgf_result_o0__1_carry_i_13__7_n_0;
wire sgf_result_o0__1_carry_i_15__4_n_0;
wire sgf_result_o0__1_carry_i_16__1_n_0;
wire sgf_result_o0__1_carry_i_17__3_n_0;
wire sgf_result_o0__1_carry_i_1__12_n_0;
wire sgf_result_o0__1_carry_i_23__0_n_0;
wire sgf_result_o0__1_carry_i_25__0_n_0;
wire sgf_result_o0__1_carry_i_26__0_n_0;
wire sgf_result_o0__1_carry_i_2__12_n_0;
wire sgf_result_o0__1_carry_i_3__12_n_0;
wire sgf_result_o0__1_carry_i_4__12_n_0;
wire sgf_result_o0__1_carry_i_5__12_n_0;
wire sgf_result_o0__1_carry_i_6__9_n_0;
wire sgf_result_o0__1_carry_i_7__12_n_0;
wire sgf_result_o0__1_carry_i_8__11_n_0;
wire sgf_result_o0__1_carry_i_8__11_n_1;
wire sgf_result_o0__1_carry_i_8__11_n_2;
wire sgf_result_o0__1_carry_i_8__11_n_3;
wire sgf_result_o0__1_carry_i_8__12_n_2;
wire sgf_result_o0__1_carry_i_8__12_n_3;
wire sgf_result_o0__1_carry_i_8__7_n_0;
wire sgf_result_o0__1_carry_i_9__2_n_0;
wire sgf_result_o0__1_carry_i_9__6_n_0;
wire sgf_result_o0__1_carry_i_9__6_n_1;
wire sgf_result_o0__1_carry_i_9__6_n_2;
wire sgf_result_o0__1_carry_i_9__6_n_3;
wire sgf_result_o0__1_carry_i_9__7_n_2;
wire sgf_result_o0__1_carry_i_9__7_n_3;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire \sgf_result_o[15] ;
wire \sgf_result_o[15]_0 ;
wire [2:0]\sgf_result_o[15]_1 ;
wire \sgf_result_o[15]_2 ;
wire \sgf_result_o[15]_3 ;
wire [0:0]\sgf_result_o[15]_4 ;
wire [3:0]\sgf_result_o[15]_5 ;
wire [1:0]\sgf_result_o[19] ;
wire [2:0]\sgf_result_o[19]_0 ;
wire [3:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [1:0]\sgf_result_o[47]_1 ;
wire \sgf_result_o[47]_10 ;
wire \sgf_result_o[47]_11 ;
wire \sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [2:0]\sgf_result_o[47]_4 ;
wire \sgf_result_o[47]_5 ;
wire \sgf_result_o[47]_6 ;
wire \sgf_result_o[47]_7 ;
wire [3:0]\sgf_result_o[47]_8 ;
wire [2:0]\sgf_result_o[47]_9 ;
wire [3:1]NLW_S_B0__21_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__21_carry__1_O_UNCONNECTED;
wire [3:3]NLW_S_B0_carry__0_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED;
wire [2:2]NLW_sgf_result_o0__1_carry_i_8__12_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry_i_8__12_O_UNCONNECTED;
wire [2:2]NLW_sgf_result_o0__1_carry_i_9__7_CO_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry_i_9__7_O_UNCONNECTED;
CARRY4 S_B0__21_carry
(.CI(1'b0),
.CO({S_B0__21_carry_n_0,S_B0__21_carry_n_1,S_B0__21_carry_n_2,S_B0__21_carry_n_3}),
.CYINIT(1'b1),
.DI({DI,1'b1}),
.O(\sgf_result_o[47] ),
.S(\Data_A_i[20]_1 ));
CARRY4 S_B0__21_carry__0
(.CI(S_B0__21_carry_n_0),
.CO({S_B0__21_carry__0_n_0,S_B0__21_carry__0_n_1,S_B0__21_carry__0_n_2,S_B0__21_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Data_B_i[20] ),
.O(\sgf_result_o[47]_0 ),
.S(\Data_B_i[20]_0 ));
CARRY4 S_B0__21_carry__1
(.CI(S_B0__21_carry__0_n_0),
.CO({NLW_S_B0__21_carry__1_CO_UNCONNECTED[3:1],S_B0__21_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp__4[6]}),
.O({NLW_S_B0__21_carry__1_O_UNCONNECTED[3:2],\sgf_result_o[47]_1 }),
.S({1'b0,1'b0,\Data_A_i[20]_2 }));
CARRY4 S_B0_carry
(.CI(1'b0),
.CO({S_B0_carry_n_0,S_B0_carry_n_1,S_B0_carry_n_2,S_B0_carry_n_3}),
.CYINIT(1'b0),
.DI({O[2:0],1'b0}),
.O(Q_middle_temp__4[3:0]),
.S(S));
CARRY4 S_B0_carry__0
(.CI(S_B0_carry_n_0),
.CO({NLW_S_B0_carry__0_CO_UNCONNECTED[3],S_B0_carry__0_n_1,S_B0_carry__0_n_2,S_B0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[20] ,O[3]}),
.O(Q_middle_temp__4[7:4]),
.S(\Data_A_i[20]_0 ));
LUT6 #(
.INIT(64'h077FF880F880077F))
S_B0_carry_i_6
(.I0(\sgf_result_o[47]_3 [0]),
.I1(\sgf_result_o[47]_4 [0]),
.I2(\sgf_result_o[47]_3 [1]),
.I3(\sgf_result_o[47]_4 [1]),
.I4(\sgf_result_o[47]_4 [2]),
.I5(\sgf_result_o[47]_3 [2]),
.O(\sgf_result_o[47]_6 ));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({sgf_result_o0__1_carry_i_1__12_n_0,sgf_result_o0__1_carry_i_2__12_n_0,sgf_result_o0__1_carry_i_3__12_n_0,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S({sgf_result_o0__1_carry_i_4__12_n_0,sgf_result_o0__1_carry_i_5__12_n_0,sgf_result_o0__1_carry_i_6__9_n_0,sgf_result_o0__1_carry_i_7__12_n_0}));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3:2],sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sgf_result_o0__1_carry__0_i_1__12_n_0}),
.O({NLW_sgf_result_o0__1_carry__0_O_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_5,sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b0,sgf_result_o0__1_carry__0_i_2__10_n_0,sgf_result_o0__1_carry__0_i_3__2_n_0,sgf_result_o0__1_carry__0_i_4__12_n_0}));
LUT6 #(
.INIT(64'h11F1F1FF1111F11F))
sgf_result_o0__1_carry__0_i_1__12
(.I0(sgf_result_o0__1_carry_i_16__1_n_0),
.I1(sgf_result_o0__1_carry_i_9__2_n_0),
.I2(sgf_result_o0__1_carry_i_12__8_n_0),
.I3(\sgf_result_o[47]_2 ),
.I4(sgf_result_o0__1_carry_i_8__7_n_0),
.I5(sgf_result_o0__1_carry_i_10__5_n_0),
.O(sgf_result_o0__1_carry__0_i_1__12_n_0));
LUT2 #(
.INIT(4'h1))
sgf_result_o0__1_carry__0_i_2__10
(.I0(sgf_result_o0__1_carry__0_i_5__12_n_0),
.I1(sgf_result_o0__1_carry_i_16__1_n_0),
.O(sgf_result_o0__1_carry__0_i_2__10_n_0));
LUT4 #(
.INIT(16'h3503))
sgf_result_o0__1_carry__0_i_3__2
(.I0(sgf_result_o0__1_carry_i_8__7_n_0),
.I1(sgf_result_o0__1_carry_i_16__1_n_0),
.I2(\sgf_result_o[47]_2 ),
.I3(sgf_result_o0__1_carry_i_12__8_n_0),
.O(sgf_result_o0__1_carry__0_i_3__2_n_0));
LUT6 #(
.INIT(64'h1C1FFF1111111C1F))
sgf_result_o0__1_carry__0_i_4__12
(.I0(sgf_result_o0__1_carry_i_16__1_n_0),
.I1(sgf_result_o0__1_carry_i_9__2_n_0),
.I2(sgf_result_o0__1_carry_i_8__7_n_0),
.I3(sgf_result_o0__1_carry_i_10__5_n_0),
.I4(\sgf_result_o[47]_2 ),
.I5(sgf_result_o0__1_carry_i_12__8_n_0),
.O(sgf_result_o0__1_carry__0_i_4__12_n_0));
LUT6 #(
.INIT(64'hAAAAFFEBFFEBFFFF))
sgf_result_o0__1_carry__0_i_5__12
(.I0(\sgf_result_o[47]_2 ),
.I1(\sgf_result_o[47]_8 [0]),
.I2(\sgf_result_o[47]_9 [0]),
.I3(\sgf_result_o[15]_2 ),
.I4(\sgf_result_o[47]_10 ),
.I5(sgf_result_o0__1_carry__0_i_6_n_0),
.O(sgf_result_o0__1_carry__0_i_5__12_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hEEE8E888))
sgf_result_o0__1_carry__0_i_6
(.I0(\sgf_result_o[47]_8 [3]),
.I1(\sgf_result_o[15]_4 ),
.I2(\sgf_result_o[47]_8 [2]),
.I3(sgf_result_o0__1_carry_i_26__0_n_0),
.I4(\sgf_result_o[47]_9 [2]),
.O(sgf_result_o0__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hF069690F96F0F069))
sgf_result_o0__1_carry_i_10__5
(.I0(\sgf_result_o[47]_3 [0]),
.I1(\sgf_result_o[47]_4 [0]),
.I2(\sgf_result_o[47]_5 ),
.I3(\sgf_result_o[47]_3 [3]),
.I4(CO),
.I5(\sgf_result_o[15] ),
.O(sgf_result_o0__1_carry_i_10__5_n_0));
LUT6 #(
.INIT(64'h077FF880F880077F))
sgf_result_o0__1_carry_i_11__11
(.I0(\sgf_result_o[47]_8 [0]),
.I1(\sgf_result_o[47]_9 [0]),
.I2(\sgf_result_o[47]_8 [1]),
.I3(\sgf_result_o[47]_9 [1]),
.I4(\sgf_result_o[47]_9 [2]),
.I5(\sgf_result_o[47]_8 [2]),
.O(\sgf_result_o[47]_2 ));
LUT6 #(
.INIT(64'hD400FD40FD40D400))
sgf_result_o0__1_carry_i_12__8
(.I0(\sgf_result_o[15]_3 ),
.I1(\sgf_result_o[15]_4 ),
.I2(\sgf_result_o[47]_8 [3]),
.I3(\sgf_result_o[47]_10 ),
.I4(\sgf_result_o[47]_9 [0]),
.I5(\sgf_result_o[47]_8 [0]),
.O(sgf_result_o0__1_carry_i_12__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h96696996))
sgf_result_o0__1_carry_i_13__7
(.I0(\sgf_result_o[47]_4 [0]),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\sgf_result_o[15] ),
.I3(\sgf_result_o[47]_3 [3]),
.I4(CO),
.O(sgf_result_o0__1_carry_i_13__7_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h66696999))
sgf_result_o0__1_carry_i_14__0
(.I0(CO),
.I1(\sgf_result_o[47]_3 [3]),
.I2(\sgf_result_o[47]_4 [2]),
.I3(sgf_result_o0__1_carry_i_23__0_n_0),
.I4(\sgf_result_o[47]_3 [2]),
.O(\sgf_result_o[15]_0 ));
LUT6 #(
.INIT(64'hA5959555A9A5A595))
sgf_result_o0__1_carry_i_15__4
(.I0(\sgf_result_o[47]_2 ),
.I1(\sgf_result_o[47]_11 ),
.I2(\sgf_result_o[47]_10 ),
.I3(\sgf_result_o[47]_8 [3]),
.I4(\sgf_result_o[15]_4 ),
.I5(\sgf_result_o[15]_3 ),
.O(sgf_result_o0__1_carry_i_15__4_n_0));
LUT6 #(
.INIT(64'hFFEBAAAAFFFFFFEB))
sgf_result_o0__1_carry_i_16__1
(.I0(\sgf_result_o[47]_6 ),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[15]_0 ),
.I4(\sgf_result_o[47]_5 ),
.I5(sgf_result_o0__1_carry_i_25__0_n_0),
.O(sgf_result_o0__1_carry_i_16__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h96))
sgf_result_o0__1_carry_i_17__3
(.I0(\sgf_result_o[47]_9 [0]),
.I1(\sgf_result_o[47]_8 [0]),
.I2(\sgf_result_o[15]_2 ),
.O(sgf_result_o0__1_carry_i_17__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h66696999))
sgf_result_o0__1_carry_i_18__4
(.I0(\sgf_result_o[15]_4 ),
.I1(\sgf_result_o[47]_8 [3]),
.I2(\sgf_result_o[47]_9 [2]),
.I3(sgf_result_o0__1_carry_i_26__0_n_0),
.I4(\sgf_result_o[47]_8 [2]),
.O(\sgf_result_o[15]_2 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h7887))
sgf_result_o0__1_carry_i_19__4
(.I0(\sgf_result_o[47]_4 [0]),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\sgf_result_o[47]_4 [1]),
.I3(\sgf_result_o[47]_3 [1]),
.O(\sgf_result_o[47]_5 ));
LUT6 #(
.INIT(64'hE11111E1E1EE11E1))
sgf_result_o0__1_carry_i_1__12
(.I0(sgf_result_o0__1_carry_i_8__7_n_0),
.I1(sgf_result_o0__1_carry_i_9__2_n_0),
.I2(sgf_result_o0__1_carry_i_10__5_n_0),
.I3(\sgf_result_o[47]_2 ),
.I4(sgf_result_o0__1_carry_i_12__8_n_0),
.I5(sgf_result_o0__1_carry_i_13__7_n_0),
.O(sgf_result_o0__1_carry_i_1__12_n_0));
LUT6 #(
.INIT(64'h00151555557F7FFF))
sgf_result_o0__1_carry_i_20__3
(.I0(\sgf_result_o[47]_3 [2]),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[47]_3 [1]),
.I4(\sgf_result_o[47]_4 [1]),
.I5(\sgf_result_o[47]_4 [2]),
.O(\sgf_result_o[15] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h8778))
sgf_result_o0__1_carry_i_21__3
(.I0(\sgf_result_o[47]_9 [0]),
.I1(\sgf_result_o[47]_8 [0]),
.I2(\sgf_result_o[47]_9 [1]),
.I3(\sgf_result_o[47]_8 [1]),
.O(\sgf_result_o[47]_10 ));
LUT6 #(
.INIT(64'h00151555557F7FFF))
sgf_result_o0__1_carry_i_22__0
(.I0(\sgf_result_o[47]_8 [2]),
.I1(\sgf_result_o[47]_8 [0]),
.I2(\sgf_result_o[47]_9 [0]),
.I3(\sgf_result_o[47]_8 [1]),
.I4(\sgf_result_o[47]_9 [1]),
.I5(\sgf_result_o[47]_9 [2]),
.O(\sgf_result_o[15]_3 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_23__0
(.I0(\sgf_result_o[47]_4 [1]),
.I1(\sgf_result_o[47]_3 [1]),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[47]_3 [0]),
.O(sgf_result_o0__1_carry_i_23__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o0__1_carry_i_24__0
(.I0(\sgf_result_o[47]_8 [0]),
.I1(\sgf_result_o[47]_9 [0]),
.O(\sgf_result_o[47]_11 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hEEE8E888))
sgf_result_o0__1_carry_i_25__0
(.I0(\sgf_result_o[47]_3 [3]),
.I1(CO),
.I2(\sgf_result_o[47]_3 [2]),
.I3(sgf_result_o0__1_carry_i_23__0_n_0),
.I4(\sgf_result_o[47]_4 [2]),
.O(sgf_result_o0__1_carry_i_25__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hE888))
sgf_result_o0__1_carry_i_26__0
(.I0(\sgf_result_o[47]_9 [1]),
.I1(\sgf_result_o[47]_8 [1]),
.I2(\sgf_result_o[47]_9 [0]),
.I3(\sgf_result_o[47]_8 [0]),
.O(sgf_result_o0__1_carry_i_26__0_n_0));
LUT6 #(
.INIT(64'h2DD2D22D22222222))
sgf_result_o0__1_carry_i_2__12
(.I0(sgf_result_o0__1_carry_i_10__5_n_0),
.I1(sgf_result_o0__1_carry_i_9__2_n_0),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[47]_3 [0]),
.I4(\sgf_result_o[15]_0 ),
.I5(sgf_result_o0__1_carry_i_15__4_n_0),
.O(sgf_result_o0__1_carry_i_2__12_n_0));
LUT4 #(
.INIT(16'h1441))
sgf_result_o0__1_carry_i_3__12
(.I0(sgf_result_o0__1_carry_i_9__2_n_0),
.I1(\sgf_result_o[15]_0 ),
.I2(\sgf_result_o[47]_3 [0]),
.I3(\sgf_result_o[47]_4 [0]),
.O(sgf_result_o0__1_carry_i_3__12_n_0));
LUT6 #(
.INIT(64'h78F078F078F00F0F))
sgf_result_o0__1_carry_i_4__12
(.I0(sgf_result_o0__1_carry_i_10__5_n_0),
.I1(sgf_result_o0__1_carry_i_15__4_n_0),
.I2(sgf_result_o0__1_carry_i_1__12_n_0),
.I3(sgf_result_o0__1_carry_i_3__12_n_0),
.I4(sgf_result_o0__1_carry_i_16__1_n_0),
.I5(sgf_result_o0__1_carry_i_17__3_n_0),
.O(sgf_result_o0__1_carry_i_4__12_n_0));
LUT3 #(
.INIT(8'hA9))
sgf_result_o0__1_carry_i_5__12
(.I0(sgf_result_o0__1_carry_i_2__12_n_0),
.I1(sgf_result_o0__1_carry_i_17__3_n_0),
.I2(sgf_result_o0__1_carry_i_8__7_n_0),
.O(sgf_result_o0__1_carry_i_5__12_n_0));
LUT3 #(
.INIT(8'hB4))
sgf_result_o0__1_carry_i_6__9
(.I0(sgf_result_o0__1_carry_i_17__3_n_0),
.I1(sgf_result_o0__1_carry_i_10__5_n_0),
.I2(sgf_result_o0__1_carry_i_3__12_n_0),
.O(sgf_result_o0__1_carry_i_6__9_n_0));
LUT6 #(
.INIT(64'h0069690069000069))
sgf_result_o0__1_carry_i_7__12
(.I0(\sgf_result_o[15]_0 ),
.I1(\sgf_result_o[47]_3 [0]),
.I2(\sgf_result_o[47]_4 [0]),
.I3(\sgf_result_o[15]_2 ),
.I4(\sgf_result_o[47]_8 [0]),
.I5(\sgf_result_o[47]_9 [0]),
.O(sgf_result_o0__1_carry_i_7__12_n_0));
CARRY4 sgf_result_o0__1_carry_i_8__11
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_8__11_n_0,sgf_result_o0__1_carry_i_8__11_n_1,sgf_result_o0__1_carry_i_8__11_n_2,sgf_result_o0__1_carry_i_8__11_n_3}),
.CYINIT(1'b0),
.DI(\Data_B_i[12] ),
.O(\sgf_result_o[47]_8 ),
.S(\Data_B_i[16] ));
CARRY4 sgf_result_o0__1_carry_i_8__12
(.CI(sgf_result_o0__1_carry_i_8__11_n_0),
.CO({\sgf_result_o[15]_4 ,NLW_sgf_result_o0__1_carry_i_8__12_CO_UNCONNECTED[2],sgf_result_o0__1_carry_i_8__12_n_2,sgf_result_o0__1_carry_i_8__12_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Data_B_i[12]_0 [1:0]}),
.O({NLW_sgf_result_o0__1_carry_i_8__12_O_UNCONNECTED[3],\sgf_result_o[47]_9 }),
.S({1'b1,\Data_B_i[12]_0 [2],\Data_B_i[20]_5 }));
LUT6 #(
.INIT(64'hA5A6A6AA65A5A5A6))
sgf_result_o0__1_carry_i_8__7
(.I0(\sgf_result_o[47]_6 ),
.I1(\sgf_result_o[47]_7 ),
.I2(\sgf_result_o[47]_5 ),
.I3(\sgf_result_o[47]_3 [3]),
.I4(CO),
.I5(\sgf_result_o[15] ),
.O(sgf_result_o0__1_carry_i_8__7_n_0));
LUT6 #(
.INIT(64'hF069690F96F0F069))
sgf_result_o0__1_carry_i_9__2
(.I0(\sgf_result_o[47]_8 [0]),
.I1(\sgf_result_o[47]_9 [0]),
.I2(\sgf_result_o[47]_10 ),
.I3(\sgf_result_o[47]_8 [3]),
.I4(\sgf_result_o[15]_4 ),
.I5(\sgf_result_o[15]_3 ),
.O(sgf_result_o0__1_carry_i_9__2_n_0));
CARRY4 sgf_result_o0__1_carry_i_9__6
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_i_9__6_n_0,sgf_result_o0__1_carry_i_9__6_n_1,sgf_result_o0__1_carry_i_9__6_n_2,sgf_result_o0__1_carry_i_9__6_n_3}),
.CYINIT(1'b0),
.DI(\Data_A_i[12] ),
.O(\sgf_result_o[47]_3 ),
.S(\Data_A_i[16] ));
CARRY4 sgf_result_o0__1_carry_i_9__7
(.CI(sgf_result_o0__1_carry_i_9__6_n_0),
.CO({CO,NLW_sgf_result_o0__1_carry_i_9__7_CO_UNCONNECTED[2],sgf_result_o0__1_carry_i_9__7_n_2,sgf_result_o0__1_carry_i_9__7_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Data_A_i[12]_0 [1:0]}),
.O({NLW_sgf_result_o0__1_carry_i_9__7_O_UNCONNECTED[3],\sgf_result_o[47]_4 }),
.S({1'b1,\Data_A_i[12]_0 [2],\Data_A_i[20]_7 }));
LUT2 #(
.INIT(4'hB))
sgf_result_o1__0_carry__0_i_1__2
(.I0(sgf_result_o0__1_carry__0_n_7),
.I1(\Data_B_i[20]_1 ),
.O(\sgf_result_o[19] [1]));
LUT3 #(
.INIT(8'hB2))
sgf_result_o1__0_carry__0_i_2__2
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[20]_6 ),
.I2(\Data_B_i[20]_4 ),
.O(\sgf_result_o[19] [0]));
LUT3 #(
.INIT(8'h59))
sgf_result_o1__0_carry__0_i_3__2
(.I0(sgf_result_o0__1_carry__0_n_5),
.I1(\Data_A_i[20]_3 ),
.I2(sgf_result_o0__1_carry__0_n_6),
.O(\sgf_result_o[19]_0 [2]));
LUT4 #(
.INIT(16'hD22D))
sgf_result_o1__0_carry__0_i_4__2
(.I0(\Data_B_i[20]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[20]_3 ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(\sgf_result_o[19]_0 [1]));
LUT3 #(
.INIT(8'h96))
sgf_result_o1__0_carry__0_i_5__2
(.I0(\sgf_result_o[19] [0]),
.I1(\Data_B_i[20]_1 ),
.I2(sgf_result_o0__1_carry__0_n_7),
.O(\sgf_result_o[19]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
sgf_result_o1__0_carry_i_12__2
(.I0(\sgf_result_o[47]_3 [0]),
.I1(\sgf_result_o[47]_4 [0]),
.O(\sgf_result_o[47]_7 ));
LUT3 #(
.INIT(8'hB2))
sgf_result_o1__0_carry_i_1__2
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[20]_5 ),
.I2(\Data_B_i[20]_3 ),
.O(\sgf_result_o[15]_1 [2]));
LUT3 #(
.INIT(8'h4D))
sgf_result_o1__0_carry_i_2__2
(.I0(\Data_A_i[20]_4 ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[20]_2 ),
.O(\sgf_result_o[15]_1 [1]));
LUT6 #(
.INIT(64'hFBBFFBBFFBBFA22A))
sgf_result_o1__0_carry_i_3__2
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\sgf_result_o[47]_7 ),
.I2(\sgf_result_o[47]_8 [0]),
.I3(\sgf_result_o[47]_9 [0]),
.I4(\sgf_result_o[15]_0 ),
.I5(\sgf_result_o[15]_2 ),
.O(\sgf_result_o[15]_1 [0]));
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__0_carry_i_4__2
(.I0(sgf_result_o0__1_carry_n_4),
.I1(\Data_A_i[20]_6 ),
.I2(\Data_B_i[20]_4 ),
.I3(\sgf_result_o[15]_1 [2]),
.O(\sgf_result_o[15]_5 [3]));
LUT4 #(
.INIT(16'h9669))
sgf_result_o1__0_carry_i_5__2
(.I0(sgf_result_o0__1_carry_n_5),
.I1(\Data_A_i[20]_5 ),
.I2(\Data_B_i[20]_3 ),
.I3(\sgf_result_o[15]_1 [1]),
.O(\sgf_result_o[15]_5 [2]));
LUT4 #(
.INIT(16'h6996))
sgf_result_o1__0_carry_i_6__2
(.I0(\Data_A_i[20]_4 ),
.I1(sgf_result_o0__1_carry_n_6),
.I2(\Data_B_i[20]_2 ),
.I3(\sgf_result_o[15]_1 [0]),
.O(\sgf_result_o[15]_5 [1]));
LUT6 #(
.INIT(64'h9999966996699999))
sgf_result_o1__0_carry_i_7__2
(.I0(sgf_result_o0__1_carry_n_7),
.I1(\Data_A_i[20]_8 ),
.I2(\sgf_result_o[47]_9 [0]),
.I3(\sgf_result_o[47]_8 [0]),
.I4(\sgf_result_o[47]_4 [0]),
.I5(\sgf_result_o[47]_3 [0]),
.O(\sgf_result_o[15]_5 [0]));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized8
(\sgf_result_o[47] ,
\sgf_result_o[47]_0 ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[47]_5 ,
DI,
S,
\Data_A_i[17] ,
\Data_A_i[13] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12] ,
\Data_B_i[15] ,
\Data_B_i[13] ,
\Data_B_i[16] ,
\Data_A_i[14] ,
\Data_A_i[17]_0 ,
\Data_A_i[17]_1 ,
\Data_A_i[14]_0 ,
\Data_A_i[14]_1 ,
\Data_A_i[17]_2 ,
O,
\Data_A_i[17]_3 ,
\Data_A_i[17]_4 ,
\Data_A_i[14]_2 ,
\Data_B_i[16]_0 );
output [2:0]\sgf_result_o[47] ;
output [2:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [1:0]\sgf_result_o[47]_5 ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_A_i[17] ;
input [2:0]\Data_A_i[13] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[12] ;
input \Data_B_i[15] ;
input \Data_B_i[13] ;
input \Data_B_i[16] ;
input \Data_A_i[14] ;
input \Data_A_i[17]_0 ;
input \Data_A_i[17]_1 ;
input \Data_A_i[14]_0 ;
input \Data_A_i[14]_1 ;
input \Data_A_i[17]_2 ;
input [3:0]O;
input [3:0]\Data_A_i[17]_3 ;
input [3:0]\Data_A_i[17]_4 ;
input [3:0]\Data_A_i[14]_2 ;
input [1:0]\Data_B_i[16]_0 ;
wire [2:0]DI;
wire [2:0]\Data_A_i[13] ;
wire \Data_A_i[14] ;
wire \Data_A_i[14]_0 ;
wire \Data_A_i[14]_1 ;
wire [3:0]\Data_A_i[14]_2 ;
wire [2:0]\Data_A_i[17] ;
wire \Data_A_i[17]_0 ;
wire \Data_A_i[17]_1 ;
wire \Data_A_i[17]_2 ;
wire [3:0]\Data_A_i[17]_3 ;
wire [3:0]\Data_A_i[17]_4 ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire \Data_B_i[13] ;
wire \Data_B_i[15] ;
wire \Data_B_i[16] ;
wire [1:0]\Data_B_i[16]_0 ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire [3:0]S;
wire S_B0__30_carry__0_i_10__0_n_0;
wire S_B0__30_carry__0_i_10__0_n_1;
wire S_B0__30_carry__0_i_10__0_n_2;
wire S_B0__30_carry__0_i_10__0_n_3;
wire S_B0__30_carry__1_i_10__0_n_3;
wire S_B0__30_carry_i_9_n_0;
wire S_B0__30_carry_i_9_n_1;
wire S_B0__30_carry_i_9_n_2;
wire S_B0__30_carry_i_9_n_3;
wire sgf_result_o0__1_carry__0_n_1;
wire sgf_result_o0__1_carry__0_n_2;
wire sgf_result_o0__1_carry__0_n_3;
wire sgf_result_o0__1_carry__0_n_4;
wire sgf_result_o0__1_carry__0_n_6;
wire sgf_result_o0__1_carry__0_n_7;
wire sgf_result_o0__1_carry_n_0;
wire sgf_result_o0__1_carry_n_1;
wire sgf_result_o0__1_carry_n_2;
wire sgf_result_o0__1_carry_n_3;
wire sgf_result_o0__1_carry_n_4;
wire sgf_result_o0__1_carry_n_5;
wire sgf_result_o0__1_carry_n_6;
wire sgf_result_o0__1_carry_n_7;
wire [2:0]\sgf_result_o[47] ;
wire [2:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\^sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [1:0]\sgf_result_o[47]_5 ;
wire [3:1]NLW_S_B0__30_carry__1_i_10__0_CO_UNCONNECTED;
wire [3:2]NLW_S_B0__30_carry__1_i_10__0_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED;
assign \sgf_result_o[47]_2 [3] = sgf_result_o0__1_carry__0_n_4;
assign \sgf_result_o[47]_2 [2:0] = \^sgf_result_o[47]_2 [2:0];
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry__0_i_1__1
(.I0(\Data_A_i[14]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[17]_2 ),
.O(\sgf_result_o[47] [1]));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'h8E))
S_B0__0_carry__0_i_2__1
(.I0(\Data_A_i[17]_1 ),
.I1(sgf_result_o0__1_carry_n_4),
.I2(\Data_A_i[14]_0 ),
.O(\sgf_result_o[47] [0]));
LUT4 #(
.INIT(16'h4DB2))
S_B0__0_carry__0_i_4__1
(.I0(\Data_B_i[13] ),
.I1(\Data_B_i[16] ),
.I2(sgf_result_o0__1_carry__0_n_6),
.I3(\sgf_result_o[47] [2]),
.O(\^sgf_result_o[47]_2 [2]));
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry__0_i_5__1
(.I0(\sgf_result_o[47] [1]),
.I1(\Data_B_i[13] ),
.I2(\Data_B_i[16] ),
.I3(sgf_result_o0__1_carry__0_n_6),
.O(\^sgf_result_o[47]_2 [1]));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry__0_i_6__1
(.I0(\Data_A_i[14]_1 ),
.I1(sgf_result_o0__1_carry__0_n_7),
.I2(\Data_A_i[17]_2 ),
.I3(\sgf_result_o[47] [0]),
.O(\^sgf_result_o[47]_2 [0]));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'h4D))
S_B0__0_carry_i_1__1
(.I0(\Data_A_i[14] ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[17]_0 ),
.O(\sgf_result_o[47]_0 [2]));
LUT6 #(
.INIT(64'h87770000FFFF8777))
S_B0__0_carry_i_2__1
(.I0(Data_B_i_IBUF[2]),
.I1(Data_A_i_IBUF[1]),
.I2(Data_A_i_IBUF[2]),
.I3(Data_B_i_IBUF[1]),
.I4(sgf_result_o0__1_carry_n_6),
.I5(\Data_B_i[12] ),
.O(\sgf_result_o[47]_0 [1]));
(* HLUTNM = "lutpair82" *)
LUT5 #(
.INIT(32'h2ABFBFBF))
S_B0__0_carry_i_3__1
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_0 [0]));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h9669))
S_B0__0_carry_i_4__1
(.I0(\Data_A_i[17]_1 ),
.I1(sgf_result_o0__1_carry_n_4),
.I2(\Data_A_i[14]_0 ),
.I3(\sgf_result_o[47]_0 [2]),
.O(\sgf_result_o[47]_1 [3]));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_5__1
(.I0(\Data_A_i[14] ),
.I1(sgf_result_o0__1_carry_n_5),
.I2(\Data_A_i[17]_0 ),
.I3(\sgf_result_o[47]_0 [1]),
.O(\sgf_result_o[47]_1 [2]));
LUT4 #(
.INIT(16'h6996))
S_B0__0_carry_i_6__1
(.I0(\sgf_result_o[47]_0 [0]),
.I1(\Data_B_i[15] ),
.I2(\Data_B_i[12] ),
.I3(sgf_result_o0__1_carry_n_6),
.O(\sgf_result_o[47]_1 [1]));
(* HLUTNM = "lutpair82" *)
LUT5 #(
.INIT(32'h6A959595))
S_B0__0_carry_i_7__1
(.I0(sgf_result_o0__1_carry_n_7),
.I1(Data_A_i_IBUF[0]),
.I2(Data_B_i_IBUF[0]),
.I3(Data_A_i_IBUF[1]),
.I4(Data_B_i_IBUF[1]),
.O(\sgf_result_o[47]_1 [0]));
CARRY4 S_B0__30_carry__0_i_10__0
(.CI(S_B0__30_carry_i_9_n_0),
.CO({S_B0__30_carry__0_i_10__0_n_0,S_B0__30_carry__0_i_10__0_n_1,S_B0__30_carry__0_i_10__0_n_2,S_B0__30_carry__0_i_10__0_n_3}),
.CYINIT(1'b0),
.DI({\Data_A_i[17]_4 [2:0],O[3]}),
.O(\sgf_result_o[47]_4 ),
.S(\Data_A_i[14]_2 ));
CARRY4 S_B0__30_carry__1_i_10__0
(.CI(S_B0__30_carry__0_i_10__0_n_0),
.CO({NLW_S_B0__30_carry__1_i_10__0_CO_UNCONNECTED[3:1],S_B0__30_carry__1_i_10__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Data_A_i[17]_4 [3]}),
.O({NLW_S_B0__30_carry__1_i_10__0_O_UNCONNECTED[3:2],\sgf_result_o[47]_5 }),
.S({1'b0,1'b0,\Data_B_i[16]_0 }));
CARRY4 S_B0__30_carry_i_9
(.CI(1'b0),
.CO({S_B0__30_carry_i_9_n_0,S_B0__30_carry_i_9_n_1,S_B0__30_carry_i_9_n_2,S_B0__30_carry_i_9_n_3}),
.CYINIT(1'b0),
.DI({O[2:0],1'b0}),
.O(\sgf_result_o[47]_3 ),
.S(\Data_A_i[17]_3 ));
CARRY4 sgf_result_o0__1_carry
(.CI(1'b0),
.CO({sgf_result_o0__1_carry_n_0,sgf_result_o0__1_carry_n_1,sgf_result_o0__1_carry_n_2,sgf_result_o0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({DI,1'b0}),
.O({sgf_result_o0__1_carry_n_4,sgf_result_o0__1_carry_n_5,sgf_result_o0__1_carry_n_6,sgf_result_o0__1_carry_n_7}),
.S(S));
CARRY4 sgf_result_o0__1_carry__0
(.CI(sgf_result_o0__1_carry_n_0),
.CO({NLW_sgf_result_o0__1_carry__0_CO_UNCONNECTED[3],sgf_result_o0__1_carry__0_n_1,sgf_result_o0__1_carry__0_n_2,sgf_result_o0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\Data_A_i[17] }),
.O({sgf_result_o0__1_carry__0_n_4,\sgf_result_o[47] [2],sgf_result_o0__1_carry__0_n_6,sgf_result_o0__1_carry__0_n_7}),
.S({1'b1,\Data_A_i[13] }));
endmodule
(* ORIG_REF_NAME = "Recursive_KOA" *)
module Recursive_KOA__parameterized9
(O,
\sgf_result_o[23] ,
\sgf_result_o[23]_0 ,
\sgf_result_o[47] ,
\sgf_result_o[15] ,
\sgf_result_o[15]_0 ,
\sgf_result_o[15]_1 ,
\sgf_result_o[15]_2 ,
\sgf_result_o[23]_1 ,
\sgf_result_o[47]_0 ,
\sgf_result_o[19] ,
\sgf_result_o[47]_1 ,
\sgf_result_o[47]_2 ,
\sgf_result_o[47]_3 ,
\sgf_result_o[47]_4 ,
\sgf_result_o[39] ,
\sgf_result_o[43] ,
DI,
S,
\Data_B_i[18] ,
\Data_A_i[18] ,
\Data_A_i[22] ,
Data_B_i_IBUF,
Data_A_i_IBUF,
\Data_B_i[12] ,
\Data_A_i[18]_0 ,
p_0_in,
\Data_B_i[18]_0 ,
\Data_B_i[18]_1 ,
CO,
\Data_B_i[18]_2 ,
\Data_A_i[18]_1 ,
\Data_B_i[18]_3 ,
\Data_A_i[18]_2 ,
\Data_B_i[18]_4 ,
\Data_A_i[18]_3 ,
\Data_A_i[18]_4 ,
\Data_A_i[23] ,
\Data_A_i[17] ,
Q_middle_temp__2,
\Data_A_i[17]_0 ,
\Data_A_i[23]_0 ,
\Data_A_i[17]_1 ,
\Data_A_i[17]_2 ,
\Data_A_i[14] ,
\Data_A_i[14]_0 ,
\Data_A_i[14]_1 ,
\Data_A_i[23]_1 ,
\Data_A_i[20] );
output [3:0]O;
output [3:0]\sgf_result_o[23] ;
output [0:0]\sgf_result_o[23]_0 ;
output [2:0]\sgf_result_o[47] ;
output \sgf_result_o[15] ;
output \sgf_result_o[15]_0 ;
output \sgf_result_o[15]_1 ;
output \sgf_result_o[15]_2 ;
output [2:0]\sgf_result_o[23]_1 ;
output [3:0]\sgf_result_o[47]_0 ;
output [3:0]\sgf_result_o[19] ;
output [3:0]\sgf_result_o[47]_1 ;
output [3:0]\sgf_result_o[47]_2 ;
output [3:0]\sgf_result_o[47]_3 ;
output [3:0]\sgf_result_o[47]_4 ;
output [3:0]\sgf_result_o[39] ;
output [2:0]\sgf_result_o[43] ;
input [2:0]DI;
input [3:0]S;
input [2:0]\Data_B_i[18] ;
input [2:0]\Data_A_i[18] ;
input [0:0]\Data_A_i[22] ;
input [2:0]Data_B_i_IBUF;
input [2:0]Data_A_i_IBUF;
input \Data_B_i[12] ;
input [3:0]\Data_A_i[18]_0 ;
input [2:0]p_0_in;
input [3:0]\Data_B_i[18]_0 ;
input [1:0]\Data_B_i[18]_1 ;
input [0:0]CO;
input \Data_B_i[18]_2 ;
input \Data_A_i[18]_1 ;
input \Data_B_i[18]_3 ;
input \Data_A_i[18]_2 ;
input \Data_B_i[18]_4 ;
input \Data_A_i[18]_3 ;
input \Data_A_i[18]_4 ;
input [1:0]\Data_A_i[23] ;
input [1:0]\Data_A_i[17] ;
input [0:0]Q_middle_temp__2;
input [3:0]\Data_A_i[17]_0 ;
input [3:0]\Data_A_i[23]_0 ;
input [3:0]\Data_A_i[17]_1 ;
input [3:0]\Data_A_i[17]_2 ;
input [3:0]\Data_A_i[14] ;
input [3:0]\Data_A_i[14]_0 ;
input [1:0]\Data_A_i[14]_1 ;
input [3:0]\Data_A_i[23]_1 ;
input [2:0]\Data_A_i[20] ;
wire [0:0]CO;
wire [2:0]DI;
wire [3:0]\Data_A_i[14] ;
wire [3:0]\Data_A_i[14]_0 ;
wire [1:0]\Data_A_i[14]_1 ;
wire [1:0]\Data_A_i[17] ;
wire [3:0]\Data_A_i[17]_0 ;
wire [3:0]\Data_A_i[17]_1 ;
wire [3:0]\Data_A_i[17]_2 ;
wire [2:0]\Data_A_i[18] ;
wire [3:0]\Data_A_i[18]_0 ;
wire \Data_A_i[18]_1 ;
wire \Data_A_i[18]_2 ;
wire \Data_A_i[18]_3 ;
wire \Data_A_i[18]_4 ;
wire [2:0]\Data_A_i[20] ;
wire [0:0]\Data_A_i[22] ;
wire [1:0]\Data_A_i[23] ;
wire [3:0]\Data_A_i[23]_0 ;
wire [3:0]\Data_A_i[23]_1 ;
wire [2:0]Data_A_i_IBUF;
wire \Data_B_i[12] ;
wire [2:0]\Data_B_i[18] ;
wire [3:0]\Data_B_i[18]_0 ;
wire [1:0]\Data_B_i[18]_1 ;
wire \Data_B_i[18]_2 ;
wire \Data_B_i[18]_3 ;
wire \Data_B_i[18]_4 ;
wire [2:0]Data_B_i_IBUF;
wire [3:0]O;
wire \ODD1.middle_n_0 ;
wire \ODD1.middle_n_1 ;
wire \ODD1.middle_n_10 ;
wire \ODD1.middle_n_12 ;
wire \ODD1.middle_n_13 ;
wire \ODD1.middle_n_14 ;
wire \ODD1.middle_n_15 ;
wire \ODD1.middle_n_16 ;
wire \ODD1.middle_n_17 ;
wire \ODD1.middle_n_18 ;
wire \ODD1.middle_n_19 ;
wire \ODD1.middle_n_2 ;
wire \ODD1.middle_n_20 ;
wire \ODD1.middle_n_21 ;
wire \ODD1.middle_n_22 ;
wire \ODD1.middle_n_3 ;
wire \ODD1.middle_n_4 ;
wire \ODD1.middle_n_5 ;
wire \ODD1.middle_n_7 ;
wire \ODD1.middle_n_9 ;
wire \ODD1.right_lower_n_0 ;
wire \ODD1.right_lower_n_10 ;
wire \ODD1.right_lower_n_11 ;
wire \ODD1.right_lower_n_12 ;
wire \ODD1.right_lower_n_13 ;
wire \ODD1.right_lower_n_14 ;
wire \ODD1.right_lower_n_15 ;
wire \ODD1.right_lower_n_16 ;
wire \ODD1.right_lower_n_17 ;
wire \ODD1.right_lower_n_18 ;
wire \ODD1.right_lower_n_4 ;
wire \ODD1.right_lower_n_5 ;
wire \ODD1.right_lower_n_6 ;
wire \ODD1.right_lower_n_7 ;
wire \ODD1.right_lower_n_8 ;
wire \ODD1.right_lower_n_9 ;
wire [9:2]Q_middle_temp__1;
wire [0:0]Q_middle_temp__2;
wire [3:0]S;
wire [2:0]p_0_in;
wire sgf_result_o1__0_carry__0_i_6__0_n_0;
wire sgf_result_o1__0_carry__0_i_7__0_n_0;
wire sgf_result_o1__0_carry_i_10__0_n_0;
wire sgf_result_o1__0_carry_i_11__0_n_0;
wire sgf_result_o1__0_carry_i_14__0_n_0;
wire sgf_result_o1__0_carry_i_15__0_n_0;
wire sgf_result_o1__0_carry_i_16__0_n_0;
wire sgf_result_o1__0_carry_i_17__0_n_0;
wire sgf_result_o1__0_carry_i_19__0_n_0;
wire sgf_result_o1__0_carry_i_8__0_n_0;
wire sgf_result_o1__0_carry_i_9__0_n_0;
wire sgf_result_o1__21_carry__0_n_0;
wire sgf_result_o1__21_carry__0_n_1;
wire sgf_result_o1__21_carry__0_n_2;
wire sgf_result_o1__21_carry__0_n_3;
wire sgf_result_o1__21_carry__1_i_1__0_n_0;
wire sgf_result_o1__21_carry__1_n_3;
wire sgf_result_o1__21_carry__1_n_6;
wire sgf_result_o1__21_carry_n_0;
wire sgf_result_o1__21_carry_n_1;
wire sgf_result_o1__21_carry_n_2;
wire sgf_result_o1__21_carry_n_3;
wire sgf_result_o1_carry__0_n_1;
wire sgf_result_o1_carry__0_n_2;
wire sgf_result_o1_carry__0_n_3;
wire sgf_result_o1_carry_n_0;
wire sgf_result_o1_carry_n_1;
wire sgf_result_o1_carry_n_2;
wire sgf_result_o1_carry_n_3;
wire \sgf_result_o[15] ;
wire \sgf_result_o[15]_0 ;
wire \sgf_result_o[15]_1 ;
wire \sgf_result_o[15]_2 ;
wire [3:0]\sgf_result_o[19] ;
wire [3:0]\sgf_result_o[23] ;
wire [0:0]\sgf_result_o[23]_0 ;
wire [2:0]\sgf_result_o[23]_1 ;
wire [3:0]\sgf_result_o[39] ;
wire [2:0]\sgf_result_o[43] ;
wire [2:0]\sgf_result_o[47] ;
wire [3:0]\sgf_result_o[47]_0 ;
wire [3:0]\sgf_result_o[47]_1 ;
wire [3:0]\sgf_result_o[47]_2 ;
wire [3:0]\sgf_result_o[47]_3 ;
wire [3:0]\sgf_result_o[47]_4 ;
wire [3:1]NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED;
wire [3:3]NLW_sgf_result_o1_carry__0_CO_UNCONNECTED;
Recursive_KOA__parameterized12 \ODD1.middle
(.CO(CO),
.\Data_A_i[18] (\Data_A_i[18]_0 ),
.\Data_A_i[18]_0 (Q_middle_temp__1[8:7]),
.\Data_A_i[22] (sgf_result_o1__0_carry_i_14__0_n_0),
.\Data_A_i[22]_0 (sgf_result_o1__0_carry__0_i_7__0_n_0),
.\Data_A_i[22]_1 (sgf_result_o1__0_carry_i_8__0_n_0),
.\Data_A_i[22]_2 (sgf_result_o1__0_carry_i_9__0_n_0),
.\Data_A_i[22]_3 (sgf_result_o1__0_carry_i_17__0_n_0),
.\Data_A_i[22]_4 (sgf_result_o1__0_carry_i_11__0_n_0),
.\Data_B_i[18] (\Data_B_i[18]_0 ),
.\Data_B_i[18]_0 (\Data_B_i[18]_1 ),
.\Data_B_i[18]_1 (sgf_result_o1__0_carry__0_i_6__0_n_0),
.\Data_B_i[18]_2 (\ODD1.right_lower_n_0 ),
.\Data_B_i[18]_3 (sgf_result_o1__0_carry_i_16__0_n_0),
.\Data_B_i[22] (sgf_result_o1__0_carry_i_15__0_n_0),
.\Data_B_i[22]_0 (sgf_result_o1__0_carry_i_10__0_n_0),
.O({\ODD1.middle_n_0 ,\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 }),
.S({\ODD1.middle_n_15 ,\ODD1.middle_n_16 ,\ODD1.middle_n_17 }),
.p_0_in(p_0_in),
.\sgf_result_o[15] (\sgf_result_o[15] ),
.\sgf_result_o[15]_0 (\ODD1.middle_n_7 ),
.\sgf_result_o[15]_1 (\sgf_result_o[15]_0 ),
.\sgf_result_o[15]_2 (\ODD1.middle_n_9 ),
.\sgf_result_o[15]_3 (\ODD1.middle_n_10 ),
.\sgf_result_o[15]_4 (\sgf_result_o[15]_1 ),
.\sgf_result_o[15]_5 (\ODD1.middle_n_12 ),
.\sgf_result_o[15]_6 (\ODD1.middle_n_13 ),
.\sgf_result_o[15]_7 (\ODD1.middle_n_14 ),
.\sgf_result_o[19] ({\ODD1.middle_n_4 ,\ODD1.middle_n_5 }),
.\sgf_result_o[19]_0 ({\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 ,\ODD1.middle_n_21 }),
.\sgf_result_o[23] (\ODD1.middle_n_22 ));
Recursive_KOA__parameterized11 \ODD1.right_lower
(.DI(DI),
.\Data_A_i[14] (\Data_A_i[14] ),
.\Data_A_i[14]_0 (\Data_A_i[14]_0 ),
.\Data_A_i[14]_1 (\Data_A_i[14]_1 ),
.\Data_A_i[17] (\Data_A_i[17] ),
.\Data_A_i[17]_0 (\Data_A_i[17]_0 ),
.\Data_A_i[17]_1 (\Data_A_i[17]_1 ),
.\Data_A_i[17]_2 (\Data_A_i[17]_2 ),
.\Data_A_i[18] (\Data_A_i[18] ),
.\Data_A_i[18]_0 (\Data_A_i[18]_1 ),
.\Data_A_i[18]_1 (\Data_A_i[18]_3 ),
.\Data_A_i[18]_2 (\Data_A_i[18]_4 ),
.\Data_A_i[18]_3 (\Data_A_i[18]_2 ),
.\Data_A_i[18]_4 (\Data_A_i[18]_0 [0]),
.\Data_A_i[20] (\Data_A_i[20] ),
.\Data_A_i[23] (\Data_A_i[23] ),
.\Data_A_i[23]_0 (\Data_A_i[23]_0 ),
.\Data_A_i[23]_1 (\Data_A_i[23]_1 ),
.Data_A_i_IBUF(Data_A_i_IBUF),
.\Data_B_i[12] (\Data_B_i[12] ),
.\Data_B_i[18] (\Data_B_i[18] ),
.\Data_B_i[18]_0 (\Data_B_i[18]_1 ),
.\Data_B_i[18]_1 (\Data_B_i[18]_2 ),
.\Data_B_i[18]_2 (\Data_B_i[18]_4 ),
.\Data_B_i[18]_3 (\Data_B_i[18]_0 [0]),
.\Data_B_i[22] (sgf_result_o1__0_carry_i_10__0_n_0),
.Data_B_i_IBUF(Data_B_i_IBUF),
.O(O),
.Q_middle_temp__1(Q_middle_temp__1[7:2]),
.Q_middle_temp__2(Q_middle_temp__2),
.S(S),
.p_0_in(p_0_in[1:0]),
.\sgf_result_o[15] ({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 }),
.\sgf_result_o[15]_0 ({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }),
.\sgf_result_o[19] (\ODD1.right_lower_n_0 ),
.\sgf_result_o[19]_0 ({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.\sgf_result_o[19]_1 ({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }),
.\sgf_result_o[19]_2 (\sgf_result_o[19] [0]),
.\sgf_result_o[39] (\sgf_result_o[39] ),
.\sgf_result_o[43] (\sgf_result_o[43] ),
.\sgf_result_o[47] (\sgf_result_o[47] ),
.\sgf_result_o[47]_0 (\sgf_result_o[47]_0 ),
.\sgf_result_o[47]_1 (\sgf_result_o[47]_1 ),
.\sgf_result_o[47]_2 (\sgf_result_o[47]_2 ),
.\sgf_result_o[47]_3 (\sgf_result_o[47]_3 ),
.\sgf_result_o[47]_4 (\sgf_result_o[47]_4 ));
LUT6 #(
.INIT(64'h9A956595956A6A6A))
S_B0_carry__0_i_1__1
(.I0(\sgf_result_o[23] [2]),
.I1(p_0_in[2]),
.I2(\Data_B_i[18]_1 [0]),
.I3(p_0_in[0]),
.I4(CO),
.I5(\Data_B_i[18]_3 ),
.O(\sgf_result_o[19] [3]));
LUT5 #(
.INIT(32'h956A6A6A))
S_B0_carry__0_i_2__0
(.I0(\sgf_result_o[23] [1]),
.I1(\Data_B_i[18]_1 [0]),
.I2(p_0_in[1]),
.I3(p_0_in[0]),
.I4(\Data_B_i[18]_1 [1]),
.O(\sgf_result_o[19] [2]));
LUT3 #(
.INIT(8'h6A))
S_B0_carry__0_i_3__0
(.I0(\sgf_result_o[23] [0]),
.I1(p_0_in[0]),
.I2(\Data_B_i[18]_1 [0]),
.O(\sgf_result_o[19] [1]));
LUT2 #(
.INIT(4'h6))
S_B0_carry__1_i_1__0
(.I0(sgf_result_o1__21_carry__1_n_6),
.I1(\Data_B_i[18]_2 ),
.O(\sgf_result_o[23]_1 [2]));
LUT2 #(
.INIT(4'h6))
S_B0_carry__1_i_2
(.I0(\sgf_result_o[23]_0 ),
.I1(\Data_A_i[18]_2 ),
.O(\sgf_result_o[23]_1 [1]));
LUT2 #(
.INIT(4'h9))
S_B0_carry__1_i_3__0
(.I0(\sgf_result_o[23] [3]),
.I1(\Data_A_i[18]_4 ),
.O(\sgf_result_o[23]_1 [0]));
LUT6 #(
.INIT(64'h0400464B04000B0B))
sgf_result_o1__0_carry__0_i_6__0
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\sgf_result_o[15] ),
.I3(\sgf_result_o[15]_1 ),
.I4(\sgf_result_o[15]_0 ),
.I5(\ODD1.middle_n_13 ),
.O(sgf_result_o1__0_carry__0_i_6__0_n_0));
LUT6 #(
.INIT(64'h0020000000330020))
sgf_result_o1__0_carry__0_i_7__0
(.I0(\ODD1.middle_n_13 ),
.I1(\sgf_result_o[15]_0 ),
.I2(\sgf_result_o[15]_1 ),
.I3(\sgf_result_o[15] ),
.I4(\ODD1.middle_n_7 ),
.I5(\ODD1.middle_n_9 ),
.O(sgf_result_o1__0_carry__0_i_7__0_n_0));
LUT6 #(
.INIT(64'h6060609F609F6060))
sgf_result_o1__0_carry_i_10__0
(.I0(\Data_A_i[18]_0 [0]),
.I1(p_0_in[0]),
.I2(\ODD1.middle_n_7 ),
.I3(\ODD1.middle_n_9 ),
.I4(\Data_B_i[18]_0 [0]),
.I5(\Data_B_i[18]_1 [0]),
.O(sgf_result_o1__0_carry_i_10__0_n_0));
LUT6 #(
.INIT(64'h6868688068808080))
sgf_result_o1__0_carry_i_11__0
(.I0(\Data_A_i[18]_0 [3]),
.I1(\ODD1.middle_n_10 ),
.I2(\Data_B_i[18]_0 [3]),
.I3(\Data_B_i[18]_0 [2]),
.I4(\ODD1.middle_n_14 ),
.I5(CO),
.O(sgf_result_o1__0_carry_i_11__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_14__0
(.I0(\Data_A_i[18]_0 [3]),
.I1(\Data_A_i[18]_0 [2]),
.I2(\ODD1.middle_n_12 ),
.I3(p_0_in[2]),
.O(sgf_result_o1__0_carry_i_14__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h566A))
sgf_result_o1__0_carry_i_15__0
(.I0(\Data_B_i[18]_0 [3]),
.I1(\Data_B_i[18]_0 [2]),
.I2(\ODD1.middle_n_14 ),
.I3(CO),
.O(sgf_result_o1__0_carry_i_15__0_n_0));
LUT6 #(
.INIT(64'hBEFA7D72FEFA3236))
sgf_result_o1__0_carry_i_16__0
(.I0(\ODD1.middle_n_9 ),
.I1(\ODD1.middle_n_7 ),
.I2(\sgf_result_o[15] ),
.I3(\sgf_result_o[15]_1 ),
.I4(\sgf_result_o[15]_0 ),
.I5(\ODD1.middle_n_13 ),
.O(sgf_result_o1__0_carry_i_16__0_n_0));
LUT2 #(
.INIT(4'h8))
sgf_result_o1__0_carry_i_17__0
(.I0(sgf_result_o1__0_carry_i_15__0_n_0),
.I1(sgf_result_o1__0_carry_i_14__0_n_0),
.O(sgf_result_o1__0_carry_i_17__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hA880))
sgf_result_o1__0_carry_i_19__0
(.I0(\Data_A_i[18]_0 [3]),
.I1(\Data_A_i[18]_0 [2]),
.I2(\ODD1.middle_n_12 ),
.I3(p_0_in[2]),
.O(sgf_result_o1__0_carry_i_19__0_n_0));
LUT6 #(
.INIT(64'h9A9A3AC53AC59A9A))
sgf_result_o1__0_carry_i_8__0
(.I0(\sgf_result_o[15]_2 ),
.I1(\sgf_result_o[15] ),
.I2(\sgf_result_o[15]_1 ),
.I3(\sgf_result_o[15]_0 ),
.I4(\Data_B_i[18]_1 [0]),
.I5(\Data_B_i[18]_0 [0]),
.O(sgf_result_o1__0_carry_i_8__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hE8000000))
sgf_result_o1__0_carry_i_9__0
(.I0(CO),
.I1(\ODD1.middle_n_14 ),
.I2(\Data_B_i[18]_0 [2]),
.I3(\Data_B_i[18]_0 [3]),
.I4(sgf_result_o1__0_carry_i_19__0_n_0),
.O(sgf_result_o1__0_carry_i_9__0_n_0));
CARRY4 sgf_result_o1__21_carry
(.CI(1'b0),
.CO({sgf_result_o1__21_carry_n_0,sgf_result_o1__21_carry_n_1,sgf_result_o1__21_carry_n_2,sgf_result_o1__21_carry_n_3}),
.CYINIT(1'b1),
.DI({\ODD1.right_lower_n_4 ,\ODD1.right_lower_n_5 ,\ODD1.right_lower_n_6 ,1'b1}),
.O(O),
.S({\ODD1.right_lower_n_11 ,\ODD1.right_lower_n_12 ,\ODD1.right_lower_n_13 ,\ODD1.right_lower_n_14 }));
CARRY4 sgf_result_o1__21_carry__0
(.CI(sgf_result_o1__21_carry_n_0),
.CO({sgf_result_o1__21_carry__0_n_0,sgf_result_o1__21_carry__0_n_1,sgf_result_o1__21_carry__0_n_2,sgf_result_o1__21_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.right_lower_n_7 ,\ODD1.right_lower_n_8 ,\ODD1.right_lower_n_9 ,\ODD1.right_lower_n_10 }),
.O(\sgf_result_o[23] ),
.S({\ODD1.right_lower_n_15 ,\ODD1.right_lower_n_16 ,\ODD1.right_lower_n_17 ,\ODD1.right_lower_n_18 }));
CARRY4 sgf_result_o1__21_carry__1
(.CI(sgf_result_o1__21_carry__0_n_0),
.CO({NLW_sgf_result_o1__21_carry__1_CO_UNCONNECTED[3:1],sgf_result_o1__21_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q_middle_temp__1[8]}),
.O({NLW_sgf_result_o1__21_carry__1_O_UNCONNECTED[3:2],sgf_result_o1__21_carry__1_n_6,\sgf_result_o[23]_0 }),
.S({1'b0,1'b0,sgf_result_o1__21_carry__1_i_1__0_n_0,\ODD1.middle_n_22 }));
LUT1 #(
.INIT(2'h1))
sgf_result_o1__21_carry__1_i_1__0
(.I0(Q_middle_temp__1[9]),
.O(sgf_result_o1__21_carry__1_i_1__0_n_0));
CARRY4 sgf_result_o1_carry
(.CI(1'b0),
.CO({sgf_result_o1_carry_n_0,sgf_result_o1_carry_n_1,sgf_result_o1_carry_n_2,sgf_result_o1_carry_n_3}),
.CYINIT(1'b0),
.DI({\ODD1.middle_n_1 ,\ODD1.middle_n_2 ,\ODD1.middle_n_3 ,1'b0}),
.O(Q_middle_temp__1[5:2]),
.S({\ODD1.middle_n_15 ,\ODD1.middle_n_16 ,\ODD1.middle_n_17 ,\Data_A_i[22] }));
CARRY4 sgf_result_o1_carry__0
(.CI(sgf_result_o1_carry_n_0),
.CO({NLW_sgf_result_o1_carry__0_CO_UNCONNECTED[3],sgf_result_o1_carry__0_n_1,sgf_result_o1_carry__0_n_2,sgf_result_o1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\ODD1.middle_n_4 ,\ODD1.middle_n_5 ,\ODD1.middle_n_0 }),
.O(Q_middle_temp__1[9:6]),
.S({\ODD1.middle_n_18 ,\ODD1.middle_n_19 ,\ODD1.middle_n_20 ,\ODD1.middle_n_21 }));
LUT5 #(
.INIT(32'h00009666))
sgf_result_o1_carry_i_5__0
(.I0(\Data_B_i[18]_0 [1]),
.I1(\Data_B_i[18]_1 [1]),
.I2(\Data_B_i[18]_0 [0]),
.I3(\Data_B_i[18]_1 [0]),
.I4(\ODD1.middle_n_9 ),
.O(\sgf_result_o[15]_2 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_BLACKBOX_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: sys_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sys_pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire7;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [2:2] sub_wire6 = sub_wire3[2:2];
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire c2 = sub_wire6;
wire locked = sub_wire7;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire7),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3125,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "4.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.016000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "4.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 43: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 43: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 43: 0] entry_0;
reg [ 43: 0] entry_1;
wire full;
reg rd_address;
reg [ 43: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 24: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 24: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 24: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 43: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 13: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
wasca_external_sdram_controller_input_efifo_module the_wasca_external_sdram_controller_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[24],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 10000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 1;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 7;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[24],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 1;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[23 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 2;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 1;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 7;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/*
*
* Copyright (c) 2012-2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define IDX(x) (((x)+1)*(8)-1):((x)*(8))
`define IDX4(x) (((x)+1)*(4)-1):((x)*(4))
// Finds a collision with a given SHA1 hash, given some information about the
// input message.
module sha1_collision_top (
input CLK_100MHZ
);
// Clock Generator
wire hash_clk;
main_pll clk_blk (
.CLK_IN1 (CLK_100MHZ),
.CLK_OUT1 (hash_clk)
);
// SHA1 Hashers
wire [511:0] expanded_message0, expanded_message1;
wire [159:0] hash0, hash1;
sha1 hasher0 ( .clk (hash_clk), .rx_data (expanded_message0), .tx_hash (hash0) );
sha1 hasher1 ( .clk (hash_clk), .rx_data (expanded_message1), .tx_hash (hash1) );
// Comm
reg [59:0] golden_nonce = 0;
reg golden_nonce_found = 1'b0;
wire comm_new_work;
wire [55:0] comm_fixed_data;
wire [159:0] comm_target_hash;
wire [59:0] comm_start_nonce;
jtag_comm comm_blk (
.rx_hash_clk (hash_clk),
.rx_golden_nonce_found (golden_nonce_found),
.rx_golden_nonce (golden_nonce),
.tx_new_work (comm_new_work),
.tx_fixed_data (comm_fixed_data),
.tx_target_hash (comm_target_hash),
.tx_start_nonce (comm_start_nonce)
);
// Nonce Counter
wire [59:0] nonce;
wire [59:0] nonce0, nonce1;
bcd_counter # (.STEP(2)) counter_blk (
.clk (hash_clk),
.rst (golden_nonce_found | comm_new_work),
.rx_reset_value (comm_start_nonce),
.tx_nonce (nonce)
);
bcd_add counter_add0 ( .clk (hash_clk), .rx_a (nonce), .rx_b (4'd0), .tx_sum (nonce0) );
bcd_add counter_add1 ( .clk (hash_clk), .rx_a (nonce), .rx_b (4'd1), .tx_sum (nonce1) );
// Controller
reg [14*4-1:0] fixed_data = 56'h35691903801083;
reg [159:0] target_hash = 160'h754d1309a35eb188292dc628947a0e70ab7ccd2a; //160'h3b8d562adb792985a7393a6ab228aa6e7526410a;
// secret nonce is 000000509803065
expand_message msg0 ( .clk (hash_clk), .rx_fixed_data (fixed_data), .rx_nonce (nonce0), .tx_expanded_message (expanded_message0) );
expand_message msg1 ( .clk (hash_clk), .rx_fixed_data (fixed_data), .rx_nonce (nonce1), .tx_expanded_message (expanded_message1) );
always @ (posedge hash_clk)
begin
fixed_data <= comm_fixed_data;
target_hash <= comm_target_hash;
// Constantly updating the golden nonce until we've found
// a real golden nonce allows the external controller to
// monitor progress.
if (!golden_nonce_found)
golden_nonce <= nonce;
// Collision found?
if (hash0 == target_hash || hash1 == target_hash)
golden_nonce_found <= 1'b1;
if (comm_new_work)
golden_nonce_found <= 1'b0;
end
endmodule
module expand_message (
input clk,
input [14*4-1:0] rx_fixed_data,
input [59:0] rx_nonce,
output reg [511:0] tx_expanded_message
);
always @ (posedge clk)
begin
tx_expanded_message <= {32'd192, 32'h0, 224'h0, 32'h80000000, rx_fixed_data[`IDX(2)], rx_fixed_data[`IDX(1)], rx_fixed_data[`IDX(0)], 8'h00, rx_fixed_data[`IDX(6)], rx_fixed_data[`IDX(5)], rx_fixed_data[`IDX(4)], rx_fixed_data[`IDX(3)], {4'b0,rx_nonce[`IDX4(2)]}, {4'b0,rx_nonce[`IDX4(1)]}, {4'b0,rx_nonce[`IDX4(0)]}, 8'h00, {4'b0,rx_nonce[`IDX4(6)]}, {4'b0,rx_nonce[`IDX4(5)]}, {4'b0,rx_nonce[`IDX4(4)]}, {4'b0,rx_nonce[`IDX4(3)]}, {4'b0,rx_nonce[`IDX4(10)]}, {4'b0,rx_nonce[`IDX4(9)]}, {4'b0,rx_nonce[`IDX4(8)]}, {4'b0,rx_nonce[`IDX4(7)]}, {4'b0,rx_nonce[`IDX4(14)]}, {4'b0,rx_nonce[`IDX4(13)]}, {4'b0,rx_nonce[`IDX4(12)]}, {4'b0,rx_nonce[`IDX4(11)]}};
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_SYMBOL_V
`define SKY130_FD_SC_HVL__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_ep_7x.v
// Version : 1.3
//--
//-- Description: PCI Express Endpoint example FPGA design
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module xilinx_pcie_2_1_ep_7x # (
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
output [3:0] pci_exp_txp,
output [3:0] pci_exp_txn,
input [3:0] pci_exp_rxp,
input [3:0] pci_exp_rxn,
`ifdef ENABLE_LEDS
output led_0,
output led_1,
output led_2,
output led_3,
`endif
input sys_clk_p,
input sys_clk_n,
input sys_rst_n
);
localparam TCQ = 1;
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
wire [5:0] tx_buf_av;
wire tx_cfg_req;
wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
wire rx_np_req;
// Flow Control
wire [11:0] fc_cpld;
wire [7:0] fc_cplh;
wire [11:0] fc_npd;
wire [7:0] fc_nph;
wire [11:0] fc_pd;
wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire [63:0] cfg_dsn;
wire [127:0] cfg_err_aer_headerlog;
wire [4:0] cfg_aer_interrupt_msgnum;
wire cfg_err_aer_headerlog_set;
wire cfg_aer_ecrc_check_en;
wire cfg_aer_ecrc_gen_en;
wire [31:0] cfg_mgmt_di;
wire [3:0] cfg_mgmt_byte_en;
wire [9:0] cfg_mgmt_dwaddr;
wire cfg_mgmt_wr_en;
wire cfg_mgmt_rd_en;
wire cfg_mgmt_wr_readonly;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_cap;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_cap;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_lnk_rate;
wire [1:0] pl_sel_lnk_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_rst_n_c;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire [3:0] PIPE_RXUSRCLK_IN;
wire PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [3:0] PIPE_RXOUTCLK_OUT;
wire [3:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
localparam USER_CLK_FREQ = 3;
localparam USER_CLK2_DIV2 = "TRUE";
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
//-------------------------------------------------------
IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
`ifdef SIMULATION
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
`else
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .IB(sys_clk_n));
`endif
`ifdef ENABLE_LEDS
// Uncomment UCF location constraints
OBUF led_0_obuf (.O(led_0), .I(sys_rst_n_c));
OBUF led_1_obuf (.O(led_1), .I(!user_reset));
OBUF led_2_obuf (.O(led_2), .I(user_lnk_up));
OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25]));
`endif
reg user_reset_q;
reg user_lnk_up_q;
always @(posedge user_clk) begin
user_reset_q <= user_reset;
user_lnk_up_q <= user_lnk_up;
end
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
//---------- PIPE Clock Module -------------------------------------------------
pcie_7x_v1_3_pipe_clock #
(
.PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable
.PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE ( 6'h04 ), // PCIe number of lanes
`ifdef SIMULATION // PCIe Link Speed
.PCIE_LINK_SPEED ( 2 ),
`else
.PCIE_LINK_SPEED ( 3 ),
`endif
.PCIE_REFCLK_FREQ ( 0 ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk ),
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
pcie_7x_v1_3 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK )
) pcie_7x_v1_3_i
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_OOBCLK_IN ( 1'b0 ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
// TX
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
.cfg_mgmt_do ( ),
.cfg_mgmt_rd_wr_done ( ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_received_func_lvl_rst ( ),
// Management Interface
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
// Error Reporting Interface
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_pm_wake ( cfg_pm_wake ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_directed_change_done ( ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.pl_received_hot_rst ( pl_received_hot_rst ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.pl_transmit_hot_rst ( 1'b0 ),
.pl_downstream_deemph_source ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_reset ( ~sys_rst_n_c )
);
pcie_app_7x #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ )
)app (
//----------------------------------------------------------------------------------------------------------------//
// 1. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk ( user_clk ),
.user_reset ( user_reset_q ),
.user_lnk_up ( user_lnk_up_q ),
// Tx
.tx_buf_av ( tx_buf_av ),
.tx_cfg_req ( tx_cfg_req ),
.tx_err_drop ( tx_err_drop ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ), //1'b0 ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_dsn ( cfg_dsn ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Management (MGMT) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Advanced Error Reporting (AER) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph )
);
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module or_32(
input [31:0] a, //input values
input [31:0] b,
output [31:0] out //output value
);
//output is the OR of a and b
assign out[0] = a[0] | b[0];
assign out[1] = a[1] | b[1];
assign out[2] = a[2] | b[2];
assign out[3] = a[3] | b[3];
assign out[4] = a[4] | b[4];
assign out[5] = a[5] | b[5];
assign out[6] = a[6] | b[6];
assign out[7] = a[7] | b[7];
assign out[8] = a[8] | b[8];
assign out[9] = a[9] | b[9];
assign out[10] = a[10] | b[10];
assign out[11] = a[11] | b[11];
assign out[12] = a[12] | b[12];
assign out[13] = a[13] | b[13];
assign out[14] = a[14] | b[14];
assign out[15] = a[15] | b[15];
assign out[16] = a[16] | b[16];
assign out[17] = a[17] | b[17];
assign out[18] = a[18] | b[18];
assign out[19] = a[19] | b[19];
assign out[20] = a[20] | b[20];
assign out[21] = a[21] | b[21];
assign out[22] = a[22] | b[22];
assign out[23] = a[23] | b[23];
assign out[24] = a[24] | b[24];
assign out[25] = a[25] | b[25];
assign out[26] = a[26] | b[26];
assign out[27] = a[27] | b[27];
assign out[28] = a[28] | b[28];
assign out[29] = a[29] | b[29];
assign out[30] = a[30] | b[30];
assign out[31] = a[31] | b[31];
endmodule
|
`timescale 1ns / 1ps
`define READ 2'b01
`define WRITE 2'b10
`define DO_NOTHING 2'b00
`define INVALID 2'b11
`define DATA_VALID 1'b1
`define DATA_INVALID 1'b0
`define FIFO_FULL 1'b1
`define FIFO_NOT_FULL 1'b0
`define FIFO_EMPTY 1'b1
`define FIFO_NOT_EMPTY 1'b0
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:56 03/25/2015
// Design Name:
// Module Name: fifo_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_top(
data_out, empty_flag, full_flag,
vector_in, reset,
clk
);
parameter DATA_WIDTH = 4;
parameter NUM_ENTRIES = 8;
parameter OPCODE_WIDTH = 2;
parameter LINE_WIDTH = DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
parameter INITIAL_VALUE = 'b0;
parameter NUM_ENTRIES_BIT = `LOG2(NUM_ENTRIES);
output reg [DATA_WIDTH-1:0]data_out;
output reg empty_flag;
output reg full_flag;
input [OPCODE_WIDTH+DATA_WIDTH-1:0]vector_in;
input reset;
input clk;
reg [DATA_WIDTH-1:0]fifo_data[NUM_ENTRIES-1:0];
reg [NUM_ENTRIES-1:0]fifo_valid_invalid_bit;
reg [OPCODE_WIDTH-1:0]control_in; // control bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]data_in; // data bits for the module obtained from the input vector
reg [NUM_ENTRIES_BIT-1:0]fifo_head_pos;
reg [NUM_ENTRIES_BIT-1:0]fifo_tail_pos;
reg [NUM_ENTRIES_BIT-1:0]loop_variable;
always@(posedge clk)
begin
if(reset)
begin
data_out = INITIAL_VALUE;
fifo_head_pos = INITIAL_VALUE;
fifo_tail_pos = INITIAL_VALUE;
loop_variable = INITIAL_VALUE;
control_in = INITIAL_VALUE;
data_in = INITIAL_VALUE;
fifo_valid_invalid_bit = INITIAL_VALUE;
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// if the tail and head are at the same location
if(fifo_tail_pos == fifo_head_pos)begin
// check if the data contained in that location is VALID/INVALID
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_INVALID && fifo_valid_invalid_bit[fifo_head_pos] == `DATA_INVALID)
begin
// if INVALID, fifo empty
// $display("INVALID, EMPTY");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// else, fifo full
// $display("VALID, FULL");
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_FULL;
end
end else
begin
// $display("DIFFERENT LOCATIONS");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end
// $display("fifo_head_pos:%d, fifo_tail_pos:%d, empty_flag:%d, full_flag:%d", fifo_head_pos, fifo_tail_pos, empty_flag,full_flag);
control_in = vector_in[LINE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH];
data_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-DATA_WIDTH];
// $display("control: %d,data_in: %d",control_in, data_in);
case(control_in)
`READ:
begin
// $display("FIFO READ");
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_VALID)
begin
data_out = fifo_data[fifo_tail_pos];
fifo_valid_invalid_bit[fifo_tail_pos] = `DATA_INVALID;
fifo_tail_pos = fifo_tail_pos + 1'b1;
end else
begin
data_out = 'bx;
end
end
`WRITE:
begin
// $display("FIFO WRITE");
if(empty_flag == `FIFO_EMPTY && full_flag == `FIFO_NOT_FULL)
begin
fifo_data[fifo_head_pos] = data_in;
fifo_valid_invalid_bit[fifo_head_pos] = `DATA_VALID;
if(fifo_head_pos == NUM_ENTRIES-1)
fifo_head_pos = 0;
else
fifo_head_pos = fifo_head_pos + 1'b1;
end
// else
// $display("CACHE FULL, empty_flag:%d, full_flag:%d",empty_flag,full_flag);
end
// `INVALID: $display("INVLAID");
// `DO_NOTHING:
// begin
// repeat(NUM_ENTRIES)
// begin
// $display("loop_variable:%d, fifo_valid_invalid_bit:%d, fifo_data:%d", loop_variable, fifo_valid_invalid_bit[loop_variable], fifo_data[loop_variable]);
// loop_variable = loop_variable + 1'b1;
// end
// end
default: data_out = 'bx;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
|
// bfloat16
// TODO: Write tests and fix obvious bugs first.
module FP16BAddSubS0Of5(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
input arg_2,
output [15:0] ret_0,
output [15:0] ret_1,
output ret_2,
output ret_3);
wire [15:0] x;
wire [15:0] y;
wire is_sub;
wire ys;
wire yys;
wire [15:0] yy;
wire diff_sign;
wire [7:0] xe;
wire [7:0] ye;
wire swap;
wire neg_lhs;
wire neg_rhs;
wire [15:0] lhs;
wire [15:0] rhs;
assign x = arg_0;
assign y = arg_1;
assign is_sub = arg_2;
assign ys = y[15];
assign yys = is_sub ? ~ys : ys;
assign yy = {yys, y[14:0]};
assign xe = x[14:7];
assign ye = y[14:7];
assign diff_sign = x[15] ^ yy[15];
assign swap = xe < ye;
assign lhs = swap ? yy : x;
assign rhs = swap ? x : yy;
assign neg_lhs = diff_sign ? lhs[15] : 0;
assign neg_rhs = diff_sign ? rhs[15] : 0;
assign ret_0 = lhs;
assign ret_1 = rhs;
assign ret_2 = neg_lhs;
assign ret_3 = neg_rhs;
endmodule // FP16BAddSubS0Of5
module FP16BAddSubS1Of5(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
input arg_2,
input arg_3,
output ret_0,
output ret_1,
output [14:0] ret_2,
output [14:0] ret_3,
output [7:0] ret_4,
output ret_5,
output ret_6);
wire [15:0] x;
wire [15:0] y;
wire xn;
wire yn;
wire [7:0] xe;
wire [7:0] ye;
wire x1;
wire y1;
wire [6:0] xf;
wire [6:0] yf;
wire [14:0] xr;
wire [14:0] xrn;
wire [14:0] yr10;
wire [8:0] d;
wire [14:0] yr1;
wire [14:0] yr2;
wire [14:0] yr4;
wire [14:0] yr8;
wire [14:0] yrn;
assign x = arg_0;
assign y = arg_1;
assign xn = arg_2;
assign yn = arg_3;
assign xe = x[14:7];
assign ye = y[14:7];
assign xf = x[6:0];
assign yf = y[6:0];
assign x1 = xe > 0;
assign y1 = ye > 0;
assign xr = {x1, xf, 7'b0};
assign xrn = xn ? ~xr : xr;
assign yr10 = {y1, yf, 7'b0};
assign d = xe - ye;
// barrel shifter to adjust y.
assign yr1 = d[0:0] ? {1'b0, yr10[14:1]} : yr10;
assign yr2 = d[1:1] ? {2'b0, yr1[14:2]} : yr1;
assign yr4 = d[2:2] ? {4'b0, yr2[14:4]} : yr2;
assign yr8 = d[3:3] ? {8'b0, yr4[14:8]} : yr4;
assign yrn = yn ? ~yr8 : yr8;
assign ret_0 = x[15];
assign ret_1 = y[15];
assign ret_2 = xrn;
assign ret_3 = yrn;
assign ret_4 = xe;
assign ret_5 = xn;
assign ret_6 = yn;
endmodule // FP16BAddSubS1Of5
module FP16BAddSubS2Of5(
input clk,
input rst,
input arg_0,
input arg_1,
input [14:0] arg_2,
input [14:0] arg_3,
input [7:0] arg_4,
input arg_5,
input arg_6,
output [15:0] ret_0,
output ret_1,
output ret_2,
output [7:0] ret_3,
output ret_4,
output ret_5);
wire xn;
wire yn;
wire [15:0] rxy;
wire diff_sign;
wire [15:0] r_final;
assign xn = arg_5;
assign yn = arg_6;
assign diff_sign = (xn != yn);
assign rxy = arg_2 + arg_3;
assign r_final = diff_sign ? (rxy + 1) : rxy;
assign ret_0 = r_final;
assign ret_1 = arg_0;
assign ret_2 = arg_1;
assign ret_3 = arg_4;
assign ret_4 = arg_5;
assign ret_5 = arg_6;
endmodule // FP16BAddSubS2Of5
module FP16BAddSubS3Of5(
input clk,
input rst,
input [15:0] arg_0,
input arg_1,
input arg_2,
input [7:0] arg_3,
input arg_4,
input arg_5,
output [14:0] ret_0,
output ret_1,
output ret_2,
output [7:0] ret_3,
output ret_4,
output ret_5,
output ret_6);
wire [15:0] r;
wire xs;
wire ys;
wire [7:0] e;
wire xn;
wire yn;
wire diff_sign;
wire with_carry;
wire neg;
wire [14:0] neg_r;
wire [14:0] half_r;
wire [14:0] r_diff;
wire [14:0] r_same;
wire [14:0] r_final;
wire [7:0] eplus;
wire [7:0] e_final;
assign r = arg_0;
assign xs = arg_1;
assign ys = arg_2;
assign e = arg_3;
assign xn = arg_4;
assign yn = arg_5;
assign diff_sign = (xn != yn);
assign with_carry = r[15:15];
assign neg_r = (~r) + 1;
assign half_r = r[15:1];
assign neg = diff_sign & !with_carry;
assign eplus = e + 1;
assign r_diff = with_carry ? r[14:0] : neg_r;
assign r_same = with_carry ? half_r : r[14:0];
assign r_final = diff_sign ? r_diff : r_same;
assign e_final = (!diff_sign && with_carry) ? eplus : e;
assign ret_0 = r_final;
assign ret_1 = xs;
assign ret_2 = ys;
assign ret_3 = e_final;
assign ret_4 = neg;
assign ret_5 = xn;
assign ret_6 = yn;
endmodule // FP16BAddSubS3Of5
module FP16BAddSubS4Of5(
input clk,
input rst,
input [14:0] arg_0,
input arg_1,
input arg_2,
input [7:0] arg_3,
input arg_4,
input arg_5,
input arg_6,
output [15:0] ret_0);
wire [15:0] r;
wire xs;
wire ys;
wire [7:0] e;
wire [7:0] e_final;
wire [8:0] e_l0adjust;
wire underflow;
wire [7:0] e_adjust;
wire neg;
wire xn;
wire yn;
wire [7:0] rr;
wire [6:0] r_final;
wire [15:0] r8;
wire [15:0] r4;
wire [15:0] r2;
wire [15:0] r1;
wire [3:0] l0count;
wire s;
assign r = arg_0;
assign xs = arg_1;
assign ys = arg_2;
assign e = arg_3;
assign neg = arg_4;
assign xn = arg_5;
assign yn = arg_6;
assign s = (xn == yn) ? xs : (yn ? (neg ^ xs): (neg ^ ys));
assign r8 = (r[14:7] == 0) ? {r[6:0], 8'b0} : r;
assign r4 = (r8[14:11] == 0) ? {r8[10:0], 4'b0} : r8;
assign r2 = (r4[14:13] == 0) ? {r4[12:0], 2'b0} : r4;
assign r1 = (r2[14:14] == 0) ? {r2[13:0], 1'b0} : r2;
assign l0count = {r[14:7] == 0, r8[14:11] == 0, r4[14:13] == 0, r2[14:14] == 0};
assign rr = (xn == yn) ? r[14:7] : r1;
assign e_l0adjust = e - l0count;
assign underflow = e_l0adjust[8:8];
assign e_adjust = underflow ? 0 : e_l0adjust[7:0];
assign e_final = (xn == yn) ? e : e_adjust[7:0];
assign r_final = underflow ? 0 : rr[6:0];
assign ret_0 = {s, e_final, r_final};
endmodule // FP16BAddSubS4Of5
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// UART ser/des framer for use in RCN bus IP. Hard coded for 115200,1,1.
//
module rcn_uart_framer
(
input clk_50,
input rst,
output reg tx_busy,
input tx_vld,
input [7:0] tx_data,
output rx_vld,
output [7:0] rx_data,
output reg rx_frame_error,
output uart_tx,
input uart_rx
);
parameter SAMPLE_CLK_DIV = 6'd62; // Value for 115200 @ 50 MHz in
//
// 50 MHz -> sample clock (7 * bit)
//
reg [5:0] sample_cnt;
reg sample_en;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b0;
end
else if (sample_cnt == SAMPLE_CLK_DIV)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b1;
end
else
begin
sample_cnt <= sample_cnt + 6'd1;
sample_en <= 1'b0;
end
//
// Rx data sample state machine
//
reg [6:0] rx_sample;
reg [2:0] rx_bitclk_cnt;
reg rx_bitclk_en;
reg [3:0] rx_bit_cnt;
reg rx_busy;
wire rx_falling_clean = (rx_sample[6:0] == 7'b1110000);
wire rx_falling_dirty = (rx_sample[6:4] == 3'b110) && (rx_sample[1:0] == 2'b00);
wire rx_falling = rx_falling_clean || rx_falling_dirty;
wire rx_high = (rx_sample[2:1] == 2'b11);
wire rx_low = (rx_sample[2:1] == 2'b00);
always @ (posedge clk_50 or posedge rst)
if (rst)
rx_sample <= 7'd0;
else if (sample_en)
rx_sample <= {rx_sample[5:0], uart_rx};
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= 1'b0;
end
else if (sample_en)
begin
if (!rx_busy)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= (rx_falling) ? 1'b1 : 1'b0;
end
else
begin
rx_busy <= (rx_bit_cnt == 4'd9) ? 1'b0 : 1'b1;
rx_bitclk_en <= (rx_bitclk_cnt == 3'd5) ? 1'b1 : 1'b0;
if (rx_bitclk_cnt == 3'd6)
begin
rx_bitclk_cnt <= 3'd0;
rx_bit_cnt <= rx_bit_cnt + 4'd1;
end
else
begin
rx_bitclk_cnt <= rx_bitclk_cnt + 3'd1;
end
end
end
//
// Rx bit capture and signalling
//
reg [8:0] rx_capture;
reg [8:0] rx_signal_errors;
reg rx_data_done;
reg rx_busy_d1;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_capture <= 9'd0;
rx_signal_errors <= 9'd0;
end
else if (sample_en && rx_bitclk_en)
begin
rx_capture <= {rx_high && !rx_low, rx_capture[8:1]};
rx_signal_errors <= {!rx_high && !rx_low, rx_signal_errors[8:1]};
end
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_data_done <= 1'b0;
rx_busy_d1 <= 1'b0;
end
else
begin
rx_data_done <= rx_busy_d1 && !rx_busy;
rx_busy_d1 <= rx_busy;
end
assign rx_vld = rx_data_done;
assign rx_data = rx_capture[7:0];
always @ (posedge clk_50)
rx_frame_error <= (rx_signal_errors != 9'd0) || !rx_capture[8];
//
// Tx state machine
//
reg [8:0] tx_shift;
reg [2:0] tx_bitclk_cnt;
reg [3:0] tx_cnt;
assign uart_tx = tx_shift[0];
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
tx_shift <= {9{1'b1}};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b0;
end
else if (!tx_busy && tx_vld)
begin
tx_shift <= {tx_data, 1'b0};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b1;
end
else if (sample_en)
begin
tx_busy <= (tx_cnt == 4'd12) ? 1'b0 : 1'b1;
if (tx_bitclk_cnt == 3'd6)
begin
tx_bitclk_cnt <= 3'd0;
tx_shift <= {1'b1, tx_shift[8:1]};
tx_cnt <= tx_cnt + 4'd1;
end
else
begin
tx_bitclk_cnt <= tx_bitclk_cnt + 3'd1;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dcfifo_32in_32out_16kb_rd_cnt (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [31 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [31 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [1 : 0] rd_data_count;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("artix7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(509),
.C_PROG_FULL_THRESH_NEGATE_VAL(508),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(2),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(9'B0),
.prog_empty_thresh_assert(9'B0),
.prog_empty_thresh_negate(9'B0),
.prog_full_thresh(9'B0),
.prog_full_thresh_assert(9'B0),
.prog_full_thresh_negate(9'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(rd_data_count),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcadc5_spi (
spi_csn_0,
spi_csn_1,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dirn);
// 4 wire
input spi_csn_0;
input spi_csn_1;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dirn;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = spi_csn_0 & spi_csn_1;
assign spi_dirn = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64a_testpattern
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE6E22 , EP4CE10E22
// Cyclone 10 LP: 10CL006YE144, 10CL010YE144
// Tool versions: Altera Quartus Prime
// Description:
//
// Dependencies: vh/n64a_params.vh
//
// Features: testpattern
//
//////////////////////////////////////////////////////////////////////////////////
module n64a_testpattern(
VCLK,
nDSYNC,
nRST,
vmode,
Sync_in,
vdata_out
);
`include "vh/n64a_params.vh"
input VCLK;
input nDSYNC;
input nRST;
input vmode;
input [3:0] Sync_in;
output [`VDATA_O_FU_SLICE] vdata_out;
wire posedge_nVSYNC = !vdata_out[3*color_width_o+3] & Sync_in[3];
wire posedge_nHSYNC = !vdata_out[3*color_width_o+1] & Sync_in[1];
wire posedge_nCSYNC = !vdata_out[3*color_width_o ] & Sync_in[0];
reg [8:0] vcnt = 9'b0;
reg [9:0] hcnt = 10'b0;
wire [8:0] pattern_vstart = vmode ? `TESTPAT_VSTART_PAL : `TESTPAT_VSTART_NTSC;
wire [8:0] pattern_vstop = vmode ? `TESTPAT_VSTOP_PAL : `TESTPAT_VSTOP_NTSC;
reg [4:0] vdata_checkboard_fine = 5'd0;
always @(posedge VCLK) begin
if (!nDSYNC) begin
if (posedge_nHSYNC) begin
hcnt <= 10'b0;
vcnt <= &vcnt ? vcnt : vcnt + 1'b1;
end else begin
hcnt <= &hcnt ? hcnt : hcnt + 1'b1;
end
if (posedge_nVSYNC)
vcnt <= 9'b0;
if ((vcnt > pattern_vstart) && (vcnt < pattern_vstop)) begin
if ((hcnt > `TESTPAT_HSTART) && (hcnt < `TESTPAT_HSTOP))
vdata_checkboard_fine[0] <= ~vdata_checkboard_fine[0];
else
vdata_checkboard_fine[0] <= 1'b0;
if (hcnt == `TESTPAT_HSTART)
vdata_checkboard_fine[0] <= vcnt[0];
end else begin
vdata_checkboard_fine[0] <= 1'b0;
end
vdata_checkboard_fine[4:1] <= Sync_in;
end
if (!nRST) begin
vdata_checkboard_fine <= 5'd0;
vcnt <= 9'b0;
hcnt <= 10'b0;
end
end
assign vdata_out = {vdata_checkboard_fine[4:1],{3*color_width_o{vdata_checkboard_fine[0]}}};
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
module pixel_map(input clk,
input signed[67:0] p1_inv,
input signed[68:0] p2_inv,
input signed[78:0] p3_inv,
input signed[67:0] p4_inv,
input signed[68:0] p5_inv,
input signed[78:0] p6_inv,
input signed[58:0] p7_inv,
input signed[59:0] p8_inv,
input signed[70:0] p9_inv,
input signed[78:0] dec_numx_horiz,
input signed[78:0] dec_numy_horiz,
input signed[70:0] dec_denom_horiz,
input[11:0] pixel_in,
output reg[11:0] pixel_out,
output[16:0] ntsc_out_addr,
output reg vga_in_wr,
output[16:0] vga_in_addr);
// instantiate an address mapper (for the vga_in)
addr_map addr_map_vga(.hcount(cur_x),
.vcount(cur_y),
.addr(vga_in_addr));
always @(posedge clk) begin
vga_in_wr <= 1;
if ((cur_x == 639) && (cur_y == 479)) begin
cur_x <= 0;
cur_y <= 0;
end
else if ((cur_x == 639) && (cur_y != 479)) begin
cur_x <= 0;
cur_y <= cur_y + 1;
end
else if (cur_x != 639) begin
cur_x <= cur_x + 1;
cur_y <= cur_y;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_4_V
`define SKY130_FD_SC_LS__A2111OI_4_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_4_V
|
// File: ./ex-target/DotProduct.v
// Generated by MyHDL 1.0dev
// Date: Tue Oct 6 16:32:07 2015
`timescale 1ns/10ps
module DotProduct (
y,
y_da_vec,
y_db_vec,
a_vec,
b_vec
);
// Vector dot product and derivative model using fixbv type.
//
// :param y: return dot(a_vec, b_vec) as fixbv
// :param y_da_vec: return d/da dot(a_vec, b_vec) as vector of fixbv
// :param y_db_vec: return d/db dot(a_vec, b_vec) as vector of fixbv
// :param a_vec: vector of fixbv
// :param b_vec: vector of fixbv
// :param dim: vector dimensionality
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output [47:0] y_da_vec;
wire [47:0] y_da_vec;
output [47:0] y_db_vec;
wire [47:0] y_db_vec;
output [47:0] a_vec;
wire [47:0] a_vec;
output [47:0] b_vec;
wire [47:0] b_vec;
wire signed [15:0] a_list [0:3-1];
wire signed [15:0] b_list [0:3-1];
assign b_vec[48-1:32] = None;
assign b_vec[32-1:16] = None;
assign b_vec[16-1:0] = None;
assign a_vec[48-1:32] = None;
assign a_vec[32-1:16] = None;
assign a_vec[16-1:0] = None;
always @(a_list[0], a_list[1], a_list[2], b_list[0], b_list[1], b_list[2]) begin: DOTPRODUCT_DOT
reg signed [32-1:0] y_sum;
integer j;
y_sum = fixbv(0.0);
for (j=0; j<3; j=j+1) begin
y_sum = (y_sum + (a_list[j] * b_list[j]));
end
y = fixbv(y_sum);
end
assign y_da_vec = b_vec;
assign y_db_vec = a_vec;
endmodule
|
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