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//-----------------------------------------------------------------------------
// File : alu.v
// Creation date : 18.04.2017
// Creation time : 14:44:52
// Description :
// Created by : TermosPullo
// Tool : Kactus2 3.4.79 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:core:alu:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/core/alu/1.0/alu.1.0.xml
//-----------------------------------------------------------------------------
module alu #(
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter ALU_OP_WIDTH = 3 // Bits reserved for identification of alu operation
) (
// Interface: cpu_system
input [ALU_OP_WIDTH-1:0] alu_op_i,
input [DATA_WIDTH-1:0] register_value_i1,
input [DATA_WIDTH-1:0] register_value_i2,
output reg [DATA_WIDTH-1:0] alu_result_o,
output reg [DATA_WIDTH-1:0] alu_status_o
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The available operations.
parameter [ALU_OP_WIDTH-1:0]
OP_PLUS = 3'b000,
OP_MINUS = 3'b001,
OP_MUL = 3'b010,
OP_DIV = 3'b011,
OP_CMP = 3'b100;
// The available status bits.
parameter [1:0]
C_OUT = 2'd3,
NEGATIVE = 2'd2,
ZERO = 2'd1,
DIV_ZERO = 2'd0;
// Result of the operation.
reg [DATA_WIDTH*2-1:0] operation_result;
// 1 = Division with zero attempted.
integer div_zero;
always @* begin
// By default, it did not happen.
div_zero = 0;
// Select a case depending on operation. Most are pretty straightforward execution.
case(alu_op_i)
OP_PLUS: operation_result <= register_value_i1 + register_value_i2;
OP_MINUS: operation_result <= register_value_i1 - register_value_i2;
OP_MUL: operation_result <= register_value_i1 * register_value_i2;
OP_DIV: begin
if (register_value_i2 == 0) begin
// Tried division by zero. Also result is then zero.
operation_result <= 0;
div_zero = 1;
end
else begin
operation_result <= register_value_i1 / register_value_i2;
end
end
OP_CMP : operation_result <= register_value_i1 != register_value_i2;
default: begin
// Unsupported opcode -> Result is zero.
$display("ERROR: Unknown ALU operation: %d", alu_op_i);
operation_result <= 0;
end
endcase
// Output the result.
alu_result_o <= operation_result[DATA_WIDTH-1:0];
// Undefined status bits are always zero.
alu_status_o[DATA_WIDTH-1:C_OUT+1] = 0;
// Carry out is always the least significant overflow bit.
alu_status_o[C_OUT] = operation_result[DATA_WIDTH];
// If applicable, the most significant output bit is the sign.
alu_status_o[NEGATIVE] = operation_result[DATA_WIDTH-1];
// Zero bit should be obvious.
alu_status_o[ZERO] = (operation_result == 0);
// Division by zero is was resolved earlier.
alu_status_o[DIV_ZERO] = div_zero;
end
endmodule
|
////////////////////////////////////////////////////////////////
// File: yuv422_to_yuv444.v
// Author: Tersaic, modified by B. Brown
// Source: YUV422_to_444.v
// About: Removed VGA dependency. Minor syntax changes.
////////////////////////////////////////////////////////////////
module yuv422_to_yuv444
(
input wire iCLK,
input wire iRST_N,
input wire [15:0] iYCbCr,
input wire iYCbCr_valid,
output wire [7:0] oY,
output wire [7:0] oCb,
output wire [7:0] oCr,
output wire oYCbCr_valid
);
// Internal Registers
reg every_other;
reg [7:0] mY;
reg [7:0] mCb;
reg [7:0] mCr;
reg mValid;
assign oY = mY;
assign oCb = mCb;
assign oCr = mCr;
assign oYCbCr_valid = mValid;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
every_other <= 0;
mY <= 0;
mCb <= 0;
mCr <= 0;
mValid <= 0;
end
else
begin
every_other <= ~every_other;
mValid <= iYCbCr_valid;
if(every_other)
{mY,mCr} <= iYCbCr;
else
{mY,mCb} <= iYCbCr;
end
end
endmodule
|
//************************************
// Designed by: Xiaoyu Sun
// Last updated: 15/11/9
//************************************
module reducer(clk, rst, write_in, pair_in, result);
parameter data_size = 32;
parameter word_length = 128;
parameter word_num = 64;
// FSM parameters
parameter START = 4'b0000;
parameter IDLE = 4'b0001;
parameter COMBINE = 4'b0010;
input clk;
input rst;
input write_in; // When write_in==1 COMBINE, when write_in==0 IDLE
input [data_size-1:0] pair_in; // The incoming pairs
output reg [31:0] result;
// Only support 1 key
reg [3:0] count;
reg count_flag;
reg count_flag_1;
always@(posedge clk or negedge rst)
if(!rst) begin
count_flag <= 0;
end
else
count_flag <= write_in;
always@(posedge clk or negedge rst)
if(!rst) begin
count_flag_1 <= 0;
end
else if(write_in && ~count_flag)
count_flag_1 <= 1;
else
count_flag_1 <= 0;
always@(posedge clk or negedge rst)
if(!rst)
count <= 0;
else if(count_flag_1)
count <= count + 1;
reg [word_length-1:0] mem_word [word_num-1:0]; // The internal mem to store the combined words
reg [word_length-1:0] key_lut [3:0];
reg [5:0] row_pt; // Needs to point from 0 to 63
//
reg [5:0] row_pt_pre;
//
reg [7:0] col_pt; // Needs to point from 0 to 127 and some margin
reg [7:0] pt; //result pointer
reg [2:0] lut_pt; //Index LUT
reg [6:0] i; // Index the mem_word
reg [3:0] current_state;
reg [3:0] next_state;
// Delay row_pt
always@(posedge clk or negedge rst)
if(!rst)
row_pt_pre <= 6'b0;
else
row_pt_pre <= row_pt;
wire row_change;
assign row_change = (row_pt != row_pt_pre);
always@(posedge clk)
if(!rst)
current_state <= START;
else
current_state <= next_state;
always@*
begin
case(current_state)
START: begin
if(write_in == 1) next_state = COMBINE;
else next_state = START;
end
IDLE: begin
if(write_in == 1) next_state = COMBINE;
else next_state = IDLE;
end
COMBINE: begin
if(write_in == 0) next_state = IDLE;
else next_state = COMBINE;
end
default: begin
next_state = START;
end
endcase
end
always@(posedge clk)
case(current_state)
START: begin
row_pt <= 0;
col_pt <= 0;
for(i=0; i<=63; i=i+1)
mem_word[i] <= 128'b0;
end
IDLE: begin
end
COMBINE: begin
if (col_pt == 128) begin
row_pt <= row_pt + 1;
col_pt <= 0;
end
else if(write_in == 1) begin
mem_word[row_pt] <= mem_word[row_pt] + (pair_in<<col_pt);
col_pt <= col_pt + 32;
end
end
endcase
always@(posedge clk)
if (!rst)
begin
lut_pt <= 0;
pt<= 0;
result <= 32'b0;
key_lut[0] <= 128'b0;
key_lut[1] <= 128'b0;
key_lut[2] <= 128'b0;
key_lut[3] <= 128'b0;
end
else if ((mem_word[row_pt-1]!=key_lut[0]) && (mem_word[row_pt-1]!=key_lut[1]) && (mem_word[row_pt-1]!=key_lut[2]) && (mem_word[row_pt-1]!=key_lut[3]) && (col_pt==0)&&(row_change==1))
begin
result <= result + (8'b00000001 << pt);
key_lut[lut_pt] <= mem_word[row_pt-1];
lut_pt <= lut_pt +1;
pt <= pt+8;
end
else if ((mem_word[row_pt-1]==key_lut[0]) && (key_lut[0]!=0)&& (col_pt==0)&&(row_change==1))
begin
result[7:0] <= result[7:0] + 1;
end
else if ((mem_word[row_pt-1]==key_lut[1]) && (key_lut[1]!=0)&& (col_pt==0)&&(row_change==1))
begin
result[15:8] <= result[15:8] + 1;
end
else if ((mem_word[row_pt-1]==key_lut[2]) && (key_lut[2]!=0)&& (col_pt==0)&&(row_change==1))
begin
result[23:16] <= result[23:16] + 1;
end
else if ((mem_word[row_pt-1]==key_lut[3]) && (key_lut[3]!=0)&& (col_pt==0)&&(row_change==1))
begin
result[31:24] <= result[31:24] + 1;
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Encoder_Peripheral_Hardware_Specification.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Encoder_Peripheral_Hardware_Specification
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Encoder_Peripheral_Hardware_Specification
(
CLK_IN,
reset,
enb,
a,
b,
index,
valid,
count
);
input CLK_IN;
input reset;
input enb;
input a;
input b;
input index;
output valid;
output [15:0] count; // uint16
wire y;
wire Latch_Index_Pulse_out1;
wire Select_AB_Inputs_out1;
wire y_1;
wire y_2;
wire Select_AB_out1;
wire Select_AB_out2;
wire Detect_Change_To_One_out1;
wire signed [15:0] Counter_Max_out1; // int16
wire signed [15:0] Update_Count_From_AB_out1; // int16
wire [15:0] Data_Type_Conversion_out1; // uint16
// <S1>/Debounce_Index
Debounce_Index u_Debounce_Index (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(index),
.Out(y)
);
// <S1>/Latch_Index_Pulse
Latch_Index_Pulse u_Latch_Index_Pulse (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In1(y),
.Out1(Latch_Index_Pulse_out1)
);
assign valid = Latch_Index_Pulse_out1;
// <S1>/Select_AB_Inputs
assign Select_AB_Inputs_out1 = 1'b0;
// <S1>/Debounce_A
Debounce_A u_Debounce_A (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(a),
.Out(y_1)
);
// <S1>/Debounce_B
Debounce_B u_Debounce_B (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In(b),
.Out(y_2)
);
// <S1>/Select AB
Select_AB u_Select_AB (.in_select(Select_AB_Inputs_out1),
.in1(y_1),
.in2(y_2),
.A(Select_AB_out1),
.B(Select_AB_out2)
);
// <S1>/Detect Change To One
Detect_Change_To_One u_Detect_Change_To_One (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.In1(y),
.Out1(Detect_Change_To_One_out1)
);
// <S1>/Counter_Max
assign Counter_Max_out1 = 16'sd4999;
// <S1>/Update_Count_From_AB
Update_Count_From_AB u_Update_Count_From_AB (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.A(Select_AB_out1),
.B(Select_AB_out2),
.index(Detect_Change_To_One_out1),
.count_max(Counter_Max_out1), // int16
.count(Update_Count_From_AB_out1) // int16
);
// <S1>/Data Type Conversion
assign Data_Type_Conversion_out1 = Update_Count_From_AB_out1;
assign count = Data_Type_Conversion_out1;
endmodule // Encoder_Peripheral_Hardware_Specification
|
//======================================================================
//
// tb_blake2_G.v
// -------------
// Testbench for the Blake2 G function.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_blake2_G();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg [63 : 0] tb_a;
reg [63 : 0] tb_b;
reg [63 : 0] tb_c;
reg [63 : 0] tb_d;
reg [63 : 0] tb_m0;
reg [63 : 0] tb_m1;
wire [63 : 0] tb_a_prim;
wire [63 : 0] tb_b_prim;
wire [63 : 0] tb_c_prim;
wire [63 : 0] tb_d_prim;
reg display_cycle_ctr;
//----------------------------------------------------------------
// blake2_G device under test.
//----------------------------------------------------------------
blake2_G DUT(
.a(tb_a),
.b(tb_b),
.c(tb_c),
.d(tb_d),
.m0(tb_m0),
.m1(tb_m1),
.a_prim(tb_a_prim),
.b_prim(tb_b_prim),
.c_prim(tb_c_prim),
.d_prim(tb_d_prim)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases completes, %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_a = 64'h0;
tb_b = 64'h0;
tb_c = 64'h0;
tb_d = 64'h0;
tb_m0 = 64'h0;
tb_m1 = 64'h0;
end
endtask // init_dut
//----------------------------------------------------------------
//----------------------------------------------------------------
task testrunner (input [63 : 0] a, input [63 : 0] b,
input [63 : 0] c, input [63 : 0] d,
input [63 : 0] m0, input [63 : 0] m1,
input [63 : 0] prim_a, input [63 : 0] prim_b,
input [63 : 0] prim_c, input [63 : 0] prim_d);
begin : testrun
integer tc_error;
tc_error = 0;
tb_a = a;
tb_b = b;
tb_c = c;
tb_d = d;
tb_m0 = m0;
tb_m1 = m1;
#(CLK_PERIOD);
if (tb_a_prim != prim_a)
tc_error = tc_error + 1;
if (tb_b_prim != prim_b)
tc_error = tc_error + 1;
if (tb_c_prim != prim_c)
tc_error = tc_error + 1;
if (tb_d_prim != prim_d)
tc_error = tc_error + 1;
if (tc_error > 0)
begin
error_ctr = error_ctr + 1;
$display("%d Errors in test case found - dumping state:", tc_error);
$display("tb_a_prim: %016x, expected %016x", tb_a_prim, prim_a);
$display("tb_b_prim: %016x, expected %016x", tb_b_prim, prim_b);
$display("tb_c_prim: %016x, expected %016x", tb_c_prim, prim_c);
$display("tb_d_prim: %016x, expected %016x", tb_d_prim, prim_d);
end
end
endtask // testrunner
//----------------------------------------------------------------
//----------------------------------------------------------------
task TC1;
begin : test_case1
tc_ctr = tc_ctr + 1;
$display("Starting TC1");
testrunner(64'h6a09e667f2bdc948, 64'h510e527fade682d1,
64'h6a09e667f3bcc908, 64'h510e527fade68251,
64'h0000000000000000, 64'h0000000000000000,
64'hf0c9aa0de38b1b89, 64'hbbdf863401fde49b,
64'he85eb23c42183d3d, 64'h7111fd8b6445099d);
$display("Stopping TC1");
end
endtask // TC1
//----------------------------------------------------------------
//----------------------------------------------------------------
task TC2;
begin : test_case2
tc_ctr = tc_ctr + 1;
$display("Starting TC2");
testrunner(64'h6a09e667f2bd8948, 64'h510e527fade682d1,
64'h6a09e667f3bcc908, 64'h510e527fade68251,
64'h0706050403020100, 64'h0f0e0d0c0b0a0908,
64'hfce69820f2d7e54c, 64'h51324affb424aa90,
64'h032368569e359a63, 64'h8ad8f2a6176861c7);
$display("Stopping TC2");
end
endtask // TC2
//----------------------------------------------------------------
//----------------------------------------------------------------
task TC3;
begin : test_case3
tc_ctr = tc_ctr + 1;
$display("Starting TC3");
testrunner(64'h107e94c998ced482, 64'h28e4a60d02068f18,
64'h7650e70ef0a7f8cd, 64'h86570b736731f92d,
64'h2f2e2d2c2b2a2928, 64'h1f1e1d1c1b1a1918,
64'hf082ab50dd1499b7, 64'hf66d12f48baec79a,
64'h13e5af4bbe2d9010, 64'hfac6524cdebf33d2);
$display("Stopping TC3");
end
endtask // TC3
//----------------------------------------------------------------
// blake2_core
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : tb_blake2_G_test
$display("*** Testbench for Blake2 G function test started");
init_dut();
TC1();
TC2();
TC3();
display_test_result();
$display("*** Blake2 G functions simulation done.");
$finish;
end // tb_blake2_G_test
endmodule // tb_blake2_G
//======================================================================
// EOF tb_blake2_G.v
//======================================================================
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_channel (
// adc interface
adc_clk,
adc_rst,
adc_enable,
adc_pn_sel,
adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,
adc_dfmt_type,
adc_dfmt_enable,
adc_pn_type,
adc_dcfilt_offset,
adc_dcfilt_coeff,
adc_iqcor_coeff_1,
adc_iqcor_coeff_2,
adc_pn_err,
adc_pn_oos,
adc_or,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// user controls
up_usr_datatype_be,
up_usr_datatype_signed,
up_usr_datatype_shift,
up_usr_datatype_total_bits,
up_usr_datatype_bits,
up_usr_decimation_m,
up_usr_decimation_n,
adc_usr_datatype_be,
adc_usr_datatype_signed,
adc_usr_datatype_shift,
adc_usr_datatype_total_bits,
adc_usr_datatype_bits,
adc_usr_decimation_m,
adc_usr_decimation_n,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_ADC_CHID = 4'h0;
// adc interface
input adc_clk;
input adc_rst;
output adc_enable;
output adc_pn_sel;
output adc_iqcor_enb;
output adc_dcfilt_enb;
output adc_dfmt_se;
output adc_dfmt_type;
output adc_dfmt_enable;
output adc_pn_type;
output [15:0] adc_dcfilt_offset;
output [15:0] adc_dcfilt_coeff;
output [15:0] adc_iqcor_coeff_1;
output [15:0] adc_iqcor_coeff_2;
input adc_pn_err;
input adc_pn_oos;
input adc_or;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// user controls
output up_usr_datatype_be;
output up_usr_datatype_signed;
output [ 7:0] up_usr_datatype_shift;
output [ 7:0] up_usr_datatype_total_bits;
output [ 7:0] up_usr_datatype_bits;
output [15:0] up_usr_decimation_m;
output [15:0] up_usr_decimation_n;
input adc_usr_datatype_be;
input adc_usr_datatype_signed;
input [ 7:0] adc_usr_datatype_shift;
input [ 7:0] adc_usr_datatype_total_bits;
input [ 7:0] adc_usr_datatype_bits;
input [15:0] adc_usr_decimation_m;
input [15:0] adc_usr_decimation_n;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg up_adc_pn_sel = 'd0;
reg up_adc_iqcor_enb = 'd0;
reg up_adc_dcfilt_enb = 'd0;
reg up_adc_dfmt_se = 'd0;
reg up_adc_dfmt_type = 'd0;
reg up_adc_dfmt_enable = 'd0;
reg up_adc_pn_type = 'd0;
reg up_adc_enable = 'd0;
reg [15:0] up_adc_dcfilt_offset = 'd0;
reg [15:0] up_adc_dcfilt_coeff = 'd0;
reg [15:0] up_adc_iqcor_coeff_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_2 = 'd0;
reg up_usr_datatype_be = 'd0;
reg up_usr_datatype_signed = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0;
reg [ 7:0] up_usr_datatype_total_bits = 'd0;
reg [ 7:0] up_usr_datatype_bits = 'd0;
reg [15:0] up_usr_decimation_m = 'd0;
reg [15:0] up_usr_decimation_n = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_xfer_toggle = 'd0;
reg adc_up_xfer_toggle_m1 = 'd0;
reg adc_up_xfer_toggle_m2 = 'd0;
reg adc_up_xfer_toggle_m3 = 'd0;
reg adc_enable_m1 = 'd0;
reg adc_enable_m2 = 'd0;
reg adc_enable_m3 = 'd0;
reg adc_enable = 'd0;
reg adc_pn_sel = 'd0;
reg adc_iqcor_enb = 'd0;
reg adc_dcfilt_enb = 'd0;
reg adc_dfmt_se = 'd0;
reg adc_dfmt_type = 'd0;
reg adc_dfmt_enable = 'd0;
reg adc_pn_type = 'd0;
reg [15:0] adc_dcfilt_offset = 'd0;
reg [15:0] adc_dcfilt_coeff = 'd0;
reg [15:0] adc_iqcor_coeff_1 = 'd0;
reg [15:0] adc_iqcor_coeff_2 = 'd0;
reg [ 5:0] adc_xfer_cnt = 'd0;
reg adc_xfer_toggle = 'd0;
reg adc_xfer_pn_err = 'd0;
reg adc_xfer_pn_oos = 'd0;
reg adc_xfer_or = 'd0;
reg adc_acc_pn_err = 'd0;
reg adc_acc_pn_oos = 'd0;
reg adc_acc_or = 'd0;
reg up_adc_xfer_toggle_m1 = 'd0;
reg up_adc_xfer_toggle_m2 = 'd0;
reg up_adc_xfer_toggle_m3 = 'd0;
reg up_adc_xfer_pn_err = 'd0;
reg up_adc_xfer_pn_oos = 'd0;
reg up_adc_xfer_or = 'd0;
reg up_adc_pn_err = 'd0;
reg up_adc_pn_oos = 'd0;
reg up_adc_or = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire adc_up_xfer_toggle_s;
wire up_adc_xfer_toggle_s;
// decode block select
assign up_sel_s = ((up_addr[13:8] == 6'h01) && (up_addr[7:4] == PCORE_ADC_CHID)) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_pn_sel <= 'd0;
up_adc_iqcor_enb <= 'd0;
up_adc_dcfilt_enb <= 'd0;
up_adc_dfmt_se <= 'd0;
up_adc_dfmt_type <= 'd0;
up_adc_dfmt_enable <= 'd0;
up_adc_pn_type <= 'd0;
up_adc_enable <= 'd0;
up_adc_dcfilt_offset <= 'd0;
up_adc_dcfilt_coeff <= 'd0;
up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0;
up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0;
up_usr_datatype_total_bits <= 'd0;
up_usr_datatype_bits <= 'd0;
up_usr_decimation_m <= 'd0;
up_usr_decimation_n <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h0)) begin
up_adc_pn_sel <= up_wdata[10];
up_adc_iqcor_enb <= up_wdata[9];
up_adc_dcfilt_enb <= up_wdata[8];
up_adc_dfmt_se <= up_wdata[6];
up_adc_dfmt_type <= up_wdata[5];
up_adc_dfmt_enable <= up_wdata[4];
up_adc_pn_type <= up_wdata[1];
up_adc_enable <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4)) begin
up_adc_dcfilt_offset <= up_wdata[31:16];
up_adc_dcfilt_coeff <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5)) begin
up_adc_iqcor_coeff_1 <= up_wdata[31:16];
up_adc_iqcor_coeff_2 <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25];
up_usr_datatype_signed <= up_wdata[24];
up_usr_datatype_shift <= up_wdata[23:16];
up_usr_datatype_total_bits <= up_wdata[15:8];
up_usr_datatype_bits <= up_wdata[7:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9)) begin
up_usr_decimation_m <= up_wdata[31:16];
up_usr_decimation_n <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
4'h0: up_rdata <= {21'd0, up_adc_pn_sel, up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or};
4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
adc_usr_datatype_shift, adc_usr_datatype_total_bits,
adc_usr_datatype_bits};
4'h9: up_rdata <= {adc_usr_decimation_m, adc_usr_decimation_n};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// common xfer toggle (where no enable or start is available)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_xfer_toggle <= 'd0;
end else begin
if (up_wr_s == 1'b1) begin
up_xfer_toggle <= ~up_xfer_toggle;
end
end
end
// adc control transfer
assign adc_up_xfer_toggle_s = adc_up_xfer_toggle_m3 ^ adc_up_xfer_toggle_m2;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_up_xfer_toggle_m1 <= 'd0;
adc_up_xfer_toggle_m2 <= 'd0;
adc_up_xfer_toggle_m3 <= 'd0;
adc_enable_m1 <= 'd0;
adc_enable_m2 <= 'd0;
adc_enable_m3 <= 'd0;
end else begin
adc_up_xfer_toggle_m1 <= up_xfer_toggle;
adc_up_xfer_toggle_m2 <= adc_up_xfer_toggle_m1;
adc_up_xfer_toggle_m3 <= adc_up_xfer_toggle_m2;
adc_enable_m1 <= up_adc_enable;
adc_enable_m2 <= adc_enable_m1;
adc_enable_m3 <= adc_enable_m2;
end
adc_enable <= adc_enable_m3;
if (adc_up_xfer_toggle_s == 1'b1) begin
adc_pn_sel <= up_adc_pn_sel;
adc_iqcor_enb <= up_adc_iqcor_enb;
adc_dcfilt_enb <= up_adc_dcfilt_enb;
adc_dfmt_se <= up_adc_dfmt_se;
adc_dfmt_type <= up_adc_dfmt_type;
adc_dfmt_enable <= up_adc_dfmt_enable;
adc_pn_type <= up_adc_pn_type;
adc_dcfilt_offset <= up_adc_dcfilt_offset;
adc_dcfilt_coeff <= up_adc_dcfilt_coeff;
adc_iqcor_coeff_1 <= up_adc_iqcor_coeff_1;
adc_iqcor_coeff_2 <= up_adc_iqcor_coeff_2;
end
end
// adc status transfer
always @(posedge adc_clk) begin
adc_xfer_cnt <= adc_xfer_cnt + 1'b1;
if (adc_xfer_cnt == 6'd0) begin
adc_xfer_toggle <= ~adc_xfer_toggle;
adc_xfer_pn_err <= adc_acc_pn_err;
adc_xfer_pn_oos <= adc_acc_pn_oos;
adc_xfer_or <= adc_acc_or;
end
if (adc_xfer_cnt == 6'd0) begin
adc_acc_pn_err <= adc_pn_err;
adc_acc_pn_oos <= adc_pn_oos;
adc_acc_or <= adc_or;
end else begin
adc_acc_pn_err <= adc_acc_pn_err | adc_pn_err;
adc_acc_pn_oos <= adc_acc_pn_oos | adc_pn_oos;
adc_acc_or <= adc_acc_or | adc_or;
end
end
assign up_adc_xfer_toggle_s = up_adc_xfer_toggle_m2 ^ up_adc_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_xfer_toggle_m1 <= 'd0;
up_adc_xfer_toggle_m2 <= 'd0;
up_adc_xfer_toggle_m3 <= 'd0;
up_adc_xfer_pn_err <= 'd0;
up_adc_xfer_pn_oos <= 'd0;
up_adc_xfer_or <= 'd0;
up_adc_pn_err <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_or <= 'd0;
end else begin
up_adc_xfer_toggle_m1 <= adc_xfer_toggle;
up_adc_xfer_toggle_m2 <= up_adc_xfer_toggle_m1;
up_adc_xfer_toggle_m3 <= up_adc_xfer_toggle_m2;
if (up_adc_xfer_toggle_s == 1'b1) begin
up_adc_xfer_pn_err <= adc_xfer_pn_err;
up_adc_xfer_pn_oos <= adc_xfer_pn_oos;
up_adc_xfer_or <= adc_xfer_or;
end
if (up_adc_xfer_pn_err == 1'b1) begin
up_adc_pn_err <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h1)) begin
up_adc_pn_err <= up_adc_pn_err & ~up_wdata[2];
end
if (up_adc_xfer_pn_oos == 1'b1) begin
up_adc_pn_oos <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h1)) begin
up_adc_pn_oos <= up_adc_pn_oos & ~up_wdata[1];
end
if (up_adc_xfer_or == 1'b1) begin
up_adc_or <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h1)) begin
up_adc_or <= up_adc_or & ~up_wdata[0];
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_mclk_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_mclk_pad(/*AUTOARG*/
// Outputs
to_core, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, shift_dr, oe, odt_enable_mask,
mode_ctrl, hiz_n, data_in, clock_dr, cbu, cbd, bsi
);
inout pad;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
output to_core; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input [8:1] cbd; // To bw_io_ddr_mclk_txrx of bw_io_ddr_mclk_txrx.v
input [8:1] cbu; // To bw_io_ddr_mclk_txrx of bw_io_ddr_mclk_txrx.v
input clock_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input data_in; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input hiz_n; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input mode_ctrl; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input odt_enable_mask; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input oe; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input shift_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input update_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input vdd_h; // To bw_io_ddr_mclk_txrx of bw_io_ddr_mclk_txrx.v
input [7:0] vrefcode; // To bw_io_ddr_mclk_txrx of bw_io_ddr_mclk_txrx.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bscan_oe; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire data_out; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire odt_enable; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire rx_out; // From bw_io_ddr_mclk_txrx of bw_io_ddr_mclk_txrx.v
// End of automatics
/////////////////////
// TRANSCEIVER module
/////////////////////
/* bw_io_ddr_mclk_txrx AUTO_TEMPLATE(
// Outputs
.out (rx_out),
// Inputs
.data (data_out),
.oe (bscan_oe));
*/
bw_io_ddr_mclk_txrx bw_io_ddr_mclk_txrx(/*AUTOINST*/
// Outputs
.out(rx_out), // Templated
// Inouts
.pad(pad),
// Inputs
.vrefcode(vrefcode[7:0]),
.odt_enable(odt_enable),
.vdd_h(vdd_h),
.cbu(cbu[8:1]),
.cbd(cbd[8:1]),
.data(data_out), // Templated
.oe(bscan_oe)); // Templated
/////////////////////
// SCAN & JTAG module
/////////////////////
/*dram_pad_scan_jtag AUTO_TEMPLATE(
// Outputs
.oe(bscan_oe),
// Inputs
.rcv_in(rx_out),
.drv_oe(oe));
*/
bw_io_sstl_bscan bw_io_sstl_bscan(/*AUTOINST*/
// Outputs
.to_core(to_core),
.data_out(data_out),
.oe(bscan_oe), // Templated
.bso(bso),
.odt_enable(odt_enable),
// Inputs
.bsi(bsi),
.mode_ctrl(mode_ctrl),
.clock_dr(clock_dr),
.shift_dr(shift_dr),
.update_dr(update_dr),
.hiz_l(hiz_n),
.rcv_in(rx_out), // Templated
.data_in(data_in),
.drv_oe(oe), // Templated
.odt_enable_mask(odt_enable_mask));
endmodule
// Local Variables:
// verilog-library-directories:(".")
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_ddr0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_ddr0(bscan_mode_ctl_in ,spare_ddr0_paddata ,ddr_si ,
ddr0_dll_bypass_l ,ddr0_bypass_data ,spare_ddr0_pin ,clkobs ,
spare_ddr0_pindata ,ctu_io_clkobs ,tck ,spare_ddr0_pad ,
ddr_testmode_l ,ddr_se ,ps_select ,ddr_so ,pad_ddr0_sscan_out ,afo
,bypass_enable ,bscan_hiz_l_out ,bscan_shift_dr_out ,ps_select_out
,bscan_update_dr_out ,vdd18 ,test_mode ,serial_in ,
bypass_enable_out ,bscan_clock_dr_out ,serial_out ,afi ,
bscan_mode_ctl_out ,bscan_hiz_l_in ,dram0_dq ,dram0_dqs ,dram0_cb ,
dram0_addr ,dram0_ba ,dram0_cs_l ,dram0_we_l ,dram0_cas_l ,
dram0_ras_l ,dram0_cke ,dram0_ck_n ,dram0_ck_p ,
ctu_ddr0_iodll_rst_l ,dram_adbginit_l ,pad_ddr0_bso ,ddr0_ddr1_cbd
,dram_arst_l ,dram_gdbginit_l ,bscan_clock_dr_in ,
ctu_ddr0_dll_delayctr ,pad_ddr0_bsi ,pad_ddr0_sscan_in ,
ctu_io_sscan_se ,ctu_io_sscan_update ,ctu_global_snap ,
dram01_p_ref_res ,ddr0_ddr1_cbu ,bscan_shift_dr_in
,dram01_n_ref_res ,ddr0_ctu_dll_overflow ,bscan_update_dr_in ,
dram0_io_ptr_clk_inv ,dram_gclk ,dram0_io_write_en_l ,
dram0_io_ras_l ,dram0_io_cke ,io_dram0_data_in ,dram0_io_drive_data
,dram0_io_addr ,io_dram0_data_valid ,dram0_io_pad_enable ,
io_dram0_ecc_in ,dram0_io_data_out ,dram0_io_drive_enable ,
dram0_io_channel_disabled ,dram_grst_l ,clk_ddr0_cken ,
dram0_io_cs_l ,dram0_io_cas_l ,dram0_io_clk_enable ,dram0_io_bank ,
dram0_io_pad_clk_inv ,ddr0_ctu_dll_lock, ddr0_lpf_code );
output [4:0] ddr0_lpf_code ;
output [143:0] serial_out ;
output [143:0] afi ;
output [14:0] dram0_addr ;
output [2:0] dram0_ba ;
output [3:0] dram0_cs_l ;
output [3:0] dram0_ck_n ;
output [3:0] dram0_ck_p ;
output [8:1] ddr0_ddr1_cbd ;
output [8:1] ddr0_ddr1_cbu ;
output [255:0] io_dram0_data_in ;
output [31:0] io_dram0_ecc_in ;
input [6:0] spare_ddr0_paddata ;
input [4:0] ddr0_bypass_data ;
input [2:2] spare_ddr0_pindata ;
input [1:0] ctu_io_clkobs ;
input [143:0] afo ;
input [143:0] serial_in ;
input [2:0] ctu_ddr0_dll_delayctr ;
input [4:0] dram0_io_ptr_clk_inv ;
input [1:0] dram_gclk ;
input [14:0] dram0_io_addr ;
input [287:0] dram0_io_data_out ;
input [3:0] dram0_io_cs_l ;
input [2:0] dram0_io_bank ;
inout [2:2] spare_ddr0_pin ;
inout [1:0] clkobs ;
inout [6:0] spare_ddr0_pad ;
inout [127:0] dram0_dq ;
inout [35:0] dram0_dqs ;
inout [15:0] dram0_cb ;
output ddr_so ;
output pad_ddr0_sscan_out ;
output bscan_hiz_l_out ;
output bscan_shift_dr_out ;
output ps_select_out ;
output bscan_update_dr_out ;
output bypass_enable_out ;
output bscan_clock_dr_out ;
output bscan_mode_ctl_out ;
output dram0_we_l ;
output dram0_cas_l ;
output dram0_ras_l ;
output dram0_cke ;
output pad_ddr0_bso ;
output ddr0_ctu_dll_overflow ;
output io_dram0_data_valid ;
output ddr0_ctu_dll_lock ;
input bscan_mode_ctl_in ;
input ddr_si ;
input ddr0_dll_bypass_l ;
input tck ;
input ddr_testmode_l ;
input ddr_se ;
input ps_select ;
input bypass_enable ;
input vdd18 ;
input test_mode ;
input bscan_hiz_l_in ;
input ctu_ddr0_iodll_rst_l ;
input dram_adbginit_l ;
input dram_arst_l ;
input dram_gdbginit_l ;
input bscan_clock_dr_in ;
input pad_ddr0_bsi ;
input pad_ddr0_sscan_in ;
input ctu_io_sscan_se ;
input ctu_io_sscan_update ;
input ctu_global_snap ;
input dram01_p_ref_res ;
input bscan_shift_dr_in ;
input dram01_n_ref_res ;
input bscan_update_dr_in ;
input dram0_io_write_en_l ;
input dram0_io_ras_l ;
input dram0_io_cke ;
input dram0_io_drive_data ;
input dram0_io_pad_enable ;
input dram0_io_drive_enable ;
input dram0_io_channel_disabled ;
input dram_grst_l ;
input clk_ddr0_cken ;
input dram0_io_cas_l ;
input dram0_io_clk_enable ;
input dram0_io_pad_clk_inv ;
supply1 vdd ;
supply0 vss ;
wire [7:0] net223 ;
wire [7:0] net243 ;
wire net191 ;
wire clk_ddr0_cken_buf ;
wire strobe ;
wire rst_l ;
wire sscan0 ;
wire net224 ;
wire scan0 ;
wire scan1 ;
wire scan2 ;
wire scan3 ;
wire net244 ;
wire ddr_se_buf ;
wire rclk ;
wire arst2_l ;
bw_clk_cl_ddr_ddr pad_ddr0_header (
.gclk ({dram_gclk } ),
.ddr_rclk (rclk ),
.so (ddr_so_pre_latch ),
.si (scan3 ),
.gdbginit_l (dram_gdbginit_l ),
.grst_l (dram_grst_l ),
.cluster_grst_l (rst_l ),
.dbginit_l (net191 ),
.rclk (rclk ),
.se (ddr_se_buf ),
.adbginit_l (dram_adbginit_l ),
.arst_l (dram_arst_l ),
.arst2_l (arst2_l ),
.cluster_cken (clk_ddr0_cken_buf ) );
ddr_ch ddr0_ddr_ch (
.arst_l_out (arst2_l ),
.afo ({afo } ),
.serial_in ({serial_in } ),
.afi ({afi } ),
.serial_out ({serial_out } ),
.dram_io_data_out ({dram0_io_data_out } ),
.spare_ddr_pin ({spare_ddr0_pin[2] ,spare_ddr0_pad[6:0] ,
clkobs[1:0] } ),
.spare_ddr_data ({spare_ddr0_pindata[2] ,spare_ddr0_paddata[6:0] ,
ctu_io_clkobs[1:0] } ),
.dram_io_ptr_clk_inv ({dram0_io_ptr_clk_inv } ),
.io_dram_data_in ({io_dram0_data_in } ),
.io_dram_ecc_in ({io_dram0_ecc_in } ),
.dram_io_addr ({dram0_io_addr } ),
.dram_io_bank ({dram0_io_bank } ),
.dram_io_cs_l ({dram0_io_cs_l } ),
.dram_dq ({dram0_dq } ),
.dram_addr ({dram0_addr } ),
.dram_cb ({dram0_cb } ),
.dram_dqs ({dram0_dqs } ),
.dram_ba ({dram0_ba } ),
.dram_ck_n ({dram0_ck_n } ),
.dram_ck_p ({dram0_ck_p } ),
.dram_cs_l ({dram0_cs_l } ),
.lpf_code ({ddr0_lpf_code } ),
.cbu ({ddr0_ddr1_cbu } ),
.cbd ({ddr0_ddr1_cbd } ),
.update_dr_in (bscan_update_dr_in ),
.mode_ctrl_in (bscan_mode_ctl_in ),
.shift_dr_in (bscan_shift_dr_in ),
.clock_dr_in (bscan_clock_dr_in ),
.hiz_n_in (bscan_hiz_l_in ),
.testmode_l (ddr_testmode_l ),
.test_mode (test_mode ),
.bypass_enable_out (bypass_enable_out ),
.ps_select_out (ps_select_out ),
.rclk (rclk ),
.se (ddr_se_buf ),
.pad_clk_so (scan0 ),
.pad_clk_si (ddr_si ),
.bso (pad_ddr0_bso ),
.bsi (pad_ddr0_bsi ),
.mode_ctrl_out (bscan_mode_ctl_out ),
.update_dr_out (bscan_update_dr_out ),
.shift_dr_out (bscan_shift_dr_out ),
.clock_dr_out (bscan_clock_dr_out ),
.hiz_n_out (bscan_hiz_l_out ),
.bypass_enable_in (bypass_enable ),
.ps_select_in (ps_select ),
.strobe (strobe ),
.dram_io_clk_enable (dram0_io_clk_enable ),
.dram_io_cke (dram0_io_cke ),
.dram_io_ras_l (dram0_io_ras_l ),
.dram_io_write_en_l (dram0_io_write_en_l ),
.dram_io_cas_l (dram0_io_cas_l ),
.dram_cke (dram0_cke ),
.io_dram_data_valid (io_dram0_data_valid ),
.dram_ras_l (dram0_ras_l ),
.dram_we_l (dram0_we_l ),
.dram_cas_l (dram0_cas_l ),
.burst_length_four (vdd ),
.dram_io_pad_clk_inv (dram0_io_pad_clk_inv ),
.dram_io_pad_enable (dram0_io_pad_enable ),
.dram_io_drive_enable (dram0_io_drive_enable ),
.rst_l (rst_l ),
.dram_arst_l (dram_arst_l ),
.dram_io_channel_disabled (dram0_io_channel_disabled ),
.dram_io_drive_data (dram0_io_drive_data ),
.vdd_h (vdd18 ) );
bw_io_ddr_impctl_pulldown ddr0_impctl_pulldown (
.z ({ddr0_ddr1_cbd } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net243[0] ,net243[1] ,net243[2] ,net243[3] ,
net243[4] ,net243[5] ,net243[6] ,net243[7] } ),
.tclk (tck ),
.ctu_global_snap (ctu_global_snap ),
.ctu_io_sscan_in (sscan0 ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.ctu_io_sscan_out (pad_ddr0_sscan_out ),
.rclk (rclk ),
.deltabit (net244 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr0_cken_buf ),
.we_csr (vss ),
.si (scan1 ),
.se (ddr_se_buf ),
.vdd18 (vdd18 ),
.pad (dram01_n_ref_res ),
.so (scan2 ) );
// ECO 7016 added ddr0_iodll_code_adjust 10/11/04
// ECO 7016 Changed so, lpf_out port connections on ddr0_master_dll
wire [4:0] ddr0_lpf_code_pre;
wire scan3_pre;
bw_iodll_code_adjust ddr0_iodll_code_adjust (
.bypass_data (ddr0_bypass_data[4:0]),
.ddr_clk_in (rclk),
.delay_ctrl (ctu_ddr0_dll_delayctr[2:0]),
.io_dll_bypass_l (ddr0_dll_bypass_l),
.iodll_reset_l (ctu_ddr0_iodll_rst_l),
.s_controller_out (ddr0_lpf_code_pre[4:0]),
.s_percent_ctrl_out (ddr0_lpf_code[4:0]),
.se (ddr_se_buf),
.si (scan3_pre),
.so (scan3));
bw_iodll ddr0_master_dll (
.ddr_testmode_l (ddr_testmode_l ),
.bypass_data ({ddr0_bypass_data } ),
.lpf_out ({ddr0_lpf_code_pre } ),
.delay_ctrl ({ctu_ddr0_dll_delayctr } ),
.so (scan3_pre ),
.io_dll_bypass_l (ddr0_dll_bypass_l ),
.io_dll_reset_l (ctu_ddr0_iodll_rst_l ),
.se (ddr_se_buf ),
.si (scan2 ),
.ddr_clk_in (rclk ),
.iodll_lock (ddr0_ctu_dll_lock ),
.overflow (ddr0_ctu_dll_overflow ),
.strobe (strobe ) );
// End ECO 7016
bw_io_ddr_impctl_pullup ddr0_impctl_pullup (
.z ({ddr0_ddr1_cbu } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net223[0] ,net223[1] ,net223[2] ,net223[3] ,
net223[4] ,net223[5] ,net223[6] ,net223[7] } ),
.rclk (rclk ),
.so (scan1 ),
.deltabit (net224 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr0_cken_buf ),
.we_csr (vss ),
.si (scan0 ),
.se (ddr_se_buf ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.vdd18 (vdd18 ),
.ctu_io_sscan_in (pad_ddr0_sscan_in ),
.ctu_io_sscan_out (sscan0 ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.pad (dram01_p_ref_res ),
.ctu_global_snap (ctu_global_snap ),
.tclk (tck ) );
bw_u1_buf_40x I223 (
.z (ddr_se_buf ),
.a (ddr_se ) );
bw_u1_buf_40x I225 (
.z (clk_ddr0_cken_buf ),
.a (clk_ddr0_cken ) );
bw_u1_scanl_2x lockup_latch(
.so(ddr_so),
.sd(ddr_so_pre_latch),
.ck(rclk));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_BEHAVIORAL_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: block_positions.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module block_positions (
address,
addressstall_a,
clock,
data,
wren,
q);
input [9:0] address;
input addressstall_a;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 addressstall_a;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.address_a (address),
.addressstall_a (addressstall_a),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "block_locations.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "1"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "block_locations.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "block_locations.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: addressstall_a 0 0 0 0 INPUT GND "addressstall_a"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @addressstall_a 0 0 0 0 addressstall_a 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL block_positions_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module nfa_get_finals_1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
ap_ce,
finals_buckets_address0,
finals_buckets_ce0,
finals_buckets_we0,
finals_buckets_d0,
tmp_28
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [63:0] nfa_finals_buckets_datain;
output [63:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
input ap_ce;
output [3:0] finals_buckets_address0;
output finals_buckets_ce0;
output finals_buckets_we0;
output [63:0] finals_buckets_d0;
input [4:0] tmp_28;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_finals_buckets_req_write;
reg nfa_finals_buckets_rsp_read;
reg finals_buckets_ce0;
reg finals_buckets_we0;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg [4:0] tmp_28_read_reg_67;
reg [4:0] ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1;
reg [4:0] ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2;
reg [63:0] nfa_finals_buckets_read_reg_72;
wire [63:0] tmp_28_cast_fu_63_p1;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1 <= tmp_28_read_reg_67;
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2 <= ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
nfa_finals_buckets_read_reg_72 <= nfa_finals_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
tmp_28_read_reg_67 <= tmp_28;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// finals_buckets_ce0 assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
finals_buckets_ce0 = ap_const_logic_1;
end else begin
finals_buckets_ce0 = ap_const_logic_0;
end
end
/// finals_buckets_we0 assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
finals_buckets_we0 = ap_const_logic_1;
end else begin
finals_buckets_we0 = ap_const_logic_0;
end
end
/// nfa_finals_buckets_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
nfa_finals_buckets_req_write = ap_const_logic_1;
end else begin
nfa_finals_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_finals_buckets_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or nfa_finals_buckets_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (nfa_finals_buckets_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
nfa_finals_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_finals_buckets_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or nfa_finals_buckets_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign finals_buckets_address0 = tmp_28_cast_fu_63_p1;
assign finals_buckets_d0 = nfa_finals_buckets_read_reg_72;
assign nfa_finals_buckets_address = ap_const_lv32_0;
assign nfa_finals_buckets_dataout = ap_const_lv64_0;
assign nfa_finals_buckets_req_din = ap_const_logic_0;
assign nfa_finals_buckets_size = ap_const_lv32_1;
assign tmp_28_cast_fu_63_p1 = $unsigned(ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2);
endmodule //nfa_get_finals_1
|
`default_nettype none
module memory_pipe_arbiter(
input wire iCLOCK,
input wire inRESET,
//Data(Core -> Memory)
input wire iDATA_REQ,
output wire oDATA_LOCK,
input wire [1:0] iDATA_ORDER,
input wire [3:0] iDATA_MASK,
input wire iDATA_RW,
input wire [13:0] iDATA_ASID,
input wire [1:0] iDATA_MMUMOD,
input wire [2:0] iDATA_MMUPS,
input wire [31:0] iDATA_PDT,
input wire [31:0] iDATA_ADDR,
input wire [31:0] iDATA_DATA,
//Data(Memory -> Core)
output wire oDATA_REQ,
input wire iDATA_BUSY,
output wire [63:0] oDATA_DATA,
output wire [23:0] oDATA_MMU_FLAGS,
//Inst(Core -> Memory)
input wire iINST_REQ,
output wire oINST_LOCK,
input wire [1:0] iINST_MMUMOD,
input wire [2:0] iINST_MMUPS,
input wire [31:0] iINST_PDT,
input wire [13:0] iINST_ASID,
input wire [31:0] iINST_ADDR,
//Inst(Memory -> Core)
output wire oINST_REQ,
input wire iINST_BUSY,
output wire [63:0] oINST_DATA,
output wire [23:0] oINST_MMU_FLAGS,
//Memory(OutPort)
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire oMEMORY_DATA_STORE_ACK, //1:Data Access && Store(MMUFlag read only. Not Memory access.)
output wire [1:0] oMEMORY_MMU_MODE,
output wire [2:0] oMEMORY_MMU_PS,
output wire [31:0] oMEMORY_PDT,
output wire [13:0] oMEMORY_ASID,
output wire [1:0] oMEMORY_ORDER,
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW,
output wire [31:0] oMEMORY_ADDR,
output wire [31:0] oMEMORY_DATA,
//Memory(InPort)
input wire iMEMORY_VALID,
output wire oMEMORY_BUSY,
input wire iMEMORY_STORE_ACK,
input wire [63:0] iMEMORY_DATA,
input wire [23:0] iMEMORY_MMU_FLAGS
);
/*********************************************************
Wire and Register
*********************************************************/
//Matching Bridge
wire matching_bridfe_wr_full;
wire matching_bridge_rd_valid;
wire matching_bridge_rd_type;
//Core -> Memory
wire mem2core_inst_lock;
wire mem2core_data_lock;
wire core2mem_inst_condition;
wire core2mem_data_condition;
wire core2mem_data_lock = 1'b0;
reg b_core2mem_req;
reg b_core2mem_data_store_ack;
reg [1:0] b_core2mem_order;
reg [3:0] b_core2mem_mask;
reg b_core2mem_rw;
reg [1:0] b_core2mem_mmumod;
reg [2:0] b_core2mem_mmups;
reg [31:0] b_core2mem_pdt;
reg [13:0] b_core2mem_asid;
reg [31:0] b_core2mem_addr;
reg [31:0] b_core2mem_data;
//Memory -> Core
reg b_mem2core_inst_valid;
reg [63:0] b_mem2core_inst_data;
reg [23:0] b_mem2core_inst_mmu_flags;
reg b_mem2core_data_valid;
reg [63:0] b_mem2core_data_data;
reg [23:0] b_mem2core_data_mmu_flags;
//Condition
wire mem2core_common_lock = matching_bridfe_wr_full || iMEMORY_LOCK;
wire core2mem_data_write_ack_condition = iDATA_RW && core2mem_data_condition;
wire core2mem_normal_memory_access_condition = (!iDATA_RW && core2mem_data_condition) || core2mem_inst_condition;
/*********************************************************
Memory Matching Controal
*********************************************************/
mist1032isa_arbiter_matching_queue #(16, 4, 1) MEM_MATCHING_BRIDGE( //Queue deep : 16, Queue deep_n : 4, Flag_n : 1
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(1'b0),
//Write
.iWR_REQ(!mem2core_common_lock && core2mem_normal_memory_access_condition),
.iWR_FLAG(core2mem_data_condition), //0:Inst, 1:Data
.oWR_FULL(matching_bridfe_wr_full),
//Read
.iRD_REQ(iMEMORY_VALID && (matching_bridge_rd_type && !core2mem_data_lock || !matching_bridge_rd_type && !iINST_BUSY) && !iMEMORY_STORE_ACK),
.oRD_VALID(matching_bridge_rd_valid),
.oRD_FLAG(matching_bridge_rd_type), //0:Inst, 1:Data
.oRD_EMPTY()
);
/*********************************************************
Buffer & Assign(Core -> Memory)
*********************************************************/
//assign
assign mem2core_inst_lock = mem2core_common_lock || core2mem_data_condition;
assign mem2core_data_lock = mem2core_common_lock || core2mem_inst_condition;
assign core2mem_inst_condition = !iDATA_REQ && iINST_REQ;
assign core2mem_data_condition = iDATA_REQ;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_core2mem_req <= 1'b0;
b_core2mem_order <= 2'h0;
b_core2mem_mask <= 4'h0;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= 2'h0;
b_core2mem_mmups <= 3'h0;
b_core2mem_pdt <= {32{1'b0}};
b_core2mem_asid <= 14'h0;
b_core2mem_addr <= {32{1'b0}};
b_core2mem_data <= {32{1'b0}};
end
else begin
if(!mem2core_common_lock)begin
//if(b_io_startaddr_valid )
if(core2mem_data_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= iDATA_ORDER;
b_core2mem_mask <= iDATA_MASK;
b_core2mem_rw <= iDATA_RW;
b_core2mem_data_store_ack <= core2mem_data_write_ack_condition;
b_core2mem_mmumod <= iDATA_MMUMOD;
b_core2mem_mmups <= iDATA_MMUPS;
b_core2mem_pdt <= iDATA_PDT;
b_core2mem_asid <= iDATA_ASID;
b_core2mem_addr <= iDATA_ADDR;
b_core2mem_data <= iDATA_DATA;
end
else if(core2mem_inst_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= 2'h2;
b_core2mem_mask <= 4'hf;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= iINST_MMUMOD;
b_core2mem_mmups <= iINST_MMUPS;
b_core2mem_pdt <= iINST_PDT;
b_core2mem_asid <= iINST_ASID;
b_core2mem_addr <= iINST_ADDR;
b_core2mem_data <= {32{1'b0}};
end
else begin
b_core2mem_req <= 1'b0;
end
end
end
end
/*********************************************************
Inst Data Selector & Buffer & assign (Memory -> Core)
*********************************************************/
//Inst
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_inst_valid <= 1'b0;
b_mem2core_inst_data <= {63{1'b0}};
b_mem2core_inst_mmu_flags <= 24'h0;
end
else begin
if(!iINST_BUSY)begin
b_mem2core_inst_valid <= !matching_bridge_rd_type && matching_bridge_rd_valid && !iMEMORY_STORE_ACK && iMEMORY_VALID;
b_mem2core_inst_data <= iMEMORY_DATA;
b_mem2core_inst_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
//Data
assign core2mem_data_lock = 1'b0;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_data_valid <= 1'b0;
b_mem2core_data_data <= {63{1'b0}};
b_mem2core_data_mmu_flags <= 24'h0;
end
else begin
if(!core2mem_data_lock)begin
b_mem2core_data_valid <= ((matching_bridge_rd_type && matching_bridge_rd_valid) || iMEMORY_STORE_ACK) && iMEMORY_VALID;
b_mem2core_data_data <= iMEMORY_DATA;
b_mem2core_data_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
/*********************************************************
Assign
*********************************************************/
assign oDATA_LOCK = mem2core_data_lock;
assign oINST_LOCK = mem2core_inst_lock;
assign oMEMORY_REQ = b_core2mem_req;
assign oMEMORY_DATA_STORE_ACK = b_core2mem_data_store_ack;
assign oMEMORY_MMU_MODE = b_core2mem_mmumod;
assign oMEMORY_MMU_PS = b_core2mem_mmups;
assign oMEMORY_PDT = b_core2mem_pdt;
assign oMEMORY_ASID = b_core2mem_asid;
assign oMEMORY_ORDER = b_core2mem_order;
assign oMEMORY_MASK = b_core2mem_mask;
assign oMEMORY_RW = b_core2mem_rw;
assign oMEMORY_ADDR = b_core2mem_addr;
assign oMEMORY_DATA = b_core2mem_data;
assign oMEMORY_BUSY = iDATA_BUSY || iINST_BUSY;
assign oDATA_REQ = b_mem2core_data_valid && !core2mem_data_lock;
assign oDATA_DATA = b_mem2core_data_data;
assign oDATA_MMU_FLAGS = b_mem2core_data_mmu_flags;
assign oINST_REQ = b_mem2core_inst_valid && !iINST_BUSY;
assign oINST_DATA = b_mem2core_inst_data;
assign oINST_MMU_FLAGS = b_mem2core_inst_mmu_flags;
endmodule
`default_nettype wire
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 17:09:37 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/parallella-hw/fpga/vivado/archives/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ip/axi_bram_ctrl_16b/axi_bram_ctrl_16b_stub.v
// Design : axi_bram_ctrl_16b
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2014.3.1" *)
module axi_bram_ctrl_16b(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [15:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
//dummy outputs
assign s_axi_awready=1'b0;
assign s_axi_wready=1'b0;
assign s_axi_bresp[1:0]=2'b0;
assign s_axi_bvalid=1'b0;
assign s_axi_arready=1'b0;
assign s_axi_rdata[31:0]=32'b0;
assign s_axi_rresp[1:0]=2'b0;
assign s_axi_rvalid=1'b0;
assign bram_rst_a=1'b0;
assign bram_clk_a=s_axi_aclk;
assign bram_en_a=1'b0;
assign bram_we_a [3:0]=4'b0;
assign bram_addr_a[15:0]=16'b0;
assign bram_wrdata_a[31:0]=32'b0;
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xfcp_interface_uart
*/
module test_xfcp_interface_uart;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg uart_rxd = 1;
reg [7:0] down_xfcp_in_tdata = 0;
reg down_xfcp_in_tvalid = 0;
reg down_xfcp_in_tlast = 0;
reg down_xfcp_in_tuser = 0;
reg down_xfcp_out_tready = 0;
reg [15:0] prescale = 0;
// Outputs
wire uart_txd;
wire down_xfcp_in_tready;
wire [7:0] down_xfcp_out_tdata;
wire down_xfcp_out_tvalid;
wire down_xfcp_out_tlast;
wire down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
uart_rxd,
down_xfcp_in_tdata,
down_xfcp_in_tvalid,
down_xfcp_in_tlast,
down_xfcp_in_tuser,
down_xfcp_out_tready,
prescale
);
$to_myhdl(
uart_txd,
down_xfcp_in_tready,
down_xfcp_out_tdata,
down_xfcp_out_tvalid,
down_xfcp_out_tlast,
down_xfcp_out_tuser
);
// dump file
$dumpfile("test_xfcp_interface_uart.lxt");
$dumpvars(0, test_xfcp_interface_uart);
end
xfcp_interface_uart
UUT (
.clk(clk),
.rst(rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast),
.down_xfcp_out_tuser(down_xfcp_out_tuser),
.prescale(prescale)
);
endmodule
|
// Strob signals generator
module strobgen(
input clk_sys,
input ss11, ss12, ss13, ss14, ss15,
input ok$, zw, oken,
input mode, step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
);
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = zw & oken;
wire es1 = ss11 | (ss12 & ok$) | (ss13 & ok$) | ss14 | ss15;
wire has_strob2 = ss11 | ss12;
wire no_strob2 = ss13 | ss14 | ss15;
assign got = state == S_GOT;
assign strob1 = (state == S_ST1) | strob_fp;
assign strob1b = (state == S_ST1B) | strobb_fp;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
// * step jest uzbrajany jeśli MODE=1 i wystąpił STROB1
// * STEP zabrania przejścia do stanu STROB2 jeśli ss11 | ss12 (czyli jeśli jesteśmy w strob1 po którym jest strob2, to będziemy trzymać strob1)
// * STEP zabrania przejścia do stanu GOT jeśli ~(ss11 | ss12) (czyli jeśli jesteśmy w strob1 bez strob2, to będziemy trzymać strob1)
// * wciśnięcie STEP zeruje przerzutnik i CPU wykonuje krok (odpala się przejście do następnego stanu)
// * MODE=0 resetuje przerzutnik i trzyma go w takim stanie (czyli step nie działa przy MODE=0)
// * podsumowując: jeśli MODE=1, to podtrzymujemy bieżący stan STROB1 dopóki użytkownik nie wciśnie STOP
// STEP
reg lstep;
always @ (posedge clk_sys) begin
lstep <= step;
end
wire step_trig = ~mode | (step & ~lstep);
// STROBS
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
// GOT
S_GOT: begin
if (es1) begin
state <= S_ST1;
end else begin
state <= S_GOTW;
end
end
S_GOTW: begin
if (es1) begin
state <= S_ST1;
end
end
// STROB1 front
S_ST1: begin
if (step_trig) state <= S_ST1B;
else state <= S_ST1W;
end
// STROB1 front (wait for STEP)
S_ST1W: begin
if (step_trig) state <= S_ST1B;
end
// STROB1 back
S_ST1B: begin
if (has_strob2) begin
state <= S_ST2;
end else if (no_strob2 & ~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 front
S_ST2: begin
state <= S_ST2B;
end
// STROB2 back
S_ST2B: begin
if (~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 back (wait for I/F operation to end)
S_PGOT: begin
if (~if_busy) begin
state <= S_GOT;
end
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200.000000, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0\
, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_2.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_jid_to_yid_table.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_jid_to_yid_table -- JBus JID to YID translation table.
// _____________________________________________________________________________
//
// Description:
// Provides a JID to YID translation table. Provides 16 direct mapped JID to YID
// entries. Access is one read port ('trans_*' signals), and one write port
// ('alloc_*' signals).
//
// Interface:
// Translation request:
// A JID 'trans_jid' is given which returns the YID 'trans_yid' on the same cycle.
// There are no qualifier signals.
//
// Allocating an assignment request:
// When 'alloc' is asserted, the YID 'alloc_yid' will be associated with the JID 'alloc_yid'.
//
// Design Notes:
// o The table 'yid_table' is indexed by the 'jid' to provide the associated 'yid'.
// o This is a one read port, one write port structure that uses 208 storage bits.
// _____________________________________________________________________________
`include "sys.h"
module jbi_jid_to_yid_table (/*AUTOARG*/
// Outputs
trans_yid0, trans_yid1,
// Inputs
trans_jid0, trans_jid1, alloc, alloc_jid, alloc_yid, clk, rst_l
);
// Translation, port 0.
input [3:0] trans_jid0;
output [9:0] trans_yid0;
// Translation, port 1.
input [3:0] trans_jid1;
output [9:0] trans_yid1;
// Allocating an assignment.
input alloc;
input [3:0] alloc_jid;
input [9:0] alloc_yid;
// Clock and reset.
input clk;
input rst_l;
// Wires and Regs.
wire write_00, write_01, write_02, write_03, write_04, write_05, write_06, write_07;
wire write_08, write_09, write_10, write_11, write_12, write_13, write_14, write_15;
wire [9:0] next_yid_table_00, yid_table_00;
wire [9:0] next_yid_table_01, yid_table_01;
wire [9:0] next_yid_table_02, yid_table_02;
wire [9:0] next_yid_table_03, yid_table_03;
wire [9:0] next_yid_table_04, yid_table_04;
wire [9:0] next_yid_table_05, yid_table_05;
wire [9:0] next_yid_table_06, yid_table_06;
wire [9:0] next_yid_table_07, yid_table_07;
wire [9:0] next_yid_table_08, yid_table_08;
wire [9:0] next_yid_table_09, yid_table_09;
wire [9:0] next_yid_table_10, yid_table_10;
wire [9:0] next_yid_table_11, yid_table_11;
wire [9:0] next_yid_table_12, yid_table_12;
wire [9:0] next_yid_table_13, yid_table_13;
wire [9:0] next_yid_table_14, yid_table_14;
wire [9:0] next_yid_table_15, yid_table_15;
reg [9:0] trans_yid0, trans_yid1;
// YID Table Read Port0.
always @(/*AS*/trans_jid0 or yid_table_00 or yid_table_01 or yid_table_02
or yid_table_03 or yid_table_04 or yid_table_05 or yid_table_06
or yid_table_07 or yid_table_08 or yid_table_09 or yid_table_10
or yid_table_11 or yid_table_12 or yid_table_13 or yid_table_14
or yid_table_15) begin
case(trans_jid0) // synopsys infer_mux
4'd00: trans_yid0 = yid_table_00;
4'd01: trans_yid0 = yid_table_01;
4'd02: trans_yid0 = yid_table_02;
4'd03: trans_yid0 = yid_table_03;
4'd04: trans_yid0 = yid_table_04;
4'd05: trans_yid0 = yid_table_05;
4'd06: trans_yid0 = yid_table_06;
4'd07: trans_yid0 = yid_table_07;
4'd08: trans_yid0 = yid_table_08;
4'd09: trans_yid0 = yid_table_09;
4'd10: trans_yid0 = yid_table_10;
4'd11: trans_yid0 = yid_table_11;
4'd12: trans_yid0 = yid_table_12;
4'd13: trans_yid0 = yid_table_13;
4'd14: trans_yid0 = yid_table_14;
4'd15: trans_yid0 = yid_table_15;
endcase
end
// YID Table Read Port1.
always @(/*AS*/trans_jid1 or yid_table_00 or yid_table_01 or yid_table_02
or yid_table_03 or yid_table_04 or yid_table_05 or yid_table_06
or yid_table_07 or yid_table_08 or yid_table_09 or yid_table_10
or yid_table_11 or yid_table_12 or yid_table_13 or yid_table_14
or yid_table_15) begin
case(trans_jid1) // synopsys infer_mux
4'd00: trans_yid1 = yid_table_00;
4'd01: trans_yid1 = yid_table_01;
4'd02: trans_yid1 = yid_table_02;
4'd03: trans_yid1 = yid_table_03;
4'd04: trans_yid1 = yid_table_04;
4'd05: trans_yid1 = yid_table_05;
4'd06: trans_yid1 = yid_table_06;
4'd07: trans_yid1 = yid_table_07;
4'd08: trans_yid1 = yid_table_08;
4'd09: trans_yid1 = yid_table_09;
4'd10: trans_yid1 = yid_table_10;
4'd11: trans_yid1 = yid_table_11;
4'd12: trans_yid1 = yid_table_12;
4'd13: trans_yid1 = yid_table_13;
4'd14: trans_yid1 = yid_table_14;
4'd15: trans_yid1 = yid_table_15;
endcase
end
// YID Table Write Port.
assign write_00 = alloc && (alloc_jid == 4'd00);
assign write_01 = alloc && (alloc_jid == 4'd01);
assign write_02 = alloc && (alloc_jid == 4'd02);
assign write_03 = alloc && (alloc_jid == 4'd03);
assign write_04 = alloc && (alloc_jid == 4'd04);
assign write_05 = alloc && (alloc_jid == 4'd05);
assign write_06 = alloc && (alloc_jid == 4'd06);
assign write_07 = alloc && (alloc_jid == 4'd07);
assign write_08 = alloc && (alloc_jid == 4'd08);
assign write_09 = alloc && (alloc_jid == 4'd09);
assign write_10 = alloc && (alloc_jid == 4'd10);
assign write_11 = alloc && (alloc_jid == 4'd11);
assign write_12 = alloc && (alloc_jid == 4'd12);
assign write_13 = alloc && (alloc_jid == 4'd13);
assign write_14 = alloc && (alloc_jid == 4'd14);
assign write_15 = alloc && (alloc_jid == 4'd15);
assign next_yid_table_00 = alloc_yid;
assign next_yid_table_01 = alloc_yid;
assign next_yid_table_02 = alloc_yid;
assign next_yid_table_03 = alloc_yid;
assign next_yid_table_04 = alloc_yid;
assign next_yid_table_05 = alloc_yid;
assign next_yid_table_06 = alloc_yid;
assign next_yid_table_07 = alloc_yid;
assign next_yid_table_08 = alloc_yid;
assign next_yid_table_09 = alloc_yid;
assign next_yid_table_10 = alloc_yid;
assign next_yid_table_11 = alloc_yid;
assign next_yid_table_12 = alloc_yid;
assign next_yid_table_13 = alloc_yid;
assign next_yid_table_14 = alloc_yid;
assign next_yid_table_15 = alloc_yid;
// YID Table.
dffrle_ns #(10) yid_table_00_reg (.din(next_yid_table_00), .en(write_00), .q(yid_table_00), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_01_reg (.din(next_yid_table_01), .en(write_01), .q(yid_table_01), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_02_reg (.din(next_yid_table_02), .en(write_02), .q(yid_table_02), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_03_reg (.din(next_yid_table_03), .en(write_03), .q(yid_table_03), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_04_reg (.din(next_yid_table_04), .en(write_04), .q(yid_table_04), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_05_reg (.din(next_yid_table_05), .en(write_05), .q(yid_table_05), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_06_reg (.din(next_yid_table_06), .en(write_06), .q(yid_table_06), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_07_reg (.din(next_yid_table_07), .en(write_07), .q(yid_table_07), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_08_reg (.din(next_yid_table_08), .en(write_08), .q(yid_table_08), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_09_reg (.din(next_yid_table_09), .en(write_09), .q(yid_table_09), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_10_reg (.din(next_yid_table_10), .en(write_10), .q(yid_table_10), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_11_reg (.din(next_yid_table_11), .en(write_11), .q(yid_table_11), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_12_reg (.din(next_yid_table_12), .en(write_12), .q(yid_table_12), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_13_reg (.din(next_yid_table_13), .en(write_13), .q(yid_table_13), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_14_reg (.din(next_yid_table_14), .en(write_14), .q(yid_table_14), .rst_l(rst_l), .clk(clk));
dffrle_ns #(10) yid_table_15_reg (.din(next_yid_table_15), .en(write_15), .q(yid_table_15), .rst_l(rst_l), .clk(clk));
endmodule
// Local Variables:
// verilog-library-directories:("../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_jid_to_yid")
// End:
|
// test_psi2c.v
`timescale 1 ns / 1 ps
module test_psi2c;
// avalon clock interface
reg clk = 0;
reg reset = 1;
// avalon mm slave
reg [2:0]address = 3'bxxx;
reg read = 0;
wire [31:0]readdata;
reg write = 0;
reg [31:0]writedata = 32'hxxxx_xxxx;
// conduit
reg sync = 0;
wire phase;
wire send;
wire sda;
wire rda = sda;
localparam s = 31'h0000_0800; // i2c start
localparam p = 31'h0000_0400; // i2c stop
task Write(input [2:0]a, input [31:0]d);
begin
@(posedge clk) #1;
address = a;
writedata = d;
write = 1;
@(posedge clk) #1;
address = 3'bxxx;
writedata = 32'hxxxx_xxxx;
write = 0;
end
endtask
task Read(input [2:0]a);
begin
@(posedge clk) #1;
address = a;
read = 1;
@(posedge clk) #1;
address = 3'bxxx;
read = 0;
end
endtask
always #10 clk = !clk;
always @(posedge clk) sync = !sync;
assign phase = !sync;
initial
begin
#60 reset = 0;
#200 Write(0, 0);
Write(1, s + 'h2aa);
Write(1, 'h2aa);
Write(1, p + 'h2aa);
Write(0, 1);
#200 Read(0);
#1150 Read(0);
Write(3, 'h55);
Write(2, 'hca);
Write(4, 'h35);
Write(0, 1);
#1400 $stop(2);
end
psi2c DUT
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
.avs_ctrl_address(address),
.avs_ctrl_read(read),
.avs_ctrl_readdata(readdata),
.avs_ctrl_write(write),
.avs_ctrl_writedata(writedata),
.sync(sync),
.phase(phase),
.send(send),
.sda(sda),
.rda(rda)
);
endmodule
|
/*
* In The Name Of God
* ========================================
* [] File Name : cache_ctl_t.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Thu, Apr 2, 2015 10:12:18 AM
*
* [] Created By : Parham Alvani ([email protected])
* =======================================
*/
`timescale 1 ns/100 ps
module cache_ctl_t;
reg [0:15] data_in;
reg [0:4] tag;
reg enable;
reg clk;
reg write;
reg [0:1] word;
reg cmp;
reg rst;
reg valid_in;
reg [0:3] index;
wire [0:15] data_out;
wire [0:4] tag_out;
wire hit;
wire dirty;
wire valid;
initial begin
$dumpfile("cache_ctl.vcd");
$dumpvars(0, cache_ctl_t);
enable = 0;
word = 2'b11;
data_in = 16'b0000_1111_0000_1111;
valid_in = 1'b1;
tag = 5'b11101;
index = 4'b0000;
#5
enable = 1;
write = 1;
cmp = 0;
#5
enable = 0;
#5
enable = 1;
write = 0;
cmp = 1;
#5
enable = 0;
write = 0;
cmp = 0;
rst = 1;
#5
enable = 1;
#5
enable = 0;
rst = 0;
write = 0;
cmp = 0;
#5
enable = 1;
#5
enable = 0;
$stop;
end
initial begin
clk = 0;
forever begin
#5
clk = ~clk;
end
end
cache_ctl chc(clk, enable, index, word, cmp, write, tag, data_in, valid_in, rst, hit, dirty, tag_out, data_out, valid);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_PP_SYMBOL_V
|
Require Import Setoid.
Require Import Morphisms.
Require Import Coq.Program.Basics.
Require Import NArith.
Unset Printing Records.
From Ordinal Require Import Defs.
(** * Ordinal operators *)
(** The zero ordinal, which is indexed by the empty type False *)
Definition zeroOrd : Ord := ord False (False_rect _).
(** The successor ordinal, which is indexed by the unit type *)
Definition succOrd (x:Ord) : Ord := ord unit (fun _ => x).
(* Set up numeric notation for ordinals *)
Number Notation Ord Nat.of_num_uint Nat.to_num_uint
(via nat mapping [zeroOrd => O, succOrd => S]) : ord_scope.
Definition limOrd {A:Type} (f:A -> Ord) := ord A f.
(** The binary upper bound of two ordinals is constructed using a sum type
over the indices of the two incomming ordinals *)
Definition lubOrd (x y:Ord) : Ord :=
match x, y with
| ord A f, ord B g =>
ord (A+B) (fun ab => match ab with inl a => f a | inr b => g b end)
end.
Notation "x ⊔ y" := (lubOrd x y) (at level 55, right associativity) : ord_scope.
(** The supremum of a collection of ordinals is indexed by a sigma type. *)
Definition supOrd {A:Type} (f:A -> Ord) :=
ord (sigT (fun a => ordCarrier (f a)))
(fun ai => ordSize (f (projT1 ai)) (projT2 ai)).
(** The binary greatest lower bound of two ordinals is indexed by a pair, and
we essentially simultaneously play the game represented by the two ordinals.
*)
Fixpoint glbOrd (x y:Ord) : Ord :=
match x, y with
| ord A f, ord B g =>
ord (A*B) (fun ab => glbOrd (f (fst ab)) (g (snd ab)))
end.
Notation "x ⊓ y" := (glbOrd x y) (at level 55, right associativity) : ord_scope.
(** It does not appear to be possible to construct the infimum of an infinite
collection of ordinals. This would essentially compute the least ordinal
among a collection. One is tempted to make the index type of this ordinal
a dependent function (representing an element of each of the index sets of
the collection; but I have not been able to figure out how to make it work.
*)
(** We say that a function on ordinals is strongly continuous
if it preserves all nonempty suprema. *)
Definition strongly_continuous (s:Ord -> Ord) :=
forall A (f:A -> Ord) (a0:A), s (supOrd f) ≤ supOrd (fun i:A => s (f i)).
(* Natural numbers have an ordinal size.
*)
Fixpoint natOrdSize (x:nat) :=
match x with
| O => zeroOrd
| S n => succOrd (natOrdSize n)
end.
Canonical Structure ω : Ord :=
ord nat natOrdSize.
(** We can constructed the supremum of the image of a function on ordinals,
when applied to all the ordinals strictly below β.
*)
Definition boundedSup (β:Ord) (f:Ord -> Ord) : Ord :=
match β with
| ord B g => supOrd (fun i => f (g i))
end.
(** The predecessor of an ordinal is the supremum of all the ordinals
strictly below it. This function is stationary on limit ordinals
(and zero) but undoes the action of a successor.
*)
Definition predOrd (x:Ord) : Ord :=
match x with
| ord A f => supOrd f
end.
(** A "complete" ordinal is one which is directed, in an order-theoretic
sense; for which it decidable if it is inhabited; and for which all its
subordinals are also complete.
This is a technical property that appears necessary in some later proofs.
In a classical setting all ordinals have this property, as it follows
easily from the totality of order.
*)
Definition directed A (f:A -> Ord) :=
forall a1 a2, exists a', f a1 <= f a' /\ f a2 <= f a'.
Fixpoint complete (x:Ord) : Prop :=
match x with
| ord A f =>
(directed A f) /\
(inhabited A \/ ~inhabited A) /\
(forall a, complete (f a))
end.
Lemma complete_subord o :
complete o -> forall i, complete (o i).
Proof.
destruct o as [A f]; simpl; intuition.
Qed.
Lemma complete_zeroDec o :
complete o -> o <= zeroOrd \/ zeroOrd < o.
Proof.
destruct o as [A f]; simpl; intuition.
- right.
destruct H1 as [a].
rewrite ord_lt_unfold. exists a.
rewrite ord_le_unfold; simpl; intuition.
- left.
rewrite ord_le_unfold. intro a.
elim H1. exact (inhabits a).
Qed.
Lemma complete_directed o :
complete o ->
forall a1 a2, exists a',
o a1 <= o a' /\
o a2 <= o a'.
Proof.
destruct o as [A f]; simpl; intuition.
Qed.
Lemma directed_monotone :
forall (a:Ord) f,
(forall (x y:a), sz x <= sz y -> f x <= f y) ->
complete a ->
directed a f.
Proof.
intros.
hnf; simpl; intros.
destruct (complete_directed a H0 a1 a2) as [a' [??]].
exists a'.
split; apply H; auto.
Qed.
Lemma zero_unfold : zeroOrd = ord False (False_rect Ord).
Proof.
reflexivity.
Qed.
(** Zero is the least ordinal. *)
Lemma zero_least : forall o, 0 ≤ o.
Proof.
intros. rewrite ord_le_unfold.
simpl. intros [].
Qed.
Global Hint Resolve zero_least : ord.
Lemma zero_complete : complete 0.
Proof.
simpl; repeat (hnf; intuition).
right. intros [[]].
Qed.
Lemma succ_unfold x : succOrd x = ord unit (fun _ => x).
Proof.
reflexivity.
Qed.
(** Succ is a monotone operator with respetct to both lt and le, and
* is strictly above its argument.
*
* Moreover, it is the smallest ordinal which is strictly above its
* argument.
*)
Lemma succ_lt : forall o, o < succOrd o.
Proof.
intros.
rewrite ord_lt_unfold. simpl. exists tt. apply ord_le_refl.
Qed.
Global Hint Resolve succ_lt : ord.
Lemma succ_least : forall x y, x < y -> succOrd x ≤ y.
Proof.
intros.
rewrite ord_le_unfold. simpl; auto.
Qed.
Lemma succ_monotone : forall a b, a ≤ b -> succOrd a ≤ succOrd b.
Proof.
intros.
apply succ_least.
apply ord_le_lt_trans with b; auto with ord.
Qed.
Lemma succ_increasing : forall a b, a < b -> succOrd a < succOrd b.
Proof.
intros.
apply ord_le_lt_trans with b; auto with ord.
apply succ_least; auto.
Qed.
Lemma succ_trans x y : x ≤ y -> x < succOrd y.
Proof.
intros.
rewrite ord_lt_unfold.
simpl. exists tt. auto.
Qed.
Lemma succ_trans' x y : x ≤ y -> x ≤ succOrd y.
Proof.
intros.
apply ord_lt_le.
apply succ_trans; auto.
Qed.
Lemma succ_congruence : forall a b, a ≈ b -> succOrd a ≈ succOrd b.
Proof.
unfold ord_eq; intuition; apply succ_monotone; auto.
Qed.
Add Parametric Morphism : succOrd with signature
ord_le ++> ord_le as succOrd_le_mor.
Proof.
intros; apply succ_monotone; auto.
Qed.
Add Parametric Morphism : succOrd with signature
ord_lt ++> ord_lt as succOrd_lt_mor.
Proof.
intros; apply succ_increasing; auto.
Qed.
Add Parametric Morphism : succOrd with signature
ord_eq ==> ord_eq as succOrd_eq_mor.
Proof.
intros; apply succ_congruence; auto.
Qed.
Lemma succ_complete :forall o, complete o -> complete (succOrd o).
Proof.
intros; hnf; simpl; intuition.
- exists tt; split; reflexivity.
- left; exact (inhabits tt).
Qed.
Lemma natOrdSize_complete n : complete (natOrdSize n).
Proof.
induction n; simpl natOrdSize.
apply zero_complete.
apply succ_complete; auto.
Qed.
Lemma sup_unfold A (f:A->Ord) :
supOrd f =
ord (sigT (fun a => ordCarrier (f a)))
(fun ai => ordSize (f (projT1 ai)) (projT2 ai)).
Proof.
reflexivity.
Qed.
(** The supremum is nonstrictly above all the ordinals in the
* collection defined by "f". Morover it is it the smallest such.
*)
Lemma sup_le : forall A (f:A -> Ord) a, f a ≤ supOrd f.
Proof.
intros A f a.
rewrite ord_le_unfold.
intro b.
rewrite ord_lt_unfold.
exists (@existT A (fun a => ordCarrier (f a)) a b).
simpl. auto with ord.
Qed.
Lemma sup_least : forall A (f:A -> Ord) z,
(forall a, f a ≤ z) -> supOrd f ≤ z.
Proof.
intros A f z H.
rewrite ord_le_unfold.
intros [a b]; simpl.
specialize (H a).
rewrite ord_le_unfold in H.
apply H.
Qed.
Lemma sup_lt x A (f:A -> Ord) :
x < supOrd f -> exists a:A, x < f a.
Proof.
rewrite ord_lt_unfold. simpl.
intros [[a q] H]; simpl in *.
exists a.
rewrite ord_lt_unfold.
exists q. auto.
Qed.
Instance sup_ord_le_morphism (A:Type) :
Proper (pointwise_relation _ ord_le ==> ord_le) (@supOrd A).
Proof.
repeat intro.
red in H.
apply sup_least. intro a.
rewrite H.
apply sup_le.
Qed.
Instance sup_ord_eq_morphism (A:Type) :
Proper (pointwise_relation _ ord_eq ==> ord_eq) (@supOrd A).
Proof.
repeat intro.
split.
red in H.
apply sup_ord_le_morphism; red; intros; apply H.
apply sup_ord_le_morphism; red; intros; apply H.
Qed.
Lemma limit_unfold A (f:A -> Ord) : limOrd f = ord A f.
Proof.
reflexivity.
Qed.
(** The limit ordinal is strictly above all the ordinals in
* the collection defined by "f". Moreover it is the smallest
* such.
*)
Lemma limit_lt : forall A (f:A -> Ord) i, f i < limOrd f.
Proof.
intros. rewrite ord_lt_unfold. simpl.
exists i. apply ord_le_refl.
Qed.
Lemma limit_least : forall A (f:A -> Ord) z,
(forall i, f i < z) -> limOrd f ≤ z.
Proof.
intros. rewrite ord_le_unfold.
simpl. auto.
Qed.
Global Hint Resolve limit_lt sup_le : ord.
(** Supremum and limit are closely related operations.
We always have: sup f <= lim f <= succ (sup f).
Moreover: lim f = sup (succ . f)
When f is an ascending set, lim f = sup f
When f has a maximal element, lim f = succ (sup f)
*)
Lemma sup_lim : forall A (f:A -> Ord),
supOrd f ≤ limOrd f.
Proof.
intros A f.
apply sup_least.
auto with ord.
Qed.
Lemma lim_sup : forall A (f:A -> Ord),
limOrd f ≤ succOrd (supOrd f).
Proof.
intros A f.
apply limit_least. intro a.
apply ord_le_lt_trans with (supOrd f); auto with ord.
Qed.
Lemma sup_succ_lim : forall A (f:A -> Ord),
limOrd f ≈ supOrd (fun a:A => succOrd (f a)).
Proof.
intros.
split.
- apply limit_least. intros.
rewrite ord_lt_unfold.
simpl.
exists (existT _ i tt).
simpl; auto with ord.
- apply sup_least.
intros.
apply succ_least.
apply limit_lt.
Qed.
Lemma ascending_sup_lim : forall A (f:A -> Ord),
ascendingSet A f ->
limOrd f ≈ supOrd f.
Proof.
intros.
split; [ | apply sup_lim ].
apply limit_least. intro a.
destruct (H a) as [a' ?].
apply ord_lt_le_trans with (f a'); auto with ord.
Qed.
Lemma succ_sup_lim : forall A (f:A -> Ord),
hasMaxElement A f ->
limOrd f ≈ succOrd (supOrd f).
Proof.
intros.
split; [ apply lim_sup |].
apply succ_least.
destruct H as [amax Hamax].
rewrite ord_lt_unfold. simpl. exists amax.
apply sup_least. auto.
Qed.
Instance lim_ord_le_morphism (A:Type) :
Proper (pointwise_relation _ ord_le ==> ord_le) (@limOrd A).
Proof.
repeat intro.
apply limit_least. intros.
red in H. rewrite H.
apply limit_lt.
Qed.
Instance lim_ord_eq_morphism (A:Type) :
Proper (pointwise_relation _ ord_eq ==> ord_eq) (@limOrd A).
Proof.
repeat intro.
split; apply lim_ord_le_morphism;
red; intros; apply H.
Qed.
(** Provided f is a monotone function, boundedSup β f
is an upper bound of f α whenever a < β. Moreover, it
is the smallest ordinal with this property.
*)
Lemma boundedSup_le β (f:Ord -> Ord) :
(forall x y, x ≤ y -> f x ≤ f y) ->
forall x, x < β -> f x ≤ boundedSup β f.
Proof.
intro Hmono.
destruct β as [B g].
simpl; intros.
rewrite ord_lt_unfold in H.
destruct H as [b Hb].
rewrite <- (sup_le _ _ b).
apply Hmono. apply Hb.
Qed.
Lemma boundedSup_least β (f:Ord -> Ord) z :
(forall x, x < β -> f x ≤ z) ->
boundedSup β f ≤ z.
Proof.
destruct β as [B g]. simpl. intros.
apply sup_least.
intros. apply H.
apply (index_lt (ord B g)).
Qed.
(** ω is the smallest limit ordinal *)
Lemma omega_limit : limitOrdinal ω.
Proof.
simpl. split.
- exact (inhabits 0%nat).
- hnf; intros.
exists (S a); simpl; auto with ord.
Qed.
Lemma omega_least : forall x, limitOrdinal x -> ω <= x.
Proof.
intros.
destruct x as [A f]; simpl in *.
rewrite ord_le_unfold.
simpl; intro.
destruct H as [[q] H].
rewrite ord_lt_unfold; simpl.
induction a; simpl.
- exists q; auto with ord.
- destruct IHa as [r Hr].
destruct (H r) as [s Hs].
exists s.
apply succ_least.
apply ord_le_lt_trans with (f r); auto.
Qed.
Lemma natOrdSize_monotone : forall i j, (i<=j)%nat -> natOrdSize i <= natOrdSize j.
Proof.
intros i j H; induction H; simpl.
- reflexivity.
- rewrite IHle. apply ord_lt_le. apply succ_lt.
Qed.
Lemma natOrdSize_increasing m n :
(m < n)%nat -> natOrdSize m < natOrdSize n.
Proof.
intro H. induction H; simpl.
apply succ_lt.
transitivity (natOrdSize m0); auto with ord.
Qed.
Lemma succ_cancel_le x y :
succOrd x <= succOrd y -> x <= y.
Proof.
intros.
do 2 rewrite succ_unfold in H.
destruct (ord_le_subord _ _ H tt) as [??].
auto.
Qed.
Lemma succ_cancel_eq x y :
succOrd x ≈ succOrd y -> x ≈ y.
Proof.
intros; split; apply succ_cancel_le; apply H.
Qed.
Lemma natOrdSize_unique : forall m n,
natOrdSize m ≈ natOrdSize n -> m = n.
Proof.
induction m; destruct n; simpl; intros; auto.
- elim (ord_lt_irreflexive 0).
rewrite H at 2.
apply succ_trans; auto with ord.
- elim (ord_lt_irreflexive 0).
rewrite <- H at 2.
apply succ_trans; auto with ord.
- f_equal. apply IHm.
apply succ_cancel_eq; auto.
Qed.
Lemma omega_complete : complete ω.
Proof.
hnf; simpl; repeat split.
- intros a1 a2.
exists (Nat.max a1 a2); split; apply natOrdSize_monotone.
+ apply PeanoNat.Nat.le_max_l.
+ apply PeanoNat.Nat.le_max_r.
- left. exact (inhabits 0%nat).
- induction a.
+ apply zero_complete.
+ apply succ_complete; auto.
Qed.
Lemma omega_gt0 : 0 < ω.
Proof. apply (index_lt _ 0%nat). Qed.
Lemma omega_gt1 : 1 < ω.
Proof. apply (index_lt ω 1%nat). Qed.
(** Any zero ordinal is equal to the distinguished zeroOrd *)
Lemma ord_isZero z : zeroOrdinal z <-> z ≈ 0.
Proof.
split.
- intro. split; auto with ord.
destruct z as [Z f].
rewrite ord_le_unfold. intro a; elim H. exact (inhabits a).
- repeat intro.
destruct z as [Z f].
simpl. intros [a].
destruct H as [H1 H2].
rewrite ord_le_unfold in H1.
generalize (H1 a).
rewrite ord_lt_unfold.
simpl; intros [[] _].
Qed.
(** Any successor ordinal is equal to some application of succOrd. *)
Lemma ord_isSucc x : successorOrdinal x <-> exists o, x ≈ succOrd o.
Proof.
split.
- intros.
destruct x as [A f].
destruct H as [a Ha].
exists (f a).
split.
+ rewrite ord_le_unfold. simpl; intro a'.
apply ord_le_lt_trans with (f a); auto.
apply succ_lt.
+ apply succ_least.
apply (index_lt (ord A f)).
- intros [o Ho].
destruct Ho as [Ho1 Ho2].
destruct x as [A f].
simpl. hnf.
rewrite ord_le_unfold in Ho2.
specialize (Ho2 tt).
rewrite ord_lt_unfold in Ho2.
destruct Ho2 as [a Ha].
exists a. simpl in Ha.
intros.
rewrite ord_le_unfold in Ho1.
specialize (Ho1 a'). rewrite ord_lt_unfold in Ho1.
destruct Ho1 as [z Hz]. simpl in *.
transitivity o; auto.
Qed.
Lemma ord_isLimit : forall x,
limitOrdinal x <->
(x > 0 /\ (forall i, i < x -> exists j, i < j /\ j < x)).
Proof.
intros [X f].
split; simpl; intuition.
- rewrite ord_lt_unfold.
destruct H0 as [x]. exists x. auto with ord.
- rewrite ord_lt_unfold in H.
destruct H as [x ?].
destruct (H1 x) as [x' ?].
exists (f x').
split.
rewrite H; auto.
apply (index_lt (ord X f) x').
- rewrite ord_lt_unfold in H0.
destruct H0 as [x _].
exact (inhabits x).
- red; intros.
destruct (H1 (f a)) as [j [??]].
apply (index_lt (ord X f) a).
rewrite ord_lt_unfold in H2.
destruct H2 as [k ?].
exists k.
apply ord_lt_le_trans with j; auto.
Qed.
Lemma limit_boundedSup β : limitOrdinal β -> β ≈ boundedSup β (fun a => a).
Proof.
destruct β as [B g]; simpl.
intros [_ Hb].
rewrite <- ascending_sup_lim; auto.
reflexivity.
Qed.
Lemma limit_boundedSup' β :
0 < β ->
β ≈ boundedSup β (fun a => a) ->
limitOrdinal β.
Proof.
destruct β as [B g]; simpl.
intros H Heq ; split.
- rewrite ord_lt_unfold in H.
destruct H as [b ?].
exact (inhabits b).
- red. intro a.
destruct Heq as [Hle1 Hle2].
rewrite ord_le_unfold in Hle1.
generalize (Hle1 a).
simpl; intros.
rewrite ord_lt_unfold in H0.
destruct H0 as [a' ?]. simpl in *.
destruct a'. simpl in *.
exists x.
rewrite ord_lt_unfold. exists o. auto.
Qed.
Add Parametric Morphism : zeroOrdinal with signature
ord_eq ==> impl as zeroOrdinal_mor.
Proof.
repeat intro.
rewrite ord_isZero in H0.
rewrite ord_isZero.
rewrite <- H; auto.
Qed.
Add Parametric Morphism : successorOrdinal with signature
ord_eq ==> impl as succOrdinal_mor.
Proof.
repeat intro.
rewrite ord_isSucc in H0.
rewrite ord_isSucc.
destruct H0 as [o ?].
exists o.
rewrite <- H; auto.
Qed.
Add Parametric Morphism : limitOrdinal with signature
ord_eq ==> impl as limitOrdinal_mor.
Proof.
repeat intro.
rewrite ord_isLimit in H0.
rewrite ord_isLimit.
intuition.
rewrite <- H; auto.
destruct (H2 i) as [j [??]].
rewrite H; auto.
exists j; split; auto.
rewrite <- H; auto.
Qed.
Lemma pred_unfold x : predOrd x = supOrd (ordSize x).
Proof.
destruct x; reflexivity.
Qed.
(** pred(y) is the smallest ordinal that is (nonstrictly) above
* all the ordinals (strictly) below y.
*)
Lemma pred_le y :
forall x, x < y -> x ≤ predOrd y.
Proof.
intros.
destruct y as [B g]; simpl in *.
rewrite ord_lt_unfold in H.
destruct H as [b Hb]. simpl in *.
rewrite Hb.
apply sup_le.
Qed.
Lemma pred_least y z :
(forall x, x < y -> x ≤ z) ->
predOrd y ≤ z.
Proof.
intros.
destruct y as [B g]. simpl.
apply sup_least. intros.
apply H; auto with ord.
Qed.
Lemma pred_zero : 0 ≈ predOrd 0.
Proof.
split; auto with ord.
apply pred_least.
intros x H.
rewrite ord_lt_unfold in H.
destruct H as [[] _].
Qed.
Lemma pred_successor x : successorOrdinal x -> predOrd x < x.
Proof.
destruct x as [A f]; simpl; intros.
rewrite ord_lt_unfold.
red in H. simpl in *.
destruct H as [a Ha].
exists a. apply sup_least. auto.
Qed.
Lemma pred_limit x : limitOrdinal x -> x ≈ predOrd x.
Proof.
intros.
split.
- destruct x as [A f].
rewrite ord_le_unfold. simpl; intro a.
destruct H as [_ H].
destruct (H a) as [a' ?].
rewrite <- (sup_le _ _ a'). auto.
- apply pred_least.
apply ord_lt_le.
Qed.
Lemma pred_succ x : x ≈ predOrd (succOrd x).
Proof.
split.
- apply pred_le. apply succ_lt.
- apply pred_least. intros.
rewrite ord_lt_unfold in H. simpl in *.
destruct H. auto.
Qed.
Lemma succ_pred x : x ≤ succOrd (predOrd x).
Proof.
rewrite ord_le_unfold. intros.
rewrite ord_lt_unfold. simpl. exists tt.
apply pred_le; auto with ord.
Qed.
Lemma succ_pred' x : successorOrdinal x -> x ≈ succOrd (predOrd x).
Proof.
intros.
split.
- apply succ_pred.
- apply succ_least; apply pred_successor; auto.
Qed.
Add Parametric Morphism : predOrd with signature
ord_le ++> ord_le as pred_le_mor.
Proof.
intros.
apply pred_least. intros.
apply pred_le.
rewrite <- H.
auto.
Qed.
Add Parametric Morphism : predOrd with signature
ord_eq ==> ord_eq as pred_eq_mor.
Proof.
intros; split; apply pred_le_mor; apply H.
Qed.
Lemma glb_unfold x y :
x ⊓ y = ord (ordCarrier x * ordCarrier y)
(fun i => x (fst i) ⊓ y (snd i)).
Proof.
destruct x; destruct y; reflexivity.
Qed.
(** glb is the greatest lower bound of its arguments.
*)
Lemma glb_le1 : forall x y, x ⊓ y ≤ x.
Proof.
induction x as [A f Hx]. destruct y as [B g]. simpl.
rewrite ord_le_unfold; simpl.
intros [a b]; simpl.
rewrite ord_lt_unfold; simpl.
exists a. apply Hx.
Qed.
Lemma glb_le2 : forall y x, x ⊓ y ≤ y.
Proof.
induction y as [B g Hy]. destruct x as [A f]. simpl.
rewrite ord_le_unfold; simpl.
intros [a b]; simpl.
rewrite ord_lt_unfold; simpl.
exists b. apply Hy.
Qed.
Lemma glb_greatest : forall z x y, z ≤ x -> z ≤ y -> z ≤ x ⊓ y.
Proof.
induction z as [C h Hz]; simpl; intros.
rewrite ord_le_unfold; simpl; intro c.
rewrite ord_le_unfold in H.
rewrite ord_le_unfold in H0.
destruct x as [A f].
destruct y as [B g].
specialize (H c).
specialize (H0 c).
simpl.
rewrite ord_lt_unfold in H.
rewrite ord_lt_unfold in H0.
destruct H as [a Ha].
destruct H0 as [b Hb].
simpl in *.
rewrite ord_lt_unfold.
simpl.
exists (a,b). simpl.
apply Hz; auto.
Qed.
Lemma glb_complete : forall x y, complete x -> complete y -> complete (x ⊓ y).
Proof.
induction x as [X f Hx].
destruct y as [Y g].
simpl. intros [Hx1 [Hx2 Hx3]] [Hy1 [Hy2 Hy3]]; repeat split.
- intros [x1 y1] [x2 y2].
destruct (Hx1 x1 x2) as [x' [Hx'1 Hx'2]].
destruct (Hy1 y1 y2) as [y' [Hy'1 Hy'2]].
exists (x',y'). split; simpl.
+ apply glb_greatest.
* rewrite glb_le1. auto.
* rewrite glb_le2. auto.
+ apply glb_greatest.
* rewrite glb_le1. auto.
* rewrite glb_le2. auto.
- destruct Hx2 as [[x]|Hx2].
+ destruct Hy2 as [[y]|Hy2].
* left. exact (inhabits (x,y)).
* right; intros [[x' y']]; auto.
+ right; intros [[x' y']]; auto.
- intros [x y]. simpl.
apply Hx; auto.
Qed.
Add Parametric Morphism : glbOrd with signature
ord_le ++> ord_le ++> ord_le as ord_glb_le_mor.
Proof.
intros.
apply glb_greatest.
- rewrite <- H.
apply glb_le1.
- rewrite <- H0.
apply glb_le2.
Qed.
Add Parametric Morphism : glbOrd with signature
ord_eq ==> ord_eq ==> ord_eq as ord_glb_eq_mor.
Proof.
unfold ord_eq.
intros; split; apply ord_glb_le_mor; intuition.
Qed.
Lemma lub_unfold x y :
x ⊔ y = ord (ordCarrier x + ordCarrier y)
(fun xy => match xy with
| inl i => x i
| inr i => y i
end).
Proof.
destruct x; destruct y; reflexivity.
Qed.
(** lub is the least upper bound of its arguments.
*)
Lemma lub_le1 : forall x y, x ≤ x ⊔ y.
Proof.
intros. rewrite ord_le_unfold.
intros.
destruct x; destruct y; simpl.
rewrite ord_lt_unfold.
simpl.
exists (inl a).
apply ord_le_refl.
Qed.
Lemma lub_le2 : forall x y, y ≤ x ⊔ y.
Proof.
intros. rewrite ord_le_unfold.
destruct x; destruct y; simpl.
intros.
rewrite ord_lt_unfold.
exists (inr a).
apply ord_le_refl.
Qed.
Lemma lub_least x y z :
x ≤ z -> y ≤ z -> x ⊔ y ≤ z.
Proof.
repeat rewrite ord_le_unfold.
destruct x as [A f]; destruct y as [B g]; simpl; intros.
rewrite ord_lt_unfold.
destruct z as [C h]; simpl.
destruct a as [a|b].
- specialize (H a).
rewrite ord_lt_unfold in H.
destruct H as [c ?]. exists c.
simpl. auto.
- specialize (H0 b).
rewrite ord_lt_unfold in H0.
destruct H0 as [c ?].
exists c. simpl. auto.
Qed.
Lemma lub_lt a b c :
a < b ⊔ c -> a < b \/ a < c.
Proof.
rewrite ord_lt_unfold. unfold lubOrd. simpl.
intros [q ?].
destruct b as [B h].
destruct c as [C g]. simpl in *.
destruct q.
- left. rewrite ord_lt_unfold. eauto.
- right. rewrite ord_lt_unfold. eauto.
Qed.
(** lubOrd is a commutative, associative operator
*)
Lemma lub_le_comm : forall x y, x ⊔ y ≤ y ⊔ x.
Proof.
intros.
apply lub_least.
apply lub_le2.
apply lub_le1.
Qed.
Lemma lub_le_assoc1 : forall x y z,
x ⊔ (y ⊔ z) ≤ (x ⊔ y) ⊔ z.
Proof.
intros.
apply lub_least.
apply ord_le_trans with (lubOrd x y).
apply lub_le1.
apply lub_le1.
apply lub_least.
apply ord_le_trans with (lubOrd x y).
apply lub_le2.
apply lub_le1.
apply lub_le2.
Qed.
Lemma lub_le_assoc2 : forall x y z,
(x ⊔ y) ⊔ z ≤ x ⊔ (y ⊔ z).
Proof.
intros.
apply lub_least.
apply lub_least.
apply lub_le1.
apply ord_le_trans with (lubOrd y z).
apply lub_le1.
apply lub_le2.
apply ord_le_trans with (lubOrd y z).
apply lub_le2.
apply lub_le2.
Qed.
Lemma lubOrd_monotone a b c d :
a ≤ c -> b ≤ d -> a ⊔ b ≤ c ⊔ d.
Proof.
intros.
apply lub_least.
apply ord_le_trans with c; auto.
apply lub_le1.
apply ord_le_trans with d; auto.
apply lub_le2.
Qed.
Add Parametric Morphism : lubOrd with signature
ord_le ++> ord_le ++> ord_le as ord_lub_le_mor.
Proof.
intros.
apply lub_least.
- rewrite H.
apply lub_le1.
- rewrite H0.
apply lub_le2.
Qed.
Add Parametric Morphism : lubOrd with signature
ord_eq ==> ord_eq ==> ord_eq as ord_lub_eq_mor.
Proof.
unfold ord_eq.
intros; split; apply ord_lub_le_mor; intuition.
Qed.
Lemma lub_binary_sup a b :
a ⊔ b ≈ supOrd (fun i:bool => if i then a else b).
Proof.
split.
- apply lub_least.
+ rewrite <- (sup_le _ _ true).
reflexivity.
+ rewrite <- (sup_le _ _ false).
reflexivity.
- apply sup_least. intros [|].
+ apply lub_le1.
+ apply lub_le2.
Qed.
Lemma lub_continuous f a b :
(forall a b, a ≤ b -> f a ≤ f b) ->
strongly_continuous f ->
f (a ⊔ b) ≈ f a ⊔ f b.
Proof.
intros Hmono Hcont.
transitivity (f (supOrd (fun i:bool => if i then a else b))).
{ split; apply Hmono; apply lub_binary_sup. }
split.
- rewrite (Hcont bool (fun i => if i then a else b) false).
apply sup_least. intros [|].
+ apply lub_le1.
+ apply lub_le2.
- apply lub_least; apply Hmono.
+ rewrite <- (sup_le _ _ true); reflexivity.
+ rewrite <- (sup_le _ _ false); reflexivity.
Qed.
(** The lub of successors is <= the successor of the lub.
*)
Lemma succ_lub x y :
succOrd x ⊔ succOrd y ≤ succOrd (x ⊔ y).
Proof.
apply lub_least.
- apply succ_monotone.
apply lub_le1.
- apply succ_monotone.
apply lub_le2.
Qed.
Global Hint Unfold ordSize : ord.
Global Hint Resolve
limit_lt lub_le1 lub_le2
ord_lt_trans ord_le_trans ord_eq_trans
succ_trans
succ_trans'
lub_le1 lub_le2
ord_lt_le ord_le_refl ord_eq_refl : ord.
Lemma lub_complete1 : forall x y,
x >= y ->
complete x ->
complete y ->
complete (x ⊔ y).
Proof.
intros x y Hxy Hx Hy.
destruct x as [X f].
destruct y as [Y g].
simpl in *.
destruct Hx as [Hx1 [Hx2 Hx3]].
repeat split.
- intros [x1|y1].
+ intros [x2|y2].
* destruct (Hx1 x1 x2) as [x' [Hx'1 Hx'2]].
exists (inl x'); split; auto.
* destruct (ord_le_subord _ _ Hxy y2) as [x2 Hy2]. simpl in *.
destruct (Hx1 x1 x2) as [x' [Hx'1 Hx'2]].
exists (inl x'); split; auto.
transitivity (f x2); auto.
+ destruct (ord_le_subord _ _ Hxy y1) as [x1 Hy1]. simpl in *.
intros [x2|y2].
* destruct (Hx1 x1 x2) as [x' [Hx'1 Hx'2]].
exists (inl x'); split; auto.
transitivity (f x1); auto.
* destruct (ord_le_subord _ _ Hxy y2) as [x2 Hy2]. simpl in *.
destruct (Hx1 x1 x2) as [x' [Hx'1 Hx'2]].
exists (inl x'); split; auto.
transitivity (f x1); auto.
transitivity (f x2); auto.
- destruct Hx2 as [[x]|Hx2].
+ left. exact (inhabits (inl x)).
+ right. intros [[x|y]].
* apply Hx2. exact (inhabits x).
* apply Hx2.
destruct (ord_le_subord _ _ Hxy y) as [x _]. simpl in *.
exact (inhabits x).
- intros [x|y]; auto.
destruct Hy as [_ [_ Hy]].
apply Hy.
Qed.
Lemma lub_complete2 : forall x y,
x <= y ->
complete x ->
complete y ->
complete (x ⊔ y).
Proof.
intros x y Hxy Hx Hy.
destruct x as [X f].
destruct y as [Y g].
simpl in *.
destruct Hy as [Hy1 [Hy2 Hy3]].
repeat split.
- intros [x1|y1].
+ destruct (ord_le_subord _ _ Hxy x1) as [y1 Hx1]. simpl in *.
intros [x2|y2].
* destruct (ord_le_subord _ _ Hxy x2) as [y2 Hx2]. simpl in *.
destruct (Hy1 y1 y2) as [y' [Hy'1 Hy'2]].
exists (inr y'); split; auto.
transitivity (g y1); auto.
transitivity (g y2); auto.
* destruct (Hy1 y1 y2) as [y' [Hy'1 Hy'2]].
exists (inr y'); split; auto.
transitivity (g y1); auto.
+ intros [x2|y2].
* destruct (ord_le_subord _ _ Hxy x2) as [y2 Hx2]. simpl in *.
destruct (Hy1 y1 y2) as [y' [Hy'1 Hy'2]].
exists (inr y'); split; auto.
transitivity (g y2); auto.
* destruct (Hy1 y1 y2) as [y' [Hy'1 Hy'2]].
exists (inr y'); split; auto.
- destruct Hy2 as [[y]|Hy2].
+ left. exact (inhabits (inr y)).
+ right. intros [[x|y]].
* apply Hy2.
destruct (ord_le_subord _ _ Hxy x) as [y _]. simpl in *.
exact (inhabits y).
* apply Hy2.
exact (inhabits y).
- intros [x|y]; auto.
destruct Hx as [_ [_ Hx]]; apply Hx.
Qed.
Lemma lim_complete : forall A (f:A -> Ord),
(forall a, complete (f a)) ->
directed A f ->
(inhabited A \/ ~inhabited A) ->
complete (limOrd f).
Proof.
intros A f H1 H2 H3.
simpl. repeat split; auto.
Qed.
Lemma sup_complete : forall A (f:A -> Ord),
(forall a, complete (f a)) ->
directed A f ->
((exists a, 0 < f a) \/ (forall a, f a <= 0)) ->
complete (supOrd f).
Proof.
intros A f H1 H2 H3.
simpl. repeat split.
- intros [a1 q1] [a2 q2]. simpl.
destruct (H2 a1 a2) as [a' [Ha1 Ha2]].
destruct (ord_le_subord _ _ Ha1 q1) as [q1' Hq1].
destruct (ord_le_subord _ _ Ha2 q2) as [q2' Hq2].
destruct (complete_directed (f a') (H1 a') q1' q2') as [q' [Hq'1 Hq'2]].
exists (existT _ a' q'). simpl. split.
transitivity (f a' q1'); auto.
transitivity (f a' q2'); auto.
- destruct H3.
+ left. destruct H as [a Ha].
rewrite ord_lt_unfold in Ha.
destruct Ha as [q Hq].
exact (inhabits (existT _ a q)).
+ right. intros [[a q]].
destruct (ord_le_subord _ _ (H a) q) as [[] _].
- intros [a q]; simpl.
apply complete_subord; auto.
Qed.
Global Opaque lubOrd glbOrd supOrd.
|
// tb_top.v: top-level testbench for FM generator in Lattice iCE40-Ultra
// 2016-06-02 E. Brombaugh
module tb_rxadc;
// SPI slave port
reg SPI_CSL;
reg SPI_MOSI;
wire SPI_MISO;
reg SPI_SCLK;
// rxadc board interface
reg rxadc_clk;
wire rxadc_dfs;
reg rxadc_otr;
reg [9:0] rxadc_dat;
// DAC I2S output
wire dac_mclk;
wire dac_sdout;
wire dac_sclk;
wire dac_lrck;
// MCU I2S output
reg mcu_sdin;
wire mcu_sdout;
wire mcu_sclk;
wire mcu_lrck;
// RGB output
wire o_red;
wire o_green;
wire o_blue;
// ADC NCO source
real rxadc_phs;
// spi shift
reg [39:0] sr;
reg [31:0] read_data;
// spi transaction task
task spi_rxtx
(
input rw,
input [6:0] addr,
input [31:0] wdata
);
begin: spi_task
sr = {rw,addr,wdata};
SPI_CSL = 1'b0;
SPI_SCLK = 1'b0;
SPI_MOSI = sr[39];
repeat(40)
begin
#100
SPI_SCLK = 1'b1;
#100
SPI_SCLK = 1'b0;
sr = {sr[38:0],SPI_MISO};
SPI_MOSI = sr[39];
end
#100
SPI_CSL = 1'b1;
#100
read_data = sr[31:0];
end
endtask
rxadc
uut(
// SPI slave port
.SPI_CSL(SPI_CSL),
.SPI_MOSI(SPI_MOSI),
.SPI_MISO(SPI_MISO),
.SPI_SCLK(SPI_SCLK),
// rxadc board interface
.rxadc_clk(rxadc_clk),
.rxadc_dfs(rxadc_dfs),
.rxadc_otr(rxadc_otr),
.rxadc_dat(rxadc_dat),
// I2S DAC output
.dac_mclk(dac_mclk),
.dac_sdout(dac_sdout),
.dac_sclk(dac_sclk),
.dac_lrck(dac_lrck),
// I2S MCU interface
.mcu_sdin(mcu_sdin),
.mcu_sdout(mcu_sdout),
.mcu_sclk(mcu_sclk),
.mcu_lrck(mcu_lrck),
// RGB output
.o_red(o_red),
.o_green(o_green),
.o_blue(o_blue)
);
// test setup
initial
begin
// initial SPI setting
SPI_CSL = 1'b1;
SPI_MOSI = 1'b0;
SPI_SCLK = 1'b0;
// initialize RXADC
rxadc_clk = 1'b0;
rxadc_otr = 1'b0;
// initialize MCU SDIN
mcu_sdin = 1'b0;
// wait for chip to init
#4000
// read ID
spi_rxtx(1'b1, 7'd00, 32'd0);
// write params - assume the defaults are good
spi_rxtx(1'b0, 7'd1, 32'd1000); // cnt_reg
spi_rxtx(1'b0, 7'h10, 32'h00001000); // freq
spi_rxtx(1'b0, 7'h11, 32'd0); // DAC mux
spi_rxtx(1'b0, 7'd3, 32'd1); // trig
spi_rxtx(1'b0, 7'd3, 32'd0); // untrig
end
// ADC clock source
always
#12.5 rxadc_clk <= ~rxadc_clk;
// ADC data source
always @(posedge rxadc_clk)
begin
rxadc_phs <= rxadc_phs + 3*3.14159/64;
//rxadc_dat <= 10'd512 + 511*$sin(rxadc_phs);
rxadc_dat <= 10'd950;
end
endmodule
|
// megafunction wizard: %altmemphy v16.0%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// ram_controller_phy_alt_mem_phy
// ============================================================
// Generated by altmemphy 16.0 [Altera, IP Toolbench 1.3.0 Build 211]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ram_controller_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
ctl_doing_rd,
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dbg_rd_data,
dbg_waitrequest,
aux_half_rate_clk,
aux_full_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [1:0] ctl_dqs_burst;
input [1:0] ctl_wdata_valid;
input [31:0] ctl_wdata;
input [3:0] ctl_dm;
input [12:0] ctl_addr;
input [2:0] ctl_ba;
input [0:0] ctl_cas_n;
input [0:0] ctl_cke;
input [0:0] ctl_cs_n;
input [0:0] ctl_odt;
input [0:0] ctl_ras_n;
input [0:0] ctl_we_n;
input [0:0] ctl_rst_n;
input [0:0] ctl_mem_clk_disable;
input [1:0] ctl_doing_rd;
input ctl_cal_req;
input [1:0] ctl_cal_byte_lane_sel_n;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [31:0] ctl_rdata;
output [0:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [1:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output aux_half_rate_clk;
output aux_full_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [15:0] mem_dq;
inout [1:0] mem_dqs;
inout [1:0] mem_dqs_n;
ram_controller_phy_alt_mem_phy ram_controller_phy_alt_mem_phy_inst(
.pll_ref_clk(pll_ref_clk),
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n),
.ctl_dqs_burst(ctl_dqs_burst),
.ctl_wdata_valid(ctl_wdata_valid),
.ctl_wdata(ctl_wdata),
.ctl_dm(ctl_dm),
.ctl_addr(ctl_addr),
.ctl_ba(ctl_ba),
.ctl_cas_n(ctl_cas_n),
.ctl_cke(ctl_cke),
.ctl_cs_n(ctl_cs_n),
.ctl_odt(ctl_odt),
.ctl_ras_n(ctl_ras_n),
.ctl_we_n(ctl_we_n),
.ctl_rst_n(ctl_rst_n),
.ctl_mem_clk_disable(ctl_mem_clk_disable),
.ctl_doing_rd(ctl_doing_rd),
.ctl_cal_req(ctl_cal_req),
.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
.dbg_clk(dbg_clk),
.dbg_reset_n(dbg_reset_n),
.dbg_addr(dbg_addr),
.dbg_wr(dbg_wr),
.dbg_rd(dbg_rd),
.dbg_cs(dbg_cs),
.dbg_wr_data(dbg_wr_data),
.reset_request_n(reset_request_n),
.ctl_clk(ctl_clk),
.ctl_reset_n(ctl_reset_n),
.ctl_wlat(ctl_wlat),
.ctl_rdata(ctl_rdata),
.ctl_rdata_valid(ctl_rdata_valid),
.ctl_rlat(ctl_rlat),
.ctl_cal_success(ctl_cal_success),
.ctl_cal_fail(ctl_cal_fail),
.ctl_cal_warning(ctl_cal_warning),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.dbg_rd_data(dbg_rd_data),
.dbg_waitrequest(dbg_waitrequest),
.aux_half_rate_clk(aux_half_rate_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n));
defparam
ram_controller_phy_alt_mem_phy_inst.FAMILY = "Cyclone IV E",
ram_controller_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR2",
ram_controller_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
ram_controller_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
ram_controller_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
ram_controller_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
ram_controller_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
ram_controller_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
ram_controller_phy_alt_mem_phy_inst.DWIDTH_RATIO = 2,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 16,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 13,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 3,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 2,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 2,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 7519,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "7519 ps",
ram_controller_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 594,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 1092,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
ram_controller_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 64,
ram_controller_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
ram_controller_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
ram_controller_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
ram_controller_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
ram_controller_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;
endmodule
// =========================================================
// altmemphy Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="ALTMEMPHY" version="16.0" build="198" iptb_version="1.3.0 Build 211" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="ram_controller_phy_alt_mem_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="133.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="133.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(7519 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="Micron" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="Custom (Micron MT47H64M8CB-3)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="13" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="40.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="240" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="340" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="8.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="450" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="8.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="50" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="ram_controller_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="ram_controller_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+ram_controller_phy_alt_mem_phy_seq_wrapper;+ram_controller_phy_alt_mem_phy_reconfig;+ram_controller_phy_alt_mem_phy_pll;+ram_controller_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/home/caleb/Sources/Telescope_Project/VFPIX-telescope-Code/DAQ_Firmware/ram_controller_phy_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="ram_controller_phy_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP4CE55F23C8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
// IPFS_FILES: ram_controller_phy_alt_mem_phy_seq_wrapper.vo;
// =========================================================
|
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
`timescale 1ns/100ps
module
BFM_APB
(
SYSCLK
,
SYSRSTN
,
PCLK
,
PRESETN
,
PADDR
,
PENABLE
,
PWRITE
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
,
PSEL
,
INTERRUPT
,
GP_OUT
,
GP_IN
,
EXT_WR
,
EXT_RD
,
EXT_ADDR
,
EXT_DATA
,
EXT_WAIT
,
FINISHED
,
FAILED
)
;
parameter
VECTFILE
=
"test.vec"
;
parameter
MAX_INSTRUCTIONS
=
16384
;
parameter
MAX_STACK
=
1024
;
parameter
MAX_MEMTEST
=
65536
;
parameter
TPD
=
1
;
parameter
DEBUGLEVEL
=
-
1
;
parameter
ARGVALUE0
=
0
;
parameter
ARGVALUE1
=
0
;
parameter
ARGVALUE2
=
0
;
parameter
ARGVALUE3
=
0
;
parameter
ARGVALUE4
=
0
;
parameter
ARGVALUE5
=
0
;
parameter
ARGVALUE6
=
0
;
parameter
ARGVALUE7
=
0
;
parameter
ARGVALUE8
=
0
;
parameter
ARGVALUE9
=
0
;
parameter
ARGVALUE10
=
0
;
parameter
ARGVALUE11
=
0
;
parameter
ARGVALUE12
=
0
;
parameter
ARGVALUE13
=
0
;
parameter
ARGVALUE14
=
0
;
parameter
ARGVALUE15
=
0
;
parameter
ARGVALUE16
=
0
;
parameter
ARGVALUE17
=
0
;
parameter
ARGVALUE18
=
0
;
parameter
ARGVALUE19
=
0
;
parameter
ARGVALUE20
=
0
;
parameter
ARGVALUE21
=
0
;
parameter
ARGVALUE22
=
0
;
parameter
ARGVALUE23
=
0
;
parameter
ARGVALUE24
=
0
;
parameter
ARGVALUE25
=
0
;
parameter
ARGVALUE26
=
0
;
parameter
ARGVALUE27
=
0
;
parameter
ARGVALUE28
=
0
;
parameter
ARGVALUE29
=
0
;
parameter
ARGVALUE30
=
0
;
parameter
ARGVALUE31
=
0
;
parameter
ARGVALUE32
=
0
;
parameter
ARGVALUE33
=
0
;
parameter
ARGVALUE34
=
0
;
parameter
ARGVALUE35
=
0
;
parameter
ARGVALUE36
=
0
;
parameter
ARGVALUE37
=
0
;
parameter
ARGVALUE38
=
0
;
parameter
ARGVALUE39
=
0
;
parameter
ARGVALUE40
=
0
;
parameter
ARGVALUE41
=
0
;
parameter
ARGVALUE42
=
0
;
parameter
ARGVALUE43
=
0
;
parameter
ARGVALUE44
=
0
;
parameter
ARGVALUE45
=
0
;
parameter
ARGVALUE46
=
0
;
parameter
ARGVALUE47
=
0
;
parameter
ARGVALUE48
=
0
;
parameter
ARGVALUE49
=
0
;
parameter
ARGVALUE50
=
0
;
parameter
ARGVALUE51
=
0
;
parameter
ARGVALUE52
=
0
;
parameter
ARGVALUE53
=
0
;
parameter
ARGVALUE54
=
0
;
parameter
ARGVALUE55
=
0
;
parameter
ARGVALUE56
=
0
;
parameter
ARGVALUE57
=
0
;
parameter
ARGVALUE58
=
0
;
parameter
ARGVALUE59
=
0
;
parameter
ARGVALUE60
=
0
;
parameter
ARGVALUE61
=
0
;
parameter
ARGVALUE62
=
0
;
parameter
ARGVALUE63
=
0
;
parameter
ARGVALUE64
=
0
;
parameter
ARGVALUE65
=
0
;
parameter
ARGVALUE66
=
0
;
parameter
ARGVALUE67
=
0
;
parameter
ARGVALUE68
=
0
;
parameter
ARGVALUE69
=
0
;
parameter
ARGVALUE70
=
0
;
parameter
ARGVALUE71
=
0
;
parameter
ARGVALUE72
=
0
;
parameter
ARGVALUE73
=
0
;
parameter
ARGVALUE74
=
0
;
parameter
ARGVALUE75
=
0
;
parameter
ARGVALUE76
=
0
;
parameter
ARGVALUE77
=
0
;
parameter
ARGVALUE78
=
0
;
parameter
ARGVALUE79
=
0
;
parameter
ARGVALUE80
=
0
;
parameter
ARGVALUE81
=
0
;
parameter
ARGVALUE82
=
0
;
parameter
ARGVALUE83
=
0
;
parameter
ARGVALUE84
=
0
;
parameter
ARGVALUE85
=
0
;
parameter
ARGVALUE86
=
0
;
parameter
ARGVALUE87
=
0
;
parameter
ARGVALUE88
=
0
;
parameter
ARGVALUE89
=
0
;
parameter
ARGVALUE90
=
0
;
parameter
ARGVALUE91
=
0
;
parameter
ARGVALUE92
=
0
;
parameter
ARGVALUE93
=
0
;
parameter
ARGVALUE94
=
0
;
parameter
ARGVALUE95
=
0
;
parameter
ARGVALUE96
=
0
;
parameter
ARGVALUE97
=
0
;
parameter
ARGVALUE98
=
0
;
parameter
ARGVALUE99
=
0
;
localparam
OPMODE
=
0
;
localparam
CON_SPULSE
=
0
;
input
SYSCLK
;
input
SYSRSTN
;
output
PCLK
;
wire
PCLK
;
output
PRESETN
;
wire
PRESETN
;
output
[
31
:
0
]
PADDR
;
wire
[
31
:
0
]
PADDR
;
output
PENABLE
;
wire
PENABLE
;
output
PWRITE
;
wire
PWRITE
;
output
[
31
:
0
]
PWDATA
;
wire
[
31
:
0
]
PWDATA
;
input
[
31
:
0
]
PRDATA
;
input
PREADY
;
input
PSLVERR
;
output
[
15
:
0
]
PSEL
;
wire
[
15
:
0
]
PSEL
;
input
[
255
:
0
]
INTERRUPT
;
output
[
31
:
0
]
GP_OUT
;
wire
[
31
:
0
]
GP_OUT
;
input
[
31
:
0
]
GP_IN
;
output
EXT_WR
;
wire
EXT_WR
;
output
EXT_RD
;
wire
EXT_RD
;
output
[
31
:
0
]
EXT_ADDR
;
wire
[
31
:
0
]
EXT_ADDR
;
inout
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
BFMA1O1OII
;
input
EXT_WAIT
;
output
FINISHED
;
wire
FINISHED
;
output
FAILED
;
wire
FAILED
;
wire
BFMA1l0lII
;
wire
BFMA1O1lII
;
wire
BFMA1I1lII
;
wire
[
31
:
0
]
BFMA1l1lII
;
wire
[
2
:
0
]
BFMA1OO0II
;
wire
BFMA1IO0II
;
wire
[
3
:
0
]
BFMA1lO0II
;
wire
[
2
:
0
]
BFMA1OI0II
;
wire
[
1
:
0
]
BFMA1II0II
;
wire
BFMA1lI0II
;
wire
[
31
:
0
]
BFMA1Ol0II
;
wire
[
31
:
0
]
BFMA1Il0II
;
wire
BFMA1ll0II
;
wire
BFMA1O00II
;
wire
BFMA1I00II
;
wire
BFMA1l00II
;
wire
[
15
:
0
]
BFMA1O10II
;
wire
[
31
:
0
]
INSTR_IN
=
{
32
{
1
'b
0
}
}
;
assign
EXT_DATA
=
BFMA1O1OII
;
BFM_MAIN
#
(
OPMODE
,
VECTFILE
,
MAX_INSTRUCTIONS
,
MAX_STACK
,
MAX_MEMTEST
,
TPD
,
DEBUGLEVEL
,
CON_SPULSE
,
ARGVALUE0
,
ARGVALUE1
,
ARGVALUE2
,
ARGVALUE3
,
ARGVALUE4
,
ARGVALUE5
,
ARGVALUE6
,
ARGVALUE7
,
ARGVALUE8
,
ARGVALUE9
,
ARGVALUE10
,
ARGVALUE11
,
ARGVALUE12
,
ARGVALUE13
,
ARGVALUE14
,
ARGVALUE15
,
ARGVALUE16
,
ARGVALUE17
,
ARGVALUE18
,
ARGVALUE19
,
ARGVALUE20
,
ARGVALUE21
,
ARGVALUE22
,
ARGVALUE23
,
ARGVALUE24
,
ARGVALUE25
,
ARGVALUE26
,
ARGVALUE27
,
ARGVALUE28
,
ARGVALUE29
,
ARGVALUE30
,
ARGVALUE31
,
ARGVALUE32
,
ARGVALUE33
,
ARGVALUE34
,
ARGVALUE35
,
ARGVALUE36
,
ARGVALUE37
,
ARGVALUE38
,
ARGVALUE39
,
ARGVALUE40
,
ARGVALUE41
,
ARGVALUE42
,
ARGVALUE43
,
ARGVALUE44
,
ARGVALUE45
,
ARGVALUE46
,
ARGVALUE47
,
ARGVALUE48
,
ARGVALUE49
,
ARGVALUE50
,
ARGVALUE51
,
ARGVALUE52
,
ARGVALUE53
,
ARGVALUE54
,
ARGVALUE55
,
ARGVALUE56
,
ARGVALUE57
,
ARGVALUE58
,
ARGVALUE59
,
ARGVALUE60
,
ARGVALUE61
,
ARGVALUE62
,
ARGVALUE63
,
ARGVALUE64
,
ARGVALUE65
,
ARGVALUE66
,
ARGVALUE67
,
ARGVALUE68
,
ARGVALUE69
,
ARGVALUE70
,
ARGVALUE71
,
ARGVALUE72
,
ARGVALUE73
,
ARGVALUE74
,
ARGVALUE75
,
ARGVALUE76
,
ARGVALUE77
,
ARGVALUE78
,
ARGVALUE79
,
ARGVALUE80
,
ARGVALUE81
,
ARGVALUE82
,
ARGVALUE83
,
ARGVALUE84
,
ARGVALUE85
,
ARGVALUE86
,
ARGVALUE87
,
ARGVALUE88
,
ARGVALUE89
,
ARGVALUE90
,
ARGVALUE91
,
ARGVALUE92
,
ARGVALUE93
,
ARGVALUE94
,
ARGVALUE95
,
ARGVALUE96
,
ARGVALUE97
,
ARGVALUE98
,
ARGVALUE99
)
BFMA1I1OII
(
.SYSCLK
(
SYSCLK
)
,
.SYSRSTN
(
SYSRSTN
)
,
.HADDR
(
BFMA1l1lII
)
,
.HCLK
(
BFMA1O1lII
)
,
.PCLK
(
BFMA1l0lII
)
,
.HRESETN
(
BFMA1I1lII
)
,
.HBURST
(
BFMA1OO0II
)
,
.HMASTLOCK
(
BFMA1IO0II
)
,
.HPROT
(
BFMA1lO0II
)
,
.HSIZE
(
BFMA1OI0II
)
,
.HTRANS
(
BFMA1II0II
)
,
.HWRITE
(
BFMA1lI0II
)
,
.HWDATA
(
BFMA1Il0II
)
,
.HRDATA
(
BFMA1Ol0II
)
,
.HREADY
(
BFMA1ll0II
)
,
.HRESP
(
BFMA1l00II
)
,
.HSEL
(
BFMA1O10II
)
,
.INTERRUPT
(
INTERRUPT
)
,
.GP_OUT
(
GP_OUT
)
,
.GP_IN
(
GP_IN
)
,
.EXT_WR
(
EXT_WR
)
,
.EXT_RD
(
EXT_RD
)
,
.EXT_ADDR
(
EXT_ADDR
)
,
.EXT_DATA
(
EXT_DATA
)
,
.EXT_WAIT
(
EXT_WAIT
)
,
.CON_ADDR
(
16
'b
0
)
,
.CON_DATA
(
)
,
.CON_RD
(
1
'b
0
)
,
.CON_WR
(
1
'b
0
)
,
.CON_BUSY
(
)
,
.INSTR_OUT
(
)
,
.INSTR_IN
(
INSTR_IN
)
,
.FINISHED
(
FINISHED
)
,
.FAILED
(
FAILED
)
)
;
assign
PCLK
=
BFMA1l0lII
;
assign
PRESETN
=
BFMA1I1lII
;
BFMA1l1OII
#
(
TPD
)
BFMA1lO1II
(
.HCLK
(
BFMA1O1lII
)
,
.HRESETN
(
BFMA1I1lII
)
,
.HSEL
(
1
'b
1
)
,
.HWRITE
(
BFMA1lI0II
)
,
.HADDR
(
BFMA1l1lII
)
,
.HWDATA
(
BFMA1Il0II
)
,
.HRDATA
(
BFMA1Ol0II
)
,
.HREADYIN
(
BFMA1ll0II
)
,
.HREADYOUT
(
BFMA1ll0II
)
,
.HTRANS
(
BFMA1II0II
)
,
.HSIZE
(
BFMA1OI0II
)
,
.HBURST
(
BFMA1OO0II
)
,
.HMASTLOCK
(
BFMA1IO0II
)
,
.HPROT
(
BFMA1lO0II
)
,
.HRESP
(
BFMA1l00II
)
,
.PSEL
(
PSEL
)
,
.PADDR
(
PADDR
)
,
.PWRITE
(
PWRITE
)
,
.PENABLE
(
PENABLE
)
,
.PWDATA
(
PWDATA
)
,
.PRDATA
(
PRDATA
)
,
.PREADY
(
PREADY
)
,
.PSLVERR
(
PSLVERR
)
)
;
endmodule
|
`ifndef _MEM_ACCESS
`define _MEM_ACCESS
`include "../misc/mux.v"
`include "../misc/plus_one.v"
`include "../memory/data_mem.v"
module mem_access(IRfrompipe4, IRfrompipe5, RAFromPipe, ALUOut, RAMemSelectInput, wASelectInput, MemData, DataInSelect, WriteMem, RAFromPipeInc, SignalC
, Rfout1, Rfout2, mem_wb_CCR_write, ex_mem_CCR_write);
output [15:0] MemData, RAFromPipeInc;
wire [15:0] DataIn;
input [15:0] ALUOut, RAFromPipe, Rfout1, Rfout2, SignalC, , IRfrompipe5, IRfrompipe4;
input RAMemSelectInput, wASelectInput, WriteMem, DataInSelect, mem_wb_CCR_write, ex_mem_CCR_write;
wire [15:0] readAddSelected, writeAddSelected, DataInSelected;
mux16x2 RASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(RAMemSelectInput), .out(readAddSelected));
mux16x2 WASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(WAMemSelectInput), .out(writeAddSelected));
mux16x4 DataSelect2(.data0(DataInSelected), .data1(SignalB), .data2(SignalC), .data3(16'b0), .SelectInput(F3), .out(DataIn));
mux16x2 DataSelect1(.data0(Rfout1), .data1(Rfout2), .selectInput(DataInSelect), .out(DataInSelected));
data_mem DataMemory(.readAdd(readAddSelected), .out(MemData), .writeAdd(writeAddSelected), .in(DataIn), .write(WriteMem));
plus_one Inc(.in(RAFromPipe), .out(RAFromPipeInc));
forward_mem_stage(.mem_wb_op(IRfrompipe5[15:12]), .mem_wb_regA(IRfrompipe5[11:9]), .mem_wb_regC(IRfrompipe5[5:3]), .ex_mem_op(IRfrompipe4[15:12]),
.ex_mem_regA(IRfrompipe4[11:9]), .F3(F3) ,mem_wb_CCR_write(mem_wb_CCR_write), .ex_mem_CCR_write(ex_mem_CCR_write));
endmodule
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd1;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd2;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2017 05:12:24 PM
// Design Name:
// Module Name: frequency_analyzer_manager
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_analyzer_manager #
(
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 10,
parameter integer PIXEL0_INDEX = 63,
parameter integer PIXEL1_INDEX = 511,
parameter integer PIXEL2_INDEX = 1023,
parameter integer PIXEL0_FREQUENCY0 = 5000,
parameter integer PIXEL0_FREQUENCY1 = 10000,
parameter integer PIXEL1_FREQUENCY0 = 15000,
parameter integer PIXEL1_FREQUENCY1 = 20000,
parameter integer PIXEL2_FREQUENCY0 = 25000,
parameter integer PIXEL2_FREQUENCY1 = 30000,
parameter integer FREQUENCY_DEVIATION = 20,
parameter integer CLOCK_FREQUENCY = 100000000
)
(
input wire [7:0] data,
input wire pixel_clock,
input wire start,
input wire stop,
input wire clear,
output wire irq,
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
localparam integer REGISTERS_NUMBER = 6;
// frequency analyzer data
reg pixel0_sample_data;
reg pixel1_sample_data;
reg pixel2_sample_data;
reg [9:0] pixel0_counter;
reg [9:0] pixel1_counter;
reg [9:0] pixel2_counter;
wire enable;
// axi register access
wire[31:0] register_write;
wire[1:0] register_operation;
wire[7:0] register_number;
wire[31:0] register_read;
reg write_completed;
wire [31:0] pixel0_f0_action_time_net;
wire [31:0] pixel0_f1_action_time_net;
wire [31:0] pixel1_f0_action_time_net;
wire [31:0] pixel1_f1_action_time_net;
wire [31:0] pixel2_f0_action_time_net;
wire [31:0] pixel2_f1_action_time_net;
supply1 vcc;
reg[31:0] register_write_value;
reg[1:0] register_operation_value;
reg[7:0] register_number_value;
reg[1:0] hold;
wire clear_impl;
assign register_write = register_write_value;
assign register_operation = register_operation_value;
assign register_number = register_number_value;
assign clear_impl = s00_axi_aresetn & ~write_completed & ~clear;
// enable generator
FDCE #(.INIT(0)) enable_generator(.C(start), .CE(s00_axi_aresetn), .D(vcc), .Q(enable), .CLR(stop));
//todo: umv: set proper frequencies
frequency_analyzer #(
.FREQUENCY0(PIXEL0_FREQUENCY0),
.FREQUENCY1(PIXEL0_FREQUENCY1),
.FREQUENCY0_DEVIATION(FREQUENCY_DEVIATION),
.FREQUENCY1_DEVIATION(FREQUENCY_DEVIATION),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY))
pixel0_analyzer(
.sample_data(pixel0_sample_data),
.clock(s00_axi_aclk),
.enable(enable),
.clear(clear_impl),
.f0_value(pixel0_f0_action_time_net),
.f1_value(pixel0_f1_action_time_net));
frequency_analyzer #(
.FREQUENCY0(PIXEL1_FREQUENCY0),
.FREQUENCY1(PIXEL1_FREQUENCY1),
.FREQUENCY0_DEVIATION(FREQUENCY_DEVIATION),
.FREQUENCY1_DEVIATION(FREQUENCY_DEVIATION),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY))
pixel1_analyzer(
.sample_data(pixel1_sample_data),
.clock(s00_axi_aclk),
.enable(enable),
.clear(clear_impl),
.f0_value(pixel1_f0_action_time_net),
.f1_value(pixel1_f1_action_time_net));
frequency_analyzer #(
.FREQUENCY0(PIXEL2_FREQUENCY0),
.FREQUENCY1(PIXEL2_FREQUENCY1),
.FREQUENCY0_DEVIATION(FREQUENCY_DEVIATION),
.FREQUENCY1_DEVIATION(FREQUENCY_DEVIATION),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY))
pixel2_analyzer(
.sample_data(pixel2_sample_data),
.clock(s00_axi_aclk),
.enable(enable),
.clear(clear_impl),
.f0_value(pixel2_f0_action_time_net),
.f1_value(pixel2_f1_action_time_net));
assign irq = write_completed;
// Instantiation of Axi Bus Interface S00_AXI
axi_slave_impl #
(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.NUMBER_OF_REGISTERS(REGISTERS_NUMBER)
)
frequency_analyzer_manager_axi
(
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.register_operation(register_operation),
.register_number(register_number),
.register_read(register_read),
.register_write(register_write)
);
always @(posedge pixel_clock)
begin
if(~enable)
begin
pixel0_sample_data <= 0;
pixel0_counter <= 0;
end
else
begin
if(pixel0_counter == PIXEL0_INDEX)
pixel0_sample_data <= data[7] & data[6];
pixel0_counter <= pixel0_counter + 1;
end
end
always @(posedge pixel_clock)
begin
if(~enable)
begin
pixel1_sample_data <= 0;
pixel1_counter <= 0;
end
else
begin
if(pixel1_counter == PIXEL1_INDEX)
pixel1_sample_data <= data[7] & data[6];
pixel1_counter <= pixel1_counter + 1;
end
end
always @(posedge pixel_clock)
begin
if(~enable)
begin
pixel2_sample_data <= 0;
pixel2_counter <= 0;
end
else
begin
if(pixel2_counter == PIXEL2_INDEX)
pixel2_sample_data <= data[7] & data[6];
pixel2_counter <= pixel2_counter + 1;
end
end
always @(posedge s00_axi_aclk)
begin
if(~s00_axi_aresetn)
begin
write_completed = 0;
register_number_value = 0;
hold = 0;
end
else
begin
if(stop)
begin
if(~write_completed)
begin
if(hold == 0)
begin
register_number_value = register_number_value + 1;
if(register_number_value > 0 && register_number_value <= REGISTERS_NUMBER)
begin
register_operation_value = 2;//`REGISTER_WRITE_OPERATION;
register_write_value = get_frequency(register_number_value);//200 + register_number;
end
if(register_number_value == REGISTERS_NUMBER + 1)
write_completed = 1;
end
hold = hold + 1;
end
else
begin
register_operation_value = 0;
register_number_value = 0;
register_write_value = 0;
end
end
else //if(!stop)
begin
register_operation_value = 0;
register_number_value = 0;
register_write_value = 0;
write_completed = 0;
hold = 0;
end
end
end
function [31:0] get_frequency(input reg[2:0] index);
case (index)
1: get_frequency = pixel0_f0_action_time_net;
2: get_frequency = pixel0_f1_action_time_net;
3: get_frequency = pixel1_f0_action_time_net;
4: get_frequency = pixel1_f1_action_time_net;
5: get_frequency = pixel2_f0_action_time_net;
6: get_frequency = pixel2_f1_action_time_net;
default: get_frequency = 0;
endcase
endfunction
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
pf_hi_tester s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_SYMBOL_V
`define SKY130_FD_SC_LP__NOR4_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
|
/****************************************
MIST1032SA - Core
****************************************/
`default_nettype none
module core #(
parameter CORE_ID = 32'h0
)(
/****************************************
System
****************************************/
input wire iCLOCK,
input wire inRESET,
/****************************************
Core
****************************************/
//oCORE_FLASH,
output wire oFREE_TLB_FLUSH,
/****************************************
GCI Controll
****************************************/
//Interrupt Controll
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
/****************************************
Instruction Memory
****************************************/
//Req
output wire oINST_REQ,
input wire iINST_LOCK,
output wire [1:0] oINST_MMUMOD,
output wire [31:0] oINST_PDT,
output wire [31:0] oINST_ADDR,
//RAM -> This
input wire iINST_VALID,
output wire oINST_BUSY,
input wire iINST_PAGEFAULT,
input wire iINST_QUEUE_FLUSH,
input wire [63:0] iINST_DATA,
input wire [27:0] iINST_MMU_FLAGS,
/****************************************
Data Memory
****************************************/
//Req
output wire oDATA_REQ,
input wire iDATA_LOCK,
output wire [1:0] oDATA_ORDER,
output wire [3:0] oDATA_MASK,
output wire oDATA_RW, //0=Write 1=Read
output wire [13:0] oDATA_TID,
output wire [1:0] oDATA_MMUMOD,
output wire [31:0] oDATA_PDT,
output wire [31:0] oDATA_ADDR,
//This -> Data RAM
output wire [31:0] oDATA_DATA,
//Data RAM -> This
input wire iDATA_VALID,
input wire iDATA_PAGEFAULT,
input wire [63:0] iDATA_DATA,
input wire [27:0] iDATA_MMU_FLAGS,
/****************************************
IO
****************************************/
//Req
output wire oIO_REQ,
input wire iIO_BUSY,
output wire [1:0] oIO_ORDER,
output wire oIO_RW, //0=Write 1=Read
output wire [31:0] oIO_ADDR,
//Write
output wire [31:0] oIO_DATA,
//Rec
input wire iIO_VALID,
input wire [31:0] iIO_DATA,
/****************************************
Interrupt
****************************************/
input wire iINTERRUPT_VALID,
output wire oINTERRUPT_ACK,
input wire [5:0] iINTERRUPT_NUM,
/****************************************
System Infomation
****************************************/
input wire iSYSINFO_IOSR_VALID,
input wire [31:0] iSYSINFO_IOSR
);
/************************************************************************************
Core - Main Pipeline
************************************************************************************/
core_pipeline #(CORE_ID) CORE_PIPELINE(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Core
.oFREE_TLB_FLUSH(oFREE_TLB_FLUSH),
//GCI Interrupt Controll
//Interrupt Control
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
//Instruction Memory Request
.oINST_FETCH_REQ(oINST_REQ),
.iINST_FETCH_BUSY(iINST_LOCK),
.oINST_FETCH_MMUMOD(oINST_MMUMOD),
.oINST_FETCH_PDT(oINST_PDT),
.oINST_FETCH_ADDR(oINST_ADDR),
.iINST_VALID(iINST_VALID),
.oINST_BUSY(oINST_BUSY),
.iINST_PAGEFAULT(iINST_PAGEFAULT),
.iINST_QUEUE_FLUSH(iINST_QUEUE_FLUSH),
.iINST_DATA(iINST_DATA),
.iINST_MMU_FLAGS(iINST_MMU_FLAGS),
/****************************************
Data Memory
****************************************/
//Req
.oDATA_REQ(oDATA_REQ),
.iDATA_LOCK(iDATA_LOCK),
.oDATA_ORDER(oDATA_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oDATA_MASK(oDATA_MASK),
.oDATA_RW(oDATA_RW), //1=Write 0=Read
.oDATA_TID(oDATA_TID),
.oDATA_MMUMOD(oDATA_MMUMOD),
.oDATA_PDT(oDATA_PDT),
.oDATA_ADDR(oDATA_ADDR),
//This -> Data RAM
.oDATA_DATA(oDATA_DATA),
//Data RAM -> This
.iDATA_VALID(iDATA_VALID),
.iDATA_PAGEFAULT(iDATA_PAGEFAULT),
.iDATA_DATA(iDATA_DATA),
.iDATA_MMU_FLAGS(iDATA_MMU_FLAGS),
/****************************************
IO
****************************************/
//Req
.oIO_REQ(oIO_REQ),
.iIO_BUSY(iIO_BUSY),
.oIO_ORDER(oIO_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oIO_RW(oIO_RW), //0=Write 1=Read
.oIO_ADDR(oIO_ADDR),
//Write
.oIO_DATA(oIO_DATA),
//Rec
.iIO_VALID(iIO_VALID),
.iIO_DATA(iIO_DATA),
//Interrupt
.iINTERRUPT_VALID(iINTERRUPT_VALID),
.oINTERRUPT_ACK(oINTERRUPT_ACK),
.iINTERRUPT_NUM(iINTERRUPT_NUM),
.iSYSINFO_IOSR_VALID(iSYSINFO_IOSR_VALID),
.iSYSINFO_IOSR(iSYSINFO_IOSR)
);
endmodule
`default_nettype wire
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.3
// \ \ Application : xaw2verilog
// / / Filename : clk_blk.v
// /___/ /\ Timestamp : 04/07/2011 11:02:43
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle X:/DSD/pipelined_cpu/clk_blk/clk_blk.xaw -st clk_blk.v
//Design Name: clk_blk
//Device: xc3s500e-4fg320
//
// Module clk_blk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module clk_blk(CLKIN_IN,
RST_IN,
CLK0_OUT,
CLK180_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLK0_OUT;
output CLK180_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK180_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLK0_OUT = CLKFB_IN;
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
.O(CLK180_OUT));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(CLK180_BUF),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "var11_multi.v:2" *)
module var11_multi(A, B, C, D, E, F, G, H, I, J, K, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
(* src = "var11_multi.v:3" *)
input A;
(* src = "var11_multi.v:3" *)
input B;
(* src = "var11_multi.v:3" *)
input C;
(* src = "var11_multi.v:3" *)
input D;
(* src = "var11_multi.v:3" *)
input E;
(* src = "var11_multi.v:3" *)
input F;
(* src = "var11_multi.v:3" *)
input G;
(* src = "var11_multi.v:3" *)
input H;
(* src = "var11_multi.v:3" *)
input I;
(* src = "var11_multi.v:3" *)
input J;
(* src = "var11_multi.v:3" *)
input K;
(* src = "var11_multi.v:9" *)
wire [7:0] total_value;
(* src = "var11_multi.v:4" *)
output valid;
assign _030_ = ~(E & G);
assign _041_ = ~F;
assign _052_ = D & A;
assign _063_ = ~(D | A);
assign _074_ = ~(_063_ | _052_);
assign _085_ = _074_ ^ _041_;
assign _096_ = ~(_085_ | _030_);
assign _107_ = _074_ | _041_;
assign _118_ = ~E;
assign _129_ = _052_ ^ B;
assign _140_ = _129_ ^ _118_;
assign _151_ = _140_ ^ _107_;
assign _160_ = ~(_151_ ^ _096_);
assign _161_ = ~(_085_ ^ _030_);
assign _162_ = ~(E ^ G);
assign _163_ = _162_ & H;
assign _164_ = _163_ & _161_;
assign _165_ = _164_ ^ _160_;
assign _166_ = ~I;
assign _167_ = ~(_162_ | H);
assign _168_ = ~(_167_ | _163_);
assign _169_ = _168_ & _161_;
assign _170_ = _169_ | _166_;
assign _171_ = ~(_170_ | _165_);
assign _172_ = ~H;
assign _173_ = _162_ & _161_;
assign _174_ = ~((_173_ & _160_) | _172_);
assign _175_ = _151_ & _096_;
assign _176_ = ~(_129_ & E);
assign _177_ = ~(E & D);
assign _178_ = B & A;
assign _179_ = ~(B | A);
assign _180_ = _179_ | _178_;
assign _181_ = ~(_180_ | _177_);
assign _182_ = ~D;
assign _183_ = _178_ | _182_;
assign _184_ = ~((_183_ & _176_) | _181_);
assign _185_ = ~_074_;
assign _186_ = ~((_140_ & _185_) | _041_);
assign _187_ = _186_ ^ _184_;
assign _188_ = _187_ ^ G;
assign _189_ = _188_ ^ _175_;
assign _190_ = _189_ ^ _174_;
assign _191_ = _190_ ^ _171_;
assign _192_ = ~J;
assign _193_ = _168_ ^ I;
assign _194_ = ~(_170_ ^ _165_);
assign _195_ = ~(_167_ | _166_);
assign _196_ = ~(_195_ | _163_);
assign _197_ = ~(_196_ ^ _161_);
assign _198_ = _197_ & _194_;
assign _199_ = ~((_198_ & _193_) | _192_);
assign _200_ = ~(_199_ & _191_);
assign _201_ = _187_ & G;
assign _202_ = _188_ & _175_;
assign _203_ = _202_ | _201_;
assign _204_ = ~(_186_ & _184_);
assign _205_ = ~((_178_ & D) | _181_);
assign _206_ = ~(_205_ & _204_);
assign _207_ = ~(_206_ ^ _203_);
assign _208_ = _189_ & _174_;
assign _209_ = ~((_190_ & _171_) | _208_);
assign _210_ = ~(_209_ ^ _207_);
assign _211_ = ~(_210_ ^ _200_);
assign _212_ = ~K;
assign _213_ = ~(_199_ ^ _191_);
assign _214_ = _193_ & J;
assign _215_ = ~(_193_ | J);
assign _216_ = ~(_215_ | _214_);
assign _217_ = _216_ & _198_;
assign _218_ = _217_ & _213_;
assign _219_ = _218_ | _212_;
assign _220_ = _217_ & K;
assign _221_ = _220_ ^ _213_;
assign _222_ = ~(_215_ | _212_);
assign _223_ = ~((_222_ | _214_) & _197_);
assign _224_ = _193_ & K;
assign _225_ = _224_ | _197_;
assign _226_ = _194_ ? _223_ : _225_;
assign _227_ = _226_ & _221_;
assign _228_ = ~((_219_ | _211_) & _227_);
assign _229_ = ~(_210_ | _200_);
assign _230_ = ~(_190_ & _171_);
assign _231_ = _206_ & _203_;
assign _232_ = _206_ | _203_;
assign _233_ = ~((_231_ | _208_) & _232_);
assign _234_ = ~((_207_ | _230_) & _233_);
assign _000_ = E ^ C;
assign _001_ = ~(_000_ & H);
assign _002_ = ~G;
assign _003_ = E ^ D;
assign _004_ = C ? _182_ : _003_;
assign _005_ = _004_ ^ _002_;
assign _006_ = ~(_005_ | _001_);
assign _007_ = ~(_004_ | _002_);
assign _008_ = ~A;
assign _009_ = ~(D & C);
assign _010_ = ~((_009_ & _008_) | (_052_ & C));
assign _011_ = ~((D | C) & E);
assign _012_ = ~(_011_ ^ _010_);
assign _013_ = _012_ ^ F;
assign _014_ = _013_ ^ _007_;
assign _015_ = _014_ ^ _006_;
assign _016_ = _015_ ^ _166_;
assign _017_ = _016_ | _212_;
assign _018_ = _000_ | H;
assign _019_ = _018_ & K;
assign _020_ = _019_ & _001_;
assign _021_ = ~_020_;
assign _022_ = _021_ | _005_;
assign _023_ = _022_ & _017_;
assign _024_ = ~((_013_ | _004_) & G);
assign _025_ = _012_ | _041_;
assign _026_ = ~C;
assign _027_ = ~(D & A);
assign _028_ = _027_ | _026_;
assign _029_ = ~(_009_ & _008_);
assign _031_ = ~(_029_ & _028_);
assign _032_ = ~(_011_ | _031_);
assign _033_ = _027_ & C;
assign _034_ = _033_ ^ _180_;
assign _035_ = _034_ ^ _118_;
assign _036_ = _035_ ^ _032_;
assign _037_ = _036_ ^ _025_;
assign _038_ = _037_ ^ _024_;
assign _039_ = _014_ & _006_;
assign _040_ = ~((_015_ & I) | _039_);
assign _042_ = _040_ ^ _038_;
assign _043_ = _042_ | _023_;
assign _044_ = _038_ & _039_;
assign _045_ = _037_ | _024_;
assign _046_ = _036_ | _025_;
assign _047_ = _011_ | _031_;
assign _048_ = _034_ | _118_;
assign _049_ = _034_ & _118_;
assign _050_ = ~((_049_ | _047_) & _048_);
assign _051_ = ~((_026_ & _008_) | B);
assign _053_ = C & A;
assign _054_ = _053_ | D;
assign _055_ = _051_ ? _182_ : _054_;
assign _056_ = _055_ ^ E;
assign _057_ = _056_ ^ _050_;
assign _058_ = _057_ ^ _046_;
assign _059_ = _058_ ^ _045_;
assign _060_ = ~(_059_ ^ _044_);
assign _061_ = ~(_038_ & _015_);
assign _062_ = _061_ & I;
assign _064_ = _062_ ^ _060_;
assign _065_ = _042_ & _023_;
assign _066_ = _005_ & _001_;
assign _067_ = ~((_066_ | _006_) & _212_);
assign _068_ = ~((_067_ & _021_) | (_066_ & _018_));
assign _069_ = _022_ & K;
assign _070_ = _069_ ^ _016_;
assign _071_ = _070_ | _068_;
assign _072_ = _071_ | _065_;
assign _073_ = ~((_072_ & _043_) | _064_);
assign _075_ = ~((_061_ & _060_) | _166_);
assign _076_ = ~(_011_ & _031_);
assign _077_ = _035_ | _076_;
assign _078_ = ~((_035_ & _032_) | _041_);
assign _079_ = ~((_057_ & F) | (_078_ & _077_));
assign _080_ = _056_ & _050_;
assign _081_ = ~(_055_ & E);
assign _082_ = C ? _027_ : A;
assign _083_ = ~((_054_ | B) & _082_);
assign _084_ = ~(_083_ & _081_);
assign _086_ = ~((_084_ | _080_) & _047_);
assign _087_ = ~(_086_ ^ _079_);
assign _088_ = ~(_058_ | _045_);
assign _089_ = ~((_059_ & _044_) | _088_);
assign _090_ = _089_ ^ _087_;
assign _091_ = _090_ ^ _075_;
assign _092_ = ~(_009_ | _180_);
assign _093_ = _178_ ^ C;
assign _094_ = ~(_093_ & D);
assign _095_ = ~(_179_ | _178_);
assign _097_ = ~(_053_ | _095_);
assign _098_ = ~((_097_ & _094_) | _092_);
assign _099_ = _098_ ^ F;
assign _100_ = _093_ ^ D;
assign _101_ = _100_ ^ G;
assign _102_ = _101_ & H;
assign _103_ = ~(_102_ & _099_);
assign _104_ = _100_ & G;
assign _105_ = ~(_104_ & _099_);
assign _106_ = _098_ | _041_;
assign _108_ = ~(_092_ | _179_);
assign _109_ = _108_ ^ _106_;
assign _110_ = ~(_109_ ^ _105_);
assign _111_ = ~((_110_ | _172_) & _103_);
assign _112_ = ~(_109_ | _105_);
assign _113_ = _092_ | _178_;
assign _114_ = _108_ | _098_;
assign _115_ = _114_ & F;
assign _116_ = _115_ ^ _113_;
assign _117_ = _116_ ^ _112_;
assign _119_ = ~(_117_ ^ _111_);
assign _120_ = ~(_102_ | _104_);
assign _121_ = ~(_120_ ^ _099_);
assign _122_ = _101_ ^ H;
assign _123_ = ~((_122_ | _121_) & I);
assign _124_ = _103_ & H;
assign _125_ = _124_ ^ _110_;
assign _126_ = ~((_125_ & _123_) | _119_);
assign _127_ = _122_ ^ I;
assign _128_ = _127_ | _121_;
assign _130_ = ~(_122_ | _166_);
assign _131_ = _130_ ^ J;
assign _132_ = _131_ ^ _121_;
assign _133_ = _179_ | _192_;
assign _134_ = ~(_133_ | _127_);
assign _135_ = ~((_134_ & _132_) | (_128_ & J));
assign _136_ = _125_ | _123_;
assign _137_ = ~(_136_ & _135_);
assign _138_ = B | A;
assign _139_ = _127_ | _138_;
assign _141_ = ~((_127_ & _138_) | K);
assign _142_ = ~((_139_ | _192_) & _141_);
assign _143_ = _139_ & J;
assign _144_ = _143_ ^ _132_;
assign _145_ = ~((_144_ & _142_) | (_137_ & _126_));
assign _146_ = ~(_135_ & _119_);
assign _147_ = ~((_135_ | _119_) & _136_);
assign _148_ = ~((_147_ | _126_) & _146_);
assign _149_ = _058_ | _045_;
assign _150_ = _047_ & _028_;
assign _152_ = ~((_086_ | _079_) & _150_);
assign _153_ = ~((_117_ & _111_) | _152_);
assign _154_ = ~((_087_ | _149_) & _153_);
assign _155_ = ~((_090_ & _075_) | _154_);
assign _156_ = ~((_148_ | _145_) & _155_);
assign _157_ = ~((_091_ & _073_) | _156_);
assign _158_ = ~((_234_ | _229_) & _157_);
assign _159_ = ~((_219_ & _211_) | _158_);
assign valid = _159_ & _228_;
assign total_value[0] = J;
endmodule
|
/***********************************************************
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: mc_phy.v,v 1.10.10.3 2011/05/30 10:45:54 pboya Exp $
// $Author: pboya $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
//`include "phy.vh"
`define PC_OFFSET_RANGE 22:17
module mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_BITLANES_OUTONLY = PHY_0_BITLANES_OUTONLY,
parameter PHY_2_BITLANES_OUTONLY = PHY_0_BITLANES_OUTONLY,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
// parameter RCLK_SELECT_EDGE = 3'b111,
parameter DDR_CLK_SELECT_BANK = 0,
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
// common to instance 0
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_GENERATE_DDR_CK = "B",
parameter PHY_0_NUM_DDR_CK = 1,
parameter PHY_0_DIFFERENTIAL_DQS = "TRUE",
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_PO_FINE_DELAY = "UNDECLARED",
parameter PHY_0_A_PO_OCLK_DELAY = 0,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_GENERATE_DDR_CK = PHY_0_GENERATE_DDR_CK,
parameter PHY_1_NUM_DDR_CK = PHY_0_NUM_DDR_CK,
parameter PHY_1_DIFFERENTIAL_DQS = PHY_0_DIFFERENTIAL_DQS,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_PO_FINE_DELAY = PHY_0_PO_FINE_DELAY,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter IODELAY_GRP = "IODELAY_MIG",
// common to instance 2
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_GENERATE_DDR_CK = PHY_0_GENERATE_DDR_CK,
parameter PHY_2_NUM_DDR_CK = PHY_0_NUM_DDR_CK,
parameter PHY_2_DIFFERENTIAL_DQS = PHY_0_DIFFERENTIAL_DQS,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_PO_FINE_DELAY = PHY_0_PO_FINE_DELAY,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input input_sink,
output if_a_empty,
output if_empty,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
output phy_ctl_full,
/**
inout [(HIGHEST_LANE*12)-1:0] IO, // data/ctl to memory
inout [(HIGHEST_LANE*2-1):0] DQS, // to memory
**/
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output wire rst_out, // to memory
output [(PHY_0_NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output rclk,
output mcGo,
//inout [`SCAN_TEST_BUS_WIDTH-1:0] scan_test_bus_A,
//inout [`SCAN_TEST_BUS_WIDTH-1:0] scan_test_bus_B,
//inout [`SCAN_TEST_BUS_WIDTH-1:0] scan_test_bus_C,
//inout [`SCAN_TEST_BUS_WIDTH-1:0] scan_test_bus_D
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per lane, zero's only control lane calibration inputs
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output reg pi_dqs_out_of_range
);
wire [1:0] phy_encalib;
wire [7:0] calib_zero_inputs_int ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(PHY_0_NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk_w [4:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
reg rst_out_i = 1'b0;
wire freq_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] mux_i0_v;
wire [HIGHEST_BANK-1:0] mux_i1_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
wire [7:0] dummy;
wire [3:0] dummy_q[11:0];
wire [HIGHEST_LANE -1:0] dummy_data;
wire [HIGHEST_LANE*2-1:0] dummy_dqs;
localparam IF_ALMOST_EMPTY_VALUE = 1;
localparam IF_ALMOST_FULL_VALUE = 2;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam MASTER_PHY_CTL = 0;
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam real FREQ_REF_PER_NS = TCK > 2500.0 ? TCK/2/1000.0 : TCK/1000.0;
localparam DDR_TCK = TCK;
localparam FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
(PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
(PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = PI_S2_TAPS/2 * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam real PI_OFFSET = PO_DELAY - PI_INTRINSIC_DELAY;
localparam real PI_STG2_DELAY = PI_OFFSET > PI_MAX_STG2_DELAY ?
PI_OFFSET - PI_MAX_STG2_DELAY : PI_OFFSET;
localparam RCLK_SELECT_EDGE = PI_OFFSET > PI_MAX_STG2_DELAY ? RCLK_NEG_EDGE : RCLK_POS_EDGE;
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam integer L_PHY_0_PO_FINE_DELAY = PHY_0_PO_FINE_DELAY == "UNDECLARED" ? PO_CIRC_BUF_DELAY : PHY_0_PO_FINE_DELAY;
localparam integer L_PHY_1_PO_FINE_DELAY = PHY_0_PO_FINE_DELAY == "UNDECLARED" ? PO_CIRC_BUF_DELAY : PHY_1_PO_FINE_DELAY;
localparam integer L_PHY_2_PO_FINE_DELAY = PHY_0_PO_FINE_DELAY == "UNDECLARED" ? PO_CIRC_BUF_DELAY : PHY_2_PO_FINE_DELAY;
localparam PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? DEFAULT_RCLK_DELAY : 0 : 0;
localparam _PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam _PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_ctl_wr;
wire _phy_clk;
wire [2:0] mcGo_w;
reg [3:0] mcGo_r;
initial begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0d ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", RCLK_SELECT_EDGE);
end
// Use module signal_split for only for simulation purposes if it's desired to insert skew
// in signals going to different PHASER blocks. Otherwise, use the code below to bypass any
// skew insertion.
assign mem_refclk_split = mem_refclk;
assign sync_pulse_split = sync_pulse;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign data_offset_1_split1 = data_offset_1;
assign data_offset_2_split2 = data_offset_2;
assign phy_ctl_clk_split0 = phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
/*
signal_split
#(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4)
) signal_split_i
(
.phy_clk (_phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.mem_refclk_div4 (mem_refclk_div4),
.sync_pulse (sync_pulse),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (_phy_ctl_wd),
.phy_ctl_wr (_phy_ctl_wr),
.data_offset_1 (data_offset_1),
.data_offset_2 (data_offset_2),
.mem_refclk_split (mem_refclk_split),
.freq_refclk_split (freq_refclk_split),
.mem_refclk_div4_split (mem_refclk_div4_split),
.sync_pulse_split (sync_pulse_split),
.phy_ctl_clk_split0 (phy_ctl_clk_split0),
.phy_clk_split0 (phy_clk_split0),
.phy_ctl_wd_split0 (phy_ctl_wd_split0),
.phy_ctl_wr_split0 (phy_ctl_wr_split0),
.phy_ctl_clk_split1 (phy_ctl_clk_split1),
.phy_clk_split1 (phy_clk_split1),
.phy_ctl_wd_split1 (phy_ctl_wd_split1),
.data_offset_1_split1 (data_offset_1_split1),
.phy_ctl_wr_split1 (phy_ctl_wr_split1),
.phy_ctl_clk_split2 (phy_ctl_clk_split2),
.phy_clk_split2 (phy_clk_split2),
.phy_ctl_wd_split2 (phy_ctl_wd_split2),
.data_offset_2_split2 (data_offset_2_split2),
.phy_ctl_wr_split2 (phy_ctl_wr_split2),
.phy_dout_split0 (phy_dout_split0),
.phy_cmd_wr_en_split0 (phy_cmd_wr_en_split0),
.phy_data_wr_en_split0 (phy_data_wr_en_split0),
.phy_rd_en_split0 (phy_rd_en_split0),
.phy_dout_split1 (phy_dout_split1),
.phy_cmd_wr_en_split1 (phy_cmd_wr_en_split1),
.phy_data_wr_en_split1 (phy_data_wr_en_split1),
.phy_rd_en_split1 (phy_rd_en_split1),
.phy_dout_split2 (phy_dout_split2),
.phy_cmd_wr_en_split2 (phy_cmd_wr_en_split2),
.phy_data_wr_en_split2 (phy_data_wr_en_split2),
.phy_rd_en_split2 (phy_rd_en_split2)
);
*/
assign pi_dqs_found_all = & pi_dqs_found_all_w[HIGHEST_BANK-1:0];
assign pi_dqs_found_any = | pi_dqs_found_any_w[HIGHEST_BANK-1:0];
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
//assign if_empty = ! if_empty_def ? |if_empty_v : & if_empty_v;
generate
begin
if (HIGHEST_BANK==3)
assign if_empty = !if_empty_def ? (mux_i0_v[0] | mux_i0_v[1] | mux_i0_v[2]) : (mux_i1_v[0] & mux_i1_v[1] & mux_i1_v[2]);
else if (HIGHEST_BANK==2)
assign if_empty = !if_empty_def ? (mux_i0_v[0] | mux_i0_v[1]) : (mux_i1_v[0] & mux_i1_v[1]);
else
assign if_empty = !if_empty_def ? (mux_i0_v[0]) : (mux_i1_v[0]);
end
endgenerate
assign if_a_empty = |if_a_empty_v;
assign ddr_clk = ddr_clk_w[DDR_CLK_SELECT_BANK];
assign rclk = rclk_w[RCLK_SELECT_BANK];
always @(*) begin
rst_out_i <= rst_out_w[RCLK_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <=#(1) (mcGo_r << 1) | (mcGo_w[RCLK_SELECT_BANK] && phy_ctl_ready);
end
assign mcGo = mcGo_r[3];
// Substitute OBUF with direct connection to prevent possible instantiation
// of extra output if rst_out from MC_PHY isn't used
//OBUF rst_buf(.O(rst_out), .I(rst_out_i));
assign rst_out = rst_out_i;
generate
if (PHYCTL_CMD_FIFO == "TRUE" ) begin
assign _phy_ctl_wd = {if_q7, if_q6[3:0], if_q5[3:0], if_q4, if_q3, if_q2, if_q1, if_q0};
assign aux_in_[1] = if_q8;
assign aux_in_[2] = if_q9;
assign phy_ctl_a_full = _phy_ctl_a_full_f;
assign phy_ctl_full = _phy_ctl_full_f;
assign _phy_ctl_wr = ! _phy_ctl_empty_f;
assign _phy_clk = mem_refclk_div4;
end
else begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = &_phy_ctl_a_full_p;
assign phy_ctl_full = &_phy_ctl_full_p;
assign _phy_ctl_wr = phy_ctl_wr;
assign _phy_clk = phy_clk;
end
endgenerate
// this code ties off dummy wires for unused dqs signals
// on control lanes and unused data signals on data lanes.
// this keeps the allocation of the busses simple
// all lanes allocate 10-bits of data plus 2-more at the high
// end of the bus.
assign dummy [0] = (&dummy_data) & (& dummy_dqs);
// this fifo crosses domain for the phy control word from
// phy_clk to freq_refclk (ddr clk). It uses one in_fifo (4x4
// mode) that is unused in the control-path.
// Set parameter PHYCTL_CMD_FIFO = "TRUE" to use.
// otherwise this fifo is trimmed in the mapper.
// It is required to be used if there are more than 1
// phy controllers to prevent asychronous domain crossing
// in phy controller causing a skew in when phy control
// words are registered and executed. Using this fifo keeps them
// synchronous and timing is simplified.
`ifdef FUJI_PHY_BLH
B_IN_FIFO #(
`else
IN_FIFO #(
`endif
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo_i (
.ALMOSTEMPTY (_phy_ctl_a_empty_f),
.ALMOSTFULL (_phy_ctl_a_full_f),
.EMPTY (_phy_ctl_empty_f),
.FULL (_phy_ctl_full_f),
.Q0 ({dummy_q[0],if_q0}),
.Q1 ({dummy_q[1],if_q1}),
.Q2 ({dummy_q[2],if_q2}),
.Q3 ({dummy_q[3],if_q3}),
.Q4 ({dummy_q[4],if_q4}),
.Q5 ({if_q5}),
.Q6 ({if_q6}),
.Q7 ({dummy_q[7],if_q7}),
.Q8 ({dummy_q[8],if_q8}),
.Q9 ({dummy_q[9],if_q9}),
//===
.D0 (phy_ctl_wd[3:0]),
.D1 (phy_ctl_wd[7:4]),
.D2 (phy_ctl_wd[11:8]),
.D3 (phy_ctl_wd[15:12]),
.D4 (phy_ctl_wd[19:16]),
.D5 ({phy_ctl_wd[23:20], phy_ctl_wd[23:20]}),
.D6 ({phy_ctl_wd[27:24], phy_ctl_wd[27:24]}),
.D7 (phy_ctl_wd[31:28]),
.D8 (aux_in_1),
.D9 (aux_in_2),
.RDCLK (mem_refclk_div4_split0),
.RDEN ( ! _phy_ctl_empty_f ),
.RESET (rst),
.WRCLK (phy_clk_split0),
.WREN (phy_ctl_wr_split0)
);
// instance of four-lane phy
generate
if ( BYTE_LANES_B0 != 0) begin : phy_4lanes_0
phy_4lanes #(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.LAST_BANK (PHY_0_IS_LAST_BANK ),
.LANE_REMAP (PHY_0_LANE_REMAP),
//.OF_ALMOST_FULL_VALUE (PHY_O_OF_ALMOST_FULL_VALUE),
//.IF_ALMOST_EMPTY_VALUE (PHY_O_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.GENERATE_DDR_CK (PHY_0_GENERATE_DDR_CK),
.NUM_DDR_CK (PHY_0_NUM_DDR_CK),
.DIFFERENTIAL_DQS (PHY_0_DIFFERENTIAL_DQS),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.MC_DIVIDE (PHY_CLK_RATIO),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.A_PI_FINE_DELAY (PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
//.A_PI_CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
//.A_PO_CLKOUT_DIV ( PHY_0_A_PO_CLKOUT_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[`PC_OFFSET_RANGE]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (rclk_w[0]),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_empty_def (if_empty_def),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.mux_i0 (mux_i0_v[0]),
.mux_i1 (mux_i1_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.input_sink (),
.calib_sel ({calib_zero_inputs_int[0], calib_sel[1:0]}),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_in_common (calib_in_common),
.phy_encalib (phy_encalib),
.po_coarse_enable (po_coarse_enable),
.po_fine_enable (po_fine_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
if ( RCLK_SELECT_EDGE[0])
always @(posedge rclk_w[0] or posedge rst) begin
if (rst)
aux_out[3:0] <= #1 0;
else
aux_out[3:0] <= #1 aux_out_[3:0];
end
else
always @(negedge rclk_w[0] or posedge rst) begin
if (rst)
aux_out[3:0] <= #1 0;
else
aux_out[3:0] <= #1 aux_out_[3:0];
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[319:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign mux_i0_v[0] = 0;
assign mux_i1_v[0] = 0;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : phy_4lanes_1
phy_4lanes #(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
//.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
//.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.GENERATE_DDR_CK (PHY_1_GENERATE_DDR_CK),
.NUM_DDR_CK (PHY_1_NUM_DDR_CK),
.DIFFERENTIAL_DQS (PHY_1_DIFFERENTIAL_DQS),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.MC_DIVIDE (PHY_CLK_RATIO),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.A_PI_FINE_DELAY (PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
//.A_PI_CLKOUT_DIV (PHY_1_A_PI_CLKOUT_DIV),
//.A_PO_CLKOUT_DIV (PHY_1_A_PO_CLKOUT_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (rclk_w[1]),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_empty_def (if_empty_def),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.mux_i0 (mux_i0_v[1]),
.mux_i1 (mux_i1_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.input_sink (),
.calib_sel ({calib_zero_inputs_int[1], calib_sel[1:0]}),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_in_common (calib_in_common),
.phy_encalib (phy_encalib),
.po_coarse_enable (po_coarse_enable),
.po_fine_enable (po_fine_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
if ( RCLK_SELECT_EDGE[1])
always @(posedge rclk_w[1] or posedge rst) begin
if (rst)
aux_out[7:4] <= #1 0;
else
aux_out[7:4] <= #1 aux_out_[7:4];
end
else
always @(negedge rclk_w[1] or posedge rst) begin
if (rst)
aux_out[7:4] <= #1 0;
else
aux_out[7:4] <= #1 aux_out_[7:4];
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[2*320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign mux_i0_v[1] = 0;
assign mux_i1_v[1] = 0;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
end
if ( BYTE_LANES_B2 != 0) begin : phy_4lanes_2
phy_4lanes #(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
//.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
//.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.GENERATE_DDR_CK (PHY_2_GENERATE_DDR_CK),
.NUM_DDR_CK (PHY_2_NUM_DDR_CK),
.DIFFERENTIAL_DQS (PHY_2_DIFFERENTIAL_DQS),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.MC_DIVIDE (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.A_PI_FINE_DELAY (PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
//.A_PI_CLKOUT_DIV (PHY_2_A_PI_CLKOUT_DIV),
//.A_PO_CLKOUT_DIV (PHY_2_A_PO_CLKOUT_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (rclk_w[2]),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_empty_def (if_empty_def),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.mux_i0 (mux_i0_v[2]),
.mux_i1 (mux_i1_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.input_sink (),
.calib_sel ({calib_zero_inputs_int[2], calib_sel[1:0]}),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_in_common (calib_in_common),
.phy_encalib (phy_encalib),
.po_coarse_enable (po_coarse_enable),
.po_fine_enable (po_fine_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
if (RCLK_SELECT_EDGE[2])
always @(posedge rclk_w[2] or posedge rst) begin
if (rst)
aux_out[11:8] <= #1 0;
else
aux_out[11:8] <= #1 aux_out_[11:8];
end
else
always @(negedge rclk_w[2] or posedge rst) begin
if (rst)
aux_out[11:8] <= #1 0;
else
aux_out[11:8] <= #1 aux_out_[11:8];
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[3*320-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign mux_i0_v[2] = 0;
assign mux_i1_v[2] = 0;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
end
endgenerate
generate
// emit an extra phaser_in to generate rclk
// so that rst and auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
`ifdef FUJI_PHY_BLH
B_PHASER_IN_PHY #(
`else
PHASER_IN_PHY #(
`endif
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( FREQ_REF_PER_NS),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (rclk_w[RCLK_SELECT_BANK]),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580ww55.v
//
// Parallel interface k580ww55 design file of Bashkiria-2M replica.
//
// Warning: This realization is not fully operational.
module k580ww55(
input clk, input reset, input[1:0] addr, input we_n,
input[7:0] idata, output reg[7:0] odata,
input[7:0] ipa, output reg[7:0] opa,
input[7:0] ipb, output reg[7:0] opb,
input[7:0] ipc, output reg[7:0] opc);
//reg[6:0] mode;
always begin
case (addr)
2'b00: odata = ipa;
2'b01: odata = ipb;
2'b10: odata = ipc;
2'b11: odata = 8'h00;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
//mode <= 7'b0011011;
{opa,opb,opc} <= {8'hFF,8'hFF,8'hFF};
end else
if (~we_n) begin
if (addr==2'b00) opa <= idata;
if (addr==2'b01) opb <= idata;
if (addr==2'b10) opc <= idata;
//if (addr==2'b11 && idata[7]) mode <= idata[6:0];
if (addr==2'b11 && ~idata[7]) opc[idata[3:1]] <= idata[0];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// File name : sata_link.v
// Note : This is top module of SATA link Layer
// Test/Verification Environment
// Dependencies : Nil
//////////////////////////////////////////////////////////////////////////////
module sata_link #(
parameter integer CHIPSCOPE = 0
)
(
input CLK,
input RESET,
input LINKUP,
input PHY_CLK,
output reg [15:0] TX_DATA_OUT,
output reg TX_CHARISK_OUT,
input [15:0] RX_DATA_IN,
input [1:0] RX_CHARISK_IN,
input [1:0] ALIGN_COUNT,
input [31:0] TX_DATA_IN_DW,
output [31:0] RX_DATA_OUT_DW,
input PMREQ_P_T,
input PMREQ_S_T,
input PM_EN,
input LRESET,
input DATA_RDY_T,
output PHY_DETECT_T,
output ILLEGAL_STATE_T,
input ESCAPECF_T,
input FRAME_END_T,
input DECERR,
output TX_TERMN_T_O,
input RX_FIFO_RDY,
output RX_FAIL_T,
output CRC_ERR_T,
output VALID_CRC_T,
input FIS_ERR,
input GOOD_STATUS_T,
input UNRECGNZD_FIS_T,
input TX_TERMN_T_I,
output R_OK_T,
output R_ERR_T,
output SOF_T,
output EOF_T,
output TX_RDY_ACK_T,
output DATA_OUT_VLD_T,
input TX_RDY_T,
output R_OK_SENT_T,
output DATA_IN_RD_EN_T,
output X_RDY_SENT_T,
output DMA_TERMINATED
);
reg [15:0] RX_DATA_IN_LHW;
reg [31:0] RX_DATA_IN_DW;
wire [31:0] TX_DATA_OUT_DW;
reg RX_LHW;
wire TX_CHARISK_OUT_int;
reg [31:0] RX_DATA_IN_DW_int;
reg [31:0] TX_DATA_OUT_DW_int;
reg TX_CHARISK_OUT_int2;
always @(posedge PHY_CLK, posedge RESET)
begin: rxdata_2_32bit
if (RESET == 1 ) begin
RX_DATA_IN_LHW <= 16'h 957C;
RX_DATA_IN_DW_int <= 32'h 00000000;
RX_LHW <= 1;
end
else begin
if (LINKUP == 1) begin
RX_LHW <= !RX_LHW;
if (RX_LHW == 1) begin
RX_DATA_IN_LHW <= RX_DATA_IN;
RX_DATA_IN_DW_int <= RX_DATA_IN_DW_int;
end
else begin
RX_DATA_IN_DW_int <= {RX_DATA_IN, RX_DATA_IN_LHW};
RX_DATA_IN_LHW <= RX_DATA_IN_LHW;
end
end
else begin
RX_DATA_IN_LHW <= RX_DATA_IN_LHW;
RX_DATA_IN_DW_int <= RX_DATA_IN_DW_int;
end
end
end //always
always @(posedge PHY_CLK, posedge RESET)
begin: rxdata_2_32bit_aligh_to_CLK
if (RESET == 1 ) begin
RX_DATA_IN_DW <= 32'h 00000000;
end
else begin
if (LINKUP == 1) begin
if (CLK == 1) begin
RX_DATA_IN_DW <= RX_DATA_IN_DW_int;
end
else begin
RX_DATA_IN_DW <= RX_DATA_IN_DW;
end
end
else begin
RX_DATA_IN_DW <= RX_DATA_IN_DW;
end
end
end //always
always @ (posedge RESET, posedge PHY_CLK)
begin: txdata_2_16bit
if (RESET == 1 ) begin
TX_DATA_OUT <= 16'h0;
TX_CHARISK_OUT <= 0;
end
else begin
case (ALIGN_COUNT)
2'b00 :
begin
TX_DATA_OUT <= TX_DATA_OUT_DW_int[31:16];
TX_CHARISK_OUT <= 0;
end
2'b01 :
begin
TX_DATA_OUT <= TX_DATA_OUT_DW_int[15:0];
TX_CHARISK_OUT <= TX_CHARISK_OUT_int2;
end
2'b10 :
begin
TX_DATA_OUT <= TX_DATA_OUT_DW_int[31:16];
TX_CHARISK_OUT <= 0;
end
2'b11 :
begin
TX_DATA_OUT <= TX_DATA_OUT_DW_int[15:0];
TX_CHARISK_OUT <= TX_CHARISK_OUT_int2;
end
endcase
end
end //always
always @(posedge PHY_CLK, posedge RESET)
begin: txdata_aligh_to_CLK
if (RESET == 1 ) begin
TX_DATA_OUT_DW_int <= 32'h 7B4A4ABC;
end
else begin
if ((ALIGN_COUNT == 2'b00) || (ALIGN_COUNT == 2'b 10)) begin
TX_DATA_OUT_DW_int <= TX_DATA_OUT_DW;
TX_CHARISK_OUT_int2 <= TX_CHARISK_OUT_int;
end
else begin
TX_DATA_OUT_DW_int <= TX_DATA_OUT_DW_int;
TX_CHARISK_OUT_int2 <= TX_CHARISK_OUT_int2;
end
end
end //always
link_layer #(
.CHIPSCOPE (CHIPSCOPE)
)
link_layer_32bit(
.clk (CLK),
.rst (RESET),
.data_in_p (RX_DATA_IN_DW),
.data_in_t (TX_DATA_IN_DW),
.data_out_p (TX_DATA_OUT_DW),
.data_out_t (RX_DATA_OUT_DW),
.PHYRDY (LINKUP),
.TX_RDY_T (TX_RDY_T),
.PMREQ_P_T (PMREQ_P_T),
.PMREQ_S_T (PMREQ_S_T),
.PM_EN (PM_EN),
.LRESET (LRESET),
.data_rdy_T (DATA_RDY_T),
.phy_detect_T (PHY_DETECT_T),
.illegal_state_t (ILLEGAL_STATE_T),
.EscapeCF_T (ESCAPECF_T),
.frame_end_T (FRAME_END_T),
.DecErr (DECERR),
.tx_termn_T_o (TX_TERMN_T_O),
.rx_FIFO_rdy (RX_FIFO_RDY),
.rx_fail_T (RX_FAIL_T),
.crc_err_T (CRC_ERR_T),
.valid_CRC_T (VALID_CRC_T),
.FIS_err (FIS_ERR),
.Good_status_T (GOOD_STATUS_T),
.Unrecgnzd_FIS_T (UNRECGNZD_FIS_T),
.tx_termn_T_i (TX_TERMN_T_I),
.R_OK_T (R_OK_T),
.R_ERR_T (R_ERR_T),
.SOF_T (SOF_T),
.EOF_T (EOF_T),
.cntrl_char (TX_CHARISK_OUT_int),
.tx_rdy_ack_t (TX_RDY_ACK_T),
.data_out_vld_T (DATA_OUT_VLD_T),
.R_OK_SENT_T (R_OK_SENT_T),
.data_in_rd_en_t (DATA_IN_RD_EN_T),
.X_RDY_SENT_T (X_RDY_SENT_T),
.DMA_TERMINATED (DMA_TERMINATED)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:14:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: TF_EECS301_Lab4_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: EECS301 Lab 4 Top Level Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab4_TopLevel();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
reg [3:0] KEY;
reg [9:0] SW;
EECS301_Lab4_TopLevel
#(
.KEY_LOCK_DELAY( 10000 ), // 10 us
.SW_DEBOUNCE_TIME( 100 ) // 100 nS
)
uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// 7-Segment Display Signals (Active-Low)
.HEX0( HEX0 ),
.HEX1( HEX1 ),
.HEX2( HEX2 ),
.HEX3( HEX3 ),
.HEX4( HEX4 ),
.HEX5( HEX5 ),
// Button Signals (Active-Low)
.KEY( KEY ),
// Switch Signals
.SW( SW )
);
//
// Test Stimulus
//
initial
begin
// Initialize Signals
KEY = 4'hF; // Active-Low
SW = 10'h000;
#1000;
//
// Begin Testing
//
// Set input test value
SW = 10'h021;
#1000; // Wait 1uS for debounce
// Press Add Key
KEY[0] = 1'b0;
#1000; // Press for 1uS
KEY[0] = 1'b1;
#10000; // Wait 10 uS
// Press Sub Key
KEY[1] = 1'b0;
#1000; // Press for 1uS
KEY[1] = 1'b1;
#10000; // Wait 10 uS
// Press Sub Key
KEY[1] = 1'b0;
#1000; // Press for 1uS
KEY[1] = 1'b1;
#10000; // Wait 10 uS
SW = 10'h321;
#1000; // Wait 1uS for debounce
// Press Add Key
KEY[0] = 1'b0;
#1000; // Press for 1uS
KEY[0] = 1'b1;
#10000; // Wait 10 uS
// Press Clr Key
KEY[3] = 1'b0;
#1000; // Press for 1uS
KEY[3] = 1'b1;
#10000; // Wait 10 uS
end
endmodule
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
`include "mips_defines.vh"
module mips_syscallUnit (/*AUTOARG*/
// Outputs
syscall_halt,
// Inputs
pc, r_v0, Sys, rst_b, clk
);
output wire syscall_halt;
input [31:0] pc, r_v0;
input Sys, rst_b, clk;
assign syscall_halt = rst_b && Sys && (r_v0 == `SYS_EXIT);
// synthesis translate_off
always @(posedge clk)
if (rst_b && Sys)
case(r_v0)
`SYS_EXIT: begin
$display(`MSG_EOP_S, pc);
end
endcase
// synthesis translate_on
endmodule
|
(* -*- coq-prog-name: "coqtop.byte"; coq-prog-args: ("-emacs-U" "-top" "Coq.Classes.Morphisms"); compile-command: "make -C ../.. TIME='time'" -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Typeclass-based morphism definition and standard, minimal instances.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - UniversitÃcopyright Paris Sud
91405 Orsay, France *)
(* $Id$ *)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Require Export Coq.Classes.RelationClasses.
Set Implicit Arguments.
Unset Strict Implicit.
(** * Morphisms.
We now turn to the definition of [Morphism] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism on a relation [R] is an object respecting the relation (in its kernel).
The relation [R] will be instantiated by [respectful] and [A] by an arrow type
for usual morphisms. *)
Class Morphism A (R : relation A) (m : A) : Prop :=
respect : R m m.
(** We make the type implicit, it can be infered from the relations. *)
Implicit Arguments Morphism [A].
(** We allow to unfold the [relation] definition while doing morphism search. *)
Typeclasses unfold relation.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Prop)
(R' : forall (x : A) (y : B), C x -> D y -> Prop) :
(forall x : A, C x) -> (forall x : B, D x) -> Prop :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful (A B : Type)
(R : relation A) (R' : relation B) : relation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Arguments Scope Morphism [type_scope signature_scope].
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (inverse (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
Arguments Scope respectful [type_scope type_scope signature_scope signature_scope].
Open Local Scope signature_scope.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per [ PER A (R : relation A), PER B (R' : relation B) ] :
PER (A -> B) (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
(** Subrelations induce a morphism on the identity, not used for morphism search yet. *)
Lemma subrelation_id_morphism [ subrelation A R₁ R₂ ] : Morphism (R₁ ==> R₂) id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Instance morphisms_subrelation [ sub : subrelation A R₁ R₂ ] :
! subrelation (B -> A) (R ==> R₁) (R ==> R₂).
Proof. firstorder. Qed.
Instance morphisms_subrelation_left [ sub : subrelation A R₂ R₁ ] :
! subrelation (A -> B) (R₁ ==> R) (R₂ ==> R) | 3.
Proof. firstorder. Qed.
(** [Morphism] is itself a covariant morphism for [subrelation]. *)
Lemma subrelation_morphism [ sub : subrelation A R₁ R₂, mor : Morphism A R₁ m ] : Morphism R₂ m.
Proof.
intros. apply sub. apply mor.
Qed.
Instance morphism_subrelation_morphism :
Morphism (subrelation ++> @eq _ ==> impl) (@Morphism A).
Proof. reduce. subst. firstorder. Qed.
(** We use an external tactic to manage the application of subrelation, which is otherwise
always applicable. We allow its use only once per branch. *)
Inductive subrelation_done : Prop :=
did_subrelation : subrelation_done.
Ltac subrelation_tac :=
match goal with
| [ _ : subrelation_done |- _ ] => fail 1
| [ |- @Morphism _ _ _ ] => let H := fresh "H" in
set(H:=did_subrelation) ; eapply @subrelation_morphism
end.
Hint Extern 4 (@Morphism _ _ _) => subrelation_tac : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl.
Proof. firstorder. Qed.
Instance iff_inverse_impl_subrelation : subrelation iff (inverse impl).
Proof. firstorder. Qed.
Instance pointwise_subrelation [ sub : subrelation A R R' ] :
subrelation (pointwise_relation (A:=B) R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. apply H. Qed.
(** The complement of a relation conserves its morphisms. *)
Program Instance complement_morphism
[ mR : Morphism (A -> A -> Prop) (RA ==> RA ==> iff) R ] :
Morphism (RA ==> RA ==> iff) (complement R).
Next Obligation.
Proof.
unfold complement.
pose (mR x y H x0 y0 H0).
intuition.
Qed.
(** The [inverse] too, actually the [flip] instance is a bit more general. *)
Program Instance flip_morphism
[ mor : Morphism (A -> B -> C) (RA ==> RB ==> RC) f ] :
Morphism (RB ==> RA ==> RC) (flip f).
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive relation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Program Instance trans_contra_co_morphism
[ Transitive A R ] : Morphism (R --> R ++> impl) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(* (** Dually... *) *)
(* Program Instance [ Transitive A R ] => *)
(* trans_co_contra_inv_impl_morphism : Morphism (R ++> R --> inverse impl) R. *)
(* Next Obligation. *)
(* Proof with auto. *)
(* apply* trans_contra_co_morphism ; eauto. eauto. *)
(* Qed. *)
(** Morphism declarations for partial applications. *)
Program Instance trans_contra_inv_impl_morphism
[ Transitive A R ] : Morphism (R --> inverse impl) (R x).
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Program Instance trans_co_impl_morphism
[ Transitive A R ] : Morphism (R ==> impl) (R x).
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Program Instance trans_sym_co_inv_impl_morphism
[ Transitive A R, Symmetric A R ] : Morphism (R ==> inverse impl) (R x).
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Program Instance trans_sym_contra_impl_morphism
[ Transitive A R, Symmetric _ R ] : Morphism (R --> impl) (R x).
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Program Instance equivalence_partial_app_morphism
[ Equivalence A R ] : Morphism (R ==> iff) (R x).
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive relation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof
to get an [R y z] goal. *)
Program Instance trans_co_eq_inv_impl_morphism
[ Transitive A R ] : Morphism (R ==> (@eq A) ==> inverse impl) R.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(* Program Instance [ Transitive A R ] => *)
(* trans_contra_eq_impl_morphism : Morphism (R --> (@eq A) ==> impl) R. *)
(* Next Obligation. *)
(* Proof with auto. *)
(* transitivity x... *)
(* Qed. *)
(** Every Symmetric and Transitive relation gives rise to an equivariant morphism. *)
Program Instance trans_sym_morphism
[ Transitive A R, Symmetric _ R ] : Morphism (R ==> R ==> iff) R.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x...
transitivity y... transitivity y0...
Qed.
Program Instance equiv_morphism [ Equivalence A R ] :
Morphism (R ==> R ==> iff) R.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
(** In case the rewrite happens at top level. *)
Program Instance iff_inverse_impl_id :
Morphism (iff ==> inverse impl) id.
Program Instance inverse_iff_inverse_impl_id :
Morphism (iff --> inverse impl) id.
Program Instance iff_impl_id :
Morphism (iff ==> impl) id.
Program Instance inverse_iff_impl_id :
Morphism (iff --> impl) id.
(** Coq functions are morphisms for leibniz equality,
applied only if really needed. *)
(* Instance (A : Type) [ Reflexive B R ] => *)
(* eq_reflexive_morphism : Morphism (@Logic.eq A ==> R) m | 3. *)
(* Proof. simpl_relation. Qed. *)
Instance reflexive_eq_dom_reflexive (A : Type) [ Reflexive B R' ] :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_relation. Qed.
(** [respectful] is a morphism for relation equivalence. *)
Instance respectful_morphism :
Morphism (relation_equivalence ++> relation_equivalence ++> relation_equivalence) (@respectful A B).
Proof.
reduce.
unfold respectful, relation_equivalence, predicate_equivalence in * ; simpl in *.
split ; intros.
rewrite <- H0.
apply H1.
rewrite H.
assumption.
rewrite H0.
apply H1.
rewrite <- H.
assumption.
Qed.
(** Every element in the carrier of a reflexive relation is a morphism for this relation.
We use a proxy class for this case which is used internally to discharge reflexivity constraints.
The [Reflexive] instance will almost always be used, but it won't apply in general to any kind of
[Morphism (A -> B) _ _] goal, making proof-search much slower. A cleaner solution would be to be able
to set different priorities in different hint bases and select a particular hint database for
resolution of a type class constraint.*)
Class MorphismProxy A (R : relation A) (m : A) : Prop :=
respect_proxy : R m m.
Instance reflexive_morphism_proxy
[ Reflexive A R ] (x : A) : MorphismProxy A R x | 1.
Proof. firstorder. Qed.
Instance morphism_morphism_proxy
[ Morphism A R x ] : MorphismProxy A R x | 2.
Proof. firstorder. Qed.
(* Instance (A : Type) [ Reflexive B R ] => *)
(* eq_reflexive_morphism : Morphism (@Logic.eq A ==> R) m | 3. *)
(* Proof. simpl_relation. Qed. *)
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism [ Morphism (A -> B) (R ==> R') m, MorphismProxy A R x ] :
Morphism R' (m x).
Proof. simpl_relation. Qed.
Ltac partial_application_tactic :=
let tac x :=
match type of x with
| Type => fail 1
| _ => eapply @Reflexive_partial_app_morphism
end
in
let on_morphism m :=
match m with
| ?m' ?x => tac x
| ?m' _ ?x => tac x
| ?m' _ _ ?x => tac x
| ?m' _ _ _ ?x => tac x
| ?m' _ _ _ _ ?x => tac x
| ?m' _ _ _ _ _ ?x => tac x
| ?m' _ _ _ _ _ _ ?x => tac x
| ?m' _ _ _ _ _ _ _ ?x => tac x
| ?m' _ _ _ _ _ _ _ _ ?x => tac x
end
in
match goal with
| [ |- @Morphism _ _ ?m ] => on_morphism m
end.
(* Program Instance [ Morphism (A -> B) (R ==> R') m, Reflexive A R ] (x : A) => *)
(* reflexive_partial_app_morphism : Morphism R' (m x). *)
Hint Extern 4 (@Morphism _ _ _) => partial_application_tactic : typeclass_instances.
Lemma inverse_respectful : forall (A : Type) (R : relation A) (B : Type) (R' : relation B),
relation_equivalence (inverse (R ==> R')) (inverse R ==> inverse R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Special-purpose class to do normalization of signatures w.r.t. inverse. *)
Class (A : Type) => Normalizes (m : relation A) (m' : relation A) : Prop :=
normalizes : relation_equivalence m m'.
Instance inverse_respectful_norm :
Normalizes (A -> B) (inverse R ==> inverse R') (inverse (R ==> R')) .
Proof. firstorder. Qed.
(* If not an inverse on the left, do a double inverse. *)
Instance not_inverse_respectful_norm :
Normalizes (A -> B) (R ==> inverse R') (inverse (inverse R ==> R')) | 4.
Proof. firstorder. Qed.
Instance inverse_respectful_rec_norm [ Normalizes B R' (inverse R'') ] :
Normalizes (A -> B) (inverse R ==> R') (inverse (R ==> R'')).
Proof. red ; intros.
pose normalizes as r.
setoid_rewrite r.
setoid_rewrite inverse_respectful.
reflexivity.
Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Program Instance morphism_inverse_morphism
[ Morphism A R m ] : Morphism (inverse R) m | 2.
(** Bootstrap !!! *)
Instance morphism_morphism : Morphism (relation_equivalence ==> @eq _ ==> iff) (@Morphism A).
Proof.
simpl_relation.
reduce in H.
split ; red ; intros.
setoid_rewrite <- H.
apply H0.
setoid_rewrite H.
apply H0.
Qed.
Lemma morphism_releq_morphism [ Normalizes A R R', Morphism _ R' m ] : Morphism R m.
Proof.
intros.
pose respect as r.
pose normalizes as norm.
setoid_rewrite norm.
assumption.
Qed.
Inductive normalization_done : Prop := did_normalization.
Ltac morphism_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ |- @Morphism _ _ _ ] => let H := fresh "H" in
set(H:=did_normalization) ; eapply @morphism_releq_morphism
end.
Hint Extern 6 (@Morphism _ _ _) => morphism_normalization : typeclass_instances.
(** Every reflexive relation gives rise to a morphism, only for immediately solving goals without variables. *)
Lemma reflexive_morphism [ Reflexive A R ] (x : A)
: Morphism R x.
Proof. firstorder. Qed.
Ltac morphism_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : subrelation_done |- _ ] => fail 1
| [ |- @Morphism _ _ _ ] => eapply @reflexive_morphism
end.
Hint Extern 4 (@Morphism _ _ _) => morphism_reflexive : typeclass_instances.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLXBP_PP_SYMBOL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_PP_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo8to32.v when simulating
// the core, fifo8to32. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo8to32(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [15 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_2_V
`define SKY130_FD_SC_LS__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_2_V
|
/* verilator lint_off UNDRIVEN */
/* verilator lint_off UNUSED */
module axi_rom (
clk,rstn,
axi_ARVALID,
axi_ARREADY,
axi_AR,
axi_ARBURST,
axi_ARLEN,
axi_R,
axi_RVALID,
axi_RREADY,
axi_RLAST
);
input clk,rstn;
input axi_ARVALID,axi_RREADY;
output reg axi_ARREADY,axi_RVALID;
output reg axi_RLAST;
input [7:0] axi_ARLEN;
input [1:0] axi_ARBURST;
output [31:0] axi_R;
input [31:0] axi_AR;
reg [7:0] Mem [1023:0];
reg [31:0] Qint;
wire [9:0] A0;
reg [9:0] A1;
reg read_transaction;
reg burst_transaction;
reg [7:0] burstn;
reg [7:0] len;
assign A0 = {axi_AR[9:2],2'b00};
initial
begin
$readmemh("boot.mem" , Mem , 0);
end
// Read process
always @(posedge clk) Qint[ 7: 0] <= Mem[A1+0];
always @(posedge clk) Qint[15: 8] <= Mem[A1+1];
always @(posedge clk) Qint[23:16] <= Mem[A1+2];
always @(posedge clk) Qint[31:24] <= Mem[A1+3];
assign axi_R = Qint;
// control
always @(posedge clk or negedge rstn)
if (~rstn)
begin
axi_ARREADY <=0;
axi_RVALID <=0;
read_transaction <= 0;
burst_transaction <= 0;
burstn <= 0;
axi_RLAST <= 0;
end
else
begin
if (axi_ARVALID & ~read_transaction &~burst_transaction)
begin
axi_ARREADY <=1;
A1 <= A0;
if ((axi_ARLEN != 8'h0) && (axi_ARBURST == 2'b01)) begin len <= axi_ARLEN; burst_transaction <= 1; end else read_transaction <= 1 ;
end
else
begin
axi_ARREADY <=0;
end
if (axi_RREADY & read_transaction)
begin
axi_RVALID <= 1;
axi_RLAST <= 1;
read_transaction <=0;
end
else
if (axi_RREADY & burst_transaction)
begin
axi_RVALID <=1;
if (burstn == len) begin axi_RLAST <= 1; burst_transaction <=0; end
burstn <= burstn +1;
A1 <= A1 + 4;
end
else
begin
axi_RVALID <=0; axi_RLAST <= 0; burstn <=0;
end
end
endmodule
|
`include "constants.vh"
`default_nettype none
module reorderbuf
(
input wire clk,
input wire reset,
//Write Signal
input wire dp1,
input wire [`RRF_SEL-1:0] dp1_addr,
input wire [`INSN_LEN-1:0] pc_dp1,
input wire storebit_dp1,
input wire dstvalid_dp1,
input wire [`REG_SEL-1:0] dst_dp1,
input wire [`GSH_BHR_LEN-1:0] bhr_dp1,
input wire isbranch_dp1,
input wire dp2,
input wire [`RRF_SEL-1:0] dp2_addr,
input wire [`INSN_LEN-1:0] pc_dp2,
input wire storebit_dp2,
input wire dstvalid_dp2,
input wire [`REG_SEL-1:0] dst_dp2,
input wire [`GSH_BHR_LEN-1:0] bhr_dp2,
input wire isbranch_dp2,
input wire exfin_alu1,
input wire [`RRF_SEL-1:0] exfin_alu1_addr,
input wire exfin_alu2,
input wire [`RRF_SEL-1:0] exfin_alu2_addr,
input wire exfin_mul,
input wire [`RRF_SEL-1:0] exfin_mul_addr,
input wire exfin_ldst,
input wire [`RRF_SEL-1:0] exfin_ldst_addr,
input wire exfin_branch,
input wire [`RRF_SEL-1:0] exfin_branch_addr,
input wire exfin_branch_brcond,
input wire [`ADDR_LEN-1:0] exfin_branch_jmpaddr,
output reg [`RRF_SEL-1:0] comptr,
output wire [`RRF_SEL-1:0] comptr2,
output wire [1:0] comnum,
output wire stcommit,
output wire arfwe1,
output wire arfwe2,
output wire [`REG_SEL-1:0] dstarf1,
output wire [`REG_SEL-1:0] dstarf2,
output wire [`ADDR_LEN-1:0] pc_combranch,
output wire [`GSH_BHR_LEN-1:0] bhr_combranch,
output wire brcond_combranch,
output wire [`ADDR_LEN-1:0] jmpaddr_combranch,
output wire combranch,
input wire [`RRF_SEL-1:0] dispatchptr,
input wire [`RRF_SEL:0] rrf_freenum,
input wire prmiss
);
reg [`RRF_NUM-1:0] finish;
reg [`RRF_NUM-1:0] storebit;
reg [`RRF_NUM-1:0] dstvalid;
reg [`RRF_NUM-1:0] brcond;
reg [`RRF_NUM-1:0] isbranch;
reg [`ADDR_LEN-1:0] inst_pc [0:`RRF_NUM-1];
reg [`ADDR_LEN-1:0] jmpaddr [0:`RRF_NUM-1];
reg [`REG_SEL-1:0] dst [0:`RRF_NUM-1];
reg [`GSH_BHR_LEN-1:0] bhr [0:`RRF_NUM-1];
assign comptr2 = comptr+1;
wire hidp = (comptr > dispatchptr) || (rrf_freenum == 0) ?
1'b1 : 1'b0;
wire com_en1 = ({hidp, dispatchptr} - {1'b0, comptr}) > 0 ? 1'b1 : 1'b0;
wire com_en2 = ({hidp, dispatchptr} - {1'b0, comptr}) > 1 ? 1'b1 : 1'b0;
wire commit1 = com_en1 & finish[comptr];
// wire commit2 = commit1 & com_en2 & finish[comptr2];
wire commit2 =
~(~prmiss & commit1 & isbranch[comptr]) &
~(commit1 & storebit[comptr] & ~prmiss) &
commit1 & com_en2 & finish[comptr2];
assign comnum = {1'b0, commit1} + {1'b0, commit2};
assign stcommit = (commit1 & storebit[comptr] & ~prmiss) |
(commit2 & storebit[comptr2] & ~prmiss);
assign arfwe1 = ~prmiss & commit1 & dstvalid[comptr];
assign arfwe2 = ~prmiss & commit2 & dstvalid[comptr2];
assign dstarf1 = dst[comptr];
assign dstarf2 = dst[comptr2];
assign combranch = (~prmiss & commit1 & isbranch[comptr]) |
(~prmiss & commit2 & isbranch[comptr2]);
assign pc_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
inst_pc[comptr] : inst_pc[comptr2];
assign bhr_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
bhr[comptr] : bhr[comptr2];
assign brcond_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
brcond[comptr] : brcond[comptr2];
assign jmpaddr_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
jmpaddr[comptr] : jmpaddr[comptr2];
always @ (posedge clk) begin
if (reset) begin
comptr <= 0;
end else if (~prmiss) begin
comptr <= comptr + commit1 + commit2;
end
end
always @ (posedge clk) begin
if (reset) begin
finish <= 0;
brcond <= 0;
end else begin
if (dp1)
finish[dp1_addr] <= 1'b0;
if (dp2)
finish[dp2_addr] <= 1'b0;
if (exfin_alu1)
finish[exfin_alu1_addr] <= 1'b1;
if (exfin_alu2)
finish[exfin_alu2_addr] <= 1'b1;
if (exfin_mul)
finish[exfin_mul_addr] <= 1'b1;
if (exfin_ldst)
finish[exfin_ldst_addr] <= 1'b1;
if (exfin_branch) begin
finish[exfin_branch_addr] <= 1'b1;
brcond[exfin_branch_addr] <= exfin_branch_brcond;
jmpaddr[exfin_branch_addr] <= exfin_branch_jmpaddr;
end
end
end // always @ (posedge clk)
always @ (posedge clk) begin
if (dp1) begin
isbranch[dp1_addr] <= isbranch_dp1;
storebit[dp1_addr] <= storebit_dp1;
dstvalid[dp1_addr] <= dstvalid_dp1;
dst[dp1_addr] <= dst_dp1;
bhr[dp1_addr] <= bhr_dp1;
inst_pc[dp1_addr] <= pc_dp1;
end
if (dp2) begin
isbranch[dp2_addr] <= isbranch_dp2;
storebit[dp2_addr] <= storebit_dp2;
dstvalid[dp2_addr] <= dstvalid_dp2;
dst[dp2_addr] <= dst_dp2;
bhr[dp2_addr] <= bhr_dp2;
inst_pc[dp2_addr] <= pc_dp2;
end
end
endmodule // reorderbuf
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:57:49 04/12/2014
// Design Name:
// Module Name: Test_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NIST(
input wire clk,
input wire rst,
input wire rand,
output wire [7:0] test_result
);
assign test_result[7] = 0;
Frequency test1(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[0])
);
Frequency_Block test2(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[1])
);
Runs test3(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[2])
);
Longest_Run_of_Ones test4(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[3])
);
Nonoverlapping_template test7(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[4])
);
Overlapping_template test8(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[5])
);
Cumulative_Sums test13(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[6])
);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram2 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.init_file = "ROM.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.numwords_b = 65536,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "524288"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ROM.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INIT_FILE STRING "ROM.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 16 0 INPUT NODEFVAL "address_a[15..0]"
// Retrieval info: USED_PORT: address_b 0 0 16 0 INPUT NODEFVAL "address_b[15..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address_a 0 0 16 0
// Retrieval info: CONNECT: @address_b 0 0 16 0 address_b 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* bsg_cache_to_dram_ctrl.v
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_to_dram_ctrl
import bsg_cache_pkg::*;
import bsg_dmc_pkg::*;
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, parameter dram_ctrl_addr_width_p=(addr_width_p+lg_num_cache_lp)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
// dram size selection
// {0:256Mb, 1:512Mb, 2:1Gb, 3:2Gb, 4:4Gb}
, input [2:0] dram_size_i
// cache side
, input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i
, input [num_cache_p-1:0] dma_pkt_v_i
, output logic [num_cache_p-1:0] dma_pkt_yumi_o
, output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
// dmc side
, output logic app_en_o
, input app_rdy_i
, output app_cmd_e app_cmd_o
, output logic [dram_ctrl_addr_width_p-1:0] app_addr_o
, output logic app_wdf_wren_o
, input app_wdf_rdy_i
, output logic [data_width_p-1:0] app_wdf_data_o
, output logic [mask_width_lp-1:0] app_wdf_mask_o
, output logic app_wdf_end_o
, input app_rd_data_valid_i
, input [data_width_p-1:0] app_rd_data_i
, input app_rd_data_end_i
);
// round robin for dma pkts
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s dma_pkt;
logic rr_v_lo;
logic [lg_num_cache_lp-1:0] rr_tag_lo;
logic rr_yumi_li;
bsg_round_robin_n_to_1 #(
.width_p(dma_pkt_width_lp)
,.num_in_p(num_cache_p)
,.strict_p(0)
) cache_rr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_pkt_i)
,.v_i(dma_pkt_v_i)
,.yumi_o(dma_pkt_yumi_o)
,.v_o(rr_v_lo)
,.data_o(dma_pkt)
,.tag_o(rr_tag_lo)
,.yumi_i(rr_yumi_li)
);
logic [lg_num_cache_lp-1:0] tag_r, tag_n;
// rx module
//
logic rx_v_li;
logic rx_ready_lo;
bsg_cache_to_dram_ctrl_rx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_ctrl_burst_len_p(dram_ctrl_burst_len_p)
) rx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(rx_v_li)
,.tag_i(tag_r)
,.ready_o(rx_ready_lo)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_ready_i(dma_data_ready_i)
,.app_rd_data_valid_i(app_rd_data_valid_i)
,.app_rd_data_i(app_rd_data_i)
,.app_rd_data_end_i(app_rd_data_end_i)
);
// tx module
//
logic tx_v_li;
logic tx_ready_lo;
bsg_cache_to_dram_ctrl_tx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_ctrl_burst_len_p(dram_ctrl_burst_len_p)
) tx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tx_v_li)
,.tag_i(tag_r)
,.ready_o(tx_ready_lo)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_yumi_o(dma_data_yumi_o)
,.app_wdf_wren_o(app_wdf_wren_o)
,.app_wdf_rdy_i(app_wdf_rdy_i)
,.app_wdf_data_o(app_wdf_data_o)
,.app_wdf_mask_o(app_wdf_mask_o)
,.app_wdf_end_o(app_wdf_end_o)
);
// dma request
//
typedef enum logic {
WAIT,
SEND_REQ
} req_state_e;
req_state_e req_state_r, req_state_n;
logic [addr_width_p-1:0] addr_r, addr_n;
logic write_not_read_r, write_not_read_n;
logic [`BSG_SAFE_CLOG2(num_req_lp)-1:0] req_cnt_r, req_cnt_n;
always_comb begin
app_en_o = 1'b0;
app_cmd_o = WR;
rr_yumi_li = 1'b0;
tag_n = tag_r;
write_not_read_n = write_not_read_r;
rx_v_li = 1'b0;
tx_v_li = 1'b0;
req_state_n = req_state_r;
req_cnt_n = req_cnt_r;
addr_n = addr_r;
case (req_state_r)
WAIT: begin
if (rr_v_lo) begin
rr_yumi_li = 1'b1;
tag_n = rr_tag_lo;
addr_n = dma_pkt.addr;
write_not_read_n = dma_pkt.write_not_read;
req_cnt_n = '0;
req_state_n = SEND_REQ;
end
end
SEND_REQ: begin
app_en_o = (write_not_read_r
? tx_ready_lo
: rx_ready_lo);
app_cmd_o = write_not_read_r
? WR
: RD;
rx_v_li = ~write_not_read_r & rx_ready_lo & app_rdy_i;
tx_v_li = write_not_read_r & tx_ready_lo & app_rdy_i;
addr_n = (app_rdy_i & app_en_o)
? addr_r + (1 << `BSG_SAFE_CLOG2(dram_ctrl_burst_len_p*data_width_p/8))
: addr_r;
req_cnt_n = (app_rdy_i & app_en_o)
? req_cnt_r + 1
: req_cnt_r;
req_state_n = app_rdy_i & app_en_o & (req_cnt_r == num_req_lp-1)
? WAIT
: SEND_REQ;
end
endcase
end
// Append tag_r to top bits of dram address
// tag_r not used when only 1 cache exists
always_comb
case (dram_size_i)
0: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[25-$clog2(num_cache_p)-1:0]});
1: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[26-$clog2(num_cache_p)-1:0]});
2: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[27-$clog2(num_cache_p)-1:0]});
3: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[28-$clog2(num_cache_p)-1:0]});
4: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[29-$clog2(num_cache_p)-1:0]});
default: app_addr_o = {tag_r, addr_r};
endcase
// sequential
//
always_ff @ (posedge clk_i) begin
if (reset_i) begin
req_state_r <= WAIT;
tag_r <= '0;
addr_r <= '0;
req_cnt_r <= '0;
write_not_read_r <= 1'b0;
end
else begin
req_state_r <= req_state_n;
tag_r <= tag_n;
addr_r <= addr_n;
req_cnt_r <= req_cnt_n;
write_not_read_r <= write_not_read_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_dram_ctrl)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:16:56 04/05/2017
// Design Name:
// Module Name: LUTCalc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LUTCalc(
input clk,
input slow_clk,
input [6:0] bpm1_i_lut_dinb,
input [14:0] bpm1_i_lut_addrb,
input bpm1_i_lut_web,
output [6:0] bpm1_i_lut_doutb,
input [6:0] bpm1_q_lut_dinb,
input [14:0] bpm1_q_lut_addrb,
input bpm1_q_lut_web,
output [6:0] bpm1_q_lut_doutb,
input [6:0] bpm2_i_lut_dinb,
input [14:0] bpm2_i_lut_addrb,
input bpm2_i_lut_web,
output [6:0] bpm2_i_lut_doutb,
input [6:0] bpm2_q_lut_dinb,
input [14:0] bpm2_q_lut_addrb,
input bpm2_q_lut_web,
output [6:0] bpm2_q_lut_doutb,
input signed [12:0] q_signal,
output reg signed[20:0] bpm1_i_lut_out,
output reg signed [20:0] bpm1_q_lut_out,
output reg signed [20:0] bpm2_i_lut_out,
output reg signed [20:0] bpm2_q_lut_out,
input LUTcond
);
wire signed [27:0] bpm1_i_lut_out_b, bpm1_q_lut_out_b, bpm2_i_lut_out_b,bpm2_q_lut_out_b;
//reg signed [27:0] bpm1_i_lut_out_a, bpm1_q_lut_out_a, bpm2_i_lut_out_a,bpm2_q_lut_out_a;
//parameter SAMPLE_SPACING=100;
lookuptable1 bpm1_i_lut_inst (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(q_signal), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(bpm1_i_lut_out_b), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(bpm1_i_lut_dinb), // Bus [6 : 0]
.addrb(bpm1_i_lut_addrb), // Bus [14 : 0]
.web(bpm1_i_lut_web), // Bus [0 : 0]
.doutb(bpm1_i_lut_doutb)); // Bus [6 : 0]
lookuptable1 bpm1_q_lut_inst (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(q_signal), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(bpm1_q_lut_out_b), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(bpm1_q_lut_dinb), // Bus [6 : 0]
.addrb(bpm1_q_lut_addrb), // Bus [14 : 0]
.web(bpm1_q_lut_web), // Bus [0 : 0]
.doutb(bpm1_q_lut_doutb)); // Bus [6 : 0]
lookuptable1 bpm2_i_lut_inst (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(q_signal), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(bpm2_i_lut_out_b), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(bpm2_i_lut_dinb), // Bus [6 : 0]
.addrb(bpm2_i_lut_addrb), // Bus [14 : 0]
.web(bpm2_i_lut_web), // Bus [0 : 0]
.doutb(bpm2_i_lut_doutb)); // Bus [6 : 0]
lookuptable1 bpm2_q_lut_inst (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(q_signal), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(bpm2_q_lut_out_b), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(bpm2_q_lut_dinb), // Bus [6 : 0]
.addrb(bpm2_q_lut_addrb), // Bus [14 : 0]
.web(bpm2_q_lut_web), // Bus [0 : 0]
.doutb(bpm2_q_lut_doutb)); // Bus [6 : 0]
always @ (posedge clk) begin
if (LUTcond) begin
bpm1_i_lut_out<=bpm1_i_lut_out_b[20:0];
bpm1_q_lut_out<=bpm1_q_lut_out_b[20:0];
bpm2_i_lut_out<=bpm2_i_lut_out_b[20:0];
bpm2_q_lut_out<=bpm2_q_lut_out_b[20:0];
end
end
endmodule
|
//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//-- **************************************
//-- ** Copyright (C) 2005, Xilinx, Inc. **
//-- ** All Rights Reserved. **
//-- **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD_EP.v
//--
//-- Description: Bus Master Device I/O Endpoint module.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BMD_EP#
(
parameter INTERFACE_WIDTH = 128,
parameter INTERFACE_TYPE = 4'b0010,
parameter FPGA_FAMILY = 8'h14
)
(
clk,
rst_n,
en,
// LocalLink Tx
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_dsc_n,
trn_tsrc_rdy_n,
trn_tdst_dsc_n,
trn_tdst_rdy_n,
trn_tbuf_av,
trn_tstr_n,
// LocalLink Rx
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rdst_rdy_n,
trn_rbar_hit_n,
trn_rnp_ok_n,
trn_rcpl_streaming_n,
bar0_addr_o,
bar0_wr_en_o,
bar0_wr_be_o,
bar0_busy_i,
bar0_rd_d_i,
bar0_rd_be_o,
bar0_wr_d_o,
bar1_wr_en1_i,
bar1_addr1_i,
bar1_be1_i,
bar1_wr_d1_i,
bar1_wr_ack1_n_o,
bar1_wr_en2_i,
bar1_addr2_i,
bar1_be2_i,
bar1_wr_d2_i,
bar1_wr_ack2_n_o,
bar1_wr_en3_i,
bar1_addr3_i,
bar1_be3_i,
bar1_wr_d3_i,
bar1_wr_ack3_n_o,
bar1_arbiter_busy_o,
bar1_wr_busy_o,
rdata_o,
rdata_rd_en_i,
rdata_fifo_empty_o,
tdata_i,
tdata_wr_en_i,
tdata_fifo_full_o,
mwr_start_o,
mwr_done_o,
mrd_start_o,
mrd_done_o,
`ifdef PCIE2_0
pl_directed_link_change,
pl_ltssm_state,
pl_directed_link_width,
pl_directed_link_speed,
pl_directed_link_auton,
pl_upstream_preemph_src,
pl_sel_link_width,
pl_sel_link_rate,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_initial_link_width,
pl_link_upcfg_capable,
pl_lane_reversal_mode,
`endif
// Turnoff access
req_compl_o,
compl_done_o,
cpld_malformed_o,
cpld_rcv_data_size_i,
// Configuration access
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_do,
cfg_interrupt_mmenable,
cfg_interrupt_msienable,
cfg_completer_id,
cfg_ext_tag_en,
cfg_cap_max_lnk_width,
cfg_neg_max_lnk_width,
cfg_cap_max_lnk_speed,
cfg_neg_max_lnk_speed,
cfg_cap_max_payload_size,
cfg_prg_max_payload_size,
cfg_max_rd_req_size,
cfg_msi_enable,
cfg_rd_comp_bound,
cfg_phant_func_en,
cfg_phant_func_supported,
cfg_bus_mstr_enable,
/*************ouyang***************/
//response queue interface
response_queue_empty_i,
response_queue_data_i,
response_queue_rd_en_o ,//read enable signal for response queue
//msix interface
msg_lower_addr_i,
msg_upper_addr_i,
msg_data_i,
// the base addr for response queue
response_queue_addr_i,
//count enable for response queue offset
response_queue_addr_offset_cnt_en_o,
interrupt_block_i,
response_queue_cur_offset_reg_i,
response_queue_addr_offset_i
/**********************************/
);
/*************ouyang***************/
//response queue interface
input response_queue_empty_i;
input [31:0] response_queue_data_i;
output response_queue_rd_en_o ;//read enable signal for response queue
//msix interface
input [31:0] msg_lower_addr_i;
input [31:0] msg_upper_addr_i;
input [31:0] msg_data_i;
// the base addr for response queue
input [31:0] response_queue_addr_i;
//count enable for response queue offset
output response_queue_addr_offset_cnt_en_o;
input interrupt_block_i;
input [31:0] response_queue_cur_offset_reg_i;
input [10:0] response_queue_addr_offset_i;
/**********************************/
input clk;
input rst_n;
input en;
// LocalLink Tx
output [INTERFACE_WIDTH-1:0] trn_td;
output [(INTERFACE_WIDTH/8)-1:0] trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_tsrc_dsc_n;
output trn_tsrc_rdy_n;
input trn_tdst_dsc_n;
input trn_tdst_rdy_n;
input [5:0] trn_tbuf_av;
output trn_tstr_n;
// LocalLink Rx
input [INTERFACE_WIDTH-1:0] trn_rd;
input [(INTERFACE_WIDTH/8)-1:0] trn_rrem_n;
input trn_rsof_n;
input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
output trn_rdst_rdy_n;
input [6:0] trn_rbar_hit_n;
output trn_rnp_ok_n;
output trn_rcpl_streaming_n;
output [6:0] bar0_addr_o;
output bar0_wr_en_o;
output [7:0] bar0_wr_be_o;
input bar0_busy_i;
input [31:0] bar0_rd_d_i;
output [3:0] bar0_rd_be_o;
output [31:0] bar0_wr_d_o;
input bar1_wr_en1_i;
input [6:0] bar1_addr1_i;
input [3:0] bar1_be1_i;
input [31:0] bar1_wr_d1_i;
output bar1_wr_ack1_n_o;
input bar1_wr_en2_i;
input [6:0] bar1_addr2_i;
input [3:0] bar1_be2_i;
input [31:0] bar1_wr_d2_i;
output bar1_wr_ack2_n_o;
input bar1_wr_en3_i;
input [6:0] bar1_addr3_i;
input [3:0] bar1_be3_i;
input [31:0] bar1_wr_d3_i;
output bar1_wr_ack3_n_o;
output bar1_arbiter_busy_o;
output bar1_wr_busy_o;
output [127:0] rdata_o;
input rdata_rd_en_i;
output rdata_fifo_empty_o;
input [127:0] tdata_i;
input tdata_wr_en_i;
output tdata_fifo_full_o;
output mwr_start_o;
output mwr_done_o;
output mrd_start_o;
output mrd_done_o;
`ifdef PCIE2_0
output [1:0] pl_directed_link_change;
input [5:0] pl_ltssm_state;
output [1:0] pl_directed_link_width;
output pl_directed_link_speed;
output pl_directed_link_auton;
output pl_upstream_preemph_src;
input [1:0] pl_sel_link_width;
input pl_sel_link_rate;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input [2:0] pl_initial_link_width;
input pl_link_upcfg_capable;
input [1:0] pl_lane_reversal_mode;
`endif
output req_compl_o;
output compl_done_o;
output cpld_malformed_o;
input [31:0] cpld_rcv_data_size_i;
output cfg_interrupt_n;
input cfg_interrupt_rdy_n;
output cfg_interrupt_assert_n;
output [7:0] cfg_interrupt_di;
input [7:0] cfg_interrupt_do;
input [2:0] cfg_interrupt_mmenable;
input cfg_interrupt_msienable;
input [15:0] cfg_completer_id;
input cfg_ext_tag_en;
input cfg_bus_mstr_enable;
input [5:0] cfg_cap_max_lnk_width;
input [5:0] cfg_neg_max_lnk_width;
input [3:0] cfg_cap_max_lnk_speed;
input [3:0] cfg_neg_max_lnk_speed;
input [2:0] cfg_cap_max_payload_size;
input [2:0] cfg_prg_max_payload_size;
input [2:0] cfg_max_rd_req_size;
input cfg_msi_enable;
input cfg_rd_comp_bound;
input cfg_phant_func_en;
input [1:0] cfg_phant_func_supported;
// Local wires
//wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] req_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl;
wire compl_done;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire init_rst;
wire mwr_start;
wire mwr_int_dis_o;
wire mwr_done;
wire [15:0] mwr_len;
wire [7:0] mwr_tag;
wire [3:0] mwr_lbe;
wire [3:0] mwr_fbe;
wire [31:0] mwr_addr;
wire [31:0] mwr_count;
wire [31:0] mwr_data;
wire [2:0] mwr_tlp_tc_o;
wire mwr_64b_en_o;
wire mwr_phant_func_en1;
wire [7:0] mwr_up_addr_o;
wire mwr_relaxed_order;
wire mwr_nosnoop;
wire [7:0] mwr_wrr_cnt;
wire mrd_start;
wire mrd_int_dis_o;
wire mrd_done;
wire [15:0] mrd_len;
wire [7:0] mrd_tag;
wire [3:0] mrd_lbe;
wire [3:0] mrd_fbe;
wire [31:0] mrd_addr;
wire [31:0] mrd_count;
wire [2:0] mrd_tlp_tc_o;
wire mrd_64b_en_o;
wire mrd_phant_func_en1;
wire [7:0] mrd_up_addr_o;
wire mrd_relaxed_order;
wire mrd_nosnoop;
wire [7:0] mrd_wrr_cnt;
wire [7:0] cpl_ur_found;
wire [7:0] cpl_ur_tag;
wire [31:0] cpld_found;
wire mrd_start_o;
wire cpl_streaming;
wire rd_metering;
wire trn_rnp_ok_n_o;
wire trn_tstr_n_o;
wire cfg_interrupt_legacyclr;
`ifdef PCIE2_0
wire [1:0] pl_directed_link_change_o;
wire [1:0] pl_directed_link_width_o;
wire pl_directed_link_speed_o;
wire pl_directed_link_auton_o;
reg [5:0] pl_ltssm_state_user;
reg [1:0] pl_sel_link_width_user;
reg pl_sel_link_rate_user;
reg pl_link_gen2_capable_user;
reg pl_link_partner_gen2_supported_user;
reg [2:0] pl_initial_link_width_user;
reg pl_link_upcfg_capable_user;
reg [1:0] pl_lane_reversal_mode_user;
`endif
wire [31:0] cpld_data_size;
//wire [15:0] cur_mrd_count;
wire [31:0] mrd_tlp_sent;
wire [31:0] wr_data_sw;
wire [31:0] mrd_size;
wire [31:0] mwr_size;
wire mrd_done_clr;
wire mwr_done_clr;
wire bar1_wr_en0;
wire [6:0] bar1_addr0;
wire [7:0] bar1_wr_be0;
wire [31:0] bar1_wr_d0;
wire [3:0] bar1_rd_be0;
wire [31:0] bar1_rd_d0;
wire bar1_wr_en;
wire [7:0] bar1_wr_be;
wire [31:0] bar1_wr_d;
wire [6:0] bar1_addr;
wire [3:0] bar1_rd_be;
wire [31:0] bar1_rd_d;
wire bar1_wr_busy;
assign mwr_start_o = mwr_start;
assign mrd_start_o = mrd_start;
assign mwr_done_o = mwr_done;
assign mrd_done_o = mrd_done;
assign bar1_wr_busy_o = bar1_wr_busy;
assign trn_rnp_ok_n = trn_rnp_ok_n_o;
assign trn_tstr_n = trn_tstr_n_o;
assign trn_rcpl_streaming_n = ~cpl_streaming;
assign bar0_wr_en_o = (!trn_rbar_hit_n[0]) ? wr_en : 1'b0;
assign bar1_wr_en0 = (!trn_rbar_hit_n[1]) ? wr_en : 1'b0;
assign bar0_addr_o = (!trn_rbar_hit_n[0]) ? req_addr[6:0] : 7'b0;
assign bar1_addr0 = (!trn_rbar_hit_n[1]) ? req_addr[6:0] : 7'b0;
assign bar0_wr_be_o = (!trn_rbar_hit_n[0]) ? wr_be : 8'b0;
assign bar1_wr_be0 = (!trn_rbar_hit_n[1]) ? wr_be : 8'b0;
assign wr_data_sw = { wr_data[7:0] , wr_data[15:8] , wr_data[23:16] , wr_data[31:24] };
assign bar0_wr_d_o = (!trn_rbar_hit_n[0]) ? wr_data_sw : 32'b0;
assign bar1_wr_d0 = (!trn_rbar_hit_n[1]) ? wr_data_sw : 32'b0;
assign wr_busy = (!trn_rbar_hit_n[0]) ? bar0_busy_i : ( (!trn_rbar_hit_n[1]) ? bar1_wr_busy : 1'b0 );
assign bar0_rd_be_o = (!trn_rbar_hit_n[0]) ? rd_be : 4'b0;
assign bar1_rd_be0 = (!trn_rbar_hit_n[1]) ? rd_be : 4'b0;
assign rd_data = (!trn_rbar_hit_n[0]) ? bar0_rd_d_i : ( (!trn_rbar_hit_n[1]) ? bar1_rd_d0 : 32'b0 );
`ifdef PCIE2_0
// Convert to user clock domain to ease timing for gen2 designs
always @(posedge clk) begin
if (!rst_n) begin
pl_ltssm_state_user <= 6'b0;
pl_sel_link_width_user <= 2'b0;
pl_sel_link_rate_user <= 1'b0;
pl_link_gen2_capable_user <= 1'b0;
pl_link_partner_gen2_supported_user <= 1'b0;
pl_initial_link_width_user <= 3'b0;
pl_link_upcfg_capable_user <= 1'b0;
pl_lane_reversal_mode_user <= 2'b0;
end else begin
pl_ltssm_state_user <= pl_ltssm_state;
pl_sel_link_width_user <= pl_sel_link_width;
pl_sel_link_rate_user <= pl_sel_link_rate;
pl_link_gen2_capable_user <= pl_link_gen2_capable;
pl_link_partner_gen2_supported_user <= pl_link_partner_gen2_supported;
pl_initial_link_width_user <= pl_initial_link_width;
pl_link_upcfg_capable_user <= pl_link_upcfg_capable;
pl_lane_reversal_mode_user <= pl_lane_reversal_mode;
end
end
`endif
//
// BAR1 Wrapper:
//
BAR1_WRAPPER#(
.INTERFACE_TYPE(INTERFACE_TYPE),
.FPGA_FAMILY(FPGA_FAMILY)
)
BAR1_WRAP (
.clk(clk), // I
.rst_n(rst_n), // I
.en(en),
.cfg_cap_max_lnk_width(cfg_cap_max_lnk_width), // I [5:0]
.cfg_neg_max_lnk_width(cfg_neg_max_lnk_width), // I [5:0]
.cfg_cap_max_lnk_speed(cfg_cap_max_lnk_speed), // I [3:0]
.cfg_neg_max_lnk_speed(cfg_neg_max_lnk_speed), // I [3:0]
.cfg_cap_max_payload_size(cfg_cap_max_payload_size), // I [2:0]
.cfg_prg_max_payload_size(cfg_prg_max_payload_size), // I [2:0]
.cfg_max_rd_req_size(cfg_max_rd_req_size), // I [2:0]
.a_i(bar1_addr), // I [6:0]
// Read Port
.rd_be_i(bar1_rd_be), // I [3:0]
.rd_d_o(bar1_rd_d), // O [31:0]
// Write Port
.wr_be_i(bar1_wr_be), // I [7:0]
.wr_d_i(bar1_wr_d), // I [31:0]
.wr_en_i(bar1_wr_en), // I
.wr_busy_o(bar1_wr_busy), // O
.init_rst_o(init_rst), // O
.mrd_start_o(mrd_start), // O
.mrd_done_i(mrd_done), // O
.mrd_addr_o(mrd_addr), // O [31:0]
.mrd_len_o(mrd_len), // O [31:0]
.mrd_size_o(mrd_size), // O [31:0]
.mrd_tlp_tc_o(mrd_tlp_tc_o), // O [2:0]
.mrd_64b_en_o(mrd_64b_en_o), // O
.mrd_phant_func_dis1_o(mrd_phant_func_dis1), // O
.mrd_up_addr_o(mrd_up_addr_o), // O [7:0]
.mrd_relaxed_order_o(mrd_relaxed_order), // O
.mrd_nosnoop_o(mrd_nosnoop), // O
.mrd_wrr_cnt_o(mrd_wrr_cnt), // O [7:0]
.mrd_done_clr(mrd_done_clr),
.mwr_start_o(mwr_start), // O
.mwr_done_i(mwr_done), // I
.mwr_addr_o(mwr_addr), // O [31:0]
.mwr_len_o(mwr_len), // O [31:0]
.mwr_size_o(mwr_size), // O [31:0]
.mwr_tlp_tc_o(mwr_tlp_tc_o), // O [2:0]
.mwr_64b_en_o(mwr_64b_en_o), // O
.mwr_phant_func_dis1_o(mwr_phant_func_dis1), // O
.mwr_up_addr_o(mwr_up_addr_o), // O [7:0]
.mwr_relaxed_order_o(mwr_relaxed_order), // O
.mwr_nosnoop_o(mwr_nosnoop), // O
.mwr_wrr_cnt_o(mwr_wrr_cnt), // O [7:0]
.mwr_done_clr(mwr_done_clr),
.cpl_ur_found_i(cpl_ur_found), // I [7:0]
.cpl_ur_tag_i(cpl_ur_tag), // I [7:0]
`ifdef PCIE2_0
.pl_directed_link_change( pl_directed_link_change ),
.pl_ltssm_state( pl_ltssm_state_user ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_upstream_preemph_src( pl_upstream_preemph_src ),
.pl_sel_link_width( pl_sel_link_width_user ),
.pl_sel_link_rate( pl_sel_link_rate_user ),
.pl_link_gen2_capable( pl_link_gen2_capable_user ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported_user ),
.pl_initial_link_width( pl_initial_link_width_user ),
.pl_link_upcfg_capable( pl_link_upcfg_capable_user ),
.pl_lane_reversal_mode( pl_lane_reversal_mode_user ),
.pl_width_change_err( pl_width_change_err ),
.pl_speed_change_err( pl_speed_change_err ),
.clr_pl_width_change_err( clr_pl_width_change_err ),
.clr_pl_speed_change_err( clr_pl_speed_change_err ),
.clear_directed_speed_change( clear_directed_speed_change ),
`endif
.cpld_found_i(cpld_found), // I [31:0]
.cpld_data_size_i(cpld_rcv_data_size_i), // I [31:0]
.cpld_malformed_i(cpld_malformed_o), // I
.cpl_streaming_o(cpl_streaming), // O
.rd_metering_o(rd_metering), // O
.cfg_interrupt_di(cfg_interrupt_di), // O
.cfg_interrupt_do(cfg_interrupt_do), // I
.cfg_interrupt_mmenable(cfg_interrupt_mmenable), // I
.cfg_interrupt_msienable(cfg_interrupt_msienable), // I
.cfg_interrupt_legacyclr(cfg_interrupt_legacyclr), // O
.trn_rnp_ok_n_o(trn_rnp_ok_n_o), // O
.trn_tstr_n_o ( trn_tstr_n_o ) // O
);
`ifdef PCIE2_0
BMD_GEN2 BMD_GEN2_I (
.pl_directed_link_change(pl_directed_link_change),
.pl_directed_link_width(pl_directed_link_width),
.pl_directed_link_speed(pl_directed_link_speed),
.pl_directed_link_auton(pl_directed_link_auton),
.pl_sel_link_width(pl_sel_link_width_user),
.pl_sel_link_rate(pl_sel_link_rate_user),
.pl_ltssm_state( pl_ltssm_state_user ),
.clk(clk),
.rst_n(rst_n),
.pl_width_change_err(pl_width_change_err),
.pl_speed_change_err(pl_speed_change_err),
.clr_pl_width_change_err(clr_pl_width_change_err),
.clr_pl_speed_change_err(clr_pl_speed_change_err),
.clear_directed_speed_change(clear_directed_speed_change)
);
`endif
//
// Local-Link Receive Controller :
//
BMD_RX_ENGINE EP_RX (
.clk(clk), // I
.rst_n(rst_n), // I
.init_rst_i(init_rst), // I
// LocalLink Rx
.trn_rd(trn_rd), // I [63/31:0]
.trn_rrem_n(trn_rrem_n), // I [7:0]
.trn_rsof_n(trn_rsof_n), // I
.trn_reof_n(trn_reof_n), // I
.trn_rsrc_rdy_n(trn_rsrc_rdy_n), // I
.trn_rsrc_dsc_n(trn_rsrc_dsc_n), // I
.trn_rdst_rdy_n(trn_rdst_rdy_n), // O
.trn_rbar_hit_n (trn_rbar_hit_n), // I [6:0]
// Handshake with Tx engine
.req_compl_o(req_compl), // O
.compl_done_i(compl_done), // I
.addr_o(req_addr), // O [10:0]
.req_tc_o(req_tc), // O [2:0]
.req_td_o(req_td), // O
.req_ep_o(req_ep), // O
.req_attr_o(req_attr), // O [1:0]
.req_len_o(req_len), // O [9:0]
.req_rid_o(req_rid), // O [15:0]
.req_tag_o(req_tag), // O [7:0]
.req_be_o(req_be), // O [7:0]
// Memory Write Port
.wr_be_o(wr_be), // O [7:0]
.wr_data_o(wr_data), // O [31:0]
.wr_en_o(wr_en), // O
.wr_busy_i(wr_busy), // I
.rdata_o(rdata_o),
.rdata_rd_en_i(rdata_rd_en_i),
.rdata_fifo_empty_o(rdata_fifo_empty_o),
.cpl_ur_found_o(cpl_ur_found), // O [7:0]
.cpl_ur_tag_o(cpl_ur_tag), // O [7:0]
.mrd_size_i(mrd_size),
.mrd_done_o(/*mrd_done*/),
.mrd_done_clr(mrd_done_clr),
.cpld_found_o(cpld_found), // O [31:0]
.cpld_data_size_o(/*cpld_data_size*/), // O [31:0]
.cpld_malformed_o(cpld_malformed_o) // O
);
//
// Local-Link Transmit Controller
//
BMD_TX_ENGINE EP_TX (
.clk(clk), // I
.rst_n(rst_n), // I
// LocalLink Tx
.trn_td(trn_td), // O [63/31:0]
.trn_trem_n(trn_trem_n), // O [7:0]
.trn_tsof_n(trn_tsof_n), // O
.trn_teof_n(trn_teof_n), // O
.trn_tsrc_dsc_n(trn_tsrc_dsc_n), // O
.trn_tsrc_rdy_n(trn_tsrc_rdy_n), // O
.trn_tdst_dsc_n(trn_tdst_dsc_n), // I
.trn_tdst_rdy_n(trn_tdst_rdy_n), // I
.trn_tbuf_av(trn_tbuf_av), // I [5:0]
// Handshake with Rx engine
.req_compl_i(req_compl), // I
.compl_done_o(compl_done), // 0
.req_tc_i(req_tc), // I [2:0]
.req_td_i(req_td), // I
.req_ep_i(req_ep), // I
.req_attr_i(req_attr), // I [1:0]
.req_len_i(req_len), // I [9:0]
.req_rid_i(req_rid), // I [15:0]
.req_tag_i(req_tag), // I [7:0]
.req_be_i(req_be), // I [7:0]
.req_addr_i(req_addr), // I [10:0]
// Read Port
.rd_addr_o(), // I [10:0]
.rd_be_o(rd_be), // I [3:0]
.rd_data_i(rd_data), // O [31:0]
// Initiator Controls
.init_rst_i(init_rst), // I
.mrd_start_i(mrd_start_fc), // I
.mrd_addr_i(mrd_addr), // I [31:0]
.mrd_len_i(mrd_len), // I [31:0]
.mrd_size_i(mrd_size), // I [31:0]
.mrd_tlp_tc_i(mrd_tlp_tc_o), // I [2:0]
.mrd_64b_en_i(mrd_64b_en_o), // I
.mrd_phant_func_dis1_i(1'b1 /*mrd_phant_func_dis1*/), // I
.mrd_up_addr_i(mrd_up_addr_o), // I [7:0]
.mrd_lbe_i(4'hF),
.mrd_fbe_i(4'hF),
.mrd_tag_i(8'h0),
//.cur_mrd_count_o(cur_mrd_count), // O[15:0]
.mrd_tlp_sent_o(mrd_tlp_sent),
.mrd_relaxed_order_i(mrd_relaxed_order), // I
.mrd_nosnoop_i(mrd_nosnoop), // I
.mrd_wrr_cnt_i(mrd_wrr_cnt), // I [7:0]
.mrd_done_clr(mrd_done_clr),
.mrd_done(mrd_done),
.mwr_start_i(mwr_start_fc), // I
.mwr_done_o(mwr_done), // O
.mwr_addr_i(mwr_addr), // I [31:0]
.mwr_len_i(mwr_len), // I [31:0]
.mwr_size_i(mwr_size), // I [31:0]
.mwr_tlp_tc_i(mwr_tlp_tc_o), // I [2:0]
.mwr_64b_en_i(mwr_64b_en_o), // I
.mwr_phant_func_dis1_i(1'b1 /*mwr_phant_func_dis1*/), // I
.mwr_up_addr_i(mwr_up_addr_o), // I [7:0]
.mwr_lbe_i(4'hF),
.mwr_fbe_i(4'hF),
.mwr_tag_i(8'h0),
.mwr_relaxed_order_i(mwr_relaxed_order), // I
.mwr_nosnoop_i(mwr_nosnoop), // I
.mwr_wrr_cnt_i(mwr_wrr_cnt), // I [7:0]
.mwr_done_clr(mwr_done_clr),
.tdata_i(tdata_i),
.tdata_wr_en_i(tdata_wr_en_i),
.tdata_fifo_full_o(tdata_fifo_full_o),
.completer_id_i(cfg_completer_id), // I [15:0]
.cfg_ext_tag_en_i(cfg_ext_tag_en), // I
.cfg_bus_mstr_enable_i(cfg_bus_mstr_enable), // I
.cfg_phant_func_en_i(cfg_phant_func_en), // I
.cfg_phant_func_supported_i(cfg_phant_func_supported), // I [1:0]
/*************ouyang***************/
//response queue interface
.response_queue_empty_i(response_queue_empty_i),
.response_queue_data_i(response_queue_data_i),
.response_queue_rd_en_o(response_queue_rd_en_o) ,//read enable signal for response queue
//msix interface
.msg_lower_addr_i(msg_lower_addr_i),
.msg_upper_addr_i(msg_upper_addr_i),
.msg_data_i(msg_data_i),
// the base addr for response queue
.response_queue_addr_i(response_queue_addr_i),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_o(response_queue_addr_offset_cnt_en_o),
.interrupt_block_i(interrupt_block_i),
.response_queue_cur_offset_reg_i(response_queue_cur_offset_reg_i),
.response_queue_addr_offset_i(response_queue_addr_offset_i)
/**********************************/
);
assign req_compl_o = req_compl;
assign compl_done_o = compl_done;
//
// Read Transmit Throttle Unit :
//
FLOW_CONTROLLER EP_FC(
.clk(clk),
.rst_n(rst_n),
.init_rst_i(init_rst),
.mrd_start_i(mrd_start),
.mrd_len_i(mrd_len),
//.mrd_cur_rd_count_i(cur_mrd_count),
.mrd_tlp_sent_i(mrd_tlp_sent),
.cpld_data_size_i(cpld_rcv_data_size_i),
.cfg_rd_comp_bound_i(),
.rd_metering_i(rd_metering),
.mwr_start_i(mwr_start),
.trn_tbuf_av_i(trn_tbuf_av),
.mrd_start_fc_o(mrd_start_fc),
.mwr_start_fc_o(mwr_start_fc)
);
//
// BAR1 Write Arbiter
//
BAR1_WR_ARBITER BAR1_ARBITER(
.rst_n(rst_n),
.init_rst_i(init_rst),
//write port 0
.wr_en0_i(bar1_wr_en0),
.addr0_i(bar1_addr0),
.wr_be0_i(bar1_wr_be0[3:0]),
.wr_d0_i(bar1_wr_d0),
//write port 1
.wr_en1_i(bar1_wr_en1_i),
.addr1_i(bar1_addr1_i),
.wr_be1_i(bar1_be1_i),
.wr_d1_i(bar1_wr_d1_i),
//write port 2
.wr_en2_i(bar1_wr_en2_i),
.addr2_i(bar1_addr2_i),
.wr_be2_i(bar1_be2_i),
.wr_d2_i(bar1_wr_d2_i),
//write port 3
.wr_en3_i(bar1_wr_en3_i),
.addr3_i(bar1_addr3_i),
.wr_be3_i(bar1_be3_i),
.wr_d3_i(bar1_wr_d3_i),
//read port 0
.rd_be0_i(bar1_rd_be0),
.rd_d0_o(bar1_rd_d0),
//write port arbitration output
.wr_en_o(bar1_wr_en),
.addr_o(bar1_addr),
.wr_be_o(bar1_wr_be[3:0]),
.wr_d_o(bar1_wr_d),
//write port feedback signals
.ack0_n_o(bar1_wr_ack0_n),
.ack1_n_o(bar1_wr_ack1_n_o),
.ack2_n_o(bar1_wr_ack2_n_o),
.ack3_n_o(bar1_wr_ack3_n_o),
.rd_be_o(bar1_rd_be),
.rd_d_i(bar1_rd_d),
.busy_o(bar1_arbiter_busy_o)
);
endmodule // BMD_EP
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core top level. ////
//// ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
//
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_top (
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
int_o, // interrupt request
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
parameter uart_data_width = `UART_DATA_WIDTH;
parameter uart_addr_width = `UART_ADDR_WIDTH;
input wb_clk_i;
// WISHBONE interface
input wb_rst_i;
input [uart_addr_width-1:0] wb_adr_i;
input [uart_data_width-1:0] wb_dat_i;
output [uart_data_width-1:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_ack_o;
output int_o;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire [uart_addr_width-1:0] wb_adr_i;
wire [uart_data_width-1:0] wb_dat_i;
wire [uart_data_width-1:0] wb_dat_o;
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [uart_addr_width-1:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface wires
wire [3:0] ier;
wire [3:0] iir;
wire [1:0] fcr;
wire [4:0] mcr;
wire [7:0] lcr;
wire [7:0] msr;
wire [7:0] lsr;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
`endif
`ifdef DATA_BUS_WIDTH_8
//// WISHBONE interface module
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`else
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_sel_i(wb_sel_i),
.wb_dat32_o(wb_dat32_o),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`endif
// Registers
uart_regs regs(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
.ier(ier),
.iir(iir),
.fcr(fcr),
.mcr(mcr),
.lcr(lcr),
.msr(msr),
.lsr(lsr),
.rf_count(rf_count),
.tf_count(tf_count),
.tstate(tstate),
.rstate(rstate),
`endif
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
`endif
);
`ifdef DATA_BUS_WIDTH_8
`else
uart_debug_if dbg(/*AUTOINST*/
// Outputs
.wb_dat32_o (wb_dat32_o[31:0]),
// Inputs
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
.ier (ier[3:0]),
.iir (iir[3:0]),
.fcr (fcr[1:0]),
.mcr (mcr[4:0]),
.lcr (lcr[7:0]),
.msr (msr[7:0]),
.lsr (lsr[7:0]),
.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
.tstate (tstate[2:0]),
.rstate (rstate[3:0]));
`endif
initial
begin
`ifdef DATA_BUS_WIDTH_8
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
`else
$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
`endif
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
end
endmodule
|
// creates an array of shift registers, with independently
// controlled three input muxes,
// 0=keep value, 1=get prev value,2=set new value
//
//
`include "bsg_defines.v"
module bsg_fifo_shift_datapath #(parameter `BSG_INV_PARAM( width_p )
,parameter `BSG_INV_PARAM(els_p )
,parameter default_p = { (width_p) {1'b0} }
)
(input clk_i
, input [width_p-1:0] data_i
, input [els_p-1:0][1:0] sel_i
, output [width_p-1:0] data_o
);
genvar i;
logic [els_p:0][width_p-1:0] r, r_n;
assign r[els_p] = default_p;
for (i = 0; i < els_p; i=i+1)
begin: el
always_comb
begin
unique case (sel_i[i])
2'b01:
r_n[i] = r[i+1];
2'b10:
r_n[i] = data_i;
default:
r_n[i] = r[i];
endcase
end
always_ff @(posedge clk_i)
r[i] <= r_n[i];
end
assign data_o = r[0];
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_shift_datapath)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEII" inclk0_input_frequency=20000 intended_device_family="Cyclone II" operation_mode="normal" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED"
//VERSION_BEGIN 12.0 cbx_altclkbuf 2012:05:31:20:08:02:SJ cbx_altiobuf_bidir 2012:05:31:20:08:02:SJ cbx_altiobuf_in 2012:05:31:20:08:02:SJ cbx_altiobuf_out 2012:05:31:20:08:02:SJ cbx_altpll 2012:05:31:20:08:02:SJ cbx_altpll_avalon 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_counter 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_lpm_shiftreg 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module pll_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //pll_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module pll_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
pll_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //pll_stdsync_sv6
//altpll CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEII" inclk0_input_frequency=20000 intended_device_family="Cyclone II" operation_mode="normal" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" areset clk inclk locked
//VERSION_BEGIN 12.0 cbx_altclkbuf 2012:05:31:20:08:02:SJ cbx_altiobuf_bidir 2012:05:31:20:08:02:SJ cbx_altiobuf_in 2012:05:31:20:08:02:SJ cbx_altiobuf_out 2012:05:31:20:08:02:SJ cbx_altpll 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_counter 2012:05:31:20:08:02:SJ cbx_lpm_decode 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_stratixiii 2012:05:31:20:08:02:SJ cbx_stratixv 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = altpll 1 reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module pll
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [5:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
pll_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
altpll sd1
(
.activeclock(),
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(),
.icdrclk(),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sd1.clk0_divide_by = 2,
sd1.clk0_duty_cycle = 50,
sd1.clk0_multiply_by = 1,
sd1.clk0_phase_shift = "0",
sd1.compensate_clock = "CLK0",
sd1.inclk0_input_frequency = 20000,
sd1.operation_mode = "normal",
sd1.port_clk0 = "PORT_USED",
sd1.port_clk1 = "PORT_UNUSED",
sd1.port_clk2 = "PORT_UNUSED",
sd1.port_clk3 = "PORT_UNUSED",
sd1.port_clk4 = "PORT_UNUSED",
sd1.port_clk5 = "PORT_UNUSED",
sd1.port_extclk0 = "PORT_UNUSED",
sd1.port_extclk1 = "PORT_UNUSED",
sd1.port_extclk2 = "PORT_UNUSED",
sd1.port_extclk3 = "PORT_UNUSED",
sd1.port_inclk1 = "PORT_UNUSED",
sd1.port_phasecounterselect = "PORT_UNUSED",
sd1.port_phasedone = "PORT_UNUSED",
sd1.port_scandata = "PORT_UNUSED",
sd1.port_scandataout = "PORT_UNUSED",
sd1.intended_device_family = "Cyclone II",
sd1.lpm_type = "altpll";
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //pll
//VALID FILE
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: nf2_dma_que_intfc.v
// Project: NetFPGA 2.1 (NF2 Control Network FPGA)
// Description: DMA interface to cpu queues
//
// Provides pkt transfer to/from cpu queues
//
/////////////////////////////////////////////////////////////////////////
//
// txfifo_rd_data includes:
// 1 bit. 1'b 0 for "data format"; 1'b 1 for "req format"
// 1 bit. EOP in "data format". 1'b 1 indicates the last pkt word.
// 1'b 0 indicates this is not the last pkt word.
// in "req format", 1'b 0 for "dma tx", 1'b 1 for "dma rx"
// 2 bits. bytecnt in "data format". 2'b 00: 4 bytes; 2'b 01: 1 byte;
// 2'b 10: 2 bytes; 2'b 11: 3 bytes.
// always 2'b 00 in "req format"
// 32 bits. pkt data in "data format".
// {28'b 0, 4-bits queue_id} in "req format"
//
// rxfifo_wr_data includes:
// 1 bit. EOP. 1'b 1 indicates the last pkt word.
// 1'b 0 indicates this is not the last pkt word.
// 2 bits. bytecnt. 2'b 00: 4 bytes; 2'b 01: 1 byte;
// 2'b 10: 2 bytes; 2'b 11: 3 bytes.
// 32 bits. pkt data .
//
//////////////////////////////////////////////////////////////////
module nf2_dma_que_intfc
#( parameter NUM_CPU_QUEUES = 4,
parameter DMA_DATA_WIDTH = 32,
parameter DMA_CTRL_WIDTH=DMA_DATA_WIDTH/8,
parameter USER_DATA_PATH_WIDTH=64,
parameter CPCI_NF2_DATA_WIDTH=32
)
(
// ---- signals to/from CPU rx queue 0
output reg cpu_q_dma_rd_0,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data_0,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl_0,
// ---- signals to/from CPU rx queue 1
output reg cpu_q_dma_rd_1,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data_1,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl_1,
// ---- signals to/from CPU rx queue 2
output reg cpu_q_dma_rd_2,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data_2,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl_2,
// ---- signals to/from CPU rx queue 3
output reg cpu_q_dma_rd_3,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data_3,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl_3,
// signals to/from CPU tx queues
input [NUM_CPU_QUEUES-1:0] cpu_q_dma_nearly_full,
// signals to/from CPU tx queue 0
output reg cpu_q_dma_wr_0,
output reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_0,
output reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_0,
// signals to/from CPU tx queue 1
output reg cpu_q_dma_wr_1,
output reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_1,
output reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_1,
// signals to/from CPU tx queue 2
output reg cpu_q_dma_wr_2,
output reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_2,
output reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_2,
// signals to/from CPU tx queue 3
output reg cpu_q_dma_wr_3,
output reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_3,
output reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_3,
// --- signals to/from nf2_dma_sync
input txfifo_empty,
input [DMA_DATA_WIDTH +3:0] txfifo_rd_data,
output reg txfifo_rd_inc,
input rxfifo_full,
input rxfifo_nearly_full,
output reg rxfifo_wr,
output reg [DMA_DATA_WIDTH +2:0] rxfifo_wr_data,
//--- misc
input enable_dma,
input reset,
input clk
);
reg [3:0] queue_id, queue_id_nxt;
reg [DMA_DATA_WIDTH-1:0] dma_wr_data;
reg [DMA_CTRL_WIDTH-1:0] dma_wr_ctrl;
reg dma_rd_vld, dma_rd_vld_nxt;
reg [DMA_DATA_WIDTH-1:0] dma_rd_data;
reg [DMA_CTRL_WIDTH-1:0] dma_rd_ctrl;
// signals to/from CPU tx queue 0
reg cpu_q_dma_wr_0_nxt;
reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_0_nxt;
reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_0_nxt;
// signals to/from CPU tx queue 1
reg cpu_q_dma_wr_1_nxt;
reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_1_nxt;
reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_1_nxt;
// signals to/from CPU tx queue 2
reg cpu_q_dma_wr_2_nxt;
reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_2_nxt;
reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_2_nxt;
// signals to/from CPU tx queue 3
reg cpu_q_dma_wr_3_nxt;
reg [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data_3_nxt;
reg [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl_3_nxt;
// support a max "USER_DATA_PATH_WIDTH / DMA_DATA_WIDTH" ratio of 8
reg [3:0] align_cnt, align_cnt_nxt;
wire [3:0] align_cnt_plus_1 =
((align_cnt+'h 1)==(USER_DATA_PATH_WIDTH / DMA_DATA_WIDTH)) ?
'h 0 : align_cnt+'h 1;
reg [2:0] state, state_nxt;
parameter IDLE_STATE = 3'h 0,
TX_STATE = 3'h 1,
TX_PAD_STATE = 3'h 2,
RX_STATE = 3'h 3,
RX_PAD_STATE = 3'h 4;
always @(*) begin
state_nxt = state;
queue_id_nxt = queue_id;
dma_rd_vld_nxt = 1'b 0;
align_cnt_nxt = align_cnt;
txfifo_rd_inc = 1'b 0;
dma_wr_ctrl = 'h 0;
dma_wr_data = 'h 0;
cpu_q_dma_wr_0_nxt = 1'b 0;
cpu_q_dma_wr_data_0_nxt = 'h 0;
cpu_q_dma_wr_ctrl_0_nxt = 'h 0;
cpu_q_dma_wr_1_nxt = 1'b 0;
cpu_q_dma_wr_data_1_nxt = 'h 0;
cpu_q_dma_wr_ctrl_1_nxt = 'h 0;
cpu_q_dma_wr_2_nxt = 1'b 0;
cpu_q_dma_wr_data_2_nxt = 'h 0;
cpu_q_dma_wr_ctrl_2_nxt = 'h 0;
cpu_q_dma_wr_3_nxt = 1'b 0;
cpu_q_dma_wr_data_3_nxt = 'h 0;
cpu_q_dma_wr_ctrl_3_nxt = 'h 0;
cpu_q_dma_rd_0 = 1'b 0;
cpu_q_dma_rd_1 = 1'b 0;
cpu_q_dma_rd_2 = 1'b 0;
cpu_q_dma_rd_3 = 1'b 0;
dma_rd_data = 'h 0;
dma_rd_ctrl = 'h 0;
rxfifo_wr = 1'b 0;
rxfifo_wr_data = 'h 0;
case (state)
IDLE_STATE:
if (enable_dma) begin
if (! txfifo_empty) begin
txfifo_rd_inc = 1'b 1;
case (txfifo_rd_data[DMA_DATA_WIDTH +3])
1'b 0: begin
//synthesis translate_off
// Don't display an error message immediately as we may
// have seen the transition on the empty signal before the
// data signal has transitioned
#1 if (txfifo_rd_data[DMA_DATA_WIDTH +3]) begin
$display("%t %m ERROR: expect req format, but got data format!", $time);
end
//synthesis translate_on
end
1'b 1: begin
align_cnt_nxt = 'h 0;
queue_id_nxt = txfifo_rd_data;
case (txfifo_rd_data[DMA_DATA_WIDTH +2])
1'b 0: begin
//DMA tx
state_nxt = TX_STATE;
end
1'b 1: begin
//DMA rx
state_nxt = RX_STATE;
end
endcase // case(txfifo_rd_data[DMA_DATA_WIDTH +2])
end // case: 1'b 1
endcase // case(txfifo_rd_data[DMA_DATA_WIDTH +3])
end // if (! txfifo_empty)
end // if (enable_dma)
TX_STATE:
if (! txfifo_empty) begin
case (txfifo_rd_data[DMA_DATA_WIDTH +2])
1'b 0: //not EOP
dma_wr_ctrl = 'b 0;
1'b 1: begin
//EOP
case (txfifo_rd_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH])
2'b 00:
dma_wr_ctrl = 'b 1000;
2'b 01:
dma_wr_ctrl = 'b 0001;
2'b 10:
dma_wr_ctrl = 'b 0010;
2'b 11:
dma_wr_ctrl = 'b 0100;
endcase//case(txfifo_rd_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH])
end // case: 1'b 1
endcase // case(txfifo_rd_data[DMA_DATA_WIDTH +2])
dma_wr_data = txfifo_rd_data[DMA_DATA_WIDTH -1:0];
case (queue_id)
4'h 0:
if (! cpu_q_dma_nearly_full[0]) begin
txfifo_rd_inc = 1'b 1;
cpu_q_dma_wr_0_nxt = 1'b 1;
cpu_q_dma_wr_data_0_nxt = dma_wr_data;
cpu_q_dma_wr_ctrl_0_nxt = dma_wr_ctrl;
align_cnt_nxt = align_cnt_plus_1;
if (| dma_wr_ctrl) begin
if (align_cnt_nxt != 'h 0)
state_nxt = TX_PAD_STATE;
else
state_nxt = IDLE_STATE;
end
end
4'h 1:
if (! cpu_q_dma_nearly_full[1]) begin
txfifo_rd_inc = 1'b 1;
cpu_q_dma_wr_1_nxt = 1'b 1;
cpu_q_dma_wr_data_1_nxt = dma_wr_data;
cpu_q_dma_wr_ctrl_1_nxt = dma_wr_ctrl;
align_cnt_nxt = align_cnt_plus_1;
if (| dma_wr_ctrl) begin
if (align_cnt_nxt != 'h 0)
state_nxt = TX_PAD_STATE;
else
state_nxt = IDLE_STATE;
end
end
4'h 2:
if (! cpu_q_dma_nearly_full[2]) begin
txfifo_rd_inc = 1'b 1;
cpu_q_dma_wr_2_nxt = 1'b 1;
cpu_q_dma_wr_data_2_nxt = dma_wr_data;
cpu_q_dma_wr_ctrl_2_nxt = dma_wr_ctrl;
align_cnt_nxt = align_cnt_plus_1;
if (| dma_wr_ctrl) begin
if (align_cnt_nxt != 'h 0)
state_nxt = TX_PAD_STATE;
else
state_nxt = IDLE_STATE;
end
end
4'h 3:
if (! cpu_q_dma_nearly_full[3]) begin
txfifo_rd_inc = 1'b 1;
cpu_q_dma_wr_3_nxt = 1'b 1;
cpu_q_dma_wr_data_3_nxt = dma_wr_data;
cpu_q_dma_wr_ctrl_3_nxt = dma_wr_ctrl;
align_cnt_nxt = align_cnt_plus_1;
if (| dma_wr_ctrl) begin
if (align_cnt_nxt != 'h 0)
state_nxt = TX_PAD_STATE;
else
state_nxt = IDLE_STATE;
end
end
default: begin
// unknown queue_id. dequeue the pkt data anyway.
txfifo_rd_inc = 1'b 1;
if (| dma_wr_ctrl) state_nxt = IDLE_STATE;
end
endcase // case(oq_queue_id)
end // if (! txfifo_empty)
TX_PAD_STATE: begin
case (queue_id)
4'h 0:
if (! cpu_q_dma_nearly_full[0]) begin
cpu_q_dma_wr_0_nxt = 1'b 1;
align_cnt_nxt = align_cnt_plus_1;
if (align_cnt_nxt == 'h 0)
state_nxt = IDLE_STATE;
end
4'h 1:
if (! cpu_q_dma_nearly_full[1]) begin
cpu_q_dma_wr_1_nxt = 1'b 1;
align_cnt_nxt = align_cnt_plus_1;
if (align_cnt_nxt == 'h 0)
state_nxt = IDLE_STATE;
end
4'h 2:
if (! cpu_q_dma_nearly_full[2]) begin
cpu_q_dma_wr_2_nxt = 1'b 1;
align_cnt_nxt = align_cnt_plus_1;
if (align_cnt_nxt == 'h 0)
state_nxt = IDLE_STATE;
end
4'h 3:
if (! cpu_q_dma_nearly_full[3]) begin
cpu_q_dma_wr_3_nxt = 1'b 1;
align_cnt_nxt = align_cnt_plus_1;
if (align_cnt_nxt == 'h 0)
state_nxt = IDLE_STATE;
end
endcase // case(queue_id)
end // case: TX_PAD_STATE
RX_STATE: begin
if (!rxfifo_nearly_full) begin
// note that cpu queues are fall-thru queues.
// So data are available now
case (queue_id)
4'h 0: cpu_q_dma_rd_0 = 1'b 1;
4'h 1: cpu_q_dma_rd_1 = 1'b 1;
4'h 2: cpu_q_dma_rd_2 = 1'b 1;
4'h 3: cpu_q_dma_rd_3 = 1'b 1;
endcase // case(oq_queue_id)
align_cnt_nxt = align_cnt_plus_1;
case (queue_id)
4'h 0: begin
dma_rd_data = cpu_q_dma_rd_data_0;
dma_rd_ctrl = cpu_q_dma_rd_ctrl_0;
end
4'h 1: begin
dma_rd_data = cpu_q_dma_rd_data_1;
dma_rd_ctrl = cpu_q_dma_rd_ctrl_1;
end
4'h 2: begin
dma_rd_data = cpu_q_dma_rd_data_2;
dma_rd_ctrl = cpu_q_dma_rd_ctrl_2;
end
4'h 3: begin
dma_rd_data = cpu_q_dma_rd_data_3;
dma_rd_ctrl = cpu_q_dma_rd_ctrl_3;
end
endcase // case(oq_queue_id)
rxfifo_wr = 1'b 1;
rxfifo_wr_data[DMA_DATA_WIDTH -1:0] = dma_rd_data;
if (dma_rd_ctrl == 'h 0) begin
//not EOP
rxfifo_wr_data[DMA_DATA_WIDTH +2]=1'b 0;
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'b 0;
end
else begin
//EOP
rxfifo_wr_data[DMA_DATA_WIDTH +2]=1'b 1;
// data is in little endian: [7:0] is the first byte.
case (dma_rd_ctrl)
'b 0001:
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'h 1;
'b 0010:
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'h 2;
'b 0100:
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'h 3;
'b 1000:
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'h 0;
default:
rxfifo_wr_data[DMA_DATA_WIDTH +1:DMA_DATA_WIDTH]=2'h 0;
endcase // case(dma_rd_ctrl)
if (align_cnt_nxt != 'h 0)
state_nxt = RX_PAD_STATE;
else
state_nxt = IDLE_STATE;
end // else: !if(dma_rd_ctrl == 'h 0)
end // if (!rxfifo_nearly_full)
end // case: RX_STATE
RX_PAD_STATE: begin
case (queue_id)
4'h 0: cpu_q_dma_rd_0 = 1'b 1;
4'h 1: cpu_q_dma_rd_1 = 1'b 1;
4'h 2: cpu_q_dma_rd_2 = 1'b 1;
4'h 3: cpu_q_dma_rd_3 = 1'b 1;
endcase // case(oq_queue_id)
align_cnt_nxt = align_cnt_plus_1;
if (align_cnt_nxt == 'h 0)
state_nxt = IDLE_STATE;
end // case: RX_PAD_STATE
endcase // case(state)
end // always @ (*)
parameter
DMA_QUE_WR_IDLE_STATE = 'h 0,
DMA_QUE_WR_PAD_STATE = 'h 1;
reg dma_que_wr_state, dma_que_wr_state_nxt;
reg [3:0] dma_que_wr_align_cnt, dma_que_wr_align_cnt_nxt;
reg [3:0] dma_que_wr_queue_id, dma_que_wr_queue_id_nxt;
wire [3:0] dma_que_wr_align_cnt_plus_1 =
((dma_que_wr_align_cnt+'h 1)==(USER_DATA_PATH_WIDTH/DMA_DATA_WIDTH)) ?
'h 0 : dma_que_wr_align_cnt + 'h 1;
always @(posedge clk) begin
if (reset) begin
state <= IDLE_STATE;
queue_id <= 'h 0;
dma_rd_vld <= 'h 0;
align_cnt <= 'h 0;
dma_que_wr_state <= DMA_QUE_WR_IDLE_STATE;
dma_que_wr_align_cnt <= 'h 0;
dma_que_wr_queue_id <= 'h 0;
cpu_q_dma_wr_0 <= 1'b 0;
cpu_q_dma_wr_data_0 <= 'h 0;
cpu_q_dma_wr_ctrl_0 <= 'h 0;
cpu_q_dma_wr_1 <= 1'b 0;
cpu_q_dma_wr_data_1 <= 'h 0;
cpu_q_dma_wr_ctrl_1 <= 'h 0;
cpu_q_dma_wr_2 <= 1'b 0;
cpu_q_dma_wr_data_2 <= 'h 0;
cpu_q_dma_wr_ctrl_2 <= 'h 0;
cpu_q_dma_wr_3 <= 1'b 0;
cpu_q_dma_wr_data_3 <= 'h 0;
cpu_q_dma_wr_ctrl_3 <= 'h 0;
end
else begin
state <= state_nxt;
queue_id <= queue_id_nxt;
dma_rd_vld <= dma_rd_vld_nxt;
align_cnt <= align_cnt_nxt;
dma_que_wr_state <= dma_que_wr_state_nxt;
dma_que_wr_align_cnt <= dma_que_wr_align_cnt_nxt;
dma_que_wr_queue_id <= dma_que_wr_queue_id_nxt;
cpu_q_dma_wr_0 <= cpu_q_dma_wr_0_nxt;
cpu_q_dma_wr_data_0 <= cpu_q_dma_wr_data_0_nxt;
cpu_q_dma_wr_ctrl_0 <= cpu_q_dma_wr_ctrl_0_nxt;
cpu_q_dma_wr_1 <= cpu_q_dma_wr_1_nxt;
cpu_q_dma_wr_data_1 <= cpu_q_dma_wr_data_1_nxt;
cpu_q_dma_wr_ctrl_1 <= cpu_q_dma_wr_ctrl_1_nxt;
cpu_q_dma_wr_2 <= cpu_q_dma_wr_2_nxt;
cpu_q_dma_wr_data_2 <= cpu_q_dma_wr_data_2_nxt;
cpu_q_dma_wr_ctrl_2 <= cpu_q_dma_wr_ctrl_2_nxt;
cpu_q_dma_wr_3 <= cpu_q_dma_wr_3_nxt;
cpu_q_dma_wr_data_3 <= cpu_q_dma_wr_data_3_nxt;
cpu_q_dma_wr_ctrl_3 <= cpu_q_dma_wr_ctrl_3_nxt;
end
end // always @ (posedge clk)
endmodule // nf2_dma_que_intfc
|
/******************************************************************************
* File Name : regbank.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : The register bank for storing results and
* intermediate results for the eliptic curve.
* y^2 + xy = x^3 + a.x^2 + b
* where a = 1
******************************************************************************/
`timescale 1ns / 1ps
`ifndef __REGFILES_V__
`define __REGFILES_V__
//`include "xc3s_ram16x233_d.v"
//`include "bquadblk.v"
/*---------------------------------------------------------------------------
* Module Name : regbank
* Synopsis : Register bank for the EC Processor.
* Distributed RAM of Xilinx is used for the purpose of storage.
* Instance of Quadblock also made here.
*--------------------------------------------------------------------------*/
module regbank(clk, cwh, c0, c1, a0, a1, a2, a3);
input wire clk;
input wire [22:0] cwh; /* control word */
input wire [232:0] c0, c1; /* Inputs to regbank from ALU */
output wire [232:0] a0, a1, a2, a3; /* Output from regbank to ALU */
wire rb1_we;
wire [3:0] rb1_addr1, rb2_addr1, rb3_addr1;
wire [3:0] rb1_addr2, rb2_addr2, rb3_addr2;
wire [232:0] rb1_din, rb2_din, rb3_din;
wire [232:0] rb1_dout1, rb2_dout1, rb3_dout1;
wire [232:0] rb1_dout2, rb2_dout2, rb3_dout2;
wire [232:0] qin, qout;
/* Instances of distributed memory */
XC3S_RAM16X233_D regbank1(rb1_din, rb1_addr1, rb1_addr2, rb1_we, clk, rb1_dout1, rb1_dout2);
XC3S_RAM16X233_D regbank2(rb2_din, rb2_addr1, rb2_addr2, rb2_we, clk, rb2_dout1, rb2_dout2);
XC3S_RAM16X233_D regbank3(rb3_din, rb3_addr1, rb3_addr2, rb3_we, clk, rb3_dout1, rb3_dout2);
/* Quadblock instance */
bquadblk bqb(cwh[20], qin, cwh[19:16], qout);
assign qin = (cwh[21] == 1'b1) ? a1 : a2;
assign rb1_addr1 = {3'b0, cwh[0]};
assign rb1_addr2 = {3'b0, cwh[1]};
assign rb2_addr1 = {2'b0, cwh[4:3]};
assign rb2_addr2 = {2'b0, cwh[6:5]};
assign rb3_addr1 = {3'b0, cwh[8]};
assign rb3_addr2 = {3'b0, cwh[9]};
/* a0 to a3 are fed to the ALU */
assign a0 = (cwh[11] == 1'b0) ? rb1_dout1 : rb2_dout2;
assign a2 = (cwh[12] == 1'b0) ? rb2_dout1 : rb1_dout2;
assign a1 = (cwh[13] == 1'b0) ? rb3_dout1 : rb2_dout2;
assign a3 = rb3_dout2;
/* Select what get written into RAM */
assign rb1_we = cwh[2];
assign rb1_din = (cwh[22] == 1'b1) ? c0
: ((cwh[14] == 1'b0) ? c0 : c1);
assign rb2_we = cwh[7];
assign rb2_din = (cwh[22] == 1'b1) ? c1
: ((cwh[15] == 1'b0) ? c0 : c1);
assign rb3_we = cwh[10];
assign rb3_din = (cwh[22] == 1'b1) ? 233'h1
: (cwh[20] == 1'b1) ? qout
: c0;
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_databuf_ca2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_databuf_ca2(/*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Debug Unit ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Basic OR1200 debug unit. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_du.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Debug unit
//
module or1200_du(
// RISC Internal Interface
clk, rst,
dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
dcpu_dat_dc, icpu_cycstb_i,
ex_freeze, branch_op, ex_insn, id_pc,
spr_dat_npc, rf_dataw,
du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
du_read, du_write, du_except_stop, du_hwbkpt,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input dcpu_cycstb_i; // LSU status
input dcpu_we_i; // LSU status
input [31:0] dcpu_adr_i; // LSU addr
input [31:0] dcpu_dat_lsu; // LSU store data
input [31:0] dcpu_dat_dc; // LSU load data
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
input ex_freeze; // EX stage freeze
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
input [dw-1:0] ex_insn; // EX insn
input [31:0] id_pc; // insn fetch EA
input [31:0] spr_dat_npc; // Next PC (for trace)
input [31:0] rf_dataw; // ALU result (for trace)
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
output [24: 0] du_dmr1;
output du_stall; // Debug Unit Stall
output [aw-1:0] du_addr; // Debug Unit Address
input [dw-1:0] du_dat_i; // Debug Unit Data In
output [dw-1:0] du_dat_o; // Debug Unit Data Out
output du_read; // Debug Unit Read Enable
output du_write; // Debug Unit Write Enable
input [13:0] du_except_stop; // Exception masked by DSR
output du_hwbkpt; // Cause trap exception (HW Breakpoints)
input spr_cs; // SPR Chip Select
input spr_write; // SPR Read/Write
input [aw-1:0] spr_addr; // SPR Address
input [dw-1:0] spr_dat_i; // SPR Data Input
output [dw-1:0] spr_dat_o; // SPR Data Output
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
reg [dw-1:0] dbg_dat_o; // External Data Output
reg dbg_ack_o; // External Data Acknowledge (not WB compatible)
//
// Some connections go directly from the CPU through DU to Debug I/F
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
reg [1:0] dbg_is_o;
//
// Show insn activity (temp, must be removed)
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dbg_is_o <= 2'b00;
else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
dbg_is_o <= ~dbg_is_o;
`ifdef UNUSED
assign dbg_is_o = 2'b00;
`endif
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
`endif
assign dbg_wp_o = 11'b000_0000_0000;
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = dbg_stb_i && !dbg_we_i;
assign du_write = dbg_stb_i && dbg_we_i;
reg dbg_ack;
//
// Generate acknowledge -- just delay stb signal
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
dbg_ack <= 1'b0;
dbg_ack_o <= 1'b0;
end
else begin
dbg_ack <= dbg_stb_i; // valid when du_dat_i
dbg_ack_o <= dbg_ack & dbg_stb_i; // valid when dbg_dat_o
end
end
//
// Register data output
//
always @(posedge clk)
dbg_dat_o <= du_dat_i;
`ifdef OR1200_DU_IMPLEMENTED
//
// Debug Mode Register 1
//
`ifdef OR1200_DU_DMR1
reg [24:0] dmr1; // DMR1 implemented
`else
wire [24:0] dmr1; // DMR1 not implemented
`endif
assign du_dmr1 = dmr1;
//
// Debug Mode Register 2
//
`ifdef OR1200_DU_DMR2
reg [23:0] dmr2; // DMR2 implemented
`else
wire [23:0] dmr2; // DMR2 not implemented
`endif
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
`else
wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
`endif
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg [13:0] drr; // DRR implemented
`else
wire [13:0] drr; // DRR not implemented
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR0
reg [31:0] dvr0;
`else
wire [31:0] dvr0;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR1
reg [31:0] dvr1;
`else
wire [31:0] dvr1;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR2
reg [31:0] dvr2;
`else
wire [31:0] dvr2;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR3
reg [31:0] dvr3;
`else
wire [31:0] dvr3;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR4
reg [31:0] dvr4;
`else
wire [31:0] dvr4;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR5
reg [31:0] dvr5;
`else
wire [31:0] dvr5;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR6
reg [31:0] dvr6;
`else
wire [31:0] dvr6;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR7
reg [31:0] dvr7;
`else
wire [31:0] dvr7;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR0
reg [7:0] dcr0;
`else
wire [7:0] dcr0;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR1
reg [7:0] dcr1;
`else
wire [7:0] dcr1;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR2
reg [7:0] dcr2;
`else
wire [7:0] dcr2;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR3
reg [7:0] dcr3;
`else
wire [7:0] dcr3;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR4
reg [7:0] dcr4;
`else
wire [7:0] dcr4;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR5
reg [7:0] dcr5;
`else
wire [7:0] dcr5;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR6
reg [7:0] dcr6;
`else
wire [7:0] dcr6;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR7
reg [7:0] dcr7;
`else
wire [7:0] dcr7;
`endif
//
// Debug Watchpoint Counter Register 0
//
`ifdef OR1200_DU_DWCR0
reg [31:0] dwcr0;
`else
wire [31:0] dwcr0;
`endif
//
// Debug Watchpoint Counter Register 1
//
`ifdef OR1200_DU_DWCR1
reg [31:0] dwcr1;
`else
wire [31:0] dwcr1;
`endif
//
// Internal wires
//
wire dmr1_sel; // DMR1 select
wire dmr2_sel; // DMR2 select
wire dsr_sel; // DSR select
wire drr_sel; // DRR select
wire dvr0_sel,
dvr1_sel,
dvr2_sel,
dvr3_sel,
dvr4_sel,
dvr5_sel,
dvr6_sel,
dvr7_sel; // DVR selects
wire dcr0_sel,
dcr1_sel,
dcr2_sel,
dcr3_sel,
dcr4_sel,
dcr5_sel,
dcr6_sel,
dcr7_sel; // DCR selects
wire dwcr0_sel,
dwcr1_sel; // DWCR selects
reg dbg_bp_r;
reg ex_freeze_q;
`ifdef OR1200_DU_HWBKPTS
reg [31:0] match_cond0_ct;
reg [31:0] match_cond1_ct;
reg [31:0] match_cond2_ct;
reg [31:0] match_cond3_ct;
reg [31:0] match_cond4_ct;
reg [31:0] match_cond5_ct;
reg [31:0] match_cond6_ct;
reg [31:0] match_cond7_ct;
reg match_cond0_stb;
reg match_cond1_stb;
reg match_cond2_stb;
reg match_cond3_stb;
reg match_cond4_stb;
reg match_cond5_stb;
reg match_cond6_stb;
reg match_cond7_stb;
reg match0;
reg match1;
reg match2;
reg match3;
reg match4;
reg match5;
reg match6;
reg match7;
reg wpcntr0_match;
reg wpcntr1_match;
reg incr_wpcntr0;
reg incr_wpcntr1;
reg [10:0] wp;
`endif
wire du_hwbkpt;
reg du_hwbkpt_hold;
`ifdef OR1200_DU_READREGS
reg [31:0] spr_dat_o;
`endif
reg [13:0] except_stop; // Exceptions that stop because of DSR
`ifdef OR1200_DU_TB_IMPLEMENTED
wire tb_enw;
reg [7:0] tb_wadr;
reg [31:0] tb_timstmp;
`endif
wire [31:0] tbia_dat_o;
wire [31:0] tbim_dat_o;
wire [31:0] tbar_dat_o;
wire [31:0] tbts_dat_o;
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
`endif
`ifdef OR1200_DU_DMR2
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
`endif
`ifdef OR1200_DU_DVR0
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
`endif
`ifdef OR1200_DU_DVR1
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
`endif
`ifdef OR1200_DU_DVR2
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
`endif
`ifdef OR1200_DU_DVR3
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
`endif
`ifdef OR1200_DU_DVR4
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
`endif
`ifdef OR1200_DU_DVR5
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
`endif
`ifdef OR1200_DU_DVR6
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
`endif
`ifdef OR1200_DU_DVR7
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
`endif
`ifdef OR1200_DU_DCR0
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
`endif
`ifdef OR1200_DU_DCR1
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
`endif
`ifdef OR1200_DU_DCR2
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
`endif
`ifdef OR1200_DU_DCR3
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
`endif
`ifdef OR1200_DU_DCR4
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
`endif
`ifdef OR1200_DU_DCR5
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
`endif
`ifdef OR1200_DU_DCR6
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
`endif
`ifdef OR1200_DU_DCR7
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
`endif
`ifdef OR1200_DU_DWCR0
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
`endif
`ifdef OR1200_DU_DWCR1
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
`endif
// Track previous ex_freeze to detect when signals are updated
always @(posedge clk)
ex_freeze_q <= ex_freeze;
//
// Decode started exception
//
// du_except_stop comes from or1200_except
//
always @(du_except_stop or ex_freeze_q) begin
except_stop = 14'b00_0000_0000_0000;
casez (du_except_stop)
14'b1?_????_????_????:
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
14'b01_????_????_????: begin
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
14'b00_1???_????_????: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
end
14'b00_01??_????_????:
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
14'b00_001?_????_????: begin
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
end
14'b00_0001_????_????:
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
14'b00_0000_1???_????: begin
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
end
14'b00_0000_01??_????: begin
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
end
14'b00_0000_001?_????:
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
14'b00_0000_0001_????:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
14'b00_0000_0000_1???: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
14'b00_0000_0000_01??: begin
except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
end
14'b00_0000_0000_001?: begin
except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
end
14'b00_0000_0000_0001:
except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
default:
except_stop = 14'b00_0000_0000_0000;
endcase // casez (du_except_stop)
end
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
//
// Breakpoint activation register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dbg_bp_r <= 1'b0;
else if (!ex_freeze)
dbg_bp_r <= |except_stop
`ifdef OR1200_DU_DMR1_ST
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
| (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
`endif
;
else
dbg_bp_r <= |except_stop;
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dmr1 <= 25'h000_0000;
else if (dmr1_sel && spr_write)
`ifdef OR1200_DU_HWBKPTS
dmr1 <= spr_dat_i[24:0];
`else
dmr1 <= {1'b0, spr_dat_i[23:22], 22'h00_0000};
`endif
`else
assign dmr1 = 25'h000_0000;
`endif
//
// Write to DMR2
//
`ifdef OR1200_DU_DMR2
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dmr2 <= 24'h00_0000;
else if (dmr2_sel && spr_write)
dmr2 <= spr_dat_i[23:0];
`else
assign dmr2 = 24'h00_0000;
`endif
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
else if (dsr_sel && spr_write)
dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0] & 32'hffffffbf;
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
drr <= 14'b0;
else if (drr_sel && spr_write)
drr <= spr_dat_i[13:0];
else
drr <= drr | except_stop;
`else
assign drr = 14'b0;
`endif
//
// Write to DVR0
//
`ifdef OR1200_DU_DVR0
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr0 <= 32'h0000_0000;
else if (dvr0_sel && spr_write)
dvr0 <= spr_dat_i[31:0];
`else
assign dvr0 = 32'h0000_0000;
`endif
//
// Write to DVR1
//
`ifdef OR1200_DU_DVR1
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr1 <= 32'h0000_0000;
else if (dvr1_sel && spr_write)
dvr1 <= spr_dat_i[31:0];
`else
assign dvr1 = 32'h0000_0000;
`endif
//
// Write to DVR2
//
`ifdef OR1200_DU_DVR2
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr2 <= 32'h0000_0000;
else if (dvr2_sel && spr_write)
dvr2 <= spr_dat_i[31:0];
`else
assign dvr2 = 32'h0000_0000;
`endif
//
// Write to DVR3
//
`ifdef OR1200_DU_DVR3
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr3 <= 32'h0000_0000;
else if (dvr3_sel && spr_write)
dvr3 <= spr_dat_i[31:0];
`else
assign dvr3 = 32'h0000_0000;
`endif
//
// Write to DVR4
//
`ifdef OR1200_DU_DVR4
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr4 <= 32'h0000_0000;
else if (dvr4_sel && spr_write)
dvr4 <= spr_dat_i[31:0];
`else
assign dvr4 = 32'h0000_0000;
`endif
//
// Write to DVR5
//
`ifdef OR1200_DU_DVR5
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr5 <= 32'h0000_0000;
else if (dvr5_sel && spr_write)
dvr5 <= spr_dat_i[31:0];
`else
assign dvr5 = 32'h0000_0000;
`endif
//
// Write to DVR6
//
`ifdef OR1200_DU_DVR6
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr6 <= 32'h0000_0000;
else if (dvr6_sel && spr_write)
dvr6 <= spr_dat_i[31:0];
`else
assign dvr6 = 32'h0000_0000;
`endif
//
// Write to DVR7
//
`ifdef OR1200_DU_DVR7
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dvr7 <= 32'h0000_0000;
else if (dvr7_sel && spr_write)
dvr7 <= spr_dat_i[31:0];
`else
assign dvr7 = 32'h0000_0000;
`endif
//
// Write to DCR0
//
`ifdef OR1200_DU_DCR0
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr0 <= 8'h00;
else if (dcr0_sel && spr_write)
dcr0 <= spr_dat_i[7:0];
`else
assign dcr0 = 8'h00;
`endif
//
// Write to DCR1
//
`ifdef OR1200_DU_DCR1
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr1 <= 8'h00;
else if (dcr1_sel && spr_write)
dcr1 <= spr_dat_i[7:0];
`else
assign dcr1 = 8'h00;
`endif
//
// Write to DCR2
//
`ifdef OR1200_DU_DCR2
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr2 <= 8'h00;
else if (dcr2_sel && spr_write)
dcr2 <= spr_dat_i[7:0];
`else
assign dcr2 = 8'h00;
`endif
//
// Write to DCR3
//
`ifdef OR1200_DU_DCR3
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr3 <= 8'h00;
else if (dcr3_sel && spr_write)
dcr3 <= spr_dat_i[7:0];
`else
assign dcr3 = 8'h00;
`endif
//
// Write to DCR4
//
`ifdef OR1200_DU_DCR4
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr4 <= 8'h00;
else if (dcr4_sel && spr_write)
dcr4 <= spr_dat_i[7:0];
`else
assign dcr4 = 8'h00;
`endif
//
// Write to DCR5
//
`ifdef OR1200_DU_DCR5
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr5 <= 8'h00;
else if (dcr5_sel && spr_write)
dcr5 <= spr_dat_i[7:0];
`else
assign dcr5 = 8'h00;
`endif
//
// Write to DCR6
//
`ifdef OR1200_DU_DCR6
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr6 <= 8'h00;
else if (dcr6_sel && spr_write)
dcr6 <= spr_dat_i[7:0];
`else
assign dcr6 = 8'h00;
`endif
//
// Write to DCR7
//
`ifdef OR1200_DU_DCR7
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcr7 <= 8'h00;
else if (dcr7_sel && spr_write)
dcr7 <= spr_dat_i[7:0];
`else
assign dcr7 = 8'h00;
`endif
//
// Write to DWCR0
//
`ifdef OR1200_DU_DWCR0
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dwcr0 <= 32'h0000_0000;
else if (dwcr0_sel && spr_write)
dwcr0 <= spr_dat_i[31:0];
else if (incr_wpcntr0)
dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr0 = 32'h0000_0000;
`endif
//
// Write to DWCR1
//
`ifdef OR1200_DU_DWCR1
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dwcr1 <= 32'h0000_0000;
else if (dwcr1_sel && spr_write)
dwcr1 <= spr_dat_i[31:0];
else if (incr_wpcntr1)
dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr1 = 32'h0000_0000;
`endif
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2
or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
or dvr5 or dvr6 or dvr7
or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
or dcr5 or dcr6 or dcr7
or dwcr0 or dwcr1
`ifdef OR1200_DU_TB_IMPLEMENTED
or tb_wadr or tbia_dat_o or tbim_dat_o
or tbar_dat_o or tbts_dat_o
`endif
)
casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DVR0
`OR1200_DU_DVR0:
spr_dat_o = dvr0;
`endif
`ifdef OR1200_DU_DVR1
`OR1200_DU_DVR1:
spr_dat_o = dvr1;
`endif
`ifdef OR1200_DU_DVR2
`OR1200_DU_DVR2:
spr_dat_o = dvr2;
`endif
`ifdef OR1200_DU_DVR3
`OR1200_DU_DVR3:
spr_dat_o = dvr3;
`endif
`ifdef OR1200_DU_DVR4
`OR1200_DU_DVR4:
spr_dat_o = dvr4;
`endif
`ifdef OR1200_DU_DVR5
`OR1200_DU_DVR5:
spr_dat_o = dvr5;
`endif
`ifdef OR1200_DU_DVR6
`OR1200_DU_DVR6:
spr_dat_o = dvr6;
`endif
`ifdef OR1200_DU_DVR7
`OR1200_DU_DVR7:
spr_dat_o = dvr7;
`endif
`ifdef OR1200_DU_DCR0
`OR1200_DU_DCR0:
spr_dat_o = {24'h00_0000, dcr0};
`endif
`ifdef OR1200_DU_DCR1
`OR1200_DU_DCR1:
spr_dat_o = {24'h00_0000, dcr1};
`endif
`ifdef OR1200_DU_DCR2
`OR1200_DU_DCR2:
spr_dat_o = {24'h00_0000, dcr2};
`endif
`ifdef OR1200_DU_DCR3
`OR1200_DU_DCR3:
spr_dat_o = {24'h00_0000, dcr3};
`endif
`ifdef OR1200_DU_DCR4
`OR1200_DU_DCR4:
spr_dat_o = {24'h00_0000, dcr4};
`endif
`ifdef OR1200_DU_DCR5
`OR1200_DU_DCR5:
spr_dat_o = {24'h00_0000, dcr5};
`endif
`ifdef OR1200_DU_DCR6
`OR1200_DU_DCR6:
spr_dat_o = {24'h00_0000, dcr6};
`endif
`ifdef OR1200_DU_DCR7
`OR1200_DU_DCR7:
spr_dat_o = {24'h00_0000, dcr7};
`endif
`ifdef OR1200_DU_DMR1
`OR1200_DU_DMR1:
spr_dat_o = {7'h00, dmr1};
`endif
`ifdef OR1200_DU_DMR2
`OR1200_DU_DMR2:
spr_dat_o = {8'h00, dmr2};
`endif
`ifdef OR1200_DU_DWCR0
`OR1200_DU_DWCR0:
spr_dat_o = dwcr0;
`endif
`ifdef OR1200_DU_DWCR1
`OR1200_DU_DWCR1:
spr_dat_o = dwcr1;
`endif
`ifdef OR1200_DU_DSR
`OR1200_DU_DSR:
spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
`OR1200_DU_DRR:
spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
`OR1200_DU_TBADR:
spr_dat_o = {24'h000000, tb_wadr};
`OR1200_DU_TBIA:
spr_dat_o = tbia_dat_o;
`OR1200_DU_TBIM:
spr_dat_o = tbim_dat_o;
`OR1200_DU_TBAR:
spr_dat_o = tbar_dat_o;
`OR1200_DU_TBTS:
spr_dat_o = tbts_dat_o;
`endif
default:
spr_dat_o = 32'h0000_0000;
endcase
`endif
//
// DSR alias
//
assign du_dsr = dsr;
`ifdef OR1200_DU_HWBKPTS
//
// Compare To What (Match Condition 0)
//
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond0_ct = id_pc; // insn fetch EA
3'b010: match_cond0_ct = dcpu_adr_i; // load EA
3'b011: match_cond0_ct = dcpu_adr_i; // store EA
3'b100: match_cond0_ct = dcpu_dat_dc; // load data
3'b101: match_cond0_ct = dcpu_dat_lsu; // store data
3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA
default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 0)
//
always @(dcr0 or dcpu_cycstb_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond0_stb = 1'b0; //comparison disabled
3'b001: match_cond0_stb = 1'b1; // insn fetch EA
default:match_cond0_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 0
//
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match0 = 1'b0;
4'b1_001: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
4'b1_010: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
4'b1_011: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
4'b1_100: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
4'b1_101: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
4'b1_110: match0 =
({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
{(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
endcase
//
// Watchpoint 0
//
always @(dmr1 or match0)
case (dmr1[`OR1200_DU_DMR1_CW0])
2'b00: wp[0] = match0;
2'b01: wp[0] = match0;
2'b10: wp[0] = match0;
2'b11: wp[0] = 1'b0;
endcase
//
// Compare To What (Match Condition 1)
//
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond1_ct = id_pc; // insn fetch EA
3'b010: match_cond1_ct = dcpu_adr_i; // load EA
3'b011: match_cond1_ct = dcpu_adr_i; // store EA
3'b100: match_cond1_ct = dcpu_dat_dc; // load data
3'b101: match_cond1_ct = dcpu_dat_lsu; // store data
3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA
default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 1)
//
always @(dcr1 or dcpu_cycstb_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond1_stb = 1'b0; //comparison disabled
3'b001: match_cond1_stb = 1'b1; // insn fetch EA
default:match_cond1_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 1
//
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match1 = 1'b0;
4'b1_001: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
4'b1_010: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
4'b1_011: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
4'b1_100: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
4'b1_101: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
4'b1_110: match1 =
({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
{(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
endcase
//
// Watchpoint 1
//
always @(dmr1 or match1 or wp)
case (dmr1[`OR1200_DU_DMR1_CW1])
2'b00: wp[1] = match1;
2'b01: wp[1] = match1 & wp[0];
2'b10: wp[1] = match1 | wp[0];
2'b11: wp[1] = 1'b0;
endcase
//
// Compare To What (Match Condition 2)
//
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond2_ct = id_pc; // insn fetch EA
3'b010: match_cond2_ct = dcpu_adr_i; // load EA
3'b011: match_cond2_ct = dcpu_adr_i; // store EA
3'b100: match_cond2_ct = dcpu_dat_dc; // load data
3'b101: match_cond2_ct = dcpu_dat_lsu; // store data
3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA
default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 2)
//
always @(dcr2 or dcpu_cycstb_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond2_stb = 1'b0; //comparison disabled
3'b001: match_cond2_stb = 1'b1; // insn fetch EA
default:match_cond2_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 2
//
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match2 = 1'b0;
4'b1_001: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
4'b1_010: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
4'b1_011: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
4'b1_100: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
4'b1_101: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
4'b1_110: match2 =
({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
{(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
endcase
//
// Watchpoint 2
//
always @(dmr1 or match2 or wp)
case (dmr1[`OR1200_DU_DMR1_CW2])
2'b00: wp[2] = match2;
2'b01: wp[2] = match2 & wp[1];
2'b10: wp[2] = match2 | wp[1];
2'b11: wp[2] = 1'b0;
endcase
//
// Compare To What (Match Condition 3)
//
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond3_ct = id_pc; // insn fetch EA
3'b010: match_cond3_ct = dcpu_adr_i; // load EA
3'b011: match_cond3_ct = dcpu_adr_i; // store EA
3'b100: match_cond3_ct = dcpu_dat_dc; // load data
3'b101: match_cond3_ct = dcpu_dat_lsu; // store data
3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA
default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 3)
//
always @(dcr3 or dcpu_cycstb_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond3_stb = 1'b0; //comparison disabled
3'b001: match_cond3_stb = 1'b1; // insn fetch EA
default:match_cond3_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 3
//
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match3 = 1'b0;
4'b1_001: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
4'b1_010: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
4'b1_011: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
4'b1_100: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
4'b1_101: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
4'b1_110: match3 =
({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
{(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
endcase
//
// Watchpoint 3
//
always @(dmr1 or match3 or wp)
case (dmr1[`OR1200_DU_DMR1_CW3])
2'b00: wp[3] = match3;
2'b01: wp[3] = match3 & wp[2];
2'b10: wp[3] = match3 | wp[2];
2'b11: wp[3] = 1'b0;
endcase
//
// Compare To What (Match Condition 4)
//
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond4_ct = id_pc; // insn fetch EA
3'b010: match_cond4_ct = dcpu_adr_i; // load EA
3'b011: match_cond4_ct = dcpu_adr_i; // store EA
3'b100: match_cond4_ct = dcpu_dat_dc; // load data
3'b101: match_cond4_ct = dcpu_dat_lsu; // store data
3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA
default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 4)
//
always @(dcr4 or dcpu_cycstb_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond4_stb = 1'b0; //comparison disabled
3'b001: match_cond4_stb = 1'b1; // insn fetch EA
default:match_cond4_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 4
//
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match4 = 1'b0;
4'b1_001: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
4'b1_010: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
4'b1_011: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
4'b1_100: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
4'b1_101: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
4'b1_110: match4 =
({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
{(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
endcase
//
// Watchpoint 4
//
always @(dmr1 or match4 or wp)
case (dmr1[`OR1200_DU_DMR1_CW4])
2'b00: wp[4] = match4;
2'b01: wp[4] = match4 & wp[3];
2'b10: wp[4] = match4 | wp[3];
2'b11: wp[4] = 1'b0;
endcase
//
// Compare To What (Match Condition 5)
//
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond5_ct = id_pc; // insn fetch EA
3'b010: match_cond5_ct = dcpu_adr_i; // load EA
3'b011: match_cond5_ct = dcpu_adr_i; // store EA
3'b100: match_cond5_ct = dcpu_dat_dc; // load data
3'b101: match_cond5_ct = dcpu_dat_lsu; // store data
3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA
default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 5)
//
always @(dcr5 or dcpu_cycstb_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond5_stb = 1'b0; //comparison disabled
3'b001: match_cond5_stb = 1'b1; // insn fetch EA
default:match_cond5_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 5
//
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match5 = 1'b0;
4'b1_001: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
4'b1_010: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
4'b1_011: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
4'b1_100: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
4'b1_101: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
4'b1_110: match5 =
({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
{(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
endcase
//
// Watchpoint 5
//
always @(dmr1 or match5 or wp)
case (dmr1[`OR1200_DU_DMR1_CW5])
2'b00: wp[5] = match5;
2'b01: wp[5] = match5 & wp[4];
2'b10: wp[5] = match5 | wp[4];
2'b11: wp[5] = 1'b0;
endcase
//
// Compare To What (Match Condition 6)
//
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond6_ct = id_pc; // insn fetch EA
3'b010: match_cond6_ct = dcpu_adr_i; // load EA
3'b011: match_cond6_ct = dcpu_adr_i; // store EA
3'b100: match_cond6_ct = dcpu_dat_dc; // load data
3'b101: match_cond6_ct = dcpu_dat_lsu; // store data
3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA
default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 6)
//
always @(dcr6 or dcpu_cycstb_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond6_stb = 1'b0; //comparison disabled
3'b001: match_cond6_stb = 1'b1; // insn fetch EA
default:match_cond6_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 6
//
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match6 = 1'b0;
4'b1_001: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
4'b1_010: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
4'b1_011: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
4'b1_100: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
4'b1_101: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
4'b1_110: match6 =
({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
{(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
endcase
//
// Watchpoint 6
//
always @(dmr1 or match6 or wp)
case (dmr1[`OR1200_DU_DMR1_CW6])
2'b00: wp[6] = match6;
2'b01: wp[6] = match6 & wp[5];
2'b10: wp[6] = match6 | wp[5];
2'b11: wp[6] = 1'b0;
endcase
//
// Compare To What (Match Condition 7)
//
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond7_ct = id_pc; // insn fetch EA
3'b010: match_cond7_ct = dcpu_adr_i; // load EA
3'b011: match_cond7_ct = dcpu_adr_i; // store EA
3'b100: match_cond7_ct = dcpu_dat_dc; // load data
3'b101: match_cond7_ct = dcpu_dat_lsu; // store data
3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA
default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 7)
//
always @(dcr7 or dcpu_cycstb_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond7_stb = 1'b0; //comparison disabled
3'b001: match_cond7_stb = 1'b1; // insn fetch EA
default:match_cond7_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 7
//
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match7 = 1'b0;
4'b1_001: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
4'b1_010: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
4'b1_011: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
4'b1_100: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
4'b1_101: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
4'b1_110: match7 =
({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
{(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
endcase
//
// Watchpoint 7
//
always @(dmr1 or match7 or wp)
case (dmr1[`OR1200_DU_DMR1_CW7])
2'b00: wp[7] = match7;
2'b01: wp[7] = match7 & wp[6];
2'b10: wp[7] = match7 | wp[6];
2'b11: wp[7] = 1'b0;
endcase
//
// Increment Watchpoint Counter 0
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE0])
incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr0 = 1'b0;
//
// Match Condition Watchpoint Counter 0
//
always @(dwcr0)
if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
wpcntr0_match = 1'b1;
else
wpcntr0_match = 1'b0;
//
// Watchpoint 8
//
always @(dmr1 or wpcntr0_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW8])
2'b00: wp[8] = wpcntr0_match;
2'b01: wp[8] = wpcntr0_match & wp[7];
2'b10: wp[8] = wpcntr0_match | wp[7];
2'b11: wp[8] = 1'b0;
endcase
//
// Increment Watchpoint Counter 1
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE1])
incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr1 = 1'b0;
//
// Match Condition Watchpoint Counter 1
//
always @(dwcr1)
if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
wpcntr1_match = 1'b1;
else
wpcntr1_match = 1'b0;
//
// Watchpoint 9
//
always @(dmr1 or wpcntr1_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW9])
2'b00: wp[9] = wpcntr1_match;
2'b01: wp[9] = wpcntr1_match & wp[8];
2'b10: wp[9] = wpcntr1_match | wp[8];
2'b11: wp[9] = 1'b0;
endcase
//
// Watchpoint 10
//
always @(dmr1 or dbg_ewt_i or wp)
case (dmr1[`OR1200_DU_DMR1_CW10])
2'b00: wp[10] = dbg_ewt_i;
2'b01: wp[10] = dbg_ewt_i & wp[9];
2'b10: wp[10] = dbg_ewt_i | wp[9];
2'b11: wp[10] = 1'b0;
endcase
`endif
//
// Watchpoints can cause trap exception
//
`ifdef OR1200_DU_HWBKPTS
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
`else
assign du_hwbkpt = 1'b0;
`endif
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
du_hwbkpt_hold <= 1'b0;
else if (du_hwbkpt & ex_freeze)
du_hwbkpt_hold <= 1'b1;
else if (!ex_freeze)
du_hwbkpt_hold <= 1'b0;
`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//
//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
//
// Trace buffer write address pointer
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
tb_wadr <= 8'h00;
else if (tb_enw)
tb_wadr <= tb_wadr + 8'd1;
//
// Free running counter (time stamp)
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
tb_timstmp <= 32'h00000000;
else if (!dbg_bp_r)
tb_timstmp <= tb_timstmp + 32'd1;
//
// Trace buffer RAMs
//
or1200_dpram_256x32 tbia_ram(
.clk_a(clk),
.rst_a(1'b0),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbia_dat_o),
.clk_b(clk),
.rst_b(1'b0),
.addr_b(tb_wadr),
.di_b(spr_dat_npc),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbim_ram(
.clk_a(clk),
.rst_a(1'b0),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbim_dat_o),
.clk_b(clk),
.rst_b(1'b0),
.addr_b(tb_wadr),
.di_b(ex_insn),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbar_ram(
.clk_a(clk),
.rst_a(1'b0),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbar_dat_o),
.clk_b(clk),
.rst_b(1'b0),
.addr_b(tb_wadr),
.di_b(rf_dataw),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbts_ram(
.clk_a(clk),
.rst_a(1'b0),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbts_dat_o),
.clk_b(clk),
.rst_b(1'b0),
.addr_b(tb_wadr),
.di_b(tb_timstmp),
.ce_b(1'b1),
.we_b(tb_enw)
);
`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;
`endif // OR1200_DU_TB_IMPLEMENTED
`else // OR1200_DU_IMPLEMENTED
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
assign du_dmr1 = {25{1'b0}};
assign du_hwbkpt = 1'b0;
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Software programmable clock generator (still needs a reference input!)
module cf_clkgen (
// reference clock input (default 200MHz)
ref_clk,
// output clock M/N*f_in for any M/N supported by MMCM.
clk,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack);
// MMCM state machine parameters
parameter MMCM_TYPE = 'd0;
parameter MMCM_IDLE = 'h0;
parameter MMCM_READ = 'h1;
parameter MMCM_RDRDY = 'h2;
parameter MMCM_WRITE = 'h3;
parameter MMCM_WRRDY = 'h4;
// reference clock input (default 200MHz)
input ref_clk;
// output clock M/N*f_in for any M/N supported by MMCM.
output clk;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
reg mmcm_swrst;
reg mmcm_start;
reg mmcm_start_d;
reg [15:0] mmcm_clk_out_1;
reg [15:0] mmcm_clk_out_2;
reg [15:0] mmcm_clk_div;
reg [15:0] mmcm_clk_fb_1;
reg [15:0] mmcm_clk_fb_2;
reg [15:0] mmcm_lock_1;
reg [15:0] mmcm_lock_2;
reg [15:0] mmcm_lock_3;
reg [15:0] mmcm_filter_1;
reg [15:0] mmcm_filter_2;
reg [31:0] up_rdata;
reg up_sel_d;
reg up_sel_2d;
reg up_ack;
reg mmcm_rst;
reg [ 6:0] mmcm_addr;
reg mmcm_sel;
reg [15:0] mmcm_rdata;
reg [15:0] mmcm_wdata;
reg mmcm_wr;
reg [ 3:0] mmcm_count;
reg [ 2:0] mmcm_state;
wire up_wr_s;
wire up_ack_s;
wire mmcm_start_s;
wire [15:0] mmcm_wdata_s;
reg [38:0] mmcm_data_s;
wire [15:0] mmcm_rdata_s;
wire mmcm_ready_s;
wire mmcm_locked_s;
wire mmcm_clk_s;
wire mmcm_fb_clk_s;
wire buf_fb_clk_s;
// Processor write interface, most of these registers are defined by Xilinx for MMCM.
// See regmap.txt for details, the processor write is directly transferred to DRP.
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
assign mmcm_start_s = mmcm_start & ~mmcm_start_d;
assign mmcm_wdata_s = ~mmcm_data_s[31:16] & mmcm_data_s[15:0];
always @(mmcm_count or mmcm_clk_out_1 or mmcm_clk_out_2 or mmcm_clk_div or
mmcm_clk_fb_1 or mmcm_clk_fb_2 or mmcm_lock_1 or mmcm_lock_2 or mmcm_lock_3 or
mmcm_filter_1 or mmcm_filter_2) begin
case (mmcm_count)
4'b0101: mmcm_data_s = {7'h28, 16'h0000, 16'hffff};
4'b0110: mmcm_data_s = {7'h08, 16'h1000, mmcm_clk_out_1};
4'b0111: mmcm_data_s = {7'h09, 16'hfc00, mmcm_clk_out_2};
4'b1000: mmcm_data_s = {7'h16, 16'hc000, mmcm_clk_div};
4'b1001: mmcm_data_s = {7'h14, 16'h1000, mmcm_clk_fb_1};
4'b1010: mmcm_data_s = {7'h15, 16'hfc00, mmcm_clk_fb_2};
4'b1011: mmcm_data_s = {7'h18, 16'hfc00, mmcm_lock_1};
4'b1100: mmcm_data_s = {7'h19, 16'h8000, mmcm_lock_2};
4'b1101: mmcm_data_s = {7'h1a, 16'h8000, mmcm_lock_3};
4'b1110: mmcm_data_s = {7'h4e, 16'h66ff, mmcm_filter_1};
4'b1111: mmcm_data_s = {7'h4f, 16'h666f, mmcm_filter_2};
default: mmcm_data_s = 'd0;
endcase
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
mmcm_swrst <= 'd0;
mmcm_start <= 'd0;
mmcm_start_d <= 'd0;
mmcm_clk_out_1 <= 'd0;
mmcm_clk_out_2 <= 'd0;
mmcm_clk_div <= 'd0;
mmcm_clk_fb_1 <= 'd0;
mmcm_clk_fb_2 <= 'd0;
mmcm_lock_1 <= 'd0;
mmcm_lock_2 <= 'd0;
mmcm_lock_3 <= 'd0;
mmcm_filter_1 <= 'd0;
mmcm_filter_2 <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
mmcm_swrst <= up_wdata[1];
mmcm_start <= up_wdata[0];
end
mmcm_start_d <= mmcm_start;
if ((up_addr == 5'h02) && (up_wr_s == 1'b1)) begin
mmcm_clk_out_1 <= up_wdata[15:0];
end
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
mmcm_clk_out_2 <= up_wdata[15:0];
end
if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
mmcm_clk_div <= up_wdata[15:0];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
mmcm_clk_fb_1 <= up_wdata[15:0];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
mmcm_clk_fb_2 <= up_wdata[15:0];
end
if ((up_addr == 5'h07) && (up_wr_s == 1'b1)) begin
mmcm_lock_1 <= up_wdata[15:0];
end
if ((up_addr == 5'h08) && (up_wr_s == 1'b1)) begin
mmcm_lock_2 <= up_wdata[15:0];
end
if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
mmcm_lock_3 <= up_wdata[15:0];
end
if ((up_addr == 5'h0a) && (up_wr_s == 1'b1)) begin
mmcm_filter_1 <= up_wdata[15:0];
end
if ((up_addr == 5'h0b) && (up_wr_s == 1'b1)) begin
mmcm_filter_2 <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {30'd0, mmcm_swrst, mmcm_start};
5'h02: up_rdata <= {16'd0, mmcm_clk_out_1};
5'h03: up_rdata <= {16'd0, mmcm_clk_out_2};
5'h04: up_rdata <= {16'd0, mmcm_clk_div};
5'h05: up_rdata <= {16'd0, mmcm_clk_fb_1};
5'h06: up_rdata <= {16'd0, mmcm_clk_fb_2};
5'h07: up_rdata <= {16'd0, mmcm_lock_1};
5'h08: up_rdata <= {16'd0, mmcm_lock_2};
5'h09: up_rdata <= {16'd0, mmcm_lock_3};
5'h0a: up_rdata <= {16'd0, mmcm_filter_1};
5'h0b: up_rdata <= {16'd0, mmcm_filter_2};
5'h1f: up_rdata <= {30'd0, mmcm_rst, mmcm_locked_s};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// DRP state machine and control signals, write/read and then wait for ready
// The DRP is written always in order with a continous read-modify-writes.
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
mmcm_rst <= 'd1;
mmcm_addr <= 'd0;
mmcm_sel <= 'd0;
mmcm_rdata <= 'd0;
mmcm_wdata <= 'd0;
mmcm_wr <= 'd0;
mmcm_count <= 'd0;
mmcm_state <= 'd0;
end else begin
if (mmcm_state == MMCM_IDLE) begin
mmcm_rst <= mmcm_swrst;
end else begin
mmcm_rst <= 1'b1;
end
if (mmcm_state == MMCM_READ) begin
mmcm_addr <= mmcm_data_s[38:32];
end else if (mmcm_state == MMCM_IDLE) begin
mmcm_addr <= 'd0;
end
if ((mmcm_state == MMCM_READ) || (mmcm_state == MMCM_WRITE)) begin
mmcm_sel <= 1'b1;
end else begin
mmcm_sel <= 1'b0;
end
if ((mmcm_state == MMCM_RDRDY) && (mmcm_ready_s == 1'b1)) begin
mmcm_rdata <= mmcm_rdata_s;
end
if (mmcm_state == MMCM_WRITE) begin
mmcm_wdata <= (mmcm_data_s[31:16] & mmcm_rdata) | mmcm_wdata_s;
end else begin
mmcm_wdata <= 'd0;
end
if (mmcm_state == MMCM_WRITE) begin
mmcm_wr <= 1'b1;
end else begin
mmcm_wr <= 1'b0;
end
if (mmcm_state == MMCM_IDLE) begin
mmcm_count <= 4'h5;
end else if (mmcm_state == MMCM_WRITE) begin
mmcm_count <= mmcm_count + 1'b1;
end
case (mmcm_state)
MMCM_IDLE: begin
if ((mmcm_locked_s == 1'b1) && (mmcm_start_s == 1'b1)) begin
mmcm_state <= MMCM_READ; // if read back data first
end else begin
mmcm_state <= MMCM_IDLE;
end
end
MMCM_READ: begin
mmcm_state <= MMCM_RDRDY;
end
MMCM_RDRDY: begin
if (mmcm_ready_s == 1'b1) begin
mmcm_state <= MMCM_WRITE; // modify data and write back
end else begin
mmcm_state <= MMCM_RDRDY;
end
end
MMCM_WRITE: begin
mmcm_state <= MMCM_WRRDY;
end
MMCM_WRRDY: begin
if (mmcm_ready_s == 1'b0) begin
mmcm_state <= MMCM_WRRDY;
end else if (mmcm_count == 0) begin
mmcm_state <= MMCM_IDLE;
end else begin
mmcm_state <= MMCM_READ;
end
end
default: begin
mmcm_state <= MMCM_IDLE;
end
endcase
end
end
// MMCM instantiations
generate
if (MMCM_TYPE == 1) begin
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (11),
.CLKFBOUT_MULT_F (49.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKFBOUT (mmcm_fb_clk_s),
.CLKFBIN (buf_fb_clk_s),
.CLKFBOUTB (),
.CLKOUT0 (mmcm_clk_s),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN1 (ref_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DCLK (up_clk),
.DADDR (mmcm_addr),
.DEN (mmcm_sel),
.DI (mmcm_wdata),
.DO (mmcm_rdata_s),
.DRDY (mmcm_ready_s),
.DWE (mmcm_wr),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.LOCKED (mmcm_locked_s),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end else begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (11),
.CLKFBOUT_MULT_F (49.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKFBOUT (mmcm_fb_clk_s),
.CLKFBIN (buf_fb_clk_s),
.CLKFBOUTB (),
.CLKOUT0 (mmcm_clk_s),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN1 (ref_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DCLK (up_clk),
.DADDR (mmcm_addr),
.DEN (mmcm_sel),
.DI (mmcm_wdata),
.DO (mmcm_rdata_s),
.DRDY (mmcm_ready_s),
.DWE (mmcm_wr),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.LOCKED (mmcm_locked_s),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
endgenerate
BUFG i_fb_buf (
.I (mmcm_fb_clk_s),
.O (buf_fb_clk_s));
BUFG i_buf (
.I (mmcm_clk_s),
.O (clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_1_V
`define SKY130_FD_SC_HDLL__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_sim_netlist.v
// Design : system_ov7670_vga_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_vga_1_0,ov7670_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_vga_1_0
(clk_x2,
active,
data,
rgb);
input clk_x2;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input active;
input [7:0]data;
output [15:0]rgb;
wire active;
wire clk_x2;
wire [7:0]data;
wire [15:0]rgb;
system_ov7670_vga_1_0_ov7670_vga U0
(.active(active),
.clk_x2(clk_x2),
.data(data),
.rgb(rgb));
endmodule
(* ORIG_REF_NAME = "ov7670_vga" *)
module system_ov7670_vga_1_0_ov7670_vga
(rgb,
active,
clk_x2,
data);
output [15:0]rgb;
input active;
input clk_x2;
input [7:0]data;
wire active;
wire clk_x2;
wire cycle;
wire [7:0]data;
wire \data_pair[15]_i_1_n_0 ;
wire \data_pair[7]_i_1_n_0 ;
wire \data_pair_reg_n_0_[0] ;
wire \data_pair_reg_n_0_[10] ;
wire \data_pair_reg_n_0_[11] ;
wire \data_pair_reg_n_0_[12] ;
wire \data_pair_reg_n_0_[13] ;
wire \data_pair_reg_n_0_[14] ;
wire \data_pair_reg_n_0_[15] ;
wire \data_pair_reg_n_0_[1] ;
wire \data_pair_reg_n_0_[2] ;
wire \data_pair_reg_n_0_[3] ;
wire \data_pair_reg_n_0_[4] ;
wire \data_pair_reg_n_0_[5] ;
wire \data_pair_reg_n_0_[6] ;
wire \data_pair_reg_n_0_[7] ;
wire \data_pair_reg_n_0_[8] ;
wire \data_pair_reg_n_0_[9] ;
wire [15:0]rgb;
wire rgb_regn_0_0;
FDRE #(
.INIT(1'b0))
cycle_reg
(.C(clk_x2),
.CE(1'b1),
.D(\data_pair[7]_i_1_n_0 ),
.Q(cycle),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\data_pair[15]_i_1
(.I0(cycle),
.I1(active),
.O(\data_pair[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\data_pair[7]_i_1
(.I0(active),
.I1(cycle),
.O(\data_pair[7]_i_1_n_0 ));
FDRE \data_pair_reg[0]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[0]),
.Q(\data_pair_reg_n_0_[0] ),
.R(1'b0));
FDRE \data_pair_reg[10]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[2]),
.Q(\data_pair_reg_n_0_[10] ),
.R(1'b0));
FDRE \data_pair_reg[11]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[3]),
.Q(\data_pair_reg_n_0_[11] ),
.R(1'b0));
FDRE \data_pair_reg[12]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[4]),
.Q(\data_pair_reg_n_0_[12] ),
.R(1'b0));
FDRE \data_pair_reg[13]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[5]),
.Q(\data_pair_reg_n_0_[13] ),
.R(1'b0));
FDRE \data_pair_reg[14]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[6]),
.Q(\data_pair_reg_n_0_[14] ),
.R(1'b0));
FDRE \data_pair_reg[15]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[7]),
.Q(\data_pair_reg_n_0_[15] ),
.R(1'b0));
FDRE \data_pair_reg[1]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[1]),
.Q(\data_pair_reg_n_0_[1] ),
.R(1'b0));
FDRE \data_pair_reg[2]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[2]),
.Q(\data_pair_reg_n_0_[2] ),
.R(1'b0));
FDRE \data_pair_reg[3]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[3]),
.Q(\data_pair_reg_n_0_[3] ),
.R(1'b0));
FDRE \data_pair_reg[4]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[4]),
.Q(\data_pair_reg_n_0_[4] ),
.R(1'b0));
FDRE \data_pair_reg[5]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[5]),
.Q(\data_pair_reg_n_0_[5] ),
.R(1'b0));
FDRE \data_pair_reg[6]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[6]),
.Q(\data_pair_reg_n_0_[6] ),
.R(1'b0));
FDRE \data_pair_reg[7]
(.C(clk_x2),
.CE(\data_pair[7]_i_1_n_0 ),
.D(data[7]),
.Q(\data_pair_reg_n_0_[7] ),
.R(1'b0));
FDRE \data_pair_reg[8]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[0]),
.Q(\data_pair_reg_n_0_[8] ),
.R(1'b0));
FDRE \data_pair_reg[9]
(.C(clk_x2),
.CE(\data_pair[15]_i_1_n_0 ),
.D(data[1]),
.Q(\data_pair_reg_n_0_[9] ),
.R(1'b0));
FDRE \rgb_reg[0]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[0] ),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[10] ),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[11] ),
.Q(rgb[11]),
.R(1'b0));
FDRE \rgb_reg[12]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[12] ),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[13] ),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[14] ),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[15] ),
.Q(rgb[15]),
.R(1'b0));
FDRE \rgb_reg[1]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[1] ),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[2]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[2] ),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[3] ),
.Q(rgb[3]),
.R(1'b0));
FDRE \rgb_reg[4]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[4] ),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[5] ),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[6] ),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[7] ),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[8]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[8] ),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(rgb_regn_0_0),
.CE(cycle),
.D(\data_pair_reg_n_0_[9] ),
.Q(rgb[9]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rgb_regi_0
(.I0(clk_x2),
.O(rgb_regn_0_0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: VC707_Gen1x8If64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx VC707 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "tlp.vh"
`include "xilinx.vh"
`timescale 1ps / 1ps
module VC707_Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [3:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
wire pcie_refclk;
wire pcie_reset_n;
wire user_clk;
wire user_reset;
wire user_lnk_up;
wire user_app_rdy;
wire s_axis_tx_tready;
wire [C_PCI_DATA_WIDTH-1 : 0] s_axis_tx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire [`SIG_XIL_TX_TUSER_W : 0] s_axis_tx_tuser;
wire [C_PCI_DATA_WIDTH-1 : 0] m_axis_rx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
wire tx_cfg_gnt;
wire rx_np_ok;
wire rx_np_req;
wire cfg_turnoff_ok;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [63:0] cfg_dsn;
wire [11 : 0] fc_cpld;
wire [7 : 0] fc_cplh;
wire [11 : 0] fc_npd;
wire [7 : 0] fc_nph;
wire [11 : 0] fc_pd;
wire [7 : 0] fc_ph;
wire [2 : 0] fc_sel;
wire [15 : 0] cfg_status;
wire [15 : 0] cfg_command;
wire [15 : 0] cfg_dstatus;
wire [15 : 0] cfg_dcommand;
wire [15 : 0] cfg_lstatus;
wire [15 : 0] cfg_lcommand;
wire [15 : 0] cfg_dcommand2;
wire [2 : 0] cfg_pcie_link_state;
wire cfg_pmcsr_pme_en;
wire [1 : 0] cfg_pmcsr_powerstate;
wire cfg_pmcsr_pme_status;
wire cfg_received_func_lvl_rst;
wire [4 : 0] cfg_pciecap_interrupt_msgnum;
wire cfg_to_turnoff;
wire [7 : 0] cfg_bus_number;
wire [4 : 0] cfg_device_number;
wire [2 : 0] cfg_function_number;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7 : 0] cfg_interrupt_di;
wire [7 : 0] cfg_interrupt_do;
wire [2 : 0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
assign cfg_turnoff_ok = 0;
assign cfg_trn_pending = 0;
assign cfg_pm_halt_aspm_l0s = 0;
assign cfg_pm_halt_aspm_l1 = 0;
assign cfg_pm_force_state_en = 0;
assign cfg_pm_force_state = 0;
assign cfg_dsn = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
assign cfg_interrupt_stat = 0;
assign cfg_pciecap_interrupt_msgnum = 0;
assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
// Core Top Level Wrapper
PCIeGen1x8If64 PCIeGen1x8If64_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
// Tx
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
// Rx
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI-S Interface
//---------------------------------------------------------------------
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( user_app_rdy ),
// TX
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
//---------------------------------------------------------------------
// Flow Control Interface
//---------------------------------------------------------------------
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.cfg_device_number ( cfg_device_number ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_status ( cfg_status ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
//---------------------------------------------------------------------
// System (SYS) Interface
//---------------------------------------------------------------------
.sys_clk ( pcie_refclk ),
.sys_rst_n ( pcie_reset_n )
);
riffa_wrapper_vc707
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.CFG_INTERRUPT (cfg_interrupt),
.M_AXIS_RX_TREADY (m_axis_rx_tready),
.S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (s_axis_tx_tlast),
.S_AXIS_TX_TVALID (s_axis_tx_tvalid),
.S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
.FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (m_axis_rx_tlast),
.M_AXIS_RX_TVALID (m_axis_rx_tvalid),
.M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (s_axis_tx_tready),
.CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]),
.CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]),
.FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (cfg_interrupt_msienable),// TODO: Rename
.CFG_INTERRUPT_RDY (cfg_interrupt_rdy),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
.RX_NP_OK (rx_np_ok),
.TX_CFG_GNT (tx_cfg_gnt),
.RX_NP_REQ (rx_np_req)
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
// End:
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_control_data_rdy(
input posedge_clk,
input rx_resetn,
input rx_error_c,
input rx_error_d,
input [2:0] control,
input [2:0] control_l_r,
input is_control,
input [5:0] counter_neg,
input last_is_control,
output reg rx_error,
output reg ready_control_p_r,
output reg ready_data_p_r,
output reg rx_got_fct_fsm
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_fct_fsm <= 1'b0;
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
rx_error <= 1'b0;
end
else
begin
rx_error <= rx_error_c | rx_error_d;
if(counter_neg == 6'd4 && is_control)
begin
ready_control_p_r <= 1'b1;
ready_data_p_r <= 1'b0;
end
else if(counter_neg == 6'd32)
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b1;
end
else
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
rx_got_fct_fsm <= 1'b1;
else
rx_got_fct_fsm <= rx_got_fct_fsm;
end
end
endmodule
|
module cmd_parser #(
parameter SHOW_INIT_MSG = 1,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk,
input wire rstn,
output wire tx_start_o, // Signs that transmitter is busy
output wire [7:0] tx_data_o, // data byte to transmit
input wire tx_ready_i,
input wire [7:0] rx_data, // Data byte received
input wire new_rx_data, // Signs that a new byte was received
output reg [7:0] leds, // Board leds
output wire [7:0] sseg, // Board 7Segment Display
output wire [3:0] an, // 7 Segment Display enable
output reg [1:NPIS] part_pis_o, // Part interface, primary inputs
input wire [1:NPOS] part_pos_i // Part interface, primary outputs
);
// Standard names for scan chain inputs
wire clk_i;
reg scan_i, scan_i_nxt;
reg reset_i;
reg test_se_i;
reg test_tm_i;
reg scan_o;
//-- Number of bits needed for storing the baudrate divisor
`include "src/functions.vh"
localparam NPIS_WIDTH = clog2(NPIS);
localparam NPOS_WIDTH = clog2(NPOS);
reg [NPIS_WIDTH:0] cont_pis, cont_pis_nxt;
reg [NPOS_WIDTH:0] cont_pos, cont_pos_nxt;
reg [1:NPOS] part_pos;
reg [1:NPIS] part_pis;
reg csoc_clk;
reg clk_en, clk_en_nxt;
reg csoc_rstn, csoc_rstn_nxt;
reg csoc_test_se, csoc_test_se_nxt;
reg csoc_test_tm, csoc_test_tm_nxt;
reg csoc_uart_read, csoc_uart_read_nxt;
reg [7:0] csoc_data_o_reg, csoc_data_o_nxt;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
part_pis_o <= 0;
part_pos <= 0;
//
scan_i <= 0;
reset_i <= 0;
test_se_i <= 0;
test_tm_i <= 0;
//
scan_o <= 0;
end
else begin
part_pis_o[01] <= csoc_clk; //clk_i;
part_pis_o[09] <= scan_i;
part_pis_o[10] <= csoc_rstn; //reset_i;
part_pis_o[11] <= csoc_test_se; //test_se_i;
part_pis_o[12] <= csoc_test_tm; //test_tm_i;
//
part_pos <= part_pos_i;
//
scan_o <= part_pos_i[9];
//
scan_i <= scan_i_nxt;
end
end
// Put the bitgen creation time on display as a version
localparam VERSION_SIZE = 4;
reg [7:0] version [0:VERSION_SIZE-1];
initial begin
$readmemh("version.txt", version);
end
sevenseg ss0 (
.clk(clk),
.rstn(rstn),
.display_0(version[0]),
.display_1(version[1]),
.display_2(version[2]),
.display_3(version[3]),
.decplace(2'b10),
.seg(sseg),
.an(an)
);
always @(posedge clk or negedge rstn) begin
if (!rstn)
leds <= 0;
else
leds <= part_pos_i[2:9]; // joga nos leds os pinos
end
// CSOC CLOCK
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
csoc_clk <= 0;
end
else
if (clk_en)
csoc_clk <= ~csoc_clk;
end
assign clk_i = csoc_clk;
// Serial command parser
reg [4:0] state, state_nxt;
reg tx_start, tx_start_nxt;
reg run_done, run_done_nxt;
// TODO: REORGANIZE STATES
// MAIN_STATES
localparam
RESET = 0,
AVOID_MSG = 18,
INITIAL_MESSAGE = 1,
S1 = 2,
S2 = 3,
S3 = 4,
//
WAITING_COMMAND = 5,
//
SET_DUT_STATE = 6,
SA1 = 26,
//
GET_DUT_STATE = 7,
SB5 = 27,
SB51 = 30,
SB6 = 28,
SXX = 31,
//
EXECUTE_DUT = 8,
SET_INPUTS_STATE = 9,
//
GET_OUTPUTS_STATE = 10,
S4 = 11,
//
FREE_RUN_DUT = 12,
S5 = 13,
S11 = 14,
S21 = 15,
S31 = 16,
S111 = 17,
S1111 = 19,
//
SX5 = 20,
SX11 = 21,
SX21 = 22,
SX31 = 23,
SX111 = 24,
SX1111 = 25,
//
PAUSE_DUT = 29;
localparam
RESET_CMD = "r",
SET_STATE_CMD = "s",
GET_STATE_CMD = "g",
SET_INPUTS_CMD = "i",
GET_OUTPUTS_CMD = "o",
EXECUTE_CMD = "e",
FREE_RUN_CMD = "f",
PAUSE_CMD = "p";
assign tx_start_o = tx_start;
localparam MSG_SIZE = 20;
reg [7:0] mgs_mem [0:MSG_SIZE-1];
reg [7:0] msg_data, msg_data_nxt;
reg [5:0] msg_addr, msg_addr_nxt;
initial begin
$readmemh("initial_message.txt", mgs_mem);
end
reg [7:0] tx_data, tx_data_nxt;
reg [15:0] clk_count, clk_count_nxt;
reg [6:0] col_break, col_break_nxt;
reg [15:0] nclks, nclks_nxt;
reg low_byte, low_byte_nxt;
assign tx_data_o = tx_data;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= RESET;
tx_start <= 0;
tx_data <= 0;
clk_count <= 0;
col_break <= 0;
msg_data <= 0;
msg_addr <= 0;
run_done <= 0;
clk_en <= 0;
nclks <= 0;
low_byte <= 0;
//
csoc_rstn <= 0;
csoc_test_se <= 1;
csoc_test_tm <= 1;
csoc_uart_read <= 0;
csoc_data_o_reg <= 0;
//
cont_pos <= 0;
cont_pis <= 0;
end
else begin
state <= state_nxt;
tx_start <= tx_start_nxt;
clk_count <= clk_count_nxt;
col_break <= col_break_nxt;
msg_data <= mgs_mem[msg_addr];
msg_addr <= msg_addr_nxt;
tx_data <= tx_data_nxt;
run_done <= run_done_nxt;
clk_en <= clk_en_nxt;
nclks <= nclks_nxt;
low_byte <= low_byte_nxt;
//
csoc_rstn <= csoc_rstn_nxt;
csoc_test_se <= csoc_test_se_nxt;
csoc_test_tm <= csoc_test_tm_nxt;
csoc_uart_read <= csoc_uart_read_nxt;
csoc_data_o_reg <= csoc_data_o_nxt;
//
cont_pos <= cont_pos_nxt;
cont_pis <= cont_pis_nxt;
end
end
always @(*) begin
state_nxt = state;
tx_start_nxt = tx_start;
tx_data_nxt = tx_data;
clk_count_nxt = clk_count;
col_break_nxt = col_break;
msg_addr_nxt = msg_addr;
run_done_nxt = run_done;
clk_en_nxt = clk_en;
nclks_nxt = nclks;
low_byte_nxt = low_byte;
//
csoc_rstn_nxt = csoc_rstn;
csoc_test_se_nxt = csoc_test_se;
csoc_test_tm_nxt = csoc_test_tm;
csoc_uart_read_nxt = csoc_uart_read;
csoc_data_o_nxt = csoc_data_o_reg;
//
cont_pos_nxt = cont_pos;
cont_pis_nxt = cont_pis;
//
scan_i_nxt = scan_i;
case (state)
// ===================================================
RESET: begin
//
csoc_rstn_nxt = 1;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
csoc_uart_read_nxt = 0;
csoc_data_o_nxt = 0;
//
msg_addr_nxt = 0;
//
if (SHOW_INIT_MSG)
state_nxt = INITIAL_MESSAGE;
else
state_nxt = AVOID_MSG;
end
AVOID_MSG: begin
state_nxt = WAITING_COMMAND;
end
// ===================================================
INITIAL_MESSAGE: begin
if (tx_ready_i) begin
tx_start_nxt = 1;
state_nxt = S1;
end
end
S1: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S2;
end
end
S2: begin
if (tx_ready_i) begin
msg_addr_nxt = msg_addr + 1;
if (msg_addr <= MSG_SIZE) begin
state_nxt = S3;
end
else begin
msg_addr_nxt = 0;
state_nxt = WAITING_COMMAND;
end
end
end
S3: begin
if (msg_addr <= MSG_SIZE) begin
tx_data_nxt = msg_data;
end
else begin
tx_data_nxt = "\n";
end
state_nxt = INITIAL_MESSAGE;
end
// ===================================================
WAITING_COMMAND: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
csoc_rstn_nxt = 1;
nclks_nxt = 0;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
case (rx_data)
RESET_CMD: state_nxt = RESET; // reset the tester
EXECUTE_CMD: state_nxt = EXECUTE_DUT; // start PART execution for n cycles
FREE_RUN_CMD: state_nxt = FREE_RUN_DUT; // start PART execution until stop command
PAUSE_CMD: state_nxt = PAUSE_DUT; // pause PART execution
SET_STATE_CMD: state_nxt = SET_DUT_STATE; // set PART internal state
GET_STATE_CMD: state_nxt = GET_DUT_STATE; // get PART internal state
SET_INPUTS_CMD: state_nxt = SET_INPUTS_STATE; // set PART inputs
GET_OUTPUTS_CMD: state_nxt = GET_OUTPUTS_STATE; // get PART outputs
endcase
end
end
// ===================================================
SET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SB5;
//
clk_count_nxt = 0;
clk_en_nxt = 0;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
SB5: begin
if (clk_count >= nclks) begin
scan_i_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
if(new_rx_data) begin
clk_count_nxt = clk_count + 1;
case (rx_data)
"0": scan_i_nxt = 0;
"1": scan_i_nxt = 1;
endcase
state_nxt = SB51;
end
end
SB51: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = SB6;
end
end
SB6: begin
state_nxt = SXX;
end
SXX: begin
state_nxt = SB5;
end
// ===================================================
GET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S31;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S31: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = S5;
end
end
S5: begin
if (tx_ready_i) begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
clk_count_nxt = clk_count + 1;
state_nxt = S21;
end
end
end
S21: begin
case (scan_o)
0: tx_data_nxt = "0";
1: tx_data_nxt = "1";
endcase
state_nxt = S1111;
end
S1111: begin
tx_start_nxt = 1;
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S11;
end
end
S11: begin
if (clk_count > nclks) begin
clk_count_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else begin
state_nxt = S5;
end
end
// ===================================================
EXECUTE_DUT: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S4;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S4: begin
clk_en_nxt = 1;
if (csoc_clk)
if (clk_count == nclks-1) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
clk_count_nxt = clk_count + 1;
end
// ===================================================
FREE_RUN_DUT: begin
clk_en_nxt = 1;
if (csoc_clk)
clk_count_nxt = clk_count + 1;
if(new_rx_data)
if (rx_data == PAUSE_CMD)
state_nxt = WAITING_COMMAND;
end
PAUSE_DUT: begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
// ===================================================
GET_OUTPUTS_STATE: begin
clk_en_nxt = 0;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SX5;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pos_nxt = 1;
end
SX5: begin
if (tx_ready_i) begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
cont_pos_nxt = cont_pos + 1;
state_nxt = SX1111;
end
end
SX1111: begin
tx_start_nxt = 1;
state_nxt = SX111;
end
SX111: begin
tx_start_nxt = 0;
state_nxt = SX11;
end
SX11: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = SX21;
end
end
SX21: begin
if (tx_ready_i)
if (cont_pos > nclks) begin
state_nxt = WAITING_COMMAND;
end
else
state_nxt = SX31;
end
SX31: begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
state_nxt = SX5;
end
// ===================================================
SET_INPUTS_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SA1;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pis_nxt = 1;
end
SA1: begin
// if (csoc_clk)
clk_en_nxt = 1;
if(new_rx_data) begin
case (rx_data)
"0" : part_pis[cont_pis] = rx_data;
"1" : part_pis[cont_pis] = rx_data;
endcase
clk_en_nxt = 1;
cont_pis_nxt = cont_pis + 1;
if (cont_pis >= nclks) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
if (!csoc_clk)
clk_en_nxt = 1;
end
end
end
endcase
end
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 2 FIFO, loopy
module FIFOL2(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
input CLK ;
input RST ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg || DEQ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width{1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width{1'b0}} ;
end
else
`endif
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && !DEQ )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_fib.list"
`include "top.v"
module top_test_fibonacci;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test_fibonacci.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: KC705_Gen2x8If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx KC705 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "tlp.vh"
`include "xilinx.vh"
`timescale 1ps / 1ps
module KC705_Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [3:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
wire pcie_refclk;
wire pcie_reset_n;
wire user_clk;
wire user_reset;
wire user_lnk_up;
wire user_app_rdy;
wire s_axis_tx_tready;
wire [C_PCI_DATA_WIDTH-1 : 0] s_axis_tx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire [`SIG_XIL_TX_TUSER_W : 0] s_axis_tx_tuser;
wire [C_PCI_DATA_WIDTH-1 : 0] m_axis_rx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
wire tx_cfg_gnt;
wire rx_np_ok;
wire rx_np_req;
wire cfg_turnoff_ok;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [63:0] cfg_dsn;
wire [11 : 0] fc_cpld;
wire [7 : 0] fc_cplh;
wire [11 : 0] fc_npd;
wire [7 : 0] fc_nph;
wire [11 : 0] fc_pd;
wire [7 : 0] fc_ph;
wire [2 : 0] fc_sel;
wire [15 : 0] cfg_status;
wire [15 : 0] cfg_command;
wire [15 : 0] cfg_dstatus;
wire [15 : 0] cfg_dcommand;
wire [15 : 0] cfg_lstatus;
wire [15 : 0] cfg_lcommand;
wire [15 : 0] cfg_dcommand2;
wire [2 : 0] cfg_pcie_link_state;
wire cfg_pmcsr_pme_en;
wire [1 : 0] cfg_pmcsr_powerstate;
wire cfg_pmcsr_pme_status;
wire cfg_received_func_lvl_rst;
wire [4 : 0] cfg_pciecap_interrupt_msgnum;
wire cfg_to_turnoff;
wire [7 : 0] cfg_bus_number;
wire [4 : 0] cfg_device_number;
wire [2 : 0] cfg_function_number;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7 : 0] cfg_interrupt_di;
wire [7 : 0] cfg_interrupt_do;
wire [2 : 0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
assign cfg_turnoff_ok = 0;
assign cfg_trn_pending = 0;
assign cfg_pm_halt_aspm_l0s = 0;
assign cfg_pm_halt_aspm_l1 = 0;
assign cfg_pm_force_state_en = 0;
assign cfg_pm_force_state = 0;
assign cfg_dsn = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
assign cfg_interrupt_stat = 0;
assign cfg_pciecap_interrupt_msgnum = 0;
assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
// Core Top Level Wrapper
PCIeGen2x8If128 PCIeGen1x8If64_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
// Tx
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
// Rx
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI-S Interface
//---------------------------------------------------------------------
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( user_app_rdy ),
// TX
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
//---------------------------------------------------------------------
// Flow Control Interface
//---------------------------------------------------------------------
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.cfg_device_number ( cfg_device_number ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_status ( cfg_status ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
//---------------------------------------------------------------------
// System (SYS) Interface
//---------------------------------------------------------------------
.sys_clk ( pcie_refclk ),
.sys_rst_n ( pcie_reset_n )
);
riffa_wrapper_kc705
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.CFG_INTERRUPT (cfg_interrupt),
.M_AXIS_RX_TREADY (m_axis_rx_tready),
.S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (s_axis_tx_tlast),
.S_AXIS_TX_TVALID (s_axis_tx_tvalid),
.S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
.FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (m_axis_rx_tlast),
.M_AXIS_RX_TVALID (m_axis_rx_tvalid),
.M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (s_axis_tx_tready),
.CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]),
.CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]),
.FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (cfg_interrupt_msienable),// TODO: Rename
.CFG_INTERRUPT_RDY (cfg_interrupt_rdy),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
.RX_NP_OK (rx_np_ok),
.TX_CFG_GNT (tx_cfg_gnt),
.RX_NP_REQ (rx_np_req)
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/" "../..")
// End:
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// `define DEBUG
module spdif_dai #(
parameter MAX_CLK_PER_HALFBIT_LOG2 = 5 // 32 max
)(
input wire clk,
input wire rst,
input wire [(MAX_CLK_PER_HALFBIT_LOG2-1):0] clk_per_halfbit,
input wire signal_i,
output wire [23:0] data_o,
output wire ack_o,
output wire locked_o,
output wire lrck_o,
output wire [191:0] udata_o,
output wire [191:0] cdata_o);
// read async signal through chained ffs to avoid meta stable
wire buffed_signal;
parameter BUF_LEN = 2;
reg [(BUF_LEN-1):0] buf_ff;
always @(posedge clk)
buf_ff <= {buf_ff[(BUF_LEN-2):0], signal_i};
assign buffed_signal = buf_ff[BUF_LEN-1];
parameter HIST_LEN = 2;
reg [(HIST_LEN-1):0] lvl_history_ff;
always @(posedge clk)
lvl_history_ff <= {lvl_history_ff[(HIST_LEN-2):0], buffed_signal};
reg lvl_probe_ff;
always @(posedge clk)
if(lvl_history_ff[(HIST_LEN-1):(HIST_LEN-2)] == 2'b00)
lvl_probe_ff <= 0;
else if (lvl_history_ff[(HIST_LEN-1):(HIST_LEN-2)] == 2'b11)
lvl_probe_ff <= 1;
wire lvl_probe = lvl_probe_ff;
reg last_lvl;
always @(posedge clk)
last_lvl <= lvl_probe;
reg [7:0] subbit_hist_ff;
reg subbit_ready_ff;
reg signed [MAX_CLK_PER_HALFBIT_LOG2:0] pulse_duration;
always @(posedge clk) begin
subbit_ready_ff <= 0;
if(rst || last_lvl != lvl_probe) begin
pulse_duration <= 0;
end else if(pulse_duration == clk_per_halfbit/2 - 1) begin
pulse_duration <= -clk_per_halfbit + clk_per_halfbit/2;
subbit_hist_ff <= {subbit_hist_ff[6:0], last_lvl};
subbit_ready_ff <= 1;
end else
pulse_duration <= pulse_duration + 1;
end
wire subbit_ready = subbit_ready_ff;
wire [7:0] synccode = subbit_hist_ff;
wire subbit_counter_rst;
reg [5:0] subbit_counter;
parameter SUBBIT_COUNTER_UNLOCKED = 6'h3f;
always @(posedge clk) begin
if(subbit_counter_rst)
subbit_counter <= 0;
else if(subbit_ready && subbit_counter != SUBBIT_COUNTER_UNLOCKED)
subbit_counter <= subbit_counter + 1;
end
wire fullbit_signal = (subbit_counter[0] == 1'b0);
reg fullbit_signal_prev;
always @(posedge clk) begin
fullbit_signal_prev <= fullbit_signal;
end
wire fullbit_ready = fullbit_signal && !fullbit_signal_prev;
reg bmcdecode_bit_reg;
always @(subbit_hist_ff[1:0]) begin
case(subbit_hist_ff[1:0])
2'b10, 2'b01:
bmcdecode_bit_reg = 1;
2'b11, 2'b00:
bmcdecode_bit_reg = 0;
endcase
end
reg [23:0] bit_hist_ff;
always @(posedge clk) begin
if(fullbit_ready) begin
bit_hist_ff <= {bmcdecode_bit_reg, bit_hist_ff[23:1]};
end
end
// sync using synccode
parameter SYNCCODE_B1 = 8'b00010111;
parameter SYNCCODE_W1 = 8'b00011011;
parameter SYNCCODE_M1 = 8'b00011101;
parameter SYNCCODE_B2 = ~SYNCCODE_B1;
parameter SYNCCODE_W2 = ~SYNCCODE_W1;
parameter SYNCCODE_M2 = ~SYNCCODE_M1;
reg startframe_ff;
reg subbit_counter_rst_ff;
reg lrck_ff;
always @(posedge clk) begin
startframe_ff <= 0;
subbit_counter_rst_ff <= 0;
if(rst) begin
subbit_counter_rst_ff <= 1;
end else if(subbit_ready) begin
case(synccode)
SYNCCODE_B1, SYNCCODE_B2: begin
startframe_ff <= 1;
lrck_ff <= 0;
subbit_counter_rst_ff <= 1;
end
SYNCCODE_W1, SYNCCODE_W2: begin
lrck_ff <= 1;
subbit_counter_rst_ff <= 1;
end
SYNCCODE_M1, SYNCCODE_M2: begin
lrck_ff <= 0;
subbit_counter_rst_ff <= 1;
end
// default: begin end
endcase
end
end
assign subbit_counter_rst = subbit_counter_rst_ff;
// output wire locked status / lrck
reg [5:0] unlock_tolerance_counter;
parameter UNLOCK_TOLERANCE = 48;
always @(posedge clk) begin
if(subbit_counter != SUBBIT_COUNTER_UNLOCKED)
unlock_tolerance_counter <= 0;
else if (unlock_tolerance_counter != UNLOCK_TOLERANCE)
unlock_tolerance_counter <= unlock_tolerance_counter + 1;
end
assign locked_o = (unlock_tolerance_counter != UNLOCK_TOLERANCE);
assign lrck_o = lrck_ff;
// output wire data
wire audiodata_ready = (subbit_counter == 24*2) && subbit_ready; // subbit_ready is for 1clk pulse width and pipeline wait
reg [23:0] data_ff;
reg ack_ff;
always @(posedge clk) begin
if(audiodata_ready) begin
`ifdef DEBUG
$display("spdif_dai: lr %d recv %h", lrck_o, bit_hist_ff[23:0]);
`endif
data_ff <= bit_hist_ff[23:0];
ack_ff <= locked_o; // only ack if locked
end else
ack_ff <= 0;
end
assign data_o = data_ff;
assign ack_o = ack_ff;
// output wire {u,c}data
wire extradata_ready = (subbit_counter == (24+4)*2) && subbit_ready; // subbit_ready is for 1clk pulse width and pipeline wait
reg [191:0] udata_shiftreg;
reg [191:0] cdata_shiftreg;
always @(posedge clk) begin
if(rst) begin
udata_shiftreg <= 0;
cdata_shiftreg <= 0;
end else if(extradata_ready) begin
udata_shiftreg <= {udata_shiftreg[190:0], bit_hist_ff[22]};
cdata_shiftreg <= {cdata_shiftreg[190:0], bit_hist_ff[21]};
end
end
reg [191:0] udata_ff;
reg [191:0] cdata_ff;
always @(posedge clk) begin
if(startframe_ff) begin
udata_ff <= udata_shiftreg;
cdata_ff <= cdata_shiftreg;
end
end
assign udata_o = udata_ff;
assign cdata_o = cdata_ff;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:36 12/10/2012
// Design Name: top
// Module Name: C:/Documents and Settings/SPItoUART_Loopback/tb.v
// Project Name: SPItoUART_Loopback
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb;
// Inputs
reg rxd;
reg rst;
reg clk;
// Outputs
wire txd;
// Instantiate the Unit Under Test (UUT)
top uut (
.txd(txd),
.rxd(rxd),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
rxd = 0;
rst = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rxd = 1;
rst = 1;
#100;
rst = 0;
#10000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 0; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 0101
#100000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 1; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 1101
end
always begin
#20 clk = ~clk;
end
endmodule
|
`timescale 1ps / 1ps
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ../demo-out/main.v
// {{{
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ./autofpga ./autofpga -d -o ../demo-out -I ../auto-data bkram.txt buserr.txt clkcounter.txt clock.txt enet.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt icape.txt legalgen.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt sdram.txt sdspi.txt spio.txt version.txt wbmouse.txt wboledbw.txt wbpmic.txt wbscopc.txt wbscope.txt wbubus.txt xpander.txt zipmaster.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
//
// Macro defines
// {{{
//
//
// Here is a list of defines which may be used, post auto-design
// (not post-build), to turn particular peripherals (and bus masters)
// on and off. In particular, to turn off support for a particular
// design component, just comment out its respective `define below.
//
// These lines are taken from the respective @ACCESS tags for each of our
// components. If a component doesn't have an @ACCESS tag, it will not
// be listed here.
//
// First, the independent access fields for any bus masters
`define WBUBUS_MASTER
// And then for the independent peripherals
`define INCLUDE_ZIPCPU
`define GPIO_ACCESS
`define FLASH_ACCESS
`define GPSUART_ACCESS
`define BKRAM_ACCESS
`define ETHERNET_ACCESS
`define BUSPIC_ACCESS
`define SDSPI_ACCESS
`define HDMIIN_ACCESS
`define GPSTRK_ACCESS
`define NETCTRL_ACCESS
`define CFG_ACCESS
`define PWRCOUNT_ACCESS
`define HDMI_OUT_EDID_ACCESS
`define RTC_ACCESS
`define SPIO_ACCESS
`define MOUSE_ACCESS
`define OLEDBW_ACCESS
`define MICROPHONE_ACCESS
`define SCOPC_SCOPC
`define SCOPE_SCOPE
`define HDMI_IN_EDID_ACCESS
//
//
// The list of those things that have @DEPENDS tags
//
//
//
// Dependencies
// Any core with both an @ACCESS and a @DEPENDS tag will show up here.
// The @DEPENDS tag will turn into a series of ifdef's, with the @ACCESS
// being defined only if all of the ifdef's are true//
`ifdef RTC_ACCESS
`define RTCDATE_ACCESS
`endif // RTC_ACCESS
`ifdef FLASH_ACCESS
`define FLASHCFG_ACCESS
`endif // FLASH_ACCESS
// The following have unmet dependencies. They are listed
// here for reference, but their dependencies cannot be met.
`ifdef ALLCLOCKS_PRESENT
`define SDRAM_ACCESS
`endif
//
// End of dependency list
//
//
// }}}
////////////////////////////////////////////////////////////////////////////////
//
// Any include files
// {{{
// These are drawn from anything with a MAIN.INCLUDE definition.
// }}}
//
// Finally, we define our main module itself. We start with the list of
// I/O ports, or wires, passed into (or out of) the main function.
//
// These fields are copied verbatim from the respective I/O port lists,
// from the fields given by @MAIN.PORTLIST
//
module main(i_clk, i_reset,
// {{{
i_cpu_reset,
// HDMI output ports
i_hdmi_out_clk,
// HDMI output pixels
o_hdmi_out_r, o_hdmi_out_g, o_hdmi_out_b,
// GPIO ports
i_gpio, o_gpio,
// The Universal QSPI Flash
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
// The GPS-UART
i_gpsu_rx, o_gpsu_tx,
// Ethernet control (packets) lines
o_net_reset_n,
// eth_int_b // Interrupt, leave floating
// eth_pme_b // Power management event, leave floating
i_net_rx_clk, i_net_rx_dv, i_net_rx_err, i_net_rxd,
o_net_tx_clk, o_net_tx_ctl, o_net_txd,
// The SD-Card wires
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
// HDMI input ports
i_hdmi_in_clk,
i_hdmi_in_r, i_hdmi_in_g, i_hdmi_in_b,
i_hdmi_in_hsclk,
// HDMI input delay control
i_hdmi_in_actual_delay_r, i_hdmi_in_actual_delay_g,
i_hdmi_in_actual_delay_b, o_hdmi_in_delay,
// The GPS 1PPS signal port
i_gps_pps,
// The ethernet MDIO wires
o_mdclk, o_mdio, o_mdwe, i_mdio,
// HDMI out (source) EDID I2C ports
i_hdmi_out_scl, i_hdmi_out_sda, o_hdmi_out_scl, o_hdmi_out_sda,
// SDRAM ports
o_sdram_cyc, o_sdram_stb, o_sdram_we,
o_sdram_addr, o_sdram_data, o_sdram_sel,
i_sdram_stall, i_sdram_ack, i_sdram_data,
i_sdram_err
, i_sdram_dbg,
// SPIO interface
i_sw, i_btnc, i_btnd, i_btnl, i_btnr, i_btnu, o_led,
// The PS/2 Mouse
i_ps2, o_ps2,
// OLED control interface (roughly SPI)
o_oled_sck, o_oled_mosi, o_oled_dcn,
o_oled_reset_n, o_oled_panel_en, o_oled_logic_en,
// The PMic3 microphone wires
o_mic_csn, o_mic_sck, i_mic_din,
// UART/host to wishbone interface
i_host_uart_rx, o_host_uart_tx,
// HDMI input EDID I2C ports
i_hdmi_in_scl, i_hdmi_in_sda, o_hdmi_in_scl, o_hdmi_in_sda // }}}
);
////////////////////////////////////////////////////////////////////////////////
//
// Any parameter definitions
// {{{
// These are drawn from anything with a MAIN.PARAM definition.
// As they aren't connected to the toplevel at all, it would
// be best to use localparam over parameter, but here we don't
// check
//
//
// Variables/definitions needed by the ZipCPU BUS master
//
//
// A 32-bit address indicating where the ZipCPU should start running
// from
`ifdef BKROM_ACCESS
localparam RESET_ADDRESS = @$(/bkrom.BASE);
`else
`ifdef FLASH_ACCESS
localparam RESET_ADDRESS = @$RESET_ADDRESS;
`else
localparam RESET_ADDRESS = 436207616;
`endif // FLASH_ACCESS
`endif // BKROM_ACCESS
//
// The number of valid bits on the bus
localparam ZIP_ADDRESS_WIDTH = 28; // Zip-CPU address width
//
// Number of ZipCPU interrupts
localparam ZIP_INTS = 16;
//
// ZIP_START_HALTED
//
// A boolean, indicating whether or not the ZipCPU be halted on startup?
`ifdef BKROM_ACCESS
localparam ZIP_START_HALTED=1'b0;
`else
localparam ZIP_START_HALTED=1'b1;
`endif
localparam [31:0] GPSCLOCK_DEFAULT_STEP = 32'haabcc771;
localparam ICAPE_LGDIV=3;
// }}}
////////////////////////////////////////////////////////////////////////////////
//
// Port declarations
// {{{
// The next step is to declare all of the various ports that were just
// listed above.
//
// The following declarations are taken from the values of the various
// @MAIN.IODECL keys.
//
input wire i_clk;
// verilator lint_off UNUSED
input wire i_reset;
// verilator lint_on UNUSED
input wire i_cpu_reset;
// Verilator lint_off UNUSED
// HDMI output clock
input wire i_hdmi_out_clk;
// Verilator lint_on UNUSED
// HDMI output pixels
output wire [9:0] o_hdmi_out_r, o_hdmi_out_g, o_hdmi_out_b;
localparam NGPI = 16, NGPO=16;
// GPIO ports
input [(NGPI-1):0] i_gpio;
output wire [(NGPO-1):0] o_gpio;
// The Universal QSPI flash
output wire o_qspi_cs_n, o_qspi_sck;
output wire [3:0] o_qspi_dat;
input wire [3:0] i_qspi_dat;
output wire [1:0] o_qspi_mod;
input wire i_gpsu_rx;
output wire o_gpsu_tx;
// Ethernet (RGMII) control
output wire o_net_reset_n;
input wire i_net_rx_clk, i_net_rx_dv, i_net_rx_err;
input wire [7:0] i_net_rxd;
output wire [1:0] o_net_tx_clk;
output wire o_net_tx_ctl;
output wire [7:0] o_net_txd;
// SD-Card declarations
output wire o_sd_sck, o_sd_cmd;
output wire [3:0] o_sd_data;
// verilator lint_off UNUSED
input wire i_sd_cmd;
input wire [3:0] i_sd_data;
// verilator lint_on UNUSED
input wire i_sd_detect;
// HDMI input ports
input wire i_hdmi_in_clk;
input wire [9:0] i_hdmi_in_r, i_hdmi_in_g, i_hdmi_in_b;
// verilator lint_off UNUSED
input wire i_hdmi_in_hsclk;
// verilator lint_on UNUSED
// Sub-pixel delay control
input wire [4:0] i_hdmi_in_actual_delay_r;
input wire [4:0] i_hdmi_in_actual_delay_g;
input wire [4:0] i_hdmi_in_actual_delay_b;
output wire [4:0] o_hdmi_in_delay;
//The GPS Clock
input wire i_gps_pps;
// Ethernet control (MDIO)
output wire o_mdclk, o_mdio, o_mdwe;
input wire i_mdio;
// HDMI input EDID I2C ports
input wire i_hdmi_out_scl, i_hdmi_out_sda;
output wire o_hdmi_out_scl, o_hdmi_out_sda;
// SDRAM I/O declarations
output wire o_sdram_cyc,
o_sdram_stb, o_sdram_we;
output wire [25-1:0] o_sdram_addr;
output wire [(128-1):0] o_sdram_data;
output wire [(128/8)-1:0] o_sdram_sel;
//
input wire i_sdram_ack;
input wire i_sdram_stall;
input wire [(128-1):0] i_sdram_data;
// Verilator lint_off UNUSED
input wire i_sdram_err;
input wire [31:0] i_sdram_dbg;
// Verilator lint_on UNUSED
// SPIO interface
input wire [8-1:0] i_sw;
input wire i_btnc, i_btnd, i_btnl, i_btnr, i_btnu;
output wire [8-1:0] o_led;
// The PS/2 Mouse
input [1:0] i_ps2;
output wire [1:0] o_ps2;
// OLEDBW interface
output wire o_oled_sck, o_oled_mosi,
o_oled_dcn, o_oled_reset_n, o_oled_panel_en,
o_oled_logic_en;
output wire o_mic_csn, o_mic_sck;
input wire i_mic_din;
input wire i_host_uart_rx;
output wire o_host_uart_tx;
// HDMI input EDID I2C ports
input wire i_hdmi_in_scl, i_hdmi_in_sda;
output wire o_hdmi_in_scl, o_hdmi_in_sda;
// }}}
// Make Verilator happy
// {{{
// Defining bus wires for lots of components often ends up with unused
// wires lying around. We'll turn off Ver1lator's lint warning
// here that checks for unused wires.
// }}}
// verilator lint_off UNUSED
////////////////////////////////////////////////////////////////////////
//
// Declaring interrupt lines
// {{{
// These declarations come from the various components values
// given under the @INT.<interrupt name>.WIRE key.
//
wire zip_cpu_int; // zip.INT.ZIP.WIRE
wire scop_edid_int; // scop_edid.INT.SCOPE.WIRE
wire gpio_int; // gpio.INT.GPIO.WIRE
wire gpsurxf_int; // gpsu.INT.GPSRXF.WIRE
wire gpsutxf_int; // gpsu.INT.GPSTXF.WIRE
wire gpsutx_int; // gpsu.INT.GPSTX.WIRE
wire gpsurx_int; // gpsu.INT.GPSRX.WIRE
wire nettx_int; // netp.INT.NETTX.WIRE
wire netrx_int; // netp.INT.NETRX.WIRE
wire w_bus_int; // buspic.INT.BUS.WIRE
wire sdcard_int; // sdcard.INT.SDCARD.WIRE
wire hdmiin_int; // hdmiin.INT.VSYNC.WIRE
wire ck_pps; // gck.INT.PPS.WIRE
wire scop_hdmiin_int; // scope_hdmiin.INT.HINSCOPE.WIRE
wire edid_out_int; // edout.INT.EDID.WIRE
wire rtc_int; // rtc.INT.RTC.WIRE
wire spio_int; // spio.INT.SPIO.WIRE
wire mous_interrupt; // mous.INT.MOUSE.WIRE
wire oled_int; // oled.INT.OLED.WIRE
wire pmic_int; // pmic.INT.MIC.WIRE
// }}}
////////////////////////////////////////////////////////////////////////
//
// Component declarations
// {{{
// These declarations come from the @MAIN.DEFNS keys found in the
// various components comprising the design.
//
// ZipSystem/ZipCPU connection definitions
// All we define here is a set of scope wires
wire [31:0] zip_debug;
wire zip_trigger;
wire [ZIP_INTS-1:0] zip_int_vector;
wire edid_scope_trigger;
wire [30:0] edid_scope_data;
wire sd_reset;
`ifndef GPSTRK_ACCESS
reg [31:0] r_subseconds_data;
`endif
// Definitions for the flash debug port
wire flash_dbg_trigger;
wire [31:0] flash_debug;
reg r_clkhdmiout_ack;
wire w_gpsu_cts_n, w_gpsu_rts_n;
assign w_gpsu_cts_n=1'b1;
reg [28-1:0] r_buserr_addr;
//
wire netp_debug_clk;
wire [31:0] netp_debug;
reg r_sysclk_ack;
`include "builddate.v"
reg r_clkhdmiin_ack;
wire tb_pps;
wire[31:0] sdspi_debug;
reg [31:0] r_hdmi_scope_frame_offset_data;
reg r_hdmi_scope_frame_offset_ack;
initial r_hdmi_scope_frame_offset_data=0;
always @(posedge i_clk)
if ((wb_stb)&&(hdmi_scope_frame_offset_sel)&&(wb_we))
r_hdmi_scope_frame_offset_data <= wb_data;
assign hdmi_scope_frame_offset_data = r_hdmi_scope_frame_offset_data;
assign hdmi_scope_frame_offset_stall= 1'b0;
always @(posedge i_clk)
r_hdmi_scope_frame_offset_ack <= (wb_stb)&&(hdmi_scope_frame_offset_sel);
wire [31:0] hin_dbg_scope;
wire [29:0] hin_pixels;
wire [9:0] hdmi_in_r;
wire [9:0] hdmi_in_g;
wire [9:0] hdmi_in_b;
wire gps_pps, gps_led, gps_locked, gps_tracking;
wire [63:0] gps_now, gps_err, gps_step;
wire [1:0] gps_dbg_tick;
// BUILDTIME doesnt need to include builddate.v a second time
// `include "builddate.v"
reg [31:0] r_pwrcount_data;
wire [31:0] hdmi_in_data;
wire [31:0] edido_dbg;
// Definitions in support of the GPS driven RTC
// This clock step is designed to match 100000000 Hz
localparam [31:0] RTC_CLKSTEP = 32'h002af31d;
wire rtc_ppd;
reg r_rtc_ack;
`ifdef GPSTRK_ACCESS
wire rtc_pps;
`endif
wire [5-1:0] w_btn;
wire [8-1:0] w_led;
// scrn_mouse is a 32-bit field containing 16-bits of x-position and
// 16-bits of y position, limited to the size of the screen.
wire [31:0] scrn_mouse;
// Remove this scope tag via inheritance when/if you connect the
// scope interrupt
//
// Virilator lint_off UNUSED
wire scopc_int;
// Virilator lint_on UNUSED
// Remove this scope tag via inheritance when/if you connect the
// scope interrupt
//
// Virilator lint_off UNUSED
wire scope_int;
// Virilator lint_on UNUSED
//
//
// UART interface
//
//
localparam [23:0] BUSUART = 24'h64; // 1000000 baud
//
wire w_ck_uart, w_uart_tx;
wire rx_host_stb;
wire [7:0] rx_host_data;
wire tx_host_stb;
wire [7:0] tx_host_data;
wire tx_host_busy;
//
// Definitions for the WB-UART converter. We really only need one
// (more) non-bus wire--one to use to select if we are interacting
// with the ZipCPU or not.
wire wbu_zip_sel;
wire [0:0] wbubus_dbg;
`ifndef INCLUDE_ZIPCPU
//
// The bus-console depends upon the zip_dbg wires. If there is no
// ZipCPU defining them, we'll need to define them here anyway.
//
wire zip_dbg_stall, zip_dbg_ack;
wire [31:0] zip_dbg_data;
`endif
wire [31:0] edid_dbg;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declaring interrupt vector wires
// {{{
// These declarations come from the various components having
// PIC and PIC.MAX keys.
//
wire [14:0] sys_int_vector;
wire [14:0] alt_int_vector;
wire [14:0] bus_int_vector;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declare bus signals
// {{{
////////////////////////////////////////////////////////////////////////
// Bus wb
// {{{
// Wishbone definitions for bus wb, component zip
// Verilator lint_off UNUSED
wire wb_zip_cyc, wb_zip_stb, wb_zip_we;
wire [27:0] wb_zip_addr;
wire [31:0] wb_zip_data;
wire [3:0] wb_zip_sel;
wire wb_zip_stall, wb_zip_ack, wb_zip_err;
wire [31:0] wb_zip_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component wbu_arbiter
// Verilator lint_off UNUSED
wire wb_wbu_arbiter_cyc, wb_wbu_arbiter_stb, wb_wbu_arbiter_we;
wire [27:0] wb_wbu_arbiter_addr;
wire [31:0] wb_wbu_arbiter_data;
wire [3:0] wb_wbu_arbiter_sel;
wire wb_wbu_arbiter_stall, wb_wbu_arbiter_ack, wb_wbu_arbiter_err;
wire [31:0] wb_wbu_arbiter_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component buildtime
// Verilator lint_off UNUSED
wire wb_buildtime_cyc, wb_buildtime_stb, wb_buildtime_we;
wire [27:0] wb_buildtime_addr;
wire [31:0] wb_buildtime_data;
wire [3:0] wb_buildtime_sel;
wire wb_buildtime_stall, wb_buildtime_ack, wb_buildtime_err;
wire [31:0] wb_buildtime_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component buserr
// Verilator lint_off UNUSED
wire wb_buserr_cyc, wb_buserr_stb, wb_buserr_we;
wire [27:0] wb_buserr_addr;
wire [31:0] wb_buserr_data;
wire [3:0] wb_buserr_sel;
wire wb_buserr_stall, wb_buserr_ack, wb_buserr_err;
wire [31:0] wb_buserr_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component buspic
// Verilator lint_off UNUSED
wire wb_buspic_cyc, wb_buspic_stb, wb_buspic_we;
wire [27:0] wb_buspic_addr;
wire [31:0] wb_buspic_data;
wire [3:0] wb_buspic_sel;
wire wb_buspic_stall, wb_buspic_ack, wb_buspic_err;
wire [31:0] wb_buspic_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component clkhdmiin
// Verilator lint_off UNUSED
wire wb_clkhdmiin_cyc, wb_clkhdmiin_stb, wb_clkhdmiin_we;
wire [27:0] wb_clkhdmiin_addr;
wire [31:0] wb_clkhdmiin_data;
wire [3:0] wb_clkhdmiin_sel;
wire wb_clkhdmiin_stall, wb_clkhdmiin_ack, wb_clkhdmiin_err;
wire [31:0] wb_clkhdmiin_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component clkhdmiout
// Verilator lint_off UNUSED
wire wb_clkhdmiout_cyc, wb_clkhdmiout_stb, wb_clkhdmiout_we;
wire [27:0] wb_clkhdmiout_addr;
wire [31:0] wb_clkhdmiout_data;
wire [3:0] wb_clkhdmiout_sel;
wire wb_clkhdmiout_stall, wb_clkhdmiout_ack, wb_clkhdmiout_err;
wire [31:0] wb_clkhdmiout_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component gpio
// Verilator lint_off UNUSED
wire wb_gpio_cyc, wb_gpio_stb, wb_gpio_we;
wire [27:0] wb_gpio_addr;
wire [31:0] wb_gpio_data;
wire [3:0] wb_gpio_sel;
wire wb_gpio_stall, wb_gpio_ack, wb_gpio_err;
wire [31:0] wb_gpio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component hdmi_scope_frame_offset
// Verilator lint_off UNUSED
wire wb_hdmi_scope_frame_offset_cyc, wb_hdmi_scope_frame_offset_stb, wb_hdmi_scope_frame_offset_we;
wire [27:0] wb_hdmi_scope_frame_offset_addr;
wire [31:0] wb_hdmi_scope_frame_offset_data;
wire [3:0] wb_hdmi_scope_frame_offset_sel;
wire wb_hdmi_scope_frame_offset_stall, wb_hdmi_scope_frame_offset_ack, wb_hdmi_scope_frame_offset_err;
wire [31:0] wb_hdmi_scope_frame_offset_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component pwrcount
// Verilator lint_off UNUSED
wire wb_pwrcount_cyc, wb_pwrcount_stb, wb_pwrcount_we;
wire [27:0] wb_pwrcount_addr;
wire [31:0] wb_pwrcount_data;
wire [3:0] wb_pwrcount_sel;
wire wb_pwrcount_stall, wb_pwrcount_ack, wb_pwrcount_err;
wire [31:0] wb_pwrcount_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component rtcdate
// Verilator lint_off UNUSED
wire wb_rtcdate_cyc, wb_rtcdate_stb, wb_rtcdate_we;
wire [27:0] wb_rtcdate_addr;
wire [31:0] wb_rtcdate_data;
wire [3:0] wb_rtcdate_sel;
wire wb_rtcdate_stall, wb_rtcdate_ack, wb_rtcdate_err;
wire [31:0] wb_rtcdate_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component spio
// Verilator lint_off UNUSED
wire wb_spio_cyc, wb_spio_stb, wb_spio_we;
wire [27:0] wb_spio_addr;
wire [31:0] wb_spio_data;
wire [3:0] wb_spio_sel;
wire wb_spio_stall, wb_spio_ack, wb_spio_err;
wire [31:0] wb_spio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component subseconds
// Verilator lint_off UNUSED
wire wb_subseconds_cyc, wb_subseconds_stb, wb_subseconds_we;
wire [27:0] wb_subseconds_addr;
wire [31:0] wb_subseconds_data;
wire [3:0] wb_subseconds_sel;
wire wb_subseconds_stall, wb_subseconds_ack, wb_subseconds_err;
wire [31:0] wb_subseconds_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component sysclk
// Verilator lint_off UNUSED
wire wb_sysclk_cyc, wb_sysclk_stb, wb_sysclk_we;
wire [27:0] wb_sysclk_addr;
wire [31:0] wb_sysclk_data;
wire [3:0] wb_sysclk_sel;
wire wb_sysclk_stall, wb_sysclk_ack, wb_sysclk_err;
wire [31:0] wb_sysclk_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(SIO), component version
// Verilator lint_off UNUSED
wire wb_version_cyc, wb_version_stb, wb_version_we;
wire [27:0] wb_version_addr;
wire [31:0] wb_version_data;
wire [3:0] wb_version_sel;
wire wb_version_stall, wb_version_ack, wb_version_err;
wire [31:0] wb_version_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component gck
// Verilator lint_off UNUSED
wire wb_gck_cyc, wb_gck_stb, wb_gck_we;
wire [27:0] wb_gck_addr;
wire [31:0] wb_gck_data;
wire [3:0] wb_gck_sel;
wire wb_gck_stall, wb_gck_ack, wb_gck_err;
wire [31:0] wb_gck_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component mous
// Verilator lint_off UNUSED
wire wb_mous_cyc, wb_mous_stb, wb_mous_we;
wire [27:0] wb_mous_addr;
wire [31:0] wb_mous_data;
wire [3:0] wb_mous_sel;
wire wb_mous_stall, wb_mous_ack, wb_mous_err;
wire [31:0] wb_mous_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component oled
// Verilator lint_off UNUSED
wire wb_oled_cyc, wb_oled_stb, wb_oled_we;
wire [27:0] wb_oled_addr;
wire [31:0] wb_oled_data;
wire [3:0] wb_oled_sel;
wire wb_oled_stall, wb_oled_ack, wb_oled_err;
wire [31:0] wb_oled_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component rtc
// Verilator lint_off UNUSED
wire wb_rtc_cyc, wb_rtc_stb, wb_rtc_we;
wire [27:0] wb_rtc_addr;
wire [31:0] wb_rtc_data;
wire [3:0] wb_rtc_sel;
wire wb_rtc_stall, wb_rtc_ack, wb_rtc_err;
wire [31:0] wb_rtc_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component gtb
// Verilator lint_off UNUSED
wire wb_gtb_cyc, wb_gtb_stb, wb_gtb_we;
wire [27:0] wb_gtb_addr;
wire [31:0] wb_gtb_data;
wire [3:0] wb_gtb_sel;
wire wb_gtb_stall, wb_gtb_ack, wb_gtb_err;
wire [31:0] wb_gtb_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component netp
// Verilator lint_off UNUSED
wire wb_netp_cyc, wb_netp_stb, wb_netp_we;
wire [27:0] wb_netp_addr;
wire [31:0] wb_netp_data;
wire [3:0] wb_netp_sel;
wire wb_netp_stall, wb_netp_ack, wb_netp_err;
wire [31:0] wb_netp_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component hdmiin
// Verilator lint_off UNUSED
wire wb_hdmiin_cyc, wb_hdmiin_stb, wb_hdmiin_we;
wire [27:0] wb_hdmiin_addr;
wire [31:0] wb_hdmiin_data;
wire [3:0] wb_hdmiin_sel;
wire wb_hdmiin_stall, wb_hdmiin_ack, wb_hdmiin_err;
wire [31:0] wb_hdmiin_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component wb_sio
// Verilator lint_off UNUSED
wire wb_sio_cyc, wb_sio_stb, wb_sio_we;
wire [27:0] wb_sio_addr;
wire [31:0] wb_sio_data;
wire [3:0] wb_sio_sel;
wire wb_sio_stall, wb_sio_ack, wb_sio_err;
wire [31:0] wb_sio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component edin
// Verilator lint_off UNUSED
wire wb_edin_cyc, wb_edin_stb, wb_edin_we;
wire [27:0] wb_edin_addr;
wire [31:0] wb_edin_data;
wire [3:0] wb_edin_sel;
wire wb_edin_stall, wb_edin_ack, wb_edin_err;
wire [31:0] wb_edin_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb(DIO), component edout
// Verilator lint_off UNUSED
wire wb_edout_cyc, wb_edout_stb, wb_edout_we;
wire [27:0] wb_edout_addr;
wire [31:0] wb_edout_data;
wire [3:0] wb_edout_sel;
wire wb_edout_stall, wb_edout_ack, wb_edout_err;
wire [31:0] wb_edout_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component flashcfg
// Verilator lint_off UNUSED
wire wb_flashcfg_cyc, wb_flashcfg_stb, wb_flashcfg_we;
wire [27:0] wb_flashcfg_addr;
wire [31:0] wb_flashcfg_data;
wire [3:0] wb_flashcfg_sel;
wire wb_flashcfg_stall, wb_flashcfg_ack, wb_flashcfg_err;
wire [31:0] wb_flashcfg_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component pmic
// Verilator lint_off UNUSED
wire wb_pmic_cyc, wb_pmic_stb, wb_pmic_we;
wire [27:0] wb_pmic_addr;
wire [31:0] wb_pmic_data;
wire [3:0] wb_pmic_sel;
wire wb_pmic_stall, wb_pmic_ack, wb_pmic_err;
wire [31:0] wb_pmic_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component scop_edid
// Verilator lint_off UNUSED
wire wb_scop_edid_cyc, wb_scop_edid_stb, wb_scop_edid_we;
wire [27:0] wb_scop_edid_addr;
wire [31:0] wb_scop_edid_data;
wire [3:0] wb_scop_edid_sel;
wire wb_scop_edid_stall, wb_scop_edid_ack, wb_scop_edid_err;
wire [31:0] wb_scop_edid_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component scopc
// Verilator lint_off UNUSED
wire wb_scopc_cyc, wb_scopc_stb, wb_scopc_we;
wire [27:0] wb_scopc_addr;
wire [31:0] wb_scopc_data;
wire [3:0] wb_scopc_sel;
wire wb_scopc_stall, wb_scopc_ack, wb_scopc_err;
wire [31:0] wb_scopc_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component scope
// Verilator lint_off UNUSED
wire wb_scope_cyc, wb_scope_stb, wb_scope_we;
wire [27:0] wb_scope_addr;
wire [31:0] wb_scope_data;
wire [3:0] wb_scope_sel;
wire wb_scope_stall, wb_scope_ack, wb_scope_err;
wire [31:0] wb_scope_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component scope_hdmiin
// Verilator lint_off UNUSED
wire wb_scope_hdmiin_cyc, wb_scope_hdmiin_stb, wb_scope_hdmiin_we;
wire [27:0] wb_scope_hdmiin_addr;
wire [31:0] wb_scope_hdmiin_data;
wire [3:0] wb_scope_hdmiin_sel;
wire wb_scope_hdmiin_stall, wb_scope_hdmiin_ack, wb_scope_hdmiin_err;
wire [31:0] wb_scope_hdmiin_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component gpsu
// Verilator lint_off UNUSED
wire wb_gpsu_cyc, wb_gpsu_stb, wb_gpsu_we;
wire [27:0] wb_gpsu_addr;
wire [31:0] wb_gpsu_data;
wire [3:0] wb_gpsu_sel;
wire wb_gpsu_stall, wb_gpsu_ack, wb_gpsu_err;
wire [31:0] wb_gpsu_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component sdcard
// Verilator lint_off UNUSED
wire wb_sdcard_cyc, wb_sdcard_stb, wb_sdcard_we;
wire [27:0] wb_sdcard_addr;
wire [31:0] wb_sdcard_data;
wire [3:0] wb_sdcard_sel;
wire wb_sdcard_stall, wb_sdcard_ack, wb_sdcard_err;
wire [31:0] wb_sdcard_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component cfg
// Verilator lint_off UNUSED
wire wb_cfg_cyc, wb_cfg_stb, wb_cfg_we;
wire [27:0] wb_cfg_addr;
wire [31:0] wb_cfg_data;
wire [3:0] wb_cfg_sel;
wire wb_cfg_stall, wb_cfg_ack, wb_cfg_err;
wire [31:0] wb_cfg_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component mdio
// Verilator lint_off UNUSED
wire wb_mdio_cyc, wb_mdio_stb, wb_mdio_we;
wire [27:0] wb_mdio_addr;
wire [31:0] wb_mdio_data;
wire [3:0] wb_mdio_sel;
wire wb_mdio_stall, wb_mdio_ack, wb_mdio_err;
wire [31:0] wb_mdio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component wb_dio
// Verilator lint_off UNUSED
wire wb_dio_cyc, wb_dio_stb, wb_dio_we;
wire [27:0] wb_dio_addr;
wire [31:0] wb_dio_data;
wire [3:0] wb_dio_sel;
wire wb_dio_stall, wb_dio_ack, wb_dio_err;
wire [31:0] wb_dio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component netb
// Verilator lint_off UNUSED
wire wb_netb_cyc, wb_netb_stb, wb_netb_we;
wire [27:0] wb_netb_addr;
wire [31:0] wb_netb_data;
wire [3:0] wb_netb_sel;
wire wb_netb_stall, wb_netb_ack, wb_netb_err;
wire [31:0] wb_netb_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component bkram
// Verilator lint_off UNUSED
wire wb_bkram_cyc, wb_bkram_stb, wb_bkram_we;
wire [27:0] wb_bkram_addr;
wire [31:0] wb_bkram_data;
wire [3:0] wb_bkram_sel;
wire wb_bkram_stall, wb_bkram_ack, wb_bkram_err;
wire [31:0] wb_bkram_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component flash
// Verilator lint_off UNUSED
wire wb_flash_cyc, wb_flash_stb, wb_flash_we;
wire [27:0] wb_flash_addr;
wire [31:0] wb_flash_data;
wire [3:0] wb_flash_sel;
wire wb_flash_stall, wb_flash_ack, wb_flash_err;
wire [31:0] wb_flash_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb, component xpand
// Verilator lint_off UNUSED
wire wb_xpand_cyc, wb_xpand_stb, wb_xpand_we;
wire [27:0] wb_xpand_addr;
wire [31:0] wb_xpand_data;
wire [3:0] wb_xpand_sel;
wire wb_xpand_stall, wb_xpand_ack, wb_xpand_err;
wire [31:0] wb_xpand_idata;
// Verilator lint_on UNUSED
// }}}
// Bus wbu
// {{{
// Wishbone definitions for bus wbu, component wbu
// Verilator lint_off UNUSED
wire wbu_wbu_cyc, wbu_wbu_stb, wbu_wbu_we;
wire [1:0] wbu_wbu_addr;
wire [31:0] wbu_wbu_data;
wire [3:0] wbu_wbu_sel;
wire wbu_wbu_stall, wbu_wbu_ack, wbu_wbu_err;
wire [31:0] wbu_wbu_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbu, component wbu_arbiter
// Verilator lint_off UNUSED
wire wbu_wbu_arbiter_cyc, wbu_wbu_arbiter_stb, wbu_wbu_arbiter_we;
wire [1:0] wbu_wbu_arbiter_addr;
wire [31:0] wbu_wbu_arbiter_data;
wire [3:0] wbu_wbu_arbiter_sel;
wire wbu_wbu_arbiter_stall, wbu_wbu_arbiter_ack, wbu_wbu_arbiter_err;
wire [31:0] wbu_wbu_arbiter_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbu, component zip
// Verilator lint_off UNUSED
wire wbu_zip_cyc, wbu_zip_stb, wbu_zip_we;
wire [1:0] wbu_zip_addr;
wire [31:0] wbu_zip_data;
wire [3:0] wbu_zip_sel;
wire wbu_zip_stall, wbu_zip_ack, wbu_zip_err;
wire [31:0] wbu_zip_idata;
// Verilator lint_on UNUSED
// }}}
// Bus rambus
// {{{
// Wishbone definitions for bus rambus, component hdmiin
// Verilator lint_off UNUSED
wire rambus_hdmiin_cyc, rambus_hdmiin_stb, rambus_hdmiin_we;
wire [24:0] rambus_hdmiin_addr;
wire [127:0] rambus_hdmiin_data;
wire [15:0] rambus_hdmiin_sel;
wire rambus_hdmiin_stall, rambus_hdmiin_ack, rambus_hdmiin_err;
wire [127:0] rambus_hdmiin_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus rambus, component xpand
// Verilator lint_off UNUSED
wire rambus_xpand_cyc, rambus_xpand_stb, rambus_xpand_we;
wire [24:0] rambus_xpand_addr;
wire [127:0] rambus_xpand_data;
wire [15:0] rambus_xpand_sel;
wire rambus_xpand_stall, rambus_xpand_ack, rambus_xpand_err;
wire [127:0] rambus_xpand_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus rambus, component sdram
// Verilator lint_off UNUSED
wire rambus_sdram_cyc, rambus_sdram_stb, rambus_sdram_we;
wire [24:0] rambus_sdram_addr;
wire [127:0] rambus_sdram_data;
wire [15:0] rambus_sdram_sel;
wire rambus_sdram_stall, rambus_sdram_ack, rambus_sdram_err;
wire [127:0] rambus_sdram_idata;
// Verilator lint_on UNUSED
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Peripheral address decoding, bus handling
// {{{
//
// BUS-LOGIC for wb
// {{{
//
// wb Bus logic to handle SINGLE slaves
//
reg r_wb_sio_ack;
reg [31:0] r_wb_sio_data;
assign wb_sio_stall = 1'b0;
initial r_wb_sio_ack = 1'b0;
always @(posedge i_clk)
r_wb_sio_ack <= (wb_sio_stb);
assign wb_sio_ack = r_wb_sio_ack;
always @(posedge i_clk)
casez( wb_sio_addr[3:0] )
4'h0: r_wb_sio_data <= wb_buildtime_idata;
4'h1: r_wb_sio_data <= wb_buserr_idata;
4'h2: r_wb_sio_data <= wb_buspic_idata;
4'h3: r_wb_sio_data <= wb_clkhdmiin_idata;
4'h4: r_wb_sio_data <= wb_clkhdmiout_idata;
4'h5: r_wb_sio_data <= wb_gpio_idata;
4'h6: r_wb_sio_data <= wb_hdmi_scope_frame_offset_idata;
4'h7: r_wb_sio_data <= wb_pwrcount_idata;
4'h8: r_wb_sio_data <= wb_rtcdate_idata;
4'h9: r_wb_sio_data <= wb_spio_idata;
4'ha: r_wb_sio_data <= wb_subseconds_idata;
4'hb: r_wb_sio_data <= wb_sysclk_idata;
4'hc: r_wb_sio_data <= wb_version_idata;
default: r_wb_sio_data <= wb_version_idata;
endcase
assign wb_sio_idata = r_wb_sio_data;
//
// Now to translate this logic to the various SIO slaves
//
// In this case, the SIO bus has the prefix wb_sio
// and all of the slaves have various wires beginning
// with their own respective bus prefixes.
// Our goal here is to make certain that all of
// the slave bus inputs match the SIO bus wires
assign wb_buildtime_cyc = wb_sio_cyc;
assign wb_buildtime_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h0); // 0x0000000
assign wb_buildtime_we = wb_sio_we;
assign wb_buildtime_data= wb_sio_data;
assign wb_buildtime_sel = wb_sio_sel;
assign wb_buserr_cyc = wb_sio_cyc;
assign wb_buserr_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h1); // 0x0000004
assign wb_buserr_we = wb_sio_we;
assign wb_buserr_data= wb_sio_data;
assign wb_buserr_sel = wb_sio_sel;
assign wb_buspic_cyc = wb_sio_cyc;
assign wb_buspic_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h2); // 0x0000008
assign wb_buspic_we = wb_sio_we;
assign wb_buspic_data= wb_sio_data;
assign wb_buspic_sel = wb_sio_sel;
assign wb_clkhdmiin_cyc = wb_sio_cyc;
assign wb_clkhdmiin_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h3); // 0x000000c
assign wb_clkhdmiin_we = wb_sio_we;
assign wb_clkhdmiin_data= wb_sio_data;
assign wb_clkhdmiin_sel = wb_sio_sel;
assign wb_clkhdmiout_cyc = wb_sio_cyc;
assign wb_clkhdmiout_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h4); // 0x0000010
assign wb_clkhdmiout_we = wb_sio_we;
assign wb_clkhdmiout_data= wb_sio_data;
assign wb_clkhdmiout_sel = wb_sio_sel;
assign wb_gpio_cyc = wb_sio_cyc;
assign wb_gpio_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h5); // 0x0000014
assign wb_gpio_we = wb_sio_we;
assign wb_gpio_data= wb_sio_data;
assign wb_gpio_sel = wb_sio_sel;
assign wb_hdmi_scope_frame_offset_cyc = wb_sio_cyc;
assign wb_hdmi_scope_frame_offset_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h6); // 0x0000018
assign wb_hdmi_scope_frame_offset_we = wb_sio_we;
assign wb_hdmi_scope_frame_offset_data= wb_sio_data;
assign wb_hdmi_scope_frame_offset_sel = wb_sio_sel;
assign wb_pwrcount_cyc = wb_sio_cyc;
assign wb_pwrcount_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h7); // 0x000001c
assign wb_pwrcount_we = wb_sio_we;
assign wb_pwrcount_data= wb_sio_data;
assign wb_pwrcount_sel = wb_sio_sel;
assign wb_rtcdate_cyc = wb_sio_cyc;
assign wb_rtcdate_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h8); // 0x0000020
assign wb_rtcdate_we = wb_sio_we;
assign wb_rtcdate_data= wb_sio_data;
assign wb_rtcdate_sel = wb_sio_sel;
assign wb_spio_cyc = wb_sio_cyc;
assign wb_spio_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'h9); // 0x0000024
assign wb_spio_we = wb_sio_we;
assign wb_spio_data= wb_sio_data;
assign wb_spio_sel = wb_sio_sel;
assign wb_subseconds_cyc = wb_sio_cyc;
assign wb_subseconds_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'ha); // 0x0000028
assign wb_subseconds_we = wb_sio_we;
assign wb_subseconds_data= wb_sio_data;
assign wb_subseconds_sel = wb_sio_sel;
assign wb_sysclk_cyc = wb_sio_cyc;
assign wb_sysclk_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'hb); // 0x000002c
assign wb_sysclk_we = wb_sio_we;
assign wb_sysclk_data= wb_sio_data;
assign wb_sysclk_sel = wb_sio_sel;
assign wb_version_cyc = wb_sio_cyc;
assign wb_version_stb = wb_sio_stb && (wb_sio_addr[ 3: 0] == 4'hc); // 0x0000030
assign wb_version_we = wb_sio_we;
assign wb_version_data= wb_sio_data;
assign wb_version_sel = wb_sio_sel;
//
// wb Bus logic to handle 10 DOUBLE slaves
//
//
reg [1:0] r_wb_dio_ack;
// # dlist = 10, nextlg(#dlist) = 4
reg [3:0] r_wb_dio_bus_select;
reg [31:0] r_wb_dio_data;
// DOUBLE peripherals are not allowed to stall.
assign wb_dio_stall = 1'b0;
// DOUBLE peripherals return their acknowledgments in two
// clocks--always, allowing us to collect this logic together
// in a slave independent manner. Here, the acknowledgment
// is treated as a two stage shift register, cleared on any
// reset, or any time the cycle line drops. (Dropping the
// cycle line aborts the transaction.)
initial r_wb_dio_ack = 0;
always @(posedge i_clk)
if (i_reset || !wb_dio_cyc)
r_wb_dio_ack <= 0;
else
r_wb_dio_ack <= { r_wb_dio_ack[0], (wb_dio_stb) };
assign wb_dio_ack = r_wb_dio_ack[1];
// Since it costs us two clocks to go through this
// logic, we'll take one of those clocks here to set
// a selection index, and then on the next clock we'll
// use this index to select from among the vaious
// possible bus return values
always @(posedge i_clk)
casez(wb_dio_addr[7:2])
6'b00_0000: r_wb_dio_bus_select <= 4'd0;
6'b00_0001: r_wb_dio_bus_select <= 4'd1;
6'b00_0010: r_wb_dio_bus_select <= 4'd2;
6'b00_0011: r_wb_dio_bus_select <= 4'd3;
6'b00_010?: r_wb_dio_bus_select <= 4'd4;
6'b00_011?: r_wb_dio_bus_select <= 4'd5;
6'b00_10??: r_wb_dio_bus_select <= 4'd6;
6'b00_11??: r_wb_dio_bus_select <= 4'd7;
6'b01_????: r_wb_dio_bus_select <= 4'd8;
6'b1?_????: r_wb_dio_bus_select <= 4'd9;
default: r_wb_dio_bus_select <= 0;
endcase
always @(posedge i_clk)
casez(r_wb_dio_bus_select)
4'd0: r_wb_dio_data <= wb_gck_idata;
4'd1: r_wb_dio_data <= wb_mous_idata;
4'd2: r_wb_dio_data <= wb_oled_idata;
4'd3: r_wb_dio_data <= wb_rtc_idata;
4'd4: r_wb_dio_data <= wb_gtb_idata;
4'd5: r_wb_dio_data <= wb_netp_idata;
4'd6: r_wb_dio_data <= wb_hdmiin_idata;
4'd7: r_wb_dio_data <= wb_sio_idata;
4'd8: r_wb_dio_data <= wb_edin_idata;
4'd9: r_wb_dio_data <= wb_edout_idata;
default: r_wb_dio_data <= wb_edout_idata;
endcase
assign wb_dio_idata = r_wb_dio_data;
assign wb_gck_cyc = wb_dio_cyc;
assign wb_gck_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3f) == 6'h00); // 0x0000000 - 0x000000f
assign wb_gck_we = wb_dio_we;
assign wb_gck_addr= wb_dio_addr;
assign wb_gck_data= wb_dio_data;
assign wb_gck_sel = wb_dio_sel;
assign wb_mous_cyc = wb_dio_cyc;
assign wb_mous_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3f) == 6'h01); // 0x0000010 - 0x000001f
assign wb_mous_we = wb_dio_we;
assign wb_mous_addr= wb_dio_addr;
assign wb_mous_data= wb_dio_data;
assign wb_mous_sel = wb_dio_sel;
assign wb_oled_cyc = wb_dio_cyc;
assign wb_oled_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3f) == 6'h02); // 0x0000020 - 0x000002f
assign wb_oled_we = wb_dio_we;
assign wb_oled_addr= wb_dio_addr;
assign wb_oled_data= wb_dio_data;
assign wb_oled_sel = wb_dio_sel;
assign wb_rtc_cyc = wb_dio_cyc;
assign wb_rtc_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3f) == 6'h03); // 0x0000030 - 0x000003f
assign wb_rtc_we = wb_dio_we;
assign wb_rtc_addr= wb_dio_addr;
assign wb_rtc_data= wb_dio_data;
assign wb_rtc_sel = wb_dio_sel;
assign wb_gtb_cyc = wb_dio_cyc;
assign wb_gtb_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3e) == 6'h04); // 0x0000040 - 0x000005f
assign wb_gtb_we = wb_dio_we;
assign wb_gtb_addr= wb_dio_addr;
assign wb_gtb_data= wb_dio_data;
assign wb_gtb_sel = wb_dio_sel;
assign wb_netp_cyc = wb_dio_cyc;
assign wb_netp_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3e) == 6'h06); // 0x0000060 - 0x000007f
assign wb_netp_we = wb_dio_we;
assign wb_netp_addr= wb_dio_addr;
assign wb_netp_data= wb_dio_data;
assign wb_netp_sel = wb_dio_sel;
assign wb_hdmiin_cyc = wb_dio_cyc;
assign wb_hdmiin_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3c) == 6'h08); // 0x0000080 - 0x00000bf
assign wb_hdmiin_we = wb_dio_we;
assign wb_hdmiin_addr= wb_dio_addr;
assign wb_hdmiin_data= wb_dio_data;
assign wb_hdmiin_sel = wb_dio_sel;
assign wb_sio_cyc = wb_dio_cyc;
assign wb_sio_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h3c) == 6'h0c); // 0x00000c0 - 0x00000ff
assign wb_sio_we = wb_dio_we;
assign wb_sio_addr= wb_dio_addr;
assign wb_sio_data= wb_dio_data;
assign wb_sio_sel = wb_dio_sel;
assign wb_edin_cyc = wb_dio_cyc;
assign wb_edin_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h30) == 6'h10); // 0x0000100 - 0x00001ff
assign wb_edin_we = wb_dio_we;
assign wb_edin_addr= wb_dio_addr;
assign wb_edin_data= wb_dio_data;
assign wb_edin_sel = wb_dio_sel;
assign wb_edout_cyc = wb_dio_cyc;
assign wb_edout_stb = wb_dio_stb && ((wb_dio_addr[ 7: 2] & 6'h20) == 6'h20); // 0x0000200 - 0x00003ff
assign wb_edout_we = wb_dio_we;
assign wb_edout_addr= wb_dio_addr;
assign wb_edout_data= wb_dio_data;
assign wb_edout_sel = wb_dio_sel;
assign wb_flashcfg_err= 1'b0;
assign wb_pmic_err= 1'b0;
assign wb_scop_edid_err= 1'b0;
assign wb_scopc_err= 1'b0;
assign wb_scope_err= 1'b0;
assign wb_scope_hdmiin_err= 1'b0;
assign wb_gpsu_err= 1'b0;
assign wb_sdcard_err= 1'b0;
assign wb_cfg_err= 1'b0;
assign wb_mdio_err= 1'b0;
assign wb_dio_err= 1'b0;
assign wb_netb_err= 1'b0;
assign wb_bkram_err= 1'b0;
assign wb_flash_err= 1'b0;
// info: @ERROR.WIRE for xpand matches the buses error name, wb_xpand_err
//
// Connect the wb bus components together using the wbxbar()
//
//
wbxbar #(
.NM(2), .NS(15), .AW(28), .DW(32),
.SLAVE_ADDR({
// Address width = 28
// Address LSBs = 2
// Slave name width = 12
{ 28'h8000000 }, // xpand: 0x20000000
{ 28'h7000000 }, // flash: 0x1c000000
{ 28'h6800000 }, // bkram: 0x1a000000
{ 28'h6000000 }, // netb: 0x18000000
{ 28'h5800000 }, // wb_dio: 0x16000000
{ 28'h5000000 }, // mdio: 0x14000000
{ 28'h4800000 }, // cfg: 0x12000000
{ 28'h4000000 }, // sdcard: 0x10000000
{ 28'h3800000 }, // gpsu: 0x0e000000
{ 28'h3000000 }, // scope_hdmiin: 0x0c000000
{ 28'h2800000 }, // scope: 0x0a000000
{ 28'h2000000 }, // scopc: 0x08000000
{ 28'h1800000 }, // scop_edid: 0x06000000
{ 28'h1000000 }, // pmic: 0x04000000
{ 28'h0800000 } // flashcfg: 0x02000000
}),
.SLAVE_MASK({
// Address width = 28
// Address LSBs = 2
// Slave name width = 12
{ 28'h8000000 }, // xpand
{ 28'hf800000 }, // flash
{ 28'hf800000 }, // bkram
{ 28'hf800000 }, // netb
{ 28'hf800000 }, // wb_dio
{ 28'hf800000 }, // mdio
{ 28'hf800000 }, // cfg
{ 28'hf800000 }, // sdcard
{ 28'hf800000 }, // gpsu
{ 28'hf800000 }, // scope_hdmiin
{ 28'hf800000 }, // scope
{ 28'hf800000 }, // scopc
{ 28'hf800000 }, // scop_edid
{ 28'hf800000 }, // pmic
{ 28'hf800000 } // flashcfg
}),
.OPT_DBLBUFFER(1'b1))
wb_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
wb_wbu_arbiter_cyc,
wb_zip_cyc
}),
.i_mstb({
wb_wbu_arbiter_stb,
wb_zip_stb
}),
.i_mwe({
wb_wbu_arbiter_we,
wb_zip_we
}),
.i_maddr({
wb_wbu_arbiter_addr,
wb_zip_addr
}),
.i_mdata({
wb_wbu_arbiter_data,
wb_zip_data
}),
.i_msel({
wb_wbu_arbiter_sel,
wb_zip_sel
}),
.o_mstall({
wb_wbu_arbiter_stall,
wb_zip_stall
}),
.o_mack({
wb_wbu_arbiter_ack,
wb_zip_ack
}),
.o_mdata({
wb_wbu_arbiter_idata,
wb_zip_idata
}),
.o_merr({
wb_wbu_arbiter_err,
wb_zip_err
}),
// Slave connections
.o_scyc({
wb_xpand_cyc,
wb_flash_cyc,
wb_bkram_cyc,
wb_netb_cyc,
wb_dio_cyc,
wb_mdio_cyc,
wb_cfg_cyc,
wb_sdcard_cyc,
wb_gpsu_cyc,
wb_scope_hdmiin_cyc,
wb_scope_cyc,
wb_scopc_cyc,
wb_scop_edid_cyc,
wb_pmic_cyc,
wb_flashcfg_cyc
}),
.o_sstb({
wb_xpand_stb,
wb_flash_stb,
wb_bkram_stb,
wb_netb_stb,
wb_dio_stb,
wb_mdio_stb,
wb_cfg_stb,
wb_sdcard_stb,
wb_gpsu_stb,
wb_scope_hdmiin_stb,
wb_scope_stb,
wb_scopc_stb,
wb_scop_edid_stb,
wb_pmic_stb,
wb_flashcfg_stb
}),
.o_swe({
wb_xpand_we,
wb_flash_we,
wb_bkram_we,
wb_netb_we,
wb_dio_we,
wb_mdio_we,
wb_cfg_we,
wb_sdcard_we,
wb_gpsu_we,
wb_scope_hdmiin_we,
wb_scope_we,
wb_scopc_we,
wb_scop_edid_we,
wb_pmic_we,
wb_flashcfg_we
}),
.o_saddr({
wb_xpand_addr,
wb_flash_addr,
wb_bkram_addr,
wb_netb_addr,
wb_dio_addr,
wb_mdio_addr,
wb_cfg_addr,
wb_sdcard_addr,
wb_gpsu_addr,
wb_scope_hdmiin_addr,
wb_scope_addr,
wb_scopc_addr,
wb_scop_edid_addr,
wb_pmic_addr,
wb_flashcfg_addr
}),
.o_sdata({
wb_xpand_data,
wb_flash_data,
wb_bkram_data,
wb_netb_data,
wb_dio_data,
wb_mdio_data,
wb_cfg_data,
wb_sdcard_data,
wb_gpsu_data,
wb_scope_hdmiin_data,
wb_scope_data,
wb_scopc_data,
wb_scop_edid_data,
wb_pmic_data,
wb_flashcfg_data
}),
.o_ssel({
wb_xpand_sel,
wb_flash_sel,
wb_bkram_sel,
wb_netb_sel,
wb_dio_sel,
wb_mdio_sel,
wb_cfg_sel,
wb_sdcard_sel,
wb_gpsu_sel,
wb_scope_hdmiin_sel,
wb_scope_sel,
wb_scopc_sel,
wb_scop_edid_sel,
wb_pmic_sel,
wb_flashcfg_sel
}),
.i_sstall({
wb_xpand_stall,
wb_flash_stall,
wb_bkram_stall,
wb_netb_stall,
wb_dio_stall,
wb_mdio_stall,
wb_cfg_stall,
wb_sdcard_stall,
wb_gpsu_stall,
wb_scope_hdmiin_stall,
wb_scope_stall,
wb_scopc_stall,
wb_scop_edid_stall,
wb_pmic_stall,
wb_flashcfg_stall
}),
.i_sack({
wb_xpand_ack,
wb_flash_ack,
wb_bkram_ack,
wb_netb_ack,
wb_dio_ack,
wb_mdio_ack,
wb_cfg_ack,
wb_sdcard_ack,
wb_gpsu_ack,
wb_scope_hdmiin_ack,
wb_scope_ack,
wb_scopc_ack,
wb_scop_edid_ack,
wb_pmic_ack,
wb_flashcfg_ack
}),
.i_sdata({
wb_xpand_idata,
wb_flash_idata,
wb_bkram_idata,
wb_netb_idata,
wb_dio_idata,
wb_mdio_idata,
wb_cfg_idata,
wb_sdcard_idata,
wb_gpsu_idata,
wb_scope_hdmiin_idata,
wb_scope_idata,
wb_scopc_idata,
wb_scop_edid_idata,
wb_pmic_idata,
wb_flashcfg_idata
}),
.i_serr({
wb_xpand_err,
wb_flash_err,
wb_bkram_err,
wb_netb_err,
wb_dio_err,
wb_mdio_err,
wb_cfg_err,
wb_sdcard_err,
wb_gpsu_err,
wb_scope_hdmiin_err,
wb_scope_err,
wb_scopc_err,
wb_scop_edid_err,
wb_pmic_err,
wb_flashcfg_err
})
);
// End of bus logic for wb
// }}}
//
// BUS-LOGIC for wbu
// {{{
//
// No class SINGLE peripherals on the "wbu" bus
//
//
// No class DOUBLE peripherals on the "wbu" bus
//
assign wbu_wbu_arbiter_err= 1'b0;
assign wbu_zip_err= 1'b0;
//
// Connect the wbu bus components together using the wbxbar()
//
//
wbxbar #(
.NM(1), .NS(2), .AW(2), .DW(32),
.SLAVE_ADDR({
// Address width = 2
// Address LSBs = 2
// Slave name width = 11
{ 2'h2 }, // zip: 0x8
{ 2'h0 } // wbu_arbiter: 0x0
}),
.SLAVE_MASK({
// Address width = 2
// Address LSBs = 2
// Slave name width = 11
{ 2'h2 }, // zip
{ 2'h2 } // wbu_arbiter
}),
.OPT_DBLBUFFER(1'b1))
wbu_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
wbu_wbu_cyc
}),
.i_mstb({
wbu_wbu_stb
}),
.i_mwe({
wbu_wbu_we
}),
.i_maddr({
wbu_wbu_addr
}),
.i_mdata({
wbu_wbu_data
}),
.i_msel({
wbu_wbu_sel
}),
.o_mstall({
wbu_wbu_stall
}),
.o_mack({
wbu_wbu_ack
}),
.o_mdata({
wbu_wbu_idata
}),
.o_merr({
wbu_wbu_err
}),
// Slave connections
.o_scyc({
wbu_zip_cyc,
wbu_wbu_arbiter_cyc
}),
.o_sstb({
wbu_zip_stb,
wbu_wbu_arbiter_stb
}),
.o_swe({
wbu_zip_we,
wbu_wbu_arbiter_we
}),
.o_saddr({
wbu_zip_addr,
wbu_wbu_arbiter_addr
}),
.o_sdata({
wbu_zip_data,
wbu_wbu_arbiter_data
}),
.o_ssel({
wbu_zip_sel,
wbu_wbu_arbiter_sel
}),
.i_sstall({
wbu_zip_stall,
wbu_wbu_arbiter_stall
}),
.i_sack({
wbu_zip_ack,
wbu_wbu_arbiter_ack
}),
.i_sdata({
wbu_zip_idata,
wbu_wbu_arbiter_idata
}),
.i_serr({
wbu_zip_err,
wbu_wbu_arbiter_err
})
);
// End of bus logic for wbu
// }}}
//
// BUS-LOGIC for rambus
// {{{
//
// No class SINGLE peripherals on the "rambus" bus
//
//
// No class DOUBLE peripherals on the "rambus" bus
//
assign rambus_sdram_err= 1'b0;
//
// Connect the rambus bus components together using the wbxbar()
//
//
wbxbar #(
.NM(2), .NS(1), .AW(25), .DW(128),
.SLAVE_ADDR({
// Address width = 25
// Address LSBs = 4
// Slave name width = 5
{ 25'h0000000 } // sdram: 0x00000000
}),
.SLAVE_MASK({
// Address width = 25
// Address LSBs = 4
// Slave name width = 5
{ 25'h0000000 } // sdram
}),
.OPT_DBLBUFFER(1'b1))
rambus_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
rambus_xpand_cyc,
rambus_hdmiin_cyc
}),
.i_mstb({
rambus_xpand_stb,
rambus_hdmiin_stb
}),
.i_mwe({
rambus_xpand_we,
rambus_hdmiin_we
}),
.i_maddr({
rambus_xpand_addr,
rambus_hdmiin_addr
}),
.i_mdata({
rambus_xpand_data,
rambus_hdmiin_data
}),
.i_msel({
rambus_xpand_sel,
rambus_hdmiin_sel
}),
.o_mstall({
rambus_xpand_stall,
rambus_hdmiin_stall
}),
.o_mack({
rambus_xpand_ack,
rambus_hdmiin_ack
}),
.o_mdata({
rambus_xpand_idata,
rambus_hdmiin_idata
}),
.o_merr({
rambus_xpand_err,
rambus_hdmiin_err
}),
// Slave connections
.o_scyc({
rambus_sdram_cyc
}),
.o_sstb({
rambus_sdram_stb
}),
.o_swe({
rambus_sdram_we
}),
.o_saddr({
rambus_sdram_addr
}),
.o_sdata({
rambus_sdram_data
}),
.o_ssel({
rambus_sdram_sel
}),
.i_sstall({
rambus_sdram_stall
}),
.i_sack({
rambus_sdram_ack
}),
.i_sdata({
rambus_sdram_idata
}),
.i_serr({
rambus_sdram_err
})
);
// End of bus logic for rambus
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declare the interrupt busses
// {{{
// Interrupt busses are defined by anything with a @PIC tag.
// The @PIC.BUS tag defines the name of the wire bus below,
// while the @PIC.MAX tag determines the size of the bus width.
//
// For your peripheral to be assigned to this bus, it must have an
// @INT.NAME.WIRE= tag to define the wire name of the interrupt line,
// and an @INT.NAME.PIC= tag matching the @PIC.BUS tag of the bus
// your interrupt will be assigned to. If an @INT.NAME.ID tag also
// exists, then your interrupt will be assigned to the position given
// by the ID# in that tag.
//
assign sys_int_vector = {
1'b0,
1'b0,
pmic_int,
mous_interrupt,
ck_pps,
sdcard_int,
netrx_int,
nettx_int,
w_bus_int,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0
};
assign alt_int_vector = {
rtc_int,
edid_out_int,
gpsutxf_int,
gpsurxf_int,
gpsutx_int,
gpsurx_int,
gpio_int,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0
};
assign bus_int_vector = {
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
mous_interrupt,
spio_int,
scop_hdmiin_int,
sdcard_int,
scop_edid_int
};
// }}}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
// @MAIN.INSERT and @MAIN.ALT
// {{{
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//
// Now we turn to defining all of the parts and pieces of what
// each of the various peripherals does, and what logic it needs.
//
// This information comes from the @MAIN.INSERT and @MAIN.ALT tags.
// If an @ACCESS tag is available, an ifdef is created to handle
// having the access and not. If the @ACCESS tag is `defined above
// then the @MAIN.INSERT code is executed. If not, the @MAIN.ALT
// code is exeucted, together with any other cleanup settings that
// might need to take place--such as returning zeros to the bus,
// or making sure all of the various interrupt wires are set to
// zero if the component is not included.
//
`ifdef INCLUDE_ZIPCPU
// {{{
//
//
// The ZipCPU/ZipSystem BUS master
//
//
assign zip_int_vector = { alt_int_vector[14:8], sys_int_vector[14:6] };
zipsystem #(.RESET_ADDRESS(RESET_ADDRESS),
.ADDRESS_WIDTH(ZIP_ADDRESS_WIDTH),
.LGICACHE(12),.LGDCACHE(12),
.START_HALTED(ZIP_START_HALTED),
`ifdef VERILATOR
.RESET_DURATION(20),
`else
.RESET_DURATION(20_000),
`endif
.EXTERNAL_INTERRUPTS(ZIP_INTS))
swic(i_clk, (i_reset)||(i_cpu_reset),
// Zippys wishbone interface
wb_zip_cyc, wb_zip_stb, wb_zip_we,
wb_zip_addr[28-1:0],
wb_zip_data, // 32 bits wide
wb_zip_sel, // 32/8 bits wide
wb_zip_stall, wb_zip_ack, wb_zip_idata,wb_zip_err,
zip_int_vector, zip_cpu_int,
// Debug wishbone interface
wbu_zip_cyc, wbu_zip_stb, wbu_zip_we,
wbu_zip_addr[1-1:0],
wbu_zip_data, // 32 bits wide
wbu_zip_sel, // 32/8 bits wide
wbu_zip_stall, wbu_zip_ack, wbu_zip_idata,
zip_debug);
assign zip_trigger = zip_debug[31];
// }}}
`else // INCLUDE_ZIPCPU
// {{{
// Null bus master
// {{{
// }}}
// Null bus slave
// {{{
//
// In the case that there is no wbu_zip peripheral
// responding on the wbu bus
assign wbu_zip_ack = 1'b0;
assign wbu_zip_err = (wbu_zip_stb);
assign wbu_zip_stall = 0;
assign wbu_zip_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign zip_cpu_int = 1'b0; // zip.INT.ZIP.WIRE
// }}}
// }}}
`endif // INCLUDE_ZIPCPU
assign edid_scope_trigger = edido_dbg[31];
assign edid_scope_data = edido_dbg[30:0];
wbscopc #(.LGMEM(5'hb), .MAX_STEP(31'h10000)) theicscop(i_clk, 1'b1,
edid_scope_trigger, edid_scope_data,
i_clk, wb_scop_edid_cyc, wb_scop_edid_stb, wb_scop_edid_we,
wb_scop_edid_addr[1-1:0],
wb_scop_edid_data, // 32 bits wide
wb_scop_edid_sel, // 32/8 bits wide
wb_scop_edid_stall, wb_scop_edid_ack, wb_scop_edid_idata,
scop_edid_int);
`ifdef GPIO_ACCESS
// {{{
//
// GPIO
//
// This interface should allow us to control up to 16 GPIO inputs, and
// another 16 GPIO outputs. The interrupt trips when any of the inputs
// changes. (Sorry, which input isn't (yet) selectable.)
//
localparam INITIAL_GPIO = 16'h04f;
wbgpio #(NGPI, NGPO, INITIAL_GPIO)
gpioi(i_clk, wb_gpio_cyc, wb_gpio_stb, wb_gpio_we,
wb_gpio_data, // 32 bits wide
wb_gpio_sel, // 32/8 bits wide
wb_gpio_stall, wb_gpio_ack, wb_gpio_idata,
i_gpio, o_gpio, gpio_int);
assign sd_reset = o_gpio[6];
// }}}
`else // GPIO_ACCESS
// {{{
// Null interrupt definitions
// {{{
assign gpio_int = 1'b0; // gpio.INT.GPIO.WIRE
// }}}
// }}}
`endif // GPIO_ACCESS
`ifdef FLASHCFG_ACCESS
// {{{
// The Flash control interface is defined by the flash instantiation
// hence we don't need to do anything to define it here.
// }}}
`else // FLASHCFG_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb_flashcfg peripheral
// responding on the wb bus
assign wb_flashcfg_ack = 1'b0;
assign wb_flashcfg_err = (wb_flashcfg_stb);
assign wb_flashcfg_stall = 0;
assign wb_flashcfg_idata = 0;
// }}}
// }}}
`endif // FLASHCFG_ACCESS
`ifdef GPSTRK_ACCESS
assign wb_subseconds_idata = gps_now[31:0];
`else
always @(posedge i_clk)
if (wb_subseconds_stb && wb_subseconds_we)
r_subseconds_data <= wb_data;
else
r_subseconds_data <= r_subseconds_data
+ { 16'h0, RTLCLKSTEP[31:16] };
assign wb_subseconds_idata = r_subseconds_data;
`endif
`ifdef FLASH_ACCESS
// {{{
qflexpress #(.LGFLASHSZ(24), .OPT_CLKDIV(1),
.NDUMMY(6), .RDDELAY(1),
.OPT_STARTUP_FILE("spansion.hex"),
`ifdef FLASHCFG_ACCESS
.OPT_CFG(1'b1)
`else
.OPT_CFG(1'b0)
`endif
)
flashi(i_clk, i_reset,
// Primary memory reading inputs
wb_flash_cyc, wb_flash_stb, wb_flash_we,
wb_flash_addr[22-1:0],
wb_flash_data, // 32 bits wide
wb_flash_sel, // 32/8 bits wide
wb_flash_stall, wb_flash_ack, wb_flash_idata,
// Configuration bus ports
wb_flashcfg_cyc, wb_flashcfg_stb, wb_flashcfg_we,
wb_flashcfg_data, // 32 bits wide
wb_flashcfg_sel, // 32/8 bits wide
wb_flashcfg_stall, wb_flashcfg_ack, wb_flashcfg_idata,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_dbg_trigger, flash_debug);
// }}}
`else // FLASH_ACCESS
// {{{
assign o_qspi_sck = 1'b1;
assign o_qspi_cs_n = 1'b1;
assign o_qspi_mod = 2'b01;
assign o_qspi_dat = 4'b1111;
// Null bus slave
// {{{
//
// In the case that there is no wb_flash peripheral
// responding on the wb bus
assign wb_flash_ack = 1'b0;
assign wb_flash_err = (wb_flash_stb);
assign wb_flash_stall = 0;
assign wb_flash_idata = 0;
// }}}
// }}}
`endif // FLASH_ACCESS
clkcounter clkclkhdmioutctr(i_clk, ck_pps, i_clk_200mhz, wb_clkhdmiout_idata);
initial r_clkhdmiout_ack = 0;
always @(posedge i_clk)
r_clkhdmiout_ack <= (wb_clkhdmiout_stb);
assign wb_clkhdmiout_ack = r_clkhdmiout_ack;
assign wb_clkhdmiout_stall = 1'b0;
`ifdef GPSUART_ACCESS
// {{{
wbuart #(.INITIAL_SETUP(31'h000028b0))
gpsu_uart(i_clk, 1'b0,
wb_gpsu_cyc, wb_gpsu_stb, wb_gpsu_we,
wb_gpsu_addr[2-1:0],
wb_gpsu_data, // 32 bits wide
wb_gpsu_sel, // 32/8 bits wide
wb_gpsu_stall, wb_gpsu_ack, wb_gpsu_idata,
i_gpsu_rx, o_gpsu_tx, w_gpsu_cts_n, w_gpsu_rts_n,
gpsurx_int, gpsutx_int,
gpsurxf_int, gpsutxf_int);
// }}}
`else // GPSUART_ACCESS
// {{{
assign o_gpsu_tx = 1'b1;
assign w_gpsu_rts_n = 1'b0;
// Null bus slave
// {{{
//
// In the case that there is no wb_gpsu peripheral
// responding on the wb bus
assign wb_gpsu_ack = 1'b0;
assign wb_gpsu_err = (wb_gpsu_stb);
assign wb_gpsu_stall = 0;
assign wb_gpsu_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign gpsurxf_int = 1'b0; // gpsu.INT.GPSRXF.WIRE
assign gpsutxf_int = 1'b0; // gpsu.INT.GPSTXF.WIRE
assign gpsutx_int = 1'b0; // gpsu.INT.GPSTX.WIRE
assign gpsurx_int = 1'b0; // gpsu.INT.GPSRX.WIRE
// }}}
// }}}
`endif // GPSUART_ACCESS
`ifdef BKRAM_ACCESS
// {{{
memdev #(.LGMEMSZ(20), .EXTRACLOCK(1))
bkrami(i_clk, i_reset,
wb_bkram_cyc, wb_bkram_stb, wb_bkram_we,
wb_bkram_addr[18-1:0],
wb_bkram_data, // 32 bits wide
wb_bkram_sel, // 32/8 bits wide
wb_bkram_stall, wb_bkram_ack, wb_bkram_idata);
// }}}
`else // BKRAM_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb_bkram peripheral
// responding on the wb bus
assign wb_bkram_ack = 1'b0;
assign wb_bkram_err = (wb_bkram_stb);
assign wb_bkram_stall = 0;
assign wb_bkram_idata = 0;
// }}}
// }}}
`endif // BKRAM_ACCESS
always @(posedge i_clk)
if (wb_zip_err)
begin
r_buserr_addr <= 0;
r_buserr_addr[28-1:0] <= wb_zip_addr[28-1:0];
end else if (wbu_wbu_err)
begin
r_buserr_addr <= 0;
r_buserr_addr[2-1:0] <= wbu_wbu_addr[2-1:0];
end
assign wb_buserr_stall= 1'b0;
assign wb_buserr_ack = wb_buserr_stb;
assign wb_buserr_idata = { {(30-28){1'b0}},
r_buserr_addr, 2'b00 };
`ifdef ETHERNET_ACCESS
// {{{
enetpackets #(.MEMORY_ADDRESS_WIDTH(14))
netctrl(i_clk, i_reset,
wb_netb_cyc, wb_netb_stb, wb_netb_we,
wb_netb_addr[13-1:0],
wb_netb_data, // 32 bits wide
wb_netb_sel, // 32/8 bits wide
wb_netb_stall, wb_netb_ack, wb_netb_idata,
wb_netp_cyc, wb_netp_stb, wb_netp_we,
wb_netp_addr[3-1:0],
wb_netp_data, // 32 bits wide
wb_netp_sel, // 32/8 bits wide
wb_netp_stall, wb_netp_ack, wb_netp_idata,
o_net_reset_n,
i_net_rx_clk, i_net_rx_dv, i_net_rx_err, i_net_rxd,
i_clk_125mhz, o_net_tx_clk, o_net_tx_ctl, o_net_txd,
netrx_int, nettx_int, netp_debug_clk, netp_debug);
// }}}
`else // ETHERNET_ACCESS
// {{{
// Null interrupt definitions
// {{{
assign nettx_int = 1'b0; // netp.INT.NETTX.WIRE
assign netrx_int = 1'b0; // netp.INT.NETRX.WIRE
// }}}
// }}}
`endif // ETHERNET_ACCESS
`ifdef BUSPIC_ACCESS
// {{{
//
// The BUS Interrupt controller
//
icontrol #(15) buspici(i_clk, 1'b0,
wb_buspic_cyc, wb_buspic_stb, wb_buspic_we,
wb_buspic_data, // 32 bits wide
wb_buspic_sel, // 32/8 bits wide
wb_buspic_stall, wb_buspic_ack, wb_buspic_idata,
bus_int_vector, w_bus_int);
// }}}
`else // BUSPIC_ACCESS
// {{{
// Null interrupt definitions
// {{{
assign w_bus_int = 1'b0; // buspic.INT.BUS.WIRE
// }}}
// }}}
`endif // BUSPIC_ACCESS
`ifndef ETHERNET_ACCESS
// Ethernet packet memory declaration
//
// The only time this needs to be defined is when the ethernet module
// itself isnt defined. Otherwise, the access is accomplished by the
// ethernet module
memdev #(14)
enet_buffers(i_clk,
wb_netb_cyc, wb_netb_stb, wb_netb_we,
wb_netb_addr[13-1:0],
wb_netb_data, // 32 bits wide
wb_netb_sel, // 32/8 bits wide
wb_netb_stall, wb_netb_ack, wb_netb_idata);
`else
// These don't need to be defined here, and indeed should not be defined here
// lest their definitions override those of the netb interface defined in the
// enetpackets module
//
// assign wb_netb_ack = 1'b0;
// assign wb_netb_stall = 1'b0;
// assign wb_netb_data = wb_netp_data;
`endif
clkcounter clksysclkctr(i_clk, ck_pps, i_clk, wb_sysclk_idata);
initial r_sysclk_ack = 0;
always @(posedge i_clk)
r_sysclk_ack <= (wb_sysclk_stb);
assign wb_sysclk_ack = r_sysclk_ack;
assign wb_sysclk_stall = 1'b0;
assign wb_version_idata = `DATESTAMP;
assign wb_version_ack = wb_version_stb;
assign wb_version_stall = 1'b0;
clkcounter clkclkhdmiinctr(i_clk, ck_pps, i_hdmi_in_clk, wb_clkhdmiin_idata);
initial r_clkhdmiin_ack = 0;
always @(posedge i_clk)
r_clkhdmiin_ack <= (wb_clkhdmiin_stb);
assign wb_clkhdmiin_ack = r_clkhdmiin_ack;
assign wb_clkhdmiin_stall = 1'b0;
assign o_hdmi_out_r = hdmi_in_r;
assign o_hdmi_out_g = hdmi_in_g;
assign o_hdmi_out_b = hdmi_in_b;
`ifdef GPSTRK_ACCESS
gpsclock_tb #(.CLOCK_FREQUENCY_HZ(100000000))
ppstb(i_clk, ck_pps, tb_pps,
wb_gtb_cyc, wb_gtb_stb, wb_gtb_we,
wb_gtb_addr[3-1:0],
wb_gtb_data, // 32 bits wide
wb_gtb_sel, // 32/8 bits wide
wb_gtb_stall, wb_gtb_ack, wb_gtb_idata,
gps_err, gps_now, gps_step);
`ifdef GPSTB
assign gps_pps = tb_pps;
`else
assign gps_pps = i_gps_pps;
`endif
`endif
`ifdef SDSPI_ACCESS
// {{{
// SPI mapping
wire w_sd_cs_n, w_sd_mosi, w_sd_miso;
sdspi sdcardi(i_clk, sd_reset,
wb_sdcard_cyc, wb_sdcard_stb, wb_sdcard_we,
wb_sdcard_addr[2-1:0],
wb_sdcard_data, // 32 bits wide
wb_sdcard_sel, // 32/8 bits wide
wb_sdcard_stall, wb_sdcard_ack, wb_sdcard_idata,
w_sd_cs_n, o_sd_sck, w_sd_mosi, w_sd_miso, i_sd_detect,
sdcard_int, 1'b1, sdspi_debug);
assign w_sd_miso = i_sd_data[0];
assign o_sd_data = { w_sd_cs_n, 3'b111 };
assign o_sd_cmd = w_sd_mosi;
// }}}
`else // SDSPI_ACCESS
// {{{
assign o_sd_sck = 1'b1;
assign o_sd_cmd = 1'b1;
assign o_sd_data = 4'hf;
// Null bus slave
// {{{
//
// In the case that there is no wb_sdcard peripheral
// responding on the wb bus
assign wb_sdcard_ack = 1'b0;
assign wb_sdcard_err = (wb_sdcard_stb);
assign wb_sdcard_stall = 0;
assign wb_sdcard_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign sdcard_int = 1'b0; // sdcard.INT.SDCARD.WIRE
// }}}
// }}}
`endif // SDSPI_ACCESS
`ifdef HDMIIN_ACCESS
// {{{
// HDMI input processor
hdmiin thehdmiin(i_clk, i_hdmi_in_clk, ck_pps,
//
i_hdmi_in_actual_delay_r,
i_hdmi_in_actual_delay_g,
i_hdmi_in_actual_delay_b,
o_hdmi_in_delay,
//
i_hdmi_in_r, i_hdmi_in_g, i_hdmi_in_b,
wb_cyc, (wb_stb)&&(hdmiin_sel), wb_we, wb_addr[3:0],
wb_data, wb_sel,
hdmiin_stall, hdmiin_ack, hdmiin_data,
rambus_cyc, rambus_stb, rambus_we,
rambus_addr, rambus_data, rambus_sel,
rambus_stall, rambus_ack, rambus_err,
hdmiin_int,
hin_pixels, hin_dbg_scope);
assign hdmi_in_r = hin_pixels[29:20];
assign hdmi_in_g = hin_pixels[19:10];
assign hdmi_in_b = hin_pixels[ 9: 0];
// }}}
`else // HDMIIN_ACCESS
// {{{
// Null bus master
// {{{
// }}}
// Null interrupt definitions
// {{{
assign hdmiin_int = 1'b0; // hdmiin.INT.VSYNC.WIRE
// }}}
// }}}
`endif // HDMIIN_ACCESS
`ifdef GPSTRK_ACCESS
// {{{
// Verilator lint_off UNUSED
wire [1:0] ck_dbg;
// Verilator lint_on UNUSED
gpsclock #(.DEFAULT_STEP(GPSCLOCK_DEFAULT_STEP))
ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
wb_gck_cyc, wb_gck_stb, wb_gck_we,
wb_gck_addr[2-1:0],
wb_gck_data, // 32 bits wide
wb_gck_sel, // 32/8 bits wide
wb_gck_stall, wb_gck_ack, wb_gck_idata,
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
ck_dbg);
// }}}
`else // GPSTRK_ACCESS
// {{{
wire [31:0] pre_step;
assign pre_step = { 16'h00, (({GPSCLOCK_DEFAULT_STEP[27:0],20'h00})
>>GPSCLOCK_DEFAULT_STEP[31:28]) };
always @(posedge i_clk)
{ ck_pps, gps_step[31:0] } <= gps_step + pre_step;
assign gck_stall = 1'b0;
assign gps_now = 64'h0;
assign gps_err = 64'h0;
assign gps_step = 64'h0;
assign gps_led = 1'b0;
assign gps_locked = 1'b0;
// Null interrupt definitions
// {{{
assign ck_pps = 1'b0; // gck.INT.PPS.WIRE
// }}}
// }}}
`endif // GPSTRK_ACCESS
assign wb_buildtime_idata = `BUILDTIME;
assign wb_buildtime_ack = wb_buildtime_stb;
assign wb_buildtime_stall = 1'b0;
`ifdef NETCTRL_ACCESS
// {{{
// Verilator lint_off UNUSED
wire[31:0] mdio_debug;
// Verilator lint_on UNUSED
enetctrl #(2)
mdio(i_clk, i_reset, wb_mdio_cyc, wb_mdio_stb, wb_mdio_we,
wb_mdio_addr[5-1:0],
wb_mdio_data, // 32 bits wide
wb_mdio_sel, // 32/8 bits wide
wb_mdio_stall, wb_mdio_ack, wb_mdio_idata,
o_mdclk, o_mdio, i_mdio, o_mdwe, mdio_debug);
// }}}
`else // NETCTRL_ACCESS
// {{{
assign o_mdclk = 1'b1;
assign o_mdio = 1'b1;
assign o_mdwe = 1'b0;
// Null bus slave
// {{{
//
// In the case that there is no wb_mdio peripheral
// responding on the wb bus
assign wb_mdio_ack = 1'b0;
assign wb_mdio_err = (wb_mdio_stb);
assign wb_mdio_stall = 0;
assign wb_mdio_idata = 0;
// }}}
// }}}
`endif // NETCTRL_ACCESS
`ifdef CFG_ACCESS
// {{{
`ifdef VERILATOR
reg r_cfg_ack;
initial r_cfg_ack = 1'b0;
always @(posedge i_clk)
r_cfg_ack <= wb_cfg_stb;
assign wb_cfg_ack = r_cfg_ack;
assign wb_cfg_stall = 1'b0;
assign wb_cfg_idata = 32'h00;
`else
wbicapetwo #(ICAPE_LGDIV)
cfgport(i_clk, wb_cfg_cyc, wb_cfg_stb, wb_cfg_we,
wb_cfg_addr[5-1:0],
wb_cfg_data, // 32 bits wide
wb_cfg_sel, // 32/8 bits wide
wb_cfg_stall, wb_cfg_ack, wb_cfg_idata);
`endif
// }}}
`else // CFG_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb_cfg peripheral
// responding on the wb bus
assign wb_cfg_ack = 1'b0;
assign wb_cfg_err = (wb_cfg_stb);
assign wb_cfg_stall = 0;
assign wb_cfg_idata = 0;
// }}}
// }}}
`endif // CFG_ACCESS
`ifdef PWRCOUNT_ACCESS
// {{{
initial r_pwrcount_data = 32'h0;
always @(posedge i_clk)
if (r_pwrcount_data[31])
r_pwrcount_data[30:0] <= r_pwrcount_data[30:0] + 1'b1;
else
r_pwrcount_data[31:0] <= r_pwrcount_data[31:0] + 1'b1;
assign wb_pwrcount_stall = 1'b0;
assign wb_pwrcount_ack = wb_pwrcount_stb;
assign wb_pwrcount_idata = r_pwrcount_data;
// }}}
`else // PWRCOUNT_ACCESS
// {{{
// }}}
`endif // PWRCOUNT_ACCESS
`ifdef RTCDATE_ACCESS
// {{{
//
// The Calendar DATE
//
rtcdate rtcdatei(i_clk, rtc_ppd,
wb_rtcdate_cyc, wb_rtcdate_stb, wb_rtcdate_we,
wb_rtcdate_data, // 32 bits wide
wb_rtcdate_sel, // 32/8 bits wide
wb_rtcdate_stall, wb_rtcdate_ack, wb_rtcdate_idata);
// }}}
`else // RTCDATE_ACCESS
// {{{
// }}}
`endif // RTCDATE_ACCESS
reg scope_hdmiin_trigger, scope_hdmiin_tmp, scope_hdmiin_pre_trigger,
scope_hdmiin_count_triggered;
wire scope_hdmiin_clear_stb;
reg [31:0] scope_hdmiin_counter, scope_hdmiin_trigger_foo;
initial scope_hdmiin_pre_trigger = 1'b1;
always @(posedge i_hdmi_in_clk)
if (scope_hdmiin_trigger_foo == 0)
begin
scope_hdmiin_trigger_foo <= 32'd2475000-1'b1;
scope_hdmiin_pre_trigger <= 1'b1;
end else begin
scope_hdmiin_trigger_foo <= scope_hdmiin_trigger_foo-1'b1;
scope_hdmiin_pre_trigger <= 1'b0;
end
transferstb scope_hdmiin_clearctri(i_clk, i_hdmi_in_clk,
((wb_stb)&&(scope_hdmiin_sel)&&(wb_we)&&(!wb_addr[0])),
scope_hdmiin_clear_stb);
initial scope_hdmiin_count_triggered = 1'b0;
always @(posedge i_hdmi_in_clk)
if (scope_hdmiin_clear_stb)
scope_hdmiin_count_triggered <= 1'b0;
else if (scope_hdmiin_pre_trigger)
scope_hdmiin_count_triggered <= 1'b1;
initial scope_hdmiin_counter = 32'hffff_ffff;
always @(posedge i_hdmi_in_clk)
if (!scope_hdmiin_count_triggered)
scope_hdmiin_counter <= hdmi_scope_frame_offset_data;
else if (scope_hdmiin_counter != 0)
scope_hdmiin_counter <= scope_hdmiin_counter - 1'b1;
initial scope_hdmiin_trigger = 1'b0;
always @(posedge i_hdmi_in_clk)
scope_hdmiin_trigger <= (scope_hdmiin_counter == 0);
wbscope #(.LGMEM(5'd14), .SYNCHRONOUS(0)
) copyhdmiin(i_hdmi_in_clk, 1'b1,
scope_hdmiin_trigger, hin_dbg_scope,
i_clk, wb_cyc, (wb_stb)&&(scope_hdmiin_sel), wb_we, wb_addr[0],
{ wb_data[31:20], 20'h0 },
scope_hdmiin_stall, scope_hdmiin_ack,
scope_hdmiin_data,
scop_hdmiin_int);
`ifdef HDMI_OUT_EDID_ACCESS
// {{{
wbi2cmaster #(.READ_ONLY(1'b1),.MEM_ADDR_BITS(8)) the_edout(i_clk,
wb_edout_cyc, wb_edout_stb, wb_edout_we,
wb_edout_addr[7-1:0],
wb_edout_data, // 32 bits wide
wb_edout_sel, // 32/8 bits wide
wb_edout_stall, wb_edout_ack, wb_edout_idata,
i_hdmi_out_scl, i_hdmi_out_sda, o_hdmi_out_scl, o_hdmi_out_sda,
edid_out_int,
edido_dbg);
// }}}
`else // HDMI_OUT_EDID_ACCESS
// {{{
assign o_hdmi_out_scl = 1'b1;
assign o_hdmi_out_sda = 1'b1;
// Null interrupt definitions
// {{{
assign edid_out_int = 1'b0; // edout.INT.EDID.WIRE
// }}}
// }}}
`endif // HDMI_OUT_EDID_ACCESS
`ifdef RTC_ACCESS
// {{{
`ifdef GPSTRK_ACCESS
rtcgps #(RTC_CLKSTEP) thertc(i_clk, i_reset,
wb_rtc_cyc, wb_rtc_stb, wb_rtc_we,
wb_rtc_addr[2-1:0],
wb_rtc_data, // 32 bits wide
wb_rtc_sel, // 32/8 bits wide
wb_rtc_stall, wb_rtc_ack, wb_rtc_idata,
rtc_int, rtc_ppd,
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
`else
rtclight #(32'h2af31d) thertc(i_clk, i_reset,
wb_cyc, (wb_stb)&&(rtc_sel), wb_we, { 1'b0, wb_addr[1:0] },
wb_data, wb_sel,
rtc_stall, rtc_ack, rtc_data,
rtc_int, rtc_ppd);
`endif
// }}}
`else // RTC_ACCESS
// {{{
`ifdef GPSTRK_ACCESS
assign rtc_pps = 1'b0;
`endif
assign rtc_ppd = 1'b0;
// Null interrupt definitions
// {{{
assign rtc_int = 1'b0; // rtc.INT.RTC.WIRE
// }}}
// }}}
`endif // RTC_ACCESS
`ifdef SDRAM_ACCESS
// {{{
assign o_sdram_cyc = rambus_sdram_cyc;
assign o_sdram_stb =(rambus_sdram_stb);
assign o_sdram_we = rambus_sdram_we;
assign o_sdram_addr = rambus_sdram_addr[25-1:0];
assign o_sdram_data = rambus_sdram_data;
assign o_sdram_sel = rambus_sdram_sel;
assign rambus_sdram_ack = i_sdram_ack;
assign rambus_sdram_stall = i_sdram_stall;
assign rambus_sdram_idata = i_sdram_data;
// }}}
`else // SDRAM_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no rambus_sdram peripheral
// responding on the rambus bus
assign rambus_sdram_ack = 1'b0;
assign rambus_sdram_err = (rambus_sdram_stb);
assign rambus_sdram_stall = 0;
assign rambus_sdram_idata = 0;
// }}}
// }}}
`endif // SDRAM_ACCESS
`ifdef SPIO_ACCESS
// {{{
//
// Special purpose I/O driver (buttons, LEDs, and switches)
//
assign w_btn = { i_btnc, i_btnd, i_btnl, i_btnr, i_btnu };
spio #(.NBTN(5), .NLEDS(8), .NSW(8)) spioi(i_clk,
wb_spio_cyc, wb_spio_stb, wb_spio_we,
wb_spio_data, // 32 bits wide
wb_spio_sel, // 32/8 bits wide
wb_spio_stall, wb_spio_ack, wb_spio_idata,
i_sw, w_btn, w_led, spio_int);
assign o_led = w_led;
// }}}
`else // SPIO_ACCESS
// {{{
assign w_btn = 0;
assign o_led = 0;
// Null interrupt definitions
// {{{
assign spio_int = 1'b0; // spio.INT.SPIO.WIRE
// }}}
// }}}
`endif // SPIO_ACCESS
`ifdef MOUSE_ACCESS
// {{{
wbmouse themouse(i_clk,
wb_mous_cyc, wb_mous_stb, wb_mous_we,
wb_mous_addr[2-1:0],
wb_mous_data, // 32 bits wide
wb_mous_sel, // 32/8 bits wide
wb_mous_stall, wb_mous_ack, wb_mous_idata,
i_ps2, o_ps2,
scrn_mouse, mous_interrupt);
// }}}
`else // MOUSE_ACCESS
// {{{
// If there is no mouse, declare mouse types of things to be .. absent
assign scrn_mouse = 32'h00;
assign o_ps2 = 2'b11;
// Null interrupt definitions
// {{{
assign mous_interrupt = 1'b0; // mous.INT.MOUSE.WIRE
// }}}
// }}}
`endif // MOUSE_ACCESS
`ifdef OLEDBW_ACCESS
// {{{
wboledbw #(.CBITS(4)) oledctrl(i_clk,
wb_oled_cyc, wb_oled_stb, wb_oled_we,
wb_oled_addr[2-1:0],
wb_oled_data, // 32 bits wide
wb_oled_sel, // 32/8 bits wide
wb_oled_stall, wb_oled_ack, wb_oled_idata,
o_oled_sck, o_oled_mosi, o_oled_dcn,
{ o_oled_reset_n, o_oled_panel_en, o_oled_logic_en },
oled_int);
// }}}
`else // OLEDBW_ACCESS
// {{{
assign o_oled_sck = 1'b1;
assign o_oled_mosi = 1'b1;
assign o_oled_dcn = 1'b1;
assign o_oled_reset_n = 1'b0;
assign o_oled_panel_en= 1'b0;
assign o_oled_logic_en= 1'b0;
// Null interrupt definitions
// {{{
assign oled_int = 1'b0; // oled.INT.OLED.WIRE
// }}}
// }}}
`endif // OLEDBW_ACCESS
`ifdef MICROPHONE_ACCESS
// {{{
wbmic #(.DEFAULT_RELOAD(@$.CLKSPERSAMPLE))
microphone(i_clk, 1'b0,
wb_pmic_cyc, wb_pmic_stb, wb_pmic_we,
wb_pmic_addr[1-1:0],
wb_pmic_data, // 32 bits wide
wb_pmic_sel, // 32/8 bits wide
wb_pmic_stall, wb_pmic_ack, wb_pmic_idata,
o_mic_csn, o_mic_sck, i_mic_din, pmic_int);
// }}}
`else // MICROPHONE_ACCESS
// {{{
assign o_mic_csn = 1'b1;
assign o_mic_sck = 1'b1;
// Null bus slave
// {{{
//
// In the case that there is no wb_pmic peripheral
// responding on the wb bus
assign wb_pmic_ack = 1'b0;
assign wb_pmic_err = (wb_pmic_stb);
assign wb_pmic_stall = 0;
assign wb_pmic_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign pmic_int = 1'b0; // pmic.INT.MIC.WIRE
// }}}
// }}}
`endif // MICROPHONE_ACCESS
`ifdef SCOPC_SCOPC
// {{{
wbscopc #(.LGMEM(12),
.SYNCHRONOUS(1))
scopci(i_clk, 1'b1, @$(TRIGGER), @$(DEBUG),
i_clk, wb_scopc_cyc, wb_scopc_stb, wb_scopc_we,
wb_scopc_addr[1-1:0],
wb_scopc_data, // 32 bits wide
wb_scopc_sel, // 32/8 bits wide
wb_scopc_stall, wb_scopc_ack, wb_scopc_idata,
scopc_int);
// }}}
`else // SCOPC_SCOPC
// {{{
assign scopc_int = 0;
// Null bus slave
// {{{
//
// In the case that there is no wb_scopc peripheral
// responding on the wb bus
assign wb_scopc_ack = 1'b0;
assign wb_scopc_err = (wb_scopc_stb);
assign wb_scopc_stall = 0;
assign wb_scopc_idata = 0;
// }}}
// }}}
`endif // SCOPC_SCOPC
`ifdef SCOPE_SCOPE
// {{{
wbscope #(.LGMEM(12),
.SYNCHRONOUS(1))
scopei(i_clk, 1'b1, @$(TRIGGER), @$(DEBUG),
i_clk, wb_scope_cyc, wb_scope_stb, wb_scope_we,
wb_scope_addr[1-1:0],
wb_scope_data, // 32 bits wide
wb_scope_sel, // 32/8 bits wide
wb_scope_stall, wb_scope_ack, wb_scope_idata,
scope_int);
// }}}
`else // SCOPE_SCOPE
// {{{
assign scope_int = 0;
// Null bus slave
// {{{
//
// In the case that there is no wb_scope peripheral
// responding on the wb bus
assign wb_scope_ack = 1'b0;
assign wb_scope_err = (wb_scope_stb);
assign wb_scope_stall = 0;
assign wb_scope_idata = 0;
// }}}
// }}}
`endif // SCOPE_SCOPE
`ifdef WBUBUS_MASTER
// {{{
// The Host USB interface, to be used by the WB-UART bus
rxuartlite #(BUSUART) rcv(s_clk, i_host_uart_rx,
rx_host_stb, rx_host_data);
txuartlite #(BUSUART) txv(s_clk, tx_host_stb, tx_host_data,
o_host_uart_tx, tx_host_busy);
`ifdef INCLUDE_ZIPCPU
// assign wbu_zip_sel = wbu_addr[1];
`else
assign wbu_zip_sel = 1'b0;
assign zip_dbg_ack = 1'b0;
assign zip_dbg_stall = 1'b0;
assign zip_dbg_data = 0;
`endif
`ifndef BUSPIC_ACCESS
wire w_bus_int;
assign w_bus_int = 1'b0;
`endif
wire [31:0] wbu_tmp_addr;
wbubus genbus(i_clk, i_host_rx_stb, i_host_rx_data,
wbu_wbu_cyc, wbu_wbu_stb, wbu_wbu_we, wbu_tmp_addr, wbu_wbu_data,
wbu_wbu_stall, wbu_wbu_ack, wbu_wbu_idata, wbu_wbu_err,
w_bus_int,
o_host_tx_stb, o_host_tx_data, i_host_tx_busy,
wbubus_dbg[0]);
assign wbu_sel = 4'hf;
assign wbu_addr = wbu_tmp_addr[(2-1):0];
// }}}
`else // WBUBUS_MASTER
// {{{
// Null bus master
// {{{
// }}}
// }}}
`endif // WBUBUS_MASTER
busexpander #(.AWIN(27), .DWIN(32),
.DWOUT(128))
xpandi32x128(
i_clk, i_reset,
wb_xpand_cyc, wb_xpand_stb, wb_xpand_we,
wb_xpand_addr[27-1:0],
wb_xpand_data, // 32 bits wide
wb_xpand_sel, // 32/8 bits wide
wb_xpand_stall, wb_xpand_ack, wb_xpand_idata, wb_xpand_err,
//
rambus_xpand_cyc, rambus_xpand_stb, rambus_xpand_we,
rambus_xpand_addr[25-1:0],
rambus_xpand_data, // 128 bits wide
rambus_xpand_sel, // 128/8 bits wide
rambus_xpand_stall, rambus_xpand_ack, rambus_xpand_idata,rambus_xpand_err);
`ifdef HDMI_IN_EDID_ACCESS
// {{{
wbi2cslave #( .INITIAL_MEM("edid.hex"),
.I2C_READ_ONLY(1'b1),
.MEM_ADDR_BITS(8))
the_input_edid(i_clk, 1'b0,
wb_edin_cyc, wb_edin_stb, wb_edin_we,
wb_edin_addr[6-1:0],
wb_edin_data, // 32 bits wide
wb_edin_sel, // 32/8 bits wide
wb_edin_stall, wb_edin_ack, wb_edin_idata,
i_hdmi_in_scl, i_hdmi_in_sda, o_hdmi_in_scl, o_hdmi_in_sda,
edid_dbg);
// }}}
`else // HDMI_IN_EDID_ACCESS
// {{{
assign o_hdmi_in_scl = 1'b1;
assign o_hdmi_in_sda = 1'b1;
// }}}
`endif // HDMI_IN_EDID_ACCESS
// }}}
endmodule // main.v
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
|
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 14:54:03 09/27/2011
// Module Name: spmc_uart_light_peri
//////////////////////////////////////////////////////////////////////////////////
module spmc_uart_light_peri(
input wire clk_peri, //Systemtakt
input wire [17:0] do_peri, //Datenbus vom MC
output wire [17:0] di_peri, //Datenbus zum MC
input wire [9:0] addr_peri, //Adressbus vom MC
input wire access_peri, //Signale fuer Peripheriezugriffe
input wire wr_peri, //Schreibsignal
input wire reset, //Reset-Signal
output wire intr, //Interrupt
input wire rx,
output wire tx,
input wire tx_chain_i
);
`include "uart_light/util/uart_functions.v"
parameter
BASE_ADR = 10'h0,
USTATUS_ADR = 0,
URX_ADR = 1,
UTX_ADR = 2,
CLOCK_FREQUENCY = 25000000,
FIFO_TX_DEPTH = 8,
FIFO_RX_DEPTH = 8,
BAUDRATE = 115200,
INTERRUPT_SUPPORTED = "FALSE",
ENABLE_TX_CHAIN = "FALSE",
ALL_PORTS = 3,
DECODSIM_DEB = "NO",
FIFO_ADDR_BITS_TX = log2(FIFO_TX_DEPTH - 1),
FIFO_ADDR_BITS_RX = log2(FIFO_RX_DEPTH - 1),
BAUD_ERROR_09 = baud_error(CLOCK_FREQUENCY, 9, BAUDRATE),
BAUD_ERROR_10 = baud_error(CLOCK_FREQUENCY, 10, BAUDRATE),
BAUD_ERROR_11 = baud_error(CLOCK_FREQUENCY, 11, BAUDRATE),
BAUD_ERROR_12 = baud_error(CLOCK_FREQUENCY, 12, BAUDRATE),
BAUD_ERROR_13 = baud_error(CLOCK_FREQUENCY, 13, BAUDRATE),
BAUD_ERROR_14 = baud_error(CLOCK_FREQUENCY, 14, BAUDRATE),
BAUD_ERROR_15 = baud_error(CLOCK_FREQUENCY, 15, BAUDRATE),
BAUD_ERROR_16 = baud_error(CLOCK_FREQUENCY, 16, BAUDRATE),
BAUD_ERROR_17 = baud_error(CLOCK_FREQUENCY, 17, BAUDRATE),
BAUD_ERROR_18 = baud_error(CLOCK_FREQUENCY, 18, BAUDRATE),
BAUD_ERROR_19 = baud_error(CLOCK_FREQUENCY, 19, BAUDRATE),
BAUD_ERROR_20 = baud_error(CLOCK_FREQUENCY, 20, BAUDRATE),
BAUD_ERROR_21 = baud_error(CLOCK_FREQUENCY, 21, BAUDRATE),
SAMPLING_COUNT = find_best_ovs_rate(CLOCK_FREQUENCY, BAUDRATE),
SC_SIZE = log2(SAMPLING_COUNT),
BR_DIVISOR_TX = CLOCK_FREQUENCY/BAUDRATE,
BR_DIVISOR_RX = baud_divisor(ovs_freq_10x(CLOCK_FREQUENCY, SAMPLING_COUNT), BAUDRATE),
BRD_SIZE_TX = log2(BR_DIVISOR_TX - 1),
BRD_SIZE_RX = log2(BR_DIVISOR_RX - 1);
wire fifo_rx_full;
wire fifo_rx_empty;
wire fifo_tx_full;
wire fifo_tx_empty;
wire fifo_tx_read;
wire [17:0] port_status;
wire [17:0] port_rx;
wire [7:0] word_rx;
wire uart_tx;
wire clk_rx;
generate
if (ENABLE_TX_CHAIN == "TRUE")
assign tx = uart_tx & tx_chain_i;
else
assign tx = uart_tx;
endgenerate
// Dekodierung der Adressen ********************** START *************************************
// chipselect fuer die Statusregister (ohne Modemsignale)
wire select_status_read; // Lesen
wire select_rx; // Lesen
wire select_tx; // Schreiben
wire select;
wire [ALL_PORTS-1:0] reg_select;
wire [ALL_PORTS-1:0] reg_read;
wire [ALL_PORTS-1:0] reg_write;
// Addressdekoder fuer alle Geraeteregister
reg_access_decoder #(
.REG_COUNT( ALL_PORTS ),
.BASE_ADR( BASE_ADR ),
.SIM_DEBUG( DECODSIM_DEB )
)
decod1 (
.reset( reset ),
.clk_peri( clk_peri ),
.addr_peri( addr_peri ),
.access_peri( access_peri ),
.wr_peri( wr_peri ),
.peri_select( select ),
.reg_select( reg_select ),
.reg_read( reg_read ),
.reg_write( reg_write )
);
// chipselect fuer die FIFO-,Status- und Steuerregister
assign select_status_read = reg_read[USTATUS_ADR]; // Lesen
assign select_rx = reg_read[URX_ADR]; // Lesen
assign select_tx = reg_write[UTX_ADR]; // Schreiben
// Dekodierung der Adressen ********************** END **************************************
generate
if(INTERRUPT_SUPPORTED == "FALSE") begin: ININTERRUPT_IS_NOT_SUPPORTED
assign port_status = {14'b0, fifo_tx_full, fifo_tx_empty, fifo_rx_full, fifo_rx_empty};
assign intr = 1'b0;
end else begin: INTERRUPT_IS_SUPPORTED
wire select_status_write, ir_tx, ir_rx;
reg intr_enable_tx, intr_enable_rx, intr_tx, intr_rx, intr_txr, fifo_rx_read;
reg clk_rx_toggle, clk_rx_lock, clk_rx_lock_val;
assign select_status_write = reg_write[USTATUS_ADR]; // Schreiben
assign port_status = {7'b0, intr_enable_tx, intr_enable_rx, 3'b0, intr_tx, intr_txr, fifo_tx_full, fifo_tx_empty, fifo_rx_full, fifo_rx_empty};
assign intr = ir_tx | ir_rx;
assign ir_tx = intr_enable_tx ? intr_tx:1'b0;
assign ir_rx = intr_enable_rx ? intr_rx:1'b0;
always @(posedge clk_peri, posedge reset) begin
if(reset) begin
intr_enable_tx <= 1'b0;
intr_enable_rx <= 1'b0;
end
else if(select_status_write) begin // INTR Freigabe im Statusregister
{intr_enable_tx, intr_enable_rx} <= do_peri[10:9];
end
end
always @(posedge clk_rx) begin
clk_rx_toggle <= !clk_rx_toggle;
end
always @(posedge clk_peri, posedge reset) begin
if(reset) begin
intr_tx <= 1'b0;
intr_rx <= 1'b0;
intr_txr <= 1'b1; // 1. Tx Interrupt sofort senden
fifo_rx_read <= 1'b0;
end
else if(select_status_write) begin
intr_tx <= 1'b0;
end
else if(select_rx)begin
intr_rx <= 1'b0;
clk_rx_lock <= 1'b1; // clk_rx lock setzen
fifo_rx_read <= 1'b1; // Daten lesen merken und Freigabe fuer einen Takt sperren
end
else if(select_tx) begin
intr_txr <= 1'b1; // Schreiben von Daten merken
end
else begin
if(!fifo_tx_full && intr_txr && !intr_tx) begin
intr_txr <= 1'b0; // naechste Interrupt erst wenn wieder etwas geschrieben wurde.
intr_tx <= 1'b1;
end
if(!fifo_rx_empty && !clk_rx_lock) begin //intr_rx wird gesetzt, sofern fifo_rx nicht leer ist
intr_rx <= 1'b1;
end
if (fifo_rx_read)
clk_rx_lock_val <= clk_rx_toggle;
else
if (clk_rx_toggle != clk_rx_lock_val)
clk_rx_lock <= 1'b0;
fifo_rx_read <= 1'b0; // intr_rx wieder freigeben
end
end
end
endgenerate
assign port_rx = {10'b0, word_rx};
assign di_peri = select_status_read ? port_status : (select_rx ? port_rx : 18'b0);
uart_light
#(
.FIFO_ADDR_BITS_RX(FIFO_ADDR_BITS_RX),
.FIFO_ADDR_BITS_TX(FIFO_ADDR_BITS_TX),
.BR_DIVISOR_TX(BR_DIVISOR_TX),
.BR_DIVISOR_RX(BR_DIVISOR_RX),
.BRD_SIZE_TX(BRD_SIZE_TX),
.BRD_SIZE_RX(BRD_SIZE_RX),
.SAMPLING_COUNT(SAMPLING_COUNT),
.SC_SIZE(SC_SIZE)
)
uart0(
.reset(reset),
.clk_peri(clk_peri),
//tx
.tx(uart_tx),
.word_ready(select_tx),
.word_tx(do_peri[7:0]),
.fifo_tx_full(fifo_tx_full),
.fifo_tx_empty(fifo_tx_empty),
.fifo_tx_read(fifo_tx_read),
//rx
.rx(rx),
.read_ready(select_rx),
.word_rx(word_rx),
.fifo_rx_full(fifo_rx_full),
.fifo_rx_empty(fifo_rx_empty),
.clk_rx_out(clk_rx)
);
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's ALU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// ALU ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_alu.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.15 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.14 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13 2004/05/09 19:49:03 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6 2002/03/29 16:40:10 lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5 2002/03/29 16:33:59 lampret
// Added again just recently removed full_case directive
//
// Revision 1.4 2002/03/29 15:16:53 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:45 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
(* DONT_TOUCH = "yes" *) module or1200_alu(
a, b, mult_mac_result, macrc_op,
alu_op, shrot_op, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
cyforw, cy_we, carry, flag
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] a;
input [width-1:0] b;
input [width-1:0] mult_mac_result;
input macrc_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
input [5:0] cust5_limm;
output [width-1:0] result;
output flagforw;
output flag_we;
output cyforw;
output cy_we;
input carry;
input flag;
//
// Internal wires and regs
//
reg [width-1:0] result;
reg [width-1:0] shifted_rotated;
reg [width-1:0] result_cust5;
reg flagforw;
reg flagcomp;
reg flag_we;
reg cy_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire a_eq_b;
wire a_lt_b;
`endif
wire [width-1:0] result_sum;
`ifdef OR1200_IMPL_ADDC
wire [width-1:0] result_csum;
wire cy_csum;
`endif
wire [width-1:0] result_and;
wire cy_sum;
reg cyforw;
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {32'd0, carry};
`endif
assign result_and = a & b;
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
//
// Central part of the ALU
//
always @(alu_op or a or b or result_csum or flag or result_cust5 or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
casex (alu_op) // synopsys parallel_case
`else
casex (alu_op) // synopsys full_case parallel_case
`endif
`OR1200_ALUOP_FF1: begin
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
end
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
`OR1200_ALUOP_SHROT : begin
result = shifted_rotated;
end
`OR1200_ALUOP_ADD : begin
result = result_sum;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC : begin
result = result_csum;
end
`endif
`OR1200_ALUOP_SUB : begin
result = a - b;
end
`OR1200_ALUOP_XOR : begin
result = a ^ b;
end
`OR1200_ALUOP_OR : begin
result = a | b;
end
`OR1200_ALUOP_IMM : begin
result = b;
end
`OR1200_ALUOP_MOVHI : begin
if (macrc_op) begin
result = mult_mac_result;
end
else begin
result = b << 16;
end
end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV,
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL : begin
result = mult_mac_result;
end
`endif
`OR1200_ALUOP_CMOV: begin
result = flag ? a : b;
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
begin
`endif
result=result_and;
end
endcase
end
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casex (cust5_op) // synopsys parallel_case
5'h1 : begin
casex (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
2'h3: result_cust5 = {b[7:0], a[23:0]};
endcase
end
5'h2 :
result_cust5 = a | (1 << cust5_limm);
5'h3 :
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
default: begin
result_cust5 = a;
end
endcase
end
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_csum or result_and or flagcomp) begin
casex (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
flag_we = 1'b1;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC : begin
flagforw = (result_csum == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_AND: begin
flagforw = (result_and == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_COMP: begin
flagforw = flagcomp;
flag_we = 1'b1;
end
default: begin
flagforw = 1'b0;
flag_we = 1'b0;
end
endcase
end
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
or cy_csum
`endif
) begin
casex (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
cy_we = 1'b1;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC: begin
cyforw = cy_csum;
cy_we = 1'b1;
end
`endif
`endif
default: begin
cyforw = 1'b0;
cy_we = 1'b0;
end
endcase
end
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
case (shrot_op) // synopsys parallel_case
`OR1200_SHROTOP_SLL :
shifted_rotated = (a << b[4:0]);
`OR1200_SHROTOP_SRL :
shifted_rotated = (a >> b[4:0]);
`ifdef OR1200_IMPL_ALU_ROTATE
`OR1200_SHROTOP_ROR :
shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
default:
shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
endcase
end
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = (comp_a == comp_b);
`OR1200_COP_SFNE:
flagcomp = (comp_a != comp_b);
`OR1200_COP_SFGT:
flagcomp = (comp_a > comp_b);
`OR1200_COP_SFGE:
flagcomp = (comp_a >= comp_b);
`OR1200_COP_SFLT:
flagcomp = (comp_a < comp_b);
`OR1200_COP_SFLE:
flagcomp = (comp_a <= comp_b);
default:
flagcomp = 1'b0;
endcase
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Set Implicit Arguments.
Require Export Notations.
Notation "A -> B" := (forall (_ : A), B) : type_scope.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [proof_admitted] is used to implement the admit tactic *)
Axiom proof_admitted : False.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ assumption | ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ | assumption ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left; assumption| right]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left| right; assumption]);
[apply Hl | apply Hr]; assumption.
Qed.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_l]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [apply Hl | ]; assumption.
+ apply HypR; split; [apply Hr | ]; assumption.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_r]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [ | apply Hl ]; assumption.
+ apply HypR; split; [ | apply Hr ]; assumption.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; split; intros [? ?]; split; assumption.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; split; [ intros [[? ?] ?]| intros [? [? ?]]]; repeat split; assumption.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_l]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ right | destruct Fl | ]; assumption. }
{ destruct Hr; [ right | destruct Fr | ]; assumption. }
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_r]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ left | | destruct Fl ]; assumption. }
{ destruct Hr; [ left | | destruct Fr ]; assumption. }
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; split; (intros [? | ?]; [ right | left ]; assumption).
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; split; [ intros [[?|?]|?]| intros [?|[?|?]]].
+ left; assumption.
+ right; left; assumption.
+ right; right; assumption.
+ left; left; assumption.
+ left; right; assumption.
+ right; assumption.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; split; intros [Hl Hr]; (split; intros; [ apply Hl | apply Hr]); assumption.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [Q] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : t , p & q" := (ex2 (fun x:t => p) (fun x:t => q))
(at level 200, x ident, t at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : t , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror : core.
Hint Resolve eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' H in '/' H' ']'").
Notation "'rew' [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- H in '/' H' ']'").
Notation "'rew' <- [ P ] H 'in' H'" := (eq_rect_r P H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
Notation "'rew' -> [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Import EqNotations.
Lemma rew_opp_r : forall A (P:A->Type) (x y:A) (H:x=y) (a:P y), rew H in rew <- H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Lemma rew_opp_l : forall A (P:A->Type) (x y:A) (H:x=y) (a:P x), rew <- H in rew H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal_compose : forall A B C (a b:A) (f:A->B) (g:B->C) (e:a=b),
f_equal g (f_equal f e) = f_equal (fun a => g (f a)) e.
Proof.
destruct e. reflexivity.
Defined.
(** The goupoid structure of equality *)
Theorem eq_trans_refl_l : forall A (x y:A) (e:x=y), eq_trans eq_refl e = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_trans_refl_r : forall A (x y:A) (e:x=y), eq_trans e eq_refl = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_sym_involutive : forall A (x y:A) (e:x=y), eq_sym (eq_sym e) = e.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_l : forall A (x y:A) (e:x=y), eq_trans (eq_sym e) e = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_r : forall A (x y:A) (e:x=y), eq_trans e (eq_sym e) = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_assoc : forall A (x y z t:A) (e:x=y) (e':y=z) (e'':z=t),
eq_trans e (eq_trans e' e'') = eq_trans (eq_trans e e') e''.
Proof.
destruct e''; reflexivity.
Defined.
(** Extra properties of equality *)
Theorem eq_id_comm_l : forall A (f:A->A) (Hf:forall a, a = f a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf a)).
pattern (f a) at 1 2 3 4 5 7 8, (Hf a) at 1 2.
destruct (Hf a).
destruct (Hf a).
reflexivity.
Defined.
Theorem eq_id_comm_r : forall A (f:A->A) (Hf:forall a, f a = a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf (f (f a)))).
set (Hfsymf := fun a => eq_sym (Hf a)).
change (eq_sym (Hf (f (f a)))) with (Hfsymf (f (f a))).
pattern (Hfsymf (f (f a))).
destruct (eq_id_comm_l f Hfsymf (f a)).
destruct (eq_id_comm_l f Hfsymf a).
unfold Hfsymf.
destruct (Hf a). simpl. unfold a0; clear a0.
rewrite eq_trans_refl_l.
reflexivity.
Defined.
Lemma eq_trans_map_distr : forall A B x y z (f:A->B) (e:x=y) (e':y=z), f_equal f (eq_trans e e') = eq_trans (f_equal f e) (f_equal f e').
Proof.
destruct e'.
reflexivity.
Defined.
Lemma eq_sym_map_distr : forall A B (x y:A) (f:A->B) (e:x=y), eq_sym (f_equal f e) = f_equal f (eq_sym e).
Proof.
destruct e.
reflexivity.
Defined.
Lemma eq_trans_sym_distr : forall A (x y z:A) (e:x=y) (e':y=z), eq_sym (eq_trans e e') = eq_trans (eq_sym e') (eq_sym e).
Proof.
destruct e, e'.
reflexivity.
Defined.
(* Aliases *)
Notation sym_eq := eq_sym (compat "8.3").
Notation trans_eq := eq_trans (compat "8.3").
Notation sym_not_eq := not_eq_sym (compat "8.3").
Notation refl_equal := eq_refl (compat "8.3").
Notation sym_equal := eq_sym (compat "8.3").
Notation trans_equal := eq_trans (compat "8.3").
Notation sym_not_equal := not_eq_sym (compat "8.3").
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
replace x1 with x0 by (transitivity x; [symmetry|]; auto).
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros ? ? ? [? ?] [? ?]; split; intros; auto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* REMINDER: Please do not put solutions to the exercises in
publicly accessible places. Thank you!! *)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data). We begin with polymorphism. *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.)
What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** (Side note on notation: In .v files, the "forall" quantifier is
spelled out in letters. In the generated HTML files, [forall] is
usually typeset as the usual mathematical "upside down A," but
you'll see the spelled-out "forall" in a few places, as in the
above comments. This is just a quirk of typesetting: there is no
difference in meaning.) *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've written [nil] and [cons] explicitly here because we haven't
yet defined the [ [] ] and [::] notations for the new version of
lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic versions of all the
list-processing functions that we wrote before. Here is [repeat],
for example: *)
Fixpoint repeat (X : Type) (x : X) (count : nat) : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat X x count')
end.
(** As with [nil] and [cons], we can use [repeat] by applying it
first to a type and then to its list argument: *)
Example test_repeat1 :
repeat nat 4 2 = cons nat 4 (cons nat 4 (nil nat)).
Proof. reflexivity. Qed.
(** To use [repeat] to build other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_repeat2 :
repeat bool false 1 = cons bool false (nil bool).
Proof. reflexivity. Qed.
Module MumbleGrumble.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* No, yes, yes, yes, yes, no, yes *)
*)
(** [] *)
End MumbleGrumble.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [repeat] again, but this time we
won't specify the types of any of the arguments. Will Coq still
accept it? *)
Fixpoint repeat' X x count : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat' X x count')
end.
(** Indeed it will. Let's see what type Coq has assigned to [repeat']: *)
Check repeat'.
(* ===> forall X : Type, X -> nat -> list X *)
Check repeat.
(* ===> forall X : Type, X -> nat -> list X *)
(** It has exactly the same type type as [repeat]. Coq was able
to use _type inference_ to deduce what the types of [X], [x], and
[count] must be, based on how they are used. For example, since
[X] is used as an argument to [cons], it must be a [Type], since
[cons] expects a [Type] as its first argument; matching [count]
with [0] and [S] means it must be a [nat]; and so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks, so we will continue to use them most of the time. You
should try to find a balance in your own code between too many
type annotations (which can clutter and distract) and too
few (which forces readers to perform type inference in their heads
in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** To we use a polymorphic function, we need to pass it one or
more types in addition to its other arguments. For example, the
recursive call in the body of the [repeat] function above must
pass along the type [X]. But since the second argument to
[repeat] is an element of [X], it seems entirely obvious that the
first argument can only be [X] -- why should we have to write it
explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please try to figure out for yourself
what belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- indeed, the
two procedures rely on the same underlying mechanisms. Instead of
simply omitting the types of some arguments to a function, like
repeat' X x count : list X :=
we can also replace the types with [_]
repeat' (X : _) (x : _) (count : _) : list X :=
to tell Coq to attempt to infer the missing information.
Using implicit arguments, the [count] function can be written
like this: *)
Fixpoint repeat'' X x count : list X :=
match count with
| 0 => nil _
| S count' => cons _ x (repeat'' _ x count')
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference in both keystrokes and
readability is nontrivial. For example, suppose we want to write
down a list containing the numbers [1], [2], and [3]. Instead of
writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' :=
cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** We can go further and even avoid writing [_]'s in most cases by
telling Coq _always_ to infer the type argument(s) of a given
function. The [Arguments] directive specifies the name of the
function (or constructor) and then lists its argument names, with
curly braces around any arguments to be treated as implicit. (If
some arguments of a definition don't have a name, as is often the
case for constructors, they can be marked with a wildcard pattern
[_].) *)
Arguments nil {X}.
Arguments cons {X} _ _.
Arguments repeat {X} x count.
(** Now, we don't have to supply type arguments at all: *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
(** Alternatively, we can declare an argument to be implicit
when defining the function itself, by surrounding it in curly
braces. For example: *)
Fixpoint repeat''' {X : Type} (x : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => cons x (repeat''' x count')
end.
(** (Note that we didn't even have to provide a type argument to the
recursive call to [repeat''']; indeed, it would be invalid to
provide one!)
We will use the latter style whenever possible, but we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. The reason for this is that marking the
parameter of an inductive type as implicit causes it to become
implicit for the type itself, not just for its constructors. For
instance, consider the following alternative definition of the
[list] type: *)
Inductive list' {X:Type} : Type :=
| nil' : list'
| cons' : X -> list' -> list'.
(** Because [X] is declared as implicit for the _entire_ inductive
definition including [list'] itself, we now have to write just
[list'] whether we are talking about lists of numbers or booleans
or anything else, rather than [list' nat] or [list' bool] or
whatever; this is a step too far. *)
(** Let's finish by re-implementing a few other standard list
functions on our new polymorphic lists... *)
Fixpoint app {X : Type} (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons h (app t l2)
end.
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => nil
| cons h t => app (rev t) (cons h nil)
end.
Fixpoint length {X : Type} (l : list X) : nat :=
match l with
| nil => 0
| cons _ l' => S (length l')
end.
Example test_rev1 :
rev (cons 1 (cons 2 nil)) = (cons 2 (cons 1 nil)).
Proof. reflexivity. Qed.
Example test_rev2:
rev (cons true nil) = cons true nil.
Proof. reflexivity. Qed.
Example test_length1: length (cons 1 (cons 2 (cons 3 nil))) = 3.
Proof. reflexivity. Qed.
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly just this time. For
example, suppose we write this: *)
Fail Definition mynil := nil.
(** (The [Fail] qualifier that appears before [Definition] can be
used with _any_ command, and is used to ensure that that command
indeed fails when executed. If the command does fail, Coq prints
the corresponding error message, but continues processing the rest
of the file.)
Here, Coq gives us an error because it doesn't know what type
argument to supply to [nil]. We can help it by providing an
explicit type declaration (so that Coq has more information
available when it gets to the "application" of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Complete the proofs below. *)
Theorem app_nil_r : forall (X:Type), forall l:list X,
l ++ [] = l.
Proof.
intros. induction l as [| x l'].
- reflexivity.
- simpl. rewrite IHl'. reflexivity.
Qed.
Theorem app_assoc : forall A (l m n:list A),
l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros. induction l as [| x l'].
- reflexivity.
- simpl. rewrite IHl'. reflexivity.
Qed.
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros. induction l1 as [| x l1'].
- reflexivity.
- simpl. rewrite IHl1'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (more_poly_exercises) *)
(** Here are some slightly more interesting ones... *)
Theorem rev_app_distr: forall X (l1 l2 : list X),
rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
intros. induction l1 as [| x l1'].
- simpl.
assert (HAppNil: forall X (l : list X), l ++ [] = l).
{ intros. induction l.
- reflexivity.
- simpl. rewrite IHl. reflexivity. }
rewrite HAppNil. reflexivity.
- simpl. rewrite IHl1'. rewrite <- app_assoc. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l as [| x l'].
- reflexivity.
- simpl.
assert (HRevAppSingle: forall X x (l:list X), rev (l ++ [x]) = x :: rev l).
{ intros. induction l.
- reflexivity.
- simpl. rewrite IHl. reflexivity. }
rewrite HRevAppSingle. rewrite IHl'. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_, often called _products_: *)
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for product _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should only be used when parsing types. This avoids a clash with
the multiplication symbol.) *)
(** It is easy at first to get [(x,y)] and [X*Y] confused.
Remember that [(x,y)] is a _value_ built from two other values,
while [X*Y] is a _type_ built from two other types. If [x] has
type [X] and [y] has type [Y], then [(x,y)] has type [X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with
| (x, y) => x
end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with
| (x, y) => y
end.
(** The following function takes two lists and combines them
into a list of pairs. In other functional languages, it is often
called [zip]; we call it [combine] for consistency with Coq's
standard library. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx, ly with
| [], _ => []
| _, [] => []
| x :: tx, y :: ty => (x, y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Compute (combine [1;2] [false;false;true;true]).
print? [] *)
(** **** Exercise: 2 stars, recommended (split) *)
(** The function [split] is the right inverse of [combine]: it takes a
list of pairs and returns a pair of lists. In many functional
languages, it is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit test. *)
Fixpoint split {X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| (x, y) :: xs => (x :: fst (split xs), y :: snd (split xs))
| [] => ([], [])
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_,
which generalize [natoption] from the previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** We can now rewrite the [nth_error] function so that it works
with any type of lists. *)
Fixpoint nth_error {X : Type} (l : list X) (n : nat)
: option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else nth_error l' (pred n)
end.
Example test_nth_error1 : nth_error [4;5;6;7] 0 = Some 4.
Proof. reflexivity. Qed.
Example test_nth_error2 : nth_error [[1];[2]] 1 = Some [2].
Proof. reflexivity. Qed.
Example test_nth_error3 : nth_error [true] 2 = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_error_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_error] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_error {X : Type} (l : list X) : option X :=
match l with
| x :: _ => Some x
| [] => None
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_error.
Example test_hd_error1 : hd_error [1;2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_error2 : hd_error [[1];[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(** Like many other modern programming languages -- including
all functional languages (ML, Haskell, Scheme, Scala, Clojure,
etc.) -- Coq treats functions as first-class citizens, allowing
them to be passed as arguments to other functions, returned as
results, stored in data structures, etc.*)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Filter *)
(** Here is a more useful higher-order function, taking a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filtering" the list, returning a new list containing just
those elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is arguably a little sad, in the example just above, to
be forced to define the function [length_is_1] and give it a name
just to be able to pass it as an argument to [filter], since we
will probably never use it again. Moreover, this is not an
isolated example: when using higher-order functions, we often want
to pass as arguments "one-off" functions that we will never use
again; having to give each of these functions a name would be
tedious.
Fortunately, there is a better way. We can construct a function
"on the fly" without declaring it at the top level or giving it a
name. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** The expression [(fun n => n * n)] can be read as "the function
that, given a number [n], yields [n * n]." *)
(** Here is the [filter] example, rewritten to use an anonymous
function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (evenb n) (negb (leb n 7))) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list. *)
Definition partition {X : Type}
(test : X -> bool)
(l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X) : (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same, since [map] takes _two_ type arguments, [X] and [Y]; it
can thus be applied to a list of numbers and a function from
numbers to booleans to yield a list of booleans: *)
Example test_map2:
map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a _list of lists_ of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** *** Exercises *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros. induction l as [| x l'].
- reflexivity.
- simpl.
assert (H: forall (l0 : list X), map f (l0 ++ [x]) = map f l0 ++ [f x]).
{ intros. induction l0.
- reflexivity.
- simpl. rewrite IHl0. reflexivity. }
rewrite H. rewrite IHl'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, recommended (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| x :: xs => (f x) ++ flat_map f xs
| [] => []
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y)
: Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Some more examples: *)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 :
fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 :
fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 :
fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions That Construct Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as arguments. Let's look at some examples that
involve _returning_ functions as the results of other functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. This operator is _right-associative_, so the type of
[plus] is really a shorthand for [nat -> (nat -> nat)] -- i.e., it
can be read as saying that "[plus] is a one-argument function that
takes a [nat] and returns a one-argument function that takes
another [nat] and returns a [nat]." In the examples above, we
have always applied [plus] to both of its arguments at once, but
if we like we can supply just the first. This is called _partial
application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ##################################################### *)
(** * Additional Exercises *)
Module Exercises.
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros. induction l as [| x l'].
- reflexivity.
- unfold fold_length. unfold fold_length in IHl'.
simpl. rewrite IHl'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x acc => f x :: acc) l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y : Type) (f : X -> Y) (l : list X),
map f l = fold_map f l.
Proof.
intros. induction l as [| x l'].
- reflexivity.
- unfold fold_map. unfold fold_map in IHl'.
simpl. rewrite <- IHl'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
(* FILL IN HERE *) admit.
(** As a trivial example of the usefulness of currying, we can use it
to shorten one of the examples that we saw above: *)
Example test_map2: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** Thought exercise: before running the following commands, can you
calculate the types of [prod_curry] and [prod_uncurry]? *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type)
(f : X -> Y -> Z)
x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (nth_error_informal) *)
(** Recall the definition of the [nth_error] function:
Fixpoint nth_error {X : Type} (l : list X) (n : nat) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else nth_error l' (pred n)
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @nth_error X l n = None
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
(** This exercise explores an alternative way of defining natural
numbers, using the so-called _Church numerals_, named after
mathematician Alonzo Church. We can represent a natural number
[n] as a function that takes a function [f] as a parameter and
returns [f] iterated [n] times. *)
Module Church.
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Iterating
a function once should be the same as just applying it. Thus: *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** Similarly, [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** Defining [zero] is somewhat trickier: how can we "apply a function
zero times"? The answer is actually simple: just return the
argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] can be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in
particular how the [doit3times] function we've defined previously
is actually just the Church representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number: *)
Definition succ (n : nat) : nat :=
(* FILL IN HERE *) admit.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** Addition of two natural numbers: *)
Definition plus (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** Multiplication: *)
Definition mult (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** Exponentiation: *)
(** (_Hint_: Polymorphism plays a crucial role here. However,
choosing the right type to iterate over can be tricky. If you hit
a "Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic.) *)
Definition exp (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
End Church.
(** [] *)
End Exercises.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:32:38 01/08/2017
// Design Name:
// Module Name: plane
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module planeB(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input [10:0] poX,
input [10:0] poY,
output reg wing,
output reg body
);
parameter pL = 40;
parameter pW = 10;
parameter wL = 15;
parameter wW = 15;
parameter wP = 10;
// body
always@(posedge clk, posedge rst)
begin
if(rst) body <= 0;
else begin
if(x < poX+pL && x > poX && y < poY+wL+pW && y >poY+wL) body <= 1;
else body <= 0;
end
end
// wing
always@(posedge clk, posedge rst)
begin
if(rst) wing <= 0;
else begin
if(x < poX+wP+wW && x > poX+wP && y < poY+wL && y > poY && x-poX+y-poY >wW+wP) wing <= 1;
else if(x < poX+wP+wW && x > poX+wP && y > poY+wL+pW && y < poY+wL+wL+pW && x-poX-y+poY >wP-wL-pW) wing <= 1;
else wing <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
module hankel_matrixd_d #(
parameter ROW = 4,
parameter COL = 4,
parameter WIDTH = 16,
parameter ADDR = 8
)(
input clk,
input start,
input [WIDTH-1:0] data,
output reg [ADDR-1:0] addr,
output reg rd
);
reg [WIDTH-1:0] mat [0:ROW-1] [0:COL-1];
reg [7:0] r,c,r_i,c_i,state;
reg [WIDTH-1:0] data_i;
reg [ADDR-1:0] addr_i;
parameter
IDLE = 2'b00,
INIT = 2'b01,
COPY = 2'b10,
WRITE= 2'b11;
initial begin
c <= 0;
r <= 0;
addr <=0;
//addr_i <=0;
rd<=0;
state <= IDLE;
end
always@(posedge clk) begin
case(state)
IDLE: begin
if(start)
state <= INIT;
rd <=1;
r<=0;
c<=0;
addr <=0;
end
INIT: begin
if(r==0) begin
mat[r][c] <= data;
c <= c+1;
addr <= addr+1;
if(c==COL-1) begin
c <= 0;
state <= COPY;
r <= r+1;
end
end
end
COPY: begin
if(r!=0) begin
mat[r][c] <= mat[r-1][c+1];
c <= c+1;
if(c==COL-2)begin
state <= WRITE;
rd <= 1;
addr <= addr+1;
end
end
end
WRITE: begin
mat[r][c]<= data;
state <= COPY;
r <= r+1;
c<=0;
if(r==ROW-1)
state <= IDLE;
end
endcase
end
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/spifsm.v:3" *)
module \$paramod\SPIFSM\SPPRWidth=4\SPRWidth=4\DataWidth=8 (Reset_n_i, Clk_i, Start_i, Done_o, Byte0_o, Byte1_o, SPI_Transmission_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_Data_i, SPI_FIFOFull_i, SPI_FIFOEmpty_i, ADT7310CS_n_o, ParamCounterPreset_i);
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$0\Byte0_o[7:0] ;
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$0\Byte1_o[7:0] ;
(* src = "../../verilog/spifsm.v:217" *)
wire [31:0] \$0\SPI_FSM_Timer[31:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\ADT7310CS_n_o[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\SPI_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$2\SPI_ReadNext_o[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2453 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2455 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2457 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2459 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2461 ;
wire \$auto$opt_reduce.cc:126:opt_mux$2477 ;
wire \$procmux$297_CMP ;
wire \$procmux$298_CMP ;
wire \$procmux$301_CMP ;
wire \$procmux$302_CMP ;
wire \$procmux$305_CMP ;
wire \$procmux$334_CMP ;
wire \$procmux$335_CMP ;
wire \$procmux$336_CMP ;
wire [31:0] \$procmux$80_Y ;
(* src = "../../verilog/spifsm.v:231" *)
wire [31:0] \$sub$../../verilog/spifsm.v:231$46_Y ;
(* src = "../../verilog/spifsm.v:24" *)
output ADT7310CS_n_o;
(* src = "../../verilog/spifsm.v:13" *)
output [7:0] Byte0_o;
(* src = "../../verilog/spifsm.v:14" *)
output [7:0] Byte1_o;
(* src = "../../verilog/spifsm.v:9" *)
input Clk_i;
(* src = "../../verilog/spifsm.v:12" *)
output Done_o;
(* src = "../../verilog/spifsm.v:26" *)
input [31:0] ParamCounterPreset_i;
(* src = "../../verilog/spifsm.v:8" *)
input Reset_n_i;
(* src = "../../verilog/spifsm.v:20" *)
input [7:0] SPI_Data_i;
(* src = "../../verilog/spifsm.v:19" *)
output [7:0] SPI_Data_o;
(* src = "../../verilog/spifsm.v:22" *)
input SPI_FIFOEmpty_i;
(* src = "../../verilog/spifsm.v:21" *)
input SPI_FIFOFull_i;
(* src = "../../verilog/spifsm.v:215" *)
wire [31:0] SPI_FSM_Timer;
(* src = "../../verilog/spifsm.v:45" *)
wire SPI_FSM_TimerEnable;
(* src = "../../verilog/spifsm.v:43" *)
wire SPI_FSM_TimerOvfl;
(* src = "../../verilog/spifsm.v:44" *)
wire SPI_FSM_TimerPreset;
(* src = "../../verilog/spifsm.v:47" *)
wire SPI_FSM_Wr0;
(* src = "../../verilog/spifsm.v:46" *)
wire SPI_FSM_Wr1;
(* src = "../../verilog/spifsm.v:18" *)
output SPI_ReadNext_o;
(* src = "../../verilog/spifsm.v:16" *)
input SPI_Transmission_i;
(* src = "../../verilog/spifsm.v:17" *)
output SPI_Write_o;
(* src = "../../verilog/spifsm.v:11" *)
input Start_i;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2454 (
.A({ SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$298_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2453 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000110),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2456 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2455 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000001001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2458 (
.A({ SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2457 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2460 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2459 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2462 (
.A({ \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$302_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2461 )
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2478 (
.A({ \$procmux$334_CMP , \$procmux$301_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2477 )
);
(* src = "../../verilog/spifsm.v:236" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/spifsm.v:236$47 (
.A(SPI_FSM_Timer),
.B(0),
.Y(SPI_FSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/spifsm.v:41" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000011),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000001010),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000100),
.STATE_NUM(32'b00000000000000000000000000001011),
.STATE_NUM_LOG2(32'b00000000000000000000000000000100),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(44'b01110011010110010001011010100010010010000000),
.TRANS_NUM(32'b00000000000000000000000000001111),
.TRANS_TABLE(315'b1010z1z101000001000001010z0z000100001000001001zzz001000000000101000zzz010100100000000111zzz010001000000000110zzz001100000010000101zzz101000010000000100zzz000000000000000011z0z100100000001000011z1z001100000001000010zz1100000000000010010zz0001000000000010001zzz0111100000000000001zz0110000001000000000zz00000000010000)
) \$fsm$\SPI_FSM_State$2481 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl }),
.CTRL_OUT({ SPI_FSM_Wr1, SPI_FSM_Wr0, \$procmux$336_CMP , \$procmux$335_CMP , \$procmux$334_CMP , \$procmux$305_CMP , \$procmux$302_CMP , \$procmux$301_CMP , \$procmux$298_CMP , \$procmux$297_CMP })
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2439 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0_o[7:0] ),
.Q(Byte0_o)
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$2440 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1_o[7:0] ),
.Q(Byte1_o)
);
(* src = "../../verilog/spifsm.v:217" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$2441 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SPI_FSM_Timer[31:0] ),
.Q(SPI_FSM_Timer)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$296 (
.A(1'b0),
.B({ 1'b1, \$2\SPI_FSM_TimerEnable[0:0] }),
.S({ \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(SPI_FSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$317 (
.A(1'b1),
.B({ 1'b0, SPI_FSM_TimerOvfl }),
.S({ \$procmux$298_CMP , \$procmux$297_CMP }),
.Y(SPI_FSM_TimerPreset)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$371 (
.A(1'b0),
.B({ \$2\SPI_ReadNext_o[0:0] , 1'b1 }),
.S({ \$auto$opt_reduce.cc:126:opt_mux$2477 , \$auto$opt_reduce.cc:126:opt_mux$2453 }),
.Y(SPI_ReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$396 (
.A(1'b1),
.B({ \$2\ADT7310CS_n_o[0:0] , \$2\SPI_FSM_TimerEnable[0:0] , 1'b0 }),
.S({ \$procmux$305_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2455 }),
.Y(ADT7310CS_n_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$413 (
.A(1'b1),
.B({ \$2\ADT7310CS_n_o[0:0] , 1'b0 }),
.S({ \$procmux$305_CMP , \$auto$opt_reduce.cc:126:opt_mux$2457 }),
.Y(Done_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$439 (
.A(8'b00001000),
.B(24'b001000000101000011111111),
.S({ \$procmux$302_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2459 }),
.Y(SPI_Data_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$481 (
.A(1'b0),
.B({ Start_i, SPI_FSM_TimerOvfl, 1'b1 }),
.S({ \$procmux$305_CMP , \$procmux$297_CMP , \$auto$opt_reduce.cc:126:opt_mux$2461 }),
.Y(SPI_Write_o)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$535 (
.A(Start_i),
.Y(\$2\ADT7310CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$641 (
.A(SPI_Transmission_i),
.Y(\$2\SPI_ReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$659 (
.A(SPI_FSM_TimerOvfl),
.Y(\$2\SPI_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$70 (
.A(Byte0_o),
.B(SPI_Data_i),
.S(SPI_FSM_Wr0),
.Y(\$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$77 (
.A(Byte1_o),
.B(SPI_Data_i),
.S(SPI_FSM_Wr1),
.Y(\$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$80 (
.A(SPI_FSM_Timer),
.B(\$sub$../../verilog/spifsm.v:231$46_Y ),
.S(SPI_FSM_TimerEnable),
.Y(\$procmux$80_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$83 (
.A(\$procmux$80_Y ),
.B(ParamCounterPreset_i),
.S(SPI_FSM_TimerPreset),
.Y(\$0\SPI_FSM_Timer[31:0] )
);
(* src = "../../verilog/spifsm.v:231" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/spifsm.v:231$46 (
.A(SPI_FSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/spifsm.v:231$46_Y )
);
endmodule
(* src = "../../verilog/sensorfsm.v:3" *)
module \$paramod\SensorFSM\DataWidth=8 (Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorValue_o, MeasureFSM_Start_o, MeasureFSM_Done_i, MeasureFSM_Byte0_i, MeasureFSM_Byte1_i, ParamThreshold_i, ParamCounterPreset_i);
(* src = "../../verilog/sensorfsm.v:130" *)
wire [15:0] \$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:153" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$2463 ;
wire \$procmux$1004_CMP ;
wire \$procmux$1007_CMP ;
wire \$procmux$1129_CMP ;
wire [15:0] \$procmux$826_Y ;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [15:0] \$sub$../../verilog/sensorfsm.v:144$59_Y ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/sensorfsm.v:7" *)
input Clk_i;
(* src = "../../verilog/sensorfsm.v:10" *)
output CpuIntr_o;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [16:0] DiffAB;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] DiffBA;
(* src = "../../verilog/sensorfsm.v:9" *)
input Enable_i;
(* src = "../../verilog/sensorfsm.v:15" *)
input [7:0] MeasureFSM_Byte0_i;
(* src = "../../verilog/sensorfsm.v:16" *)
input [7:0] MeasureFSM_Byte1_i;
(* src = "../../verilog/sensorfsm.v:14" *)
input MeasureFSM_Done_i;
(* src = "../../verilog/sensorfsm.v:13" *)
output MeasureFSM_Start_o;
(* src = "../../verilog/sensorfsm.v:19" *)
input [15:0] ParamCounterPreset_i;
(* src = "../../verilog/sensorfsm.v:18" *)
input [15:0] ParamThreshold_i;
(* src = "../../verilog/sensorfsm.v:6" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:32" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/sensorfsm.v:33" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/sensorfsm.v:128" *)
wire [15:0] SensorFSM_Timer;
(* src = "../../verilog/sensorfsm.v:31" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/sensorfsm.v:29" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/sensorfsm.v:30" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] SensorValue;
(* src = "../../verilog/sensorfsm.v:11" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/sensorfsm.v:38" *)
wire [15:0] Word0;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$2464 (
.A({ \$procmux$1129_CMP , \$procmux$1007_CMP , \$procmux$1004_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$2463 )
);
(* src = "../../verilog/sensorfsm.v:149" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/sensorfsm.v:149$60 (
.A(SensorFSM_Timer),
.B(16'b0000000000000000),
.Y(SensorFSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/sensorfsm.v:27" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000011),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000010),
.STATE_NUM(32'b00000000000000000000000000000100),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(8'b11011000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(117'b011zzzz0100000100zz10100010101zz1001001010zzz0000001001z11z011100001z01z010100001zz0z001100000zzz1010010000zzz0000010)
) \$fsm$\SensorFSM_State$2494 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SensorFSM_TimerOvfl, SensorFSM_DiffTooLarge, MeasureFSM_Done_i, Enable_i }),
.CTRL_OUT({ \$procmux$1129_CMP , \$procmux$1007_CMP , \$procmux$1004_CMP })
);
(* src = "../../verilog/sensorfsm.v:174" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/sensorfsm.v:174$67 (
.A(AbsDiffResult),
.B(ParamThreshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/sensorfsm.v:130" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2443 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[15:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/sensorfsm.v:153" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$2444 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1036 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1065 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\MeasureFSM_Start_o[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1142 (
.A(MeasureFSM_Done_i),
.B(SensorFSM_DiffTooLarge),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1174 (
.A(1'b1),
.B(\$4\SensorFSM_TimerPreset[0:0] ),
.S(MeasureFSM_Done_i),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$1206 (
.A(SensorFSM_DiffTooLarge),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$826 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/sensorfsm.v:144$59_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$826_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$829 (
.A(\$procmux$826_Y ),
.B(ParamCounterPreset_i),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$832 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$923 (
.A(\$auto$opt_reduce.cc:126:opt_mux$2463 ),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$943 (
.A(\$procmux$1004_CMP ),
.B(\$2\MeasureFSM_Start_o[0:0] ),
.Y(MeasureFSM_Start_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$953 (
.A(\$procmux$1129_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$983 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$1007_CMP , \$procmux$1004_CMP , \$procmux$1129_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$998 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$1007_CMP , \$procmux$1004_CMP , \$procmux$1129_CMP }),
.Y(SensorFSM_TimerPreset)
);
(* src = "../../verilog/sensorfsm.v:144" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:144$59 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/sensorfsm.v:144$59_Y )
);
(* src = "../../verilog/sensorfsm.v:170" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/sensorfsm.v:170$64 (
.A({ 1'b0, MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/sensorfsm.v:171" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/sensorfsm.v:171$65 (
.A(Word0),
.B({ MeasureFSM_Byte1_i, MeasureFSM_Byte0_i }),
.Y(DiffBA)
);
(* src = "../../verilog/sensorfsm.v:172" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/sensorfsm.v:172$66 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue = { MeasureFSM_Byte1_i, MeasureFSM_Byte0_i };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/adt7310.v:1" *)
module ADT7310(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, ADT7310CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, SPICounterPresetH_i, SPICounterPresetL_i, Threshold_i, PeriodCounterPreset_i, SensorValue_o, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/adt7310.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/adt7310.v:7" *)
input Enable_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPreset_i" *)
(* src = "../../verilog/adt7310.v:33" *)
input [15:0] PeriodCounterPreset_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/adt7310.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SPICounterPresetH_i" *)
(* src = "../../verilog/adt7310.v:27" *)
input [15:0] SPICounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SPICounterPresetL_i" *)
(* src = "../../verilog/adt7310.v:29" *)
input [15:0] SPICounterPresetL_i;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1 *)
(* src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/adt7310.v:13" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/adt7310.v:19" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/adt7310.v:35" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/adt7310.v:31" *)
input [15:0] Threshold_i;
(* src = "../../verilog/adt7310.v:60" *)
\$paramod\SPIFSM\SPPRWidth=4\SPRWidth=4\DataWidth=8 SPIFSM_1 (
.ADT7310CS_n_o(ADT7310CS_n_o),
.Byte0_o(SPIFSM_Byte0_s),
.Byte1_o(SPIFSM_Byte1_s),
.Clk_i(Clk_i),
.Done_o(SPIFSM_Done_s),
.ParamCounterPreset_i({ SPICounterPresetH_i, SPICounterPresetL_i }),
.Reset_n_i(Reset_n_i),
.SPI_Data_i(SPI_Data_i),
.SPI_Data_o(SPI_Data_o),
.SPI_FIFOEmpty_i(SPI_FIFOEmpty_i),
.SPI_FIFOFull_i(SPI_FIFOFull_i),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o),
.Start_i(SPIFSM_Start_s)
);
(* src = "../../verilog/adt7310.v:86" *)
\$paramod\SensorFSM\DataWidth=8 SensorFSM_1 (
.Clk_i(Clk_i),
.CpuIntr_o(CpuIntr_o),
.Enable_i(Enable_i),
.MeasureFSM_Byte0_i(SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i(SPIFSM_Byte1_s),
.MeasureFSM_Done_i(SPIFSM_Done_s),
.MeasureFSM_Start_o(SPIFSM_Start_s),
.ParamCounterPreset_i(PeriodCounterPreset_i),
.ParamThreshold_i(Threshold_i),
.Reset_n_i(Reset_n_i),
.SensorValue_o(SensorValue_o)
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
endmodule
|
/*888888888 .d88888b. 8888888b.
888 d88P" "Y88b 888 Y88b
888 888 888 888 888
888 888 888 888 d88P
888 888 888 8888888P"
888 888 888 888
888 Y88b. .d88P 888
888 "Y88888P" 8*/
/////////////////////////////////////////////////////////////////////
// In this TOP module, we create data, replacing data from from
// sensor, or other. These data are under the form of a counter
// to further on check more easily the integrity of the received
// data. We simply send counting data to the transmitting module
// (fifo_spi) at regular intervall.
//
// The trick here is that we have a spi block data signal that
// will in our case stop us from sending more data to the
// fifo_spi module. this signal is necesseray with dealing with
// the CC3200 TI wireless module, that sometime cannot accept to
// receive data. It force us, either to stop procucing data (that's
// what we are doing here) or to store the produced data to a memory
// before sending them later when the CC3200 will get "unstuck" and
// will again accept receiving data. the later option is to implement
// since it will bring much more flexibility to the system.
/////////////////////////////////////////////////////////////////////
module top_SRAM (
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [7:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO, // GPIO Connections
// SRAM
inout [15:0] SRAM_DQ, // Sram Data line
output [19:0] SRAM_ADDR, // Sram Address line
output SRAM_CE_N, SRAM_OE_N, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N // Sram controms
);
// State parameters
parameter
state_rst = 4'd0,
state_idle = 4'd1,
state_delay = 4'd2,
state_check_block = 4'd3,
state_start_send = 4'd4,
state_cnt_increase = 4'd5;
// Fifo filling parameter
parameter AVAIL = 21'b 0_1000_0000_0000_0000_0000;
parameter AVAIL_DIV = AVAIL/21'd18;
/*88888b. 8888888888 .d8888b. 888
888 "Y88b 888 d88P Y88b 888
888 888 888 888 888 888
888 888 8888888 888 888
888 888 888 888 888
888 888 888 888 888 888
888 .d88P 888 Y88b d88P 888
8888888P" 8888888888 "Y8888P" 888888*/
// general
wire clk;
wire rst_n;
wire locked;
wire [7:0] sum_SW;
wire [31:0] delay;
wire SW_17_debounced;
reg fifo_block_read;
// Pll
wire pll_in_c0;
wire pll_out_c0;
// Fifo spi
wire dout;
wire sck;
wire ss;
wire send_data;
wire cc3200_flow_ctrl_n;
wire fifo_busy;
wire fifo_full;
wire [31:0] din;
reg fifo_we;
wire [31:0] fifo_debug;
wire [21:0] available;
// Seven segment display
wire [4:0] number_0, number_1, number_2, number_3,
number_4, number_5, number_6, number_7;
// State Machine
wire [31:0] delay_cnt_plus_one;
wire [31:0] data_cnt_plus_one;
reg [31:0] delay_cnt;
reg [31:0] data_cnt;
reg [3:0] current_state, next_state;
/*8b d888 .d88888b. 8888888b. 888 888 888 8888888888
8888b d8888 d88P" "Y88b 888 "Y88b 888 888 888 888
88888b.d88888 888 888 888 888 888 888 888 888
888Y88888P888 888 888 888 888 888 888 888 8888888
888 Y888P 888 888 888 888 888 888 888 888 888
888 Y8P 888 888 888 888 888 888 888 888 888
888 " 888 Y88b. .d88P 888 .d88P Y88b. .d88P 888 888
888 888 "Y88888P" 8888888P" "Y88888P" 88888888 88888888*/
// deboucer for the SW17 switch
DeBounce DeBounce_i_0 (clk, rst_n, SW[17], SW_17_debounced);
// pll for 40 MHz clock (to get the 20 MHz SPI)
pll pll_0 (
.areset (!rst_n),
.inclk0 (pll_in_c0),
.c0 (pll_out_c0),
.locked (locked)
);
// Main module
fifo_spi_sram fifo_spi_i (
// common
.clk (clk),
.nrst (rst_n),
// Microcontroller block signal
.block (fifo_block_read),
// writting module (data and command)
.we (fifo_we),
.din (din),
.fifo_busy (fifo_busy),
.fifo_full (fifo_full),
// SPI
.dout (dout),
.sck (sck),
.ss (ss),
// SRAM
.fifo_SRAM_ADDR (SRAM_ADDR),
.fifo_SRAM_DQ (SRAM_DQ),
.fifo_SRAM_CE_N (SRAM_CE_N),
.fifo_SRAM_OE_N (SRAM_OE_N),
.fifo_SRAM_WE_N (SRAM_WE_N),
.fifo_SRAM_LB_N (SRAM_LB_N),
.fifo_SRAM_UB_N (SRAM_UB_N),
// debug
.available (available),
.debug (fifo_debug)
);
//Seven segment display
SSD seven_seg_0 (number_0, HEX0);
SSD seven_seg_1 (number_1, HEX1);
SSD seven_seg_2 (number_2, HEX2);
SSD seven_seg_3 (number_3, HEX3);
SSD seven_seg_4 (number_4, HEX4);
SSD seven_seg_5 (number_5, HEX5);
SSD seven_seg_6 (number_6, HEX6);
SSD seven_seg_7 (number_7, HEX7);
/*888 .d8888b. .d8888b. 8888888 .d8888b. 888b 888
d88888 d88P Y88b d88P Y88b 888 d88P Y88b 8888b 888
d88P888 Y88b. Y88b. 888 888 888 88888b 888
d88P 888 "Y888b. "Y888b. 888 888 888Y88b 888
d88P 888 "Y88b. "Y88b. 888 888 88888 888 Y88b888
d88P 888 "888 "888 888 888 888 888 Y88888
d8888888888 Y88b d88P Y88b d88P 888 Y88b d88P 888 Y8888
d88P 888 "Y8888P" "Y8888P" 8888888 "Y8888P88 888 Y8*/
// general
assign sum_SW = SW[0] + SW[1] + SW[2] + SW[3] + SW[4] + SW[5] +
SW[6] + SW[7] + SW[8] + SW[9] + SW[10] + SW[11];
assign delay = 32'd128 + (1 << sum_SW);
// sum_SW == 12 ==> 0.3 Mbits/sec
// sum_SW == 11 ==> 0.7 Mbits/sec
// sum_SW == 10 ==> 1.3 Mbits/sec
// sum_SW == 9 ==> 2.5 Mbits/sec
// sum_SW == 8 ==> 4.1 Mbits/sec
// sum_SW == 7 ==> 6.1 Mbits/sec
// sum_SW == 6 ==> 8.2 Mbits/sec
// pll
assign pll_in_c0 = CLOCK_50;
// assign clk = CLOCK_50;
assign clk = pll_out_c0;
// Fifo spi
assign din = data_cnt;
assign rst_n = KEY[0];
assign send_data = KEY[1];
assign GPIO[0] = sck;
assign GPIO[1] = dout;
assign GPIO[2] = ss;
// debug
assign GPIO[6] = sck;
assign GPIO[7] = dout;
assign GPIO[8] = ss;
assign GPIO[9] = fifo_debug[8];
assign GPIO[10] = fifo_debug[9];
assign GPIO[11] = fifo_debug[10];
assign GPIO[5:3] = 0;
assign GPIO[35:12] = {23{1'bz}}; // High impedance for the inputs
// Switch
// assign cc3200_flow_ctrl_n = SW_17_debounced; // manual spi_block
// CC3200
assign cc3200_flow_ctrl_n = GPIO[35]; // CC3200 input
// State Machine
assign delay_cnt_plus_one = delay_cnt + 32'b1;
assign data_cnt_plus_one = data_cnt + 32'b1;
// Seven segment display
assign number_0 = {1'b0, fifo_debug[3:0]};
assign number_1 = {1'b0, fifo_debug[7:4]};
assign number_2 = {1'b0, current_state};
assign number_3 = 5'h1_0;
assign number_4 = 5'h1_0;
assign number_5 = 5'h1_0;
assign number_6 = 5'h1_0;
assign number_7 = 5'h1_0;
// LEDS
assign LEDG[0] = fifo_busy;
assign LEDG[1] = fifo_full;
assign LEDG[7:2] = 0;
// Display the filling of the fifo on LEDs
assign LEDR[0] = available > (AVAIL_DIV * 21'd1) ? 1'b1 : 1'b0;
assign LEDR[1] = available > (AVAIL_DIV * 21'd2) ? 1'b1 : 1'b0;
assign LEDR[2] = available > (AVAIL_DIV * 21'd3) ? 1'b1 : 1'b0;
assign LEDR[3] = available > (AVAIL_DIV * 21'd4) ? 1'b1 : 1'b0;
assign LEDR[4] = available > (AVAIL_DIV * 21'd5) ? 1'b1 : 1'b0;
assign LEDR[5] = available > (AVAIL_DIV * 21'd6) ? 1'b1 : 1'b0;
assign LEDR[6] = available > (AVAIL_DIV * 21'd7) ? 1'b1 : 1'b0;
assign LEDR[7] = available > (AVAIL_DIV * 21'd8) ? 1'b1 : 1'b0;
assign LEDR[8] = available > (AVAIL_DIV * 21'd9) ? 1'b1 : 1'b0;
assign LEDR[9] = available > (AVAIL_DIV * 21'd10) ? 1'b1 : 1'b0;
assign LEDR[10] = available > (AVAIL_DIV * 21'd11) ? 1'b1 : 1'b0;
assign LEDR[11] = available > (AVAIL_DIV * 21'd12) ? 1'b1 : 1'b0;
assign LEDR[12] = available > (AVAIL_DIV * 21'd13) ? 1'b1 : 1'b0;
assign LEDR[13] = available > (AVAIL_DIV * 21'd14) ? 1'b1 : 1'b0;
assign LEDR[14] = available > (AVAIL_DIV * 21'd15) ? 1'b1 : 1'b0;
assign LEDR[15] = available > (AVAIL_DIV * 21'd16) ? 1'b1 : 1'b0;
assign LEDR[16] = available > (AVAIL_DIV * 21'd17) ? 1'b1 : 1'b0;
assign LEDR[17] = available > (AVAIL_DIV * 21'd18) ? 1'b1 : 1'b0;
/*88888b. 8888888888 .d8888b.
888 Y88b 888 d88P Y88b
888 888 888 888 888
888 d88P 8888888 888
8888888P" 888 888 88888
888 T88b 888 888 888
888 T88b 888 Y88b d88P
888 T88b 8888888888 "Y8888P*/
// fifo_block_read reg
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
fifo_block_read <= 0;
end
else begin
fifo_block_read <= cc3200_flow_ctrl_n;
end
end
// Fifo_we reg
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
fifo_we <= 0;
end
else begin
if (current_state == state_start_send)
fifo_we <= 1'b1;
else
fifo_we <= 1'b0;
end
end
// Delay and Data counters
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
delay_cnt <= 0;
data_cnt <= 0;
end
else begin
case (current_state)
state_idle : begin
delay_cnt <= 0;
data_cnt <= data_cnt;
end
state_delay : begin
delay_cnt <= delay_cnt_plus_one;
data_cnt <= data_cnt;
end
state_cnt_increase : begin
delay_cnt <= delay_cnt;
data_cnt <= data_cnt_plus_one;
end
default : begin
delay_cnt <= delay_cnt;
data_cnt <= data_cnt;
end
endcase
end
end
/*88888888 .d8888b. 888b d888
888 d88P Y88b 8888b d8888
888 Y88b. 88888b.d88888
8888888 "Y888b. 888Y88888P888
888 "Y88b. 888 Y888P 888
888 "888 888 Y8P 888
888 Y88b d88P 888 " 888
888 "Y8888P" 888 8*/
// Registers flops :
// State register
// Delay counter register (to create sending time interval)
// Data counter register (to create the fake data sent to fifo_spi)
always @ (negedge clk or negedge rst_n) begin
if (!rst_n)
current_state <= state_rst;
else
current_state <= next_state;
end
// FSM combinationnal in/out
// Used to send data regularly to the fifo_spi module
always @ (*) begin
next_state = current_state;
case (current_state)
state_rst : begin // 0
if (!send_data) begin
next_state = state_idle;
end
end
// Step used to reinit the counter register
state_idle : begin // 1
next_state = state_delay;
end
// Check: is this the time to send a 32 bit data to fifo_spi ?
state_delay : begin // 2
if (delay_cnt >= delay) begin
next_state = state_check_block;
end
end
// Check: is the SPI blocked (CC3200 TCP conn slow) ?
state_check_block : begin // 3
if ( (!fifo_busy) && (!fifo_full)) begin
next_state = state_start_send;
end
end
state_start_send : begin // 4
next_state = state_cnt_increase;
end
state_cnt_increase : begin // 5
next_state = state_idle;
end
default : next_state = state_rst;
endcase
end
endmodule
|
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//************************************************************//
// - a lot work in progress, many thing are useless
// TODO: clean this up and make it more general
// TODO: add comments
//************************************************************//
//add err input
module SSDS_spoof(
clk,
cyc,
ack,
we,
err,
clk_count,
data_out,
reset
);
input clk;
input cyc;
input ack;
input we;
input err;
input [31:0] clk_count;
input reset;
output [31:0] data_out;
wire [31:0] clk_count;
wire cyc;
wire ack;
wire we;
wire clk;
wire reset;
wire err;
reg [31:0] data_out;
//HLSM registers
reg [31:0] CountRead;
reg [31:0] CountRead_Next;
reg [31:0] CountWrite;
reg [31:0] CountWrite_Next;
reg [31:0] Clk_Counter;
reg [31:0] Clk_Counter_Next;
reg [3:0] HoldCycles;
reg [3:0] HoldCycles_Next;
//state registers
reg [2:0] CurrentState;
reg [2:0] NextState;
//FSM states, Placeholder to implement safe fsm
localparam STATE_Initial = 3'd0,
STATE_1 = 3'd1,
STATE_2 = 3'd2,
STATE_3 = 3'd3,
STATE_4 = 3'd4,
STATE_5_Placeholder = 3'd5,
STATE_6_Placeholder = 3'd6,
STATE_7_Placeholder = 3'd7;
//number of clock cycles to hold every output;
localparam OUTPUT_TIME = 4'd3;
//synchronous state and registers transition
always@ (posedge clk)
begin: STATE_TRANS
if(reset == 1)
begin
CurrentState <= STATE_Initial;
Clk_Counter <= clk_count;
CountRead <= 0;
CountWrite <= 0;
HoldCycles <= 0;
HoldCycles_Next <= 0;
CountRead_Next <= 0;
CountWrite_Next <= 0;
end
else
begin
CurrentState <= NextState;
Clk_Counter <= Clk_Counter_Next;
HoldCycles <= HoldCycles_Next;
CountRead <= CountRead_Next;
CountWrite <= CountWrite_Next;
end
end
//output logic (synchronous), tri-state when output is not ready
always@ (posedge clk)
begin: OUTPUT_LOGIC
if(reset == 1)
data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
else
begin
case(CurrentState)
STATE_Initial: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
STATE_1: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
STATE_2: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
STATE_3: data_out<=CountRead;
STATE_4: data_out<=CountWrite;
STATE_5_Placeholder: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
STATE_6_Placeholder: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
STATE_7_Placeholder: data_out<=32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
end
end
//conditional state transition combinational logic
always@ (*)
begin
if(Clk_Counter == 32'b00000000000000000000000000000000) //count stop - unconditional jump to STATE_3
begin
NextState = STATE_3;
Clk_Counter_Next <= clk_count; //reset count
HoldCycles_Next <= OUTPUT_TIME;
end
else
begin
case(CurrentState)
STATE_Initial: begin
Clk_Counter_Next <= Clk_Counter-1;
if(cyc)
begin
if(we) NextState <= STATE_1;
else NextState <= STATE_2;
end
else NextState <= STATE_Initial;
end
STATE_1: begin
Clk_Counter_Next <= Clk_Counter-1;
if(err)
begin
NextState <= STATE_Initial;
//add err count
end
else
begin
if(!cyc)
begin
NextState <= STATE_Initial;
CountRead_Next <= CountRead+1;
end
end
end
STATE_2: begin
Clk_Counter_Next <= Clk_Counter-1;
if(err)
begin
NextState <= STATE_Initial;
//add err count
end
else
begin
if(!cyc)
begin
NextState <= STATE_Initial;
CountWrite_Next <= CountWrite+1;
end
end
end
STATE_3: begin
if(HoldCycles == 4'b0000)
begin
NextState <= STATE_4;
HoldCycles_Next <= OUTPUT_TIME;
end
else
begin
NextState <= STATE_3;
HoldCycles_Next <= HoldCycles-1;
end
end
STATE_4: begin
if(HoldCycles == 4'b0000)
begin
NextState <= STATE_Initial;
HoldCycles_Next <= OUTPUT_TIME;
CountRead_Next <= 0;
CountWrite_Next <= 0;
Clk_Counter_Next <= clk_count;
end
else
begin
NextState <= STATE_4;
HoldCycles_Next <= HoldCycles-1;
end
end
STATE_5_Placeholder: begin
end
STATE_6_Placeholder: begin
end
STATE_7_Placeholder: begin
end
endcase
end
end
endmodule
|
module uart(
// Outputs
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
// Inputs
input uart_wr_i, // Raise to transmit byte
input [7:0]uart_dat_i, // 8-bit data
input sys_clk_i, // System clock, 68 MHz
input sys_rst_i // System reset
);
reg [3:0] bitcount;
reg [8:0] shifter;
assign uart_busy = |bitcount[3:1];
assign sending = |bitcount;
// sys_clk_i is 50MHz. We want a 115200Hz clock
reg [28:0] d;
wire [28:0] dInc = d[28] ? (115200) : (115200 - 50000000);
wire [28:0] dNxt = d + dInc;
always @(posedge sys_clk_i)
begin
d = dNxt;
end
wire ser_clk = ~d[28]; // this is the 115200 Hz clock
always @(posedge sys_clk_i)
begin
if (sys_rst_i) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
// just got a new byte
if (uart_wr_i & ~uart_busy) begin
shifter <= { uart_dat_i[7:0], 1'h0 };
bitcount <= (1 + 8 + 2);
end
if (sending & ser_clk) begin
{ shifter, uart_tx } <= { 1'h1, shifter };
bitcount <= bitcount - 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:52 06/07/2015
// Design Name:
// Module Name: UART_LOOPBACK
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_LOOPBACK(
// UART USB ports
input sys_clk, // 27 MHZ on SP605
output CTS,// I am ready to receive data
input RTS, // USB Clear to send
output TX, // Output to USB
input RX, // Input to USB
output [3:0] leds
);
// LOOPBACK WIRES
wire [7:0] TxD_par;
wire TxD_ready;
assign leds = {CTS,RTS,TxD_par[1:0]};
UART_IP uartip(
// UART USB ports
.sys_clk(sys_clk), // 27 MHZ on SP605
.RTS(RTS),// I am ready to receive data
.CTS(CTS), // USB Clear to send
.TX(TX), // Output to USB
.RX(RX), // Input to USB
// FPGA
.TxD_par(TxD_par),
.TxD_ready(TxD_ready),
.RxD_par(TxD_par),
.RxD_start(TxD_ready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_SYMBOL_V
|
//--------------------------------------------------------------------------------
// sampler.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Produces samples from input applying a programmable divider to the clock.
// Sampling rate can be calculated by:
//
// r = f / (d + 1)
//
// Where r is the sampling rate, f is the clock frequency and d is the value
// programmed into the divider register.
//
// As of version 0.6 sampling on an extClock_mode clock is also supported. If extclock_mode
// is set '1', the extClock_mode clock will be used to sample data. (Divider is
// ignored for this.)
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
module sampler #(
parameter integer DW = 32, // data width
parameter integer CW = 24 // counter width
)(
// system signas
input wire clk, // clock
input wire rst, // reset
// configuration/control signals
input wire extClock_mode, // clock selection
input wire wrDivider, // write divider register
input wire [CW-1:0] config_data, // configuration data
// input stream
input wire sti_valid, // sti_data is valid
input wire [DW-1:0] sti_data, // 32 input channels
// output stream
output reg sto_valid, // new sample ready
output reg [DW-1:0] sto_data, // sampled data
output reg ready50
);
//
// Registers...
//
reg next_sto_valid;
reg [DW-1:0] next_sto_data;
reg [CW-1:0] divider, next_divider;
reg [CW-1:0] counter, next_counter; // Made counter decrementing. Better synth.
wire counter_zero = ~|counter;
//
// Generate slow sample reference...
//
initial
begin
divider = 0;
counter = 0;
sto_valid = 0;
sto_data = 0;
end
always @ (posedge clk)
begin
divider <= next_divider;
counter <= next_counter;
sto_valid <= next_sto_valid;
sto_data <= next_sto_data;
end
always @*
begin
next_divider = divider;
next_counter = counter;
next_sto_valid = 1'b0;
next_sto_data = sto_data;
if (extClock_mode)
begin
next_sto_valid = sti_valid;
next_sto_data = sti_data;
end
else if (sti_valid && counter_zero)
begin
next_sto_valid = 1'b1;
next_sto_data = sti_data;
end
//
// Manage counter divider for internal clock sampling mode...
//
if (wrDivider)
begin
next_divider = config_data[CW-1:0];
next_counter = next_divider;
next_sto_valid = 1'b0; // reset
end
else if (sti_valid)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
//
// Generate ready50 50% duty cycle sample signal...
//
always @(posedge clk)
begin
if (wrDivider)
ready50 <= 1'b0; // reset
else if (counter_zero)
ready50 <= 1'b1;
else if (counter == divider[CW-1:1])
ready50 <= 1'b0;
end
endmodule
|
//======================================
//
// intra mode desicion fetch
// luyanheng
//
//======================================
module md_fetch(
clk,
rstn,
enable,
cnt,
sram_rdata,
x1,
x2,
x3,
sram_raddr,
sram_read
);
input clk;
input rstn;
input enable;
input [5:0] cnt;
input [31:0] sram_rdata;
output [23:0] x1;
output [15:0] x2;
output [23:0] x3;
output sram_read;
output [3:0] sram_raddr;
reg [23:0] x1;
reg [15:0] x2;
reg [23:0] x3;
reg [31:0] tmp1;
reg [31:0] tmp2;
reg [31:0] tmp3;
reg [31:0] tmp4;
reg [31:0] tmp5;
reg [31:0] tmp6;
reg sram_read;
reg [3:0] sram_raddr;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
tmp1<='d0;
tmp2<='d0;
tmp3<='d0;
tmp4<='d0;
tmp5<='d0;
tmp6<='d0;
end
else
case(cnt)
'd2:begin
tmp1<=sram_rdata;
end
'd3:begin
tmp2<=sram_rdata;
end
'd4:begin
tmp3<=sram_rdata;
end
'd5:begin
tmp4<=sram_rdata;
end
'd6:begin
tmp5<=sram_rdata;
end
'd7:begin
tmp6<=sram_rdata;
end
'd9:begin
tmp1<=tmp2;
tmp2<=tmp3;
tmp3<=sram_rdata;
end
'd11:begin
tmp4<=tmp5;
tmp5<=tmp6;
tmp6<=sram_rdata;
end
'd15:begin
tmp1<=tmp2;
tmp2<=tmp3;
tmp3<=sram_rdata;
end
'd17:begin
tmp4<=tmp5;
tmp5<=tmp6;
tmp6<=sram_rdata;
end
'd21:begin
tmp1<=tmp2;
tmp2<=tmp3;
tmp3<=sram_rdata;
end
'd23:begin
tmp4<=tmp5;
tmp5<=tmp6;
tmp6<=sram_rdata;
end
'd27:begin
tmp1<=tmp2;
tmp2<=tmp3;
tmp3<=sram_rdata;
end
'd29:begin
tmp4<=tmp5;
tmp5<=tmp6;
tmp6<=sram_rdata;
end
'd33:begin
tmp1<=tmp2;
tmp2<=tmp3;
tmp3<=sram_rdata;
end
'd35:begin
tmp4<=tmp5;
tmp5<=tmp6;
tmp6<=sram_rdata;
end
default:begin
tmp1<=tmp1;
tmp2<=tmp2;
tmp3<=tmp3;
tmp4<=tmp4;
tmp5<=tmp5;
tmp6<=tmp6;
end
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
begin
sram_read <= 1'b0;
sram_raddr <= 'd0;
end
else if(enable)
case(cnt)
'd0:begin
sram_read <= 1'b1;
sram_raddr <= 'd0;
end
'd1:begin
sram_read <= 1'b1;
sram_raddr <= 'd2;
end
'd2:begin
sram_read <= 1'b1;
sram_raddr <= 'd4;
end
'd3:begin
sram_read <= 1'b1;
sram_raddr <= 'd1;
end
'd4:begin
sram_read <= 1'b1;
sram_raddr <= 'd3;
end
'd5:begin
sram_read <= 1'b1;
sram_raddr <= 'd5;
end
'd7:begin
sram_read <= 1'b1;
sram_raddr <= 'd6;
end
'd9:begin
sram_read <= 1'b1;
sram_raddr <= 'd7;
end
'd13:begin
sram_read <= 1'b1;
sram_raddr <= 'd8;
end
'd15:begin
sram_read <= 1'b1;
sram_raddr <= 'd9;
end
'd19:begin
sram_read <= 1'b1;
sram_raddr <= 'd10;
end
'd21:begin
sram_read <= 1'b1;
sram_raddr <= 'd11;
end
'd25:begin
sram_read <= 1'b1;
sram_raddr <= 'd12;
end
'd27:begin
sram_read <= 1'b1;
sram_raddr <= 'd13;
end
'd31:begin
sram_read <= 1'b1;
sram_raddr <= 'd14;
end
'd33:begin
sram_read <= 1'b1;
sram_raddr <= 'd15;
end
default:begin
sram_read <= 'b0;
sram_raddr <= 'd0;
end
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
begin
x1 <= 'd0;
x2 <= 'd0;
x3 <= 'd0;
end
else
case(cnt)
'd5,'d11,'d17,'d23,'d29,'d35: begin
x1 <= tmp1[31:8];
x2 <= {tmp2[31:24],tmp2[15:8]};
x3 <= tmp3[31:8];
end
'd6,'d12,'d18,'d24,'d30,'d36: begin
x1 <= tmp1[23:0];
x2 <= {tmp2[23:16],tmp2[7:0]};
x3 <= tmp3[23:0];
end
'd7: begin
x1 <= {tmp1[15:0],tmp4[31:24]};
x2 <= {tmp2[15:8],tmp5[31:24]};
x3 <= {tmp3[15:0],sram_rdata[31:24]};
end
'd13,'d19,'d25,'d31,'d37: begin
x1 <= {tmp1[15:0],tmp4[31:24]};
x2 <= {tmp2[15:8],tmp5[31:24]};
x3 <= {tmp3[15:0],tmp6[31:24]};//tmp
end
'd8,'d14,'d20,'d26,'d32,'d38: begin
x1 <= {tmp1[7:0],tmp4[31:16]};
x2 <= {tmp2[7:0],tmp5[23:16]};
x3 <= {tmp3[7:0],tmp6[31:16]};
end
'd9,'d15,'d21,'d27,'d33,'d39: begin
x1 <= tmp4[31:8];
x2 <= {tmp5[31:24],tmp5[15:8]};
x3 <= tmp6[31:8];
end
'd10,'d16,'d22,'d28,'d34,'d40: begin
x1 <= tmp4[23:0];
x2 <= {tmp5[23:16],tmp5[7:0]};
x3 <= tmp6[23:0];
end
default: begin
x1 <= 'd0;
x2 <= 'd0;
x3 <= 'd0;
end
endcase
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
// Date : Tue Aug 15 10:43:42 2017
// Host : ACER-BLUES running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/fifo_bt_txd/fifo_bt_txd_sim_netlist.v
// Design : fifo_bt_txd
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_bt_txd,fifo_generator_v13_1_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_4,Vivado 2017.1" *)
(* NotValidForBitStream *)
module fifo_bt_txd
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [7:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [7:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "8" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "1kx18" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1022" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_bt_txd_fifo_generator_v13_1_4 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module fifo_bt_txd_blk_mem_gen_generic_cstr
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_bt_txd_blk_mem_gen_prim_width
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_bt_txd_blk_mem_gen_prim_wrapper
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 ;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({Q,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({\gc0.count_d1_reg[9] ,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,din[7:4],1'b0,1'b0,1'b0,1'b0,din[3:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19 ,D[7:4],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27 ,D[3:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 }),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(SR),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module fifo_bt_txd_blk_mem_gen_top
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_6" *)
module fifo_bt_txd_blk_mem_gen_v8_3_6
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.D(D),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_6_synth" *)
module fifo_bt_txd_blk_mem_gen_v8_3_6_synth
(D,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din);
output [7:0]D;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
wire [7:0]D;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.D(D),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module fifo_bt_txd_clk_x_pntrs
(v1_reg,
v1_reg_0,
RD_PNTR_WR,
Q,
\gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [9:0]RD_PNTR_WR;
input [9:0]Q;
input [9:0]\gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]AR;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [8:0]bin2gray;
wire [9:0]\gc0.count_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ;
wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;
wire [7:0]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire p_0_out;
wire [9:0]p_22_out;
wire [9:0]p_3_out;
wire [9:0]p_4_out;
wire [9:9]p_5_out;
wire [9:9]p_6_out;
wire rd_clk;
wire [9:0]rd_pntr_gc;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire [9:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(p_22_out[0]),
.I1(Q[0]),
.I2(p_22_out[1]),
.I3(Q[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(p_22_out[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(p_22_out[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(p_22_out[2]),
.I1(Q[2]),
.I2(p_22_out[3]),
.I3(Q[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(p_22_out[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(p_22_out[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(p_22_out[4]),
.I1(Q[4]),
.I2(p_22_out[5]),
.I3(Q[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(p_22_out[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(p_22_out[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(p_22_out[6]),
.I1(Q[6]),
.I2(p_22_out[7]),
.I3(Q[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(p_22_out[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(p_22_out[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(p_22_out[8]),
.I1(Q[8]),
.I2(p_22_out[9]),
.I3(Q[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(p_22_out[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(p_22_out[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg_0[4]));
fifo_bt_txd_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
fifo_bt_txd_synchronizer_ff__parameterized0_6 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
fifo_bt_txd_synchronizer_ff__parameterized0_7 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\gnxpm_cdc.wr_pntr_bin_reg[8] ({p_0_out,gray2bin}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_5_out),
.rd_clk(rd_clk));
fifo_bt_txd_synchronizer_ff__parameterized0_8 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.\gnxpm_cdc.rd_pntr_bin_reg[8] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[0]),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[4]),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[5]),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[6]),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[7]),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_5_out),
.Q(p_22_out[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(bin2gray[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(bin2gray[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(bin2gray[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(bin2gray[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(bin2gray[7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(bin2gray[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_bt_txd_compare
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_bt_txd_compare_3
(ram_full_fb_i_reg,
v1_reg_0,
wr_rst_busy,
out,
wr_en,
comp1);
output ram_full_fb_i_reg;
input [4:0]v1_reg_0;
input wr_rst_busy;
input out;
input wr_en;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire comp2;
wire out;
wire ram_full_fb_i_reg;
wire [4:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(wr_rst_busy),
.I1(comp2),
.I2(out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_bt_txd_compare_4
(ram_empty_fb_i_reg,
v1_reg,
out,
rd_en,
\gpregsm1.curr_fwft_state_reg[1] ,
comp1);
output ram_empty_fb_i_reg;
input [4:0]v1_reg;
input out;
input rd_en;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT6 #(
.INIT(64'hBABBBBBBAAAAAAAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(out),
.I2(rd_en),
.I3(\gpregsm1.curr_fwft_state_reg[1] [1]),
.I4(\gpregsm1.curr_fwft_state_reg[1] [0]),
.I5(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_bt_txd_compare_5
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module fifo_bt_txd_fifo_generator_ramfifo
(wr_rst_busy,
empty,
full,
dout,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output empty;
output full;
output [7:0]dout;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire [4:0]\gras.rsts/c0/v1_reg ;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [9:0]p_0_out;
wire [9:0]p_12_out;
wire [9:0]p_23_out;
wire p_5_out;
wire rd_clk;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
fifo_bt_txd_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.Q(p_0_out),
.RD_PNTR_WR(p_23_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.rd_clk(rd_clk),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ),
.wr_clk(wr_clk));
fifo_bt_txd_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (p_0_out),
.E(p_5_out),
.Q(rd_pntr_plus1),
.empty(empty),
.out({rd_rst_i[2],rd_rst_i[0]}),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ));
fifo_bt_txd_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.Q(p_12_out),
.RD_PNTR_WR(p_23_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.full(full),
.out(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_bt_txd_memory \gntv_or_sync_fifo.mem
(.E(p_5_out),
.Q(p_12_out),
.SR(rd_rst_i[0]),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_bt_txd_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.rd_clk(rd_clk),
.rst(rst),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module fifo_bt_txd_fifo_generator_top
(wr_rst_busy,
empty,
full,
dout,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output empty;
output full;
output [7:0]dout;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_bt_txd_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "8" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "1kx18" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1022" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_4" *)
module fifo_bt_txd_fifo_generator_v13_1_4
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [7:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [7:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_bt_txd_fifo_generator_v13_1_4_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_4_synth" *)
module fifo_bt_txd_fifo_generator_v13_1_4_synth
(wr_rst_busy,
empty,
full,
dout,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output empty;
output full;
output [7:0]dout;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_bt_txd_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "memory" *)
module fifo_bt_txd_memory
(dout,
wr_clk,
rd_clk,
WEA,
tmp_ram_rd_en,
SR,
Q,
\gc0.count_d1_reg[9] ,
din,
E);
output [7:0]dout;
input wr_clk;
input rd_clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]SR;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [7:0]din;
input [0:0]E;
wire [0:0]E;
wire [9:0]Q;
wire [0:0]SR;
wire [0:0]WEA;
wire [7:0]din;
wire [7:0]dout;
wire [7:0]doutb;
wire [9:0]\gc0.count_d1_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_bt_txd_blk_mem_gen_v8_3_6 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.Q(Q),
.SR(SR),
.WEA(WEA),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(rd_clk),
.CE(E),
.D(doutb[0]),
.Q(dout[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(rd_clk),
.CE(E),
.D(doutb[1]),
.Q(dout[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(rd_clk),
.CE(E),
.D(doutb[2]),
.Q(dout[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(rd_clk),
.CE(E),
.D(doutb[3]),
.Q(dout[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(rd_clk),
.CE(E),
.D(doutb[4]),
.Q(dout[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(rd_clk),
.CE(E),
.D(doutb[5]),
.Q(dout[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(rd_clk),
.CE(E),
.D(doutb[6]),
.Q(dout[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(rd_clk),
.CE(E),
.D(doutb[7]),
.Q(dout[7]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module fifo_bt_txd_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
E,
rd_clk,
out);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
input [0:0]E;
input rd_clk;
input [0:0]out;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire [0:0]E;
wire [9:0]Q;
wire \gc0.count[9]_i_2_n_0 ;
wire [0:0]out;
wire [9:0]plusOp;
wire rd_clk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(out),
.D(plusOp[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module fifo_bt_txd_rd_fwft
(out,
empty,
tmp_ram_rd_en,
E,
\gc0.count_d1_reg[9] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
ram_empty_fb_i_reg);
output [1:0]out;
output empty;
output tmp_ram_rd_en;
output [0:0]E;
output [0:0]\gc0.count_d1_reg[9] ;
input rd_clk;
input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input ram_empty_fb_i_reg;
wire [0:0]E;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gc0.count_d1_reg[9] ;
wire [1:0]next_fwft_state;
wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
(* DONT_TOUCH *) wire user_valid;
assign empty = empty_fwft_i;
assign out[1:0] = curr_fwft_state;
LUT5 #(
.INIT(32'hBABBBBBB))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2
(.I0(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.I3(curr_fwft_state[1]),
.I4(curr_fwft_state[0]),
.O(tmp_ram_rd_en));
LUT5 #(
.INIT(32'hFFCB8000))
aempty_fwft_fb_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[0]),
.I2(curr_fwft_state[1]),
.I3(ram_empty_fb_i_reg),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hF320))
empty_fwft_fb_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(empty_fwft_fb_i),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hF320))
empty_fwft_fb_o_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(empty_fwft_fb_o_i),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h4555))
\gc0.count_d1[9]_i_1
(.I0(ram_empty_fb_i_reg),
.I1(rd_en),
.I2(curr_fwft_state[1]),
.I3(curr_fwft_state[0]),
.O(\gc0.count_d1_reg[9] ));
LUT3 #(
.INIT(8'hA2))
\goreg_bm.dout_i[7]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.O(E));
LUT3 #(
.INIT(8'hBA))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[1]),
.I1(rd_en),
.I2(curr_fwft_state[0]),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[1]),
.I1(rd_en),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.D(next_fwft_state[0]),
.Q(user_valid));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module fifo_bt_txd_rd_logic
(empty,
Q,
tmp_ram_rd_en,
E,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ,
v1_reg,
v1_reg_0,
rd_clk,
out,
rd_en);
output empty;
output [9:0]Q;
output tmp_ram_rd_en;
output [0:0]E;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [1:0]out;
input rd_en;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ;
wire [0:0]E;
wire [9:0]Q;
wire empty;
wire \gr1.gr1_int.rfwft_n_0 ;
wire [1:0]out;
wire [0:0]p_0_in;
wire p_2_out;
wire p_7_out;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
fifo_bt_txd_rd_fwft \gr1.gr1_int.rfwft
(.E(E),
.empty(empty),
.\gc0.count_d1_reg[9] (p_7_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out),
.out({\gr1.gr1_int.rfwft_n_0 ,p_0_in}),
.ram_empty_fb_i_reg(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_bt_txd_rd_status_flags_as \gras.rsts
(.\gpregsm1.curr_fwft_state_reg[1] ({\gr1.gr1_int.rfwft_n_0 ,p_0_in}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0));
fifo_bt_txd_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram ),
.E(p_7_out),
.Q(Q),
.out(out[1]),
.rd_clk(rd_clk));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module fifo_bt_txd_rd_status_flags_as
(out,
v1_reg,
v1_reg_0,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
\gpregsm1.curr_fwft_state_reg[1] );
output out;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire c0_n_0;
wire comp1;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
assign out = ram_empty_fb_i;
fifo_bt_txd_compare_4 c0
(.comp1(comp1),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.out(ram_empty_fb_i),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg));
fifo_bt_txd_compare_5 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module fifo_bt_txd_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
rd_clk,
wr_clk,
rst);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
input rd_clk;
input wr_clk;
input rst;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire rd_clk;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
fifo_bt_txd_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
fifo_bt_txd_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
fifo_bt_txd_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
fifo_bt_txd_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff__parameterized0_6
(D,
Q,
wr_clk,
AR);
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff__parameterized0_7
(out,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_bt_txd_synchronizer_ff__parameterized0_8
(out,
\gnxpm_cdc.rd_pntr_bin_reg[8] ,
D,
wr_clk,
AR);
output [0:0]out;
output [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
input [9:0]D;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module fifo_bt_txd_wr_bin_cntr
(v1_reg,
v1_reg_0,
Q,
RD_PNTR_WR,
E,
wr_clk,
AR);
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [9:0]Q;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]p_13_out;
wire [9:0]plusOp__0;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire [9:0]wr_pntr_plus2;
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[2]),
.I3(wr_pntr_plus2[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(wr_pntr_plus2[2]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[3]),
.I4(wr_pntr_plus2[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(wr_pntr_plus2[3]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(wr_pntr_plus2[2]),
.I4(wr_pntr_plus2[4]),
.I5(wr_pntr_plus2[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.I2(wr_pntr_plus2[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[8]_i_1
(.I0(wr_pntr_plus2[6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(wr_pntr_plus2[7]),
.I3(wr_pntr_plus2[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[9]_i_1
(.I0(wr_pntr_plus2[7]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(wr_pntr_plus2[6]),
.I3(wr_pntr_plus2[8]),
.I4(wr_pntr_plus2[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gic0.gc0.count[9]_i_2
(.I0(wr_pntr_plus2[5]),
.I1(wr_pntr_plus2[3]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[0]),
.I4(wr_pntr_plus2[2]),
.I5(wr_pntr_plus2[4]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(AR),
.Q(p_13_out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[1]),
.Q(p_13_out[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[2]),
.Q(p_13_out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[3]),
.Q(p_13_out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[4]),
.Q(p_13_out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[5]),
.Q(p_13_out[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[6]),
.Q(p_13_out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[7]),
.Q(p_13_out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[8]),
.Q(p_13_out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[9]),
.Q(p_13_out[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(AR),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(wr_pntr_plus2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(wr_pntr_plus2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(wr_pntr_plus2[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(wr_pntr_plus2[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(wr_pntr_plus2[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(wr_pntr_plus2[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(wr_pntr_plus2[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_13_out[0]),
.I1(RD_PNTR_WR[0]),
.I2(p_13_out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(wr_pntr_plus2[0]),
.I1(RD_PNTR_WR[0]),
.I2(wr_pntr_plus2[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_13_out[2]),
.I1(RD_PNTR_WR[2]),
.I2(p_13_out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(wr_pntr_plus2[2]),
.I1(RD_PNTR_WR[2]),
.I2(wr_pntr_plus2[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_13_out[4]),
.I1(RD_PNTR_WR[4]),
.I2(p_13_out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(wr_pntr_plus2[4]),
.I1(RD_PNTR_WR[4]),
.I2(wr_pntr_plus2[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_13_out[6]),
.I1(RD_PNTR_WR[6]),
.I2(p_13_out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(wr_pntr_plus2[6]),
.I1(RD_PNTR_WR[6]),
.I2(wr_pntr_plus2[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_13_out[8]),
.I1(RD_PNTR_WR[8]),
.I2(p_13_out[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(wr_pntr_plus2[8]),
.I1(RD_PNTR_WR[8]),
.I2(wr_pntr_plus2[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg_0[4]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module fifo_bt_txd_wr_logic
(full,
WEA,
Q,
wr_clk,
out,
wr_en,
AR,
RD_PNTR_WR,
wr_rst_busy);
output full;
output [0:0]WEA;
output [9:0]Q;
input wr_clk;
input out;
input wr_en;
input [0:0]AR;
input [9:0]RD_PNTR_WR;
input wr_rst_busy;
wire [0:0]AR;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [0:0]WEA;
wire [4:0]\c1/v1_reg ;
wire [4:0]\c2/v1_reg ;
wire full;
wire out;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_bt_txd_wr_status_flags_as \gwas.wsts
(.E(WEA),
.full(full),
.out(out),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_bt_txd_wr_bin_cntr wpntr
(.AR(AR),
.E(WEA),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module fifo_bt_txd_wr_status_flags_as
(full,
E,
v1_reg,
v1_reg_0,
wr_clk,
out,
wr_en,
wr_rst_busy);
output full;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input wr_clk;
input out;
input wr_en;
input wr_rst_busy;
wire [0:0]E;
wire c2_n_0;
wire comp1;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
fifo_bt_txd_compare c1
(.comp1(comp1),
.v1_reg(v1_reg));
fifo_bt_txd_compare_3 c2
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_fb_i_reg(c2_n_0),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(out),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(out),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_vref_logic_high.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_vref_logic_high(in,vrefcode,vdd18);
input vdd18;
input [7:1] in;
output [7:0] vrefcode;
assign vrefcode[7:0] = {in[7:1],1'b0};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_4_V
`define SKY130_FD_SC_HS__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_4_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/22/2015
// Design Name: SendChars
////////////////////////////////////////////////////////////////////////////////
module SendCharsTest;
reg [5:0] NumberOfChars;
reg Clock, Reset, Start, tx_full, uartClock;
wire [5:0] RAMAddress;
wire Transmitting, write_to_uart;
SendChars uut (
.NumberOfChars(NumberOfChars),
.Clock(Clock),
.Reset(Reset),
.Start(Start),
.tx_full(tx_full),
.uartClock(uartClock),
.RAMAddress(RAMAddress),
.Transmitting(Transmitting),
.write_to_uart(write_to_uart)
);
always #5 Clock = ~Clock;
always #21 uartClock = ~uartClock;
initial begin
NumberOfChars = 0; Clock = 0; Reset = 1; Start = 0; tx_full = 0; uartClock = 0; #10;
Reset = 0; # 10;
NumberOfChars = 10; #10;
Start = 1; #10;
Start = 0; #250;
tx_full = 1; #100;
tx_full = 0; #200;
$stop;
end
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C
*/
input wire i2c_scl_i,
output wire i2c_scl_o,
output wire i2c_scl_t,
input wire i2c_sda_i,
output wire i2c_sda_o,
output wire i2c_sda_t,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_gmii_clk,
input wire phy_gmii_rst,
input wire phy_gmii_clk_en,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// XFCP UART interface
wire [7:0] xfcp_uart_interface_down_tdata;
wire xfcp_uart_interface_down_tvalid;
wire xfcp_uart_interface_down_tready;
wire xfcp_uart_interface_down_tlast;
wire xfcp_uart_interface_down_tuser;
wire [7:0] xfcp_uart_interface_up_tdata;
wire xfcp_uart_interface_up_tvalid;
wire xfcp_uart_interface_up_tready;
wire xfcp_uart_interface_up_tlast;
wire xfcp_uart_interface_up_tuser;
assign uart_rts = 1'b1;
xfcp_interface_uart
xfcp_interface_uart_inst (
.clk(clk),
.rst(rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.down_xfcp_in_tdata(xfcp_uart_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_uart_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_uart_interface_up_tready),
.down_xfcp_in_tlast(xfcp_uart_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_uart_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_uart_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_uart_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_uart_interface_down_tready),
.down_xfcp_out_tlast(xfcp_uart_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_uart_interface_down_tuser),
.prescale(125000000/(115200*8))
);
// XFCP Ethernet interface
wire [7:0] xfcp_udp_interface_down_tdata;
wire xfcp_udp_interface_down_tvalid;
wire xfcp_udp_interface_down_tready;
wire xfcp_udp_interface_down_tlast;
wire xfcp_udp_interface_down_tuser;
wire [7:0] xfcp_udp_interface_up_tdata;
wire xfcp_udp_interface_up_tvalid;
wire xfcp_udp_interface_up_tready;
wire xfcp_udp_interface_up_tlast;
wire xfcp_udp_interface_up_tuser;
// AXI between MAC and Ethernet modules
wire [7:0] rx_eth_axis_tdata;
wire rx_eth_axis_tvalid;
wire rx_eth_axis_tready;
wire rx_eth_axis_tlast;
wire rx_eth_axis_tuser;
wire [7:0] tx_eth_axis_tdata;
wire tx_eth_axis_tvalid;
wire tx_eth_axis_tready;
wire tx_eth_axis_tlast;
wire tx_eth_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [15:0] local_port = 16'd14000;
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
assign phy_reset_n = ~rst;
assign led = 0;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rx_clk(phy_gmii_clk),
.rx_rst(phy_gmii_rst),
.tx_clk(phy_gmii_clk),
.tx_rst(phy_gmii_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_eth_axis_tdata),
.tx_axis_tvalid(tx_eth_axis_tvalid),
.tx_axis_tready(tx_eth_axis_tready),
.tx_axis_tlast(tx_eth_axis_tlast),
.tx_axis_tuser(tx_eth_axis_tuser),
.rx_axis_tdata(rx_eth_axis_tdata),
.rx_axis_tvalid(rx_eth_axis_tvalid),
.rx_axis_tready(rx_eth_axis_tready),
.rx_axis_tlast(rx_eth_axis_tlast),
.rx_axis_tuser(rx_eth_axis_tuser),
.gmii_rxd(phy_gmii_rxd),
.gmii_rx_dv(phy_gmii_rx_dv),
.gmii_rx_er(phy_gmii_rx_er),
.gmii_txd(phy_gmii_txd),
.gmii_tx_en(phy_gmii_tx_en),
.gmii_tx_er(phy_gmii_tx_er),
.rx_clk_enable(phy_gmii_clk_en),
.tx_clk_enable(phy_gmii_clk_en),
.rx_mii_select(1'b0),
.tx_mii_select(1'b0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
xfcp_interface_udp
xfcp_interface_udp_inst (
.clk(clk),
.rst(rst),
.s_eth_axis_tdata(rx_eth_axis_tdata),
.s_eth_axis_tvalid(rx_eth_axis_tvalid),
.s_eth_axis_tready(rx_eth_axis_tready),
.s_eth_axis_tlast(rx_eth_axis_tlast),
.s_eth_axis_tuser(rx_eth_axis_tuser),
.m_eth_axis_tdata(tx_eth_axis_tdata),
.m_eth_axis_tvalid(tx_eth_axis_tvalid),
.m_eth_axis_tready(tx_eth_axis_tready),
.m_eth_axis_tlast(tx_eth_axis_tlast),
.m_eth_axis_tuser(tx_eth_axis_tuser),
.down_xfcp_in_tdata(xfcp_udp_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_udp_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_udp_interface_up_tready),
.down_xfcp_in_tlast(xfcp_udp_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_udp_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_udp_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_udp_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_udp_interface_down_tready),
.down_xfcp_out_tlast(xfcp_udp_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_udp_interface_down_tuser),
.local_mac(local_mac),
.local_ip(local_ip),
.local_port(local_port),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask)
);
// XFCP 2x1 switch
wire [7:0] xfcp_interface_switch_down_tdata;
wire xfcp_interface_switch_down_tvalid;
wire xfcp_interface_switch_down_tready;
wire xfcp_interface_switch_down_tlast;
wire xfcp_interface_switch_down_tuser;
wire [7:0] xfcp_interface_switch_up_tdata;
wire xfcp_interface_switch_up_tvalid;
wire xfcp_interface_switch_up_tready;
wire xfcp_interface_switch_up_tlast;
wire xfcp_interface_switch_up_tuser;
xfcp_arb #(
.PORTS(2)
)
xfcp_interface_arb_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata({xfcp_udp_interface_down_tdata, xfcp_uart_interface_down_tdata}),
.up_xfcp_in_tvalid({xfcp_udp_interface_down_tvalid, xfcp_uart_interface_down_tvalid}),
.up_xfcp_in_tready({xfcp_udp_interface_down_tready, xfcp_uart_interface_down_tready}),
.up_xfcp_in_tlast({xfcp_udp_interface_down_tlast, xfcp_uart_interface_down_tlast}),
.up_xfcp_in_tuser({xfcp_udp_interface_down_tuser, xfcp_uart_interface_down_tuser}),
.up_xfcp_out_tdata({xfcp_udp_interface_up_tdata, xfcp_uart_interface_up_tdata}),
.up_xfcp_out_tvalid({xfcp_udp_interface_up_tvalid, xfcp_uart_interface_up_tvalid}),
.up_xfcp_out_tready({xfcp_udp_interface_up_tready, xfcp_uart_interface_up_tready}),
.up_xfcp_out_tlast({xfcp_udp_interface_up_tlast, xfcp_uart_interface_up_tlast}),
.up_xfcp_out_tuser({xfcp_udp_interface_up_tuser, xfcp_uart_interface_up_tuser}),
.down_xfcp_in_tdata(xfcp_interface_switch_up_tdata),
.down_xfcp_in_tvalid(xfcp_interface_switch_up_tvalid),
.down_xfcp_in_tready(xfcp_interface_switch_up_tready),
.down_xfcp_in_tlast(xfcp_interface_switch_up_tlast),
.down_xfcp_in_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_out_tdata(xfcp_interface_switch_down_tdata),
.down_xfcp_out_tvalid(xfcp_interface_switch_down_tvalid),
.down_xfcp_out_tready(xfcp_interface_switch_down_tready),
.down_xfcp_out_tlast(xfcp_interface_switch_down_tlast),
.down_xfcp_out_tuser(xfcp_interface_switch_down_tuser)
);
// XFCP 1x4 switch
wire [7:0] xfcp_switch_port_0_down_tdata;
wire xfcp_switch_port_0_down_tvalid;
wire xfcp_switch_port_0_down_tready;
wire xfcp_switch_port_0_down_tlast;
wire xfcp_switch_port_0_down_tuser;
wire [7:0] xfcp_switch_port_0_up_tdata;
wire xfcp_switch_port_0_up_tvalid;
wire xfcp_switch_port_0_up_tready;
wire xfcp_switch_port_0_up_tlast;
wire xfcp_switch_port_0_up_tuser;
wire [7:0] xfcp_switch_port_1_down_tdata;
wire xfcp_switch_port_1_down_tvalid;
wire xfcp_switch_port_1_down_tready;
wire xfcp_switch_port_1_down_tlast;
wire xfcp_switch_port_1_down_tuser;
wire [7:0] xfcp_switch_port_1_up_tdata;
wire xfcp_switch_port_1_up_tvalid;
wire xfcp_switch_port_1_up_tready;
wire xfcp_switch_port_1_up_tlast;
wire xfcp_switch_port_1_up_tuser;
wire [7:0] xfcp_switch_port_2_down_tdata;
wire xfcp_switch_port_2_down_tvalid;
wire xfcp_switch_port_2_down_tready;
wire xfcp_switch_port_2_down_tlast;
wire xfcp_switch_port_2_down_tuser;
wire [7:0] xfcp_switch_port_2_up_tdata;
wire xfcp_switch_port_2_up_tvalid;
wire xfcp_switch_port_2_up_tready;
wire xfcp_switch_port_2_up_tlast;
wire xfcp_switch_port_2_up_tuser;
wire [7:0] xfcp_switch_port_3_down_tdata;
wire xfcp_switch_port_3_down_tvalid;
wire xfcp_switch_port_3_down_tready;
wire xfcp_switch_port_3_down_tlast;
wire xfcp_switch_port_3_down_tuser;
wire [7:0] xfcp_switch_port_3_up_tdata;
wire xfcp_switch_port_3_up_tvalid;
wire xfcp_switch_port_3_up_tready;
wire xfcp_switch_port_3_up_tlast;
wire xfcp_switch_port_3_up_tuser;
xfcp_switch #(
.PORTS(4),
.XFCP_ID_TYPE(16'h0100),
.XFCP_ID_STR("XFCP switch"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("VCU118")
)
xfcp_switch_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_interface_switch_down_tdata),
.up_xfcp_in_tvalid(xfcp_interface_switch_down_tvalid),
.up_xfcp_in_tready(xfcp_interface_switch_down_tready),
.up_xfcp_in_tlast(xfcp_interface_switch_down_tlast),
.up_xfcp_in_tuser(xfcp_interface_switch_down_tuser),
.up_xfcp_out_tdata(xfcp_interface_switch_up_tdata),
.up_xfcp_out_tvalid(xfcp_interface_switch_up_tvalid),
.up_xfcp_out_tready(xfcp_interface_switch_up_tready),
.up_xfcp_out_tlast(xfcp_interface_switch_up_tlast),
.up_xfcp_out_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_in_tdata( {xfcp_switch_port_3_up_tdata, xfcp_switch_port_2_up_tdata, xfcp_switch_port_1_up_tdata, xfcp_switch_port_0_up_tdata }),
.down_xfcp_in_tvalid( {xfcp_switch_port_3_up_tvalid, xfcp_switch_port_2_up_tvalid, xfcp_switch_port_1_up_tvalid, xfcp_switch_port_0_up_tvalid }),
.down_xfcp_in_tready( {xfcp_switch_port_3_up_tready, xfcp_switch_port_2_up_tready, xfcp_switch_port_1_up_tready, xfcp_switch_port_0_up_tready }),
.down_xfcp_in_tlast( {xfcp_switch_port_3_up_tlast, xfcp_switch_port_2_up_tlast, xfcp_switch_port_1_up_tlast, xfcp_switch_port_0_up_tlast }),
.down_xfcp_in_tuser( {xfcp_switch_port_3_up_tuser, xfcp_switch_port_2_up_tuser, xfcp_switch_port_1_up_tuser, xfcp_switch_port_0_up_tuser }),
.down_xfcp_out_tdata( {xfcp_switch_port_3_down_tdata, xfcp_switch_port_2_down_tdata, xfcp_switch_port_1_down_tdata, xfcp_switch_port_0_down_tdata }),
.down_xfcp_out_tvalid({xfcp_switch_port_3_down_tvalid, xfcp_switch_port_2_down_tvalid, xfcp_switch_port_1_down_tvalid, xfcp_switch_port_0_down_tvalid}),
.down_xfcp_out_tready({xfcp_switch_port_3_down_tready, xfcp_switch_port_2_down_tready, xfcp_switch_port_1_down_tready, xfcp_switch_port_0_down_tready}),
.down_xfcp_out_tlast( {xfcp_switch_port_3_down_tlast, xfcp_switch_port_2_down_tlast, xfcp_switch_port_1_down_tlast, xfcp_switch_port_0_down_tlast }),
.down_xfcp_out_tuser( {xfcp_switch_port_3_down_tuser, xfcp_switch_port_2_down_tuser, xfcp_switch_port_1_down_tuser, xfcp_switch_port_0_down_tuser })
);
// XFCP WB RAM 0
wire [7:0] ram_0_wb_adr_i;
wire [31:0] ram_0_wb_dat_i;
wire [31:0] ram_0_wb_dat_o;
wire ram_0_wb_we_i;
wire [3:0] ram_0_wb_sel_i;
wire ram_0_wb_stb_i;
wire ram_0_wb_ack_o;
wire ram_0_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 0"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_0 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_0_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_0_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_0_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_0_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_0_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_0_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_0_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_0_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_0_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_0_up_tuser),
.wb_adr_o(ram_0_wb_adr_i),
.wb_dat_i(ram_0_wb_dat_o),
.wb_dat_o(ram_0_wb_dat_i),
.wb_we_o(ram_0_wb_we_i),
.wb_sel_o(ram_0_wb_sel_i),
.wb_stb_o(ram_0_wb_stb_i),
.wb_ack_i(ram_0_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_0_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_0_inst (
.clk(clk),
.adr_i(ram_0_wb_adr_i),
.dat_i(ram_0_wb_dat_i),
.dat_o(ram_0_wb_dat_o),
.we_i(ram_0_wb_we_i),
.sel_i(ram_0_wb_sel_i),
.stb_i(ram_0_wb_stb_i),
.ack_o(ram_0_wb_ack_o),
.cyc_i(ram_0_wb_cyc_i)
);
// XFCP WB RAM 1
wire [7:0] ram_1_wb_adr_i;
wire [31:0] ram_1_wb_dat_i;
wire [31:0] ram_1_wb_dat_o;
wire ram_1_wb_we_i;
wire [3:0] ram_1_wb_sel_i;
wire ram_1_wb_stb_i;
wire ram_1_wb_ack_o;
wire ram_1_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 1"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_1 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_1_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_1_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_1_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_1_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_1_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_1_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_1_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_1_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_1_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_1_up_tuser),
.wb_adr_o(ram_1_wb_adr_i),
.wb_dat_i(ram_1_wb_dat_o),
.wb_dat_o(ram_1_wb_dat_i),
.wb_we_o(ram_1_wb_we_i),
.wb_sel_o(ram_1_wb_sel_i),
.wb_stb_o(ram_1_wb_stb_i),
.wb_ack_i(ram_1_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_1_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_1_inst (
.clk(clk),
.adr_i(ram_1_wb_adr_i),
.dat_i(ram_1_wb_dat_i),
.dat_o(ram_1_wb_dat_o),
.we_i(ram_1_wb_we_i),
.sel_i(ram_1_wb_sel_i),
.stb_i(ram_1_wb_stb_i),
.ack_o(ram_1_wb_ack_o),
.cyc_i(ram_1_wb_cyc_i)
);
// XFCP WB RAM 2
wire [7:0] ram_2_wb_adr_i;
wire [31:0] ram_2_wb_dat_i;
wire [31:0] ram_2_wb_dat_o;
wire ram_2_wb_we_i;
wire [3:0] ram_2_wb_sel_i;
wire ram_2_wb_stb_i;
wire ram_2_wb_ack_o;
wire ram_2_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 2"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_2 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_2_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_2_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_2_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_2_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_2_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_2_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_2_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_2_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_2_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_2_up_tuser),
.wb_adr_o(ram_2_wb_adr_i),
.wb_dat_i(ram_2_wb_dat_o),
.wb_dat_o(ram_2_wb_dat_i),
.wb_we_o(ram_2_wb_we_i),
.wb_sel_o(ram_2_wb_sel_i),
.wb_stb_o(ram_2_wb_stb_i),
.wb_ack_i(ram_2_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_2_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_2_inst (
.clk(clk),
.adr_i(ram_2_wb_adr_i),
.dat_i(ram_2_wb_dat_i),
.dat_o(ram_2_wb_dat_o),
.we_i(ram_2_wb_we_i),
.sel_i(ram_2_wb_sel_i),
.stb_i(ram_2_wb_stb_i),
.ack_o(ram_2_wb_ack_o),
.cyc_i(ram_2_wb_cyc_i)
);
// XFCP I2C Master
xfcp_mod_i2c_master #(
.XFCP_ID_STR("XFCP I2C Master"),
.DEFAULT_PRESCALE(125000000/(400000*4))
)
i2c_master_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_3_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_3_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_3_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_3_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_3_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_3_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_3_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_3_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_3_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_3_up_tuser),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
|
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM Physical IP, INC.
//
// Copyright (c) 1993-2013 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc. In addition,
// this Software is protected by patents, copyright law and international
// treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// name: Advantage Single-Port Register File Generator
// TSMC 90nm CLN90G Process
// version: 2007Q2V1
// comment:
// configuration: -instname "D_Cache" -words 32 -bits 128 -frequency 100 -ring_width 2.0 -mux 1 -write_mask off -wp_size 8 -top_layer "met5-9" -power_type rings -horiz met3 -vert met2 -redundancy off -rcols 1 -rrows 0 -bmux off -ema on -cust_comment "" -bus_notation on -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename "VDD:VDD,VSS:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname on -diodes on -inside_ring_type VSS -drive 4 -asvm off -corners ff_1.1_-40.0,ff_1.1_125.0,tt_1.0_25.0,ss_0.9_125.0
//
// Verilog model for Synchronous Single-Port Register File
//
// Instance Name: D_Cache
// Words: 32
// Bits: 128
// Mux: 1
// Drive: 4
// Write Mask: Off
// Extra Margin Adjustment: On
// Accelerated Retention Test: Off
// Redundant Rows: 0
// Redundant Columns: 0
// Test Muxes Off
//
// Creation Date: 2013-03-11 09:15:27Z
// Version: 2007Q2V1
//
// Modeling Assumptions: This model supports full gate level simulation
// including proper x-handling and timing check behavior. Unit
// delay timing is included in the model. Back-annotation of SDF
// (v2.1) is supported. SDF can be created utilyzing the delay
// calculation views provided with this generator and supported
// delay calculators. All buses are modeled [MSB:LSB]. All
// ports are padded with Verilog primitives.
//
// Modeling Limitations: None.
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1 ns/1 ps
`celldefine
module D_Cache (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA
);
parameter BITS = 128;
parameter WORD_DEPTH = 32;
parameter ADDR_WIDTH = 5;
parameter WORDX = {BITS{1'bx}};
parameter WORD1 = {BITS{1'b1}};
parameter ADDRX = {ADDR_WIDTH{1'bx}};
parameter ADDR1 = {ADDR_WIDTH{1'b1}};
parameter WEN_WIDTH = 1;
parameter WP_SIZE = 128 ;
parameter RCOLS = 0;
parameter MASKX = {WEN_WIDTH{1'bx}};
parameter MASK1 = {WEN_WIDTH{1'b1}};
parameter MASK0 = {WEN_WIDTH{1'b0}};
parameter MUX = 1;
parameter COL_ADDR_WIDTH = 0;
parameter RROWS = 0;
parameter UPM_WIDTH = 3;
parameter UPM0 = {UPM_WIDTH{1'b0}};
parameter RCA_WIDTH = 1;
parameter RED_COLUMNS = 1;
output [127:0] Q;
input CLK;
input CEN;
input WEN;
input [4:0] A;
input [127:0] D;
input [2:0] EMA;
reg [BITS+RED_COLUMNS-1:0] mem [0:WORD_DEPTH-1];
reg [BITS+RED_COLUMNS-1:0] rows [(MUX*4)-1:0]; // added 2 bits for column redundancy
reg NOT_CEN;
reg NOT_WEN;
reg NOT_A4;
reg NOT_A3;
reg NOT_A2;
reg NOT_A1;
reg NOT_A0;
reg [ADDR_WIDTH-1:0] NOT_A;
reg NOT_D127;
reg NOT_D126;
reg NOT_D125;
reg NOT_D124;
reg NOT_D123;
reg NOT_D122;
reg NOT_D121;
reg NOT_D120;
reg NOT_D119;
reg NOT_D118;
reg NOT_D117;
reg NOT_D116;
reg NOT_D115;
reg NOT_D114;
reg NOT_D113;
reg NOT_D112;
reg NOT_D111;
reg NOT_D110;
reg NOT_D109;
reg NOT_D108;
reg NOT_D107;
reg NOT_D106;
reg NOT_D105;
reg NOT_D104;
reg NOT_D103;
reg NOT_D102;
reg NOT_D101;
reg NOT_D100;
reg NOT_D99;
reg NOT_D98;
reg NOT_D97;
reg NOT_D96;
reg NOT_D95;
reg NOT_D94;
reg NOT_D93;
reg NOT_D92;
reg NOT_D91;
reg NOT_D90;
reg NOT_D89;
reg NOT_D88;
reg NOT_D87;
reg NOT_D86;
reg NOT_D85;
reg NOT_D84;
reg NOT_D83;
reg NOT_D82;
reg NOT_D81;
reg NOT_D80;
reg NOT_D79;
reg NOT_D78;
reg NOT_D77;
reg NOT_D76;
reg NOT_D75;
reg NOT_D74;
reg NOT_D73;
reg NOT_D72;
reg NOT_D71;
reg NOT_D70;
reg NOT_D69;
reg NOT_D68;
reg NOT_D67;
reg NOT_D66;
reg NOT_D65;
reg NOT_D64;
reg NOT_D63;
reg NOT_D62;
reg NOT_D61;
reg NOT_D60;
reg NOT_D59;
reg NOT_D58;
reg NOT_D57;
reg NOT_D56;
reg NOT_D55;
reg NOT_D54;
reg NOT_D53;
reg NOT_D52;
reg NOT_D51;
reg NOT_D50;
reg NOT_D49;
reg NOT_D48;
reg NOT_D47;
reg NOT_D46;
reg NOT_D45;
reg NOT_D44;
reg NOT_D43;
reg NOT_D42;
reg NOT_D41;
reg NOT_D40;
reg NOT_D39;
reg NOT_D38;
reg NOT_D37;
reg NOT_D36;
reg NOT_D35;
reg NOT_D34;
reg NOT_D33;
reg NOT_D32;
reg NOT_D31;
reg NOT_D30;
reg NOT_D29;
reg NOT_D28;
reg NOT_D27;
reg NOT_D26;
reg NOT_D25;
reg NOT_D24;
reg NOT_D23;
reg NOT_D22;
reg NOT_D21;
reg NOT_D20;
reg NOT_D19;
reg NOT_D18;
reg NOT_D17;
reg NOT_D16;
reg NOT_D15;
reg NOT_D14;
reg NOT_D13;
reg NOT_D12;
reg NOT_D11;
reg NOT_D10;
reg NOT_D9;
reg NOT_D8;
reg NOT_D7;
reg NOT_D6;
reg NOT_D5;
reg NOT_D4;
reg NOT_D3;
reg NOT_D2;
reg NOT_D1;
reg NOT_D0;
reg [BITS-1:0] NOT_D;
reg NOT_EMA2;
reg NOT_EMA1;
reg NOT_EMA0;
reg [UPM_WIDTH-1:0] NOT_EMA;
reg NOT_CLK_PER;
reg NOT_CLK_MINH;
reg NOT_CLK_MINL;
reg LAST_NOT_CEN;
reg LAST_NOT_WEN;
reg [ADDR_WIDTH-1:0] LAST_NOT_A;
reg [BITS-1:0] LAST_NOT_D;
reg [UPM_WIDTH-1:0] LAST_NOT_EMA;
reg LAST_NOT_CLK_PER;
reg LAST_NOT_CLK_MINH;
reg LAST_NOT_CLK_MINL;
wire [BITS-1:0] _Q;
wire _CLK;
wire _CEN;
wire _WEN;
wire [ADDR_WIDTH-1:0] _A;
wire [BITS-1:0] _D;
wire [UPM_WIDTH-1:0] _EMA;
wire CEN_flag;
wire TCEN_flag;
wire flag;
wire D_flag;
wire cyc_flag;
wire EMA2eq0andEMA1eq0andEMA0eq0;
wire EMA2eq0andEMA1eq0andEMA0eq1;
wire EMA2eq0andEMA1eq1andEMA0eq0;
wire EMA2eq0andEMA1eq1andEMA0eq1;
wire EMA2eq1andEMA1eq0andEMA0eq0;
wire EMA2eq1andEMA1eq0andEMA0eq1;
wire EMA2eq1andEMA1eq1andEMA0eq0;
wire EMA2eq1andEMA1eq1andEMA0eq1;
reg LATCHED_CEN;
reg LATCHED_WEN;
reg [ADDR_WIDTH-1:0] LATCHED_A;
reg [BITS-1:0] LATCHED_D;
reg [UPM_WIDTH-1:0] LATCHED_EMA;
reg [BITS-1:0] Qi;
reg [BITS-1:0] LAST_Qi;
reg [BITS-1:0] dummy_qb;
reg LAST_CLK;
reg [BITS+RED_COLUMNS-1:0] last_status [(MUX*2)-1:0];
task update_notifier_buses;
begin
NOT_A = {
NOT_A4,
NOT_A3,
NOT_A2,
NOT_A1,
NOT_A0};
NOT_D = {
NOT_D127,
NOT_D126,
NOT_D125,
NOT_D124,
NOT_D123,
NOT_D122,
NOT_D121,
NOT_D120,
NOT_D119,
NOT_D118,
NOT_D117,
NOT_D116,
NOT_D115,
NOT_D114,
NOT_D113,
NOT_D112,
NOT_D111,
NOT_D110,
NOT_D109,
NOT_D108,
NOT_D107,
NOT_D106,
NOT_D105,
NOT_D104,
NOT_D103,
NOT_D102,
NOT_D101,
NOT_D100,
NOT_D99,
NOT_D98,
NOT_D97,
NOT_D96,
NOT_D95,
NOT_D94,
NOT_D93,
NOT_D92,
NOT_D91,
NOT_D90,
NOT_D89,
NOT_D88,
NOT_D87,
NOT_D86,
NOT_D85,
NOT_D84,
NOT_D83,
NOT_D82,
NOT_D81,
NOT_D80,
NOT_D79,
NOT_D78,
NOT_D77,
NOT_D76,
NOT_D75,
NOT_D74,
NOT_D73,
NOT_D72,
NOT_D71,
NOT_D70,
NOT_D69,
NOT_D68,
NOT_D67,
NOT_D66,
NOT_D65,
NOT_D64,
NOT_D63,
NOT_D62,
NOT_D61,
NOT_D60,
NOT_D59,
NOT_D58,
NOT_D57,
NOT_D56,
NOT_D55,
NOT_D54,
NOT_D53,
NOT_D52,
NOT_D51,
NOT_D50,
NOT_D49,
NOT_D48,
NOT_D47,
NOT_D46,
NOT_D45,
NOT_D44,
NOT_D43,
NOT_D42,
NOT_D41,
NOT_D40,
NOT_D39,
NOT_D38,
NOT_D37,
NOT_D36,
NOT_D35,
NOT_D34,
NOT_D33,
NOT_D32,
NOT_D31,
NOT_D30,
NOT_D29,
NOT_D28,
NOT_D27,
NOT_D26,
NOT_D25,
NOT_D24,
NOT_D23,
NOT_D22,
NOT_D21,
NOT_D20,
NOT_D19,
NOT_D18,
NOT_D17,
NOT_D16,
NOT_D15,
NOT_D14,
NOT_D13,
NOT_D12,
NOT_D11,
NOT_D10,
NOT_D9,
NOT_D8,
NOT_D7,
NOT_D6,
NOT_D5,
NOT_D4,
NOT_D3,
NOT_D2,
NOT_D1,
NOT_D0};
NOT_EMA = {
NOT_EMA2,
NOT_EMA1,
NOT_EMA0};
end
endtask
task mem_cycle;
inout [BITS-1:0] q;
inout [BITS-1:0] other_q;
input cen;
input [WEN_WIDTH-1:0] wen;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input [UPM_WIDTH-1:0] ema;
input artn;
input ten;
input ben;
input tcen;
input [WEN_WIDTH-1:0] twen;
input [ADDR_WIDTH-1:0] ta;
input [BITS-1:0] td;
input rren;
input rra;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input contention_flag;
input [BITS-1:0] other_cren;
input port; // 0 for A port, 1 for B port
integer mask_section ;
integer lsb ;
integer msb ;
reg CENi;
reg [WEN_WIDTH-1:0] WENi;
reg [ADDR_WIDTH-1:0] Ai;
reg [BITS-1:0] Di;
reg ValidDummyPinsi;
begin
CENi = ten ? cen : tcen;
Ai = ten ? a : ta;
WENi = ten ? wen : twen;
Di = ten ? d : td;
ValidDummyPinsi = (^({ema,artn}) !== 1'bx);
if ( (artn !== 1'b1) & (WENi !== MASK1) & (WENi !== MASK0))
begin
$display("ARTN is active and all bits of WEN are not active or inactive");
$display("Setting WEN bus to x");
WENi = MASKX;
end
if (!valid_cren(cren))
begin
$display("CREN is in an invalid state");
$display("Setting CREN bus to x");
cren = WORDX;
end
for (mask_section=0;mask_section<WEN_WIDTH; mask_section=mask_section+1)
begin
lsb = (mask_section)*(WP_SIZE) ;
msb = BITS <= (lsb+WP_SIZE-1) ? (BITS-1) : (lsb+WP_SIZE-1) ;
casez({WENi[mask_section],CENi,ValidDummyPinsi})
3'b101: begin
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0,contention_flag,port);
end
3'b001: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0,contention_flag,other_cren,port);
write_thru(q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0);
end
3'b?1?: ;
3'b10?,
3'b1x?: begin
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,port);
end
3'b00?,
3'b0x?: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,other_cren,port);
write_thru(q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1);
end
3'bx0?,
3'bxx?: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,other_cren,port);
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,port);
end
endcase
end
end
endtask
task read_mem;
inout [BITS-1:0] q;
inout [BITS-1:0] other_q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
input contention;
input port;
integer msb;
integer lsb;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [BITS+RED_COLUMNS-1:0] other_status;
reg [BITS+RED_COLUMNS-1:0] status;
integer m;
integer n;
begin
if (rren === 1'bx)
begin
for (n=lsb; n<=msb; n=n+1) q[n] = 1'bx ;
x_mem;
x_rows;
end
else
begin
if (!valid_address(a,rren,radd))
begin
for (n=lsb; n<=msb; n=n+1) q[n] = 1'bx ;
if (rren === 1'b1)
begin
x_mem;
end
else if (rren === 1'b0)
begin
casez({radd,1'b0})
2'bxx: x_rows;
2'bx?: begin
x_row(0,1'b0);
x_row(1,1'b0);
end
2'b?x: begin
x_row(radd,0);
x_row(radd,1);
end
default:
x_row(radd,1'b0);
endcase
end
end
else
begin
if (rren === 1'b1)
tmpdata = mem[a];
else if (rren === 1'b0)
tmpdata = rows[{1'b0,radd}];
status = last_status[port];
other_status = last_status[!port];
for (n=lsb; n<=msb; n=n+1)
begin
if (cren[n] === 1'b1)
begin
if ((other_status[n] === 1'b0) & contention)
begin
tmpdata[n] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n];
status[n] = 1'b1;
end
end
else if (cren[n] === 1'b0)
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n+rca+1] === 1'b0) & contention)
begin
tmpdata[n+rca+1] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n+rca+1];
status[n+rca+1] = 1'b1;
end
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
if ((other_status[n+m+1] === 1'b0) & contention)
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b1;
end
q[n] = 1'bx;
end
else
begin
if ((other_status[n+1] === 1'b0) & contention)
begin
tmpdata[n+1] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n+1];
status[n+1] = 1'b1;
end
end
end
else
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
if ((other_status[n+rca+1] === 1'b0) & contention)
tmpdata[n+rca+1] = 1'bx;
status[n] = 1'b1;
status[n+rca+1] = 1'b1;
q[n] = 1'bx;
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
for (m=0; m<RED_COLUMNS; m=m+1)
begin
if ((other_status[n+m+1] === 1'b0) & contention)
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b1;
end
status[n] = 1'b1;
q[n] = 1'bx;
end
else
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
q[n] = 1'bx;
status[n] = 1'b1;
status[n+1] = 1'b1;
end
end
end
if (rren === 1'b1)
mem[a] = tmpdata;
else if (rren === 1'b0)
rows[{1'b0,radd}] = tmpdata;
last_status[port] = status;
if (msb == BITS-1)
begin
if (rren === 1'b1)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_mem(a,BITS+m,tmpdata[BITS+m]);
end
end
else if (rren === 1'b0)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_rows(a,BITS+m,tmpdata[BITS+m],radd,1'b0);
end
end
update_status(status,port);
end
end
end
end
endtask
task write_mem;
inout [BITS-1:0] other_q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
input contention;
input [BITS-1:0] other_cren;
input port;
integer msb;
integer lsb;
integer m;
integer n;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [BITS+RED_COLUMNS-1:0] other_status;
reg [BITS+RED_COLUMNS-1:0] status;
reg [ADDR_WIDTH-1:0] tmpaddr;
begin
if (rren === 1'bx)
begin
x_mem;
x_rows;
end
else
begin
if (!valid_address(a,rren,radd))
begin
if (rren === 1'b1)
begin
x_mem;
end
else if (rren === 1'b0)
begin
casez({radd,1'b0})
2'bxx: x_rows;
2'bx?: begin
x_row(0,1'b0);
x_row(1,1'b0);
end
2'b?x: begin
x_row(radd,0);
x_row(radd,1);
end
default:
x_row(radd,1'b0);
endcase
end
end
else
begin
if (rren === 1'b1)
tmpdata = mem[a];
else if (rren === 1'b0)
tmpdata = rows[{1'b0,radd}];
status = last_status[port];
other_status = last_status[!port];
for (n=lsb; n<=msb; n=n+1)
begin
if (cren[n] === 1'b1)
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
else if ((other_status[n] === 1'b1) & contention)
begin
tmpdata[n] = 1'bx;
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
end
else
begin
tmpdata[n] = xout ? 1'bx : d[n];
status[n] = 1'b0;
end
if ((n < BITS-1) & (cren[n+1] === 1'b0))
begin
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
else if ((other_status[n+1] === 1'b1) & contention)
begin
tmpdata[n+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
else
begin
tmpdata[n+1] = xout ? 1'bx : d[n];
status[n+1] = 1'b0;
end
end
else if ((n < BITS-1) & (cren[n+1] === 1'bx))
begin
tmpdata[n+1] = 1'bx;
status[n+1] = 1'b0;
if ((other_status[n+1] === 1'b1) & contention)
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
end
else if (cren[n] === 1'b0)
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n+rca+1] === 1'b0) & contention)
tmpdata[n+rca+1] = 1'bx;
else if ((other_status[n+rca+1] === 1'b1) & contention)
begin
tmpdata[n+rca+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
else
begin
tmpdata[n+rca+1] = xout ? 1'bx : d[n];
status[n+rca+1] = 1'b0;
end
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b0;
if ((other_status[n+m+1] === 1'b1) & contention)
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
end
else
begin
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
else if ((other_status[n+1] === 1'b1) & contention)
begin
tmpdata[n+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
else
begin
tmpdata[n+1] = xout ? 1'bx : d[n];
status[n+1] = 1'b0;
end
end
if (n === 0)
begin
if ((other_status[0] === 1'b0) & contention)
tmpdata[0] = 1'bx;
else if ((other_status[0] === 1'b1) & contention)
begin
tmpdata[0] = 1'bx;
if (other_cren[0] === 1'b1)
other_q[0] = 1'bx;
end
else
begin
tmpdata[0] = xout ? 1'bx : 1'b0;
status[0] = 1'b0;
end
end
end
else
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
tmpdata[n] = 1'bx;
tmpdata[n+rca+1] = 1'bx;
status[n] = 1'b0;
status[n+rca+1] = 1'b0;
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
if ((other_status[n+rca+1] === 1'b1) & contention)
other_q[n] = 1'bx;
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
tmpdata[n] = 1'bx;
status[n] = 1'b0;
for (m=0; m<RED_COLUMNS; m=m+1)
begin
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b0;
if ((other_status[n+m+1] === 1'b1) & contention)
other_q[n] = 1'bx;
end
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
end
else
begin
tmpdata[n] = 1'bx;
tmpdata[n+1] = 1'bx;
status[n] = 1'b0;
status[n+1] = 1'b0;
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
if ((other_status[n+1] === 1'b1) & contention)
if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
else if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
end
end
if (rren === 1'b1)
mem[a]=tmpdata;
else if (rren === 1'b0)
rows[{1'b0,radd}] = tmpdata;
last_status[port] = status;
// copy the redundent columns to all all combinations of ymux addresses
if (msb == BITS-1)
begin
if (rren === 1'b1)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_mem(a,BITS+m,tmpdata[BITS+m]);
end
end
else if (rren === 1'b0)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_rows(a,BITS+m,tmpdata[BITS+m],radd,1'b0);
end
end
update_status(status,port);
end
end
end
end
endtask
task write_thru;
inout [BITS-1:0] q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
integer msb;
integer lsb;
integer n;
begin
if (^cren !== 1'bx)
for (n=lsb;n<=msb;n=n+1) q[n] = xout ? 1'bx : d[n] ;
else
for (n=lsb;n<=msb;n=n+1) q[n] = 1'bx ;
end
endtask
task update_last_notifiers;
begin
LAST_NOT_CEN = NOT_CEN;
LAST_NOT_WEN = NOT_WEN;
LAST_NOT_A = NOT_A;
LAST_NOT_D = NOT_D;
LAST_NOT_EMA = NOT_EMA;
LAST_NOT_CLK_PER = NOT_CLK_PER;
LAST_NOT_CLK_MINH = NOT_CLK_MINH;
LAST_NOT_CLK_MINL = NOT_CLK_MINL;
end
endtask
task latch_inputs;
begin
LATCHED_CEN = _CEN;
LATCHED_WEN = _WEN;
LATCHED_A = _A;
LATCHED_D = _D;
LATCHED_EMA = _EMA;
end
endtask
task x_inputs;
integer n;
begin
LATCHED_CEN = (NOT_CEN!==LAST_NOT_CEN) ? 1'bx : LATCHED_CEN ;
LATCHED_WEN = (NOT_WEN!==LAST_NOT_WEN) ? 1'bx : LATCHED_WEN ;
for (n=0; n<ADDR_WIDTH; n=n+1)
begin
LATCHED_A[n] = (NOT_A[n]!==LAST_NOT_A[n]) ? 1'bx : LATCHED_A[n] ;
end
for (n=0; n<BITS; n=n+1)
begin
LATCHED_D[n] = (NOT_D[n]!==LAST_NOT_D[n]) ? 1'bx : LATCHED_D[n] ;
end
for (n=0; n<UPM_WIDTH; n=n+1)
begin
LATCHED_EMA[n] = (NOT_EMA[n]!==LAST_NOT_EMA[n]) ? 1'bx : LATCHED_EMA[n] ;
end
end
endtask
task update_status;
input [BITS+RED_COLUMNS-1:0] val;
input port;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
integer n;
begin
for (n=0; n<=MUX-1; n=n+1)
begin
tmpdata = last_status[port];
tmpdata[BITS+RED_COLUMNS-1:BITS] = val[BITS+RED_COLUMNS-1:BITS];
last_status[port] = tmpdata;
end
end
endtask // update_status
task clear_status;
input port;
reg tmpaddr;
integer n;
begin
for (n=0; n<=MUX-1; n=n+1)
begin
tmpaddr = port;
last_status[tmpaddr] = {WORDX,{RED_COLUMNS{1'bx}}};
end
end
endtask // clear_status
task replace_bit_in_mem;
input [ADDR_WIDTH-1:0] a;
input pos;
input data;
integer pos;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [ADDR_WIDTH-1:0] tmpaddr;
integer n;
begin
tmpdata = mem[a];
tmpdata[pos] = data;
mem[a] = tmpdata;
end
endtask // replace_bit_in_mem
task replace_bit_in_rows;
input [ADDR_WIDTH-1:0] a;
input pos;
input data;
input radd;
input bank_address;
integer pos;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
integer n;
begin
tmpdata = rows[{bank_address,radd}];
tmpdata[pos] = data;
rows[{bank_address,radd}] = tmpdata;
end
endtask // replace_bit_in_rows
task x_mem;
integer n;
begin
for (n=0; n<WORD_DEPTH; n=n+1)
mem[n]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bits for column redundancy
end
endtask
task x_rows;
integer n;
begin
for (n=0; n<MUX*4; n=n+1)
rows[n]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bits for column redundancy
end
endtask
task x_row;
input radd;
input bank_address;
integer n;
reg [COL_ADDR_WIDTH+1:0] tmpaddr;
begin
for (n=0; n<MUX; n=n+1)
begin
tmpaddr = n;
tmpaddr[COL_ADDR_WIDTH] = radd;
tmpaddr[COL_ADDR_WIDTH+1] = bank_address;
rows[tmpaddr]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bit for column redundancy
end
end
endtask // x_rows
task process_violations;
begin
if ((NOT_CLK_PER!==LAST_NOT_CLK_PER) ||
(NOT_CLK_MINH!==LAST_NOT_CLK_MINH) ||
(NOT_CLK_MINL!==LAST_NOT_CLK_MINL))
begin
if (LATCHED_CEN !== 1'b1)
begin
x_mem;
Qi = WORDX ;
end
end
else
begin
update_notifier_buses;
x_inputs;
mem_cycle(Qi,
dummy_qb,
LATCHED_CEN,
LATCHED_WEN,
LATCHED_A,
LATCHED_D,
LATCHED_EMA,
1'b1,
1'b1,
1'b1,
1'b1,
MASK1,
ADDR1,
WORD1,
1'b1,
1'b1,
WORD1,
1'b1,
1'b0,
WORD1,
0
);
end
update_last_notifiers;
end
endtask
function valid_address;
input [ADDR_WIDTH-1:0] a;
input rren;
input radd;
begin
if (rren === 1'b1)
valid_address = (^(a) !== 1'bx);
else if (rren === 1'b0)
valid_address = (^{radd} !== 1'bx);
else
valid_address = 0;
end
endfunction
function valid_cren;
input [BITS-1:0] cren;
reg [BITS-1:0] data;
begin
data = cren;
while (data[0] == 1'b1)
data = data >> 1;
if (~|data === 1'b1)
valid_cren = 1;
else
valid_cren = 0;
end
endfunction // valid_cren
function is_contention;
input [ADDR_WIDTH-1:0] aa;
input [ADDR_WIDTH-1:0] ab;
input [ADDR_WIDTH-1:0] taa;
input [ADDR_WIDTH-1:0] tab;
input rrena;
input rrenb;
input tena;
input tenb;
input rraa;
input rrab;
input [BITS-1:0] crena;
input [BITS-1:0] crenb;
input [RCA_WIDTH-1:0] rcaa;
input [RCA_WIDTH-1:0] rcab;
input [WEN_WIDTH-1:0] wena;
input [WEN_WIDTH-1:0] wenb;
input [WEN_WIDTH-1:0] twena;
input [WEN_WIDTH-1:0] twenb;
input cena;
input cenb;
input tcena;
input tcenb;
input artna;
input artnb;
reg [ADDR_WIDTH-1:0] adda;
reg [ADDR_WIDTH-1:0] addb;
reg [ADDR_WIDTH-1:COL_ADDR_WIDTH] row_adda;
reg [ADDR_WIDTH-1:COL_ADDR_WIDTH] row_addb;
reg add_colision;
reg col_add_colision;
reg row_add_colision;
reg rra_colision;
reg rca_colision;
reg both_ports_reading;
reg [WEN_WIDTH-1:0] wenai;
reg [WEN_WIDTH-1:0] wenbi;
begin
wenai = (tena ? wena : twena);
wenbi = (tenb ? wenb : twenb);
if ( (artna !== 1'b1) & (wenai !== MASK1) & (wenai !== MASK0))
wenai = MASKX;
if ( (artnb !== 1'b1) & (wenbi !== MASK1) & (wenbi !== MASK0))
wenbi = MASKX;
if (!valid_cren(crena))
crena = WORDX;
if (!valid_cren(crenb))
crenb = WORDX;
col_add_colision = 1'b1;
rra_colision = (rraa == rrab) | ((rraa == rrab) === 1'bx);
adda = (tena ? aa : taa);
addb = (tenb ? ab : tab);
add_colision = (adda == addb) | (^adda === 1'bx) | (^addb === 1'bx);
row_adda = (tena ? aa[ADDR_WIDTH-1:COL_ADDR_WIDTH] : taa[ADDR_WIDTH-1:COL_ADDR_WIDTH]);
row_addb = (tenb ? ab[ADDR_WIDTH-1:COL_ADDR_WIDTH] : tab[ADDR_WIDTH-1:COL_ADDR_WIDTH]);
row_add_colision = (row_adda == row_addb) | (^row_adda === 1'bx) | (^row_addb === 1'bx);
rca_colision = 1'b1;
both_ports_reading = (wenai === MASK1) &
(wenbi === MASK1);
is_contention =
// if either rrena or rrenb are unkown the whole memory is corrupted.
(((rrena === 1'bx) |
(rrenb === 1'bx) |
// in redundant row array
((rrena !== 1'b1) & (rrenb !== 1'b1) & ((rraa === 1'bx) | (rrab === 1'bx))) |
((rrena !== 1'b1) & (rrenb !== 1'b1) & col_add_colision & rra_colision) |
// in normal array
((rrena !== 1'b0) & (rrenb !== 1'b0) & add_colision) |
// redundant column in normal array
((rrena !== 1'b0) & (rrenb !== 1'b0) & row_add_colision &
(crena[BITS-1] !== 1'b1) & (crenb[BITS-1] !== 1'b1) & rca_colision) |
// redundant column in rednundant row
((rrena !== 1'b1) & (rrenb !== 1'b1) & rra_colision &
(crena[BITS-1] !== 1'b1) & (crenb[BITS-1] !== 1'b1) &
((wenai[WEN_WIDTH-1] !== 1'b1) | (wenbi[WEN_WIDTH-1] !== 1'b1)) &
rca_colision)) &
!both_ports_reading &
((tena ? cena : tcena) !== 1'b1) &
((tenb ? cenb : tcenb) !== 1'b1)) ;
end
endfunction
buf (Q[127], _Q[127]);
buf (Q[126], _Q[126]);
buf (Q[125], _Q[125]);
buf (Q[124], _Q[124]);
buf (Q[123], _Q[123]);
buf (Q[122], _Q[122]);
buf (Q[121], _Q[121]);
buf (Q[120], _Q[120]);
buf (Q[119], _Q[119]);
buf (Q[118], _Q[118]);
buf (Q[117], _Q[117]);
buf (Q[116], _Q[116]);
buf (Q[115], _Q[115]);
buf (Q[114], _Q[114]);
buf (Q[113], _Q[113]);
buf (Q[112], _Q[112]);
buf (Q[111], _Q[111]);
buf (Q[110], _Q[110]);
buf (Q[109], _Q[109]);
buf (Q[108], _Q[108]);
buf (Q[107], _Q[107]);
buf (Q[106], _Q[106]);
buf (Q[105], _Q[105]);
buf (Q[104], _Q[104]);
buf (Q[103], _Q[103]);
buf (Q[102], _Q[102]);
buf (Q[101], _Q[101]);
buf (Q[100], _Q[100]);
buf (Q[99], _Q[99]);
buf (Q[98], _Q[98]);
buf (Q[97], _Q[97]);
buf (Q[96], _Q[96]);
buf (Q[95], _Q[95]);
buf (Q[94], _Q[94]);
buf (Q[93], _Q[93]);
buf (Q[92], _Q[92]);
buf (Q[91], _Q[91]);
buf (Q[90], _Q[90]);
buf (Q[89], _Q[89]);
buf (Q[88], _Q[88]);
buf (Q[87], _Q[87]);
buf (Q[86], _Q[86]);
buf (Q[85], _Q[85]);
buf (Q[84], _Q[84]);
buf (Q[83], _Q[83]);
buf (Q[82], _Q[82]);
buf (Q[81], _Q[81]);
buf (Q[80], _Q[80]);
buf (Q[79], _Q[79]);
buf (Q[78], _Q[78]);
buf (Q[77], _Q[77]);
buf (Q[76], _Q[76]);
buf (Q[75], _Q[75]);
buf (Q[74], _Q[74]);
buf (Q[73], _Q[73]);
buf (Q[72], _Q[72]);
buf (Q[71], _Q[71]);
buf (Q[70], _Q[70]);
buf (Q[69], _Q[69]);
buf (Q[68], _Q[68]);
buf (Q[67], _Q[67]);
buf (Q[66], _Q[66]);
buf (Q[65], _Q[65]);
buf (Q[64], _Q[64]);
buf (Q[63], _Q[63]);
buf (Q[62], _Q[62]);
buf (Q[61], _Q[61]);
buf (Q[60], _Q[60]);
buf (Q[59], _Q[59]);
buf (Q[58], _Q[58]);
buf (Q[57], _Q[57]);
buf (Q[56], _Q[56]);
buf (Q[55], _Q[55]);
buf (Q[54], _Q[54]);
buf (Q[53], _Q[53]);
buf (Q[52], _Q[52]);
buf (Q[51], _Q[51]);
buf (Q[50], _Q[50]);
buf (Q[49], _Q[49]);
buf (Q[48], _Q[48]);
buf (Q[47], _Q[47]);
buf (Q[46], _Q[46]);
buf (Q[45], _Q[45]);
buf (Q[44], _Q[44]);
buf (Q[43], _Q[43]);
buf (Q[42], _Q[42]);
buf (Q[41], _Q[41]);
buf (Q[40], _Q[40]);
buf (Q[39], _Q[39]);
buf (Q[38], _Q[38]);
buf (Q[37], _Q[37]);
buf (Q[36], _Q[36]);
buf (Q[35], _Q[35]);
buf (Q[34], _Q[34]);
buf (Q[33], _Q[33]);
buf (Q[32], _Q[32]);
buf (Q[31], _Q[31]);
buf (Q[30], _Q[30]);
buf (Q[29], _Q[29]);
buf (Q[28], _Q[28]);
buf (Q[27], _Q[27]);
buf (Q[26], _Q[26]);
buf (Q[25], _Q[25]);
buf (Q[24], _Q[24]);
buf (Q[23], _Q[23]);
buf (Q[22], _Q[22]);
buf (Q[21], _Q[21]);
buf (Q[20], _Q[20]);
buf (Q[19], _Q[19]);
buf (Q[18], _Q[18]);
buf (Q[17], _Q[17]);
buf (Q[16], _Q[16]);
buf (Q[15], _Q[15]);
buf (Q[14], _Q[14]);
buf (Q[13], _Q[13]);
buf (Q[12], _Q[12]);
buf (Q[11], _Q[11]);
buf (Q[10], _Q[10]);
buf (Q[9], _Q[9]);
buf (Q[8], _Q[8]);
buf (Q[7], _Q[7]);
buf (Q[6], _Q[6]);
buf (Q[5], _Q[5]);
buf (Q[4], _Q[4]);
buf (Q[3], _Q[3]);
buf (Q[2], _Q[2]);
buf (Q[1], _Q[1]);
buf (Q[0], _Q[0]);
buf (_CLK, CLK);
buf (_CEN, CEN);
buf (_WEN, WEN);
buf (_A[4], A[4]);
buf (_A[3], A[3]);
buf (_A[2], A[2]);
buf (_A[1], A[1]);
buf (_A[0], A[0]);
buf (_D[127], D[127]);
buf (_D[126], D[126]);
buf (_D[125], D[125]);
buf (_D[124], D[124]);
buf (_D[123], D[123]);
buf (_D[122], D[122]);
buf (_D[121], D[121]);
buf (_D[120], D[120]);
buf (_D[119], D[119]);
buf (_D[118], D[118]);
buf (_D[117], D[117]);
buf (_D[116], D[116]);
buf (_D[115], D[115]);
buf (_D[114], D[114]);
buf (_D[113], D[113]);
buf (_D[112], D[112]);
buf (_D[111], D[111]);
buf (_D[110], D[110]);
buf (_D[109], D[109]);
buf (_D[108], D[108]);
buf (_D[107], D[107]);
buf (_D[106], D[106]);
buf (_D[105], D[105]);
buf (_D[104], D[104]);
buf (_D[103], D[103]);
buf (_D[102], D[102]);
buf (_D[101], D[101]);
buf (_D[100], D[100]);
buf (_D[99], D[99]);
buf (_D[98], D[98]);
buf (_D[97], D[97]);
buf (_D[96], D[96]);
buf (_D[95], D[95]);
buf (_D[94], D[94]);
buf (_D[93], D[93]);
buf (_D[92], D[92]);
buf (_D[91], D[91]);
buf (_D[90], D[90]);
buf (_D[89], D[89]);
buf (_D[88], D[88]);
buf (_D[87], D[87]);
buf (_D[86], D[86]);
buf (_D[85], D[85]);
buf (_D[84], D[84]);
buf (_D[83], D[83]);
buf (_D[82], D[82]);
buf (_D[81], D[81]);
buf (_D[80], D[80]);
buf (_D[79], D[79]);
buf (_D[78], D[78]);
buf (_D[77], D[77]);
buf (_D[76], D[76]);
buf (_D[75], D[75]);
buf (_D[74], D[74]);
buf (_D[73], D[73]);
buf (_D[72], D[72]);
buf (_D[71], D[71]);
buf (_D[70], D[70]);
buf (_D[69], D[69]);
buf (_D[68], D[68]);
buf (_D[67], D[67]);
buf (_D[66], D[66]);
buf (_D[65], D[65]);
buf (_D[64], D[64]);
buf (_D[63], D[63]);
buf (_D[62], D[62]);
buf (_D[61], D[61]);
buf (_D[60], D[60]);
buf (_D[59], D[59]);
buf (_D[58], D[58]);
buf (_D[57], D[57]);
buf (_D[56], D[56]);
buf (_D[55], D[55]);
buf (_D[54], D[54]);
buf (_D[53], D[53]);
buf (_D[52], D[52]);
buf (_D[51], D[51]);
buf (_D[50], D[50]);
buf (_D[49], D[49]);
buf (_D[48], D[48]);
buf (_D[47], D[47]);
buf (_D[46], D[46]);
buf (_D[45], D[45]);
buf (_D[44], D[44]);
buf (_D[43], D[43]);
buf (_D[42], D[42]);
buf (_D[41], D[41]);
buf (_D[40], D[40]);
buf (_D[39], D[39]);
buf (_D[38], D[38]);
buf (_D[37], D[37]);
buf (_D[36], D[36]);
buf (_D[35], D[35]);
buf (_D[34], D[34]);
buf (_D[33], D[33]);
buf (_D[32], D[32]);
buf (_D[31], D[31]);
buf (_D[30], D[30]);
buf (_D[29], D[29]);
buf (_D[28], D[28]);
buf (_D[27], D[27]);
buf (_D[26], D[26]);
buf (_D[25], D[25]);
buf (_D[24], D[24]);
buf (_D[23], D[23]);
buf (_D[22], D[22]);
buf (_D[21], D[21]);
buf (_D[20], D[20]);
buf (_D[19], D[19]);
buf (_D[18], D[18]);
buf (_D[17], D[17]);
buf (_D[16], D[16]);
buf (_D[15], D[15]);
buf (_D[14], D[14]);
buf (_D[13], D[13]);
buf (_D[12], D[12]);
buf (_D[11], D[11]);
buf (_D[10], D[10]);
buf (_D[9], D[9]);
buf (_D[8], D[8]);
buf (_D[7], D[7]);
buf (_D[6], D[6]);
buf (_D[5], D[5]);
buf (_D[4], D[4]);
buf (_D[3], D[3]);
buf (_D[2], D[2]);
buf (_D[1], D[1]);
buf (_D[0], D[0]);
buf (_EMA[2], EMA[2]);
buf (_EMA[1], EMA[1]);
buf (_EMA[0], EMA[0]);
assign _Q = Qi ;
assign CEN_flag = 1'b1; // use this for cen
assign flag = !_CEN; // use this for normal mission-mode inputs
assign D_flag = !(_CEN || _WEN);
assign cyc_flag = !_CEN; // use this for non-muxed inputs.
assign EMA2eq0andEMA1eq0andEMA0eq0 = !_EMA[2] && !_EMA[1] && !_EMA[0];
assign EMA2eq0andEMA1eq0andEMA0eq1 = !_EMA[2] && !_EMA[1] && _EMA[0];
assign EMA2eq0andEMA1eq1andEMA0eq0 = !_EMA[2] && _EMA[1] && !_EMA[0];
assign EMA2eq0andEMA1eq1andEMA0eq1 = !_EMA[2] && _EMA[1] && _EMA[0];
assign EMA2eq1andEMA1eq0andEMA0eq0 = _EMA[2] && !_EMA[1] && !_EMA[0];
assign EMA2eq1andEMA1eq0andEMA0eq1 = _EMA[2] && !_EMA[1] && _EMA[0];
assign EMA2eq1andEMA1eq1andEMA0eq0 = _EMA[2] && _EMA[1] && !_EMA[0];
assign EMA2eq1andEMA1eq1andEMA0eq1 = _EMA[2] && _EMA[1] && _EMA[0];
always @(
NOT_CEN or
NOT_WEN or
NOT_A4 or
NOT_A3 or
NOT_A2 or
NOT_A1 or
NOT_A0 or
NOT_D127 or
NOT_D126 or
NOT_D125 or
NOT_D124 or
NOT_D123 or
NOT_D122 or
NOT_D121 or
NOT_D120 or
NOT_D119 or
NOT_D118 or
NOT_D117 or
NOT_D116 or
NOT_D115 or
NOT_D114 or
NOT_D113 or
NOT_D112 or
NOT_D111 or
NOT_D110 or
NOT_D109 or
NOT_D108 or
NOT_D107 or
NOT_D106 or
NOT_D105 or
NOT_D104 or
NOT_D103 or
NOT_D102 or
NOT_D101 or
NOT_D100 or
NOT_D99 or
NOT_D98 or
NOT_D97 or
NOT_D96 or
NOT_D95 or
NOT_D94 or
NOT_D93 or
NOT_D92 or
NOT_D91 or
NOT_D90 or
NOT_D89 or
NOT_D88 or
NOT_D87 or
NOT_D86 or
NOT_D85 or
NOT_D84 or
NOT_D83 or
NOT_D82 or
NOT_D81 or
NOT_D80 or
NOT_D79 or
NOT_D78 or
NOT_D77 or
NOT_D76 or
NOT_D75 or
NOT_D74 or
NOT_D73 or
NOT_D72 or
NOT_D71 or
NOT_D70 or
NOT_D69 or
NOT_D68 or
NOT_D67 or
NOT_D66 or
NOT_D65 or
NOT_D64 or
NOT_D63 or
NOT_D62 or
NOT_D61 or
NOT_D60 or
NOT_D59 or
NOT_D58 or
NOT_D57 or
NOT_D56 or
NOT_D55 or
NOT_D54 or
NOT_D53 or
NOT_D52 or
NOT_D51 or
NOT_D50 or
NOT_D49 or
NOT_D48 or
NOT_D47 or
NOT_D46 or
NOT_D45 or
NOT_D44 or
NOT_D43 or
NOT_D42 or
NOT_D41 or
NOT_D40 or
NOT_D39 or
NOT_D38 or
NOT_D37 or
NOT_D36 or
NOT_D35 or
NOT_D34 or
NOT_D33 or
NOT_D32 or
NOT_D31 or
NOT_D30 or
NOT_D29 or
NOT_D28 or
NOT_D27 or
NOT_D26 or
NOT_D25 or
NOT_D24 or
NOT_D23 or
NOT_D22 or
NOT_D21 or
NOT_D20 or
NOT_D19 or
NOT_D18 or
NOT_D17 or
NOT_D16 or
NOT_D15 or
NOT_D14 or
NOT_D13 or
NOT_D12 or
NOT_D11 or
NOT_D10 or
NOT_D9 or
NOT_D8 or
NOT_D7 or
NOT_D6 or
NOT_D5 or
NOT_D4 or
NOT_D3 or
NOT_D2 or
NOT_D1 or
NOT_D0 or
NOT_EMA2 or
NOT_EMA1 or
NOT_EMA0 or
NOT_CLK_PER or
NOT_CLK_MINH or
NOT_CLK_MINL
)
begin
process_violations;
end
always @( _CLK )
begin
casez({LAST_CLK,_CLK})
2'b01: begin
latch_inputs;
clear_status(0);
mem_cycle(Qi,
dummy_qb,
LATCHED_CEN,
LATCHED_WEN,
LATCHED_A,
LATCHED_D,
LATCHED_EMA,
1'b1,
1'b1,
1'b1,
1'b1,
MASK1,
ADDR1,
WORD1,
1'b1,
1'b1,
WORD1,
1'b1,
1'b0,
WORD1,
0
);
end
2'b10,
2'bx?,
2'b00,
2'b11: ;
2'b?x: begin
x_mem;
Qi = WORDX ;
end
endcase
LAST_CLK = _CLK;
end
specify
$setuphold(posedge CLK &&& CEN_flag, posedge CEN, 1.000, 0.500, NOT_CEN);
$setuphold(posedge CLK &&& CEN_flag, negedge CEN, 1.000, 0.500, NOT_CEN);
$setuphold(posedge CLK &&& flag, posedge WEN, 1.000, 0.500, NOT_WEN);
$setuphold(posedge CLK &&& flag, negedge WEN, 1.000, 0.500, NOT_WEN);
$setuphold(posedge CLK &&& flag, posedge A[4], 1.000, 0.500, NOT_A4);
$setuphold(posedge CLK &&& flag, negedge A[4], 1.000, 0.500, NOT_A4);
$setuphold(posedge CLK &&& flag, posedge A[3], 1.000, 0.500, NOT_A3);
$setuphold(posedge CLK &&& flag, negedge A[3], 1.000, 0.500, NOT_A3);
$setuphold(posedge CLK &&& flag, posedge A[2], 1.000, 0.500, NOT_A2);
$setuphold(posedge CLK &&& flag, negedge A[2], 1.000, 0.500, NOT_A2);
$setuphold(posedge CLK &&& flag, posedge A[1], 1.000, 0.500, NOT_A1);
$setuphold(posedge CLK &&& flag, negedge A[1], 1.000, 0.500, NOT_A1);
$setuphold(posedge CLK &&& flag, posedge A[0], 1.000, 0.500, NOT_A0);
$setuphold(posedge CLK &&& flag, negedge A[0], 1.000, 0.500, NOT_A0);
$setuphold(posedge CLK &&& D_flag, posedge D[127], 1.000, 0.500, NOT_D127);
$setuphold(posedge CLK &&& D_flag, negedge D[127], 1.000, 0.500, NOT_D127);
$setuphold(posedge CLK &&& D_flag, posedge D[126], 1.000, 0.500, NOT_D126);
$setuphold(posedge CLK &&& D_flag, negedge D[126], 1.000, 0.500, NOT_D126);
$setuphold(posedge CLK &&& D_flag, posedge D[125], 1.000, 0.500, NOT_D125);
$setuphold(posedge CLK &&& D_flag, negedge D[125], 1.000, 0.500, NOT_D125);
$setuphold(posedge CLK &&& D_flag, posedge D[124], 1.000, 0.500, NOT_D124);
$setuphold(posedge CLK &&& D_flag, negedge D[124], 1.000, 0.500, NOT_D124);
$setuphold(posedge CLK &&& D_flag, posedge D[123], 1.000, 0.500, NOT_D123);
$setuphold(posedge CLK &&& D_flag, negedge D[123], 1.000, 0.500, NOT_D123);
$setuphold(posedge CLK &&& D_flag, posedge D[122], 1.000, 0.500, NOT_D122);
$setuphold(posedge CLK &&& D_flag, negedge D[122], 1.000, 0.500, NOT_D122);
$setuphold(posedge CLK &&& D_flag, posedge D[121], 1.000, 0.500, NOT_D121);
$setuphold(posedge CLK &&& D_flag, negedge D[121], 1.000, 0.500, NOT_D121);
$setuphold(posedge CLK &&& D_flag, posedge D[120], 1.000, 0.500, NOT_D120);
$setuphold(posedge CLK &&& D_flag, negedge D[120], 1.000, 0.500, NOT_D120);
$setuphold(posedge CLK &&& D_flag, posedge D[119], 1.000, 0.500, NOT_D119);
$setuphold(posedge CLK &&& D_flag, negedge D[119], 1.000, 0.500, NOT_D119);
$setuphold(posedge CLK &&& D_flag, posedge D[118], 1.000, 0.500, NOT_D118);
$setuphold(posedge CLK &&& D_flag, negedge D[118], 1.000, 0.500, NOT_D118);
$setuphold(posedge CLK &&& D_flag, posedge D[117], 1.000, 0.500, NOT_D117);
$setuphold(posedge CLK &&& D_flag, negedge D[117], 1.000, 0.500, NOT_D117);
$setuphold(posedge CLK &&& D_flag, posedge D[116], 1.000, 0.500, NOT_D116);
$setuphold(posedge CLK &&& D_flag, negedge D[116], 1.000, 0.500, NOT_D116);
$setuphold(posedge CLK &&& D_flag, posedge D[115], 1.000, 0.500, NOT_D115);
$setuphold(posedge CLK &&& D_flag, negedge D[115], 1.000, 0.500, NOT_D115);
$setuphold(posedge CLK &&& D_flag, posedge D[114], 1.000, 0.500, NOT_D114);
$setuphold(posedge CLK &&& D_flag, negedge D[114], 1.000, 0.500, NOT_D114);
$setuphold(posedge CLK &&& D_flag, posedge D[113], 1.000, 0.500, NOT_D113);
$setuphold(posedge CLK &&& D_flag, negedge D[113], 1.000, 0.500, NOT_D113);
$setuphold(posedge CLK &&& D_flag, posedge D[112], 1.000, 0.500, NOT_D112);
$setuphold(posedge CLK &&& D_flag, negedge D[112], 1.000, 0.500, NOT_D112);
$setuphold(posedge CLK &&& D_flag, posedge D[111], 1.000, 0.500, NOT_D111);
$setuphold(posedge CLK &&& D_flag, negedge D[111], 1.000, 0.500, NOT_D111);
$setuphold(posedge CLK &&& D_flag, posedge D[110], 1.000, 0.500, NOT_D110);
$setuphold(posedge CLK &&& D_flag, negedge D[110], 1.000, 0.500, NOT_D110);
$setuphold(posedge CLK &&& D_flag, posedge D[109], 1.000, 0.500, NOT_D109);
$setuphold(posedge CLK &&& D_flag, negedge D[109], 1.000, 0.500, NOT_D109);
$setuphold(posedge CLK &&& D_flag, posedge D[108], 1.000, 0.500, NOT_D108);
$setuphold(posedge CLK &&& D_flag, negedge D[108], 1.000, 0.500, NOT_D108);
$setuphold(posedge CLK &&& D_flag, posedge D[107], 1.000, 0.500, NOT_D107);
$setuphold(posedge CLK &&& D_flag, negedge D[107], 1.000, 0.500, NOT_D107);
$setuphold(posedge CLK &&& D_flag, posedge D[106], 1.000, 0.500, NOT_D106);
$setuphold(posedge CLK &&& D_flag, negedge D[106], 1.000, 0.500, NOT_D106);
$setuphold(posedge CLK &&& D_flag, posedge D[105], 1.000, 0.500, NOT_D105);
$setuphold(posedge CLK &&& D_flag, negedge D[105], 1.000, 0.500, NOT_D105);
$setuphold(posedge CLK &&& D_flag, posedge D[104], 1.000, 0.500, NOT_D104);
$setuphold(posedge CLK &&& D_flag, negedge D[104], 1.000, 0.500, NOT_D104);
$setuphold(posedge CLK &&& D_flag, posedge D[103], 1.000, 0.500, NOT_D103);
$setuphold(posedge CLK &&& D_flag, negedge D[103], 1.000, 0.500, NOT_D103);
$setuphold(posedge CLK &&& D_flag, posedge D[102], 1.000, 0.500, NOT_D102);
$setuphold(posedge CLK &&& D_flag, negedge D[102], 1.000, 0.500, NOT_D102);
$setuphold(posedge CLK &&& D_flag, posedge D[101], 1.000, 0.500, NOT_D101);
$setuphold(posedge CLK &&& D_flag, negedge D[101], 1.000, 0.500, NOT_D101);
$setuphold(posedge CLK &&& D_flag, posedge D[100], 1.000, 0.500, NOT_D100);
$setuphold(posedge CLK &&& D_flag, negedge D[100], 1.000, 0.500, NOT_D100);
$setuphold(posedge CLK &&& D_flag, posedge D[99], 1.000, 0.500, NOT_D99);
$setuphold(posedge CLK &&& D_flag, negedge D[99], 1.000, 0.500, NOT_D99);
$setuphold(posedge CLK &&& D_flag, posedge D[98], 1.000, 0.500, NOT_D98);
$setuphold(posedge CLK &&& D_flag, negedge D[98], 1.000, 0.500, NOT_D98);
$setuphold(posedge CLK &&& D_flag, posedge D[97], 1.000, 0.500, NOT_D97);
$setuphold(posedge CLK &&& D_flag, negedge D[97], 1.000, 0.500, NOT_D97);
$setuphold(posedge CLK &&& D_flag, posedge D[96], 1.000, 0.500, NOT_D96);
$setuphold(posedge CLK &&& D_flag, negedge D[96], 1.000, 0.500, NOT_D96);
$setuphold(posedge CLK &&& D_flag, posedge D[95], 1.000, 0.500, NOT_D95);
$setuphold(posedge CLK &&& D_flag, negedge D[95], 1.000, 0.500, NOT_D95);
$setuphold(posedge CLK &&& D_flag, posedge D[94], 1.000, 0.500, NOT_D94);
$setuphold(posedge CLK &&& D_flag, negedge D[94], 1.000, 0.500, NOT_D94);
$setuphold(posedge CLK &&& D_flag, posedge D[93], 1.000, 0.500, NOT_D93);
$setuphold(posedge CLK &&& D_flag, negedge D[93], 1.000, 0.500, NOT_D93);
$setuphold(posedge CLK &&& D_flag, posedge D[92], 1.000, 0.500, NOT_D92);
$setuphold(posedge CLK &&& D_flag, negedge D[92], 1.000, 0.500, NOT_D92);
$setuphold(posedge CLK &&& D_flag, posedge D[91], 1.000, 0.500, NOT_D91);
$setuphold(posedge CLK &&& D_flag, negedge D[91], 1.000, 0.500, NOT_D91);
$setuphold(posedge CLK &&& D_flag, posedge D[90], 1.000, 0.500, NOT_D90);
$setuphold(posedge CLK &&& D_flag, negedge D[90], 1.000, 0.500, NOT_D90);
$setuphold(posedge CLK &&& D_flag, posedge D[89], 1.000, 0.500, NOT_D89);
$setuphold(posedge CLK &&& D_flag, negedge D[89], 1.000, 0.500, NOT_D89);
$setuphold(posedge CLK &&& D_flag, posedge D[88], 1.000, 0.500, NOT_D88);
$setuphold(posedge CLK &&& D_flag, negedge D[88], 1.000, 0.500, NOT_D88);
$setuphold(posedge CLK &&& D_flag, posedge D[87], 1.000, 0.500, NOT_D87);
$setuphold(posedge CLK &&& D_flag, negedge D[87], 1.000, 0.500, NOT_D87);
$setuphold(posedge CLK &&& D_flag, posedge D[86], 1.000, 0.500, NOT_D86);
$setuphold(posedge CLK &&& D_flag, negedge D[86], 1.000, 0.500, NOT_D86);
$setuphold(posedge CLK &&& D_flag, posedge D[85], 1.000, 0.500, NOT_D85);
$setuphold(posedge CLK &&& D_flag, negedge D[85], 1.000, 0.500, NOT_D85);
$setuphold(posedge CLK &&& D_flag, posedge D[84], 1.000, 0.500, NOT_D84);
$setuphold(posedge CLK &&& D_flag, negedge D[84], 1.000, 0.500, NOT_D84);
$setuphold(posedge CLK &&& D_flag, posedge D[83], 1.000, 0.500, NOT_D83);
$setuphold(posedge CLK &&& D_flag, negedge D[83], 1.000, 0.500, NOT_D83);
$setuphold(posedge CLK &&& D_flag, posedge D[82], 1.000, 0.500, NOT_D82);
$setuphold(posedge CLK &&& D_flag, negedge D[82], 1.000, 0.500, NOT_D82);
$setuphold(posedge CLK &&& D_flag, posedge D[81], 1.000, 0.500, NOT_D81);
$setuphold(posedge CLK &&& D_flag, negedge D[81], 1.000, 0.500, NOT_D81);
$setuphold(posedge CLK &&& D_flag, posedge D[80], 1.000, 0.500, NOT_D80);
$setuphold(posedge CLK &&& D_flag, negedge D[80], 1.000, 0.500, NOT_D80);
$setuphold(posedge CLK &&& D_flag, posedge D[79], 1.000, 0.500, NOT_D79);
$setuphold(posedge CLK &&& D_flag, negedge D[79], 1.000, 0.500, NOT_D79);
$setuphold(posedge CLK &&& D_flag, posedge D[78], 1.000, 0.500, NOT_D78);
$setuphold(posedge CLK &&& D_flag, negedge D[78], 1.000, 0.500, NOT_D78);
$setuphold(posedge CLK &&& D_flag, posedge D[77], 1.000, 0.500, NOT_D77);
$setuphold(posedge CLK &&& D_flag, negedge D[77], 1.000, 0.500, NOT_D77);
$setuphold(posedge CLK &&& D_flag, posedge D[76], 1.000, 0.500, NOT_D76);
$setuphold(posedge CLK &&& D_flag, negedge D[76], 1.000, 0.500, NOT_D76);
$setuphold(posedge CLK &&& D_flag, posedge D[75], 1.000, 0.500, NOT_D75);
$setuphold(posedge CLK &&& D_flag, negedge D[75], 1.000, 0.500, NOT_D75);
$setuphold(posedge CLK &&& D_flag, posedge D[74], 1.000, 0.500, NOT_D74);
$setuphold(posedge CLK &&& D_flag, negedge D[74], 1.000, 0.500, NOT_D74);
$setuphold(posedge CLK &&& D_flag, posedge D[73], 1.000, 0.500, NOT_D73);
$setuphold(posedge CLK &&& D_flag, negedge D[73], 1.000, 0.500, NOT_D73);
$setuphold(posedge CLK &&& D_flag, posedge D[72], 1.000, 0.500, NOT_D72);
$setuphold(posedge CLK &&& D_flag, negedge D[72], 1.000, 0.500, NOT_D72);
$setuphold(posedge CLK &&& D_flag, posedge D[71], 1.000, 0.500, NOT_D71);
$setuphold(posedge CLK &&& D_flag, negedge D[71], 1.000, 0.500, NOT_D71);
$setuphold(posedge CLK &&& D_flag, posedge D[70], 1.000, 0.500, NOT_D70);
$setuphold(posedge CLK &&& D_flag, negedge D[70], 1.000, 0.500, NOT_D70);
$setuphold(posedge CLK &&& D_flag, posedge D[69], 1.000, 0.500, NOT_D69);
$setuphold(posedge CLK &&& D_flag, negedge D[69], 1.000, 0.500, NOT_D69);
$setuphold(posedge CLK &&& D_flag, posedge D[68], 1.000, 0.500, NOT_D68);
$setuphold(posedge CLK &&& D_flag, negedge D[68], 1.000, 0.500, NOT_D68);
$setuphold(posedge CLK &&& D_flag, posedge D[67], 1.000, 0.500, NOT_D67);
$setuphold(posedge CLK &&& D_flag, negedge D[67], 1.000, 0.500, NOT_D67);
$setuphold(posedge CLK &&& D_flag, posedge D[66], 1.000, 0.500, NOT_D66);
$setuphold(posedge CLK &&& D_flag, negedge D[66], 1.000, 0.500, NOT_D66);
$setuphold(posedge CLK &&& D_flag, posedge D[65], 1.000, 0.500, NOT_D65);
$setuphold(posedge CLK &&& D_flag, negedge D[65], 1.000, 0.500, NOT_D65);
$setuphold(posedge CLK &&& D_flag, posedge D[64], 1.000, 0.500, NOT_D64);
$setuphold(posedge CLK &&& D_flag, negedge D[64], 1.000, 0.500, NOT_D64);
$setuphold(posedge CLK &&& D_flag, posedge D[63], 1.000, 0.500, NOT_D63);
$setuphold(posedge CLK &&& D_flag, negedge D[63], 1.000, 0.500, NOT_D63);
$setuphold(posedge CLK &&& D_flag, posedge D[62], 1.000, 0.500, NOT_D62);
$setuphold(posedge CLK &&& D_flag, negedge D[62], 1.000, 0.500, NOT_D62);
$setuphold(posedge CLK &&& D_flag, posedge D[61], 1.000, 0.500, NOT_D61);
$setuphold(posedge CLK &&& D_flag, negedge D[61], 1.000, 0.500, NOT_D61);
$setuphold(posedge CLK &&& D_flag, posedge D[60], 1.000, 0.500, NOT_D60);
$setuphold(posedge CLK &&& D_flag, negedge D[60], 1.000, 0.500, NOT_D60);
$setuphold(posedge CLK &&& D_flag, posedge D[59], 1.000, 0.500, NOT_D59);
$setuphold(posedge CLK &&& D_flag, negedge D[59], 1.000, 0.500, NOT_D59);
$setuphold(posedge CLK &&& D_flag, posedge D[58], 1.000, 0.500, NOT_D58);
$setuphold(posedge CLK &&& D_flag, negedge D[58], 1.000, 0.500, NOT_D58);
$setuphold(posedge CLK &&& D_flag, posedge D[57], 1.000, 0.500, NOT_D57);
$setuphold(posedge CLK &&& D_flag, negedge D[57], 1.000, 0.500, NOT_D57);
$setuphold(posedge CLK &&& D_flag, posedge D[56], 1.000, 0.500, NOT_D56);
$setuphold(posedge CLK &&& D_flag, negedge D[56], 1.000, 0.500, NOT_D56);
$setuphold(posedge CLK &&& D_flag, posedge D[55], 1.000, 0.500, NOT_D55);
$setuphold(posedge CLK &&& D_flag, negedge D[55], 1.000, 0.500, NOT_D55);
$setuphold(posedge CLK &&& D_flag, posedge D[54], 1.000, 0.500, NOT_D54);
$setuphold(posedge CLK &&& D_flag, negedge D[54], 1.000, 0.500, NOT_D54);
$setuphold(posedge CLK &&& D_flag, posedge D[53], 1.000, 0.500, NOT_D53);
$setuphold(posedge CLK &&& D_flag, negedge D[53], 1.000, 0.500, NOT_D53);
$setuphold(posedge CLK &&& D_flag, posedge D[52], 1.000, 0.500, NOT_D52);
$setuphold(posedge CLK &&& D_flag, negedge D[52], 1.000, 0.500, NOT_D52);
$setuphold(posedge CLK &&& D_flag, posedge D[51], 1.000, 0.500, NOT_D51);
$setuphold(posedge CLK &&& D_flag, negedge D[51], 1.000, 0.500, NOT_D51);
$setuphold(posedge CLK &&& D_flag, posedge D[50], 1.000, 0.500, NOT_D50);
$setuphold(posedge CLK &&& D_flag, negedge D[50], 1.000, 0.500, NOT_D50);
$setuphold(posedge CLK &&& D_flag, posedge D[49], 1.000, 0.500, NOT_D49);
$setuphold(posedge CLK &&& D_flag, negedge D[49], 1.000, 0.500, NOT_D49);
$setuphold(posedge CLK &&& D_flag, posedge D[48], 1.000, 0.500, NOT_D48);
$setuphold(posedge CLK &&& D_flag, negedge D[48], 1.000, 0.500, NOT_D48);
$setuphold(posedge CLK &&& D_flag, posedge D[47], 1.000, 0.500, NOT_D47);
$setuphold(posedge CLK &&& D_flag, negedge D[47], 1.000, 0.500, NOT_D47);
$setuphold(posedge CLK &&& D_flag, posedge D[46], 1.000, 0.500, NOT_D46);
$setuphold(posedge CLK &&& D_flag, negedge D[46], 1.000, 0.500, NOT_D46);
$setuphold(posedge CLK &&& D_flag, posedge D[45], 1.000, 0.500, NOT_D45);
$setuphold(posedge CLK &&& D_flag, negedge D[45], 1.000, 0.500, NOT_D45);
$setuphold(posedge CLK &&& D_flag, posedge D[44], 1.000, 0.500, NOT_D44);
$setuphold(posedge CLK &&& D_flag, negedge D[44], 1.000, 0.500, NOT_D44);
$setuphold(posedge CLK &&& D_flag, posedge D[43], 1.000, 0.500, NOT_D43);
$setuphold(posedge CLK &&& D_flag, negedge D[43], 1.000, 0.500, NOT_D43);
$setuphold(posedge CLK &&& D_flag, posedge D[42], 1.000, 0.500, NOT_D42);
$setuphold(posedge CLK &&& D_flag, negedge D[42], 1.000, 0.500, NOT_D42);
$setuphold(posedge CLK &&& D_flag, posedge D[41], 1.000, 0.500, NOT_D41);
$setuphold(posedge CLK &&& D_flag, negedge D[41], 1.000, 0.500, NOT_D41);
$setuphold(posedge CLK &&& D_flag, posedge D[40], 1.000, 0.500, NOT_D40);
$setuphold(posedge CLK &&& D_flag, negedge D[40], 1.000, 0.500, NOT_D40);
$setuphold(posedge CLK &&& D_flag, posedge D[39], 1.000, 0.500, NOT_D39);
$setuphold(posedge CLK &&& D_flag, negedge D[39], 1.000, 0.500, NOT_D39);
$setuphold(posedge CLK &&& D_flag, posedge D[38], 1.000, 0.500, NOT_D38);
$setuphold(posedge CLK &&& D_flag, negedge D[38], 1.000, 0.500, NOT_D38);
$setuphold(posedge CLK &&& D_flag, posedge D[37], 1.000, 0.500, NOT_D37);
$setuphold(posedge CLK &&& D_flag, negedge D[37], 1.000, 0.500, NOT_D37);
$setuphold(posedge CLK &&& D_flag, posedge D[36], 1.000, 0.500, NOT_D36);
$setuphold(posedge CLK &&& D_flag, negedge D[36], 1.000, 0.500, NOT_D36);
$setuphold(posedge CLK &&& D_flag, posedge D[35], 1.000, 0.500, NOT_D35);
$setuphold(posedge CLK &&& D_flag, negedge D[35], 1.000, 0.500, NOT_D35);
$setuphold(posedge CLK &&& D_flag, posedge D[34], 1.000, 0.500, NOT_D34);
$setuphold(posedge CLK &&& D_flag, negedge D[34], 1.000, 0.500, NOT_D34);
$setuphold(posedge CLK &&& D_flag, posedge D[33], 1.000, 0.500, NOT_D33);
$setuphold(posedge CLK &&& D_flag, negedge D[33], 1.000, 0.500, NOT_D33);
$setuphold(posedge CLK &&& D_flag, posedge D[32], 1.000, 0.500, NOT_D32);
$setuphold(posedge CLK &&& D_flag, negedge D[32], 1.000, 0.500, NOT_D32);
$setuphold(posedge CLK &&& D_flag, posedge D[31], 1.000, 0.500, NOT_D31);
$setuphold(posedge CLK &&& D_flag, negedge D[31], 1.000, 0.500, NOT_D31);
$setuphold(posedge CLK &&& D_flag, posedge D[30], 1.000, 0.500, NOT_D30);
$setuphold(posedge CLK &&& D_flag, negedge D[30], 1.000, 0.500, NOT_D30);
$setuphold(posedge CLK &&& D_flag, posedge D[29], 1.000, 0.500, NOT_D29);
$setuphold(posedge CLK &&& D_flag, negedge D[29], 1.000, 0.500, NOT_D29);
$setuphold(posedge CLK &&& D_flag, posedge D[28], 1.000, 0.500, NOT_D28);
$setuphold(posedge CLK &&& D_flag, negedge D[28], 1.000, 0.500, NOT_D28);
$setuphold(posedge CLK &&& D_flag, posedge D[27], 1.000, 0.500, NOT_D27);
$setuphold(posedge CLK &&& D_flag, negedge D[27], 1.000, 0.500, NOT_D27);
$setuphold(posedge CLK &&& D_flag, posedge D[26], 1.000, 0.500, NOT_D26);
$setuphold(posedge CLK &&& D_flag, negedge D[26], 1.000, 0.500, NOT_D26);
$setuphold(posedge CLK &&& D_flag, posedge D[25], 1.000, 0.500, NOT_D25);
$setuphold(posedge CLK &&& D_flag, negedge D[25], 1.000, 0.500, NOT_D25);
$setuphold(posedge CLK &&& D_flag, posedge D[24], 1.000, 0.500, NOT_D24);
$setuphold(posedge CLK &&& D_flag, negedge D[24], 1.000, 0.500, NOT_D24);
$setuphold(posedge CLK &&& D_flag, posedge D[23], 1.000, 0.500, NOT_D23);
$setuphold(posedge CLK &&& D_flag, negedge D[23], 1.000, 0.500, NOT_D23);
$setuphold(posedge CLK &&& D_flag, posedge D[22], 1.000, 0.500, NOT_D22);
$setuphold(posedge CLK &&& D_flag, negedge D[22], 1.000, 0.500, NOT_D22);
$setuphold(posedge CLK &&& D_flag, posedge D[21], 1.000, 0.500, NOT_D21);
$setuphold(posedge CLK &&& D_flag, negedge D[21], 1.000, 0.500, NOT_D21);
$setuphold(posedge CLK &&& D_flag, posedge D[20], 1.000, 0.500, NOT_D20);
$setuphold(posedge CLK &&& D_flag, negedge D[20], 1.000, 0.500, NOT_D20);
$setuphold(posedge CLK &&& D_flag, posedge D[19], 1.000, 0.500, NOT_D19);
$setuphold(posedge CLK &&& D_flag, negedge D[19], 1.000, 0.500, NOT_D19);
$setuphold(posedge CLK &&& D_flag, posedge D[18], 1.000, 0.500, NOT_D18);
$setuphold(posedge CLK &&& D_flag, negedge D[18], 1.000, 0.500, NOT_D18);
$setuphold(posedge CLK &&& D_flag, posedge D[17], 1.000, 0.500, NOT_D17);
$setuphold(posedge CLK &&& D_flag, negedge D[17], 1.000, 0.500, NOT_D17);
$setuphold(posedge CLK &&& D_flag, posedge D[16], 1.000, 0.500, NOT_D16);
$setuphold(posedge CLK &&& D_flag, negedge D[16], 1.000, 0.500, NOT_D16);
$setuphold(posedge CLK &&& D_flag, posedge D[15], 1.000, 0.500, NOT_D15);
$setuphold(posedge CLK &&& D_flag, negedge D[15], 1.000, 0.500, NOT_D15);
$setuphold(posedge CLK &&& D_flag, posedge D[14], 1.000, 0.500, NOT_D14);
$setuphold(posedge CLK &&& D_flag, negedge D[14], 1.000, 0.500, NOT_D14);
$setuphold(posedge CLK &&& D_flag, posedge D[13], 1.000, 0.500, NOT_D13);
$setuphold(posedge CLK &&& D_flag, negedge D[13], 1.000, 0.500, NOT_D13);
$setuphold(posedge CLK &&& D_flag, posedge D[12], 1.000, 0.500, NOT_D12);
$setuphold(posedge CLK &&& D_flag, negedge D[12], 1.000, 0.500, NOT_D12);
$setuphold(posedge CLK &&& D_flag, posedge D[11], 1.000, 0.500, NOT_D11);
$setuphold(posedge CLK &&& D_flag, negedge D[11], 1.000, 0.500, NOT_D11);
$setuphold(posedge CLK &&& D_flag, posedge D[10], 1.000, 0.500, NOT_D10);
$setuphold(posedge CLK &&& D_flag, negedge D[10], 1.000, 0.500, NOT_D10);
$setuphold(posedge CLK &&& D_flag, posedge D[9], 1.000, 0.500, NOT_D9);
$setuphold(posedge CLK &&& D_flag, negedge D[9], 1.000, 0.500, NOT_D9);
$setuphold(posedge CLK &&& D_flag, posedge D[8], 1.000, 0.500, NOT_D8);
$setuphold(posedge CLK &&& D_flag, negedge D[8], 1.000, 0.500, NOT_D8);
$setuphold(posedge CLK &&& D_flag, posedge D[7], 1.000, 0.500, NOT_D7);
$setuphold(posedge CLK &&& D_flag, negedge D[7], 1.000, 0.500, NOT_D7);
$setuphold(posedge CLK &&& D_flag, posedge D[6], 1.000, 0.500, NOT_D6);
$setuphold(posedge CLK &&& D_flag, negedge D[6], 1.000, 0.500, NOT_D6);
$setuphold(posedge CLK &&& D_flag, posedge D[5], 1.000, 0.500, NOT_D5);
$setuphold(posedge CLK &&& D_flag, negedge D[5], 1.000, 0.500, NOT_D5);
$setuphold(posedge CLK &&& D_flag, posedge D[4], 1.000, 0.500, NOT_D4);
$setuphold(posedge CLK &&& D_flag, negedge D[4], 1.000, 0.500, NOT_D4);
$setuphold(posedge CLK &&& D_flag, posedge D[3], 1.000, 0.500, NOT_D3);
$setuphold(posedge CLK &&& D_flag, negedge D[3], 1.000, 0.500, NOT_D3);
$setuphold(posedge CLK &&& D_flag, posedge D[2], 1.000, 0.500, NOT_D2);
$setuphold(posedge CLK &&& D_flag, negedge D[2], 1.000, 0.500, NOT_D2);
$setuphold(posedge CLK &&& D_flag, posedge D[1], 1.000, 0.500, NOT_D1);
$setuphold(posedge CLK &&& D_flag, negedge D[1], 1.000, 0.500, NOT_D1);
$setuphold(posedge CLK &&& D_flag, posedge D[0], 1.000, 0.500, NOT_D0);
$setuphold(posedge CLK &&& D_flag, negedge D[0], 1.000, 0.500, NOT_D0);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[2], 1.000, 0.500, NOT_EMA2);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[2], 1.000, 0.500, NOT_EMA2);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[1], 1.000, 0.500, NOT_EMA1);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[1], 1.000, 0.500, NOT_EMA1);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[0], 1.000, 0.500, NOT_EMA0);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[0], 1.000, 0.500, NOT_EMA0);
$width(posedge CLK, 1.000, 0, NOT_CLK_MINH);
$width(negedge CLK, 1.000, 0, NOT_CLK_MINL);
`ifdef NO_SDTC
$period(posedge CLK, 3.000, NOT_CLK_PER);
`else
$period(posedge CLK &&& EMA2eq0andEMA1eq0andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq0andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq1andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq1andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq0andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq0andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq1andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq1andEMA0eq1, 3.000, NOT_CLK_PER);
`endif
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[127])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[126])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[125])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[124])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[123])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[122])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[121])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[120])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[119])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[118])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[117])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[116])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[115])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[114])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[113])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[112])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[111])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[110])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[109])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[108])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[107])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[106])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[105])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[104])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[103])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[102])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[101])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[100])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[99])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[98])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[97])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[96])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[95])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[94])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[93])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[92])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[91])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[90])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[89])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[88])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[87])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[86])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[85])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[84])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[83])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[82])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[81])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[80])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[79])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[78])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[77])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[76])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[75])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[74])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[73])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[72])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[71])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[70])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[69])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[68])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[67])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[66])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[65])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[64])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[63])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[62])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[61])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[60])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[59])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[58])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[57])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[56])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[55])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[54])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[53])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[52])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[51])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[50])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[49])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[48])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[47])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[46])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[45])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[44])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[43])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[42])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[41])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[40])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[39])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[38])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[37])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[36])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[35])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[34])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[33])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[32])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
endspecify
endmodule
`endcelldefine
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