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//--------------------------------------------------------------------------------
// Project : SWITCH
// File : v7_enet_top.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Merged Ethernet Controller Top File for V7
//
//--------------------------------------------------------------------------------
module ethernet_top(
input i_rst,
input i_clk_125,
input i_clk_200,
output phy_resetn,
// V6 GMII I/F
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
output gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
input gmii_col,
input gmii_crs,
input mii_tx_clk,
// V7 SGMII I/F
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// PHY MDIO I/F
output mdio_out,
input mdio_in,
output mdc_out,
output mdio_t,
//Reg file
input i_enet_enable, // Enable the ethernet core
input i_enet_loopback, // Enable loopback mode
input [31:0] i_enet_ddr_source_addr, // Where is data for ethernet
input [31:0] i_enet_ddr_dest_addr, // Where to store ethernet data
input [31:0] i_enet_rcv_data_size, // How much data should be received from enet
input [31:0] i_enet_snd_data_size, // How much data should be sent through enet
output [31:0] o_enet_rx_cnt, // Ethernet RX Performance Counter
output [31:0] o_enet_tx_cnt, // Ethernet TX Performance Counter
output o_enet_rx_done, // Ethernet RX Completed
output o_enet_tx_done, // Ethernet TX Completed
//To DDR controller
output o_ddr_wr_req,
output o_ddr_rd_req,
output [255:0] o_ddr_wr_data,
output [31:0] o_ddr_wr_be,
output [31:0] o_ddr_wr_addr,
output [31:0] o_ddr_rd_addr,
input [255:0] i_ddr_rd_data,
input i_ddr_wr_ack,
input i_ddr_rd_ack,
input i_ddr_rd_data_valid
);
// Instantiate V7 Top File
v7_ethernet_top v7_et
(
.glbl_rst(i_rst),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_in),
.mdio_o(mdio_out),
.mdio_t(mdio_t),
.mdc(mdc_out),
.i_enet_enable(i_enet_enable),
.i_enet_loopback(i_enet_loopback),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid)
);
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* TIMER A */
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer clock input mux. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
integer my_counter;
always @ (negedge mclk)
my_counter <= my_counter+1;
wire [15:0] tar = timerA_0.tar;
// Generate TACLK as MCLK/3
integer taclk_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taclk_cnt <= 0;
else if (taclk_cnt==2) taclk_cnt <= 0;
else taclk_cnt <= taclk_cnt+1;
always @ (taclk_cnt)
if (taclk_cnt==2) taclk = 1'b1;
else taclk = 1'b0;
// Generate INCLK as MCLK/5
integer inclk_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) inclk_cnt <= 0;
else if (inclk_cnt==4) inclk_cnt <= 0;
else inclk_cnt <= inclk_cnt+1;
always @ (inclk_cnt)
if (inclk_cnt==4) inclk = 1'b1;
else inclk = 1'b0;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef ASIC_CLOCKING
tb_skip_finish("| (this test is not supported in ASIC mode) |");
`else
// TIMER A TEST: INPUT MUX - TACLK
//--------------------------------------------------------
// @(r15 === 16'h0000);
@(r15 === 16'h0001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0032) tb_error("====== TIMER A TEST: INPUT MUX - TACLK =====");
// TIMER A TEST: INPUT MUX - ACLK
//--------------------------------------------------------
@(r15 === 16'h1000);
@(r15 === 16'h1001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0005) tb_error("====== TIMER A TEST: INPUT MUX - ACLK =====");
// TIMER A TEST: INPUT MUX - SMCLK
//--------------------------------------------------------
@(r15 === 16'h2000);
@(r15 === 16'h2001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0013) tb_error("====== TIMER A TEST: INPUT MUX - SMCLK =====");
// TIMER A TEST: INPUT MUX - INCLK
//--------------------------------------------------------
@(r15 === 16'h3000);
@(r15 === 16'h3001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h001E) tb_error("====== TIMER A TEST: INPUT MUX - INCLK =====");
`endif
stimulus_done = 1;
end
|
`timescale 1ns/10ps
`include "pipeconnect.h"
`define TARGET_LOG 0
`define READER_LOG 1
`define WRITER_LOG 1
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
parameter name = 1;
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
if (`TARGET_LOG & req`R)
$display("Target%1d", name);
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
parameter name = 1;
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
if (`TARGET_LOG & req`R & ready)
$display("Target%1d", name);
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module reader
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
parameter name = 1;
reg [31:0] counter, data;
reg [31:0] dataExpect;
reg dataValid;
wire pause = ^counter[1:0];
always @(posedge clk)
if (rst) begin
counter <= name << 16;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataExpect <= data;
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD) begin
if (`READER_LOG)
$display("%6d init%1d got %x, expected %x !!! BAD!",
$time, name, res`RD, dataExpect);
end else begin
if (`READER_LOG)
$display("%6d init%1d got %x as expected", $time, name, res`RD);
end
end
if (~res`WAIT) begin
counter <= counter + name;
if (pause) begin
req`R <= 0;
end else begin
req`R <= 1;
req`A <= counter;
data <= counter;
if (`READER_LOG)
$display("%6d init%1d requests %x", $time, name, counter);
end
end else begin
if (`READER_LOG)
$display("%6d init%1d waits", $time, name);
end
end
endmodule
module writer
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
parameter name = 1;
reg [31:0] counter, data;
wire pause = ^counter[2:1];
always @(posedge clk)
if (rst) begin
counter <= name << 16;
req <= 0;
end else begin
if (~res`WAIT) begin
counter <= counter + name;
if (pause) begin
req`W <= 0;
end else begin
req`W <= 1;
req`A <= counter;
req`WD <= counter;
if (`WRITER_LOG)
$display("%6d writer%1d requests %x", $time, name, counter);
end
end else begin
if (`WRITER_LOG)
$display("%6d writer%1d waits", $time, name);
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req, req1, req2, reqA, reqB;
wire `RES res, res1, res2, resA, resB;
wire [31:0] addr1 = req1`A;
wire read1 = req1`R;
wire wai1 = res1`WAIT;
wire [31:0] data1 = res1`RD;
wire [31:0] addr2 = req2`A;
wire read2 = req2`R;
wire wai2 = res2`WAIT;
wire [31:0] data2 = res2`RD;
reader #(1) reader1(clk, rst, req1, res1);
writer #(2) writer2(clk, rst, req2, res2);
slowtarget #(1) target1(clk, rst, reqA, resA);
slowtarget #(2) target2(clk, rst, reqB, resB);
xbar2x2 xbar(clk,
addr1[2], req1, res1,
addr2[2], req2, res2,
reqA, resA,
reqB, resB);
always # 5 clk = ~clk;
initial begin
$monitor(// "%d%d %4d 1: %x %d %d %x 2: %x %d %d %x",
"%4d 1: %x %d %d %x 2: %x %d %d %x",
// rst, clk,
$time,
addr1, read1, wai1, data1,
addr2, read2, wai2, data2);
clk = 1;
rst = 1;
#15 rst = 0;
#20000 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_4_V
`define SKY130_FD_SC_MS__BUF_4_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_4_V
|
`timescale 1ns / 1ps
`default_nettype none //To avoid bugs involving implicit nets
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Acknowledgements: Prof. Kyle Gilsdorf (Arizona State)
// - http://www.public.asu.edu/~kyle135/
// - [email protected]
//
//
// Author: Rushang Vinod Vandana Karia
// - Masters in Computer Science @ Arizona State
// - [email protected]
// - 4806283130
// - github.com/RushangKaria
//
//
// Module: TftCtl.v
//
//
// Description : TFT display controller.
//
// Copyright : Copyright (C) 2014 Rushang Vinod Vandana Karia
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
module TftCtl
(
input wire CLK_I,
input wire CLK_180_I,
input wire RST_I,
input wire [31:0] X_I,
input wire [31:0] Y_I,
input wire [11:0] Z_I,
input wire WE_I,
input wire WR_CLK,
input wire [3:0] MSEL_I,
output wire [7:0] R_O,
output wire [7:0] G_O,
output wire [7:0] B_O,
output wire DE_O,
output wire CLK_O,
output wire DISP_O,
output wire BKLT_O,
output wire VDDEN_O
);
///////////////////////////////////////////////////////////////////////
// MODULE SPECIFIC PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////
`include"resolutions.v" //Include the converted library files
//`include"video_rom.v" //over here. You can make place them
//`include"touch_panel.v" //at the head but warnings occur
parameter integer CLOCKFREQ = 9; //MHz
parameter integer TPOWERUP = 1; //ms
parameter integer TPOWERDOWN = 1; //ms
parameter integer TLEDWARMUP = 200; //ms
parameter integer TLEDCOOLDOWN = 200; //ms
parameter integer TLEDWARMUP_CYCLES = CLOCKFREQ * TLEDWARMUP * 1000;
parameter integer TLEDCOOLDOWN_CYCLES = CLOCKFREQ * TLEDCOOLDOWN * 1000;
parameter integer TPOWERUP_CYCLES = CLOCKFREQ * TPOWERUP * 1000;
parameter integer TPOWERDOWN_CYCLES = CLOCKFREQ * TPOWERDOWN * 1000;
parameter integer STATE_OFF = 0; //State machine for the
parameter integer STATE_POWER_UP = 1; //initialization of the TFT
parameter integer STATE_LED_WARM_UP = 2;
parameter integer STATE_LED_COOL_DOWN = 3;
parameter integer STATE_POWER_DOWN = 4;
parameter integer STATE_ON = 5;
parameter integer FB_COLOR_DEPTH = 2;
parameter integer GROUND = 0;
parameter integer VDD = 1;
///////////////////////////////////////////////////////////////////////////////////////
// SIGNALS LOCAL TO MODULE
///////////////////////////////////////////////////////////////////////////////////////
reg [$clog2(TLEDCOOLDOWN_CYCLES)-1:0] waitCnt;
wire waitCntEn;
reg [$clog2(STATE_ON)-1:0] state;
reg [$clog2(STATE_ON)-1:0] next_state;
reg [$clog2(2**28)-1:0] cntDyn;
wire [31:0] VtcHCnt;
wire [31:0] VtcVCnt;
wire VtcRst;
wire VtcVde;
wire VtcHs;
wire VtcVs;
wire int_Bklt;
reg int_De;
wire clkStop;
wire [7:0] int_R;
wire [7:0] int_G;
wire [7:0] int_B;
reg [FB_COLOR_DEPTH-1:0] vram_data;
reg [FB_COLOR_DEPTH-1:0] reg_wrdata;
reg [$clog2(H_480_272p_AV*V_480_272p_AV)-1:0] vram_addr;
reg [$clog2(H_480_272p_AV*V_480_272p_AV)-1:0] vram_wraddr;
reg [FB_COLOR_DEPTH-1:0] vram [H_480_272p_AV*V_480_272p_AV-1:0];
reg vram_we;
//@Deprecated
reg reg_X;
reg reg_Y;
reg reg_WE;
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
integer i;
//synthesis attribute RAM_STYLE of vram is "BLOCK"
initial
begin
waitCnt = 0;
int_De = 1'b0;
state = STATE_POWER_DOWN;
end
///////////////////////////////////////////////////////////////////////////////////////
// VIDEO TIMING CONTROLLER :: MODULE INSTANTIAION
///////////////////////////////////////////////////////////////////////////////////////
/*
* This module provides the video
* timing controls for the TFT.
* This involves the display
* protocol
*/
VideoTimingCtl vtc
(
.PCLK_I (CLK_I),
.RSEL_I (R480_272P),
.RST_I (VtcRst),
.VDE_O (VtcVde),
.HS_O (VtcHs),
.VS_O (VtcVs),
.HCNT_O (VtcHCnt),
.VCNT_O (VtcVCnt)
);
assign VtcRst = 1'b0;
///////////////////////////////////////////////////////////////////////////////////////
// VRAM ADDRESS COUNTER
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
begin
int_De <= VtcVde;
if(VtcRst)
vram_addr <= 'b0;
else if(VtcVde)
if(vram_addr == H_480_272p_AV*V_480_272p_AV-1)
vram_addr <= 'b0;
else
vram_addr <= vram_addr+1;
end
always@(posedge CLK_I)
begin
if(X_I >= 0 && X_I < H_480_272p_AV && Y_I >= 0 && Y_I < V_480_272p_AV)
vram_we <= WE_I;
else
vram_we <= 1'b0;
vram_wraddr <= (Y_I)*H_480_272p_AV+X_I;
if(Z_I < 'h200)
reg_wrdata <= 2'b11;
else if(Z_I < 'h300)
reg_wrdata <= 2'b10;
else
reg_wrdata <= 2'b01;
end
///////////////////////////////////////////////////////////////////////////////////////
// VRAM REGISTERED OUTPUT
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
vram_data <= vram[vram_addr];
always@(posedge CLK_I)
if(vram_we)
vram[vram_wraddr] = reg_wrdata;
///////////////////////////////////////////////////////////////////////////////////////
// SCREEN DIVISION INTO RED, GREEN and BLACK THIRDS
///////////////////////////////////////////////////////////////////////////////////////
assign int_R = (VtcHCnt < H_480_272p_AV/3) ? {vram_data,6'b000000} :8'h00;
assign int_G = (VtcHCnt >= H_480_272p_AV/3 && VtcHCnt < H_480_272p_AV*2/3) ? {vram_data,6'b000000} :8'h00;
assign int_B = (VtcHCnt >= H_480_272p_AV*2/3) ? {vram_data,6'b000000} :8'h00;
///////////////////////////////////////////////////////////////////////////////////////
// BACKLIGHT INTENSITY CONTROL :: MODULE INSTANTIATION
///////////////////////////////////////////////////////////////////////////////////////
/*
* This module controls the intensity of the
* backlight so that the data is visible
* instead of a white screen
*/
Pulse_Width_Modulation #(
.C_CLK_I_FREQUENCY (9),
.C_PWM_FREQUENCY (25000),
.C_PWM_RESOLUTION (3)
)
pwm
(
.CLK_I (CLK_I),
.RST_I (1'b0),
.DUTY_FACTOR_I (MSEL_I[2:0]),
.PWM_O (int_Bklt)
);
///////////////////////////////////////////////////////////////////////////////////////
// LCD POWER SEQUENCE
///////////////////////////////////////////////////////////////////////////////////////
assign BKLT_O = (state == STATE_ON) ? int_Bklt :1'b0;
assign VDDEN_O = (state == STATE_OFF || state == STATE_POWER_DOWN) ? 1'b0 :1'b1;
assign DISP_O = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 1'b0 :1'b1;
assign DE_O = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 'b0 :int_De;
assign R_O = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 'b0 :int_R;
assign G_O = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 'b0 :int_G;
assign B_O = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 'b0 :int_B;
assign clkStop = (state == STATE_OFF || state == STATE_POWER_DOWN || state == STATE_POWER_UP) ? 1'b1 :1'b0;
assign waitCntEn = ((state == STATE_POWER_UP || state == STATE_LED_WARM_UP ||
state == STATE_LED_COOL_DOWN || state == STATE_POWER_DOWN)&&(state==next_state))? 1'b1 :1'b0;
always@(posedge CLK_I)
state <= next_state;
always@*
case(state)
STATE_OFF : next_state = (MSEL_I[3] && ~RST_I) ? STATE_POWER_UP :STATE_OFF;
STATE_POWER_UP : next_state = (waitCnt == TPOWERUP_CYCLES) ? STATE_LED_WARM_UP :STATE_POWER_UP;
STATE_LED_WARM_UP : next_state = (waitCnt == TLEDWARMUP_CYCLES) ? STATE_ON :STATE_LED_WARM_UP;
STATE_ON : next_state = (~MSEL_I[3] && RST_I) ? STATE_LED_COOL_DOWN :STATE_ON;
STATE_LED_COOL_DOWN : next_state = (waitCnt == TLEDCOOLDOWN_CYCLES) ? STATE_POWER_DOWN :STATE_LED_COOL_DOWN;
STATE_POWER_DOWN : next_state = (waitCnt == TPOWERDOWN_CYCLES) ? STATE_OFF :STATE_POWER_DOWN;
default : next_state = STATE_OFF;
endcase
///////////////////////////////////////////////////////////////////////////////////////
// WAIT COUNTER
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(waitCntEn==0)
waitCnt <= 0;
else
waitCnt <= waitCnt+1;
///////////////////////////////////////////////////////////////////////////////////////
// CLOCK FORWARDING DONE RIGHT
///////////////////////////////////////////////////////////////////////////////////////
ODDR2 #(
.DDR_ALIGNMENT ("NONE"), //Set output alignment to "NONE", "C0", "C1"
.INIT (1'b0), //Set initial Q to 0
.SRTYPE ("SYNC") //Synchronous reset
)
Inst_ODDR2_MCLK_FORWARD
(
.Q (CLK_O), //Output data
.C0 (CLK_I), //Input clock
.C1 (CLK_180_I),
.CE (1'b1), //Clock enable
.D0 (1'b1), //Data associated with C0
.D1 (1'b0), //Data associated with C1
.R (clkStop), //Clock reset
.S (1'b0) //Set input
);
endmodule
|
//
// bv_count module
//
// bv2.0_programmable
//
// Created by LiJunnan on 16/9/16.
// Copyright (c) 2016year LiJunnan. All rights reserved.
`timescale 1ns/1ps
module bv_count(
reset,
clk,
bv_valid,
bv,
count,
bv_out_valid,
bv_out,
count_out
);
parameter width = 64;
parameter width_count = 6;
parameter stage = 1;
parameter range_end = 1;
input reset;
input clk;
input bv_valid;
input [width-1:0] bv;
input [width_count-1:0] count;
output reg bv_out_valid;
output reg [width-1:0] bv_out;
output reg [width_count-1:0] count_out;
always @ (posedge clk)begin
if(bv_valid == 1'b1)begin
bv_out_valid <= 1'b1;
if(bv[range_end-1:0])begin
bv_out <= bv;
count_out <= count;
end
else begin
bv_out <= bv >> range_end;
count_out <= count + range_end;
end
end
else begin
bv_out_valid <= 1'b0;
bv_out <= {width{1'b0}};
count_out <= {width_count{1'b0}};
end
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : rdcost_decision.v
// Author : Huang Lei Lei
// Created : 2014-10-21
// Description : linear approximation of RDcost
//
//-------------------------------------------------------------------
//
// Modified : 2015-08-18 by HLL
// Description : abs logic of coe_x_abs corrected
//
// $Id$
//
//-------------------------------------------------------------------
module rdcost_decision (
clk ,
rst_n ,
pre_min_size_i ,
pre_qp_i ,
pre_sel_i ,
pre_size_i ,
pre_position_i ,
coe_val_i ,
coe_data_i ,
rec_val_i ,
rec_data_i ,
ori_data_i ,
cover_valid_o ,
cover_value_o
);
//*** INPUT/OUPUT DECLRATION ***************************************************
// global
input clk ;
input rst_n ;
// sys ctrl
input pre_min_size_i ;
// pre information
input [5 : 0] pre_qp_i ;
input [1 : 0] pre_sel_i ;
input [1 : 0] pre_size_i ;
input [7 : 0] pre_position_i ;
// coe data
input coe_val_i ;
input [511 : 0] coe_data_i ;
// rec & ori data
input rec_val_i ;
input [255 : 0] rec_data_i ;
input [255 : 0] ori_data_i ;
// cover
output reg cover_valid_o ;
output reg cover_value_o ;
//*** WIRE/REG DECLRATION ******************************************************
wire [7 : 0] rec_0_i , ori_0_i , rec_10_i , ori_10_i , rec_20_i , ori_20_i , rec_30_i , ori_30_i ;
wire [7 : 0] rec_1_i , ori_1_i , rec_11_i , ori_11_i , rec_21_i , ori_21_i , rec_31_i , ori_31_i ;
wire [7 : 0] rec_2_i , ori_2_i , rec_12_i , ori_12_i , rec_22_i , ori_22_i ;
wire [7 : 0] rec_3_i , ori_3_i , rec_13_i , ori_13_i , rec_23_i , ori_23_i ;
wire [7 : 0] rec_4_i , ori_4_i , rec_14_i , ori_14_i , rec_24_i , ori_24_i ;
wire [7 : 0] rec_5_i , ori_5_i , rec_15_i , ori_15_i , rec_25_i , ori_25_i ;
wire [7 : 0] rec_6_i , ori_6_i , rec_16_i , ori_16_i , rec_26_i , ori_26_i ;
wire [7 : 0] rec_7_i , ori_7_i , rec_17_i , ori_17_i , rec_27_i , ori_27_i ;
wire [7 : 0] rec_8_i , ori_8_i , rec_18_i , ori_18_i , rec_28_i , ori_28_i ;
wire [7 : 0] rec_9_i , ori_9_i , rec_19_i , ori_19_i , rec_29_i , ori_29_i ;
wire signed [15 : 0] coe_0_i , coe_10_i , coe_20_i , coe_30_i ;
wire signed [15 : 0] coe_1_i , coe_11_i , coe_21_i , coe_31_i ;
wire signed [15 : 0] coe_2_i , coe_12_i , coe_22_i ;
wire signed [15 : 0] coe_3_i , coe_13_i , coe_23_i ;
wire signed [15 : 0] coe_4_i , coe_14_i , coe_24_i ;
wire signed [15 : 0] coe_5_i , coe_15_i , coe_25_i ;
wire signed [15 : 0] coe_6_i , coe_16_i , coe_26_i ;
wire signed [15 : 0] coe_7_i , coe_17_i , coe_27_i ;
wire signed [15 : 0] coe_8_i , coe_18_i , coe_28_i ;
wire signed [15 : 0] coe_9_i , coe_19_i , coe_29_i ;
//*** MAIN BODY ****************************************************************
//--- Global Signals -------------------
assign { coe_0_i ,coe_1_i ,coe_2_i ,coe_3_i ,coe_4_i ,coe_5_i ,coe_6_i ,coe_7_i ,coe_8_i ,coe_9_i ,
coe_10_i ,coe_11_i ,coe_12_i ,coe_13_i ,coe_14_i ,coe_15_i ,coe_16_i ,coe_17_i ,coe_18_i ,coe_19_i ,
coe_20_i ,coe_21_i ,coe_22_i ,coe_23_i ,coe_24_i ,coe_25_i ,coe_26_i ,coe_27_i ,coe_28_i ,coe_29_i ,
coe_30_i ,coe_31_i }
= coe_data_i ;
assign { rec_0_i ,rec_1_i ,rec_2_i ,rec_3_i ,rec_4_i ,rec_5_i ,rec_6_i ,rec_7_i ,rec_8_i ,rec_9_i ,
rec_10_i ,rec_11_i ,rec_12_i ,rec_13_i ,rec_14_i ,rec_15_i ,rec_16_i ,rec_17_i ,rec_18_i ,rec_19_i ,
rec_20_i ,rec_21_i ,rec_22_i ,rec_23_i ,rec_24_i ,rec_25_i ,rec_26_i ,rec_27_i ,rec_28_i ,rec_29_i ,
rec_30_i ,rec_31_i }
= rec_data_i ;
assign { ori_0_i ,ori_1_i ,ori_2_i ,ori_3_i ,ori_4_i ,ori_5_i ,ori_6_i ,ori_7_i ,ori_8_i ,ori_9_i ,
ori_10_i ,ori_11_i ,ori_12_i ,ori_13_i ,ori_14_i ,ori_15_i ,ori_16_i ,ori_17_i ,ori_18_i ,ori_19_i ,
ori_20_i ,ori_21_i ,ori_22_i ,ori_23_i ,ori_24_i ,ori_25_i ,ori_26_i ,ori_27_i ,ori_28_i ,ori_29_i ,
ori_30_i ,ori_31_i }
= ori_data_i ;
reg [5:0] coe_cnt_r;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
coe_cnt_r <= 'd0;
else if( (cover_valid_o) )
coe_cnt_r <= 'd0 ;
else if( (coe_val_i=='d1) || ( (coe_cnt_r>='d01)&&(coe_cnt_r<='d40) ) ) begin
coe_cnt_r <= coe_cnt_r + 'd1;
end
end
reg [5:0] rec_cnt_r;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
rec_cnt_r <= 'd0;
else if( (cover_valid_o) )
rec_cnt_r <= 'd0 ;
else if( (rec_val_i=='d1) || ( (rec_cnt_r>='d01)&&(rec_cnt_r<='d40) ) ) begin
rec_cnt_r <= rec_cnt_r + 'd1 ;
end
end
//--- Distortion -----------------------
// pipeline 1
wire signed [8:0] dif_0 = ori_0_i - rec_0_i ;
wire signed [8:0] dif_1 = ori_1_i - rec_1_i ;
wire signed [8:0] dif_2 = ori_2_i - rec_2_i ;
wire signed [8:0] dif_3 = ori_3_i - rec_3_i ;
wire signed [8:0] dif_4 = ori_4_i - rec_4_i ;
wire signed [8:0] dif_5 = ori_5_i - rec_5_i ;
wire signed [8:0] dif_6 = ori_6_i - rec_6_i ;
wire signed [8:0] dif_7 = ori_7_i - rec_7_i ;
wire signed [8:0] dif_8 = ori_8_i - rec_8_i ;
wire signed [8:0] dif_9 = ori_9_i - rec_9_i ;
wire signed [8:0] dif_10 = ori_10_i - rec_10_i ;
wire signed [8:0] dif_11 = ori_11_i - rec_11_i ;
wire signed [8:0] dif_12 = ori_12_i - rec_12_i ;
wire signed [8:0] dif_13 = ori_13_i - rec_13_i ;
wire signed [8:0] dif_14 = ori_14_i - rec_14_i ;
wire signed [8:0] dif_15 = ori_15_i - rec_15_i ;
wire signed [8:0] dif_16 = ori_16_i - rec_16_i ;
wire signed [8:0] dif_17 = ori_17_i - rec_17_i ;
wire signed [8:0] dif_18 = ori_18_i - rec_18_i ;
wire signed [8:0] dif_19 = ori_19_i - rec_19_i ;
wire signed [8:0] dif_20 = ori_20_i - rec_20_i ;
wire signed [8:0] dif_21 = ori_21_i - rec_21_i ;
wire signed [8:0] dif_22 = ori_22_i - rec_22_i ;
wire signed [8:0] dif_23 = ori_23_i - rec_23_i ;
wire signed [8:0] dif_24 = ori_24_i - rec_24_i ;
wire signed [8:0] dif_25 = ori_25_i - rec_25_i ;
wire signed [8:0] dif_26 = ori_26_i - rec_26_i ;
wire signed [8:0] dif_27 = ori_27_i - rec_27_i ;
wire signed [8:0] dif_28 = ori_28_i - rec_28_i ;
wire signed [8:0] dif_29 = ori_29_i - rec_29_i ;
wire signed [8:0] dif_30 = ori_30_i - rec_30_i ;
wire signed [8:0] dif_31 = ori_31_i - rec_31_i ;
wire [07:0] dif_0_abs = ( dif_0[8]==0 ) ? dif_0[7:0] : (~dif_0+1) ;
wire [07:0] dif_1_abs = ( dif_1[8]==0 ) ? dif_1[7:0] : (~dif_1+1) ;
wire [07:0] dif_2_abs = ( dif_2[8]==0 ) ? dif_2[7:0] : (~dif_2+1) ;
wire [07:0] dif_3_abs = ( dif_3[8]==0 ) ? dif_3[7:0] : (~dif_3+1) ;
wire [07:0] dif_4_abs = ( dif_4[8]==0 ) ? dif_4[7:0] : (~dif_4+1) ;
wire [07:0] dif_5_abs = ( dif_5[8]==0 ) ? dif_5[7:0] : (~dif_5+1) ;
wire [07:0] dif_6_abs = ( dif_6[8]==0 ) ? dif_6[7:0] : (~dif_6+1) ;
wire [07:0] dif_7_abs = ( dif_7[8]==0 ) ? dif_7[7:0] : (~dif_7+1) ;
wire [07:0] dif_8_abs = ( dif_8[8]==0 ) ? dif_8[7:0] : (~dif_8+1) ;
wire [07:0] dif_9_abs = ( dif_9[8]==0 ) ? dif_9[7:0] : (~dif_9+1) ;
wire [07:0] dif_10_abs = ( dif_10[8]==0 ) ? dif_10[7:0] : (~dif_10+1) ;
wire [07:0] dif_11_abs = ( dif_11[8]==0 ) ? dif_11[7:0] : (~dif_11+1) ;
wire [07:0] dif_12_abs = ( dif_12[8]==0 ) ? dif_12[7:0] : (~dif_12+1) ;
wire [07:0] dif_13_abs = ( dif_13[8]==0 ) ? dif_13[7:0] : (~dif_13+1) ;
wire [07:0] dif_14_abs = ( dif_14[8]==0 ) ? dif_14[7:0] : (~dif_14+1) ;
wire [07:0] dif_15_abs = ( dif_15[8]==0 ) ? dif_15[7:0] : (~dif_15+1) ;
wire [07:0] dif_16_abs = ( dif_16[8]==0 ) ? dif_16[7:0] : (~dif_16+1) ;
wire [07:0] dif_17_abs = ( dif_17[8]==0 ) ? dif_17[7:0] : (~dif_17+1) ;
wire [07:0] dif_18_abs = ( dif_18[8]==0 ) ? dif_18[7:0] : (~dif_18+1) ;
wire [07:0] dif_19_abs = ( dif_19[8]==0 ) ? dif_19[7:0] : (~dif_19+1) ;
wire [07:0] dif_20_abs = ( dif_20[8]==0 ) ? dif_20[7:0] : (~dif_20+1) ;
wire [07:0] dif_21_abs = ( dif_21[8]==0 ) ? dif_21[7:0] : (~dif_21+1) ;
wire [07:0] dif_22_abs = ( dif_22[8]==0 ) ? dif_22[7:0] : (~dif_22+1) ;
wire [07:0] dif_23_abs = ( dif_23[8]==0 ) ? dif_23[7:0] : (~dif_23+1) ;
wire [07:0] dif_24_abs = ( dif_24[8]==0 ) ? dif_24[7:0] : (~dif_24+1) ;
wire [07:0] dif_25_abs = ( dif_25[8]==0 ) ? dif_25[7:0] : (~dif_25+1) ;
wire [07:0] dif_26_abs = ( dif_26[8]==0 ) ? dif_26[7:0] : (~dif_26+1) ;
wire [07:0] dif_27_abs = ( dif_27[8]==0 ) ? dif_27[7:0] : (~dif_27+1) ;
wire [07:0] dif_28_abs = ( dif_28[8]==0 ) ? dif_28[7:0] : (~dif_28+1) ;
wire [07:0] dif_29_abs = ( dif_29[8]==0 ) ? dif_29[7:0] : (~dif_29+1) ;
wire [07:0] dif_30_abs = ( dif_30[8]==0 ) ? dif_30[7:0] : (~dif_30+1) ;
wire [07:0] dif_31_abs = ( dif_31[8]==0 ) ? dif_31[7:0] : (~dif_31+1) ;
wire [09:0] add_0 = dif_0_abs + dif_1_abs + dif_2_abs + dif_3_abs ;
wire [09:0] add_1 = dif_4_abs + dif_5_abs + dif_6_abs + dif_7_abs ;
wire [09:0] add_2 = dif_8_abs + dif_9_abs + dif_10_abs + dif_11_abs ;
wire [09:0] add_3 = dif_12_abs + dif_13_abs + dif_14_abs + dif_15_abs ;
wire [09:0] add_4 = dif_16_abs + dif_17_abs + dif_18_abs + dif_19_abs ;
wire [09:0] add_5 = dif_20_abs + dif_21_abs + dif_22_abs + dif_23_abs ;
wire [09:0] add_6 = dif_24_abs + dif_25_abs + dif_26_abs + dif_27_abs ;
wire [09:0] add_7 = dif_28_abs + dif_29_abs + dif_30_abs + dif_31_abs ;
wire [17:0] sse_0 = add_0 * add_0[9:2] ;
wire [17:0] sse_1 = add_1 * add_1[9:2] ;
wire [17:0] sse_2 = add_2 * add_2[9:2] ;
wire [17:0] sse_3 = add_3 * add_3[9:2] ;
wire [17:0] sse_4 = add_4 * add_4[9:2] ;
wire [17:0] sse_5 = add_5 * add_5[9:2] ;
wire [17:0] sse_6 = add_6 * add_6[9:2] ;
wire [17:0] sse_7 = add_7 * add_7[9:2] ;
reg [17:0] sse_0_reg ,sse_1_reg ,sse_2_reg ,sse_3_reg ,sse_4_reg ,sse_5_reg ,sse_6_reg ,sse_7_reg ;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sse_0_reg <= 'd0 ;
sse_1_reg <= 'd0 ;
sse_2_reg <= 'd0 ;
sse_3_reg <= 'd0 ;
sse_4_reg <= 'd0 ;
sse_5_reg <= 'd0 ;
sse_6_reg <= 'd0 ;
sse_7_reg <= 'd0 ;
end
else begin
sse_0_reg <= sse_0 ;
sse_1_reg <= sse_1 ;
sse_2_reg <= sse_2 ;
sse_3_reg <= sse_3 ;
sse_4_reg <= sse_4 ;
sse_5_reg <= sse_5 ;
sse_6_reg <= sse_6 ;
sse_7_reg <= sse_7 ;
end
end
// pipeline 2
wire [17:0] sse_0_dec = sse_0_reg ;
wire [17:0] sse_2_dec = sse_2_reg ;
wire [17:0] sse_4_dec = sse_4_reg ;
wire [17:0] sse_6_dec = sse_6_reg ;
wire [17:0] sse_1_dec = ( pre_size_i==2'b00 ) ? 0 : sse_1_reg ;
wire [17:0] sse_3_dec = ( pre_size_i==2'b00 ) ? 0 : sse_3_reg ;
wire [17:0] sse_5_dec = ( pre_size_i==2'b00 ) ? 0 : sse_5_reg ;
wire [17:0] sse_7_dec = ( pre_size_i==2'b00 ) ? 0 : sse_7_reg ;
wire [21:0] sse_line = sse_0_reg + sse_1_reg + sse_2_dec + sse_3_dec + sse_4_dec + sse_5_dec + sse_6_dec + sse_7_dec ;
reg [21:0] sse_line_reg ;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
sse_line_reg <= 'd0;
else begin
sse_line_reg <= sse_line;
end
end
// pipeline 3
reg[26:0] sse;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
sse <= 'd0;
else if( (rec_cnt_r=='d1) )
sse <= 'd0;
else if( (pre_sel_i=='d0) && ( ((pre_size_i=='d0)&&(rec_cnt_r<='d02)) ||
((pre_size_i=='d1)&&(rec_cnt_r<='d03)) ||
((pre_size_i=='d2)&&(rec_cnt_r<='d09)) ||
((pre_size_i=='d3)&&(rec_cnt_r<='d33))
)
)
sse <= sse + sse_line_reg;
else begin
sse <= sse;
end
end
//--- Bitrate --------------------------
// pipeline 1
reg [11:0] a, b ;
always @(posedge clk or negedge rst_n )begin
if( !rst_n ) begin
a <= 'd0 ;
b <= 'd0 ;
end
else if( coe_cnt_r==1 )begin
case( pre_qp_i )
6'd0 : begin a <= 'd1 ; b <= 'd1 ; end
6'd1 : begin a <= 'd1 ; b <= 'd1 ; end
6'd2 : begin a <= 'd1 ; b <= 'd1 ; end
6'd3 : begin a <= 'd1 ; b <= 'd1 ; end
6'd4 : begin a <= 'd1 ; b <= 'd2 ; end
6'd5 : begin a <= 'd1 ; b <= 'd2 ; end
6'd6 : begin a <= 'd1 ; b <= 'd2 ; end
6'd7 : begin a <= 'd1 ; b <= 'd2 ; end
6'd8 : begin a <= 'd1 ; b <= 'd3 ; end
6'd9 : begin a <= 'd1 ; b <= 'd3 ; end
6'd10 : begin a <= 'd1 ; b <= 'd4 ; end
6'd11 : begin a <= 'd1 ; b <= 'd4 ; end
6'd12 : begin a <= 'd1 ; b <= 'd5 ; end
6'd13 : begin a <= 'd1 ; b <= 'd5 ; end
6'd14 : begin a <= 'd1 ; b <= 'd6 ; end
6'd15 : begin a <= 'd1 ; b <= 'd7 ; end
6'd16 : begin a <= 'd1 ; b <= 'd8 ; end
6'd17 : begin a <= 'd1 ; b <= 'd9 ; end
6'd18 : begin a <= 'd1 ; b <= 'd11 ; end
6'd19 : begin a <= 'd1 ; b <= 'd13 ; end
6'd20 : begin a <= 'd1 ; b <= 'd15 ; end
6'd21 : begin a <= 'd1 ; b <= 'd17 ; end
6'd22 : begin a <= 'd2 ; b <= 'd19 ; end
6'd23 : begin a <= 'd2 ; b <= 'd22 ; end
6'd24 : begin a <= 'd2 ; b <= 'd25 ; end
6'd25 : begin a <= 'd3 ; b <= 'd29 ; end
6'd26 : begin a <= 'd4 ; b <= 'd33 ; end
6'd27 : begin a <= 'd5 ; b <= 'd38 ; end
6'd28 : begin a <= 'd6 ; b <= 'd43 ; end
6'd29 : begin a <= 'd8 ; b <= 'd49 ; end
6'd30 : begin a <= 'd10 ; b <= 'd56 ; end
6'd31 : begin a <= 'd13 ; b <= 'd62 ; end
6'd32 : begin a <= 'd17 ; b <= 'd70 ; end
6'd33 : begin a <= 'd21 ; b <= 'd78 ; end
6'd34 : begin a <= 'd28 ; b <= 'd86 ; end
6'd35 : begin a <= 'd36 ; b <= 'd93 ; end
6'd36 : begin a <= 'd47 ; b <= 'd100 ; end
6'd37 : begin a <= 'd61 ; b <= 'd105 ; end
6'd38 : begin a <= 'd78 ; b <= 'd108 ; end
6'd39 : begin a <= 'd100 ; b <= 'd107 ; end
6'd40 : begin a <= 'd130 ; b <= 'd101 ; end
6'd41 : begin a <= 'd167 ; b <= 'd87 ; end
6'd42 : begin a <= 'd216 ; b <= 'd62 ; end
6'd43 : begin a <= 'd279 ; b <= 'd22 ; end
6'd44 : begin a <= 'd358 ; b <= 'd1 ; end
6'd45 : begin a <= 'd461 ; b <= 'd1 ; end
6'd46 : begin a <= 'd593 ; b <= 'd1 ; end
6'd47 : begin a <= 'd762 ; b <= 'd1 ; end
6'd48 : begin a <= 'd980 ; b <= 'd1 ; end
6'd49 : begin a <= 'd1260 ; b <= 'd1 ; end
6'd50 : begin a <= 'd1618 ; b <= 'd1 ; end
6'd51 : begin a <= 'd2078 ; b <= 'd1 ; end
default : begin a <= 'd1 ; b <= 'd1 ; end
endcase
end
end
wire [14:0] coe_0_abs = ( coe_0_i[15] ==0 ) ? coe_0_i : (~coe_0_i + 1) ;
wire [14:0] coe_1_abs = ( coe_1_i[15] ==0 ) ? coe_1_i : (~coe_1_i + 1) ;
wire [14:0] coe_2_abs = ( coe_2_i[15] ==0 ) ? coe_2_i : (~coe_2_i + 1) ;
wire [14:0] coe_3_abs = ( coe_3_i[15] ==0 ) ? coe_3_i : (~coe_3_i + 1) ;
wire [14:0] coe_4_abs = ( coe_4_i[15] ==0 ) ? coe_4_i : (~coe_4_i + 1) ;
wire [14:0] coe_5_abs = ( coe_5_i[15] ==0 ) ? coe_5_i : (~coe_5_i + 1) ;
wire [14:0] coe_6_abs = ( coe_6_i[15] ==0 ) ? coe_6_i : (~coe_6_i + 1) ;
wire [14:0] coe_7_abs = ( coe_7_i[15] ==0 ) ? coe_7_i : (~coe_7_i + 1) ;
wire [14:0] coe_8_abs = ( coe_8_i[15] ==0 ) ? coe_8_i : (~coe_8_i + 1) ;
wire [14:0] coe_9_abs = ( coe_9_i[15] ==0 ) ? coe_9_i : (~coe_9_i + 1) ;
wire [14:0] coe_10_abs = ( coe_10_i[15]==0 ) ? coe_10_i : (~coe_10_i + 1) ;
wire [14:0] coe_11_abs = ( coe_11_i[15]==0 ) ? coe_11_i : (~coe_11_i + 1) ;
wire [14:0] coe_12_abs = ( coe_12_i[15]==0 ) ? coe_12_i : (~coe_12_i + 1) ;
wire [14:0] coe_13_abs = ( coe_13_i[15]==0 ) ? coe_13_i : (~coe_13_i + 1) ;
wire [14:0] coe_14_abs = ( coe_14_i[15]==0 ) ? coe_14_i : (~coe_14_i + 1) ;
wire [14:0] coe_15_abs = ( coe_15_i[15]==0 ) ? coe_15_i : (~coe_15_i + 1) ;
wire [14:0] coe_16_abs = ( coe_16_i[15]==0 ) ? coe_16_i : (~coe_16_i + 1) ;
wire [14:0] coe_17_abs = ( coe_17_i[15]==0 ) ? coe_17_i : (~coe_17_i + 1) ;
wire [14:0] coe_18_abs = ( coe_18_i[15]==0 ) ? coe_18_i : (~coe_18_i + 1) ;
wire [14:0] coe_19_abs = ( coe_19_i[15]==0 ) ? coe_19_i : (~coe_19_i + 1) ;
wire [14:0] coe_20_abs = ( coe_20_i[15]==0 ) ? coe_20_i : (~coe_20_i + 1) ;
wire [14:0] coe_21_abs = ( coe_21_i[15]==0 ) ? coe_21_i : (~coe_21_i + 1) ;
wire [14:0] coe_22_abs = ( coe_22_i[15]==0 ) ? coe_22_i : (~coe_22_i + 1) ;
wire [14:0] coe_23_abs = ( coe_23_i[15]==0 ) ? coe_23_i : (~coe_23_i + 1) ;
wire [14:0] coe_24_abs = ( coe_24_i[15]==0 ) ? coe_24_i : (~coe_24_i + 1) ;
wire [14:0] coe_25_abs = ( coe_25_i[15]==0 ) ? coe_25_i : (~coe_25_i + 1) ;
wire [14:0] coe_26_abs = ( coe_26_i[15]==0 ) ? coe_26_i : (~coe_26_i + 1) ;
wire [14:0] coe_27_abs = ( coe_27_i[15]==0 ) ? coe_27_i : (~coe_27_i + 1) ;
wire [14:0] coe_28_abs = ( coe_28_i[15]==0 ) ? coe_28_i : (~coe_28_i + 1) ;
wire [14:0] coe_29_abs = ( coe_29_i[15]==0 ) ? coe_29_i : (~coe_29_i + 1) ;
wire [14:0] coe_30_abs = ( coe_30_i[15]==0 ) ? coe_30_i : (~coe_30_i + 1) ;
wire [14:0] coe_31_abs = ( coe_31_i[15]==0 ) ? coe_31_i : (~coe_31_i + 1) ;
wire [16:0] add_coe_0 = coe_0_abs + coe_1_abs + coe_2_abs + coe_3_abs ;
wire [16:0] add_coe_1 = coe_4_abs + coe_5_abs + coe_6_abs + coe_7_abs ;
wire [16:0] add_coe_2 = coe_8_abs + coe_9_abs + coe_10_abs + coe_11_abs ;
wire [16:0] add_coe_3 = coe_12_abs + coe_13_abs + coe_14_abs + coe_15_abs ;
wire [16:0] add_coe_4 = coe_16_abs + coe_17_abs + coe_18_abs + coe_19_abs ;
wire [16:0] add_coe_5 = coe_20_abs + coe_21_abs + coe_22_abs + coe_23_abs ;
wire [16:0] add_coe_6 = coe_24_abs + coe_25_abs + coe_26_abs + coe_27_abs ;
wire [16:0] add_coe_7 = coe_28_abs + coe_29_abs + coe_30_abs + coe_31_abs ;
wire [17:0] rate_0 = add_coe_0 + add_coe_1 ;
wire [17:0] rate_1 = add_coe_2 + add_coe_3 ;
wire [17:0] rate_2 = add_coe_4 + add_coe_5 ;
wire [17:0] rate_3 = add_coe_6 + add_coe_7 ;
reg [17:0] rate_0_reg;
reg [17:0] rate_1_reg;
reg [17:0] rate_2_reg;
reg [17:0] rate_3_reg;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )begin
rate_0_reg <= 'd0;
rate_1_reg <= 'd0;
rate_2_reg <= 'd0;
rate_3_reg <= 'd0;
end
else begin
rate_0_reg <= rate_0;
rate_1_reg <= rate_1;
rate_2_reg <= rate_2;
rate_3_reg <= rate_3;
end
end
// pipeline 2
wire [16:0] rate_0_dec = rate_0_reg ;
wire [16:0] rate_2_dec = rate_2_reg ;
wire [16:0] rate_1_dec = ( pre_size_i==2'b00 ) ? 0 : rate_1_reg ;
wire [16:0] rate_3_dec = ( pre_size_i==2'b00 ) ? 0 : rate_3_reg ;
wire [18:0] rate_line = rate_0_reg + rate_1_dec + rate_2_dec + rate_3_dec;
reg [18:0] rate_line_reg;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
rate_line_reg <= 'd0;
else begin
rate_line_reg <= rate_line;
end
end
// pipeline 3
wire [23:0] bitrate_line = a * rate_line_reg ;
reg [23:0] bitrate_line_reg ;
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
bitrate_line_reg <= 'd0;
else begin
bitrate_line_reg <= bitrate_line;
end
end
// pipeline 4
reg [23:0] bitrate;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
bitrate <= 'd0;
else if( (coe_cnt_r=='d2) )
bitrate <= 'd0;
else if( (pre_sel_i=='d0) && ( ((pre_size_i=='d0)&&(coe_cnt_r<='d03))||
((pre_size_i=='d1)&&(coe_cnt_r<='d04))||
((pre_size_i=='d2)&&(coe_cnt_r<='d10))||
((pre_size_i=='d3)&&(coe_cnt_r<='d34))
)
)
bitrate <= bitrate + bitrate_line_reg;
else begin
bitrate <= bitrate;
end
end
//--- Cost -----------------------------
wire [23:0] cost_current_w = sse[26:3] + bitrate + b ;
//--- Compare --------------------------
reg [23:0] cost_in_8x8 ;
reg [23:0] cost_in_16x16 ;
reg [23:0] cost_in_32x32 ;
// pipeline 1
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
cover_valid_o <= 'd0 ;
else if( (pre_size_i=='d0)&&(rec_cnt_r=='d03) ||
(pre_size_i=='d1)&&(rec_cnt_r=='d04) ||
(pre_size_i=='d2)&&(rec_cnt_r=='d10) ||
(pre_size_i=='d3)&&(rec_cnt_r=='d34)
)
cover_valid_o <= 'd1 ;
else begin
cover_valid_o <= 'd0 ;
end
end
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
cover_value_o <= 'd0 ;
else if( pre_sel_i )
cover_value_o <= 'd1 ;
else if( (pre_size_i=='d0)&&(rec_cnt_r=='d03) )
cover_value_o <= 'd1 ;
else if( (pre_size_i=='d1)&&(rec_cnt_r=='d04) )
if( pre_min_size_i )
cover_value_o <= 'd1 ;
else begin
cover_value_o <= ( cost_current_w<=cost_in_8x8 ) ;
end
else if( (pre_size_i=='d2)&&(rec_cnt_r=='d10) )
cover_value_o <= ( cost_current_w<=cost_in_16x16 ) ;
else if( (pre_size_i=='d3)&&(rec_cnt_r=='d34) ) begin
cover_value_o <= ( cost_current_w<=cost_in_32x32 ) ;
end
end
// pipeline 2
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
cost_in_8x8 <= 'd0 ;
else if( (pre_size_i=='d0)&&(rec_cnt_r=='d01)&&(pre_position_i[1:0]=='b00) )
cost_in_8x8 <= 'd0 ;
else if( (pre_size_i=='d0)&&(rec_cnt_r=='d04) ) begin
cost_in_8x8 <= cost_in_8x8 + cost_current_w ;
end
end
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
cost_in_16x16 <= 'd0 ;
else if( (pre_size_i=='d1)&&(rec_cnt_r=='d01)&&(pre_position_i[3:0]=='b00) )
cost_in_16x16 <= 'd0 ;
else if( (pre_size_i=='d1)&&(rec_cnt_r=='d05) ) begin
if( cover_value_o )
cost_in_16x16 <= cost_in_16x16 + cost_current_w ;
else begin
cost_in_16x16 <= cost_in_16x16 + cost_in_8x8 ;
end
end
end
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
cost_in_32x32 <= 'd0 ;
else if( (pre_size_i=='d2)&&(rec_cnt_r=='d01)&&(pre_position_i[5:0]=='b00) )
cost_in_32x32 <= 'd0 ;
else if( (pre_size_i=='d2)&&(rec_cnt_r=='d11) ) begin
if( cover_value_o )
cost_in_32x32 <= cost_in_32x32 + cost_current_w ;
else begin
cost_in_32x32 <= cost_in_32x32 + cost_in_16x16 ;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_TB_V
`define SKY130_FD_SC_LS__O2111A_TB_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_TB_V
|
// ddr3_s4_uniphy_example_d0.v
// This file was auto-generated from altera_avalon_mm_traffic_generator_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:48:48
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_d0 #(
parameter DEVICE_FAMILY = "Stratix IV",
parameter TG_AVL_DATA_WIDTH = 64,
parameter TG_AVL_ADDR_WIDTH = 27,
parameter TG_AVL_WORD_ADDR_WIDTH = 24,
parameter TG_AVL_SIZE_WIDTH = 3,
parameter TG_AVL_BE_WIDTH = 8,
parameter TG_GEN_BYTE_ADDR = 1,
parameter TG_NUM_DRIVER_LOOP = 1,
parameter TG_RANDOM_BYTE_ENABLE = 1,
parameter TG_ENABLE_READ_COMPARE = 1,
parameter TG_POWER_OF_TWO_BURSTS_ONLY = 0,
parameter TG_BURST_ON_BURST_BOUNDARY = 0,
parameter TG_TIMEOUT_COUNTER_WIDTH = 30,
parameter TG_MAX_READ_LATENCY = 20,
parameter TG_SINGLE_RW_SEQ_ADDR_COUNT = 32,
parameter TG_SINGLE_RW_RAND_ADDR_COUNT = 32,
parameter TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT = 32,
parameter TG_BLOCK_RW_SEQ_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_RAND_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_BLOCK_SIZE = 8,
parameter TG_TEMPLATE_STAGE_COUNT = 4,
parameter TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT = 4,
parameter TG_RAND_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_RAND_ADDR_GEN_MAX_BURSTCOUNT = 4,
parameter TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT = 4,
parameter TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT = 50
) (
input wire clk, // avl_clock.clk
input wire reset_n, // avl_reset.reset_n
output wire pass, // status.pass
output wire fail, // .fail
output wire test_complete, // .test_complete
input wire avl_ready, // avl.waitrequest_n
output wire [26:0] avl_addr, // .address
output wire [2:0] avl_size, // .burstcount
output wire [63:0] avl_wdata, // .writedata
input wire [63:0] avl_rdata, // .readdata
output wire avl_write_req, // .write
output wire avl_read_req, // .read
input wire avl_rdata_valid, // .readdatavalid
output wire [7:0] avl_be, // .byteenable
output wire avl_burstbegin // .beginbursttransfer
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (DEVICE_FAMILY != "Stratix IV")
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
device_family_check ( .error(1'b1) );
end
if (TG_AVL_DATA_WIDTH != 64)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_data_width_check ( .error(1'b1) );
end
if (TG_AVL_ADDR_WIDTH != 27)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_addr_width_check ( .error(1'b1) );
end
if (TG_AVL_WORD_ADDR_WIDTH != 24)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_word_addr_width_check ( .error(1'b1) );
end
if (TG_AVL_SIZE_WIDTH != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_size_width_check ( .error(1'b1) );
end
if (TG_AVL_BE_WIDTH != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_be_width_check ( .error(1'b1) );
end
if (TG_GEN_BYTE_ADDR != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_gen_byte_addr_check ( .error(1'b1) );
end
if (TG_NUM_DRIVER_LOOP != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_num_driver_loop_check ( .error(1'b1) );
end
if (TG_RANDOM_BYTE_ENABLE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_random_byte_enable_check ( .error(1'b1) );
end
if (TG_ENABLE_READ_COMPARE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_enable_read_compare_check ( .error(1'b1) );
end
if (TG_POWER_OF_TWO_BURSTS_ONLY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_power_of_two_bursts_only_check ( .error(1'b1) );
end
if (TG_BURST_ON_BURST_BOUNDARY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_burst_on_burst_boundary_check ( .error(1'b1) );
end
if (TG_TIMEOUT_COUNTER_WIDTH != 30)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_timeout_counter_width_check ( .error(1'b1) );
end
if (TG_MAX_READ_LATENCY != 20)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_max_read_latency_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_SEQ_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_seq_addr_count_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_RAND_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_rand_addr_count_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_rand_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_SEQ_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_RAND_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_rand_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_rand_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_BLOCK_SIZE != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_block_size_check ( .error(1'b1) );
end
if (TG_TEMPLATE_STAGE_COUNT != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_template_stage_count_check ( .error(1'b1) );
end
if (TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_seq_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_seq_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_ADDR_GEN_MAX_BURSTCOUNT != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT != 50)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_rand_addr_percent_check ( .error(1'b1) );
end
endgenerate
driver_avl_use_be_avl_use_burstbegin #(
.DEVICE_FAMILY ("Stratix IV"),
.TG_AVL_DATA_WIDTH (64),
.TG_AVL_ADDR_WIDTH (27),
.TG_AVL_WORD_ADDR_WIDTH (24),
.TG_AVL_SIZE_WIDTH (3),
.TG_AVL_BE_WIDTH (8),
.TG_GEN_BYTE_ADDR (1),
.TG_NUM_DRIVER_LOOP (1),
.TG_RANDOM_BYTE_ENABLE (1),
.TG_ENABLE_READ_COMPARE (1),
.TG_POWER_OF_TWO_BURSTS_ONLY (0),
.TG_BURST_ON_BURST_BOUNDARY (0),
.TG_TIMEOUT_COUNTER_WIDTH (30),
.TG_MAX_READ_LATENCY (20),
.TG_SINGLE_RW_SEQ_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT (32),
.TG_BLOCK_RW_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_BLOCK_SIZE (8),
.TG_TEMPLATE_STAGE_COUNT (4),
.TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT (50)
) traffic_generator_0 (
.pass (pass), // status.pass
.fail (fail), // .fail
.test_complete (test_complete), // .test_complete
.clk (clk), // avl_clock.clk
.reset_n (reset_n), // avl_reset.reset_n
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_addr (avl_addr), // .address
.avl_size (avl_size), // .burstcount
.avl_wdata (avl_wdata), // .writedata
.avl_rdata (avl_rdata), // .readdata
.avl_write_req (avl_write_req), // .write
.avl_read_req (avl_read_req), // .read
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_be (avl_be), // .byteenable
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.pnf_per_bit (), // (terminated)
.pnf_per_bit_persist () // (terminated)
);
endmodule
|
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_wr_wait, tx_rd_wait,
// Inputs
reset, txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
tx_lclk_par, tx_lclk, tx_lclk_out, tx_frame_par, tx_data_par,
ecfg_tx_enable, ecfg_tx_gpio_enable, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# reset
//###########
input reset;
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; //tx clock (up to 500MHz)
output txo_frame_p, txo_frame_n; //tx frame signal
output [7:0] txo_data_p, txo_data_n; //tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; //tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; //tx read pushback
//#############
//# Fabric interface
//#############
input tx_lclk_par; // Slow lclk for parallel side (bit rate / 8)
input tx_lclk; // High speed clock for serdesd (bit rate / 2)
input tx_lclk_out; // High speed lclk output clock (90deg from tx_lclk)
input [7:0] tx_frame_par; // Parallel frame for serdes
input [63:0] tx_data_par; // Parallel data for serdes
output tx_wr_wait;
output tx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_tx_enable; //enable signal for tx
input ecfg_tx_gpio_enable;//forces tx wait pins to constants
input [8:0] ecfg_dataout; // frame & data for GPIO mode
//############
//# REGS
//############
reg [63:0] pdata;
reg [7:0] pframe;
reg [1:0] txenb_sync;
reg [1:0] txgpio_sync;
//############
//# WIRES
//############
wire [7:0] tx_data; // High-speed serial data outputs
wire [7:0] tx_data_t; // Tristate signal to OBUF's
wire tx_frame; // serial frame signal
wire tx_lclk_buf;
wire txenb;
wire txgpio;
integer n;
//#############################
//# Serializer instantiations
//#############################
assign txenb = txenb_sync[0];
assign txgpio = txgpio_sync[0];
// Sync these control bits into our domain
always @ (posedge tx_lclk_par)
begin
txenb_sync[1:0] <= {ecfg_tx_enable, txenb_sync[1]};
txgpio_sync[1:0] <= {ecfg_tx_gpio_enable, txgpio_sync[1]};
if(txgpio)
begin
pframe <= {8{ecfg_dataout[8]}};
for(n=0; n<8; n=n+1)
pdata[n*8+7 -: 8] <= ecfg_dataout[7:0];
end else if(txenb)
begin
pframe[7:0] <= tx_frame_par[7:0];
pdata[63:0] <= tx_data_par[63:0];
end
else
begin
pframe[7:0] <= 8'd0;
pdata[63:0] <= 64'd0;
end
end
//FRAME SERDES
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b1), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_txdata
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_data[i]), // 1-bit output: Data path output
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(tx_data_t[i]), // 1-bit output: 3-state control
.CLK(tx_lclk), // 1-bit input: High speed clock
.CLKDIV(tx_lclk_par), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pdata[i+56]), // First data out
.D2(pdata[i+48]),
.D3(pdata[i+40]),
.D4(pdata[i+32]),
.D5(pdata[i+24]),
.D6(pdata[i+16]),
.D7(pdata[i+8]),
.D8(pdata[i]), // Last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(reset), // 1-bit input: Reset
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.T1(~ecfg_tx_enable), //TODO: Which clock is this one??
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b1) // 1-bit input: 3-state clock enable
);
end // block: gen_serdes
endgenerate
//DATA SERDES
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_tframe
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_frame), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(tx_lclk), // 1-bit input: High speed clock
.CLKDIV(tx_lclk_par), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pframe[7]), // first data out
.D2(pframe[6]),
.D3(pframe[5]),
.D4(pframe[4]),
.D5(pframe[3]),
.D6(pframe[2]),
.D7(pframe[1]),
.D8(pframe[0]), // last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(reset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
//################################
//# LCLK Creation (and gating)
//################################
//Don't worry about glitching, no dynamic frequency switching
//TODO: Enable dynamic frequency throttling (but why?)
ODDR
#(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst
(
.Q (tx_lclk_buf),
.C (tx_lclk_out),
.CE (1'b0),
.D1 (ecfg_tx_enable),
.D2 (1'b0),
.R (reset),
.S (1'b0));
//################################
//# Output Buffers
//################################
OBUFTDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFTDS_txdata [7:0]
(
.O (txo_data_p),
.OB (txo_data_n),
.I (tx_data),
.T (tx_data_t) //not sure about this??
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_txframe
(
.O (txo_frame_p),
.OB (txo_frame_n),
.I (tx_frame)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_lclk
(
.O (txo_lclk_p),
.OB (txo_lclk_n),
.I (tx_lclk_buf)
);
//################################
//# Wait Input Buffers
//################################
//TODO: make differential an option on both
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_txwrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait));
//TODO: Come up with cleaner defines for this
//Parallella and other platforms...
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_txwrwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
/*
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module menu_bg (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("menu_bg.mif"),
.C_INIT_FILE("menu_bg.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(11025),
.C_READ_DEPTH_A(11025),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(11025),
.C_READ_DEPTH_B(11025),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.22775 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_to_sw_port (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=15625 clk0_duty_cycle=50 clk0_multiply_by=576 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=TX_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="UART_TX_PLL_tx0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module TX_PLL_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 15625,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 576,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //TX_PLL_altpll
//VALID FILE
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXR Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These packets must
// meet max-request, max-payload, and payload termination requirements (see Read
// Completion Boundary). The TXR Engine does not check these requirements during
// operation, but may do so during simulation. This Engine is capable of
// operating at "line rate". This file also contains the txr_formatter module,
// which formats request headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txr_engine_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR Classic
input TXR_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
output TXR_TLP_VALID,
output TXR_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
output TXR_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY
);
`include "functions.vh"
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
txr_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txr_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txr_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXR_DATA_READY),
.TX_PKT (TXR_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXR_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXR_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXR_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXR_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXR_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXR_DATA_VALID),
.TX_DATA (TXR_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXR_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txr_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
`include "functions.vh"
wire wWrReq;
wire [`TLP_FMT_W-1:0] wHdrLoFmt;
wire [63:0] wHdrLo;
wire [63:0] _wTxHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddr[1:0];
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddrDW0;
wire wTxHdr4DW;
wire wTxHdrAlignmentNeeded;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign wHdrLoFmt = {1'b0, TXR_META_TYPE[`TRLS_TYPE_PAY_I],1'bx};
// Reserved Fields
assign wHdrLo[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wHdrLo[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wHdrLo[`TLP_TH_R] = `TLP_TH_W'b0;
assign wHdrLo[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wHdrLo[`TLP_RSVD2_R] = `TLP_RSVD2_V;
// Generic Header Fields
assign wHdrLo[`TLP_LEN_R] = TXR_META_LENGTH;
assign wHdrLo[`TLP_EP_R] = TXR_META_EP;
assign wHdrLo[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wHdrLo[`TLP_ATTR0_R] = TXR_META_ATTR[1:0];
assign wHdrLo[`TLP_ATTR1_R] = TXR_META_ATTR[2];
assign wHdrLo[`TLP_TYPE_R] = TXR_META_TYPE; // WORKAROUND
assign wHdrLo[`TLP_TC_R] = TXR_META_TC;
assign wHdrLo[`TLP_FMT_R] = wHdrLoFmt;
// Request Specific Fields
assign wHdrLo[`TLP_REQFBE_R] = TXR_META_FDWBE;
assign wHdrLo[`TLP_REQLBE_R] = TXR_META_LDWBE;
assign wHdrLo[`TLP_REQTAG_R] = TXR_META_TAG;
assign wHdrLo[`TLP_REQREQID_R] = CONFIG_COMPLETER_ID;
// Second header formatting stage
assign wTxHdr4DW = wTxHdrAddr[1] != 32'b0;
assign {wTxHdr[`TLP_FMT_R],wTxHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(_wTxHdr[`TLP_TYPE_I +: `SIG_TYPE_W],wTxHdr4DW);
assign wTxHdr[`TLP_TYPE_I-1:0] = _wTxHdr[`TLP_TYPE_I-1:0];
assign wTxHdr[63:32] = _wTxHdr[63:32];
assign wTxHdr[127:64] = {wTxHdrAddr[~wTxHdr4DW],wTxHdrAddr[wTxHdr4DW]};
// Metadata, to the aligner
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrAddrDW0 = wTxHdrAddr[0];
assign wTxHdrAlignmentNeeded = (wTxHdrAddrDW0[2] == wTxHdr4DW);
assign wTxHdrNonpayLen = {1'b0,{wTxHdr4DW,~wTxHdr4DW,~wTxHdr4DW}} + ((C_VENDOR == "ALTERA") ? {3'b0,(wTxHdrAlignmentNeeded & ~wTxHdrNopayload)}:0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXR_META_READY),
.RD_DATA ({wTxHdrAddr[1],wTxHdrAddr[0],_wTxHdr[63:0]}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({TXR_META_ADDR, wHdrLo}),
.WR_DATA_VALID (TXR_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 11:27:29 AM
// Design Name:
// Module Name: Barrel_shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Barrel_Shifter
//#(parameter SWR=26, parameter EWR=5) //Implicit bit + Significand Width (23 bits for simple format, 52 bits for Double format)
//+ guard Bit + round bit
#(parameter SWR=55, parameter EWR=6)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Shift_Data_i,
input wire Left_Right_i,
input wire Bit_Shift_i,
/////////////////////////////////////////////7
output wire [SWR-1:0] N_mant_o
);
wire [SWR-1:0] Data_Reg;
////////////////////////////////////////////////////7
Mux_Array #(.SWR(SWR),.EWR(EWR)) Mux_Array(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Shift_Value_i(Shift_Value_i),
.Data_i(Shift_Data_i),
.FSM_left_right_i(Left_Right_i),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_Reg)
);
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: NetFPGA_Gen2x8If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx NetFPGA Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module NetFPGA_Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [1:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
// Core Top Level Wrapper
PCIeGen2x8If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_NetFPGA
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
/*AUTOINST*/);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("../../../../riffa_hdl/" "../../")
// End:
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_data_mover (
input clk,
input resetn,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
input enable,
output reg enabled,
output xfer_req,
output s_axi_ready,
input s_axi_valid,
input [C_DATA_WIDTH-1:0] s_axi_data,
input m_axi_ready,
output m_axi_valid,
output [C_DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_DISABLE_WAIT_FOR_ID = 1;
parameter C_BEATS_PER_BURST_WIDTH = 4;
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00;
reg [C_ID_WIDTH-1:0] id = 'h00;
reg [C_ID_WIDTH-1:0] id_next = 'h00;
reg pending_burst = 1'b0;
reg active = 1'b0;
reg last_eot = 1'b0;
reg last_non_eot = 1'b0;
wire last_load;
wire last;
assign xfer_req = active;
assign response_id = id;
assign last = eot ? last_eot : last_non_eot;
assign s_axi_ready = m_axi_ready & pending_burst & active;
assign m_axi_valid = s_axi_valid & pending_burst & active;
assign m_axi_data = s_axi_data;
assign m_axi_last = last;
// If we want to support zero delay between transfers we have to assert
// req_ready on the same cycle on which the last load happens.
assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
assign req_ready = last_load || ~active;
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (C_DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)
enabled <= 1'b0;
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id)
enabled <= 1'b0;
end
end
end
end
always @(posedge clk) begin
if (req_ready) begin
last_eot <= req_last_burst_length == 'h0;
last_non_eot <= 1'b0;
beat_counter <= 'h1;
end else if (s_axi_ready && s_axi_valid) begin
last_eot <= beat_counter == last_burst_length;
last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
beat_counter <= beat_counter + 1;
end
end
always @(posedge clk) begin
if (req_ready)
last_burst_length <= req_last_burst_length;
end
always @(posedge clk) begin
if (enabled == 1'b0 || resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid) begin
active <= 1'b1;
end else if (last_load) begin
active <= 1'b0;
end
end
always @(*)
begin
if ((s_axi_ready && s_axi_valid && last) ||
(sync_id && pending_burst))
id_next <= inc_id(id);
else
id_next <= id;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
id <= id_next;
end
end
always @(posedge clk) begin
pending_burst <= id_next != request_id;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ed_e
//
// Generated
// by: wig
// on: Mon Sep 25 09:53:03 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ed_e.v,v 1.1 2006/09/25 15:14:59 wig Exp $
// $Date: 2006/09/25 15:14:59 $
// $Log: inst_ed_e.v,v $
// Revision 1.1 2006/09/25 15:14:59 wig
// Adding testcase for `foo support
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.93 2006/09/25 08:24:10 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ed_e
//
// No user `defines in this module
module inst_ed_e
//
// Generated Module inst_ed
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eda
inst_eda_e inst_eda (
);
// End of Generated Instance Port Map for inst_eda
// Generated Instance Port Map for inst_edb
inst_edb_e inst_edb (
);
// End of Generated Instance Port Map for inst_edb
endmodule
//
// End of Generated Module rtl of inst_ed_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbp (
RESET_B,
D ,
GATE ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_BLACKBOX_V
`define SKY130_FD_SC_LS__A221O_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_BLACKBOX_V
|
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "simple";
defparam `ADXL362_ACCELEROMETER.XDATA_FILE = "accelerometer_00_xdata.txt";
defparam `ADXL362_ACCELEROMETER.YDATA_FILE = "accelerometer_00_ydata.txt";
defparam `ADXL362_ACCELEROMETER.ZDATA_FILE = "accelerometer_00_zdata.txt";
defparam `ADXL362_ACCELEROMETER.TEMPERATURE_FILE = "accelerometer_00_temperature_data.txt";
parameter number_of_tests = 1;
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("Simple 00 Case");
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
$display("Wait for SPI to start #@ %d", $time);
@(negedge spi_testbench.ncs_o);
$display("SPI to started #@ %d", $time);
@(posedge spi_testbench.ncs_o);
$display("SPI done #@ %d", $time);
`TEST_COMPARE("TEMPERATURE", 16'h02A5, spi_testbench.dut.temperature);
#1000;
`TEST_COMPLETE;
end
endmodule // test_case
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:38 03/01/2016
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(
input CLOCK,
input RESET,
input [2:0] MODE,
output [7:0] LED,
input FAST
);
//for IO
//// GENRERATING SLOW CLOCK ////
wire CLK;
reg [26:0] Buffer = 0;
always@ (posedge CLOCK) Buffer = Buffer + 1;
assign CLK = FAST ? CLOCK : Buffer[26];
//// IO MODE SEL ////
wire [31:0] IF_CurrPC;
assign LED[7] = RESET;
assign LED[6] = CLK;
wire [5:0] OUTPUT;
assign LED[5:0] = OUTPUT;
wire [31:0] reg1;
wire [31:0] reg2;
wire [5:0] reg12;
assign reg12[5:3] = reg2;
assign reg12[2:0] = reg1;
wire [31:0] CURR_PC_IO;
assign CURR_PC_IO = IF_CurrPC>>2;
wire [5:0] TEMP1;
wire [5:0] TEMP2;
assign TEMP1 = MODE[0] ? reg1:reg12;
assign TEMP2 = MODE[1] ? reg2:TEMP1;
assign OUTPUT = MODE[2]? CURR_PC_IO:TEMP2;
//1.0 For stage IF to ID;
reg [31:0] IF_ID_PCAdd4;
reg [31:0] IF_ID_Instr;
//2.0 For stage ID to EX;
reg [31:0] ID_EX_PCAdd4;
reg [31:0] ID_EX_RegReadData1;
reg [31:0] ID_EX_RegReadData2;
reg [31:0] ID_EX_SignExt;
reg [20:16] ID_EX_InstHigh;
reg [15:11] ID_EX_InstLow;
//2.1 To EX
reg [31:0] ID_EX_Instr;
reg ID_EX_RegDst;
reg [1:0] ID_EX_ALUOp;
reg ID_EX_ALUSrc;
//2.2 To MEM
reg ID_EX_Jump;
reg ID_EX_Branch;
reg ID_EX_MemWrite;
reg ID_EX_MemRead;
//2.3 To WB
reg ID_EX_MemToReg;
reg ID_EX_RegWrite;
//3.0 For stage EX to MEM;
reg EX_MEM_Zero;
reg [31:0] EX_MEM_ALUOut;
reg [31:0] EX_MEM_BranchAddress;
reg [31:0] EX_MEM_JumpAddress;
reg [31:0] EX_MEM_RegReadData2;
//3.1 To MEM
reg EX_MEM_Branch;
reg EX_MEM_MemWrite;
reg EX_MEM_MemRead;
reg EX_MEM_Jump= 0;
reg [4:0] EX_MEM_RegWriteAddress; //rt or rd
//3.2 To WB
reg EX_MEM_MemToReg;
reg EX_MEM_RegWrite;
//4.0 For stage MEM to WB;
reg [31:0] MEM_WB_ALUOut;
reg [31:0] MEM_WB_MemReadData;
reg [4:0] MEM_WB_RegWriteAddress;
reg MEM_WB_RegWrite;
reg MEM_WB_MemToReg;
//////////////////////////////////////////////////////////////////////////////////////////////
//1.0 IF
wire IF_PCSrc, //for MUX sel signal
IF_Branch,
IF_Zero;
wire FLUSH;
wire IF_Jump;
wire [31:0] IF_BranchAddress;
wire [31:0] IF_JumpAddress;
//wire [31:0] IF_CurrPC; DEFINED BEFORE
wire [31:0] IF_NextPC;
wire [31:0] IF_PCAdd4;
wire [31:0] IF_Instr;
//associate with reg
assign FLUSH = RESET? 0: IF_Branch | IF_Jump;
assign IF_BranchAddress = EX_MEM_BranchAddress;
assign IF_Zero = EX_MEM_Zero;
assign IF_Branch = RESET? 0 : EX_MEM_Branch;
assign IF_Jump = RESET? 0 :EX_MEM_Jump;
assign IF_JumpAddress = EX_MEM_JumpAddress;
//Combinational Logic
assign IF_PCAdd4 = IF_CurrPC +4;
assign IF_PCSrc = IF_Branch & IF_Zero & ~RESET;
wire [31:0] IF_NextPCJ;
assign IF_NextPCJ = IF_Jump? IF_JumpAddress : IF_PCAdd4;
assign IF_NextPC = IF_PCSrc? IF_BranchAddress: IF_NextPCJ; //MUX
wire [31:0] IF_JumpAdress;
//assign IF_NextPC = IF_PCAdd4;
//update PC at posedge
Pc mainPC (
.clock_in(CLK),
.nextPC(IF_NextPC),
.currPC(IF_CurrPC),
.rst(RESET)
);
wire [31:0] IF_Index;
assign IF_Index = IF_CurrPC>>2;
instructionMemory InstrMemory (
.address(IF_Index),
.clock_in(CLK),
.reset(RESET),
.readData(IF_Instr)
);
//InstMem;
//1.5 IF/ID REG UPDATE
always @(posedge CLK)
begin
IF_ID_PCAdd4 <= FLUSH ? 0: IF_PCAdd4;
IF_ID_Instr <= FLUSH ? 0: IF_Instr;
end
//2.0 ID
wire [31:0] ID_Instr;
wire [5:0] ID_OpCode;
wire [31:0] ID_PCAdd4;
wire [4:0] ID_RegReadAddress1;
wire [4:0] ID_RegReadAddress2;
wire [15:0] ID_Imm;
wire [31:0] ID_SignExt;
wire [20:16] ID_InstHigh;
wire [15:11] ID_InstLow;
wire [31:0] ID_RegReadData1;
wire [31:0] ID_RegReadData2;
wire WB_RegWrite,
WB_MemToReg;
wire [4:0] WB_RegWriteAddress;
wire [31:0] WB_MemReadData;
wire [31:0] WB_ALUOut;
wire [31:0] WB_RegWriteData;
wire ID_Jump;
//associate with reg
assign ID_Instr = IF_ID_Instr;
assign ID_PCAdd4 = IF_ID_PCAdd4;
assign ID_OpCode = ID_Instr[31:26];
assign ID_RegReadAddress1 = ID_Instr[25:21];
assign ID_RegReadAddress2 = ID_Instr[20:16];
assign ID_Imm = ID_Instr[15:0];
assign ID_InstHigh = ID_Instr[20:16];
assign ID_InstLow = ID_Instr[15:11];
assign WB_RegWrite = MEM_WB_RegWrite;
assign WB_MemToReg = MEM_WB_MemToReg;
assign WB_RegWriteAddress = MEM_WB_RegWriteAddress;
assign WB_ALUOut = MEM_WB_ALUOut;
assign WB_MemReadData = MEM_WB_MemReadData;
assign WB_RegWriteData = WB_MemToReg? WB_MemReadData: WB_ALUOut;
Register mainReg (
.clock_in(CLK),
.regWrite(WB_RegWrite),
.readReg1(ID_RegReadAddress1),
.readReg2(ID_RegReadAddress2),
.writeReg(WB_RegWriteAddress),
.writeData(WB_RegWriteData),
.reset(RESET),
.readData1(ID_RegReadData1),
.readData2(ID_RegReadData2),
.reg1(reg1),
.reg2(reg2)
);
//To EX
wire [1:0] ID_ALUOp;
wire ID_RegDst,
ID_ALUSrc;
//2.2 To MEM
wire ID_Branch;
wire ID_MemWrite;
wire ID_MemRead;
//2.3 To WB
wire ID_MemToReg;
wire ID_RegWrite;
wire JUMP; //of no use
Ctr mainCtr (
.opCode(ID_OpCode),
.regDst(ID_RegDst),
.aluSrc(ID_ALUSrc),
.memToReg(ID_MemToReg),
.regWrite(ID_RegWrite),
.memRead(ID_MemRead),
.memWrite(ID_MemWrite),
.branch(ID_Branch),
.aluOp(ID_ALUOp),
.jump(ID_Jump)
);
signExt mainSignExt (
.inst(ID_Imm),
.data(ID_SignExt)
);
//2.5 ID/EX REG UPDATE
always @(posedge CLK)
begin
//2.0 For Stage ID To EX
ID_EX_PCAdd4 <= FLUSH ? 0: ID_PCAdd4;
ID_EX_RegReadData1 <= FLUSH ? 0: ID_RegReadData1;
ID_EX_RegReadData2 <= FLUSH ? 0: ID_RegReadData2;
ID_EX_SignExt <= FLUSH ? 0: ID_SignExt;
ID_EX_InstHigh <= FLUSH ? 0: ID_InstHigh;
ID_EX_InstLow <= FLUSH ? 0: ID_InstLow;
//2.1 To EX
ID_EX_RegDst <= FLUSH ? 0: ID_RegDst;
ID_EX_ALUOp <= FLUSH ? 0: ID_ALUOp;
ID_EX_ALUSrc <= FLUSH ? 0: ID_ALUSrc;
//2.2 To MEM
ID_EX_Branch <= FLUSH ? 0: ID_Branch;
ID_EX_MemWrite <= FLUSH ? 0: ID_MemWrite;
ID_EX_MemRead <= FLUSH ? 0: ID_MemRead;
//2.3 To WB
ID_EX_MemToReg <= FLUSH ? 0: ID_MemToReg;
ID_EX_RegWrite <= FLUSH ? 0: ID_RegWrite;
end
//3.0 EX
//2.0 For stage ID to EX;
wire [31:0] EX_PCAdd4;
wire [31:0] EX_ALUSrc1;
wire [31:0] EX_ALUSrc2;
wire [31:0] EX_RegReadData2;
wire [31:0] EX_SignExt;
wire [20:16] EX_InstHigh;
wire [15:11] EX_InstLow;
wire [31:0] EX_Instr;
wire EX_RegDst,
EX_ALUSrc;
wire [1:0] EX_ALUOp;
wire [4:0] EX_RegWriteAddress;
wire [5:0] EX_Funct;
wire EX_Jump;
wire [31:0] EX_JumpAddress;
//associate with Reg
assign EX_RegDst = ID_EX_RegDst;
assign EX_ALUOp = ID_EX_ALUOp;
assign EX_ALUSrc1 = ID_EX_RegReadData1;
assign EX_ALUSrc = ID_EX_ALUSrc; //contral signal
assign EX_ALUSrc2 = EX_ALUSrc? EX_SignExt: EX_RegReadData2;
assign EX_RegWriteAddress = EX_RegDst? EX_InstLow: EX_InstHigh; //MUX
assign EX_PCAdd4 = ID_EX_PCAdd4;
assign EX_RegReadData2 = ID_EX_RegReadData2;
assign EX_SignExt = ID_EX_SignExt;
assign EX_Funct = ID_EX_SignExt[5:0];
assign EX_InstHigh = ID_EX_InstHigh;
assign EX_InstLow = ID_EX_InstLow;
assign EX_Jump = ID_EX_Jump;
assign EX_Instr = ID_EX_Instr;
assign EX_JumpAddress[31:28] = EX_PCAdd4[31:28];
assign EX_JumpAddress[27:2] = EX_Instr[25:0];
assign EX_JumpAddress[1:0] = 2'b00;//Instances
wire [3:0] EX_ALUCtr;
AluCtr mainALUCtr (
.aluOp(EX_ALUOp),
.funct(EX_Funct),
.aluCtr(EX_ALUCtr)
);
wire EX_Zero;
wire [31:0] EX_ALUOut;
wire [31:0] EX_ALUSrc1_f;
wire [31:0] EX_ALUSrc2_f;
Alu mainALU (
.input1(EX_ALUSrc1_f),
.input2(EX_ALUSrc2_f),
.aluCtr(EX_ALUCtr),
.zero(EX_Zero),
.aluRes(EX_ALUOut)
);
//2.2 To MEM
wire EX_Branch,
EX_MemWrite,
EX_MemRead;
assign EX_Branch = ID_EX_Branch;
assign EX_MemWrite = ID_EX_MemWrite;
assign EX_MemRead = ID_EX_MemRead;
//2.3 To WB
wire EX_MemToReg,
EX_RegWrite;
assign EX_MemToReg = ID_EX_MemToReg;
assign EX_RegWrite = ID_EX_RegWrite;
//BranchAddress
wire [31:0] EX_BranchAddress;
assign EX_BranchAddress = (EX_SignExt<<2) + EX_PCAdd4;
//3.5 EX/MEM REG UPDATE
always @(posedge CLK)
begin
EX_MEM_Branch <= FLUSH ? 0: EX_Branch;
EX_MEM_MemWrite <= FLUSH ? 0: EX_MemWrite;
EX_MEM_MemRead <= FLUSH ? 0: EX_MemRead;
EX_MEM_MemToReg <= FLUSH ? 0: EX_MemToReg;
EX_MEM_RegWrite <= FLUSH ? 0: EX_RegWrite;
EX_MEM_BranchAddress <= FLUSH ? 0: EX_BranchAddress;
EX_MEM_Zero <= FLUSH ? 0: EX_Zero;
EX_MEM_ALUOut <= FLUSH ? 0: EX_ALUOut;
EX_MEM_RegWriteAddress <= FLUSH ? 0: EX_RegWriteAddress;
EX_MEM_RegReadData2 <= FLUSH ? 0: EX_RegReadData2;
end
//4.0 MEM
wire MEM_MemWrite,
MEM_MemRead;
wire [4:0] MEM_RegWriteAddress;
wire [31:0] MEM_ALUOut;
wire [31:0] MEM_MemWriteData;
wire [31:0] MEM_MemReadData;
//associate with reg
assign MEM_MemWrite = EX_MEM_MemWrite;
assign MEM_MemRead = EX_MEM_MemRead;
assign MEM_RegWriteAddress = EX_MEM_RegWriteAddress;
assign MEM_ALUOut = EX_MEM_ALUOut;
assign MEM_MemWriteData = EX_MEM_RegReadData2;
//instances
dataMemory DataMemory (
.clock_in(CLK),
.address(MEM_ALUOut),
.writeData(MEM_MemWriteData),
.readData(MEM_MemReadData),
.memWrite(MEM_MemWrite),
.memRead(MEM_MemRead)
);
//to WB
wire MEM_MemToReg,
MEM_RegWrite;
assign MEM_MemToReg = EX_MEM_MemToReg;
assign MEM_RegWrite = EX_MEM_RegWrite;
//4.5 MEM/WB REG UPDATE
always @(posedge CLK)
begin
MEM_WB_ALUOut = MEM_ALUOut;
MEM_WB_MemReadData = MEM_MemReadData;
MEM_WB_RegWriteAddress = MEM_RegWriteAddress;
MEM_WB_RegWrite = MEM_RegWrite;
MEM_WB_MemToReg = MEM_MemToReg;
end
//UPDATE REGISTER USED FOR JUMP
always @(posedge CLK) begin
ID_EX_Jump <= ID_Jump;
ID_EX_Instr <= ID_Instr;
EX_MEM_Jump <= EX_Jump;
EX_MEM_JumpAddress <= EX_JumpAddress;
end
//FORWARDING PART
//MUX
//wire [31:0] EX_ALUSrc1_f; //as mux output;
//wire [31:0] EX_ALUSrc2_f; //defined before ALU
wire [31:0] EX_MEM_ALU; //input from other stage
wire [31:0] MEM_WB_ALU;
assign EX_MEM_ALU = EX_MEM_ALUOut;
assign MEM_WB_ALU = MEM_WB_ALUOut;
wire [1:0] forwardA;
wire [1:0] forwardB;
//FORWARD UNIT
wire [4:0] EX_MEM_regWriteAddress_f;
wire [4:0] MEM_WB_regWriteAddress_f;
wire MEM_WB_regWrite_f;
wire EX_MEM_regWrite_f;
wire [4:0] rs_f;
wire [4:0] rt_f;
assign EX_MEM_regWriteAddress_f = EX_MEM_RegWriteAddress;
assign MEM_WB_regWriteAddress_f = MEM_WB_RegWriteAddress;
assign EX_MEM_regWrite_f = EX_MEM_RegWrite;
assign MEM_WB_regWrite_f = MEM_WB_RegWrite;
assign rs_f = ID_EX_Instr[25:21];//ID_EX
assign rt_f = ID_EX_Instr[20:16];
forwardUnit mainFUnit (
.rs(rs_f),
.rt(rt_f),
.MEM_WB_regWrite(MEM_WB_regWrite_f),
.MEM_WB_rd(MEM_WB_regWriteAddress_f),
.EX_MEM_regWrite(EX_MEM_regWrite_f),
.EX_MEM_rd(EX_MEM_regWriteAddress_f),
.forwardA(forwardA),
.forwardB(forwardB),
.rst(RESET)
);
forwardMux MUXA (
.ID_EX(EX_ALUSrc1),
.EX_MEM(EX_MEM_ALU),
.MEM_WB(MEM_WB_ALU),
.Forward(forwardA),
.Sel(EX_ALUSrc1_f)
);
forwardMux MUXB (
.ID_EX(EX_ALUSrc2),
.EX_MEM(EX_MEM_ALU),
.MEM_WB(MEM_WB_ALU),
.Forward(forwardB),
.Sel(EX_ALUSrc2_f)
);
endmodule
|
/*
PC to FPGA Command Table
Command Description Operand
data_bus_in[7:4] data_bus[3:0]
---------------- -------------------------------- --------------------
0 - Unused / illegal N/A
1 - Request panel selector data N/A
2 - Set panel address {2'b0, panel_addr}
3 - Set row address row_addr
4 - Set chunk address chunk_addr
5 - Set nibble 0 of chunk nibble
6 - Set nibble 1 of chunk nibble
7 - Set nibble 2 of chunk nibble
8 - Set nibble 3 of chunk nibble
9 - Set nibble 4 of chunk nibble
10 - Set nibble 5 of chunk nibble
11 - Set nibble 6 of chunk nibble
12 - Set nibble 7 of chunk nibble
13 - Write chunk N/A
14 - Unused / illegal N/A
15 - Unused / illegal N/A
FPGA to PC Command Table
Command Description Operand
data_bus_out[7:4] data_bus[3:0]
----------------- -------------------------------- --------------------
0 - Unused / illegal N/A
1 - Set panel 0 number panel_switches[3:0]
2 - Set panel 1 number panel_switches[7:4]
3 - Set panel 2 number panel_switches[11:8]
4 - Set panel 3 number panel_switches[15:12]
5 - Unused / illegal N/A
6 - Unused / illegal N/A
7 - Unused / illegal N/A
8 - Unused / illegal N/A
9 - Unused / illegal N/A
10 - Unused / illegal N/A
10 - Unused / illegal N/A
11 - Unused / illegal N/A
12 - Unused / illegal N/A
13 - Unused / illegal N/A
14 - Unused / illegal N/A
15 - Unused / illegal N/A
*/
module usb_controller
(
input clk,
input reset_n,
input [15:0] panel_switches_raw,
input rxf_n_raw,
input txe_n_raw,
input [7:0] data_bus_in_raw,
output [7:0] data_bus_out,
output rd_n,
output wr_n,
output data_out_enable,
output [31:0] chunk_data,
output [3:0] chunk_addr,
output chunk_write_enable,
output [3:0] row_addr,
output [1:0] panel_addr,
output [4:0] state_out,
output panel_select_request
);
wire rxf_n, txe_n;
wire command_write_enable, clear_psr;
wire [15:0] panel_switches;
wire [7:0] data_bus_in;
wire [15:0] command_select;
assign chunk_write_enable = command_select[13] & command_write_enable;
synchronizer #(.WIDTH(16)) panel_sw_sync
(.clk(clk), .in(panel_switches_raw), .out(panel_switches));
synchronizer #(.WIDTH(8)) data_bus_input_sync
(.clk(clk), .in(data_bus_in_raw), .out(data_bus_in));
synchronizer #(.WIDTH(2)) rx_tx_sync
(.clk(clk), .in({rxf_n_raw, txe_n_raw}), .out({rxf_n, txe_n}));
usb_sequencer seq
(.clk(clk),
.reset_n(reset_n),
.rxf_n(rxf_n),
.txe_n(txe_n),
.panel_select_request(panel_select_request),
.panel_switches(panel_switches),
.data_out(data_bus_out),
.rd_n(rd_n),
.wr_n(wr_n),
.data_out_enable(data_out_enable),
.command_write_enable(command_write_enable),
.clear_psr(clear_psr),
.state_out(state_out));
decoder #(.WIDTH(4)) command_decoder
(.addr(data_bus_in[7:4]), .y(command_select));
jk_flipflop panel_select_request_register
(.clk(clk),
.reset_n(reset_n),
.j(command_select[1] & command_write_enable),
.k(clear_psr),
.q(panel_select_request));
register_with_write_enable #(.WIDTH(2)) panel_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[2] & command_write_enable),
.d(data_bus_in[1:0]),
.q(panel_addr));
register_with_write_enable #(.WIDTH(4)) row_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[3] & command_write_enable),
.d(data_bus_in[3:0]),
.q(row_addr));
register_with_write_enable #(.WIDTH(4)) chunk_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[4] & command_write_enable),
.d(data_bus_in[3:0]),
.q(chunk_addr));
genvar i;
generate
for (i=0; i<8; i=i+1)
begin : nibble_registers
register_with_write_enable #(.WIDTH(4)) nibble_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[i+5] & command_write_enable),
.d(data_bus_in[3:0]),
.q(chunk_data[4*i+3:4*i]));
end
endgenerate
endmodule // usb_controller
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[3]),
.D (sw[14]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[2]),
.D (sw[13]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram1 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[1]),
.D (sw[12]),
.WE (sw[15])
);
RAM32X1S #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram2 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[0]),
.D (sw[11]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_4_V
`define SKY130_FD_SC_MS__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_4_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
reg probepresent /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
probepresent <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
probepresent <= jdo[19] ? 1
: jdo[18] ? 0
: probepresent;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset)
begin
jtag_break <= probepresent;
resetlatch <= 1;
end
else if (~debugack & debugreq & probepresent)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "STRATIXIV",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonWr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (MonDReg[31 : 0]),
.q_a (oci_ram_readdata),
.q_b (sramdout),
.wren_a (chipselect & write & debugaccess &
~address[8]
),
.wren_b (MonWr)
);
//synthesis translate_off
`ifdef NO_PLI
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_default_contents.dat";
`else
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgdout = (MonAReg[4 : 2] == 3'd0)? 32'h00010020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001311 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00010000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input chipselect;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = chipselect & write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000000);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 14: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 16: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 18: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 18: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 18: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exception;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire synced;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exception = 1'b0;
assign is_exception = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign synced = pending_frametype != 4'b1010;
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
end
else if (instr_retired | advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) & (
~record_itrace |
is_idct |
is_exception |
record_dct_outcome_in_sync
))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & synced & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (pending_frametype != 4'b0000))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
end
else if (record_itrace & synced & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= 4'b0000;
end
end
else
itm <= 4'b0000;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 18: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_trc_ctrl_td_mode, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_td_mode ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count_tm_count, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc_fifowp, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc_fifocount, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 35: 0] q_a;
output [ 35: 0] q_b;
input [ 6: 0] address_a;
input [ 6: 0] address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 35: 0] data_a;
input [ 35: 0] data_b;
input wren_a;
input wren_b;
wire [ 35: 0] q_a;
wire [ 35: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "STRATIXIV",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 128,
the_altsyncram.numwords_b = 128,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 36,
the_altsyncram.width_b = 36,
the_altsyncram.widthad_a = 7,
the_altsyncram.widthad_b = 7,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 35: 0] trc_jtag_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire [ 35: 0] unused_bdpram_port_q_a;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = (0) ?
trc_jtag_data : 0;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component
(
.address_a (trc_im_addr),
.address_b (trc_jtag_addr),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (trc_im_data),
.data_b (jdo[36 : 1]),
.q_a (unused_bdpram_port_q_a),
.q_b (trc_jtag_data),
.wren_a (tw_valid & trc_enb),
.wren_b (take_action_tracemem_b)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address,
av_ld_data_aligned_filtered,
begintransfer,
byteenable,
chipselect,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess,
hbreak_enabled,
reset,
reset_n,
test_ending,
test_has_ended,
write,
writedata,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 14: 0] F_pc;
input [ 8: 0] address;
input [ 31: 0] av_ld_data_aligned_filtered;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input [ 18: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess;
input hbreak_enabled;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] MonDReg;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
wire clkx2;
wire [ 18: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_debug the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_ocimem the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.begintransfer (begintransfer),
.byteenable (byteenable),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.oci_ram_readdata (oci_ram_readdata),
.resetrequest (resetrequest),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.write (write),
.writedata (writedata)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_avalon_reg the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_avalon_reg
(
.address (address),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_break the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_xbrk the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dbrk the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_itrace the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dtrace the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifo the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_pib the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_im the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign readdata = address[8] ? oci_reg_readdata : oci_ram_readdata;
assign jtag_debug_module_debugaccess_to_roms = debugack;
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_begintransfer,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_select,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
no_ci_readra
)
;
output [ 18: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 16: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input jtag_debug_module_begintransfer;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_select;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 14: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 18: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 14: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 14: 0] F_pc_no_crst_nxt;
wire [ 14: 0] F_pc_nxt;
wire [ 14: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 16: 0] F_pcb;
wire [ 16: 0] F_pcb_nxt;
wire [ 16: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 18: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 18: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 16: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench, which is an e_instance
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cmp_result (W_cmp_result),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000000;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 16392 :
(F_pc_sel_nxt == 2'b01)? 8 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[16 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 16384;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a, which is an nios_sdp_ram
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a_module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_a.dat";
`else
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b, which is an nios_sdp_ram
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b_module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_b.dat";
`else
defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[18 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[18 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000000;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000000;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci the_ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.begintransfer (jtag_debug_module_begintransfer),
.byteenable (jtag_debug_module_byteenable),
.chipselect (jtag_debug_module_select),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.write (jtag_debug_module_write),
.writedata (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
resetrequest <= 1'b0;
break_on_reset <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 19: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 21: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 21: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
itm,
trc_ctrl,
trc_on
)
;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h180020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
end
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 1'b0;
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 21: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//limbus_cpu_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
limbus_cpu_cpu_nios2_oci_td_mode limbus_cpu_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else
begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dtm,
itm,
jrst_n,
reset_n,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
limbus_cpu_cpu_nios2_oci_compute_input_tm_cnt the_limbus_cpu_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
limbus_cpu_cpu_nios2_oci_fifo_wrptr_inc the_limbus_cpu_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
limbus_cpu_cpu_nios2_oci_fifo_cnt_inc the_limbus_cpu_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_pib (
// outputs:
tr_data
)
;
output [ 35: 0] tr_data;
wire [ 35: 0] tr_data;
assign tr_data = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000011111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000011111);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//limbus_cpu_cpu_ociram_sp_ram, which is an nios_sp_ram
limbus_cpu_cpu_ociram_sp_ram_module limbus_cpu_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_cpu_cpu_ociram_sp_ram.lpm_file = "limbus_cpu_cpu_ociram_default_contents.dat";
`else
defparam limbus_cpu_cpu_ociram_sp_ram.lpm_file = "limbus_cpu_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00180020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001616 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00180000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
write_nxt,
writedata_nxt,
// outputs:
debug_mem_slave_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output debug_mem_slave_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 19: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire debug_mem_slave_debugaccess_to_roms;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire [ 35: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
limbus_cpu_cpu_nios2_oci_debug the_limbus_cpu_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
limbus_cpu_cpu_nios2_oci_break the_limbus_cpu_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
limbus_cpu_cpu_nios2_oci_xbrk the_limbus_cpu_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
limbus_cpu_cpu_nios2_oci_dbrk the_limbus_cpu_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
limbus_cpu_cpu_nios2_oci_itrace the_limbus_cpu_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
limbus_cpu_cpu_nios2_oci_dtrace the_limbus_cpu_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
limbus_cpu_cpu_nios2_oci_fifo the_limbus_cpu_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.trc_on (trc_on),
.tw (tw)
);
limbus_cpu_cpu_nios2_oci_pib the_limbus_cpu_cpu_nios2_oci_pib
(
.tr_data (tr_data)
);
limbus_cpu_cpu_nios2_oci_im the_limbus_cpu_cpu_nios2_oci_im
(
.clk (clk),
.jrst_n (jrst_n),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
limbus_cpu_cpu_nios2_avalon_reg the_limbus_cpu_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
limbus_cpu_cpu_nios2_ocimem the_limbus_cpu_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign debug_mem_slave_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
limbus_cpu_cpu_debug_slave_wrapper the_limbus_cpu_cpu_debug_slave_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_data |
trigout |
debugack;
assign debugreq = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu (
// inputs:
clk,
d_readdata,
d_waitrequest,
debug_mem_slave_address,
debug_mem_slave_byteenable,
debug_mem_slave_debugaccess,
debug_mem_slave_read,
debug_mem_slave_write,
debug_mem_slave_writedata,
i_readdata,
i_waitrequest,
irq,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
debug_mem_slave_debugaccess_to_roms,
debug_mem_slave_readdata,
debug_mem_slave_waitrequest,
debug_reset_request,
dummy_ci_port,
i_address,
i_read
)
;
output [ 21: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output debug_mem_slave_debugaccess_to_roms;
output [ 31: 0] debug_mem_slave_readdata;
output debug_mem_slave_waitrequest;
output debug_reset_request;
output dummy_ci_port;
output [ 21: 0] i_address;
output i_read;
input clk;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 8: 0] debug_mem_slave_address;
input [ 3: 0] debug_mem_slave_byteenable;
input debug_mem_slave_debugaccess;
input debug_mem_slave_read;
input debug_mem_slave_write;
input [ 31: 0] debug_mem_slave_writedata;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 31: 0] irq;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_and;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_intr_inst;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_ex;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_ld_st_ex;
wire D_ctrl_logic;
wire D_ctrl_mem16;
wire D_ctrl_mem32;
wire D_ctrl_mem8;
wire D_ctrl_rd_ctl_reg;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_set_src2_rem_imm;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_signed_imm12;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_src_imm5_shift_rot;
wire D_ctrl_st;
wire D_ctrl_st_ex;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
wire D_is_opx_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 4: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 19: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 71: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 21: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
wire E_rf_ecc_recoverable_valid;
wire E_rf_ecc_unrecoverable_valid;
wire E_rf_ecc_valid_any;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire [ 4: 0] E_shift_rot_shfcnt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
wire E_valid;
reg E_valid_from_R;
wire [ 71: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 4: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire F_is_opx_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 4: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_op_rsv02;
wire F_op_op_rsv09;
wire F_op_op_rsv10;
wire F_op_op_rsv17;
wire F_op_op_rsv18;
wire F_op_op_rsv25;
wire F_op_op_rsv26;
wire F_op_op_rsv33;
wire F_op_op_rsv34;
wire F_op_op_rsv41;
wire F_op_op_rsv42;
wire F_op_op_rsv49;
wire F_op_op_rsv57;
wire F_op_op_rsv61;
wire F_op_op_rsv62;
wire F_op_op_rsv63;
wire F_op_opx_rsv00;
wire F_op_opx_rsv10;
wire F_op_opx_rsv15;
wire F_op_opx_rsv17;
wire F_op_opx_rsv21;
wire F_op_opx_rsv25;
wire F_op_opx_rsv33;
wire F_op_opx_rsv34;
wire F_op_opx_rsv35;
wire F_op_opx_rsv42;
wire F_op_opx_rsv43;
wire F_op_opx_rsv44;
wire F_op_opx_rsv47;
wire F_op_opx_rsv50;
wire F_op_opx_rsv51;
wire F_op_opx_rsv55;
wire F_op_opx_rsv56;
wire F_op_opx_rsv60;
wire F_op_opx_rsv63;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 19: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 19: 0] F_pc_no_crst_nxt;
wire [ 19: 0] F_pc_nxt;
wire [ 19: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 21: 0] F_pcb;
wire [ 21: 0] F_pcb_nxt;
wire [ 21: 0] F_pcb_plus_four;
wire F_valid;
wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_and;
wire R_ctrl_alu_force_and_nxt;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_intr_inst;
wire R_ctrl_intr_inst_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_ex;
wire R_ctrl_ld_ex_nxt;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_ld_st_ex;
wire R_ctrl_ld_st_ex_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_mem16;
wire R_ctrl_mem16_nxt;
reg R_ctrl_mem32;
wire R_ctrl_mem32_nxt;
reg R_ctrl_mem8;
wire R_ctrl_mem8_nxt;
reg R_ctrl_rd_ctl_reg;
wire R_ctrl_rd_ctl_reg_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_set_src2_rem_imm;
wire R_ctrl_set_src2_rem_imm_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_signed_imm12;
wire R_ctrl_signed_imm12_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_src_imm5_shift_rot;
wire R_ctrl_src_imm5_shift_rot_nxt;
reg R_ctrl_st;
reg R_ctrl_st_ex;
wire R_ctrl_st_ex_nxt;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_a_q;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_rf_b_q;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
wire [ 31: 0] R_stw_data;
reg R_valid;
wire [ 71: 0] R_vinst;
reg R_wr_dst_reg;
reg W1_rf_ecc_recoverable_valid;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg [ 31: 0] W_cdsr_reg;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
wire [ 4: 0] W_dst_regnum;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 21: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_up_ex_mon_state;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 71: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 21: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
wire debug_mem_slave_clk;
wire debug_mem_slave_debugaccess_to_roms;
wire [ 31: 0] debug_mem_slave_readdata;
wire debug_mem_slave_reset;
wire debug_mem_slave_waitrequest;
wire debug_reset_request;
wire dummy_ci_port;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 21: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_limbus_cpu_cpu_test_bench, which is an e_instance
limbus_cpu_cpu_test_bench the_limbus_cpu_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_break (R_ctrl_break),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cdsr_reg (W_cdsr_reg),
.W_cmp_result (W_cmp_result),
.W_cpuid_reg (W_cpuid_reg),
.W_dst_regnum (W_dst_regnum),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_ecc_unrecoverable_valid (W_rf_ecc_unrecoverable_valid),
.W_rf_ecc_valid_any (W_rf_ecc_valid_any),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[10 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[10 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[10 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_op_rsv02 = F_iw_op == 2;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_op_rsv09 = F_iw_op == 9;
assign F_op_op_rsv10 = F_iw_op == 10;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_op_rsv17 = F_iw_op == 17;
assign F_op_op_rsv18 = F_iw_op == 18;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_op_rsv25 = F_iw_op == 25;
assign F_op_op_rsv26 = F_iw_op == 26;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_op_rsv33 = F_iw_op == 33;
assign F_op_op_rsv34 = F_iw_op == 34;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_op_rsv41 = F_iw_op == 41;
assign F_op_op_rsv42 = F_iw_op == 42;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_op_rsv49 = F_iw_op == 49;
assign F_op_custom = F_iw_op == 50;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_op_rsv57 = F_iw_op == 57;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_op_rsv61 = F_iw_op == 61;
assign F_op_op_rsv62 = F_iw_op == 62;
assign F_op_op_rsv63 = F_iw_op == 63;
assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
assign F_is_opx_inst = F_iw_op == 58;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign dummy_ci_port = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = irq[31 : 0] & 32'b00000000000000000000000000011111;
assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 393224 :
(F_pc_sel_nxt == 2'b01)? 524808 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[21 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid | W_rf_ecc_unrecoverable_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 393216;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | W_rf_ecc_unrecoverable_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid | W1_rf_ecc_recoverable_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 :
D_ctrl_alu_force_and ? 2'b01 :
D_logic_op_raw;
assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign E_rf_ecc_valid_any = E_rf_ecc_recoverable_valid|E_rf_ecc_unrecoverable_valid;
assign W_rf_ecc_valid_any = W_rf_ecc_recoverable_valid|W_rf_ecc_unrecoverable_valid;
assign E_rf_ecc_recoverable_valid = 1'b0;
assign E_rf_ecc_unrecoverable_valid = 1'b0;
assign W_dst_regnum = R_dst_regnum;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_recoverable_valid <= 0;
else
W_rf_ecc_recoverable_valid <= E_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W1_rf_ecc_recoverable_valid <= 0;
else
W1_rf_ecc_recoverable_valid <= W_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_unrecoverable_valid <= 0;
else
W_rf_ecc_unrecoverable_valid <= E_rf_ecc_unrecoverable_valid & ~E_rf_ecc_recoverable_valid;
end
assign R_rf_a = R_rf_a_q;
assign R_rf_b = R_rf_b_q;
assign W_rf_wren = (R_wr_dst_reg & W_valid) | W_rf_ecc_valid_any | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//limbus_cpu_cpu_register_bank_a, which is an nios_sdp_ram
limbus_cpu_cpu_register_bank_a_module limbus_cpu_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a_q),
.rdaddress (D_iw_a),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_cpu_cpu_register_bank_a.lpm_file = "limbus_cpu_cpu_rf_ram_a.dat";
`else
defparam limbus_cpu_cpu_register_bank_a.lpm_file = "limbus_cpu_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//limbus_cpu_cpu_register_bank_b, which is an nios_sdp_ram
limbus_cpu_cpu_register_bank_b_module limbus_cpu_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b_q),
.rdaddress (D_iw_b),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_cpu_cpu_register_bank_b.lpm_file = "limbus_cpu_cpu_rf_ram_b.dat";
`else
defparam limbus_cpu_cpu_register_bank_b.lpm_file = "limbus_cpu_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
assign R_src1 = (((R_ctrl_br & E_valid_from_R) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid_from_R))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_src_imm5_shift_rot)? {{11 {1'b0}},D_iw_imm5} :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid_from_R <= 0;
else
E_valid_from_R <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_valid = E_valid_from_R & ~E_rf_ecc_valid_any;
assign E_stall = (E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall) & ~(E_rf_ecc_valid_any|W_rf_ecc_valid_any|W1_rf_ecc_recoverable_valid);
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[21 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_shfcnt = E_src2[4 : 0];
assign E_shift_rot_cnt_nxt = E_new_inst ? E_shift_rot_shfcnt : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 5'd0)? W_status_reg :
(D_iw_control_regnum == 5'd1)? W_estatus_reg :
(D_iw_control_regnum == 5'd2)? W_bstatus_reg :
(D_iw_control_regnum == 5'd3)? W_ienable_reg :
(D_iw_control_regnum == 5'd4)? W_ipending_reg :
(D_iw_control_regnum == 5'd5)? W_cpuid_reg :
W_cdsr_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rd_ctl_reg))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_sth_data = R_rf_b[15 : 0];
assign R_stw_data = R_rf_b[31 : 0];
assign R_stb_data = R_rf_b[7 : 0];
assign E_st_data = (D_ctrl_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_ctrl_mem16)? {R_sth_data, R_sth_data} :
R_stw_data;
assign E_mem_byte_en = ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst & ~E_rf_ecc_valid_any) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = ((R_ctrl_st & (~R_ctrl_st_ex | W_up_ex_mon_state)) & E_new_inst & ~E_rf_ecc_valid_any) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_ctrl_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_ctrl_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_ctrl_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_ctrl_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_ctrl_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_up_ex_mon_state <= 0;
else if (R_en)
W_up_ex_mon_state <= (R_ctrl_ld_ex & W_valid) ? 1'b1 :
((D_op_eret & W_valid) | (R_ctrl_st_ex & W_valid)) ? 1'b0 :
W_up_ex_mon_state;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= D_ctrl_intr_inst ? W_status_reg : E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cdsr_reg <= 0;
else
W_cdsr_reg <= 0;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rd_ctl_reg ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[21 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst | W_rf_ecc_unrecoverable_valid) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception|W_rf_ecc_unrecoverable_valid) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000011111;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000011111;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
limbus_cpu_cpu_nios2_oci the_limbus_cpu_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (debug_mem_slave_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (debug_mem_slave_byteenable),
.clk (debug_mem_slave_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
.debugaccess_nxt (debug_mem_slave_debugaccess),
.hbreak_enabled (hbreak_enabled),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (debug_mem_slave_read),
.readdata (debug_mem_slave_readdata),
.reset (debug_mem_slave_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (debug_reset_request),
.waitrequest (debug_mem_slave_waitrequest),
.write_nxt (debug_mem_slave_write),
.writedata_nxt (debug_mem_slave_writedata)
);
//debug_mem_slave, which is an e_avalon_slave
assign debug_mem_slave_clk = clk;
assign debug_mem_slave_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv44|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = 1'b0;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_rd_ctl_reg = D_op_rdctl;
assign R_ctrl_rd_ctl_reg_nxt = D_ctrl_rd_ctl_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rd_ctl_reg <= 0;
else if (R_en)
R_ctrl_rd_ctl_reg <= R_ctrl_rd_ctl_reg_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|D_op_jmpi|D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_ror;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|D_op_srl|D_op_srai|D_op_sra|D_op_ror;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_sll|
D_op_roli|
D_op_rol|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_ror;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_set_src2_rem_imm = 1'b0;
assign R_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_set_src2_rem_imm <= 0;
else if (R_en)
R_ctrl_set_src2_rem_imm <= R_ctrl_set_src2_rem_imm_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_signed_imm12 = 1'b0;
assign R_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_signed_imm12 <= 0;
else if (R_en)
R_ctrl_signed_imm12 <= R_ctrl_signed_imm12_nxt;
end
assign D_ctrl_src_imm5_shift_rot = D_op_roli|D_op_slli|D_op_srli|D_op_srai;
assign R_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src_imm5_shift_rot <= 0;
else if (R_en)
R_ctrl_src_imm5_shift_rot <= R_ctrl_src_imm5_shift_rot_nxt;
end
assign D_ctrl_br_uncond = D_op_br;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|D_op_bge|D_op_blt|D_op_bne|D_op_beq|D_op_bgeu|D_op_bltu;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_bgeu;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_ex = 1'b0;
assign R_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_ex <= 0;
else if (R_en)
R_ctrl_ld_ex <= R_ctrl_ld_ex_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st_ex = 1'b0;
assign R_ctrl_st_ex_nxt = D_ctrl_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st_ex <= 0;
else if (R_en)
R_ctrl_st_ex <= R_ctrl_st_ex_nxt;
end
assign D_ctrl_st = D_op_stb|D_op_sth|D_op_stw|D_op_stbio|D_op_sthio|D_op_stwio;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_st_ex = 1'b0;
assign R_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_st_ex <= 0;
else if (R_en)
R_ctrl_ld_st_ex <= R_ctrl_ld_st_ex_nxt;
end
assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
assign R_ctrl_mem8_nxt = D_ctrl_mem8;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem8 <= 0;
else if (R_en)
R_ctrl_mem8 <= R_ctrl_mem8_nxt;
end
assign D_ctrl_mem16 = D_op_ldhu|D_op_ldh|D_op_ldhio|D_op_ldhuio|D_op_sth|D_op_sthio;
assign R_ctrl_mem16_nxt = D_ctrl_mem16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem16 <= 0;
else if (R_en)
R_ctrl_mem16 <= R_ctrl_mem16_nxt;
end
assign D_ctrl_mem32 = D_op_ldw|D_op_ldwio|D_op_stw|D_op_stwio;
assign R_ctrl_mem32_nxt = D_ctrl_mem32;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem32 <= 0;
else if (R_en)
R_ctrl_mem32 <= R_ctrl_mem32_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_jmpi;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_intr_inst = 1'b0;
assign R_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_intr_inst <= 0;
else if (R_en)
R_ctrl_intr_inst <= R_ctrl_intr_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_ret|
D_op_jmp|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_bgeu|
D_op_beq|
D_op_bne|
D_op_br;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
assign D_ctrl_alu_force_and = 1'b0;
assign R_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_and <= 0;
else if (R_en)
R_ctrl_alu_force_and <= R_ctrl_alu_force_and_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_custom)? 56'h20637573746f6d :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_custom)? 56'h20637573746f6d :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
assign R_vinst = R_valid ? D_inst : {9{8'h2d}};
assign E_vinst = E_valid ? D_inst : {9{8'h2d}};
assign W_vinst = W_valid ? D_inst : {9{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
|
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ram_controller_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C8";
localparam MEM_IF_DQS_WIDTH = 2;
localparam MEM_IF_DWIDTH = 16;
localparam MEM_IF_DM_WIDTH = 2;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 2;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 64;
localparam MEM_IF_CLK_PS = 7519;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 594;
localparam MEM_IF_MR_1 = 1092;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Cyclone IV E";
localparam FAMILYGROUP_ID = 2;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 2048;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 0;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 0;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 12;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 26610;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
ram_controller_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_2_V
`define SKY130_FD_SC_MS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:16 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_stub.v
// Design : zynq_design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module zynq_design_1_xbar_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
endmodule
|
`timescale 1ns/10ps
(* whitebox *)
(* FASM_PARAMS="INV.ESEL=ESEL;INV.OSEL=OSEL;INV.FIXHOLD=FIXHOLD;INV.WPD=WPD;INV.DS=DS" *)
module BIDIR_CELL(
I_PAD_$inp, I_DAT, I_EN,
O_PAD_$out, O_DAT, O_EN
);
(* iopad_external_pin *)
input wire I_PAD_$inp;
input wire I_EN;
input wire O_DAT;
input wire O_EN;
(* DELAY_CONST_I_PAD_$inp="{iopath_IP_IZ}" *)
(* DELAY_CONST_I_EN="1e-10" *) // No timing for IE/INEN -> IZ in LIB/SDF.
output wire I_DAT;
(* DELAY_CONST_O_DAT="{iopath_OQI_IP}" *)
(* DELAY_CONST_O_EN="{iopath_IE_IP}" *)
(* iopad_external_pin *)
output wire O_PAD_$out;
specify
(O_DAT => O_PAD_$out) = (0,0);
(O_EN => O_PAD_$out) = (0,0);
(I_PAD_$inp => I_DAT) = (0,0);
(I_EN => I_DAT) = (0,0);
endspecify
// Parameters
parameter [0:0] ESEL = 0;
parameter [0:0] OSEL = 0;
parameter [0:0] FIXHOLD = 0;
parameter [0:0] WPD = 0;
parameter [0:0] DS = 0;
// Behavioral model
assign I_DAT = (I_EN == 1'b1) ? I_PAD_$inp : 1'b0;
assign O_PAD_$out = (O_EN == 1'b1) ? O_DAT : 1'b0;
endmodule
|
`include "pcm.v"
module BusPCM
#(
// bus-related
parameter bus_width=32,
parameter bus_max_devices=16,
parameter bus_buffer_size=1,
parameter device_id=1,
parameter data_resolution=8
)
(
// bus side
input clk,
inout [bus_width-1:0] bus_data,
inout [bus_max_devices-1:0] bus_receiver,
inout [bus_max_devices-1:0] bus_write_request,
inout [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice
// output
output pcm_out
);
wire [bus_width-1:0] client_data_in,
wire [bus_max_devices-1:0] client_source_addr,
wire client_read_next,
wire client_input_buffer_empty,
wire client_input_buffer_full,
BusReader
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) reader
(
clk,
bus_data,
bus_receiver,
bus_buffer_full,
bus_voice,
client_data_in,
client_source_addr,
client_read_next,
client_input_buffer_empty,
client_input_buffer_full
);
reg [data_resolution-1:0] pcm_in;
PCM
#(
.data_resolution(data_resolution),
)
{
pcm_in,
clk,
pcm_out
};
always @(posedge clk) begin
if {~client_input_buffer_empty) begin
pcm_in<=bus_data;
bus_next<=1;
end
else begin
bus_next<=0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:29:45 11/23/2014
// Design Name:
// Module Name: ssg_display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ssg_display(
//input [3:0] sw,
input clk,
input greset,
output [7:0] sseg_cathode,
output [3:0] sseg_anode
);
wire dp;
//assign sseg_anode = 4'b1110;
assign dp = 1;
wire clkEnable_100Hz,clkEnable_25Hz;
clkEnable_gen #(.DES_CLOCK(250000)) Clock_100Hz (
.enable(clkEnable_100Hz),
.clock(clk),
.greset(greset));
clkEnable_gen #(.DES_CLOCK(6000000)) Clock_25Hz (
.enable(clkEnable_25Hz),
.clock(clk),
.greset(greset));
wire [15:0] BCDCount;
vCounter4DigitBCD BCDCounter_4Dig(.enable(clkEnable_25Hz),
.clk(clk),
.count(BCDCount),
.grst(greset)
);
reg [1:0] cnt;
initial cnt = 2'b0;
always @(posedge clk)
begin
if (clkEnable_100Hz)
cnt = cnt + 1;
else
cnt = cnt;
end
wire [3:0] hex_in;
assign sseg_anode = (cnt == 2'b00)? 4'b0111 : ( cnt==2'b01 )? 4'b1011:( cnt==2'b10 )?4'b1101 : 4'b1110;
assign hex_in = ( cnt == 0 )? BCDCount[15:12] : ( cnt == 1 )? BCDCount[11:8] : ( cnt == 2 )? BCDCount[7:4] : BCDCount[3:0];
hex_to_sseg hexToSSEG(
.hex(hex_in),
.dp(dp),
.sseg(sseg_cathode)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_nstep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_nstep
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_nstep(/*AUTOARG*/
// Outputs
cmp_nstep_sel, jbus_nstep_sel, dram_nstep_sel,
// Inputs
io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_dram,
jtag_clock_dr_jbus, jtag_clsp_force_cken_jbus,
jtag_clsp_force_cken_dram, jtag_clsp_force_cken_cmp,
jtag_nstep_count, jtag_nstep_domain, jtag_nstep_vld, cmp_gclk_bypass,
dram_gclk_bypass, jbus_gclk_bypass, capture_l, start_clk_early_jl,
testmode_l, shadreg_div_cmult, shadreg_div_jmult, shadreg_div_dmult
);
input io_pwron_rst_l;
input jtag_clock_dr_cmp;
input jtag_clock_dr_dram;
input jtag_clock_dr_jbus;
input jtag_clsp_force_cken_jbus;
input jtag_clsp_force_cken_dram;
input jtag_clsp_force_cken_cmp;
input [3:0] jtag_nstep_count;
input [2:0] jtag_nstep_domain;
input jtag_nstep_vld;
input cmp_gclk_bypass;
input dram_gclk_bypass;
input jbus_gclk_bypass;
input capture_l;
input start_clk_early_jl;
input testmode_l;
input [13:0] shadreg_div_cmult;
input [9:0] shadreg_div_jmult;
input [9:0] shadreg_div_dmult;
output cmp_nstep_sel;
output jbus_nstep_sel;
output dram_nstep_sel;
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (cmp_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_cmp),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[0]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(cmp_nstep_sel),
.shadreg_div_mult(shadreg_div_cmult[13:0]),
.force_cken(jtag_clsp_force_cken_cmp),
);
*/
ctu_clsp_clkgn_nstep_cnt u_cmp(/*AUTOINST*/
// Outputs
.nstep_sel(cmp_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk (cmp_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_cmp), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[0]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult(shadreg_div_cmult[13:0]), // Templated
.force_cken(jtag_clsp_force_cken_cmp)); // Templated
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (jbus_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_jbus),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[2]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(jbus_nstep_sel),
.shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}),
.force_cken(jtag_clsp_force_cken_jbus),
);
*/
ctu_clsp_clkgn_nstep_cnt u_jbus(/*AUTOINST*/
// Outputs
.nstep_sel(jbus_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk (jbus_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_jbus), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[2]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}), // Templated
.force_cken(jtag_clsp_force_cken_jbus)); // Templated
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (dram_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_dram),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[1]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(dram_nstep_sel),
.shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}),
.force_cken(jtag_clsp_force_cken_dram),
);
*/
ctu_clsp_clkgn_nstep_cnt u_dram(/*AUTOINST*/
// Outputs
.nstep_sel(dram_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk(dram_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_dram), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[1]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}), // Templated
.force_cken(jtag_clsp_force_cken_dram)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_2_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S4_2_altera (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [3:0] data;
input [11:0] rdaddress;
input [11:0] wraddress;
input wren;
output [3:0] q;
parameter init_file = "";
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({4{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = init_file,
//altsyncram_component.init_file = "lr_latest_00.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 4,
altsyncram_component.width_b = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "lr_latest_00.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "lr_latest_00.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_b 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_2_altera_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Generator : SpinalHDL v1.1.5 git head : 0310b2489a097f2b9de5535e02192d9ddd2764ae
// Date : 12/11/2018, 20:09:50
// Component : Fifo
module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset);
wire [7:0] _zz_1;
wire [7:0] _zz_2;
wire _zz_3;
reg [5:0] head;
reg [5:0] tail;
reg full;
reg empty;
wire [5:0] headNext;
wire [5:0] tailNext;
wire writing;
wire reading;
wire readingWriting;
reg [7:0] mem [0:63];
assign _zz_2 = io_dataIn;
assign _zz_3 = ((! full) && io_write);
always @ (posedge clk) begin
if(_zz_3) begin
mem[head] <= _zz_2;
end
end
assign _zz_1 = mem[tail];
assign headNext = (head + (6'b000001));
assign tailNext = (tail + (6'b000001));
assign writing = (io_write && (! io_read));
assign reading = ((! io_write) && io_read);
assign readingWriting = (io_write && io_read);
assign io_dataOut = _zz_1;
assign io_empty = empty;
assign io_full = full;
always @ (posedge clk or posedge reset) begin
if (reset) begin
head <= (6'b000000);
tail <= (6'b000000);
full <= 1'b0;
empty <= 1'b1;
end else begin
if(writing)begin
if((! full))begin
head <= headNext;
full <= (headNext == tail);
empty <= 1'b0;
end
end
if(reading)begin
if((! empty))begin
tail <= tailNext;
empty <= (tailNext == head);
full <= 1'b0;
end
end
if(readingWriting)begin
if(full)begin
tail <= tailNext;
full <= 1'b0;
end
if(empty)begin
head <= headNext;
empty <= 1'b0;
end
if(((! full) && (! empty)))begin
tail <= tailNext;
head <= headNext;
end
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Register Block
// File : der_top.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the top level register block for Imagine-MI
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_top
(
input de_clk, // drawing engine clock input
input de_rstn, // de reset input
input hb_clk, // host bus clock input
input hb_rstn, // host reset input
input [31:0] hb_din, // host bus data
input [8:2] dlp_adr, // host bus address through preproc
input [8:2] hb_adr_r, // host bus address bypasses preproc
input hb_wstrb, // host bus write strobes
input [3:0] hb_ben, // host bus byte enables.
input hb_csn, // host bus chip select.
input [15:0] lpat_state, // line pattern state register
input [53:0] dl_rdback, // dlp read back data.
input [4:0] flow, // Flow register.
input busy_dlp, // Busy feedback from the DLP.
input de_clint_tog, // Clip Interrupt Toggle Signal.
input de_ddint_tog, // Drawing Done Int Toggle Signal.
input sup_done, // 3D setup is done.
input abort_cmd, // 3D setup abort.
input dex_busy, // Drawing engine 2D EX busy.
input pc_last, // Last push to the Pixel Cache.
input cmd_done_3d, // Last Pixel generated, for current cmd.
input pal_busy, //
output goline, // Start 2D Line.
output goblt, // Start 2D BLT.
output pal_load, // Load Texture Palette.
output tc_inv_cmd, // Invalidate Texture.
output go_sup, // Start the setup engine.
output load_actv_3d, // Start 3D execution.
output cmdcpyclr, // Command copy clear.
output load_actvn,
output tc_xyw_sel, // Sel TC or XYW for cache writing
output [11:0] buf_ctrl_2, // buffer control register output.
output [1:0] ps_1, // pixel size bits.
output [27:0] sorg_2, // source origin register output
output [27:0] dorg_2, // destination origin register output
output [31:0] de_sorg_2, // source origin register output
output [31:0] de_dorg_2, // destination origin register output
output [11:0] sptch_2, // source pitch register output
output [11:0] dptch_2, // destination pitch register output
output [3:0] opc_1, // opcode register output
output [3:0] opc_15, // opcode register output
output [3:0] rop_1, // raster opcode register output
output [3:0] rop_2, // raster opcode register output
output [4:0] style_2, // drawing style register output
output solid_1, // Solid level one signal.
output prst_1, // drawing pattern style register
output nlst_2, // drawing pattern style register
output or_apat_1, // Or of apat_1
output [1:0] apat_2, // drawing area pattern mode.
output [2:0] hdf_1, // Host data format.
output [2:0] clp_2, // drawing clip control register
output [31:0] fore_2, // foreground color register output
output [31:0] back_2, // background color register output
output [31:0] lpat_1, // Line Pattern Level 1
output [15:0] pctrl_1,
output [31:0] clptl_1,
output [31:0] clpbr_1,
output [3:0] mask_2, // plane mask register output
output [23:0] de_key_2, // Key data out
output [159:0] xydat_1, // level 1 XY data for 2D
output [15:0] alpha_2, // Alpha register
output [17:0] acntrl_2, // Alpha control register
output [31:0] hb_dout, // host bus read back path
output busy_hb, // busy to the host.
output stpl_1, // packed stipple bit level one
output de_ca_rdy, // cache ready bit to the exec unit
output ps16s_2, // 8bpp host data
output ps565s_2, // 8bpp host data
output cmd_trig_comb,
output [1:0] bc_lvl_2,
output interrupt,
output [6:0] mem_offset, // Define an offset for operations
output [3:0] sorg_upper, // Define an offset for text
output load_15,
output busy_3d
);
`ifdef CORE_3D parameter en_3d = 1'b1;
`else parameter en_3d =1'b0;
`endif
wire [1:0] intm;
wire [1:0] intp;
wire [13:0] buf_ctrl_1;
wire [31:0] sorg_1;
wire [31:0] dorg_1;
wire [11:0] sptch_1;
wire [11:0] dptch_1;
wire [4:0] style_1;
wire nlst_1;
wire [1:0] apat_1;
wire [2:0] clp_1;
wire [31:0] fore_1;
wire [31:0] back_1;
wire [3:0] mask_1;
wire [23:0] de_key_1;
wire [31:0] xy0_1;
wire [31:0] xy1_1;
wire [31:0] xy2_1;
wire [31:0] xy3_1;
wire [31:0] xy4_1;
wire [15:0] alpha_1;
wire [17:0] acntrl_1;
wire [31:0] mf_sorg_2; /* multi function sorg. */
wire [31:0] mf_dorg_2; /* multi function dorg. */
wire cr_pulse;
wire hb_ca_rdy;
wire bc_co;
wire [1:0] bc_lvl_1;
wire prst;
wire cmdrdy;
wire cmdack;
wire [3:0] opc_2;
der_reg_1 u_der_reg_1
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_csn (hb_csn),
.cmdack (cmdack),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog),
.en_3d (en_3d),
.intm (intm),
.intp (intp),
.buf_ctrl_1 ({cr_pulse,buf_ctrl_1}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.opc_1 (opc_1),
.rop_1 (rop_1),
.style_1 (style_1),
.patrn_1 ({prst,nlst_1,apat_1}),
.hdf_1 (hdf_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.lpat_1 (lpat_1),
.pctrl_1 (pctrl_1),
.clptl_1 (clptl_1),
.clpbr_1 (clpbr_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.cmdrdy (cmdrdy),
.busy_hb (busy_hb),
.stpl_1 (stpl_1),
.cmd_trig_comb (cmd_trig_comb),
.bc_lvl_1 (bc_lvl_1),
.interrupt (interrupt),
.mem_offset_1 (mem_offset),
.sorg_upper_1 (sorg_upper)
);
`ifdef CORE_3D
wire [13:0] buf_ctrl_15;
wire [31:0] sorg_15;
wire [31:0] dorg_15;
wire [31:0] mf_sorg_15;
wire [31:0] mf_dorg_15;
wire [11:0] sptch_15;
wire [11:0] dptch_15;
wire [4:0] style_15;
wire nlst_15;
wire [1:0] apat_15;
wire [2:0] clp_15;
wire [31:0] fore_15;
wire [31:0] back_15;
wire [3:0] mask_15;
wire [23:0] de_key_15;
wire [31:0] xy0_15;
wire [31:0] xy1_15;
wire [31:0] xy2_15;
wire [31:0] xy3_15;
wire [31:0] xy4_15;
wire [15:0] alpha_15;
wire [17:0] acntrl_15;
wire [1:0] bc_lvl_15;
wire [3:0] rop_15;
assign solid_1 = style_15[0];
assign tc_xyw_sel = buf_ctrl_15[11];
assign ps_1 = buf_ctrl_15[8:7];
assign xydat_1 = {xy0_15,xy1_15,xy2_15,xy3_15,xy4_15};
der_reg_15 u_der_reg_15
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_15 (load_15),
.buf_ctrl_1 ({buf_ctrl_1[13:12], buf_ctrl_1[10:0]}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.rop_1 (rop_1),
.style_1 (style_1),
.nlst_1 (nlst_1),
.apat_1 (apat_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.bc_lvl_1 (bc_lvl_1),
.opc_1 (opc_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.buf_ctrl_15 ({bc_co,buf_ctrl_15}),
.sorg_15 (sorg_15),
.dorg_15 (dorg_15),
.sptch_15 (sptch_15),
.dptch_15 (dptch_15),
.rop_15 (rop_15),
.style_15 (style_15),
.nlst_15 (nlst_15),
.apat_15 (apat_15),
.clp_15 (clp_15),
.fore_15 (fore_15),
.back_15 (back_15),
.mask_15 (mask_15),
.de_key_15 (de_key_15),
.alpha_15 (alpha_15),
.acntrl_15 (acntrl_15),
.bc_lvl_15 (bc_lvl_15),
.opc_15 (opc_15),
.xy0_15 (xy0_15),
.xy1_15 (xy1_15),
.xy2_15 (xy2_15),
.xy3_15 (xy3_15),
.xy4_15 (xy4_15)
);
der_reg_2 u_der_reg_2
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_actvn (load_actvn),
.cmdcpyclr (cmdcpyclr),
.buf_ctrl_1 ({1'b0, buf_ctrl_15[12], buf_ctrl_15[10:0]}),
.sorg_1 (sorg_15),
.dorg_1 (dorg_15),
.sptch_1 (sptch_15),
.dptch_1 (dptch_15),
.rop_1 (rop_15),
.opc_1 (opc_15),
.style_1 (style_15),
.nlst_1 (nlst_15),
.apat_1 (apat_15),
.clp_1 (clp_15),
.fore_1 (fore_15),
.back_1 (back_15),
.mask_1 (mask_15),
.de_key_1 (de_key_15),
.alpha_1 (alpha_15),
.acntrl_1 (acntrl_15),
.bc_lvl_1 (bc_lvl_15),
`else
assign solid_1 = style_1[0];
assign tc_xyw_sel = buf_ctrl_1[11];
assign ps_1 = buf_ctrl_1[8:7];
assign xydat_1 = {xy0_1,xy1_1,xy2_1,xy3_1,xy4_1};
der_reg_2 u_der_reg_2
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_actvn (load_actvn),
.cmdcpyclr (cmdcpyclr),
.buf_ctrl_1 ({buf_ctrl_1[13:12], buf_ctrl_1[10:0]}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.rop_1 (rop_1),
.opc_1 (opc_1),
.style_1 (style_1),
.nlst_1 (nlst_1),
.apat_1 (apat_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.bc_lvl_1 (bc_lvl_1),
`endif
.buf_ctrl_2 ({bc_co,buf_ctrl_2}),
.sorg_2 (mf_sorg_2),
.dorg_2 (mf_dorg_2),
.sptch_2 (sptch_2),
.dptch_2 (dptch_2),
.rop_2 (rop_2),
.style_2 (style_2),
.nlst_2 (nlst_2),
.apat_2 (apat_2),
.clp_2 (clp_2),
.fore_2 (fore_2),
.back_2 (back_2),
.mask_2 (mask_2),
.de_key_2 (de_key_2),
.alpha_2 (alpha_2),
.acntrl_2 (acntrl_2),
.bc_lvl_2 (bc_lvl_2),
.opc_2 (opc_2)
);
der_rdmux D_RDMUX
(
.hb_adr (hb_adr_r),
.intm (intm),
.intp (intp),
.flow (flow),
.busy (busy_dlp),
.buf_ctrl_1 ({hb_ca_rdy,buf_ctrl_1}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.opc_1 (opc_1),
.rop_1 (rop_1),
.style_1 (style_1),
.patrn_1 ({prst,nlst_1,apat_1}),
.hdf_1 (hdf_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.lpat_1 (lpat_1),
.pctrl_1 (pctrl_1),
.clptl_1 (clptl_1),
.clpbr_1 (clpbr_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.lpat_state (lpat_state),
.dl_rdback (dl_rdback),
.bc_lvl_1 (bc_lvl_1),
.mem_offset_1 (mem_offset),
.sorg_upper_1 (sorg_upper),
.hb_dout (hb_dout)
);
der_misc u_der_misc
(
.de_clk (de_clk),
.hb_clk (hb_clk),
.prst (prst),
.cr_pulse (cr_pulse),
.ps_sel_2 (buf_ctrl_2[10:9]),
.bc_co (bc_co),
.mf_sorg_2 (mf_sorg_2),
.mf_dorg_2 (mf_dorg_2),
.apat_1 (apat_1),
.sd_selector (buf_ctrl_2[4]),
.prst_1 (prst_1),
.hb_ca_rdy (hb_ca_rdy),
.de_ca_rdy (de_ca_rdy),
.ps16s_2 (ps16s_2),
.ps565s_2 (ps565s_2),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.sorg_2 (sorg_2),
.dorg_2 (dorg_2),
.or_apat_1 (or_apat_1)
);
// Command Dispatcher.
der_smdisp u_der_smdisp
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.en_3d (en_3d),
.cmdrdy (cmdrdy),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
.dex_busy (dex_busy),
.opc_1 (opc_1),
.opc_15 (opc_15),
.opc_2 (opc_2),
.pc_last (pc_last),
.cmd_done_3d (cmd_done_3d),
.pal_busy (pal_busy),
// Outputs
.go_sup (go_sup),
.load_15 (load_15), // Transfer parameters from L1 to L1.5
.load_actvn (load_actvn), // Transfer parameters from L1.5 to L2
.load_actv_3d (load_actv_3d),// Transfer parameters from L1.5 to L2, in 3D engine.
.goline (goline),
.goblt (goblt),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.cmdack (cmdack),
.cmdcpyclr (cmdcpyclr),
.busy_3d (busy_3d)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_2_V
`define SKY130_FD_SC_LS__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_2_V
|
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//************************************************************//
// - a lot work in progress, many thing are useless
// TODO: clean this up and make it more general
// TODO: add comments
//************************************************************//
module spoof(
instruction_opcode,
ex_freeze,
clk_in,
data_out,
reset
);
input [31:0] instruction_opcode;
input ex_freeze;
input clk_in;
input reset;
output data_out;
localparam STATE_Initial = 3'd0,
STATE_1 = 3'd1,
STATE_2 = 3'd2,
STATE_3 = 3'd3,
STATE_4 = 3'd4,
STATE_5_Placeholder = 3'd5,
STATE_6_Placeholder = 3'd6,
STATE_7_Placeholder = 3'd7;
//OPCODES for sequence recognition
localparam OPCODE_A = 32'h15000000,
OPCODE_B = 32'h15000000,
OPCODE_C = 32'h15000000,
OPCODE_D = 32'h15000000;
wire [31:0] instruction_opcode;
wire ex_freeze;
wire clk_in;
wire reset;
reg data_out;
//state registers
reg[2:0] CurrentState;
reg[2:0] NextState;
//synchronous state transition
always@ (posedge clk_in)
begin: STATE_TRANS
if(reset) CurrentState <= STATE_Initial;
else CurrentState <= NextState;
end
//conditional state transition
always@ (*)
begin
if(ex_freeze) begin
NextState <= CurrentState;
end
else begin
case(CurrentState)
STATE_Initial: begin
if(instruction_opcode == OPCODE_A) NextState <= STATE_1;
else NextState <= STATE_Initial;
end
STATE_1: begin
if(instruction_opcode == OPCODE_B) NextState <= STATE_2;
else NextState <= STATE_Initial;
end
STATE_2: begin
if(instruction_opcode == OPCODE_C) NextState <= STATE_3;
else NextState <= STATE_Initial;
end
STATE_3: begin
if(instruction_opcode == OPCODE_D) NextState <= STATE_4;
else NextState <= STATE_Initial;
end
STATE_4: begin
NextState <= STATE_Initial;
end
STATE_5_Placeholder: begin
end
STATE_6_Placeholder: begin
end
STATE_7_Placeholder: begin
end
endcase
end
end
//output
always@ (*)
begin
data_out = 1'b0;
if(CurrentState == STATE_4) data_out = 1'b1;
end
endmodule
|
`timescale 1ns / 1ps
module spi #(
parameter clk_divisor=8 // SCLK shall be this many
// times slower than CLK;
// can only be an even number.
)
(
input clk, // Processor clock
input rst, // Processor reset
input [7:0] data_in, // Data to be transferred
output reg[7:0] data_out, // Received data
input ready_send, // Initialize transfer
output busy, // Transaction is in progress
input miso, // Master in slave out
output mosi, // Master out slave in
output sclk, // SPI clock
output ss // Slave select
);
reg[ 3:0] sctr;
reg[ 7:0] data_in_reg;
reg[31:0] ctr;
assign ss = sctr == 0;
assign sclk = !sctr[0] || ss;
assign mosi = data_in_reg[sctr >> 1];
assign busy = !ss;
always @(posedge clk) begin
if (rst) begin
sctr <= 0;
ctr <= 0;
data_out <= 0;
end else if (ready_send && !sctr) begin
data_in_reg <= data_in;
sctr <= 15;
ctr <= 0;
end else if (sctr && ctr + 1 == clk_divisor >> 1) begin
ctr <= 0;
if (sctr[0])
data_out[sctr >> 1] <= miso;
sctr <= sctr - 1;
end else if (sctr) begin
ctr <= ctr + 1;
end
end
endmodule
|
//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name: red_pitaya_iq_fgen_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// This module outputs 4 signed signals:
// sin(f*t), cos(f*t),sin(f*t+phi), cos(f*t+phi)
// The maximally positive signal is 2**(LUTBITS-1)-1
// The maximally negative signal is -(2**(LUTBITS-1)-1)
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_fgen_block #(
parameter LUTSZ = 11,
parameter LUTBITS = 17,
parameter PHASEBITS = 32
)
(
input clk_i,
input rstn_i,
input on,
input sin_at_2f,
input cos_at_2f,
input sin_shifted_at_2f,
input cos_shifted_at_2f,
input [PHASEBITS-1:0] start_phase,
input [PHASEBITS-1:0] shift_phase,
output [LUTBITS-1:0] sin_o ,
output [LUTBITS-1:0] cos_o ,
output [LUTBITS-1:0] sin_shifted_o ,
output [LUTBITS-1:0] cos_shifted_o
);
reg [LUTBITS-1:0] sin;
reg [LUTBITS-1:0] cos;
reg [LUTBITS-1:0] sin_shifted;
reg [LUTBITS-1:0] cos_shifted;
assign sin_o = sin;
assign sin_shifted_o = sin_shifted;
assign cos_o = cos;
assign cos_shifted_o = cos_shifted;
localparam QSHIFT = {{PHASEBITS-1{1'b0}},1'b1} << (PHASEBITS-2);
//lut data block
reg [LUTBITS-1-1:0] lutrom [0:(1<<LUTSZ)-1];
reg [PHASEBITS-1:0] phase;
wire [PHASEBITS-1:0] wwphase1;
wire [PHASEBITS-1:0] wwphase2;
wire [PHASEBITS-1:0] wwphase3;
wire [PHASEBITS-1:0] wwphase4;
wire [LUTBITS-1:0] wphase1;
wire [LUTBITS-1:0] wphase2;
wire [LUTBITS-1:0] wphase3;
wire [LUTBITS-1:0] wphase4;
wire invertphase1;
wire invertphase2;
wire invertphase3;
wire invertphase4;
wire invertsignal1;
wire invertsignal2;
wire invertsignal3;
wire invertsignal4;
reg invertsignal1_reg;
reg invertsignal2_reg;
reg invertsignal3_reg;
reg invertsignal4_reg;
reg invertsignal1_reg_reg;
reg invertsignal2_reg_reg;
reg invertsignal3_reg_reg;
reg invertsignal4_reg_reg;
reg [LUTBITS-1:0] sin_reg;
reg [LUTBITS-1:0] cos_reg;
reg [LUTBITS-1:0] sin_shifted_reg;
reg [LUTBITS-1:0] cos_shifted_reg;
reg [LUTBITS-1:0] phase1;
reg [LUTBITS-1:0] phase2;
reg [LUTBITS-1:0] phase3;
reg [LUTBITS-1:0] phase4;
// in clock cycle n-1, phase is incremented (see far below in the else-block
// in clock cycle n,
// - we assign wwphase1-4, the phase of the 4 subgenerators (possibly doubled phase counter for generation at 2f)
// - we assign wphase1-4,
// - we assign invertphase1-4, the flag telling if we are in the rising or falling quadrant of the sine
// - we assign invertsignal1-4, the flag telling if we in the positive or negative sign of the sine
assign wwphase1 = sin_at_2f ? {phase[PHASEBITS-1:0],1'b0} : phase; // wwphase1 ready in cycle n
assign wwphase2 = cos_at_2f ? {phase[PHASEBITS-1:0],1'b0} + QSHIFT : phase + QSHIFT;
assign wwphase3 = sin_shifted_at_2f ? {phase[PHASEBITS-1:0],1'b0} + start_phase : phase + start_phase;
assign wwphase4 = cos_shifted_at_2f ? {phase[PHASEBITS-1:0],1'b0} + start_phase + QSHIFT : phase + start_phase + QSHIFT;
assign wphase1 = wwphase1[PHASEBITS-2-1:PHASEBITS-2-LUTSZ]; //wwphase1 ready in cycle n
assign wphase2 = wwphase2[PHASEBITS-2-1:PHASEBITS-2-LUTSZ];
assign wphase3 = wwphase3[PHASEBITS-2-1:PHASEBITS-2-LUTSZ];
assign wphase4 = wwphase4[PHASEBITS-2-1:PHASEBITS-2-LUTSZ];
assign invertphase1 = wwphase1[PHASEBITS-1-1]; //invertphase1 ready in cycle n
assign invertphase2 = wwphase2[PHASEBITS-1-1];
assign invertphase3 = wwphase3[PHASEBITS-1-1];
assign invertphase4 = wwphase4[PHASEBITS-1-1];
assign invertsignal1 = wwphase1[PHASEBITS-1]; //invertsignal1 ready in cycle n
assign invertsignal2 = wwphase2[PHASEBITS-1];
assign invertsignal3 = wwphase3[PHASEBITS-1];
assign invertsignal4 = wwphase4[PHASEBITS-1];
//main loop
always @(posedge clk_i) begin
phase1 <= invertphase1 ? (~wphase1) : wphase1; //phase1 ready in cycle n+1
phase2 <= invertphase2 ? (~wphase2) : wphase2;
phase3 <= invertphase3 ? (~wphase3) : wphase3;
phase4 <= invertphase4 ? (~wphase4) : wphase4;
invertsignal1_reg <= invertsignal1; //invertsignal1_reg ready in cycle n+1
invertsignal2_reg <= invertsignal2;
invertsignal3_reg <= invertsignal3;
invertsignal4_reg <= invertsignal4;
invertsignal1_reg_reg <= invertsignal1_reg; //invertsignal1_reg_reg ready in cycle n+2
invertsignal2_reg_reg <= invertsignal2_reg;
invertsignal3_reg_reg <= invertsignal3_reg;
invertsignal4_reg_reg <= invertsignal4_reg;
sin_reg <= lutrom[phase1]; //sin_reg ready in cycle n+2
cos_reg <= lutrom[phase2];
sin_shifted_reg <= lutrom[phase3];
cos_shifted_reg <= lutrom[phase4];
if (on==1'b0) begin
phase <= {PHASEBITS{1'b0}};
sin <= {LUTBITS{1'b0}};
cos <= {LUTBITS{1'b0}};
sin_shifted <= {LUTBITS{1'b0}};
cos_shifted <= {LUTBITS{1'b0}};
end
else begin
phase <= phase + shift_phase; // new phase is ready in (arbitrary) cycle n
sin <= invertsignal1_reg_reg ? ((~sin_reg)+'b1) : sin_reg; //sin ready in cycle n+3 - based purely on signals that are ready in cycle n+2 -> timing correct, latency 3 cycles
cos <= invertsignal2_reg_reg ? ((~cos_reg)+'b1) : cos_reg;
sin_shifted <= invertsignal3_reg_reg ? ((~sin_shifted_reg)+'b1) : sin_shifted_reg;
cos_shifted <= invertsignal4_reg_reg ? ((~cos_shifted_reg)+'b1) : cos_shifted_reg;
end
end
//LUT ROM
//created by this (unpolished) python code:
/*
LUTSZ = 11 #number of LUT entries
LUTBITS = 17 #LUT word size
def from_pyint(v,bitlength=14):
v = int(v)
if v < 0:
v = v + 2**bitlength
v= (v & (2**bitlength-1))
return int(v)
data = np.zeros(2**LUTSZ,dtype=np.long)
for i in range(len(data)):
data[i] = np.long(np.round((2**(LUTBITS-1)-1)*np.sin(((float(i)+0.5)/len(data))*0.5*np.pi)))
data = [from_pyint(v,bitlength=LUTBITS) for v in data]
plot(data)
print "reg [LUTBITS-1-1:0] lutrom [0:(1<<LUTSZ)-1];"
print ""
print "initial begin"
for i in range(len(data)):
string = " lutrom["+str(i)+"] = "+str(LUTBITS-1)+"'d"+str(data[i])+";"
print string
print "end"
*/
initial begin
lutrom[0] = 16'd25;
lutrom[1] = 16'd75;
lutrom[2] = 16'd126;
lutrom[3] = 16'd176;
lutrom[4] = 16'd226;
lutrom[5] = 16'd276;
lutrom[6] = 16'd327;
lutrom[7] = 16'd377;
lutrom[8] = 16'd427;
lutrom[9] = 16'd478;
lutrom[10] = 16'd528;
lutrom[11] = 16'd578;
lutrom[12] = 16'd628;
lutrom[13] = 16'd679;
lutrom[14] = 16'd729;
lutrom[15] = 16'd779;
lutrom[16] = 16'd829;
lutrom[17] = 16'd880;
lutrom[18] = 16'd930;
lutrom[19] = 16'd980;
lutrom[20] = 16'd1030;
lutrom[21] = 16'd1081;
lutrom[22] = 16'd1131;
lutrom[23] = 16'd1181;
lutrom[24] = 16'd1231;
lutrom[25] = 16'd1282;
lutrom[26] = 16'd1332;
lutrom[27] = 16'd1382;
lutrom[28] = 16'd1432;
lutrom[29] = 16'd1483;
lutrom[30] = 16'd1533;
lutrom[31] = 16'd1583;
lutrom[32] = 16'd1633;
lutrom[33] = 16'd1684;
lutrom[34] = 16'd1734;
lutrom[35] = 16'd1784;
lutrom[36] = 16'd1834;
lutrom[37] = 16'd1885;
lutrom[38] = 16'd1935;
lutrom[39] = 16'd1985;
lutrom[40] = 16'd2035;
lutrom[41] = 16'd2086;
lutrom[42] = 16'd2136;
lutrom[43] = 16'd2186;
lutrom[44] = 16'd2236;
lutrom[45] = 16'd2287;
lutrom[46] = 16'd2337;
lutrom[47] = 16'd2387;
lutrom[48] = 16'd2437;
lutrom[49] = 16'd2488;
lutrom[50] = 16'd2538;
lutrom[51] = 16'd2588;
lutrom[52] = 16'd2638;
lutrom[53] = 16'd2688;
lutrom[54] = 16'd2739;
lutrom[55] = 16'd2789;
lutrom[56] = 16'd2839;
lutrom[57] = 16'd2889;
lutrom[58] = 16'd2939;
lutrom[59] = 16'd2990;
lutrom[60] = 16'd3040;
lutrom[61] = 16'd3090;
lutrom[62] = 16'd3140;
lutrom[63] = 16'd3191;
lutrom[64] = 16'd3241;
lutrom[65] = 16'd3291;
lutrom[66] = 16'd3341;
lutrom[67] = 16'd3391;
lutrom[68] = 16'd3442;
lutrom[69] = 16'd3492;
lutrom[70] = 16'd3542;
lutrom[71] = 16'd3592;
lutrom[72] = 16'd3642;
lutrom[73] = 16'd3693;
lutrom[74] = 16'd3743;
lutrom[75] = 16'd3793;
lutrom[76] = 16'd3843;
lutrom[77] = 16'd3893;
lutrom[78] = 16'd3943;
lutrom[79] = 16'd3994;
lutrom[80] = 16'd4044;
lutrom[81] = 16'd4094;
lutrom[82] = 16'd4144;
lutrom[83] = 16'd4194;
lutrom[84] = 16'd4244;
lutrom[85] = 16'd4295;
lutrom[86] = 16'd4345;
lutrom[87] = 16'd4395;
lutrom[88] = 16'd4445;
lutrom[89] = 16'd4495;
lutrom[90] = 16'd4545;
lutrom[91] = 16'd4595;
lutrom[92] = 16'd4646;
lutrom[93] = 16'd4696;
lutrom[94] = 16'd4746;
lutrom[95] = 16'd4796;
lutrom[96] = 16'd4846;
lutrom[97] = 16'd4896;
lutrom[98] = 16'd4946;
lutrom[99] = 16'd4996;
lutrom[100] = 16'd5047;
lutrom[101] = 16'd5097;
lutrom[102] = 16'd5147;
lutrom[103] = 16'd5197;
lutrom[104] = 16'd5247;
lutrom[105] = 16'd5297;
lutrom[106] = 16'd5347;
lutrom[107] = 16'd5397;
lutrom[108] = 16'd5447;
lutrom[109] = 16'd5498;
lutrom[110] = 16'd5548;
lutrom[111] = 16'd5598;
lutrom[112] = 16'd5648;
lutrom[113] = 16'd5698;
lutrom[114] = 16'd5748;
lutrom[115] = 16'd5798;
lutrom[116] = 16'd5848;
lutrom[117] = 16'd5898;
lutrom[118] = 16'd5948;
lutrom[119] = 16'd5998;
lutrom[120] = 16'd6048;
lutrom[121] = 16'd6098;
lutrom[122] = 16'd6148;
lutrom[123] = 16'd6198;
lutrom[124] = 16'd6248;
lutrom[125] = 16'd6298;
lutrom[126] = 16'd6349;
lutrom[127] = 16'd6399;
lutrom[128] = 16'd6449;
lutrom[129] = 16'd6499;
lutrom[130] = 16'd6549;
lutrom[131] = 16'd6599;
lutrom[132] = 16'd6649;
lutrom[133] = 16'd6699;
lutrom[134] = 16'd6749;
lutrom[135] = 16'd6799;
lutrom[136] = 16'd6849;
lutrom[137] = 16'd6899;
lutrom[138] = 16'd6949;
lutrom[139] = 16'd6999;
lutrom[140] = 16'd7049;
lutrom[141] = 16'd7099;
lutrom[142] = 16'd7148;
lutrom[143] = 16'd7198;
lutrom[144] = 16'd7248;
lutrom[145] = 16'd7298;
lutrom[146] = 16'd7348;
lutrom[147] = 16'd7398;
lutrom[148] = 16'd7448;
lutrom[149] = 16'd7498;
lutrom[150] = 16'd7548;
lutrom[151] = 16'd7598;
lutrom[152] = 16'd7648;
lutrom[153] = 16'd7698;
lutrom[154] = 16'd7748;
lutrom[155] = 16'd7798;
lutrom[156] = 16'd7848;
lutrom[157] = 16'd7897;
lutrom[158] = 16'd7947;
lutrom[159] = 16'd7997;
lutrom[160] = 16'd8047;
lutrom[161] = 16'd8097;
lutrom[162] = 16'd8147;
lutrom[163] = 16'd8197;
lutrom[164] = 16'd8247;
lutrom[165] = 16'd8296;
lutrom[166] = 16'd8346;
lutrom[167] = 16'd8396;
lutrom[168] = 16'd8446;
lutrom[169] = 16'd8496;
lutrom[170] = 16'd8546;
lutrom[171] = 16'd8596;
lutrom[172] = 16'd8645;
lutrom[173] = 16'd8695;
lutrom[174] = 16'd8745;
lutrom[175] = 16'd8795;
lutrom[176] = 16'd8845;
lutrom[177] = 16'd8894;
lutrom[178] = 16'd8944;
lutrom[179] = 16'd8994;
lutrom[180] = 16'd9044;
lutrom[181] = 16'd9094;
lutrom[182] = 16'd9143;
lutrom[183] = 16'd9193;
lutrom[184] = 16'd9243;
lutrom[185] = 16'd9293;
lutrom[186] = 16'd9342;
lutrom[187] = 16'd9392;
lutrom[188] = 16'd9442;
lutrom[189] = 16'd9492;
lutrom[190] = 16'd9541;
lutrom[191] = 16'd9591;
lutrom[192] = 16'd9641;
lutrom[193] = 16'd9691;
lutrom[194] = 16'd9740;
lutrom[195] = 16'd9790;
lutrom[196] = 16'd9840;
lutrom[197] = 16'd9889;
lutrom[198] = 16'd9939;
lutrom[199] = 16'd9989;
lutrom[200] = 16'd10038;
lutrom[201] = 16'd10088;
lutrom[202] = 16'd10138;
lutrom[203] = 16'd10187;
lutrom[204] = 16'd10237;
lutrom[205] = 16'd10287;
lutrom[206] = 16'd10336;
lutrom[207] = 16'd10386;
lutrom[208] = 16'd10436;
lutrom[209] = 16'd10485;
lutrom[210] = 16'd10535;
lutrom[211] = 16'd10584;
lutrom[212] = 16'd10634;
lutrom[213] = 16'd10684;
lutrom[214] = 16'd10733;
lutrom[215] = 16'd10783;
lutrom[216] = 16'd10832;
lutrom[217] = 16'd10882;
lutrom[218] = 16'd10932;
lutrom[219] = 16'd10981;
lutrom[220] = 16'd11031;
lutrom[221] = 16'd11080;
lutrom[222] = 16'd11130;
lutrom[223] = 16'd11179;
lutrom[224] = 16'd11229;
lutrom[225] = 16'd11278;
lutrom[226] = 16'd11328;
lutrom[227] = 16'd11377;
lutrom[228] = 16'd11427;
lutrom[229] = 16'd11476;
lutrom[230] = 16'd11526;
lutrom[231] = 16'd11575;
lutrom[232] = 16'd11625;
lutrom[233] = 16'd11674;
lutrom[234] = 16'd11724;
lutrom[235] = 16'd11773;
lutrom[236] = 16'd11823;
lutrom[237] = 16'd11872;
lutrom[238] = 16'd11921;
lutrom[239] = 16'd11971;
lutrom[240] = 16'd12020;
lutrom[241] = 16'd12070;
lutrom[242] = 16'd12119;
lutrom[243] = 16'd12168;
lutrom[244] = 16'd12218;
lutrom[245] = 16'd12267;
lutrom[246] = 16'd12317;
lutrom[247] = 16'd12366;
lutrom[248] = 16'd12415;
lutrom[249] = 16'd12465;
lutrom[250] = 16'd12514;
lutrom[251] = 16'd12563;
lutrom[252] = 16'd12613;
lutrom[253] = 16'd12662;
lutrom[254] = 16'd12711;
lutrom[255] = 16'd12761;
lutrom[256] = 16'd12810;
lutrom[257] = 16'd12859;
lutrom[258] = 16'd12908;
lutrom[259] = 16'd12958;
lutrom[260] = 16'd13007;
lutrom[261] = 16'd13056;
lutrom[262] = 16'd13106;
lutrom[263] = 16'd13155;
lutrom[264] = 16'd13204;
lutrom[265] = 16'd13253;
lutrom[266] = 16'd13302;
lutrom[267] = 16'd13352;
lutrom[268] = 16'd13401;
lutrom[269] = 16'd13450;
lutrom[270] = 16'd13499;
lutrom[271] = 16'd13548;
lutrom[272] = 16'd13598;
lutrom[273] = 16'd13647;
lutrom[274] = 16'd13696;
lutrom[275] = 16'd13745;
lutrom[276] = 16'd13794;
lutrom[277] = 16'd13843;
lutrom[278] = 16'd13893;
lutrom[279] = 16'd13942;
lutrom[280] = 16'd13991;
lutrom[281] = 16'd14040;
lutrom[282] = 16'd14089;
lutrom[283] = 16'd14138;
lutrom[284] = 16'd14187;
lutrom[285] = 16'd14236;
lutrom[286] = 16'd14285;
lutrom[287] = 16'd14334;
lutrom[288] = 16'd14383;
lutrom[289] = 16'd14432;
lutrom[290] = 16'd14481;
lutrom[291] = 16'd14530;
lutrom[292] = 16'd14579;
lutrom[293] = 16'd14628;
lutrom[294] = 16'd14677;
lutrom[295] = 16'd14726;
lutrom[296] = 16'd14775;
lutrom[297] = 16'd14824;
lutrom[298] = 16'd14873;
lutrom[299] = 16'd14922;
lutrom[300] = 16'd14971;
lutrom[301] = 16'd15020;
lutrom[302] = 16'd15069;
lutrom[303] = 16'd15118;
lutrom[304] = 16'd15167;
lutrom[305] = 16'd15216;
lutrom[306] = 16'd15265;
lutrom[307] = 16'd15314;
lutrom[308] = 16'd15362;
lutrom[309] = 16'd15411;
lutrom[310] = 16'd15460;
lutrom[311] = 16'd15509;
lutrom[312] = 16'd15558;
lutrom[313] = 16'd15607;
lutrom[314] = 16'd15655;
lutrom[315] = 16'd15704;
lutrom[316] = 16'd15753;
lutrom[317] = 16'd15802;
lutrom[318] = 16'd15851;
lutrom[319] = 16'd15899;
lutrom[320] = 16'd15948;
lutrom[321] = 16'd15997;
lutrom[322] = 16'd16046;
lutrom[323] = 16'd16094;
lutrom[324] = 16'd16143;
lutrom[325] = 16'd16192;
lutrom[326] = 16'd16240;
lutrom[327] = 16'd16289;
lutrom[328] = 16'd16338;
lutrom[329] = 16'd16386;
lutrom[330] = 16'd16435;
lutrom[331] = 16'd16484;
lutrom[332] = 16'd16532;
lutrom[333] = 16'd16581;
lutrom[334] = 16'd16630;
lutrom[335] = 16'd16678;
lutrom[336] = 16'd16727;
lutrom[337] = 16'd16776;
lutrom[338] = 16'd16824;
lutrom[339] = 16'd16873;
lutrom[340] = 16'd16921;
lutrom[341] = 16'd16970;
lutrom[342] = 16'd17018;
lutrom[343] = 16'd17067;
lutrom[344] = 16'd17115;
lutrom[345] = 16'd17164;
lutrom[346] = 16'd17212;
lutrom[347] = 16'd17261;
lutrom[348] = 16'd17309;
lutrom[349] = 16'd17358;
lutrom[350] = 16'd17406;
lutrom[351] = 16'd17455;
lutrom[352] = 16'd17503;
lutrom[353] = 16'd17552;
lutrom[354] = 16'd17600;
lutrom[355] = 16'd17649;
lutrom[356] = 16'd17697;
lutrom[357] = 16'd17745;
lutrom[358] = 16'd17794;
lutrom[359] = 16'd17842;
lutrom[360] = 16'd17890;
lutrom[361] = 16'd17939;
lutrom[362] = 16'd17987;
lutrom[363] = 16'd18035;
lutrom[364] = 16'd18084;
lutrom[365] = 16'd18132;
lutrom[366] = 16'd18180;
lutrom[367] = 16'd18229;
lutrom[368] = 16'd18277;
lutrom[369] = 16'd18325;
lutrom[370] = 16'd18373;
lutrom[371] = 16'd18422;
lutrom[372] = 16'd18470;
lutrom[373] = 16'd18518;
lutrom[374] = 16'd18566;
lutrom[375] = 16'd18615;
lutrom[376] = 16'd18663;
lutrom[377] = 16'd18711;
lutrom[378] = 16'd18759;
lutrom[379] = 16'd18807;
lutrom[380] = 16'd18855;
lutrom[381] = 16'd18904;
lutrom[382] = 16'd18952;
lutrom[383] = 16'd19000;
lutrom[384] = 16'd19048;
lutrom[385] = 16'd19096;
lutrom[386] = 16'd19144;
lutrom[387] = 16'd19192;
lutrom[388] = 16'd19240;
lutrom[389] = 16'd19288;
lutrom[390] = 16'd19336;
lutrom[391] = 16'd19384;
lutrom[392] = 16'd19432;
lutrom[393] = 16'd19480;
lutrom[394] = 16'd19528;
lutrom[395] = 16'd19576;
lutrom[396] = 16'd19624;
lutrom[397] = 16'd19672;
lutrom[398] = 16'd19720;
lutrom[399] = 16'd19768;
lutrom[400] = 16'd19816;
lutrom[401] = 16'd19864;
lutrom[402] = 16'd19912;
lutrom[403] = 16'd19960;
lutrom[404] = 16'd20007;
lutrom[405] = 16'd20055;
lutrom[406] = 16'd20103;
lutrom[407] = 16'd20151;
lutrom[408] = 16'd20199;
lutrom[409] = 16'd20247;
lutrom[410] = 16'd20294;
lutrom[411] = 16'd20342;
lutrom[412] = 16'd20390;
lutrom[413] = 16'd20438;
lutrom[414] = 16'd20486;
lutrom[415] = 16'd20533;
lutrom[416] = 16'd20581;
lutrom[417] = 16'd20629;
lutrom[418] = 16'd20676;
lutrom[419] = 16'd20724;
lutrom[420] = 16'd20772;
lutrom[421] = 16'd20819;
lutrom[422] = 16'd20867;
lutrom[423] = 16'd20915;
lutrom[424] = 16'd20962;
lutrom[425] = 16'd21010;
lutrom[426] = 16'd21058;
lutrom[427] = 16'd21105;
lutrom[428] = 16'd21153;
lutrom[429] = 16'd21200;
lutrom[430] = 16'd21248;
lutrom[431] = 16'd21295;
lutrom[432] = 16'd21343;
lutrom[433] = 16'd21390;
lutrom[434] = 16'd21438;
lutrom[435] = 16'd21485;
lutrom[436] = 16'd21533;
lutrom[437] = 16'd21580;
lutrom[438] = 16'd21628;
lutrom[439] = 16'd21675;
lutrom[440] = 16'd21723;
lutrom[441] = 16'd21770;
lutrom[442] = 16'd21818;
lutrom[443] = 16'd21865;
lutrom[444] = 16'd21912;
lutrom[445] = 16'd21960;
lutrom[446] = 16'd22007;
lutrom[447] = 16'd22054;
lutrom[448] = 16'd22102;
lutrom[449] = 16'd22149;
lutrom[450] = 16'd22196;
lutrom[451] = 16'd22244;
lutrom[452] = 16'd22291;
lutrom[453] = 16'd22338;
lutrom[454] = 16'd22385;
lutrom[455] = 16'd22433;
lutrom[456] = 16'd22480;
lutrom[457] = 16'd22527;
lutrom[458] = 16'd22574;
lutrom[459] = 16'd22621;
lutrom[460] = 16'd22669;
lutrom[461] = 16'd22716;
lutrom[462] = 16'd22763;
lutrom[463] = 16'd22810;
lutrom[464] = 16'd22857;
lutrom[465] = 16'd22904;
lutrom[466] = 16'd22951;
lutrom[467] = 16'd22998;
lutrom[468] = 16'd23045;
lutrom[469] = 16'd23093;
lutrom[470] = 16'd23140;
lutrom[471] = 16'd23187;
lutrom[472] = 16'd23234;
lutrom[473] = 16'd23281;
lutrom[474] = 16'd23328;
lutrom[475] = 16'd23375;
lutrom[476] = 16'd23421;
lutrom[477] = 16'd23468;
lutrom[478] = 16'd23515;
lutrom[479] = 16'd23562;
lutrom[480] = 16'd23609;
lutrom[481] = 16'd23656;
lutrom[482] = 16'd23703;
lutrom[483] = 16'd23750;
lutrom[484] = 16'd23797;
lutrom[485] = 16'd23843;
lutrom[486] = 16'd23890;
lutrom[487] = 16'd23937;
lutrom[488] = 16'd23984;
lutrom[489] = 16'd24031;
lutrom[490] = 16'd24077;
lutrom[491] = 16'd24124;
lutrom[492] = 16'd24171;
lutrom[493] = 16'd24218;
lutrom[494] = 16'd24264;
lutrom[495] = 16'd24311;
lutrom[496] = 16'd24358;
lutrom[497] = 16'd24404;
lutrom[498] = 16'd24451;
lutrom[499] = 16'd24498;
lutrom[500] = 16'd24544;
lutrom[501] = 16'd24591;
lutrom[502] = 16'd24637;
lutrom[503] = 16'd24684;
lutrom[504] = 16'd24730;
lutrom[505] = 16'd24777;
lutrom[506] = 16'd24824;
lutrom[507] = 16'd24870;
lutrom[508] = 16'd24917;
lutrom[509] = 16'd24963;
lutrom[510] = 16'd25009;
lutrom[511] = 16'd25056;
lutrom[512] = 16'd25102;
lutrom[513] = 16'd25149;
lutrom[514] = 16'd25195;
lutrom[515] = 16'd25242;
lutrom[516] = 16'd25288;
lutrom[517] = 16'd25334;
lutrom[518] = 16'd25381;
lutrom[519] = 16'd25427;
lutrom[520] = 16'd25473;
lutrom[521] = 16'd25520;
lutrom[522] = 16'd25566;
lutrom[523] = 16'd25612;
lutrom[524] = 16'd25658;
lutrom[525] = 16'd25705;
lutrom[526] = 16'd25751;
lutrom[527] = 16'd25797;
lutrom[528] = 16'd25843;
lutrom[529] = 16'd25890;
lutrom[530] = 16'd25936;
lutrom[531] = 16'd25982;
lutrom[532] = 16'd26028;
lutrom[533] = 16'd26074;
lutrom[534] = 16'd26120;
lutrom[535] = 16'd26166;
lutrom[536] = 16'd26212;
lutrom[537] = 16'd26258;
lutrom[538] = 16'd26305;
lutrom[539] = 16'd26351;
lutrom[540] = 16'd26397;
lutrom[541] = 16'd26443;
lutrom[542] = 16'd26489;
lutrom[543] = 16'd26535;
lutrom[544] = 16'd26580;
lutrom[545] = 16'd26626;
lutrom[546] = 16'd26672;
lutrom[547] = 16'd26718;
lutrom[548] = 16'd26764;
lutrom[549] = 16'd26810;
lutrom[550] = 16'd26856;
lutrom[551] = 16'd26902;
lutrom[552] = 16'd26948;
lutrom[553] = 16'd26993;
lutrom[554] = 16'd27039;
lutrom[555] = 16'd27085;
lutrom[556] = 16'd27131;
lutrom[557] = 16'd27176;
lutrom[558] = 16'd27222;
lutrom[559] = 16'd27268;
lutrom[560] = 16'd27314;
lutrom[561] = 16'd27359;
lutrom[562] = 16'd27405;
lutrom[563] = 16'd27451;
lutrom[564] = 16'd27496;
lutrom[565] = 16'd27542;
lutrom[566] = 16'd27587;
lutrom[567] = 16'd27633;
lutrom[568] = 16'd27679;
lutrom[569] = 16'd27724;
lutrom[570] = 16'd27770;
lutrom[571] = 16'd27815;
lutrom[572] = 16'd27861;
lutrom[573] = 16'd27906;
lutrom[574] = 16'd27952;
lutrom[575] = 16'd27997;
lutrom[576] = 16'd28043;
lutrom[577] = 16'd28088;
lutrom[578] = 16'd28133;
lutrom[579] = 16'd28179;
lutrom[580] = 16'd28224;
lutrom[581] = 16'd28269;
lutrom[582] = 16'd28315;
lutrom[583] = 16'd28360;
lutrom[584] = 16'd28405;
lutrom[585] = 16'd28451;
lutrom[586] = 16'd28496;
lutrom[587] = 16'd28541;
lutrom[588] = 16'd28587;
lutrom[589] = 16'd28632;
lutrom[590] = 16'd28677;
lutrom[591] = 16'd28722;
lutrom[592] = 16'd28767;
lutrom[593] = 16'd28812;
lutrom[594] = 16'd28858;
lutrom[595] = 16'd28903;
lutrom[596] = 16'd28948;
lutrom[597] = 16'd28993;
lutrom[598] = 16'd29038;
lutrom[599] = 16'd29083;
lutrom[600] = 16'd29128;
lutrom[601] = 16'd29173;
lutrom[602] = 16'd29218;
lutrom[603] = 16'd29263;
lutrom[604] = 16'd29308;
lutrom[605] = 16'd29353;
lutrom[606] = 16'd29398;
lutrom[607] = 16'd29443;
lutrom[608] = 16'd29488;
lutrom[609] = 16'd29533;
lutrom[610] = 16'd29577;
lutrom[611] = 16'd29622;
lutrom[612] = 16'd29667;
lutrom[613] = 16'd29712;
lutrom[614] = 16'd29757;
lutrom[615] = 16'd29802;
lutrom[616] = 16'd29846;
lutrom[617] = 16'd29891;
lutrom[618] = 16'd29936;
lutrom[619] = 16'd29980;
lutrom[620] = 16'd30025;
lutrom[621] = 16'd30070;
lutrom[622] = 16'd30114;
lutrom[623] = 16'd30159;
lutrom[624] = 16'd30204;
lutrom[625] = 16'd30248;
lutrom[626] = 16'd30293;
lutrom[627] = 16'd30337;
lutrom[628] = 16'd30382;
lutrom[629] = 16'd30427;
lutrom[630] = 16'd30471;
lutrom[631] = 16'd30516;
lutrom[632] = 16'd30560;
lutrom[633] = 16'd30604;
lutrom[634] = 16'd30649;
lutrom[635] = 16'd30693;
lutrom[636] = 16'd30738;
lutrom[637] = 16'd30782;
lutrom[638] = 16'd30826;
lutrom[639] = 16'd30871;
lutrom[640] = 16'd30915;
lutrom[641] = 16'd30959;
lutrom[642] = 16'd31004;
lutrom[643] = 16'd31048;
lutrom[644] = 16'd31092;
lutrom[645] = 16'd31137;
lutrom[646] = 16'd31181;
lutrom[647] = 16'd31225;
lutrom[648] = 16'd31269;
lutrom[649] = 16'd31313;
lutrom[650] = 16'd31357;
lutrom[651] = 16'd31402;
lutrom[652] = 16'd31446;
lutrom[653] = 16'd31490;
lutrom[654] = 16'd31534;
lutrom[655] = 16'd31578;
lutrom[656] = 16'd31622;
lutrom[657] = 16'd31666;
lutrom[658] = 16'd31710;
lutrom[659] = 16'd31754;
lutrom[660] = 16'd31798;
lutrom[661] = 16'd31842;
lutrom[662] = 16'd31886;
lutrom[663] = 16'd31930;
lutrom[664] = 16'd31974;
lutrom[665] = 16'd32017;
lutrom[666] = 16'd32061;
lutrom[667] = 16'd32105;
lutrom[668] = 16'd32149;
lutrom[669] = 16'd32193;
lutrom[670] = 16'd32236;
lutrom[671] = 16'd32280;
lutrom[672] = 16'd32324;
lutrom[673] = 16'd32368;
lutrom[674] = 16'd32411;
lutrom[675] = 16'd32455;
lutrom[676] = 16'd32499;
lutrom[677] = 16'd32542;
lutrom[678] = 16'd32586;
lutrom[679] = 16'd32630;
lutrom[680] = 16'd32673;
lutrom[681] = 16'd32717;
lutrom[682] = 16'd32760;
lutrom[683] = 16'd32804;
lutrom[684] = 16'd32847;
lutrom[685] = 16'd32891;
lutrom[686] = 16'd32934;
lutrom[687] = 16'd32978;
lutrom[688] = 16'd33021;
lutrom[689] = 16'd33065;
lutrom[690] = 16'd33108;
lutrom[691] = 16'd33151;
lutrom[692] = 16'd33195;
lutrom[693] = 16'd33238;
lutrom[694] = 16'd33281;
lutrom[695] = 16'd33325;
lutrom[696] = 16'd33368;
lutrom[697] = 16'd33411;
lutrom[698] = 16'd33454;
lutrom[699] = 16'd33498;
lutrom[700] = 16'd33541;
lutrom[701] = 16'd33584;
lutrom[702] = 16'd33627;
lutrom[703] = 16'd33670;
lutrom[704] = 16'd33713;
lutrom[705] = 16'd33756;
lutrom[706] = 16'd33799;
lutrom[707] = 16'd33842;
lutrom[708] = 16'd33886;
lutrom[709] = 16'd33929;
lutrom[710] = 16'd33972;
lutrom[711] = 16'd34015;
lutrom[712] = 16'd34057;
lutrom[713] = 16'd34100;
lutrom[714] = 16'd34143;
lutrom[715] = 16'd34186;
lutrom[716] = 16'd34229;
lutrom[717] = 16'd34272;
lutrom[718] = 16'd34315;
lutrom[719] = 16'd34358;
lutrom[720] = 16'd34400;
lutrom[721] = 16'd34443;
lutrom[722] = 16'd34486;
lutrom[723] = 16'd34529;
lutrom[724] = 16'd34571;
lutrom[725] = 16'd34614;
lutrom[726] = 16'd34657;
lutrom[727] = 16'd34699;
lutrom[728] = 16'd34742;
lutrom[729] = 16'd34785;
lutrom[730] = 16'd34827;
lutrom[731] = 16'd34870;
lutrom[732] = 16'd34912;
lutrom[733] = 16'd34955;
lutrom[734] = 16'd34997;
lutrom[735] = 16'd35040;
lutrom[736] = 16'd35082;
lutrom[737] = 16'd35125;
lutrom[738] = 16'd35167;
lutrom[739] = 16'd35210;
lutrom[740] = 16'd35252;
lutrom[741] = 16'd35294;
lutrom[742] = 16'd35337;
lutrom[743] = 16'd35379;
lutrom[744] = 16'd35421;
lutrom[745] = 16'd35464;
lutrom[746] = 16'd35506;
lutrom[747] = 16'd35548;
lutrom[748] = 16'd35590;
lutrom[749] = 16'd35632;
lutrom[750] = 16'd35675;
lutrom[751] = 16'd35717;
lutrom[752] = 16'd35759;
lutrom[753] = 16'd35801;
lutrom[754] = 16'd35843;
lutrom[755] = 16'd35885;
lutrom[756] = 16'd35927;
lutrom[757] = 16'd35969;
lutrom[758] = 16'd36011;
lutrom[759] = 16'd36053;
lutrom[760] = 16'd36095;
lutrom[761] = 16'd36137;
lutrom[762] = 16'd36179;
lutrom[763] = 16'd36221;
lutrom[764] = 16'd36263;
lutrom[765] = 16'd36305;
lutrom[766] = 16'd36347;
lutrom[767] = 16'd36388;
lutrom[768] = 16'd36430;
lutrom[769] = 16'd36472;
lutrom[770] = 16'd36514;
lutrom[771] = 16'd36555;
lutrom[772] = 16'd36597;
lutrom[773] = 16'd36639;
lutrom[774] = 16'd36680;
lutrom[775] = 16'd36722;
lutrom[776] = 16'd36764;
lutrom[777] = 16'd36805;
lutrom[778] = 16'd36847;
lutrom[779] = 16'd36888;
lutrom[780] = 16'd36930;
lutrom[781] = 16'd36972;
lutrom[782] = 16'd37013;
lutrom[783] = 16'd37055;
lutrom[784] = 16'd37096;
lutrom[785] = 16'd37137;
lutrom[786] = 16'd37179;
lutrom[787] = 16'd37220;
lutrom[788] = 16'd37262;
lutrom[789] = 16'd37303;
lutrom[790] = 16'd37344;
lutrom[791] = 16'd37385;
lutrom[792] = 16'd37427;
lutrom[793] = 16'd37468;
lutrom[794] = 16'd37509;
lutrom[795] = 16'd37550;
lutrom[796] = 16'd37592;
lutrom[797] = 16'd37633;
lutrom[798] = 16'd37674;
lutrom[799] = 16'd37715;
lutrom[800] = 16'd37756;
lutrom[801] = 16'd37797;
lutrom[802] = 16'd37838;
lutrom[803] = 16'd37879;
lutrom[804] = 16'd37920;
lutrom[805] = 16'd37961;
lutrom[806] = 16'd38002;
lutrom[807] = 16'd38043;
lutrom[808] = 16'd38084;
lutrom[809] = 16'd38125;
lutrom[810] = 16'd38166;
lutrom[811] = 16'd38207;
lutrom[812] = 16'd38248;
lutrom[813] = 16'd38288;
lutrom[814] = 16'd38329;
lutrom[815] = 16'd38370;
lutrom[816] = 16'd38411;
lutrom[817] = 16'd38451;
lutrom[818] = 16'd38492;
lutrom[819] = 16'd38533;
lutrom[820] = 16'd38573;
lutrom[821] = 16'd38614;
lutrom[822] = 16'd38655;
lutrom[823] = 16'd38695;
lutrom[824] = 16'd38736;
lutrom[825] = 16'd38776;
lutrom[826] = 16'd38817;
lutrom[827] = 16'd38857;
lutrom[828] = 16'd38898;
lutrom[829] = 16'd38938;
lutrom[830] = 16'd38979;
lutrom[831] = 16'd39019;
lutrom[832] = 16'd39059;
lutrom[833] = 16'd39100;
lutrom[834] = 16'd39140;
lutrom[835] = 16'd39180;
lutrom[836] = 16'd39221;
lutrom[837] = 16'd39261;
lutrom[838] = 16'd39301;
lutrom[839] = 16'd39341;
lutrom[840] = 16'd39381;
lutrom[841] = 16'd39422;
lutrom[842] = 16'd39462;
lutrom[843] = 16'd39502;
lutrom[844] = 16'd39542;
lutrom[845] = 16'd39582;
lutrom[846] = 16'd39622;
lutrom[847] = 16'd39662;
lutrom[848] = 16'd39702;
lutrom[849] = 16'd39742;
lutrom[850] = 16'd39782;
lutrom[851] = 16'd39822;
lutrom[852] = 16'd39862;
lutrom[853] = 16'd39902;
lutrom[854] = 16'd39942;
lutrom[855] = 16'd39982;
lutrom[856] = 16'd40021;
lutrom[857] = 16'd40061;
lutrom[858] = 16'd40101;
lutrom[859] = 16'd40141;
lutrom[860] = 16'd40180;
lutrom[861] = 16'd40220;
lutrom[862] = 16'd40260;
lutrom[863] = 16'd40299;
lutrom[864] = 16'd40339;
lutrom[865] = 16'd40379;
lutrom[866] = 16'd40418;
lutrom[867] = 16'd40458;
lutrom[868] = 16'd40497;
lutrom[869] = 16'd40537;
lutrom[870] = 16'd40576;
lutrom[871] = 16'd40616;
lutrom[872] = 16'd40655;
lutrom[873] = 16'd40695;
lutrom[874] = 16'd40734;
lutrom[875] = 16'd40773;
lutrom[876] = 16'd40813;
lutrom[877] = 16'd40852;
lutrom[878] = 16'd40891;
lutrom[879] = 16'd40931;
lutrom[880] = 16'd40970;
lutrom[881] = 16'd41009;
lutrom[882] = 16'd41048;
lutrom[883] = 16'd41087;
lutrom[884] = 16'd41127;
lutrom[885] = 16'd41166;
lutrom[886] = 16'd41205;
lutrom[887] = 16'd41244;
lutrom[888] = 16'd41283;
lutrom[889] = 16'd41322;
lutrom[890] = 16'd41361;
lutrom[891] = 16'd41400;
lutrom[892] = 16'd41439;
lutrom[893] = 16'd41478;
lutrom[894] = 16'd41517;
lutrom[895] = 16'd41556;
lutrom[896] = 16'd41594;
lutrom[897] = 16'd41633;
lutrom[898] = 16'd41672;
lutrom[899] = 16'd41711;
lutrom[900] = 16'd41750;
lutrom[901] = 16'd41788;
lutrom[902] = 16'd41827;
lutrom[903] = 16'd41866;
lutrom[904] = 16'd41904;
lutrom[905] = 16'd41943;
lutrom[906] = 16'd41982;
lutrom[907] = 16'd42020;
lutrom[908] = 16'd42059;
lutrom[909] = 16'd42097;
lutrom[910] = 16'd42136;
lutrom[911] = 16'd42174;
lutrom[912] = 16'd42213;
lutrom[913] = 16'd42251;
lutrom[914] = 16'd42290;
lutrom[915] = 16'd42328;
lutrom[916] = 16'd42366;
lutrom[917] = 16'd42405;
lutrom[918] = 16'd42443;
lutrom[919] = 16'd42481;
lutrom[920] = 16'd42520;
lutrom[921] = 16'd42558;
lutrom[922] = 16'd42596;
lutrom[923] = 16'd42634;
lutrom[924] = 16'd42672;
lutrom[925] = 16'd42710;
lutrom[926] = 16'd42749;
lutrom[927] = 16'd42787;
lutrom[928] = 16'd42825;
lutrom[929] = 16'd42863;
lutrom[930] = 16'd42901;
lutrom[931] = 16'd42939;
lutrom[932] = 16'd42977;
lutrom[933] = 16'd43015;
lutrom[934] = 16'd43053;
lutrom[935] = 16'd43090;
lutrom[936] = 16'd43128;
lutrom[937] = 16'd43166;
lutrom[938] = 16'd43204;
lutrom[939] = 16'd43242;
lutrom[940] = 16'd43279;
lutrom[941] = 16'd43317;
lutrom[942] = 16'd43355;
lutrom[943] = 16'd43393;
lutrom[944] = 16'd43430;
lutrom[945] = 16'd43468;
lutrom[946] = 16'd43505;
lutrom[947] = 16'd43543;
lutrom[948] = 16'd43581;
lutrom[949] = 16'd43618;
lutrom[950] = 16'd43656;
lutrom[951] = 16'd43693;
lutrom[952] = 16'd43731;
lutrom[953] = 16'd43768;
lutrom[954] = 16'd43805;
lutrom[955] = 16'd43843;
lutrom[956] = 16'd43880;
lutrom[957] = 16'd43917;
lutrom[958] = 16'd43955;
lutrom[959] = 16'd43992;
lutrom[960] = 16'd44029;
lutrom[961] = 16'd44066;
lutrom[962] = 16'd44104;
lutrom[963] = 16'd44141;
lutrom[964] = 16'd44178;
lutrom[965] = 16'd44215;
lutrom[966] = 16'd44252;
lutrom[967] = 16'd44289;
lutrom[968] = 16'd44326;
lutrom[969] = 16'd44363;
lutrom[970] = 16'd44400;
lutrom[971] = 16'd44437;
lutrom[972] = 16'd44474;
lutrom[973] = 16'd44511;
lutrom[974] = 16'd44548;
lutrom[975] = 16'd44585;
lutrom[976] = 16'd44622;
lutrom[977] = 16'd44658;
lutrom[978] = 16'd44695;
lutrom[979] = 16'd44732;
lutrom[980] = 16'd44769;
lutrom[981] = 16'd44805;
lutrom[982] = 16'd44842;
lutrom[983] = 16'd44879;
lutrom[984] = 16'd44915;
lutrom[985] = 16'd44952;
lutrom[986] = 16'd44988;
lutrom[987] = 16'd45025;
lutrom[988] = 16'd45061;
lutrom[989] = 16'd45098;
lutrom[990] = 16'd45134;
lutrom[991] = 16'd45171;
lutrom[992] = 16'd45207;
lutrom[993] = 16'd45244;
lutrom[994] = 16'd45280;
lutrom[995] = 16'd45316;
lutrom[996] = 16'd45353;
lutrom[997] = 16'd45389;
lutrom[998] = 16'd45425;
lutrom[999] = 16'd45461;
lutrom[1000] = 16'd45498;
lutrom[1001] = 16'd45534;
lutrom[1002] = 16'd45570;
lutrom[1003] = 16'd45606;
lutrom[1004] = 16'd45642;
lutrom[1005] = 16'd45678;
lutrom[1006] = 16'd45714;
lutrom[1007] = 16'd45750;
lutrom[1008] = 16'd45786;
lutrom[1009] = 16'd45822;
lutrom[1010] = 16'd45858;
lutrom[1011] = 16'd45894;
lutrom[1012] = 16'd45930;
lutrom[1013] = 16'd45966;
lutrom[1014] = 16'd46001;
lutrom[1015] = 16'd46037;
lutrom[1016] = 16'd46073;
lutrom[1017] = 16'd46109;
lutrom[1018] = 16'd46144;
lutrom[1019] = 16'd46180;
lutrom[1020] = 16'd46216;
lutrom[1021] = 16'd46251;
lutrom[1022] = 16'd46287;
lutrom[1023] = 16'd46322;
lutrom[1024] = 16'd46358;
lutrom[1025] = 16'd46394;
lutrom[1026] = 16'd46429;
lutrom[1027] = 16'd46464;
lutrom[1028] = 16'd46500;
lutrom[1029] = 16'd46535;
lutrom[1030] = 16'd46571;
lutrom[1031] = 16'd46606;
lutrom[1032] = 16'd46641;
lutrom[1033] = 16'd46677;
lutrom[1034] = 16'd46712;
lutrom[1035] = 16'd46747;
lutrom[1036] = 16'd46782;
lutrom[1037] = 16'd46818;
lutrom[1038] = 16'd46853;
lutrom[1039] = 16'd46888;
lutrom[1040] = 16'd46923;
lutrom[1041] = 16'd46958;
lutrom[1042] = 16'd46993;
lutrom[1043] = 16'd47028;
lutrom[1044] = 16'd47063;
lutrom[1045] = 16'd47098;
lutrom[1046] = 16'd47133;
lutrom[1047] = 16'd47168;
lutrom[1048] = 16'd47203;
lutrom[1049] = 16'd47238;
lutrom[1050] = 16'd47272;
lutrom[1051] = 16'd47307;
lutrom[1052] = 16'd47342;
lutrom[1053] = 16'd47377;
lutrom[1054] = 16'd47412;
lutrom[1055] = 16'd47446;
lutrom[1056] = 16'd47481;
lutrom[1057] = 16'd47515;
lutrom[1058] = 16'd47550;
lutrom[1059] = 16'd47585;
lutrom[1060] = 16'd47619;
lutrom[1061] = 16'd47654;
lutrom[1062] = 16'd47688;
lutrom[1063] = 16'd47723;
lutrom[1064] = 16'd47757;
lutrom[1065] = 16'd47792;
lutrom[1066] = 16'd47826;
lutrom[1067] = 16'd47860;
lutrom[1068] = 16'd47895;
lutrom[1069] = 16'd47929;
lutrom[1070] = 16'd47963;
lutrom[1071] = 16'd47997;
lutrom[1072] = 16'd48032;
lutrom[1073] = 16'd48066;
lutrom[1074] = 16'd48100;
lutrom[1075] = 16'd48134;
lutrom[1076] = 16'd48168;
lutrom[1077] = 16'd48202;
lutrom[1078] = 16'd48236;
lutrom[1079] = 16'd48270;
lutrom[1080] = 16'd48304;
lutrom[1081] = 16'd48338;
lutrom[1082] = 16'd48372;
lutrom[1083] = 16'd48406;
lutrom[1084] = 16'd48440;
lutrom[1085] = 16'd48474;
lutrom[1086] = 16'd48508;
lutrom[1087] = 16'd48541;
lutrom[1088] = 16'd48575;
lutrom[1089] = 16'd48609;
lutrom[1090] = 16'd48643;
lutrom[1091] = 16'd48676;
lutrom[1092] = 16'd48710;
lutrom[1093] = 16'd48743;
lutrom[1094] = 16'd48777;
lutrom[1095] = 16'd48811;
lutrom[1096] = 16'd48844;
lutrom[1097] = 16'd48878;
lutrom[1098] = 16'd48911;
lutrom[1099] = 16'd48945;
lutrom[1100] = 16'd48978;
lutrom[1101] = 16'd49011;
lutrom[1102] = 16'd49045;
lutrom[1103] = 16'd49078;
lutrom[1104] = 16'd49111;
lutrom[1105] = 16'd49145;
lutrom[1106] = 16'd49178;
lutrom[1107] = 16'd49211;
lutrom[1108] = 16'd49244;
lutrom[1109] = 16'd49277;
lutrom[1110] = 16'd49310;
lutrom[1111] = 16'd49344;
lutrom[1112] = 16'd49377;
lutrom[1113] = 16'd49410;
lutrom[1114] = 16'd49443;
lutrom[1115] = 16'd49476;
lutrom[1116] = 16'd49509;
lutrom[1117] = 16'd49542;
lutrom[1118] = 16'd49574;
lutrom[1119] = 16'd49607;
lutrom[1120] = 16'd49640;
lutrom[1121] = 16'd49673;
lutrom[1122] = 16'd49706;
lutrom[1123] = 16'd49738;
lutrom[1124] = 16'd49771;
lutrom[1125] = 16'd49804;
lutrom[1126] = 16'd49836;
lutrom[1127] = 16'd49869;
lutrom[1128] = 16'd49902;
lutrom[1129] = 16'd49934;
lutrom[1130] = 16'd49967;
lutrom[1131] = 16'd49999;
lutrom[1132] = 16'd50032;
lutrom[1133] = 16'd50064;
lutrom[1134] = 16'd50097;
lutrom[1135] = 16'd50129;
lutrom[1136] = 16'd50161;
lutrom[1137] = 16'd50194;
lutrom[1138] = 16'd50226;
lutrom[1139] = 16'd50258;
lutrom[1140] = 16'd50291;
lutrom[1141] = 16'd50323;
lutrom[1142] = 16'd50355;
lutrom[1143] = 16'd50387;
lutrom[1144] = 16'd50419;
lutrom[1145] = 16'd50451;
lutrom[1146] = 16'd50483;
lutrom[1147] = 16'd50515;
lutrom[1148] = 16'd50547;
lutrom[1149] = 16'd50579;
lutrom[1150] = 16'd50611;
lutrom[1151] = 16'd50643;
lutrom[1152] = 16'd50675;
lutrom[1153] = 16'd50707;
lutrom[1154] = 16'd50739;
lutrom[1155] = 16'd50771;
lutrom[1156] = 16'd50802;
lutrom[1157] = 16'd50834;
lutrom[1158] = 16'd50866;
lutrom[1159] = 16'd50898;
lutrom[1160] = 16'd50929;
lutrom[1161] = 16'd50961;
lutrom[1162] = 16'd50992;
lutrom[1163] = 16'd51024;
lutrom[1164] = 16'd51056;
lutrom[1165] = 16'd51087;
lutrom[1166] = 16'd51118;
lutrom[1167] = 16'd51150;
lutrom[1168] = 16'd51181;
lutrom[1169] = 16'd51213;
lutrom[1170] = 16'd51244;
lutrom[1171] = 16'd51275;
lutrom[1172] = 16'd51307;
lutrom[1173] = 16'd51338;
lutrom[1174] = 16'd51369;
lutrom[1175] = 16'd51400;
lutrom[1176] = 16'd51431;
lutrom[1177] = 16'd51463;
lutrom[1178] = 16'd51494;
lutrom[1179] = 16'd51525;
lutrom[1180] = 16'd51556;
lutrom[1181] = 16'd51587;
lutrom[1182] = 16'd51618;
lutrom[1183] = 16'd51649;
lutrom[1184] = 16'd51680;
lutrom[1185] = 16'd51711;
lutrom[1186] = 16'd51741;
lutrom[1187] = 16'd51772;
lutrom[1188] = 16'd51803;
lutrom[1189] = 16'd51834;
lutrom[1190] = 16'd51865;
lutrom[1191] = 16'd51895;
lutrom[1192] = 16'd51926;
lutrom[1193] = 16'd51957;
lutrom[1194] = 16'd51987;
lutrom[1195] = 16'd52018;
lutrom[1196] = 16'd52048;
lutrom[1197] = 16'd52079;
lutrom[1198] = 16'd52109;
lutrom[1199] = 16'd52140;
lutrom[1200] = 16'd52170;
lutrom[1201] = 16'd52201;
lutrom[1202] = 16'd52231;
lutrom[1203] = 16'd52262;
lutrom[1204] = 16'd52292;
lutrom[1205] = 16'd52322;
lutrom[1206] = 16'd52352;
lutrom[1207] = 16'd52383;
lutrom[1208] = 16'd52413;
lutrom[1209] = 16'd52443;
lutrom[1210] = 16'd52473;
lutrom[1211] = 16'd52503;
lutrom[1212] = 16'd52533;
lutrom[1213] = 16'd52563;
lutrom[1214] = 16'd52593;
lutrom[1215] = 16'd52623;
lutrom[1216] = 16'd52653;
lutrom[1217] = 16'd52683;
lutrom[1218] = 16'd52713;
lutrom[1219] = 16'd52743;
lutrom[1220] = 16'd52773;
lutrom[1221] = 16'd52802;
lutrom[1222] = 16'd52832;
lutrom[1223] = 16'd52862;
lutrom[1224] = 16'd52892;
lutrom[1225] = 16'd52921;
lutrom[1226] = 16'd52951;
lutrom[1227] = 16'd52980;
lutrom[1228] = 16'd53010;
lutrom[1229] = 16'd53040;
lutrom[1230] = 16'd53069;
lutrom[1231] = 16'd53099;
lutrom[1232] = 16'd53128;
lutrom[1233] = 16'd53157;
lutrom[1234] = 16'd53187;
lutrom[1235] = 16'd53216;
lutrom[1236] = 16'd53245;
lutrom[1237] = 16'd53275;
lutrom[1238] = 16'd53304;
lutrom[1239] = 16'd53333;
lutrom[1240] = 16'd53362;
lutrom[1241] = 16'd53392;
lutrom[1242] = 16'd53421;
lutrom[1243] = 16'd53450;
lutrom[1244] = 16'd53479;
lutrom[1245] = 16'd53508;
lutrom[1246] = 16'd53537;
lutrom[1247] = 16'd53566;
lutrom[1248] = 16'd53595;
lutrom[1249] = 16'd53624;
lutrom[1250] = 16'd53653;
lutrom[1251] = 16'd53682;
lutrom[1252] = 16'd53710;
lutrom[1253] = 16'd53739;
lutrom[1254] = 16'd53768;
lutrom[1255] = 16'd53797;
lutrom[1256] = 16'd53825;
lutrom[1257] = 16'd53854;
lutrom[1258] = 16'd53883;
lutrom[1259] = 16'd53911;
lutrom[1260] = 16'd53940;
lutrom[1261] = 16'd53968;
lutrom[1262] = 16'd53997;
lutrom[1263] = 16'd54025;
lutrom[1264] = 16'd54054;
lutrom[1265] = 16'd54082;
lutrom[1266] = 16'd54110;
lutrom[1267] = 16'd54139;
lutrom[1268] = 16'd54167;
lutrom[1269] = 16'd54195;
lutrom[1270] = 16'd54224;
lutrom[1271] = 16'd54252;
lutrom[1272] = 16'd54280;
lutrom[1273] = 16'd54308;
lutrom[1274] = 16'd54336;
lutrom[1275] = 16'd54364;
lutrom[1276] = 16'd54392;
lutrom[1277] = 16'd54420;
lutrom[1278] = 16'd54448;
lutrom[1279] = 16'd54476;
lutrom[1280] = 16'd54504;
lutrom[1281] = 16'd54532;
lutrom[1282] = 16'd54560;
lutrom[1283] = 16'd54588;
lutrom[1284] = 16'd54616;
lutrom[1285] = 16'd54643;
lutrom[1286] = 16'd54671;
lutrom[1287] = 16'd54699;
lutrom[1288] = 16'd54727;
lutrom[1289] = 16'd54754;
lutrom[1290] = 16'd54782;
lutrom[1291] = 16'd54809;
lutrom[1292] = 16'd54837;
lutrom[1293] = 16'd54864;
lutrom[1294] = 16'd54892;
lutrom[1295] = 16'd54919;
lutrom[1296] = 16'd54947;
lutrom[1297] = 16'd54974;
lutrom[1298] = 16'd55001;
lutrom[1299] = 16'd55029;
lutrom[1300] = 16'd55056;
lutrom[1301] = 16'd55083;
lutrom[1302] = 16'd55111;
lutrom[1303] = 16'd55138;
lutrom[1304] = 16'd55165;
lutrom[1305] = 16'd55192;
lutrom[1306] = 16'd55219;
lutrom[1307] = 16'd55246;
lutrom[1308] = 16'd55273;
lutrom[1309] = 16'd55300;
lutrom[1310] = 16'd55327;
lutrom[1311] = 16'd55354;
lutrom[1312] = 16'd55381;
lutrom[1313] = 16'd55408;
lutrom[1314] = 16'd55435;
lutrom[1315] = 16'd55461;
lutrom[1316] = 16'd55488;
lutrom[1317] = 16'd55515;
lutrom[1318] = 16'd55542;
lutrom[1319] = 16'd55568;
lutrom[1320] = 16'd55595;
lutrom[1321] = 16'd55621;
lutrom[1322] = 16'd55648;
lutrom[1323] = 16'd55675;
lutrom[1324] = 16'd55701;
lutrom[1325] = 16'd55728;
lutrom[1326] = 16'd55754;
lutrom[1327] = 16'd55780;
lutrom[1328] = 16'd55807;
lutrom[1329] = 16'd55833;
lutrom[1330] = 16'd55859;
lutrom[1331] = 16'd55886;
lutrom[1332] = 16'd55912;
lutrom[1333] = 16'd55938;
lutrom[1334] = 16'd55964;
lutrom[1335] = 16'd55990;
lutrom[1336] = 16'd56017;
lutrom[1337] = 16'd56043;
lutrom[1338] = 16'd56069;
lutrom[1339] = 16'd56095;
lutrom[1340] = 16'd56121;
lutrom[1341] = 16'd56147;
lutrom[1342] = 16'd56172;
lutrom[1343] = 16'd56198;
lutrom[1344] = 16'd56224;
lutrom[1345] = 16'd56250;
lutrom[1346] = 16'd56276;
lutrom[1347] = 16'd56301;
lutrom[1348] = 16'd56327;
lutrom[1349] = 16'd56353;
lutrom[1350] = 16'd56379;
lutrom[1351] = 16'd56404;
lutrom[1352] = 16'd56430;
lutrom[1353] = 16'd56455;
lutrom[1354] = 16'd56481;
lutrom[1355] = 16'd56506;
lutrom[1356] = 16'd56532;
lutrom[1357] = 16'd56557;
lutrom[1358] = 16'd56582;
lutrom[1359] = 16'd56608;
lutrom[1360] = 16'd56633;
lutrom[1361] = 16'd56658;
lutrom[1362] = 16'd56684;
lutrom[1363] = 16'd56709;
lutrom[1364] = 16'd56734;
lutrom[1365] = 16'd56759;
lutrom[1366] = 16'd56784;
lutrom[1367] = 16'd56809;
lutrom[1368] = 16'd56834;
lutrom[1369] = 16'd56859;
lutrom[1370] = 16'd56884;
lutrom[1371] = 16'd56909;
lutrom[1372] = 16'd56934;
lutrom[1373] = 16'd56959;
lutrom[1374] = 16'd56984;
lutrom[1375] = 16'd57009;
lutrom[1376] = 16'd57034;
lutrom[1377] = 16'd57058;
lutrom[1378] = 16'd57083;
lutrom[1379] = 16'd57108;
lutrom[1380] = 16'd57132;
lutrom[1381] = 16'd57157;
lutrom[1382] = 16'd57181;
lutrom[1383] = 16'd57206;
lutrom[1384] = 16'd57231;
lutrom[1385] = 16'd57255;
lutrom[1386] = 16'd57279;
lutrom[1387] = 16'd57304;
lutrom[1388] = 16'd57328;
lutrom[1389] = 16'd57353;
lutrom[1390] = 16'd57377;
lutrom[1391] = 16'd57401;
lutrom[1392] = 16'd57425;
lutrom[1393] = 16'd57450;
lutrom[1394] = 16'd57474;
lutrom[1395] = 16'd57498;
lutrom[1396] = 16'd57522;
lutrom[1397] = 16'd57546;
lutrom[1398] = 16'd57570;
lutrom[1399] = 16'd57594;
lutrom[1400] = 16'd57618;
lutrom[1401] = 16'd57642;
lutrom[1402] = 16'd57666;
lutrom[1403] = 16'd57690;
lutrom[1404] = 16'd57714;
lutrom[1405] = 16'd57737;
lutrom[1406] = 16'd57761;
lutrom[1407] = 16'd57785;
lutrom[1408] = 16'd57809;
lutrom[1409] = 16'd57832;
lutrom[1410] = 16'd57856;
lutrom[1411] = 16'd57879;
lutrom[1412] = 16'd57903;
lutrom[1413] = 16'd57927;
lutrom[1414] = 16'd57950;
lutrom[1415] = 16'd57973;
lutrom[1416] = 16'd57997;
lutrom[1417] = 16'd58020;
lutrom[1418] = 16'd58044;
lutrom[1419] = 16'd58067;
lutrom[1420] = 16'd58090;
lutrom[1421] = 16'd58113;
lutrom[1422] = 16'd58137;
lutrom[1423] = 16'd58160;
lutrom[1424] = 16'd58183;
lutrom[1425] = 16'd58206;
lutrom[1426] = 16'd58229;
lutrom[1427] = 16'd58252;
lutrom[1428] = 16'd58275;
lutrom[1429] = 16'd58298;
lutrom[1430] = 16'd58321;
lutrom[1431] = 16'd58344;
lutrom[1432] = 16'd58367;
lutrom[1433] = 16'd58390;
lutrom[1434] = 16'd58413;
lutrom[1435] = 16'd58435;
lutrom[1436] = 16'd58458;
lutrom[1437] = 16'd58481;
lutrom[1438] = 16'd58504;
lutrom[1439] = 16'd58526;
lutrom[1440] = 16'd58549;
lutrom[1441] = 16'd58571;
lutrom[1442] = 16'd58594;
lutrom[1443] = 16'd58616;
lutrom[1444] = 16'd58639;
lutrom[1445] = 16'd58661;
lutrom[1446] = 16'd58684;
lutrom[1447] = 16'd58706;
lutrom[1448] = 16'd58728;
lutrom[1449] = 16'd58751;
lutrom[1450] = 16'd58773;
lutrom[1451] = 16'd58795;
lutrom[1452] = 16'd58817;
lutrom[1453] = 16'd58839;
lutrom[1454] = 16'd58862;
lutrom[1455] = 16'd58884;
lutrom[1456] = 16'd58906;
lutrom[1457] = 16'd58928;
lutrom[1458] = 16'd58950;
lutrom[1459] = 16'd58972;
lutrom[1460] = 16'd58993;
lutrom[1461] = 16'd59015;
lutrom[1462] = 16'd59037;
lutrom[1463] = 16'd59059;
lutrom[1464] = 16'd59081;
lutrom[1465] = 16'd59103;
lutrom[1466] = 16'd59124;
lutrom[1467] = 16'd59146;
lutrom[1468] = 16'd59168;
lutrom[1469] = 16'd59189;
lutrom[1470] = 16'd59211;
lutrom[1471] = 16'd59232;
lutrom[1472] = 16'd59254;
lutrom[1473] = 16'd59275;
lutrom[1474] = 16'd59297;
lutrom[1475] = 16'd59318;
lutrom[1476] = 16'd59339;
lutrom[1477] = 16'd59361;
lutrom[1478] = 16'd59382;
lutrom[1479] = 16'd59403;
lutrom[1480] = 16'd59424;
lutrom[1481] = 16'd59446;
lutrom[1482] = 16'd59467;
lutrom[1483] = 16'd59488;
lutrom[1484] = 16'd59509;
lutrom[1485] = 16'd59530;
lutrom[1486] = 16'd59551;
lutrom[1487] = 16'd59572;
lutrom[1488] = 16'd59593;
lutrom[1489] = 16'd59614;
lutrom[1490] = 16'd59635;
lutrom[1491] = 16'd59655;
lutrom[1492] = 16'd59676;
lutrom[1493] = 16'd59697;
lutrom[1494] = 16'd59718;
lutrom[1495] = 16'd59738;
lutrom[1496] = 16'd59759;
lutrom[1497] = 16'd59780;
lutrom[1498] = 16'd59800;
lutrom[1499] = 16'd59821;
lutrom[1500] = 16'd59841;
lutrom[1501] = 16'd59862;
lutrom[1502] = 16'd59882;
lutrom[1503] = 16'd59903;
lutrom[1504] = 16'd59923;
lutrom[1505] = 16'd59943;
lutrom[1506] = 16'd59964;
lutrom[1507] = 16'd59984;
lutrom[1508] = 16'd60004;
lutrom[1509] = 16'd60024;
lutrom[1510] = 16'd60044;
lutrom[1511] = 16'd60065;
lutrom[1512] = 16'd60085;
lutrom[1513] = 16'd60105;
lutrom[1514] = 16'd60125;
lutrom[1515] = 16'd60145;
lutrom[1516] = 16'd60165;
lutrom[1517] = 16'd60185;
lutrom[1518] = 16'd60204;
lutrom[1519] = 16'd60224;
lutrom[1520] = 16'd60244;
lutrom[1521] = 16'd60264;
lutrom[1522] = 16'd60284;
lutrom[1523] = 16'd60303;
lutrom[1524] = 16'd60323;
lutrom[1525] = 16'd60343;
lutrom[1526] = 16'd60362;
lutrom[1527] = 16'd60382;
lutrom[1528] = 16'd60401;
lutrom[1529] = 16'd60421;
lutrom[1530] = 16'd60440;
lutrom[1531] = 16'd60460;
lutrom[1532] = 16'd60479;
lutrom[1533] = 16'd60498;
lutrom[1534] = 16'd60518;
lutrom[1535] = 16'd60537;
lutrom[1536] = 16'd60556;
lutrom[1537] = 16'd60575;
lutrom[1538] = 16'd60594;
lutrom[1539] = 16'd60614;
lutrom[1540] = 16'd60633;
lutrom[1541] = 16'd60652;
lutrom[1542] = 16'd60671;
lutrom[1543] = 16'd60690;
lutrom[1544] = 16'd60709;
lutrom[1545] = 16'd60728;
lutrom[1546] = 16'd60746;
lutrom[1547] = 16'd60765;
lutrom[1548] = 16'd60784;
lutrom[1549] = 16'd60803;
lutrom[1550] = 16'd60822;
lutrom[1551] = 16'd60840;
lutrom[1552] = 16'd60859;
lutrom[1553] = 16'd60878;
lutrom[1554] = 16'd60896;
lutrom[1555] = 16'd60915;
lutrom[1556] = 16'd60933;
lutrom[1557] = 16'd60952;
lutrom[1558] = 16'd60970;
lutrom[1559] = 16'd60989;
lutrom[1560] = 16'd61007;
lutrom[1561] = 16'd61025;
lutrom[1562] = 16'd61044;
lutrom[1563] = 16'd61062;
lutrom[1564] = 16'd61080;
lutrom[1565] = 16'd61098;
lutrom[1566] = 16'd61117;
lutrom[1567] = 16'd61135;
lutrom[1568] = 16'd61153;
lutrom[1569] = 16'd61171;
lutrom[1570] = 16'd61189;
lutrom[1571] = 16'd61207;
lutrom[1572] = 16'd61225;
lutrom[1573] = 16'd61243;
lutrom[1574] = 16'd61261;
lutrom[1575] = 16'd61278;
lutrom[1576] = 16'd61296;
lutrom[1577] = 16'd61314;
lutrom[1578] = 16'd61332;
lutrom[1579] = 16'd61349;
lutrom[1580] = 16'd61367;
lutrom[1581] = 16'd61385;
lutrom[1582] = 16'd61402;
lutrom[1583] = 16'd61420;
lutrom[1584] = 16'd61437;
lutrom[1585] = 16'd61455;
lutrom[1586] = 16'd61472;
lutrom[1587] = 16'd61490;
lutrom[1588] = 16'd61507;
lutrom[1589] = 16'd61524;
lutrom[1590] = 16'd61542;
lutrom[1591] = 16'd61559;
lutrom[1592] = 16'd61576;
lutrom[1593] = 16'd61593;
lutrom[1594] = 16'd61610;
lutrom[1595] = 16'd61628;
lutrom[1596] = 16'd61645;
lutrom[1597] = 16'd61662;
lutrom[1598] = 16'd61679;
lutrom[1599] = 16'd61696;
lutrom[1600] = 16'd61713;
lutrom[1601] = 16'd61729;
lutrom[1602] = 16'd61746;
lutrom[1603] = 16'd61763;
lutrom[1604] = 16'd61780;
lutrom[1605] = 16'd61797;
lutrom[1606] = 16'd61813;
lutrom[1607] = 16'd61830;
lutrom[1608] = 16'd61847;
lutrom[1609] = 16'd61863;
lutrom[1610] = 16'd61880;
lutrom[1611] = 16'd61896;
lutrom[1612] = 16'd61913;
lutrom[1613] = 16'd61929;
lutrom[1614] = 16'd61946;
lutrom[1615] = 16'd61962;
lutrom[1616] = 16'd61979;
lutrom[1617] = 16'd61995;
lutrom[1618] = 16'd62011;
lutrom[1619] = 16'd62027;
lutrom[1620] = 16'd62044;
lutrom[1621] = 16'd62060;
lutrom[1622] = 16'd62076;
lutrom[1623] = 16'd62092;
lutrom[1624] = 16'd62108;
lutrom[1625] = 16'd62124;
lutrom[1626] = 16'd62140;
lutrom[1627] = 16'd62156;
lutrom[1628] = 16'd62172;
lutrom[1629] = 16'd62188;
lutrom[1630] = 16'd62204;
lutrom[1631] = 16'd62219;
lutrom[1632] = 16'd62235;
lutrom[1633] = 16'd62251;
lutrom[1634] = 16'd62267;
lutrom[1635] = 16'd62282;
lutrom[1636] = 16'd62298;
lutrom[1637] = 16'd62313;
lutrom[1638] = 16'd62329;
lutrom[1639] = 16'd62345;
lutrom[1640] = 16'd62360;
lutrom[1641] = 16'd62375;
lutrom[1642] = 16'd62391;
lutrom[1643] = 16'd62406;
lutrom[1644] = 16'd62422;
lutrom[1645] = 16'd62437;
lutrom[1646] = 16'd62452;
lutrom[1647] = 16'd62467;
lutrom[1648] = 16'd62482;
lutrom[1649] = 16'd62498;
lutrom[1650] = 16'd62513;
lutrom[1651] = 16'd62528;
lutrom[1652] = 16'd62543;
lutrom[1653] = 16'd62558;
lutrom[1654] = 16'd62573;
lutrom[1655] = 16'd62588;
lutrom[1656] = 16'd62603;
lutrom[1657] = 16'd62617;
lutrom[1658] = 16'd62632;
lutrom[1659] = 16'd62647;
lutrom[1660] = 16'd62662;
lutrom[1661] = 16'd62676;
lutrom[1662] = 16'd62691;
lutrom[1663] = 16'd62706;
lutrom[1664] = 16'd62720;
lutrom[1665] = 16'd62735;
lutrom[1666] = 16'd62749;
lutrom[1667] = 16'd62764;
lutrom[1668] = 16'd62778;
lutrom[1669] = 16'd62793;
lutrom[1670] = 16'd62807;
lutrom[1671] = 16'd62821;
lutrom[1672] = 16'd62836;
lutrom[1673] = 16'd62850;
lutrom[1674] = 16'd62864;
lutrom[1675] = 16'd62878;
lutrom[1676] = 16'd62893;
lutrom[1677] = 16'd62907;
lutrom[1678] = 16'd62921;
lutrom[1679] = 16'd62935;
lutrom[1680] = 16'd62949;
lutrom[1681] = 16'd62963;
lutrom[1682] = 16'd62977;
lutrom[1683] = 16'd62991;
lutrom[1684] = 16'd63004;
lutrom[1685] = 16'd63018;
lutrom[1686] = 16'd63032;
lutrom[1687] = 16'd63046;
lutrom[1688] = 16'd63059;
lutrom[1689] = 16'd63073;
lutrom[1690] = 16'd63087;
lutrom[1691] = 16'd63100;
lutrom[1692] = 16'd63114;
lutrom[1693] = 16'd63127;
lutrom[1694] = 16'd63141;
lutrom[1695] = 16'd63154;
lutrom[1696] = 16'd63168;
lutrom[1697] = 16'd63181;
lutrom[1698] = 16'd63194;
lutrom[1699] = 16'd63208;
lutrom[1700] = 16'd63221;
lutrom[1701] = 16'd63234;
lutrom[1702] = 16'd63247;
lutrom[1703] = 16'd63261;
lutrom[1704] = 16'd63274;
lutrom[1705] = 16'd63287;
lutrom[1706] = 16'd63300;
lutrom[1707] = 16'd63313;
lutrom[1708] = 16'd63326;
lutrom[1709] = 16'd63339;
lutrom[1710] = 16'd63352;
lutrom[1711] = 16'd63364;
lutrom[1712] = 16'd63377;
lutrom[1713] = 16'd63390;
lutrom[1714] = 16'd63403;
lutrom[1715] = 16'd63415;
lutrom[1716] = 16'd63428;
lutrom[1717] = 16'd63441;
lutrom[1718] = 16'd63453;
lutrom[1719] = 16'd63466;
lutrom[1720] = 16'd63478;
lutrom[1721] = 16'd63491;
lutrom[1722] = 16'd63503;
lutrom[1723] = 16'd63516;
lutrom[1724] = 16'd63528;
lutrom[1725] = 16'd63540;
lutrom[1726] = 16'd63553;
lutrom[1727] = 16'd63565;
lutrom[1728] = 16'd63577;
lutrom[1729] = 16'd63589;
lutrom[1730] = 16'd63601;
lutrom[1731] = 16'd63614;
lutrom[1732] = 16'd63626;
lutrom[1733] = 16'd63638;
lutrom[1734] = 16'd63650;
lutrom[1735] = 16'd63662;
lutrom[1736] = 16'd63673;
lutrom[1737] = 16'd63685;
lutrom[1738] = 16'd63697;
lutrom[1739] = 16'd63709;
lutrom[1740] = 16'd63721;
lutrom[1741] = 16'd63732;
lutrom[1742] = 16'd63744;
lutrom[1743] = 16'd63756;
lutrom[1744] = 16'd63767;
lutrom[1745] = 16'd63779;
lutrom[1746] = 16'd63791;
lutrom[1747] = 16'd63802;
lutrom[1748] = 16'd63814;
lutrom[1749] = 16'd63825;
lutrom[1750] = 16'd63836;
lutrom[1751] = 16'd63848;
lutrom[1752] = 16'd63859;
lutrom[1753] = 16'd63870;
lutrom[1754] = 16'd63881;
lutrom[1755] = 16'd63893;
lutrom[1756] = 16'd63904;
lutrom[1757] = 16'd63915;
lutrom[1758] = 16'd63926;
lutrom[1759] = 16'd63937;
lutrom[1760] = 16'd63948;
lutrom[1761] = 16'd63959;
lutrom[1762] = 16'd63970;
lutrom[1763] = 16'd63981;
lutrom[1764] = 16'd63992;
lutrom[1765] = 16'd64003;
lutrom[1766] = 16'd64013;
lutrom[1767] = 16'd64024;
lutrom[1768] = 16'd64035;
lutrom[1769] = 16'd64046;
lutrom[1770] = 16'd64056;
lutrom[1771] = 16'd64067;
lutrom[1772] = 16'd64077;
lutrom[1773] = 16'd64088;
lutrom[1774] = 16'd64098;
lutrom[1775] = 16'd64109;
lutrom[1776] = 16'd64119;
lutrom[1777] = 16'd64130;
lutrom[1778] = 16'd64140;
lutrom[1779] = 16'd64150;
lutrom[1780] = 16'd64160;
lutrom[1781] = 16'd64171;
lutrom[1782] = 16'd64181;
lutrom[1783] = 16'd64191;
lutrom[1784] = 16'd64201;
lutrom[1785] = 16'd64211;
lutrom[1786] = 16'd64221;
lutrom[1787] = 16'd64231;
lutrom[1788] = 16'd64241;
lutrom[1789] = 16'd64251;
lutrom[1790] = 16'd64261;
lutrom[1791] = 16'd64271;
lutrom[1792] = 16'd64281;
lutrom[1793] = 16'd64290;
lutrom[1794] = 16'd64300;
lutrom[1795] = 16'd64310;
lutrom[1796] = 16'd64320;
lutrom[1797] = 16'd64329;
lutrom[1798] = 16'd64339;
lutrom[1799] = 16'd64348;
lutrom[1800] = 16'd64358;
lutrom[1801] = 16'd64367;
lutrom[1802] = 16'd64377;
lutrom[1803] = 16'd64386;
lutrom[1804] = 16'd64395;
lutrom[1805] = 16'd64405;
lutrom[1806] = 16'd64414;
lutrom[1807] = 16'd64423;
lutrom[1808] = 16'd64432;
lutrom[1809] = 16'd64442;
lutrom[1810] = 16'd64451;
lutrom[1811] = 16'd64460;
lutrom[1812] = 16'd64469;
lutrom[1813] = 16'd64478;
lutrom[1814] = 16'd64487;
lutrom[1815] = 16'd64496;
lutrom[1816] = 16'd64505;
lutrom[1817] = 16'd64514;
lutrom[1818] = 16'd64522;
lutrom[1819] = 16'd64531;
lutrom[1820] = 16'd64540;
lutrom[1821] = 16'd64549;
lutrom[1822] = 16'd64557;
lutrom[1823] = 16'd64566;
lutrom[1824] = 16'd64574;
lutrom[1825] = 16'd64583;
lutrom[1826] = 16'd64592;
lutrom[1827] = 16'd64600;
lutrom[1828] = 16'd64608;
lutrom[1829] = 16'd64617;
lutrom[1830] = 16'd64625;
lutrom[1831] = 16'd64634;
lutrom[1832] = 16'd64642;
lutrom[1833] = 16'd64650;
lutrom[1834] = 16'd64658;
lutrom[1835] = 16'd64666;
lutrom[1836] = 16'd64675;
lutrom[1837] = 16'd64683;
lutrom[1838] = 16'd64691;
lutrom[1839] = 16'd64699;
lutrom[1840] = 16'd64707;
lutrom[1841] = 16'd64715;
lutrom[1842] = 16'd64723;
lutrom[1843] = 16'd64731;
lutrom[1844] = 16'd64738;
lutrom[1845] = 16'd64746;
lutrom[1846] = 16'd64754;
lutrom[1847] = 16'd64762;
lutrom[1848] = 16'd64769;
lutrom[1849] = 16'd64777;
lutrom[1850] = 16'd64785;
lutrom[1851] = 16'd64792;
lutrom[1852] = 16'd64800;
lutrom[1853] = 16'd64807;
lutrom[1854] = 16'd64815;
lutrom[1855] = 16'd64822;
lutrom[1856] = 16'd64829;
lutrom[1857] = 16'd64837;
lutrom[1858] = 16'd64844;
lutrom[1859] = 16'd64851;
lutrom[1860] = 16'd64858;
lutrom[1861] = 16'd64866;
lutrom[1862] = 16'd64873;
lutrom[1863] = 16'd64880;
lutrom[1864] = 16'd64887;
lutrom[1865] = 16'd64894;
lutrom[1866] = 16'd64901;
lutrom[1867] = 16'd64908;
lutrom[1868] = 16'd64915;
lutrom[1869] = 16'd64922;
lutrom[1870] = 16'd64929;
lutrom[1871] = 16'd64935;
lutrom[1872] = 16'd64942;
lutrom[1873] = 16'd64949;
lutrom[1874] = 16'd64956;
lutrom[1875] = 16'd64962;
lutrom[1876] = 16'd64969;
lutrom[1877] = 16'd64975;
lutrom[1878] = 16'd64982;
lutrom[1879] = 16'd64988;
lutrom[1880] = 16'd64995;
lutrom[1881] = 16'd65001;
lutrom[1882] = 16'd65008;
lutrom[1883] = 16'd65014;
lutrom[1884] = 16'd65020;
lutrom[1885] = 16'd65027;
lutrom[1886] = 16'd65033;
lutrom[1887] = 16'd65039;
lutrom[1888] = 16'd65045;
lutrom[1889] = 16'd65051;
lutrom[1890] = 16'd65057;
lutrom[1891] = 16'd65063;
lutrom[1892] = 16'd65069;
lutrom[1893] = 16'd65075;
lutrom[1894] = 16'd65081;
lutrom[1895] = 16'd65087;
lutrom[1896] = 16'd65093;
lutrom[1897] = 16'd65099;
lutrom[1898] = 16'd65105;
lutrom[1899] = 16'd65110;
lutrom[1900] = 16'd65116;
lutrom[1901] = 16'd65122;
lutrom[1902] = 16'd65127;
lutrom[1903] = 16'd65133;
lutrom[1904] = 16'd65138;
lutrom[1905] = 16'd65144;
lutrom[1906] = 16'd65149;
lutrom[1907] = 16'd65155;
lutrom[1908] = 16'd65160;
lutrom[1909] = 16'd65166;
lutrom[1910] = 16'd65171;
lutrom[1911] = 16'd65176;
lutrom[1912] = 16'd65181;
lutrom[1913] = 16'd65187;
lutrom[1914] = 16'd65192;
lutrom[1915] = 16'd65197;
lutrom[1916] = 16'd65202;
lutrom[1917] = 16'd65207;
lutrom[1918] = 16'd65212;
lutrom[1919] = 16'd65217;
lutrom[1920] = 16'd65222;
lutrom[1921] = 16'd65227;
lutrom[1922] = 16'd65232;
lutrom[1923] = 16'd65236;
lutrom[1924] = 16'd65241;
lutrom[1925] = 16'd65246;
lutrom[1926] = 16'd65251;
lutrom[1927] = 16'd65255;
lutrom[1928] = 16'd65260;
lutrom[1929] = 16'd65265;
lutrom[1930] = 16'd65269;
lutrom[1931] = 16'd65274;
lutrom[1932] = 16'd65278;
lutrom[1933] = 16'd65282;
lutrom[1934] = 16'd65287;
lutrom[1935] = 16'd65291;
lutrom[1936] = 16'd65295;
lutrom[1937] = 16'd65300;
lutrom[1938] = 16'd65304;
lutrom[1939] = 16'd65308;
lutrom[1940] = 16'd65312;
lutrom[1941] = 16'd65316;
lutrom[1942] = 16'd65321;
lutrom[1943] = 16'd65325;
lutrom[1944] = 16'd65329;
lutrom[1945] = 16'd65333;
lutrom[1946] = 16'd65337;
lutrom[1947] = 16'd65340;
lutrom[1948] = 16'd65344;
lutrom[1949] = 16'd65348;
lutrom[1950] = 16'd65352;
lutrom[1951] = 16'd65356;
lutrom[1952] = 16'd65359;
lutrom[1953] = 16'd65363;
lutrom[1954] = 16'd65367;
lutrom[1955] = 16'd65370;
lutrom[1956] = 16'd65374;
lutrom[1957] = 16'd65377;
lutrom[1958] = 16'd65381;
lutrom[1959] = 16'd65384;
lutrom[1960] = 16'd65387;
lutrom[1961] = 16'd65391;
lutrom[1962] = 16'd65394;
lutrom[1963] = 16'd65397;
lutrom[1964] = 16'd65401;
lutrom[1965] = 16'd65404;
lutrom[1966] = 16'd65407;
lutrom[1967] = 16'd65410;
lutrom[1968] = 16'd65413;
lutrom[1969] = 16'd65416;
lutrom[1970] = 16'd65419;
lutrom[1971] = 16'd65422;
lutrom[1972] = 16'd65425;
lutrom[1973] = 16'd65428;
lutrom[1974] = 16'd65431;
lutrom[1975] = 16'd65434;
lutrom[1976] = 16'd65436;
lutrom[1977] = 16'd65439;
lutrom[1978] = 16'd65442;
lutrom[1979] = 16'd65445;
lutrom[1980] = 16'd65447;
lutrom[1981] = 16'd65450;
lutrom[1982] = 16'd65452;
lutrom[1983] = 16'd65455;
lutrom[1984] = 16'd65457;
lutrom[1985] = 16'd65460;
lutrom[1986] = 16'd65462;
lutrom[1987] = 16'd65464;
lutrom[1988] = 16'd65467;
lutrom[1989] = 16'd65469;
lutrom[1990] = 16'd65471;
lutrom[1991] = 16'd65473;
lutrom[1992] = 16'd65476;
lutrom[1993] = 16'd65478;
lutrom[1994] = 16'd65480;
lutrom[1995] = 16'd65482;
lutrom[1996] = 16'd65484;
lutrom[1997] = 16'd65486;
lutrom[1998] = 16'd65488;
lutrom[1999] = 16'd65490;
lutrom[2000] = 16'd65492;
lutrom[2001] = 16'd65493;
lutrom[2002] = 16'd65495;
lutrom[2003] = 16'd65497;
lutrom[2004] = 16'd65499;
lutrom[2005] = 16'd65500;
lutrom[2006] = 16'd65502;
lutrom[2007] = 16'd65503;
lutrom[2008] = 16'd65505;
lutrom[2009] = 16'd65506;
lutrom[2010] = 16'd65508;
lutrom[2011] = 16'd65509;
lutrom[2012] = 16'd65511;
lutrom[2013] = 16'd65512;
lutrom[2014] = 16'd65513;
lutrom[2015] = 16'd65515;
lutrom[2016] = 16'd65516;
lutrom[2017] = 16'd65517;
lutrom[2018] = 16'd65518;
lutrom[2019] = 16'd65519;
lutrom[2020] = 16'd65520;
lutrom[2021] = 16'd65521;
lutrom[2022] = 16'd65522;
lutrom[2023] = 16'd65523;
lutrom[2024] = 16'd65524;
lutrom[2025] = 16'd65525;
lutrom[2026] = 16'd65526;
lutrom[2027] = 16'd65527;
lutrom[2028] = 16'd65528;
lutrom[2029] = 16'd65528;
lutrom[2030] = 16'd65529;
lutrom[2031] = 16'd65530;
lutrom[2032] = 16'd65530;
lutrom[2033] = 16'd65531;
lutrom[2034] = 16'd65531;
lutrom[2035] = 16'd65532;
lutrom[2036] = 16'd65532;
lutrom[2037] = 16'd65533;
lutrom[2038] = 16'd65533;
lutrom[2039] = 16'd65534;
lutrom[2040] = 16'd65534;
lutrom[2041] = 16'd65534;
lutrom[2042] = 16'd65534;
lutrom[2043] = 16'd65535;
lutrom[2044] = 16'd65535;
lutrom[2045] = 16'd65535;
lutrom[2046] = 16'd65535;
lutrom[2047] = 16'd65535;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: Uart
// Project Name:
// Target Devices:
// Tool versions:
// Description: Interfaz UART
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_UART #(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)(//-- Single Precision*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
input wire clk,
input wire rst,
output wire TX
);
//local parameters
//localparam shift_region = 2'b00;
localparam N = 2; //2 para 32 bits, 3 para 64 bits
//localparam op = 1'b1;
localparam d = 0;
//signal declaration
wire ready_op;
wire max_tick_address;
wire max_tick_ch;
wire TX_DONE;
wire beg_op;
wire ack_op;
wire load_address;
wire enab_address;
wire enab_ch;
wire load_ch;
wire TX_START;
wire [W-1:0] data_cordic;
wire [W-1:0] data_cordic_out;
wire [7:0] TX_DATA;
wire [9:0] cont_address_sig;
wire [N-1:0] cont_ch;
wire OR;
assign OR = rst | ack_op;
FSM_test fsm_test_uart(
.clk(clk),
.rst(rst),
.ready_op(ready_op),
.max_tick_address(max_tick_address),
.max_tick_ch(max_tick_ch),
.TX_DONE(TX_DONE),
.beg_op(beg_op),
.ack_op(ack_op),
.load_address(load_address),
.enab_address(enab_address),
.enab_ch(enab_ch),
.load_ch(load_ch),
.TX_START(TX_START)
);
LINEALIZADOR_NORMALIZADOR L_N(
.CLK(clk), //SYSTEM CLOCK
.I(data_cordic), //VALOR DEL ARGUMENTO DEL LOGARITMO QUE SE DESEA CALCULAR I
//.V(data_cordic), //VALOR DEL ARGUMENTO DE V PARA CONVERSION FLOTANTE A FIJO
.RST_LN_FF(OR), //SYSTEM RESET
.Begin_FSM_I(beg_op), //INICIA FSM I
//.Begin_FSM_V(beg_op), //INICIA FSM V
.ACK_I(ready_op), //INDICA QUE EL CALCULO FUE REALIZADO I
//.ACK_V(ready_op), //INDICA QUE EL CALCULO FUE REALIZADO V
.RESULT_I(data_cordic_out) //RESULTADO FINAL I
//.RESULT_V(data_cordic_out) //RESULTADO FINAL V
);
Uart uart_mod(
.RST(rst),
.CLK(clk),
.TX_START(TX_START),
.TX_DATA(TX_DATA),
.TX(TX),
.TX_DONE(TX_DONE)
);
ROM_test #(.W(W)) rom_test_uart(
.address(cont_address_sig),
.data(data_cordic)
);
cont_test #(.W(10)) cont_address(
.clk(clk),
.rst(rst),
.load(load_address),
.enable(enab_address),
.d(d),
.max_tick(max_tick_address),
.q(cont_address_sig)
);
cont_test #(.W(N)) con_mux_data(
.clk(clk),
.rst(rst),
.load(load_ch),
.enable(enab_ch),
.d(d),
.max_tick(max_tick_ch),
.q(cont_ch)
);
generate
case(W)
32:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.data_out(TX_DATA)
);
end
64:
begin
Mux_8x1 mux_64_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.ch_4(data_cordic_out[39:32]),
.ch_5(data_cordic_out[47:40]),
.ch_6(data_cordic_out[55:48]),
.ch_7(data_cordic_out[63:56]),
.data_out(TX_DATA)
);
end
default:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.data_out(TX_DATA)
);
end
endcase
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_1_V
`define SKY130_FD_SC_HD__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_1_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file FIFO30x16.v when simulating
// the core, FIFO30x16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module FIFO30x16(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [30 : 0] din;
input wr_en;
input rd_en;
output [30 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_1 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(31),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(31),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/05 22:46:48
// Design Name:
// Module Name: flow_led
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module flow_led(
input clk_src,
input reset,
input [4:0] clk_sel, // select switch for clock signal
input M,
output reg [3:0] state
);
parameter LEN = 32; // length of binary counter(different types of clock signal)
parameter l0 = 0, // // state enums
l1 = 1,
l2 = 3,
l3 = 2,
l4 = 6,
l5 = 7,
l6 = 5,
l7 = 4,
l8 = 12,
l9 = 13,
l10 = 15,
l11 = 14,
l12 = 10,
l13 = 11,
l14 = 9,
l15 = 8;
reg [3:0] nextState;
wire clk; // truly clock signal
wire [(LEN-1):0] clk_group; // divided clock signal from clk, by binary counter
assign clk = clk_group[clk_sel];
binary_counter DIVIDER (.clk_src(clk_src), .reset(reset), .clk_group(clk_group));
always @(posedge clk or posedge reset) begin
if (reset) state <= l0;
else state <= nextState;
end
always @(M or state) begin
case (state)
l0: if (!M) nextState = l1;
else nextState = l15;
l1: if (!M) nextState = l2;
else nextState = l0;
l2: if (!M) nextState = l3;
else nextState = l1;
l3: if (!M) nextState = l4;
else nextState = l2;
l4: if (!M) nextState = l5;
else nextState = l3;
l5: if (!M) nextState = l6;
else nextState = l4;
l6: if (!M) nextState = l7;
else nextState = l5;
l7: if (!M) nextState = l8;
else nextState = l6;
l8: if (!M) nextState = l9;
else nextState = l7;
l9: if (!M) nextState = l10;
else nextState = l8;
l10: if (!M) nextState = l11;
else nextState = l9;
l11: if (!M) nextState = l12;
else nextState = l10;
l12: if (!M) nextState = l13;
else nextState = l11;
l13: if (!M) nextState = l14;
else nextState = l12;
l14: if (!M) nextState = l15;
else nextState = l13;
l15: if (!M) nextState = l0;
else nextState = l14;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:14:28 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1,
OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, DP_OP_15J76_123_4372_n11,
DP_OP_15J76_123_4372_n10, DP_OP_15J76_123_4372_n9,
DP_OP_15J76_123_4372_n8, DP_OP_15J76_123_4372_n7,
DP_OP_15J76_123_4372_n6, intadd_74_B_39_, intadd_74_B_38_,
intadd_74_B_37_, intadd_74_B_36_, intadd_74_B_35_, intadd_74_B_34_,
intadd_74_B_33_, intadd_74_B_32_, intadd_74_B_31_, intadd_74_B_30_,
intadd_74_B_29_, intadd_74_B_28_, intadd_74_B_27_, intadd_74_B_26_,
intadd_74_B_25_, intadd_74_B_24_, intadd_74_B_23_, intadd_74_B_22_,
intadd_74_B_21_, intadd_74_B_20_, intadd_74_B_19_, intadd_74_B_18_,
intadd_74_B_17_, intadd_74_B_16_, intadd_74_B_15_, intadd_74_B_14_,
intadd_74_B_13_, intadd_74_B_12_, intadd_74_B_11_, intadd_74_B_10_,
intadd_74_B_9_, intadd_74_B_8_, intadd_74_B_7_, intadd_74_B_6_,
intadd_74_B_5_, intadd_74_B_4_, intadd_74_B_3_, intadd_74_B_2_,
intadd_74_B_1_, intadd_74_B_0_, intadd_74_CI, intadd_74_SUM_39_,
intadd_74_SUM_38_, intadd_74_SUM_37_, intadd_74_SUM_36_,
intadd_74_SUM_35_, intadd_74_SUM_34_, intadd_74_SUM_33_,
intadd_74_SUM_32_, intadd_74_SUM_31_, intadd_74_SUM_30_,
intadd_74_SUM_29_, intadd_74_SUM_28_, intadd_74_SUM_27_,
intadd_74_SUM_26_, intadd_74_SUM_25_, intadd_74_SUM_24_,
intadd_74_SUM_23_, intadd_74_SUM_22_, intadd_74_SUM_21_,
intadd_74_SUM_20_, intadd_74_SUM_19_, intadd_74_SUM_18_,
intadd_74_SUM_17_, intadd_74_SUM_16_, intadd_74_SUM_15_,
intadd_74_SUM_14_, intadd_74_SUM_13_, intadd_74_SUM_12_,
intadd_74_SUM_11_, intadd_74_SUM_10_, intadd_74_SUM_9_,
intadd_74_SUM_8_, intadd_74_SUM_7_, intadd_74_SUM_6_,
intadd_74_SUM_5_, intadd_74_SUM_4_, intadd_74_SUM_3_,
intadd_74_SUM_2_, intadd_74_SUM_1_, intadd_74_SUM_0_, intadd_74_n40,
intadd_74_n39, intadd_74_n38, intadd_74_n37, intadd_74_n36,
intadd_74_n35, intadd_74_n34, intadd_74_n33, intadd_74_n32,
intadd_74_n31, intadd_74_n30, intadd_74_n29, intadd_74_n28,
intadd_74_n27, intadd_74_n26, intadd_74_n25, intadd_74_n24,
intadd_74_n23, intadd_74_n22, intadd_74_n21, intadd_74_n20,
intadd_74_n19, intadd_74_n18, intadd_74_n17, intadd_74_n16,
intadd_74_n15, intadd_74_n14, intadd_74_n13, intadd_74_n12,
intadd_74_n11, intadd_74_n10, intadd_74_n9, intadd_74_n8,
intadd_74_n7, intadd_74_n6, intadd_74_n5, intadd_74_n4, intadd_74_n3,
intadd_74_n2, intadd_74_n1, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2956,
n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966,
n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976,
n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986,
n2987, n2988, n2989, n2990, n2991, n2993, n2994, n2995, n2996, n2997,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017,
n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027,
n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037,
n3038, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048,
n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058,
n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068,
n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078,
n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088,
n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098,
n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108,
n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118,
n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178,
n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188,
n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198,
n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208,
n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218,
n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228,
n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248,
n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258,
n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268,
n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278,
n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288,
n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298,
n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308,
n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318,
n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328,
n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338,
n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348,
n3349, n3350, n3351, n3352, n3353, n3354;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [39:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n3307), .Q(
Shift_reg_FLAGS_7[1]) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1816), .CK(clk), .RN(n3318), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1751), .CK(clk), .RN(n3314), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3306), .CK(clk), .RN(n3313), .Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1669), .CK(clk), .RN(n3353), .QN(
n1851) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1666), .CK(clk), .RN(n3336), .QN(
n1837) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1664), .CK(clk), .RN(n3353), .QN(
n1848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1656), .CK(clk), .RN(n3344), .QN(
n1834) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n3353), .QN(
n1856) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1650), .CK(clk), .RN(n1832), .QN(
n1836) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1649), .CK(clk), .RN(n3309), .QN(
n1838) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1648), .CK(clk), .RN(n3314), .QN(
n1839) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1647), .CK(clk), .RN(n1830), .QN(
n1835) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1646), .CK(clk), .RN(n3311), .QN(
n1852) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1645), .CK(clk), .RN(n3309), .QN(
n1833) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1644), .CK(clk), .RN(n3308), .QN(
n1857) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1643), .CK(clk), .RN(n3312), .QN(
n1855) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1634), .CK(clk), .RN(n3349), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1676), .CK(clk), .RN(n3317), .QN(
n1850) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1671), .CK(clk), .RN(n3321), .QN(
n1849) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1624), .CK(clk), .RN(n3316),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1623), .CK(clk), .RN(n3319),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1622), .CK(clk), .RN(n3318),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1621), .CK(clk), .RN(n3336),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1620), .CK(clk), .RN(n3313),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1619), .CK(clk), .RN(n3341), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1618), .CK(clk), .RN(n3327), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1617), .CK(clk), .RN(n3326), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1616), .CK(clk), .RN(n1907), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1615), .CK(clk), .RN(n3326), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1614), .CK(clk), .RN(n3335), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1613), .CK(clk), .RN(n3318), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1612), .CK(clk), .RN(n1907), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1611), .CK(clk), .RN(n3326), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1610), .CK(clk), .RN(n3345), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1609), .CK(clk), .RN(n3332), .Q(
final_result_ieee[62]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n1907), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1607), .CK(clk), .RN(n3353), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1606), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1605), .CK(clk), .RN(n3347), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1604), .CK(clk), .RN(n3335), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1603), .CK(clk), .RN(n1832), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1602), .CK(clk), .RN(n3309), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n1907), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1600), .CK(clk), .RN(n3353), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1599), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1598), .CK(clk), .RN(n3316), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1597), .CK(clk), .RN(n3319), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1596), .CK(clk), .RN(n3318), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1595), .CK(clk), .RN(n3311), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1594), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1593), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1592), .CK(clk), .RN(n3321), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1591), .CK(clk), .RN(n3319), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1590), .CK(clk), .RN(n3320), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1589), .CK(clk), .RN(n3316), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1588), .CK(clk), .RN(n3312), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1587), .CK(clk), .RN(n1830), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1586), .CK(clk), .RN(n3308), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1585), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3321), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1583), .CK(clk), .RN(n3320), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1582), .CK(clk), .RN(n3316), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1581), .CK(clk), .RN(n3319), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1580), .CK(clk), .RN(n3311), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1579), .CK(clk), .RN(n3312), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1578), .CK(clk), .RN(n3322), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1577), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1576), .CK(clk), .RN(n3321), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1575), .CK(clk), .RN(n3320), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1574), .CK(clk), .RN(n3316), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1573), .CK(clk), .RN(n3319), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1572), .CK(clk), .RN(n3318), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1571), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1570), .CK(clk), .RN(n3317), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1569), .CK(clk), .RN(n3321), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1568), .CK(clk), .RN(n3320), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1567), .CK(clk), .RN(n3316), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1566), .CK(clk), .RN(n3319), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1565), .CK(clk), .RN(n3311), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1564), .CK(clk), .RN(n3312), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1563), .CK(clk), .RN(n1830), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1562), .CK(clk), .RN(n3313), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1561), .CK(clk), .RN(n3310), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1560), .CK(clk), .RN(n1830), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1559), .CK(clk), .RN(n3315), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1558), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1557), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1550), .CK(clk), .RN(n1830), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1549), .CK(clk), .RN(n3315), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1548), .CK(clk), .RN(n3310), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1547), .CK(clk), .RN(n3324), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1546), .CK(clk), .RN(n3323), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1545), .CK(clk), .RN(n1830), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1544), .CK(clk), .RN(n1831), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1543), .CK(clk), .RN(n3310), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1542), .CK(clk), .RN(n3313), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1541), .CK(clk), .RN(n3315), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1539), .CK(clk), .RN(n3324), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1538), .CK(clk), .RN(n3323), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1536), .CK(clk), .RN(n3308), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1535), .CK(clk), .RN(n1830), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1534), .CK(clk), .RN(n1831), .Q(
DMP_SFG[2]), .QN(n3301) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1533), .CK(clk), .RN(n3315), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1532), .CK(clk), .RN(n3310), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1530), .CK(clk), .RN(n3324), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1529), .CK(clk), .RN(n3323), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1527), .CK(clk), .RN(n3322), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1526), .CK(clk), .RN(n3325), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1524), .CK(clk), .RN(n3345), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1523), .CK(clk), .RN(n3337), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1521), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1520), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1518), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1517), .CK(clk), .RN(n3338), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1515), .CK(clk), .RN(n1908), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1514), .CK(clk), .RN(n1908), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1512), .CK(clk), .RN(n1908), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1511), .CK(clk), .RN(n3325), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1509), .CK(clk), .RN(n3316), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1508), .CK(clk), .RN(n3330), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1506), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1505), .CK(clk), .RN(n3354), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1504), .CK(clk), .RN(n3353), .Q(
DMP_SFG[12]), .QN(n3156) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1503), .CK(clk), .RN(n3325), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1502), .CK(clk), .RN(n3316), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1501), .CK(clk), .RN(n3328), .Q(
DMP_SFG[13]), .QN(n3155) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1500), .CK(clk), .RN(n3313), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1499), .CK(clk), .RN(n3328), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1498), .CK(clk), .RN(n1908), .Q(
DMP_SFG[14]), .QN(n3158) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1497), .CK(clk), .RN(n3330), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1496), .CK(clk), .RN(n3333), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1495), .CK(clk), .RN(n3329), .Q(
DMP_SFG[15]), .QN(n3157) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1494), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1493), .CK(clk), .RN(n3353), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1492), .CK(clk), .RN(n3337), .Q(
DMP_SFG[16]), .QN(n3160) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1491), .CK(clk), .RN(n3337), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1490), .CK(clk), .RN(n3335), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1489), .CK(clk), .RN(n3341), .Q(
DMP_SFG[17]), .QN(n3159) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1488), .CK(clk), .RN(n3332), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1487), .CK(clk), .RN(n3345), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n3347), .Q(
DMP_SFG[18]), .QN(n3162) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1485), .CK(clk), .RN(n3326), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1484), .CK(clk), .RN(n1907), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1483), .CK(clk), .RN(n3344), .Q(
DMP_SFG[19]), .QN(n3165) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1482), .CK(clk), .RN(n3317), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1481), .CK(clk), .RN(n3341), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1480), .CK(clk), .RN(n3332), .Q(
DMP_SFG[20]), .QN(n3164) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1479), .CK(clk), .RN(n3345), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1478), .CK(clk), .RN(n3354), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1477), .CK(clk), .RN(n3327), .Q(
DMP_SFG[21]), .QN(n3168) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1476), .CK(clk), .RN(n3320), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1475), .CK(clk), .RN(n3352), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1474), .CK(clk), .RN(n3327), .Q(
DMP_SFG[22]), .QN(n3167) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(n3348), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1472), .CK(clk), .RN(n3326), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1471), .CK(clk), .RN(n3349), .Q(
DMP_SFG[23]), .QN(n3171) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1470), .CK(clk), .RN(n1832), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1469), .CK(clk), .RN(n3323), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1468), .CK(clk), .RN(n3352), .Q(
DMP_SFG[24]), .QN(n3170) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1467), .CK(clk), .RN(n3336), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1466), .CK(clk), .RN(n3334), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n3339), .Q(
DMP_SFG[25]), .QN(n3174) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n3346), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1463), .CK(clk), .RN(n3308), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n3331), .Q(
DMP_SFG[26]), .QN(n3173) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n3346), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1460), .CK(clk), .RN(n3342), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1459), .CK(clk), .RN(n3338), .Q(
DMP_SFG[27]), .QN(n3175) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1458), .CK(clk), .RN(n3343), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1457), .CK(clk), .RN(n3308), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1456), .CK(clk), .RN(n3343), .Q(
DMP_SFG[28]), .QN(n3177) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1455), .CK(clk), .RN(n3331), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1454), .CK(clk), .RN(n3328), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1453), .CK(clk), .RN(n3310), .Q(
DMP_SFG[29]), .QN(n3176) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1452), .CK(clk), .RN(n1908), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1451), .CK(clk), .RN(n3325), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1450), .CK(clk), .RN(n1908), .Q(
DMP_SFG[30]), .QN(n3179) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1449), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1448), .CK(clk), .RN(n1908), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1447), .CK(clk), .RN(n3325), .Q(
DMP_SFG[31]), .QN(n3178) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1446), .CK(clk), .RN(n3338), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1445), .CK(clk), .RN(n3317), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1444), .CK(clk), .RN(n3328), .Q(
DMP_SFG[32]), .QN(n3181) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1443), .CK(clk), .RN(n1908), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1442), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1441), .CK(clk), .RN(n3329), .Q(
DMP_SFG[33]), .QN(n3180) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1440), .CK(clk), .RN(n3329), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1439), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1438), .CK(clk), .RN(n3329), .Q(
DMP_SFG[34]), .QN(n3183) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1437), .CK(clk), .RN(n3329), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1436), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1435), .CK(clk), .RN(n3329), .Q(
DMP_SFG[35]), .QN(n3182) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1434), .CK(clk), .RN(n3329), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1433), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1432), .CK(clk), .RN(n3329), .Q(
DMP_SFG[36]), .QN(n3206) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1431), .CK(clk), .RN(n3329), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1430), .CK(clk), .RN(n3337), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1429), .CK(clk), .RN(n3330), .Q(
DMP_SFG[37]), .QN(n3223) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1428), .CK(clk), .RN(n3337), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1427), .CK(clk), .RN(n3330), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1426), .CK(clk), .RN(n3337), .Q(
DMP_SFG[38]), .QN(n3222) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1425), .CK(clk), .RN(n3330), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1424), .CK(clk), .RN(n3337), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1423), .CK(clk), .RN(n3330), .Q(
DMP_SFG[39]), .QN(n3228) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1422), .CK(clk), .RN(n3337), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1421), .CK(clk), .RN(n3330), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1420), .CK(clk), .RN(n3337), .Q(
DMP_SFG[40]), .QN(n3227) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1419), .CK(clk), .RN(n3330), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1418), .CK(clk), .RN(n3326), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1417), .CK(clk), .RN(n3352), .Q(
DMP_SFG[41]), .QN(n3246) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1416), .CK(clk), .RN(n3335), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1415), .CK(clk), .RN(n3348), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1414), .CK(clk), .RN(n3349), .Q(
DMP_SFG[42]), .QN(n3245) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1413), .CK(clk), .RN(n3326), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1412), .CK(clk), .RN(n3327), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1411), .CK(clk), .RN(n3314), .Q(
DMP_SFG[43]), .QN(n3259) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1410), .CK(clk), .RN(n3352), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1409), .CK(clk), .RN(n1908), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1408), .CK(clk), .RN(n3348), .Q(
DMP_SFG[44]), .QN(n3286) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1407), .CK(clk), .RN(n3347), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1406), .CK(clk), .RN(n3320), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1405), .CK(clk), .RN(n3342), .Q(
DMP_SFG[45]), .QN(n3285) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1404), .CK(clk), .RN(n3345), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1403), .CK(clk), .RN(n3346), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1402), .CK(clk), .RN(n3342), .Q(
DMP_SFG[46]), .QN(n3294) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1401), .CK(clk), .RN(n3334), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1400), .CK(clk), .RN(n3352), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1399), .CK(clk), .RN(n3331), .Q(
DMP_SFG[47]), .QN(n3293) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1398), .CK(clk), .RN(n3334), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1397), .CK(clk), .RN(n3328), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1396), .CK(clk), .RN(n3334), .Q(
DMP_SFG[48]), .QN(n3297) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1395), .CK(clk), .RN(n3310), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1394), .CK(clk), .RN(n3345), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1393), .CK(clk), .RN(n3326), .Q(
DMP_SFG[49]), .QN(n3296) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1392), .CK(clk), .RN(n1907), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1391), .CK(clk), .RN(n3308), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1390), .CK(clk), .RN(n3327), .Q(
DMP_SFG[50]), .QN(n3304) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1389), .CK(clk), .RN(n3341), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1388), .CK(clk), .RN(n3336), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1387), .CK(clk), .RN(n3345), .Q(
DMP_SFG[51]), .QN(n3303) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1386), .CK(clk), .RN(n3354), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1385), .CK(clk), .RN(n1907), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1384), .CK(clk), .RN(n3313), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1383), .CK(clk), .RN(n3336), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1381), .CK(clk), .RN(n3333), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1380), .CK(clk), .RN(n3333), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1379), .CK(clk), .RN(n3333), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1378), .CK(clk), .RN(n3333), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1376), .CK(clk), .RN(n3333), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1375), .CK(clk), .RN(n3333), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1374), .CK(clk), .RN(n3333), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1373), .CK(clk), .RN(n3333), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1371), .CK(clk), .RN(n3333), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1370), .CK(clk), .RN(n3333), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1369), .CK(clk), .RN(n3333), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1368), .CK(clk), .RN(n3333), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1366), .CK(clk), .RN(n3316), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1365), .CK(clk), .RN(n3334), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1364), .CK(clk), .RN(n3346), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1363), .CK(clk), .RN(n3331), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1361), .CK(clk), .RN(n3339), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1360), .CK(clk), .RN(n3342), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1359), .CK(clk), .RN(n3334), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1358), .CK(clk), .RN(n3334), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1356), .CK(clk), .RN(n3313), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3343), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1354), .CK(clk), .RN(n3339), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1353), .CK(clk), .RN(n3315), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1351), .CK(clk), .RN(n3325), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1350), .CK(clk), .RN(n3328), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1349), .CK(clk), .RN(n3352), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1348), .CK(clk), .RN(n3333), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1346), .CK(clk), .RN(n3323), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1345), .CK(clk), .RN(n3315), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1344), .CK(clk), .RN(n3308), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(n3345), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1341), .CK(clk), .RN(n3328), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1340), .CK(clk), .RN(n3347), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1339), .CK(clk), .RN(n3328), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1338), .CK(clk), .RN(n1908), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1336), .CK(clk), .RN(n3354), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1335), .CK(clk), .RN(n3335), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1334), .CK(clk), .RN(n1832), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1333), .CK(clk), .RN(n1832), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1331), .CK(clk), .RN(n1908), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1329), .CK(clk), .RN(n3340), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1327), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1323), .CK(clk), .RN(n3335), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1321), .CK(clk), .RN(n3344), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1319), .CK(clk), .RN(n3352), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1317), .CK(clk), .RN(n3353), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1315), .CK(clk), .RN(n3348), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1313), .CK(clk), .RN(n3348), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3331), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1309), .CK(clk), .RN(n3346), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1307), .CK(clk), .RN(n3343), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1305), .CK(clk), .RN(n3343), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1303), .CK(clk), .RN(n3323), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1301), .CK(clk), .RN(n3324), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1299), .CK(clk), .RN(n3337), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1297), .CK(clk), .RN(n3330), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1295), .CK(clk), .RN(n3337), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1293), .CK(clk), .RN(n3330), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1291), .CK(clk), .RN(n3337), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1289), .CK(clk), .RN(n3330), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1287), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1285), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1283), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1281), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1279), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1277), .CK(clk), .RN(n3338), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1275), .CK(clk), .RN(n3339), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1273), .CK(clk), .RN(n3346), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1271), .CK(clk), .RN(n3334), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1269), .CK(clk), .RN(n3332), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1267), .CK(clk), .RN(n3341), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3316), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1263), .CK(clk), .RN(n3340), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1261), .CK(clk), .RN(n3353), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1259), .CK(clk), .RN(n3354), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1257), .CK(clk), .RN(n3335), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1255), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1253), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1251), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1249), .CK(clk), .RN(n3340), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1247), .CK(clk), .RN(n3335), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1245), .CK(clk), .RN(n1832), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1243), .CK(clk), .RN(n3335), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1241), .CK(clk), .RN(n1908), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1239), .CK(clk), .RN(n3347), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1237), .CK(clk), .RN(n3332), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1235), .CK(clk), .RN(n3345), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1233), .CK(clk), .RN(n3349), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1231), .CK(clk), .RN(n1907), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1229), .CK(clk), .RN(n3309), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1221), .CK(clk), .RN(n3316), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1220), .CK(clk), .RN(n3312), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1219), .CK(clk), .RN(n3308), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1218), .CK(clk), .RN(n3317), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1217), .CK(clk), .RN(n3321), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1216), .CK(clk), .RN(n3320), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1215), .CK(clk), .RN(n3340),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1214), .CK(clk), .RN(n3354), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1213), .CK(clk), .RN(n3353), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1212), .CK(clk), .RN(n1908), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1210), .CK(clk), .RN(n3347), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1209), .CK(clk), .RN(n3354), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1208), .CK(clk), .RN(n3353), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1207), .CK(clk), .RN(n3354), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(n3340),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1205), .CK(clk), .RN(n3354), .Q(
final_result_ieee[63]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1170), .CK(clk), .RN(n3342),
.QN(n1840) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1161), .CK(clk), .RN(n3336),
.Q(LZD_output_NRM2_EW[5]), .QN(n3229) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1158), .CK(clk), .RN(n3332),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1155), .CK(clk), .RN(n3336),
.Q(LZD_output_NRM2_EW[4]), .QN(n3224) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1151), .CK(clk), .RN(n3345),
.Q(LZD_output_NRM2_EW[1]), .QN(n3208) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1148), .CK(clk), .RN(n1907),
.Q(LZD_output_NRM2_EW[3]), .QN(n3225) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1137), .CK(clk), .RN(n3347),
.Q(LZD_output_NRM2_EW[2]), .QN(n3207) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1134), .CK(clk), .RN(n3314), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1133), .CK(clk), .RN(n3354), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1128), .CK(clk), .RN(n1907), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1127), .CK(clk), .RN(n3311), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1126), .CK(clk), .RN(n3349), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1125), .CK(clk), .RN(n3342), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1124), .CK(clk), .RN(n3342), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1123), .CK(clk), .RN(n3331), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1121), .CK(clk), .RN(n3343), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1120), .CK(clk), .RN(n3331), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1119), .CK(clk), .RN(n3339), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1118), .CK(clk), .RN(n3343), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1117), .CK(clk), .RN(n3339), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1116), .CK(clk), .RN(n3334), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1115), .CK(clk), .RN(n3346), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(n3339), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1113), .CK(clk), .RN(n3352), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1112), .CK(clk), .RN(n1832), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1111), .CK(clk), .RN(n3348), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1110), .CK(clk), .RN(n3354), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1109), .CK(clk), .RN(n3347), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1108), .CK(clk), .RN(n1908), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1107), .CK(clk), .RN(n3308), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3352), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1105), .CK(clk), .RN(n3327), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1104), .CK(clk), .RN(n3348), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1103), .CK(clk), .RN(n3349), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1102), .CK(clk), .RN(n3349), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1101), .CK(clk), .RN(n3327), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1100), .CK(clk), .RN(n3313), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1099), .CK(clk), .RN(n3352), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1098), .CK(clk), .RN(n3336), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1097), .CK(clk), .RN(n3348), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1096), .CK(clk), .RN(n3347), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1095), .CK(clk), .RN(n3354), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1094), .CK(clk), .RN(n3336), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1093), .CK(clk), .RN(n3309), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1092), .CK(clk), .RN(n3352), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1091), .CK(clk), .RN(n3335), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1090), .CK(clk), .RN(n3348), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n3348), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1088), .CK(clk), .RN(n3354), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1087), .CK(clk), .RN(n3347), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1086), .CK(clk), .RN(n3336), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1085), .CK(clk), .RN(n3315), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1084), .CK(clk), .RN(n3352), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1083), .CK(clk), .RN(n3335), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1082), .CK(clk), .RN(n3348), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n3326), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1080), .CK(clk), .RN(n3326), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1079), .CK(clk), .RN(n3335), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1078), .CK(clk), .RN(n3310), .Q(
final_result_ieee[51]) );
CMPR32X2TS DP_OP_15J76_123_4372_U8 ( .A(n3224), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J76_123_4372_n8), .CO(DP_OP_15J76_123_4372_n7), .S(
exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS intadd_74_U41 ( .A(n3156), .B(intadd_74_B_0_), .C(intadd_74_CI),
.CO(intadd_74_n40), .S(intadd_74_SUM_0_) );
CMPR32X2TS intadd_74_U40 ( .A(n3155), .B(intadd_74_B_1_), .C(intadd_74_n40),
.CO(intadd_74_n39), .S(intadd_74_SUM_1_) );
CMPR32X2TS intadd_74_U39 ( .A(n3158), .B(intadd_74_B_2_), .C(intadd_74_n39),
.CO(intadd_74_n38), .S(intadd_74_SUM_2_) );
CMPR32X2TS intadd_74_U38 ( .A(n3157), .B(intadd_74_B_3_), .C(intadd_74_n38),
.CO(intadd_74_n37), .S(intadd_74_SUM_3_) );
CMPR32X2TS intadd_74_U37 ( .A(n3160), .B(intadd_74_B_4_), .C(intadd_74_n37),
.CO(intadd_74_n36), .S(intadd_74_SUM_4_) );
CMPR32X2TS intadd_74_U36 ( .A(n3159), .B(intadd_74_B_5_), .C(intadd_74_n36),
.CO(intadd_74_n35), .S(intadd_74_SUM_5_) );
CMPR32X2TS intadd_74_U35 ( .A(n3162), .B(intadd_74_B_6_), .C(intadd_74_n35),
.CO(intadd_74_n34), .S(intadd_74_SUM_6_) );
CMPR32X2TS intadd_74_U34 ( .A(n3165), .B(intadd_74_B_7_), .C(intadd_74_n34),
.CO(intadd_74_n33), .S(intadd_74_SUM_7_) );
CMPR32X2TS intadd_74_U33 ( .A(n3164), .B(intadd_74_B_8_), .C(intadd_74_n33),
.CO(intadd_74_n32), .S(intadd_74_SUM_8_) );
CMPR32X2TS intadd_74_U32 ( .A(n3168), .B(intadd_74_B_9_), .C(intadd_74_n32),
.CO(intadd_74_n31), .S(intadd_74_SUM_9_) );
CMPR32X2TS intadd_74_U31 ( .A(n3167), .B(intadd_74_B_10_), .C(intadd_74_n31),
.CO(intadd_74_n30), .S(intadd_74_SUM_10_) );
CMPR32X2TS intadd_74_U30 ( .A(n3171), .B(intadd_74_B_11_), .C(intadd_74_n30),
.CO(intadd_74_n29), .S(intadd_74_SUM_11_) );
CMPR32X2TS intadd_74_U29 ( .A(n3170), .B(intadd_74_B_12_), .C(intadd_74_n29),
.CO(intadd_74_n28), .S(intadd_74_SUM_12_) );
CMPR32X2TS intadd_74_U28 ( .A(n3174), .B(intadd_74_B_13_), .C(intadd_74_n28),
.CO(intadd_74_n27), .S(intadd_74_SUM_13_) );
CMPR32X2TS intadd_74_U27 ( .A(n3173), .B(intadd_74_B_14_), .C(intadd_74_n27),
.CO(intadd_74_n26), .S(intadd_74_SUM_14_) );
CMPR32X2TS intadd_74_U26 ( .A(n3175), .B(intadd_74_B_15_), .C(intadd_74_n26),
.CO(intadd_74_n25), .S(intadd_74_SUM_15_) );
CMPR32X2TS intadd_74_U25 ( .A(n3177), .B(intadd_74_B_16_), .C(intadd_74_n25),
.CO(intadd_74_n24), .S(intadd_74_SUM_16_) );
CMPR32X2TS intadd_74_U24 ( .A(n3176), .B(intadd_74_B_17_), .C(intadd_74_n24),
.CO(intadd_74_n23), .S(intadd_74_SUM_17_) );
CMPR32X2TS intadd_74_U23 ( .A(n3179), .B(intadd_74_B_18_), .C(intadd_74_n23),
.CO(intadd_74_n22), .S(intadd_74_SUM_18_) );
CMPR32X2TS intadd_74_U22 ( .A(n3178), .B(intadd_74_B_19_), .C(intadd_74_n22),
.CO(intadd_74_n21), .S(intadd_74_SUM_19_) );
CMPR32X2TS intadd_74_U21 ( .A(n3181), .B(intadd_74_B_20_), .C(intadd_74_n21),
.CO(intadd_74_n20), .S(intadd_74_SUM_20_) );
CMPR32X2TS intadd_74_U20 ( .A(n3180), .B(intadd_74_B_21_), .C(intadd_74_n20),
.CO(intadd_74_n19), .S(intadd_74_SUM_21_) );
CMPR32X2TS intadd_74_U19 ( .A(n3183), .B(intadd_74_B_22_), .C(intadd_74_n19),
.CO(intadd_74_n18), .S(intadd_74_SUM_22_) );
CMPR32X2TS intadd_74_U18 ( .A(n3182), .B(intadd_74_B_23_), .C(intadd_74_n18),
.CO(intadd_74_n17), .S(intadd_74_SUM_23_) );
CMPR32X2TS intadd_74_U17 ( .A(n3206), .B(intadd_74_B_24_), .C(intadd_74_n17),
.CO(intadd_74_n16), .S(intadd_74_SUM_24_) );
CMPR32X2TS intadd_74_U16 ( .A(n3223), .B(intadd_74_B_25_), .C(intadd_74_n16),
.CO(intadd_74_n15), .S(intadd_74_SUM_25_) );
CMPR32X2TS intadd_74_U15 ( .A(n3222), .B(intadd_74_B_26_), .C(intadd_74_n15),
.CO(intadd_74_n14), .S(intadd_74_SUM_26_) );
CMPR32X2TS intadd_74_U14 ( .A(n3228), .B(intadd_74_B_27_), .C(intadd_74_n14),
.CO(intadd_74_n13), .S(intadd_74_SUM_27_) );
CMPR32X2TS intadd_74_U13 ( .A(n3227), .B(intadd_74_B_28_), .C(intadd_74_n13),
.CO(intadd_74_n12), .S(intadd_74_SUM_28_) );
CMPR32X2TS intadd_74_U12 ( .A(n3246), .B(intadd_74_B_29_), .C(intadd_74_n12),
.CO(intadd_74_n11), .S(intadd_74_SUM_29_) );
CMPR32X2TS intadd_74_U11 ( .A(n3245), .B(intadd_74_B_30_), .C(intadd_74_n11),
.CO(intadd_74_n10), .S(intadd_74_SUM_30_) );
CMPR32X2TS intadd_74_U10 ( .A(n3259), .B(intadd_74_B_31_), .C(intadd_74_n10),
.CO(intadd_74_n9), .S(intadd_74_SUM_31_) );
CMPR32X2TS intadd_74_U9 ( .A(n3286), .B(intadd_74_B_32_), .C(intadd_74_n9),
.CO(intadd_74_n8), .S(intadd_74_SUM_32_) );
CMPR32X2TS intadd_74_U8 ( .A(n3285), .B(intadd_74_B_33_), .C(intadd_74_n8),
.CO(intadd_74_n7), .S(intadd_74_SUM_33_) );
CMPR32X2TS intadd_74_U7 ( .A(n3294), .B(intadd_74_B_34_), .C(intadd_74_n7),
.CO(intadd_74_n6), .S(intadd_74_SUM_34_) );
CMPR32X2TS intadd_74_U6 ( .A(n3293), .B(intadd_74_B_35_), .C(intadd_74_n6),
.CO(intadd_74_n5), .S(intadd_74_SUM_35_) );
CMPR32X2TS intadd_74_U5 ( .A(n3297), .B(intadd_74_B_36_), .C(intadd_74_n5),
.CO(intadd_74_n4), .S(intadd_74_SUM_36_) );
CMPR32X2TS intadd_74_U4 ( .A(n3296), .B(intadd_74_B_37_), .C(intadd_74_n4),
.CO(intadd_74_n3), .S(intadd_74_SUM_37_) );
CMPR32X2TS intadd_74_U3 ( .A(n3304), .B(intadd_74_B_38_), .C(intadd_74_n3),
.CO(intadd_74_n2), .S(intadd_74_SUM_38_) );
CMPR32X2TS intadd_74_U2 ( .A(n3303), .B(intadd_74_B_39_), .C(intadd_74_n2),
.CO(intadd_74_n1), .S(intadd_74_SUM_39_) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1760), .CK(clk), .RN(n3312),
.Q(intDX_EWSW[55]), .QN(n3299) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1762), .CK(clk), .RN(n3319),
.Q(intDX_EWSW[53]), .QN(n3298) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1204), .CK(clk), .RN(n3326), .Q(
Raw_mant_NRM_SWR[14]), .QN(n3295) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1332), .CK(clk), .RN(n3332),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3292) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1531), .CK(clk), .RN(n3323), .Q(
DMP_SFG[3]), .QN(n3290) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1194), .CK(clk), .RN(n3325), .Q(
Raw_mant_NRM_SWR[24]), .QN(n3289) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1135), .CK(clk), .RN(n1831), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3288) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1711), .CK(clk), .RN(n3307),
.Q(intDY_EWSW[38]), .QN(n3287) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1337), .CK(clk), .RN(n3341), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3284) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1667), .CK(clk), .RN(n1832), .Q(
Data_array_SWR[24]), .QN(n3283) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1668), .CK(clk), .RN(n3327), .Q(
Data_array_SWR[25]), .QN(n3282) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1697), .CK(clk), .RN(n3324),
.Q(intDY_EWSW[52]), .QN(n3281) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1655), .CK(clk), .RN(n3353), .Q(
Data_array_SWR[15]), .QN(n3280) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1742), .CK(clk), .RN(n3313),
.Q(intDY_EWSW[7]), .QN(n3279) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1719), .CK(clk), .RN(n3324),
.Q(intDY_EWSW[30]), .QN(n3278) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1727), .CK(clk), .RN(n3310),
.Q(intDY_EWSW[22]), .QN(n3277) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1735), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[14]), .QN(n3276) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1748), .CK(clk), .RN(n3311),
.Q(intDY_EWSW[1]), .QN(n3275) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1687), .CK(clk), .RN(n3321),
.Q(intDY_EWSW[62]), .QN(n3274) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1513), .CK(clk), .RN(n1908), .Q(
DMP_SFG[9]), .QN(n3273) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1685), .CK(clk), .RN(n3353), .Q(
Data_array_SWR[39]), .QN(n3272) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1684), .CK(clk), .RN(n1907), .Q(
Data_array_SWR[38]), .QN(n3271) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1682), .CK(clk), .RN(n3315), .Q(
Data_array_SWR[36]), .QN(n3270) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1699), .CK(clk), .RN(n1831),
.Q(intDY_EWSW[50]), .QN(n3269) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1703), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[46]), .QN(n3268) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1705), .CK(clk), .RN(n3310),
.Q(intDY_EWSW[44]), .QN(n3267) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1707), .CK(clk), .RN(n3308),
.Q(intDY_EWSW[42]), .QN(n3266) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1709), .CK(clk), .RN(n3309),
.Q(intDY_EWSW[40]), .QN(n3265) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1713), .CK(clk), .RN(n3314),
.Q(intDY_EWSW[36]), .QN(n3264) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1715), .CK(clk), .RN(n3312),
.Q(intDY_EWSW[34]), .QN(n3263) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1704), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[45]), .QN(n3262) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1710), .CK(clk), .RN(n3311),
.Q(intDY_EWSW[39]), .QN(n3261) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1712), .CK(clk), .RN(n3311),
.Q(intDY_EWSW[37]), .QN(n3260) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1342), .CK(clk), .RN(n3326), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3258) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1733), .CK(clk), .RN(n3311),
.Q(intDY_EWSW[16]), .QN(n3257) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1211), .CK(clk), .RN(n3326), .Q(
OP_FLAG_SFG), .QN(n3102) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1814), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[1]), .QN(n3256) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1688), .CK(clk), .RN(n3320),
.Q(intDY_EWSW[61]), .QN(n3255) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1691), .CK(clk), .RN(n3318),
.Q(intDY_EWSW[58]), .QN(n3254) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1689), .CK(clk), .RN(n3317),
.Q(intDY_EWSW[60]), .QN(n3253) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1823), .CK(clk), .RN(
n3322), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3252) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1700), .CK(clk), .RN(n3322),
.Q(intDY_EWSW[49]), .QN(n3251) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1692), .CK(clk), .RN(n3319),
.Q(intDY_EWSW[57]), .QN(n3250) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1744), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[5]), .QN(n3249) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1749), .CK(clk), .RN(n3307),
.Q(intDY_EWSW[0]), .QN(n3248) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1683), .CK(clk), .RN(n3326), .Q(
Data_array_SWR[37]), .QN(n3247) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1352), .CK(clk), .RN(n1907), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3244) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1347), .CK(clk), .RN(n3320), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3243) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1701), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[48]), .QN(n3242) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1717), .CK(clk), .RN(n3314),
.Q(intDY_EWSW[32]), .QN(n3241) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1721), .CK(clk), .RN(n3323),
.Q(intDY_EWSW[28]), .QN(n3240) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1723), .CK(clk), .RN(n3324),
.Q(intDY_EWSW[26]), .QN(n3239) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1725), .CK(clk), .RN(n3308),
.Q(intDY_EWSW[24]), .QN(n3238) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1729), .CK(clk), .RN(n3310),
.Q(intDY_EWSW[20]), .QN(n3237) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1731), .CK(clk), .RN(n3313),
.Q(intDY_EWSW[18]), .QN(n3236) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1737), .CK(clk), .RN(n3323),
.Q(intDY_EWSW[12]), .QN(n3235) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1747), .CK(clk), .RN(n3318),
.Q(intDY_EWSW[2]), .QN(n3234) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1728), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[21]), .QN(n3233) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1736), .CK(clk), .RN(n3310),
.Q(intDY_EWSW[13]), .QN(n3232) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1739), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[10]), .QN(n3231) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1740), .CK(clk), .RN(n3324),
.Q(intDY_EWSW[9]), .QN(n3230) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1756), .CK(clk), .RN(n3321),
.Q(intDX_EWSW[59]), .QN(n3226) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1807), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[8]), .QN(n3221) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1797), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[18]), .QN(n3220) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1789), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[26]), .QN(n3219) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1766), .CK(clk), .RN(n3323),
.Q(intDX_EWSW[49]), .QN(n3218) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1798), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[17]), .QN(n3217) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1794), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[21]), .QN(n3216) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1786), .CK(clk), .RN(n3322),
.Q(intDX_EWSW[29]), .QN(n3215) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1172), .CK(clk), .RN(n3331), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3214) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1793), .CK(clk), .RN(n3322),
.Q(intDX_EWSW[22]), .QN(n3213) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1795), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[20]), .QN(n3212) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1764), .CK(clk), .RN(n3316),
.Q(intDX_EWSW[51]), .QN(n3211) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1781), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[34]), .QN(n3210) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1773), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[42]), .QN(n3209) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1382), .CK(clk), .RN(n3323), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3205) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1758), .CK(clk), .RN(n3317),
.Q(intDX_EWSW[57]), .QN(n3204) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1790), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[25]), .QN(n3203) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1804), .CK(clk), .RN(n3308),
.Q(intDX_EWSW[11]), .QN(n3202) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1770), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[45]), .QN(n3201) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1629), .CK(clk), .RN(n3342),
.Q(shift_value_SHT2_EWR[3]), .QN(n3200) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1164), .CK(clk), .RN(n3339), .Q(
Raw_mant_NRM_SWR[54]), .QN(n3199) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1755), .CK(clk), .RN(n3320),
.Q(intDX_EWSW[60]), .QN(n3198) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n3313),
.Q(intDX_EWSW[13]), .QN(n3197) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1774), .CK(clk), .RN(n3310),
.Q(intDX_EWSW[41]), .QN(n3196) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1176), .CK(clk), .RN(n3339), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3195) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1779), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[36]), .QN(n3194) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n3325), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3193) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[14]), .QN(n3192) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1785), .CK(clk), .RN(n3312),
.Q(intDX_EWSW[30]), .QN(n3191) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1628), .CK(clk), .RN(n3321),
.Q(shift_value_SHT2_EWR[4]), .QN(n3190) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1803), .CK(clk), .RN(n3307),
.Q(intDX_EWSW[12]), .QN(n3189) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1787), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[28]), .QN(n3188) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1769), .CK(clk), .RN(n3308),
.Q(intDX_EWSW[46]), .QN(n3187) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1199), .CK(clk), .RN(n3325), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3186) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1782), .CK(clk), .RN(n3307),
.Q(intDX_EWSW[33]), .QN(n3185) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1812), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[3]), .QN(n3184) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1162), .CK(clk), .RN(n3342), .Q(
Raw_mant_NRM_SWR[13]), .QN(n3172) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1203), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[15]), .QN(n3169) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1201), .CK(clk), .RN(n3328), .Q(
Raw_mant_NRM_SWR[17]), .QN(n3166) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1197), .CK(clk), .RN(n3347), .Q(
Raw_mant_NRM_SWR[21]), .QN(n3163) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1193), .CK(clk), .RN(n1908), .Q(
Raw_mant_NRM_SWR[25]), .QN(n3161) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1177), .CK(clk), .RN(n3329), .Q(
Raw_mant_NRM_SWR[41]), .QN(n3154) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1175), .CK(clk), .RN(n3334), .Q(
Raw_mant_NRM_SWR[43]), .QN(n3153) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1169), .CK(clk), .RN(n3343), .Q(
Raw_mant_NRM_SWR[49]), .QN(n3152) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1552), .CK(clk), .RN(n1830), .Q(
DMP_EXP_EWSW[56]), .QN(n3151) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1761), .CK(clk), .RN(n3317),
.Q(intDX_EWSW[54]), .QN(n3150) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1553), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[55]), .QN(n3148) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1554), .CK(clk), .RN(n1831), .Q(
DMP_EXP_EWSW[54]), .QN(n3147) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1184), .CK(clk), .RN(n3342), .Q(
Raw_mant_NRM_SWR[34]), .QN(n3146) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1555), .CK(clk), .RN(n3323), .Q(
DMP_EXP_EWSW[53]), .QN(n3145) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1192), .CK(clk), .RN(n3325), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3144) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1743), .CK(clk), .RN(n3318),
.Q(intDY_EWSW[6]), .QN(n3143) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1718), .CK(clk), .RN(n3322),
.Q(intDY_EWSW[31]), .QN(n3142) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1726), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[23]), .QN(n3141) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1734), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[15]), .QN(n3140) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1706), .CK(clk), .RN(n1831),
.Q(intDY_EWSW[43]), .QN(n3139) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1708), .CK(clk), .RN(n3309),
.Q(intDY_EWSW[41]), .QN(n3138) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1714), .CK(clk), .RN(n3307),
.Q(intDY_EWSW[35]), .QN(n3137) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1716), .CK(clk), .RN(n1831),
.Q(intDY_EWSW[33]), .QN(n3136) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1698), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[51]), .QN(n3135) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1702), .CK(clk), .RN(n1830),
.Q(intDY_EWSW[47]), .QN(n3134) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1690), .CK(clk), .RN(n3316),
.Q(intDY_EWSW[59]), .QN(n3133) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1738), .CK(clk), .RN(n3315),
.Q(intDY_EWSW[11]), .QN(n3132) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1741), .CK(clk), .RN(n3323),
.Q(intDY_EWSW[8]), .QN(n3131) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1745), .CK(clk), .RN(n3309),
.Q(intDY_EWSW[4]), .QN(n3130) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1720), .CK(clk), .RN(n3313),
.Q(intDY_EWSW[29]), .QN(n3129) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1746), .CK(clk), .RN(n3308),
.Q(intDY_EWSW[3]), .QN(n3128) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1722), .CK(clk), .RN(n3322),
.Q(intDY_EWSW[27]), .QN(n3127) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1724), .CK(clk), .RN(n1831),
.Q(intDY_EWSW[25]), .QN(n3126) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1730), .CK(clk), .RN(n3313),
.Q(intDY_EWSW[19]), .QN(n3125) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1732), .CK(clk), .RN(n3324),
.Q(intDY_EWSW[17]), .QN(n3124) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3307), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3123) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1153), .CK(clk), .RN(n3343), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3122) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1190), .CK(clk), .RN(n3343), .Q(
Raw_mant_NRM_SWR[28]), .QN(n3121) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1796), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[19]), .QN(n3120) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1788), .CK(clk), .RN(n1831),
.Q(intDX_EWSW[27]), .QN(n3119) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1757), .CK(clk), .RN(n3321),
.Q(intDX_EWSW[58]), .QN(n3118) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1765), .CK(clk), .RN(n3311),
.Q(intDX_EWSW[50]), .QN(n3117) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1146), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[7]), .QN(n3115) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n3339), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3114) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1792), .CK(clk), .RN(n3312),
.Q(intDX_EWSW[23]), .QN(n3113) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1784), .CK(clk), .RN(n3311),
.Q(intDX_EWSW[31]), .QN(n3112) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1780), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[35]), .QN(n3111) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1772), .CK(clk), .RN(n3315),
.Q(intDX_EWSW[43]), .QN(n3110) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1144), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3109) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1187), .CK(clk), .RN(n3343), .Q(
Raw_mant_NRM_SWR[31]), .QN(n3108) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1129), .CK(clk), .RN(n3341), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3107) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1800), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[15]), .QN(n3106) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1198), .CK(clk), .RN(n3328), .Q(
Raw_mant_NRM_SWR[20]), .QN(n3105) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1142), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[9]), .QN(n3104) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1200), .CK(clk), .RN(n3352), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3103) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1191), .CK(clk), .RN(n3342), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3101) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1188), .CK(clk), .RN(n3346), .Q(
Raw_mant_NRM_SWR[30]), .QN(n3100) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1185), .CK(clk), .RN(n3346), .Q(
Raw_mant_NRM_SWR[33]), .QN(n3099) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1183), .CK(clk), .RN(n3330), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3098) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1182), .CK(clk), .RN(n3346), .Q(
Raw_mant_NRM_SWR[36]), .QN(n3097) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1168), .CK(clk), .RN(n3334), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3096) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1224), .CK(clk), .RN(n3319), .Q(
DmP_EXP_EWSW[55]), .QN(n3095) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1759), .CK(clk), .RN(n3308),
.Q(intDX_EWSW[56]), .QN(n3094) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n1820), .CK(clk), .RN(n3308), .Q(
busy), .QN(n3300) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1225), .CK(clk), .RN(n3316), .Q(
DmP_EXP_EWSW[54]), .QN(n3093) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1226), .CK(clk), .RN(n3316), .Q(
DmP_EXP_EWSW[53]), .QN(n3092) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1131), .CK(clk), .RN(n3345), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3091) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1186), .CK(clk), .RN(n3337), .Q(
Raw_mant_NRM_SWR[32]), .QN(n3090) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1223), .CK(clk), .RN(n3311), .Q(
DmP_EXP_EWSW[56]), .QN(n3089) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1696), .CK(clk), .RN(n3323),
.Q(intDY_EWSW[53]), .QN(n3088) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1695), .CK(clk), .RN(n3310),
.Q(intDY_EWSW[54]), .QN(n3087) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3332), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3086) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1626), .CK(clk), .RN(n3311),
.Q(shift_value_SHT2_EWR[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1810), .CK(clk), .RN(n3312),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1171), .CK(clk), .RN(n3346), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1195), .CK(clk), .RN(n3328), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1179), .CK(clk), .RN(n3330), .Q(
Raw_mant_NRM_SWR[39]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1159), .CK(clk), .RN(n3314), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1652), .CK(clk), .RN(n1832), .Q(
Data_array_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1657), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1651), .CK(clk), .RN(n3349), .Q(
Data_array_SWR[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1777), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1659), .CK(clk), .RN(n3336), .Q(
Data_array_SWR[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1763), .CK(clk), .RN(n3320),
.Q(intDX_EWSW[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1660), .CK(clk), .RN(n1832), .Q(
Data_array_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1152), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1771), .CK(clk), .RN(n3323),
.Q(intDX_EWSW[44]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1189), .CK(clk), .RN(n3352), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1778), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1768), .CK(clk), .RN(n3310),
.Q(intDX_EWSW[47]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1662), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1775), .CK(clk), .RN(n3313),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1767), .CK(clk), .RN(n3315),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1805), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1173), .CK(clk), .RN(n3334), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1808), .CK(clk), .RN(n3311),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1799), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1783), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1813), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1202), .CK(clk), .RN(n1908), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1654), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1665), .CK(clk), .RN(n1832), .Q(
Data_array_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1149), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1180), .CK(clk), .RN(n3334), .Q(
Raw_mant_NRM_SWR[38]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1140), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1167), .CK(clk), .RN(n3332), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1815), .CK(clk), .RN(n3313),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1754), .CK(clk), .RN(n3322),
.Q(intDX_EWSW[61]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1753), .CK(clk), .RN(n3314),
.Q(intDX_EWSW[62]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1824), .CK(clk), .RN(
n3311), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1675), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1678), .CK(clk), .RN(n3347), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1680), .CK(clk), .RN(n3336), .Q(
Data_array_SWR[34]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1672), .CK(clk), .RN(n3319), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1673), .CK(clk), .RN(n3353), .Q(
Data_array_SWR[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1181), .CK(clk), .RN(n3342), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1630), .CK(clk), .RN(n3318),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1510), .CK(clk), .RN(n3325), .Q(
DMP_SFG[10]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1693), .CK(clk), .RN(n3320),
.Q(intDY_EWSW[56]), .QN(n1853) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1641), .CK(clk), .RN(n3309), .Q(
Data_array_SWR[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1537), .CK(clk), .RN(n3310), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1266), .CK(clk), .RN(n3343),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1284), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1302), .CK(clk), .RN(n3342),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1310), .CK(clk), .RN(n3353),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1244), .CK(clk), .RN(n3353),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1248), .CK(clk), .RN(n1908),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1256), .CK(clk), .RN(n1832),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1260), .CK(clk), .RN(n1832),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1270), .CK(clk), .RN(n3345),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1274), .CK(clk), .RN(n3341),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1296), .CK(clk), .RN(n3337),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1232), .CK(clk), .RN(n3349),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1752), .CK(clk), .RN(n3309),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1519), .CK(clk), .RN(n1908), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1525), .CK(clk), .RN(n3329), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1516), .CK(clk), .RN(n3347), .Q(
DMP_SFG[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1254), .CK(clk), .RN(n3340),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1276), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1282), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1286), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1290), .CK(clk), .RN(n3330),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1294), .CK(clk), .RN(n3337),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3343),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1227), .CK(clk), .RN(n3317), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1262), .CK(clk), .RN(n3353),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1298), .CK(clk), .RN(n3330),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1304), .CK(clk), .RN(n3342),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1306), .CK(clk), .RN(n3334),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1312), .CK(clk), .RN(n3354), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1318), .CK(clk), .RN(n3354), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n3353), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1638), .CK(clk), .RN(n3314), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(n3336), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1326), .CK(clk), .RN(n3354), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1635), .CK(clk), .RN(n1907), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1636), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1551), .CK(clk), .RN(n3323), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1322), .CK(clk), .RN(n1832), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1330), .CK(clk), .RN(n3335), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1132), .CK(clk), .RN(n3335), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1139), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1143), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n3331), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(n3324), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1141), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1145), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1147), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[5]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1150), .CK(clk), .RN(n3344), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1037), .CK(clk), .RN(n3347), .Q(
DmP_mant_SFG_SWR[54]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1040), .CK(clk), .RN(n1908), .Q(
DmP_mant_SFG_SWR[51]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1062), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1064), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1065), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1066), .CK(clk), .RN(n3340), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1067), .CK(clk), .RN(n1907), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1068), .CK(clk), .RN(n1907), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1157), .CK(clk), .RN(n3331), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1160), .CK(clk), .RN(n3339), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1166), .CK(clk), .RN(n3342), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1632), .CK(clk), .RN(n3321), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1631), .CK(clk), .RN(n1831), .Q(
Data_array_SWR[0]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1686), .CK(clk), .RN(n3319),
.Q(intDY_EWSW[63]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1661), .CK(clk), .RN(n3347), .Q(
Data_array_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1811), .CK(clk), .RN(n3318),
.Q(intDX_EWSW[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1658), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1776), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1806), .CK(clk), .RN(n3307),
.Q(intDX_EWSW[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1663), .CK(clk), .RN(n3343), .Q(
Data_array_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1196), .CK(clk), .RN(n1832), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1809), .CK(clk), .RN(n1830),
.Q(intDX_EWSW[6]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1670), .CK(clk), .RN(n3316), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1679), .CK(clk), .RN(n3334), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1677), .CK(clk), .RN(n1832), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1674), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1681), .CK(clk), .RN(n3317), .Q(
Data_array_SWR[35]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1174), .CK(clk), .RN(n3343), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1642), .CK(clk), .RN(n1830), .Q(
Data_array_SWR[11]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1640), .CK(clk), .RN(n3312), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1639), .CK(clk), .RN(n3313), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1240), .CK(clk), .RN(n3340),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1292), .CK(clk), .RN(n3337),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1288), .CK(clk), .RN(n3330),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1278), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1252), .CK(clk), .RN(n3354),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1236), .CK(clk), .RN(n3336),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1507), .CK(clk), .RN(n3307), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1528), .CK(clk), .RN(n1831), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1522), .CK(clk), .RN(n3309), .Q(
DMP_SFG[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1228), .CK(clk), .RN(n3341),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1637), .CK(clk), .RN(n3349), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1264), .CK(clk), .RN(n3307),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1250), .CK(clk), .RN(n1832),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1246), .CK(clk), .RN(n1832),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1242), .CK(clk), .RN(n3340),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1328), .CK(clk), .RN(n3340), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1625), .CK(clk), .RN(n3320),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1316), .CK(clk), .RN(n3352), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1320), .CK(clk), .RN(n3327), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1230), .CK(clk), .RN(n3332),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1300), .CK(clk), .RN(n3343),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1272), .CK(clk), .RN(n3338),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1268), .CK(clk), .RN(n3331),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1258), .CK(clk), .RN(n3335),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1238), .CK(clk), .RN(n3345),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1234), .CK(clk), .RN(n1907),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n1819), .CK(clk), .RN(n3307), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1063), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1061), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1060), .CK(clk), .RN(n3333), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1048), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[43]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1046), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1045), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[46]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1044), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[47]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1043), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[48]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1042), .CK(clk), .RN(n3348), .Q(
DmP_mant_SFG_SWR[49]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1041), .CK(clk), .RN(n3341), .Q(
DmP_mant_SFG_SWR[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1039), .CK(clk), .RN(n3332), .Q(
DmP_mant_SFG_SWR[52]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1038), .CK(clk), .RN(n3345), .Q(
DmP_mant_SFG_SWR[53]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1054), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[37]), .QN(n1890) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1055), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[36]), .QN(n1889) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1056), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[35]), .QN(n1888) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1057), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[34]), .QN(n1887) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1058), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[33]), .QN(n1886) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1059), .CK(clk), .RN(n3350), .Q(
DmP_mant_SFG_SWR[32]), .QN(n1885) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1047), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[44]), .QN(n1898) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1049), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[42]), .QN(n1896) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1050), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[41]), .QN(n1895) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1051), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[40]), .QN(n1893) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1052), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[39]), .QN(n1892) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1053), .CK(clk), .RN(n3351), .Q(
DmP_mant_SFG_SWR[38]), .QN(n1891) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1069), .CK(clk), .RN(n3354), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1884) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1070), .CK(clk), .RN(n3335), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1883) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1071), .CK(clk), .RN(n3353), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1882) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1072), .CK(clk), .RN(n3348), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1881) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1073), .CK(clk), .RN(n1908), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1842) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3348), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1904) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1075), .CK(clk), .RN(n1908), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1903) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1076), .CK(clk), .RN(n3348), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1902) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1077), .CK(clk), .RN(n1908), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1901) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1362), .CK(clk), .RN(n1907), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1130), .CK(clk), .RN(n3345), .Q(
DmP_mant_SFG_SWR[11]), .QN(n1899) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1122), .CK(clk), .RN(n3333), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1900) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1377), .CK(clk), .RN(n3341), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1372), .CK(clk), .RN(n1908), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1367), .CK(clk), .RN(n3345), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1357), .CK(clk), .RN(n3342), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1633), .CK(clk), .RN(n3320), .Q(
Data_array_SWR[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1222), .CK(clk), .RN(n3320), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1136), .CK(clk), .RN(n1907), .Q(
DmP_mant_SFG_SWR[10]), .QN(n1897) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1694), .CK(clk), .RN(n1831),
.Q(intDY_EWSW[55]), .QN(n1854) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1556), .CK(clk), .RN(n3324), .Q(
DMP_EXP_EWSW[52]), .QN(n3291) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1163), .CK(clk), .RN(n1832), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1894) );
ADDFX1TS DP_OP_15J76_123_4372_U11 ( .A(n3208), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J76_123_4372_n11), .CO(DP_OP_15J76_123_4372_n10), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J76_123_4372_U10 ( .A(n3207), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J76_123_4372_n10), .CO(DP_OP_15J76_123_4372_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J76_123_4372_U9 ( .A(n3225), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J76_123_4372_n9), .CO(DP_OP_15J76_123_4372_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J76_123_4372_U7 ( .A(n3229), .B(DMP_exp_NRM2_EW[5]), .CI(
DP_OP_15J76_123_4372_n7), .CO(DP_OP_15J76_123_4372_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1165), .CK(clk), .RN(n3334), .Q(
Raw_mant_NRM_SWR[53]), .QN(n3116) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1822), .CK(clk), .RN(n3322), .QN(
n1905) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1750), .CK(clk), .RN(n3322),
.Q(left_right_SHT2), .QN(n3149) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1821), .CK(clk), .RN(n3314), .Q(
n1906), .QN(n3305) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1818), .CK(clk), .RN(n1831), .QN(
n3302) );
AOI222X1TS U1859 ( .A0(n3022), .A1(n3149), .B0(n3021), .B1(n1983), .C0(n3020), .C1(n3038), .Y(n3055) );
AOI222X1TS U1860 ( .A0(n2972), .A1(n3037), .B0(n2971), .B1(n1983), .C0(n2970), .C1(n3038), .Y(n2969) );
CMPR32X2TS U1861 ( .A(DMP_SFG[8]), .B(n2925), .C(n2924), .CO(n2909), .S(
n2926) );
CMPR32X2TS U1862 ( .A(DMP_SFG[4]), .B(n2901), .C(n2900), .CO(n2889), .S(
n2903) );
CMPR32X2TS U1863 ( .A(DMP_SFG[6]), .B(n2930), .C(n2929), .CO(n2898), .S(
n2931) );
CLKINVX6TS U1864 ( .A(n2760), .Y(n2761) );
NAND2X4TS U1865 ( .A(n2952), .B(n1993), .Y(n1982) );
NAND2X4TS U1866 ( .A(n1863), .B(n2308), .Y(n2318) );
INVX12TS U1867 ( .A(n2010), .Y(n2914) );
NOR2XLTS U1868 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2492)
);
NOR2X8TS U1869 ( .A(n2507), .B(n2743), .Y(n2501) );
AND2X4TS U1870 ( .A(n2507), .B(n1826), .Y(n2526) );
AOI222X1TS U1871 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2637), .B0(
Raw_mant_NRM_SWR[16]), .B1(n1826), .C0(n2613), .C1(
DmP_mant_SHT1_SW[36]), .Y(n2678) );
AOI222X1TS U1872 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2656), .B0(
Raw_mant_NRM_SWR[4]), .B1(n1826), .C0(n2587), .C1(DmP_mant_SHT1_SW[48]), .Y(n2685) );
AOI222X1TS U1873 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2656), .C0(n2587), .C1(
DmP_mant_SHT1_SW[11]), .Y(n2663) );
AOI222X1TS U1874 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2664) );
AOI222X1TS U1875 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2656), .C0(n2613), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2638) );
AOI222X1TS U1876 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2637), .B0(
Raw_mant_NRM_SWR[6]), .B1(n1826), .C0(n2613), .C1(DmP_mant_SHT1_SW[46]), .Y(n2657) );
AOI222X1TS U1877 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2656), .C0(n2587), .C1(
DmP_mant_SHT1_SW[24]), .Y(n2667) );
AOI222X1TS U1878 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2674) );
AOI222X1TS U1879 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2637), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1826), .C0(n2655), .C1(
DmP_mant_SHT1_SW[29]), .Y(n2648) );
AOI222X1TS U1880 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[20]), .Y(n2654) );
AOI222X1TS U1881 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2637), .B0(
Raw_mant_NRM_SWR[34]), .B1(n1826), .C0(n2587), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2651) );
AOI222X1TS U1882 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2637), .B0(
Raw_mant_NRM_SWR[14]), .B1(n1826), .C0(n2655), .C1(
DmP_mant_SHT1_SW[38]), .Y(n2682) );
AOI222X1TS U1883 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2656), .C0(n2587), .C1(
DmP_mant_SHT1_SW[15]), .Y(n2673) );
AOI222X1TS U1884 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[39]), .C0(n2586), .C1(DmP_mant_SHT1_SW[38]), .Y(n2601) );
AOI222X1TS U1885 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1825), .B0(
Raw_mant_NRM_SWR[2]), .B1(n1826), .C0(DmP_mant_SHT1_SW[50]), .C1(n2587), .Y(n2690) );
AOI222X1TS U1886 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n1825), .B0(n2613), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2612), .C1(DmP_mant_SHT1_SW[2]), .Y(n2525)
);
NAND2X1TS U1887 ( .A(n2445), .B(n3099), .Y(n2728) );
BUFX6TS U1888 ( .A(n2309), .Y(n2367) );
INVX1TS U1889 ( .A(n2152), .Y(n2453) );
CLKINVX6TS U1890 ( .A(n2551), .Y(n2613) );
BUFX4TS U1891 ( .A(n2863), .Y(n2817) );
BUFX4TS U1892 ( .A(n2863), .Y(n1829) );
NAND2BX1TS U1893 ( .AN(n2731), .B(n2729), .Y(n2141) );
CLKINVX3TS U1894 ( .A(n1994), .Y(n2915) );
BUFX4TS U1895 ( .A(n2535), .Y(n2683) );
NOR2X1TS U1896 ( .A(n2558), .B(n2534), .Y(n2535) );
NOR2X1TS U1897 ( .A(n2672), .B(n2558), .Y(n2559) );
INVX4TS U1898 ( .A(n2778), .Y(n2534) );
AOI222X1TS U1899 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[19]), .C0(n2586), .C1(DmP_mant_SHT1_SW[18]), .Y(n2565) );
BUFX6TS U1900 ( .A(n2540), .Y(n1825) );
INVX6TS U1901 ( .A(n2743), .Y(n1826) );
NAND3X1TS U1902 ( .A(n2478), .B(Raw_mant_NRM_SWR[1]), .C(n3122), .Y(n2702)
);
INVX1TS U1903 ( .A(n2695), .Y(n2696) );
NAND3X1TS U1904 ( .A(n2150), .B(n2467), .C(n2711), .Y(n2151) );
NAND2XLTS U1905 ( .A(Raw_mant_NRM_SWR[21]), .B(n2144), .Y(n2717) );
NOR3BX1TS U1906 ( .AN(n2155), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n2144) );
INVX1TS U1907 ( .A(n2479), .Y(n2480) );
OR2X4TS U1908 ( .A(n2851), .B(n2841), .Y(n2976) );
NAND2XLTS U1909 ( .A(Raw_mant_NRM_SWR[25]), .B(n2149), .Y(n2711) );
INVX1TS U1910 ( .A(n2713), .Y(n2465) );
INVX1TS U1911 ( .A(n2728), .Y(n2476) );
BUFX3TS U1912 ( .A(n2318), .Y(n1827) );
INVX1TS U1913 ( .A(n2709), .Y(n2474) );
OAI21X1TS U1914 ( .A0(n3283), .A1(n2010), .B0(n1998), .Y(n1847) );
INVX3TS U1915 ( .A(n1981), .Y(n1999) );
OAI21X1TS U1916 ( .A0(n3282), .A1(n2010), .B0(n2009), .Y(n1846) );
INVX3TS U1917 ( .A(n1982), .Y(n1983) );
BUFX6TS U1918 ( .A(n2067), .Y(n1858) );
AO22XLTS U1919 ( .A0(n2896), .A1(DmP_mant_SFG_SWR[13]), .B0(n1894), .B1(
n2869), .Y(n1841) );
INVX6TS U1920 ( .A(n2968), .Y(n1828) );
NAND2X4TS U1921 ( .A(n1993), .B(n3037), .Y(n1981) );
NOR2X4TS U1922 ( .A(n2738), .B(n2849), .Y(n2496) );
INVX3TS U1923 ( .A(n3018), .Y(n2018) );
INVX4TS U1924 ( .A(n3045), .Y(n1986) );
BUFX6TS U1925 ( .A(n3336), .Y(n1830) );
BUFX6TS U1926 ( .A(n3340), .Y(n3317) );
BUFX6TS U1927 ( .A(n3327), .Y(n1831) );
OR2X2TS U1928 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1978) );
BUFX6TS U1929 ( .A(n3302), .Y(n2938) );
NOR3X1TS U1930 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n2154) );
NAND2XLTS U1931 ( .A(n3103), .B(n3166), .Y(n2700) );
BUFX6TS U1932 ( .A(n1907), .Y(n3335) );
BUFX6TS U1933 ( .A(n1907), .Y(n3353) );
BUFX6TS U1934 ( .A(n1907), .Y(n3354) );
BUFX6TS U1935 ( .A(n1907), .Y(n1908) );
BUFX6TS U1936 ( .A(n1907), .Y(n1832) );
NAND2BXLTS U1937 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2201) );
NAND2X1TS U1938 ( .A(n2154), .B(n2458), .Y(n2142) );
NAND2X1TS U1939 ( .A(n2148), .B(n3153), .Y(n2152) );
NOR2X1TS U1940 ( .A(Raw_mant_NRM_SWR[26]), .B(n2157), .Y(n2149) );
NOR2X1TS U1941 ( .A(Raw_mant_NRM_SWR[34]), .B(n2727), .Y(n2445) );
NAND2X1TS U1942 ( .A(n2716), .B(n3098), .Y(n2727) );
NAND2X1TS U1943 ( .A(n2477), .B(n3101), .Y(n2157) );
NAND2X1TS U1944 ( .A(n2149), .B(n3161), .Y(n2479) );
CLKAND2X2TS U1945 ( .A(n2143), .B(n2710), .Y(n2481) );
NAND2X1TS U1946 ( .A(n2156), .B(n3100), .Y(n2713) );
NAND2X1TS U1947 ( .A(n2145), .B(n3154), .Y(n2709) );
NAND2X1TS U1948 ( .A(n3097), .B(n2481), .Y(n2461) );
NAND2X1TS U1949 ( .A(n2694), .B(n3104), .Y(n2488) );
NAND2X1TS U1950 ( .A(n2695), .B(n2698), .Y(n2491) );
NOR2X1TS U1951 ( .A(Raw_mant_NRM_SWR[14]), .B(n2725), .Y(n2448) );
NAND2BXLTS U1952 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2246) );
AOI211X1TS U1953 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1860), .B0(n2072),
.C0(n2071), .Y(n2098) );
NAND2X1TS U1954 ( .A(n2448), .B(n3172), .Y(n2737) );
OAI211XLTS U1955 ( .A0(n3101), .A1(n2450), .B0(n2449), .C0(n2703), .Y(n2451)
);
AO21XLTS U1956 ( .A0(n3186), .A1(n3105), .B0(n2726), .Y(n2483) );
AOI31XLTS U1957 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2699), .A2(n3103), .B0(
n2462), .Y(n2463) );
OAI211XLTS U1958 ( .A0(n2461), .A1(n3098), .B0(n2460), .C0(n2486), .Y(n2462)
);
AO21XLTS U1959 ( .A0(n3091), .A1(n3115), .B0(n2488), .Y(n2489) );
BUFX3TS U1960 ( .A(n2613), .Y(n2655) );
AOI222X1TS U1961 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2586), .C1(DmP_mant_SHT1_SW[9]), .Y(n2621)
);
AOI222X1TS U1962 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2656), .B0(n2613), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2612), .C1(DmP_mant_SHT1_SW[46]), .Y(n2576) );
AOI222X1TS U1963 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2656), .B0(n2587), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2612), .C1(DmP_mant_SHT1_SW[48]), .Y(n2573) );
AOI222X1TS U1964 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n1825), .B0(n2613), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2612), .C1(DmP_mant_SHT1_SW[8]), .Y(n2660)
);
AOI222X1TS U1965 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2586), .C1(DmP_mant_SHT1_SW[27]), .Y(n2597) );
AOI222X1TS U1966 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2586), .C1(DmP_mant_SHT1_SW[29]), .Y(n2594) );
AOI222X1TS U1967 ( .A0(n2880), .A1(DMP_SFG[1]), .B0(n2880), .B1(n2879), .C0(
DMP_SFG[1]), .C1(n2879), .Y(n2891) );
AOI222X1TS U1968 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1825), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2612), .C0(n2655), .C1(
DmP_mant_SHT1_SW[51]), .Y(n2570) );
NAND3XLTS U1969 ( .A(Raw_mant_NRM_SWR[0]), .B(n2743), .C(n2551), .Y(n2562)
);
AOI222X1TS U1970 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2612), .C1(DmP_mant_SHT1_SW[24]), .Y(n2622) );
AOI222X1TS U1971 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2656), .B0(n2613), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2586), .C1(DmP_mant_SHT1_SW[34]), .Y(n2557) );
AO22XLTS U1972 ( .A0(DMP_SFG[11]), .A1(n1859), .B0(DMP_SFG[10]), .B1(n2937),
.Y(n2444) );
OAI31X1TS U1973 ( .A0(Raw_mant_NRM_SWR[16]), .A1(Raw_mant_NRM_SWR[14]), .A2(
n2700), .B0(n2699), .Y(n2701) );
AOI222X1TS U1974 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[4]), .C0(n2514), .C1(DmP_mant_SHT1_SW[3]), .Y(n2539)
);
AOI222X1TS U1975 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2637), .B0(n2587), .B1(
DmP_mant_SHT1_SW[12]), .C0(n2612), .C1(DmP_mant_SHT1_SW[11]), .Y(n2617) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2637), .B0(n2587), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2586), .C1(DmP_mant_SHT1_SW[12]), .Y(n2669) );
AOI222X1TS U1977 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2637), .B0(n2587), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2586), .C1(DmP_mant_SHT1_SW[13]), .Y(n2607) );
AOI222X1TS U1978 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[16]), .C0(n2586), .C1(DmP_mant_SHT1_SW[15]), .Y(n2631) );
AOI222X1TS U1979 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2586), .C1(DmP_mant_SHT1_SW[16]), .Y(n2545) );
AOI222X1TS U1980 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[21]), .C0(n2612), .C1(DmP_mant_SHT1_SW[20]), .Y(n2600) );
AOI222X1TS U1981 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2586), .C1(DmP_mant_SHT1_SW[22]), .Y(n2616) );
AOI222X1TS U1982 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2637), .B0(n2613), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2586), .C1(DmP_mant_SHT1_SW[25]), .Y(n2548) );
AOI222X1TS U1983 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1825), .B0(n2613), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2612), .C1(DmP_mant_SHT1_SW[31]), .Y(n2611) );
AOI222X1TS U1984 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2637), .B0(n2587), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2586), .C1(DmP_mant_SHT1_SW[36]), .Y(n2604) );
AO22XLTS U1985 ( .A0(n2758), .A1(n2821), .B0(n2756), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1819) );
AO22XLTS U1986 ( .A0(n2843), .A1(DmP_EXP_EWSW[48]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1234) );
AO22XLTS U1987 ( .A0(n2843), .A1(DmP_EXP_EWSW[46]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1238) );
AO22XLTS U1988 ( .A0(n2847), .A1(DmP_EXP_EWSW[36]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1258) );
AO22XLTS U1989 ( .A0(n2847), .A1(DmP_EXP_EWSW[31]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1268) );
AO22XLTS U1990 ( .A0(n2847), .A1(DmP_EXP_EWSW[29]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1272) );
AO22XLTS U1991 ( .A0(n2835), .A1(DmP_EXP_EWSW[15]), .B0(n2833), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1300) );
AO22XLTS U1992 ( .A0(n2832), .A1(DmP_EXP_EWSW[5]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1320) );
AO22XLTS U1993 ( .A0(n2832), .A1(DmP_EXP_EWSW[7]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1316) );
AO22XLTS U1994 ( .A0(n1864), .A1(n2794), .B0(n2823), .B1(
Shift_amount_SHT1_EWR[0]), .Y(n1625) );
AO22XLTS U1995 ( .A0(n2831), .A1(DmP_EXP_EWSW[1]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1328) );
AO22XLTS U1996 ( .A0(n2843), .A1(DmP_EXP_EWSW[44]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1242) );
AO22XLTS U1997 ( .A0(n2843), .A1(DmP_EXP_EWSW[42]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1246) );
AO22XLTS U1998 ( .A0(n2843), .A1(DmP_EXP_EWSW[40]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1250) );
AO22XLTS U1999 ( .A0(n2847), .A1(DmP_EXP_EWSW[33]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1264) );
AO22XLTS U2000 ( .A0(n2830), .A1(DMP_SHT2_EWSW[6]), .B0(n3065), .B1(
DMP_SFG[6]), .Y(n1522) );
AO22XLTS U2001 ( .A0(n2830), .A1(DMP_SHT2_EWSW[4]), .B0(n3065), .B1(
DMP_SFG[4]), .Y(n1528) );
AO22XLTS U2002 ( .A0(n3082), .A1(DMP_SHT2_EWSW[11]), .B0(n3065), .B1(
DMP_SFG[11]), .Y(n1507) );
AO22XLTS U2003 ( .A0(n2843), .A1(DmP_EXP_EWSW[47]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1236) );
AO22XLTS U2004 ( .A0(n2843), .A1(DmP_EXP_EWSW[39]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1252) );
AO22XLTS U2005 ( .A0(n2835), .A1(DmP_EXP_EWSW[26]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1278) );
AO22XLTS U2006 ( .A0(n2835), .A1(DmP_EXP_EWSW[21]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1288) );
AO22XLTS U2007 ( .A0(n2835), .A1(DmP_EXP_EWSW[19]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1292) );
AO22XLTS U2008 ( .A0(n2843), .A1(DmP_EXP_EWSW[45]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1240) );
AOI2BB2XLTS U2009 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n2501), .A0N(n2660),
.A1N(n2672), .Y(n2527) );
AOI2BB2XLTS U2010 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n2501), .A0N(n2617),
.A1N(n2689), .Y(n2618) );
OAI211XLTS U2011 ( .A0(n2573), .A1(n2620), .B0(n2572), .C0(n2571), .Y(n1681)
);
AOI2BB2XLTS U2012 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n2780), .A0N(n2570), .A1N(
n2672), .Y(n2571) );
AOI2BB2XLTS U2013 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[43]), .A0N(n2647),
.A1N(n2534), .Y(n2641) );
AOI2BB2XLTS U2014 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n2501), .A0N(n2576), .A1N(
n2672), .Y(n2568) );
AOI2BB2XLTS U2015 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n2501), .A0N(n2573), .A1N(
n2689), .Y(n2574) );
AOI2BB2XLTS U2016 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[39]), .A0N(n2682),
.A1N(n2534), .Y(n2629) );
AO22XLTS U2017 ( .A0(n2774), .A1(Data_X[6]), .B0(n2765), .B1(intDX_EWSW[6]),
.Y(n1809) );
AOI2BB2XLTS U2018 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2674),
.A1N(n2534), .Y(n2675) );
AO22XLTS U2019 ( .A0(n2773), .A1(Data_X[9]), .B0(n2765), .B1(intDX_EWSW[9]),
.Y(n1806) );
AO22XLTS U2020 ( .A0(n2761), .A1(Data_X[39]), .B0(n2768), .B1(intDX_EWSW[39]), .Y(n1776) );
OAI211XLTS U2021 ( .A0(n2548), .A1(n2684), .B0(n2531), .C0(n2530), .Y(n1658)
);
AOI2BB2XLTS U2022 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n2501), .A0N(n2597),
.A1N(n2689), .Y(n2530) );
AO22XLTS U2023 ( .A0(n2773), .A1(Data_X[4]), .B0(n2760), .B1(intDX_EWSW[4]),
.Y(n1811) );
AOI2BB2XLTS U2024 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2648),
.A1N(n2534), .Y(n2649) );
AO22XLTS U2025 ( .A0(n2761), .A1(Data_Y[63]), .B0(n2776), .B1(intDY_EWSW[63]), .Y(n1686) );
AOI2BB2XLTS U2026 ( .B0(n2877), .B1(intadd_74_SUM_38_), .A0N(
Raw_mant_NRM_SWR[52]), .A1N(n2932), .Y(n1166) );
AO22XLTS U2027 ( .A0(n2822), .A1(n2864), .B0(n2863), .B1(DmP_mant_SFG_SWR[1]), .Y(n1160) );
AO22XLTS U2028 ( .A0(n3082), .A1(DMP_SHT2_EWSW[0]), .B0(n3065), .B1(
DMP_SFG[0]), .Y(n1540) );
AO22XLTS U2029 ( .A0(n2872), .A1(n2871), .B0(n3065), .B1(DmP_mant_SFG_SWR[2]), .Y(n1154) );
AO22XLTS U2030 ( .A0(n2831), .A1(DmP_EXP_EWSW[0]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1330) );
AO22XLTS U2031 ( .A0(n2832), .A1(DmP_EXP_EWSW[4]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1322) );
AOI2BB2XLTS U2032 ( .B0(n1879), .B1(n2501), .A0N(n2580), .A1N(n2689), .Y(
n2537) );
AO22XLTS U2033 ( .A0(n2831), .A1(DmP_EXP_EWSW[2]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1326) );
AO22XLTS U2034 ( .A0(n2832), .A1(DmP_EXP_EWSW[8]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1314) );
AO22XLTS U2035 ( .A0(n2832), .A1(DmP_EXP_EWSW[3]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1324) );
AO22XLTS U2036 ( .A0(n2832), .A1(DmP_EXP_EWSW[6]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1318) );
AO22XLTS U2037 ( .A0(n2832), .A1(DmP_EXP_EWSW[9]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1312) );
AO22XLTS U2038 ( .A0(n2832), .A1(DmP_EXP_EWSW[12]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1306) );
AO22XLTS U2039 ( .A0(n2832), .A1(DmP_EXP_EWSW[13]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1304) );
AO22XLTS U2040 ( .A0(n2835), .A1(DmP_EXP_EWSW[16]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1298) );
AO22XLTS U2041 ( .A0(n2835), .A1(DmP_EXP_EWSW[25]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1280) );
AO22XLTS U2042 ( .A0(n2847), .A1(DmP_EXP_EWSW[34]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1262) );
AOI222X1TS U2043 ( .A0(n2367), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n1905), .C0(intDY_EWSW[52]), .C1(n2413), .Y(n2319) );
AO22XLTS U2044 ( .A0(n2832), .A1(DmP_EXP_EWSW[11]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1308) );
AO22XLTS U2045 ( .A0(n2835), .A1(DmP_EXP_EWSW[18]), .B0(n3305), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1294) );
AO22XLTS U2046 ( .A0(n2835), .A1(DmP_EXP_EWSW[20]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1290) );
AO22XLTS U2047 ( .A0(n2835), .A1(DmP_EXP_EWSW[22]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1286) );
AO22XLTS U2048 ( .A0(n2835), .A1(DmP_EXP_EWSW[24]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[24]), .Y(n1282) );
AO22XLTS U2049 ( .A0(n2847), .A1(DmP_EXP_EWSW[27]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1276) );
AO22XLTS U2050 ( .A0(n2847), .A1(DmP_EXP_EWSW[38]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1254) );
AO22XLTS U2051 ( .A0(n3082), .A1(DMP_SHT2_EWSW[8]), .B0(n3065), .B1(
DMP_SFG[8]), .Y(n1516) );
AO22XLTS U2052 ( .A0(n3082), .A1(DMP_SHT2_EWSW[5]), .B0(n3065), .B1(
DMP_SFG[5]), .Y(n1525) );
AO22XLTS U2053 ( .A0(n3082), .A1(DMP_SHT2_EWSW[7]), .B0(n3065), .B1(
DMP_SFG[7]), .Y(n1519) );
AO22XLTS U2054 ( .A0(n2763), .A1(Data_X[63]), .B0(n2776), .B1(intDX_EWSW[63]), .Y(n1752) );
AO22XLTS U2055 ( .A0(n2843), .A1(DmP_EXP_EWSW[49]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1232) );
AO22XLTS U2056 ( .A0(n2835), .A1(DmP_EXP_EWSW[17]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1296) );
AO22XLTS U2057 ( .A0(n2847), .A1(DmP_EXP_EWSW[28]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1274) );
AO22XLTS U2058 ( .A0(n2847), .A1(DmP_EXP_EWSW[30]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1270) );
AO22XLTS U2059 ( .A0(n2847), .A1(DmP_EXP_EWSW[35]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1260) );
AO22XLTS U2060 ( .A0(n2847), .A1(DmP_EXP_EWSW[37]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1256) );
AO22XLTS U2061 ( .A0(n2843), .A1(DmP_EXP_EWSW[41]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1248) );
AO22XLTS U2062 ( .A0(n2843), .A1(DmP_EXP_EWSW[43]), .B0(n2836), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1244) );
AO22XLTS U2063 ( .A0(n2832), .A1(DmP_EXP_EWSW[10]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1310) );
AO22XLTS U2064 ( .A0(n2832), .A1(DmP_EXP_EWSW[14]), .B0(n2846), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1302) );
AO22XLTS U2065 ( .A0(n2835), .A1(DmP_EXP_EWSW[23]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1284) );
AO22XLTS U2066 ( .A0(n2847), .A1(DmP_EXP_EWSW[32]), .B0(n2844), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1266) );
AO22XLTS U2067 ( .A0(n3082), .A1(DMP_SHT2_EWSW[1]), .B0(n3065), .B1(
DMP_SFG[1]), .Y(n1537) );
AOI2BB2XLTS U2068 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2660),
.A1N(n2684), .Y(n2661) );
AO22XLTS U2069 ( .A0(n3082), .A1(DMP_SHT2_EWSW[10]), .B0(n3065), .B1(
DMP_SFG[10]), .Y(n1510) );
AOI2BB2XLTS U2070 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n2780), .A0N(n2593),
.A1N(n2689), .Y(n2581) );
AOI2BB2XLTS U2071 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[41]), .A0N(n2644),
.A1N(n2534), .Y(n2645) );
OAI211XLTS U2072 ( .A0(n2690), .A1(n2689), .B0(n2688), .C0(n2687), .Y(n1680)
);
AOI2BB2XLTS U2073 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n2686), .A0N(n2685),
.A1N(n2684), .Y(n2687) );
OAI211XLTS U2074 ( .A0(n2685), .A1(n2672), .B0(n2659), .C0(n2658), .Y(n1678)
);
AOI2BB2XLTS U2075 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2657),
.A1N(n2684), .Y(n2658) );
AOI2BB2XLTS U2076 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n2501), .A0N(n2590), .A1N(
n2672), .Y(n2591) );
AO22XLTS U2077 ( .A0(n2763), .A1(Data_X[62]), .B0(n2776), .B1(intDX_EWSW[62]), .Y(n1753) );
AO22XLTS U2078 ( .A0(n2763), .A1(Data_X[61]), .B0(n2767), .B1(intDX_EWSW[61]), .Y(n1754) );
AO22XLTS U2079 ( .A0(n2763), .A1(Data_X[0]), .B0(n2776), .B1(intDX_EWSW[0]),
.Y(n1815) );
AOI2BB2XLTS U2080 ( .B0(n2940), .B1(intadd_74_SUM_37_), .A0N(
Raw_mant_NRM_SWR[51]), .A1N(n2904), .Y(n1167) );
AOI2BB2XLTS U2081 ( .B0(n2683), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2677),
.A1N(n2534), .Y(n2549) );
AOI2BB2XLTS U2082 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2664),
.A1N(n2684), .Y(n2665) );
AO22XLTS U2083 ( .A0(n2771), .A1(Data_X[24]), .B0(n2766), .B1(intDX_EWSW[24]), .Y(n1791) );
AO22XLTS U2084 ( .A0(n2773), .A1(Data_X[2]), .B0(n2760), .B1(intDX_EWSW[2]),
.Y(n1813) );
AO22XLTS U2085 ( .A0(n2763), .A1(Data_X[32]), .B0(n2768), .B1(intDX_EWSW[32]), .Y(n1783) );
AO22XLTS U2086 ( .A0(n2771), .A1(Data_X[16]), .B0(n2765), .B1(intDX_EWSW[16]), .Y(n1799) );
AO22XLTS U2087 ( .A0(n2771), .A1(Data_X[7]), .B0(n2765), .B1(intDX_EWSW[7]),
.Y(n1808) );
AO22XLTS U2088 ( .A0(n2774), .A1(Data_X[10]), .B0(n2765), .B1(intDX_EWSW[10]), .Y(n1805) );
AO22XLTS U2089 ( .A0(n2763), .A1(Data_X[48]), .B0(n2767), .B1(intDX_EWSW[48]), .Y(n1767) );
AO22XLTS U2090 ( .A0(n2761), .A1(Data_X[40]), .B0(n2768), .B1(intDX_EWSW[40]), .Y(n1775) );
AOI2BB2XLTS U2091 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n2501), .A0N(n2611),
.A1N(n2689), .Y(n2584) );
AO22XLTS U2092 ( .A0(n2763), .A1(Data_X[47]), .B0(n2767), .B1(intDX_EWSW[47]), .Y(n1768) );
AO22XLTS U2093 ( .A0(n2764), .A1(Data_X[37]), .B0(n2768), .B1(intDX_EWSW[37]), .Y(n1778) );
AO22XLTS U2094 ( .A0(n2761), .A1(Data_X[44]), .B0(n2768), .B1(intDX_EWSW[44]), .Y(n1771) );
OAI211XLTS U2095 ( .A0(n2597), .A1(n2620), .B0(n2596), .C0(n2595), .Y(n1660)
);
AOI2BB2XLTS U2096 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n2501), .A0N(n2594),
.A1N(n2689), .Y(n2595) );
AO22XLTS U2097 ( .A0(n2764), .A1(Data_X[52]), .B0(n2767), .B1(intDX_EWSW[52]), .Y(n1763) );
OAI211XLTS U2098 ( .A0(n2648), .A1(n2681), .B0(n2640), .C0(n2639), .Y(n1659)
);
AOI2BB2XLTS U2099 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2638),
.A1N(n2534), .Y(n2639) );
AO22XLTS U2100 ( .A0(n2761), .A1(Data_X[38]), .B0(n2768), .B1(intDX_EWSW[38]), .Y(n1777) );
AOI2BB2XLTS U2101 ( .B0(Raw_mant_NRM_SWR[33]), .B1(n2501), .A0N(n2600),
.A1N(n2689), .Y(n2563) );
AOI2BB2XLTS U2102 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2622),
.A1N(n2534), .Y(n2623) );
AOI2BB2XLTS U2103 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[21]), .A0N(n2654),
.A1N(n2684), .Y(n2627) );
AOI2BB2XLTS U2104 ( .B0(n2904), .B1(intadd_74_SUM_33_), .A0N(
Raw_mant_NRM_SWR[47]), .A1N(n2940), .Y(n1171) );
AO22XLTS U2105 ( .A0(n2771), .A1(Data_X[5]), .B0(n2766), .B1(intDX_EWSW[5]),
.Y(n1810) );
AO22XLTS U2106 ( .A0(n2756), .A1(n2932), .B0(n2758), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1818) );
AOI222X1TS U2107 ( .A0(n2935), .A1(DMP_SFG[10]), .B0(n2935), .B1(n2937),
.C0(DMP_SFG[10]), .C1(n2937), .Y(n2860) );
OAI211XLTS U2108 ( .A0(n2672), .A1(n2562), .B0(n2561), .C0(n2560), .Y(n1683)
);
AOI2BB1XLTS U2109 ( .A0N(n2570), .A1N(n2534), .B0(n2686), .Y(n2560) );
OAI211XLTS U2110 ( .A0(n2690), .A1(n2534), .B0(n2554), .C0(n2553), .Y(n1682)
);
OAI21XLTS U2111 ( .A0(n2534), .A1(n2562), .B0(n2536), .Y(n1685) );
OAI211XLTS U2112 ( .A0(n2616), .A1(n2620), .B0(n2615), .C0(n2614), .Y(n1655)
);
AOI2BB2XLTS U2113 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n2501), .A0N(n2622),
.A1N(n2672), .Y(n2614) );
OAI211XLTS U2114 ( .A0(n2682), .A1(n2681), .B0(n2680), .C0(n2679), .Y(n1668)
);
AOI2BB2XLTS U2115 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2678),
.A1N(n2534), .Y(n2679) );
OAI211XLTS U2116 ( .A0(n2557), .A1(n2620), .B0(n2556), .C0(n2555), .Y(n1667)
);
AOI2BB2XLTS U2117 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n2501), .A0N(n2604),
.A1N(n2689), .Y(n2555) );
AO22XLTS U2118 ( .A0(n2140), .A1(n2139), .B0(final_result_ieee[51]), .B1(
n3027), .Y(n1078) );
AO22XLTS U2119 ( .A0(n2140), .A1(n2136), .B0(final_result_ieee[50]), .B1(
n3000), .Y(n1079) );
AO22XLTS U2120 ( .A0(n2140), .A1(n2129), .B0(final_result_ieee[49]), .B1(
n3027), .Y(n1080) );
AO22XLTS U2121 ( .A0(n2140), .A1(n2871), .B0(final_result_ieee[0]), .B1(
n3000), .Y(n1081) );
AO22XLTS U2122 ( .A0(n2140), .A1(n2131), .B0(final_result_ieee[1]), .B1(
n3027), .Y(n1082) );
AO22XLTS U2123 ( .A0(n2140), .A1(n2137), .B0(final_result_ieee[47]), .B1(
n3000), .Y(n1083) );
AO22XLTS U2124 ( .A0(n2140), .A1(n2125), .B0(final_result_ieee[3]), .B1(
n3027), .Y(n1088) );
AO22XLTS U2125 ( .A0(n2140), .A1(n2130), .B0(final_result_ieee[48]), .B1(
n3000), .Y(n1089) );
AO22XLTS U2126 ( .A0(n2140), .A1(n2123), .B0(final_result_ieee[2]), .B1(
n3027), .Y(n1090) );
AO22XLTS U2127 ( .A0(n2140), .A1(n2124), .B0(final_result_ieee[45]), .B1(
n3000), .Y(n1093) );
AO22XLTS U2128 ( .A0(n2140), .A1(n3067), .B0(final_result_ieee[29]), .B1(
n3000), .Y(n1096) );
AO22XLTS U2129 ( .A0(n2140), .A1(n2127), .B0(final_result_ieee[21]), .B1(
n3000), .Y(n1097) );
AO22XLTS U2130 ( .A0(n2140), .A1(n2128), .B0(final_result_ieee[5]), .B1(
n3000), .Y(n1098) );
AO22XLTS U2131 ( .A0(n2140), .A1(n2122), .B0(final_result_ieee[46]), .B1(
n3000), .Y(n1103) );
AO22XLTS U2132 ( .A0(n3002), .A1(n2984), .B0(final_result_ieee[41]), .B1(
n3027), .Y(n1113) );
AO22XLTS U2133 ( .A0(n3002), .A1(n2982), .B0(final_result_ieee[25]), .B1(
n3000), .Y(n1115) );
AO22XLTS U2134 ( .A0(n3002), .A1(n2978), .B0(final_result_ieee[28]), .B1(
n3000), .Y(n1117) );
AO22XLTS U2135 ( .A0(n3002), .A1(n2977), .B0(final_result_ieee[22]), .B1(
n3000), .Y(n1118) );
AO22XLTS U2136 ( .A0(n3002), .A1(n3064), .B0(final_result_ieee[26]), .B1(
n3000), .Y(n1123) );
AO22XLTS U2137 ( .A0(n3002), .A1(n3063), .B0(final_result_ieee[24]), .B1(
n3000), .Y(n1124) );
AOI2BB2XLTS U2138 ( .B0(n2877), .B1(intadd_74_SUM_34_), .A0N(n1879), .A1N(
n2877), .Y(n1170) );
OAI211XLTS U2139 ( .A0(n2601), .A1(n2620), .B0(n2567), .C0(n2566), .Y(n1671)
);
AOI2BB2XLTS U2140 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n2501), .A0N(n2583),
.A1N(n2689), .Y(n2566) );
OAI211XLTS U2141 ( .A0(n2657), .A1(n2689), .B0(n2626), .C0(n2625), .Y(n1676)
);
AOI2BB2XLTS U2142 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[45]), .A0N(n2643),
.A1N(n2684), .Y(n2625) );
OAI211XLTS U2143 ( .A0(n2539), .A1(n2672), .B0(n2517), .C0(n2516), .Y(n1634)
);
OAI211XLTS U2144 ( .A0(n2669), .A1(n2672), .B0(n2542), .C0(n2541), .Y(n1643)
);
AOI2BB2XLTS U2145 ( .B0(n2683), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2663),
.A1N(n2684), .Y(n2541) );
OAI211XLTS U2146 ( .A0(n2617), .A1(n2620), .B0(n2589), .C0(n2588), .Y(n1644)
);
AOI2BB2XLTS U2147 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n2501), .A0N(n2607),
.A1N(n2681), .Y(n2588) );
OAI211XLTS U2148 ( .A0(n2673), .A1(n2672), .B0(n2671), .C0(n2670), .Y(n1645)
);
AOI2BB2XLTS U2149 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2669),
.A1N(n2684), .Y(n2670) );
OAI211XLTS U2150 ( .A0(n2607), .A1(n2620), .B0(n2606), .C0(n2605), .Y(n1646)
);
AOI2BB2XLTS U2151 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n2501), .A0N(n2631),
.A1N(n2689), .Y(n2605) );
OAI211XLTS U2152 ( .A0(n2545), .A1(n2672), .B0(n2544), .C0(n2543), .Y(n1647)
);
AOI2BB2XLTS U2153 ( .B0(n2683), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2673),
.A1N(n2684), .Y(n2543) );
OAI211XLTS U2154 ( .A0(n2651), .A1(n2672), .B0(n2633), .C0(n2632), .Y(n1648)
);
AOI2BB2XLTS U2155 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2631),
.A1N(n2684), .Y(n2632) );
OAI211XLTS U2156 ( .A0(n2545), .A1(n2684), .B0(n2533), .C0(n2532), .Y(n1649)
);
AOI2BB2XLTS U2157 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n2501), .A0N(n2565),
.A1N(n2689), .Y(n2532) );
OAI211XLTS U2158 ( .A0(n2654), .A1(n2672), .B0(n2653), .C0(n2652), .Y(n1650)
);
AOI2BB2XLTS U2159 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[19]), .A0N(n2651),
.A1N(n2684), .Y(n2652) );
OAI211XLTS U2160 ( .A0(n2600), .A1(n2620), .B0(n2599), .C0(n2598), .Y(n1653)
);
AOI2BB2XLTS U2161 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n2501), .A0N(n2616),
.A1N(n2689), .Y(n2598) );
OAI211XLTS U2162 ( .A0(n2548), .A1(n2672), .B0(n2547), .C0(n2546), .Y(n1656)
);
AOI2BB2XLTS U2163 ( .B0(n2683), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2667),
.A1N(n2684), .Y(n2546) );
OAI211XLTS U2164 ( .A0(n2611), .A1(n2620), .B0(n2610), .C0(n2609), .Y(n1664)
);
AOI2BB2XLTS U2165 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n2501), .A0N(n2634),
.A1N(n2689), .Y(n2609) );
OAI211XLTS U2166 ( .A0(n2678), .A1(n2681), .B0(n2636), .C0(n2635), .Y(n1666)
);
AOI2BB2XLTS U2167 ( .B0(n2686), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2634),
.A1N(n2684), .Y(n2635) );
OAI211XLTS U2168 ( .A0(n2604), .A1(n2620), .B0(n2603), .C0(n2602), .Y(n1669)
);
AOI2BB2XLTS U2169 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n2780), .A0N(n2601),
.A1N(n2689), .Y(n2602) );
OA22X1TS U2170 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3007), .B0(n3247), .B1(
n2082), .Y(n1843) );
OA22X1TS U2171 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3034), .B0(n3271), .B1(
n2082), .Y(n1844) );
OA22X1TS U2172 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2944), .B0(n3272), .B1(
n2082), .Y(n1845) );
OAI221X1TS U2173 ( .A0(n3250), .A1(intDX_EWSW[57]), .B0(n1853), .B1(
intDX_EWSW[56]), .C0(n1913), .Y(n1920) );
OAI221X1TS U2174 ( .A0(n3127), .A1(intDX_EWSW[27]), .B0(n3239), .B1(
intDX_EWSW[26]), .C0(n1942), .Y(n1945) );
BUFX6TS U2175 ( .A(n2816), .Y(n2349) );
BUFX6TS U2176 ( .A(n1905), .Y(n2816) );
BUFX6TS U2177 ( .A(n2915), .Y(n2957) );
AOI222X1TS U2178 ( .A0(n3009), .A1(left_right_SHT2), .B0(n3010), .B1(n3038),
.C0(n3011), .C1(n1999), .Y(n3070) );
AOI222X4TS U2179 ( .A0(n3009), .A1(n3037), .B0(n3010), .B1(n3036), .C0(n3011), .C1(n1983), .Y(n3060) );
AOI222X1TS U2180 ( .A0(n2946), .A1(n2952), .B0(n2947), .B1(n3038), .C0(n2948), .C1(n1999), .Y(n3068) );
AOI222X4TS U2181 ( .A0(n2946), .A1(n3037), .B0(n2947), .B1(n3036), .C0(n2948), .C1(n1983), .Y(n3062) );
AOI222X1TS U2182 ( .A0(n3040), .A1(left_right_SHT2), .B0(n3043), .B1(n3038),
.C0(n3044), .C1(n1999), .Y(n3069) );
AOI222X4TS U2183 ( .A0(n3040), .A1(n3037), .B0(n3043), .B1(n3036), .C0(n3044), .C1(n1983), .Y(n3061) );
AOI222X1TS U2184 ( .A0(n2997), .A1(left_right_SHT2), .B0(n2996), .B1(n1999),
.C0(n2995), .C1(n3036), .Y(n3079) );
AOI222X4TS U2185 ( .A0(n2997), .A1(n3149), .B0(n2996), .B1(n1983), .C0(n2995), .C1(n3038), .Y(n2994) );
AOI222X1TS U2186 ( .A0(n2972), .A1(left_right_SHT2), .B0(n2971), .B1(n1999),
.C0(n2970), .C1(n3036), .Y(n3080) );
AOI222X1TS U2187 ( .A0(n2981), .A1(left_right_SHT2), .B0(n2980), .B1(n1999),
.C0(n2979), .C1(n3036), .Y(n3077) );
AOI222X4TS U2188 ( .A0(n2981), .A1(n3037), .B0(n2980), .B1(n1983), .C0(n2979), .C1(n3038), .Y(n3054) );
AOI222X1TS U2189 ( .A0(n3022), .A1(left_right_SHT2), .B0(n3021), .B1(n1999),
.C0(n3020), .C1(n3036), .Y(n3076) );
OAI211XLTS U2190 ( .A0(n2525), .A1(n2672), .B0(n2513), .C0(n2512), .Y(n1633)
);
BUFX4TS U2191 ( .A(n3300), .Y(n2818) );
NAND2X4TS U2192 ( .A(n2744), .B(n3306), .Y(n2750) );
NOR4X2TS U2193 ( .A(n2166), .B(n2238), .C(n2250), .D(n2242), .Y(n2295) );
NAND2X1TS U2194 ( .A(shift_value_SHT2_EWR[4]), .B(n2956), .Y(n2082) );
BUFX4TS U2195 ( .A(n3352), .Y(n3329) );
INVX6TS U2196 ( .A(rst), .Y(n1907) );
BUFX4TS U2197 ( .A(n3310), .Y(n3338) );
BUFX4TS U2198 ( .A(n1908), .Y(n3348) );
BUFX4TS U2199 ( .A(n1907), .Y(n3340) );
BUFX4TS U2200 ( .A(n3348), .Y(n3333) );
BUFX4TS U2201 ( .A(n3354), .Y(n3347) );
BUFX4TS U2202 ( .A(n3335), .Y(n3336) );
BUFX4TS U2203 ( .A(n1832), .Y(n3352) );
BUFX4TS U2204 ( .A(n3353), .Y(n3345) );
BUFX4TS U2205 ( .A(n3354), .Y(n3326) );
INVX2TS U2206 ( .A(n1841), .Y(n1859) );
BUFX4TS U2207 ( .A(n2823), .Y(n2820) );
BUFX6TS U2208 ( .A(n3305), .Y(n2823) );
BUFX4TS U2209 ( .A(n3340), .Y(n3328) );
BUFX4TS U2210 ( .A(n3335), .Y(n3344) );
BUFX4TS U2211 ( .A(n3326), .Y(n3337) );
BUFX4TS U2212 ( .A(n3327), .Y(n3330) );
BUFX4TS U2213 ( .A(n3340), .Y(n3334) );
BUFX4TS U2214 ( .A(n3340), .Y(n3342) );
BUFX4TS U2215 ( .A(n3353), .Y(n3343) );
BUFX4TS U2216 ( .A(n3320), .Y(n3316) );
BUFX4TS U2217 ( .A(n3314), .Y(n3320) );
BUFX4TS U2218 ( .A(n3318), .Y(n3310) );
BUFX4TS U2219 ( .A(n3353), .Y(n3315) );
BUFX4TS U2220 ( .A(n3336), .Y(n3313) );
BUFX4TS U2221 ( .A(n3317), .Y(n3323) );
BUFX4TS U2222 ( .A(n3335), .Y(n3308) );
BUFX4TS U2223 ( .A(n3353), .Y(n3314) );
BUFX4TS U2224 ( .A(n3317), .Y(n3309) );
BUFX4TS U2225 ( .A(n3349), .Y(n3318) );
INVX2TS U2226 ( .A(n1844), .Y(n1860) );
INVX2TS U2227 ( .A(n1845), .Y(n1861) );
INVX2TS U2228 ( .A(n1843), .Y(n1862) );
XNOR2X2TS U2229 ( .A(DMP_exp_NRM2_EW[10]), .B(n2115), .Y(n2126) );
BUFX4TS U2230 ( .A(n2526), .Y(n2608) );
BUFX4TS U2231 ( .A(n2817), .Y(n3071) );
AOI222X1TS U2232 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[6]), .C0(n2612), .C1(DmP_mant_SHT1_SW[5]), .Y(n2580)
);
AOI222X1TS U2233 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[7]), .C0(n2612), .C1(DmP_mant_SHT1_SW[6]), .Y(n2529)
);
INVX4TS U2234 ( .A(n1978), .Y(n2956) );
CLKINVX6TS U2235 ( .A(n1978), .Y(n2918) );
AOI222X1TS U2236 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2656), .B0(n2587), .B1(
DmP_mant_SHT1_SW[45]), .C0(n2612), .C1(DmP_mant_SHT1_SW[44]), .Y(n2590) );
AOI222X1TS U2237 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[43]), .C0(n2612), .C1(DmP_mant_SHT1_SW[42]), .Y(n2593) );
AOI222X1TS U2238 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1825), .B0(n2587), .B1(
DmP_mant_SHT1_SW[41]), .C0(n2586), .C1(DmP_mant_SHT1_SW[40]), .Y(n2583) );
AOI222X1TS U2239 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1825), .B0(n2613), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2586), .C1(DmP_mant_SHT1_SW[33]), .Y(n2634) );
CLKINVX3TS U2240 ( .A(n2349), .Y(n1863) );
OAI211XLTS U2241 ( .A0(n2529), .A1(n2672), .B0(n2521), .C0(n2520), .Y(n1637)
);
BUFX6TS U2242 ( .A(n2613), .Y(n2587) );
CLKINVX3TS U2243 ( .A(n2823), .Y(n1864) );
AOI22X2TS U2244 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[12]), .B0(n1900),
.B1(n2881), .Y(n2937) );
CLKINVX6TS U2245 ( .A(OP_FLAG_SFG), .Y(n2881) );
AOI222X4TS U2246 ( .A0(n3273), .A1(n2907), .B0(n3273), .B1(n2858), .C0(n2907), .C1(n2858), .Y(n2935) );
AOI22X2TS U2247 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n3102), .B0(n2887), .B1(
n1899), .Y(n2907) );
CLKINVX6TS U2248 ( .A(left_right_SHT2), .Y(n3037) );
BUFX4TS U2249 ( .A(n2349), .Y(n2755) );
BUFX4TS U2250 ( .A(n2349), .Y(n2417) );
BUFX6TS U2251 ( .A(n2349), .Y(n2438) );
CLKINVX6TS U2252 ( .A(n3306), .Y(n3000) );
BUFX4TS U2253 ( .A(n2787), .Y(n2791) );
BUFX6TS U2254 ( .A(n2496), .Y(n2787) );
CLKINVX6TS U2255 ( .A(n3306), .Y(n3027) );
CLKINVX6TS U2256 ( .A(n2558), .Y(n2612) );
INVX4TS U2257 ( .A(n2558), .Y(n2586) );
OAI21X2TS U2258 ( .A0(n3247), .A1(n2913), .B0(n2912), .Y(n2965) );
CLKINVX6TS U2259 ( .A(n2913), .Y(n2954) );
INVX4TS U2260 ( .A(n3071), .Y(n2825) );
INVX4TS U2261 ( .A(n3071), .Y(n2822) );
INVX4TS U2262 ( .A(n2817), .Y(n2872) );
INVX4TS U2263 ( .A(n2817), .Y(n3084) );
BUFX6TS U2264 ( .A(n2083), .Y(n3042) );
INVX4TS U2265 ( .A(n2318), .Y(n2413) );
INVX4TS U2266 ( .A(n2318), .Y(n2410) );
INVX4TS U2267 ( .A(n2318), .Y(n2431) );
INVX4TS U2268 ( .A(n2318), .Y(n2433) );
BUFX6TS U2269 ( .A(n3003), .Y(n3041) );
INVX4TS U2270 ( .A(n3071), .Y(n3082) );
INVX4TS U2271 ( .A(n2817), .Y(n2830) );
INVX4TS U2272 ( .A(n2817), .Y(n3078) );
CLKINVX6TS U2273 ( .A(n2824), .Y(n2821) );
CLKINVX6TS U2274 ( .A(n2938), .Y(n2904) );
CLKINVX6TS U2275 ( .A(n2938), .Y(n2877) );
CLKINVX6TS U2276 ( .A(n2938), .Y(n2940) );
OAI21XLTS U2277 ( .A0(DMP_SFG[11]), .A1(n1859), .B0(n2444), .Y(
intadd_74_B_0_) );
OAI211XLTS U2278 ( .A0(n2529), .A1(n2684), .B0(n2528), .C0(n2527), .Y(n1639)
);
OAI211XLTS U2279 ( .A0(n2621), .A1(n2672), .B0(n2509), .C0(n2508), .Y(n1640)
);
OAI211XLTS U2280 ( .A0(n2621), .A1(n2620), .B0(n2619), .C0(n2618), .Y(n1642)
);
AOI211X1TS U2281 ( .A0(n2468), .A1(Raw_mant_NRM_SWR[44]), .B0(n1879), .C0(
Raw_mant_NRM_SWR[47]), .Y(n2470) );
INVX2TS U2282 ( .A(n1851), .Y(n1865) );
AOI22X2TS U2283 ( .A0(Data_array_SWR[39]), .A1(n2957), .B0(
Data_array_SWR[35]), .B1(n2956), .Y(n3008) );
OAI211XLTS U2284 ( .A0(n2643), .A1(n2672), .B0(n2642), .C0(n2641), .Y(n1674)
);
INVX2TS U2285 ( .A(n1850), .Y(n1866) );
OAI211XLTS U2286 ( .A0(n2590), .A1(n2620), .B0(n2569), .C0(n2568), .Y(n1677)
);
INVX2TS U2287 ( .A(n1849), .Y(n1867) );
INVX2TS U2288 ( .A(n1857), .Y(n1868) );
INVX2TS U2289 ( .A(n1855), .Y(n1869) );
INVX2TS U2290 ( .A(n1852), .Y(n1870) );
INVX2TS U2291 ( .A(n1833), .Y(n1871) );
OAI211XLTS U2292 ( .A0(n2576), .A1(n2620), .B0(n2575), .C0(n2574), .Y(n1679)
);
OAI211XLTS U2293 ( .A0(n2644), .A1(n2672), .B0(n2630), .C0(n2629), .Y(n1670)
);
OAI221X1TS U2294 ( .A0(n3279), .A1(intDX_EWSW[7]), .B0(n3143), .B1(
intDX_EWSW[6]), .C0(n2193), .Y(n1968) );
INVX2TS U2295 ( .A(n1837), .Y(n1872) );
INVX2TS U2296 ( .A(n1838), .Y(n1873) );
INVX2TS U2297 ( .A(n1848), .Y(n1874) );
INVX2TS U2298 ( .A(n1836), .Y(n1875) );
OAI211XLTS U2299 ( .A0(n2677), .A1(n2681), .B0(n2676), .C0(n2675), .Y(n1663)
);
INVX2TS U2300 ( .A(n1835), .Y(n1876) );
INVX2TS U2301 ( .A(n1839), .Y(n1877) );
OAI221XLTS U2302 ( .A0(n3230), .A1(intDX_EWSW[9]), .B0(n3257), .B1(
intDX_EWSW[16]), .C0(n1957), .Y(n1958) );
AOI221X1TS U2303 ( .A0(n3287), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3261), .C0(n1935), .Y(n1938) );
AOI21X2TS U2304 ( .A0(Data_array_SWR[17]), .A1(n2957), .B0(n1980), .Y(n2135)
);
AOI222X1TS U2305 ( .A0(intDX_EWSW[4]), .A1(n3130), .B0(intDX_EWSW[5]), .B1(
n3249), .C0(n2192), .C1(n2191), .Y(n2194) );
OAI221X1TS U2306 ( .A0(n3232), .A1(intDX_EWSW[13]), .B0(n3130), .B1(
intDX_EWSW[4]), .C0(n1955), .Y(n1960) );
OAI211XLTS U2307 ( .A0(n2674), .A1(n2681), .B0(n2650), .C0(n2649), .Y(n1661)
);
INVX2TS U2308 ( .A(n1856), .Y(n1878) );
INVX2TS U2309 ( .A(n1840), .Y(n1879) );
INVX2TS U2310 ( .A(n1834), .Y(n1880) );
OAI211XLTS U2311 ( .A0(n2504), .A1(n2534), .B0(n2503), .C0(n2502), .Y(n1632)
);
NOR4X2TS U2312 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2729) );
BUFX4TS U2313 ( .A(n3354), .Y(n3311) );
OAI211X2TS U2314 ( .A0(intDY_EWSW[20]), .A1(n3212), .B0(n2229), .C0(n2183),
.Y(n2223) );
OAI211X2TS U2315 ( .A0(intDY_EWSW[12]), .A1(n3189), .B0(n2210), .C0(n2184),
.Y(n2214) );
XNOR2X2TS U2316 ( .A(DMP_exp_NRM2_EW[8]), .B(n2108), .Y(n2748) );
OAI211X2TS U2317 ( .A0(intDY_EWSW[28]), .A1(n3188), .B0(n2182), .C0(n2173),
.Y(n2232) );
XNOR2X2TS U2318 ( .A(DMP_exp_NRM2_EW[0]), .B(n2691), .Y(n2745) );
XNOR2X2TS U2319 ( .A(DMP_exp_NRM2_EW[9]), .B(n2111), .Y(n2749) );
AOI211X1TS U2320 ( .A0(shift_value_SHT2_EWR[5]), .A1(n3028), .B0(n2089),
.C0(n2088), .Y(n2096) );
OAI22X2TS U2321 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3026), .B0(n3270), .B1(
n2082), .Y(n3028) );
NOR2X4TS U2322 ( .A(n2497), .B(n2496), .Y(n2778) );
XNOR2X2TS U2323 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J76_123_4372_n6), .Y(
n2746) );
AOI2BB2X2TS U2324 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n2887), .A0N(n2887), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n2879) );
AOI2BB2X2TS U2325 ( .B0(DmP_mant_SFG_SWR[5]), .B1(n3102), .A0N(n2881), .A1N(
DmP_mant_SFG_SWR[5]), .Y(n2886) );
AOI2BB2X2TS U2326 ( .B0(n2896), .B1(DmP_mant_SFG_SWR[7]), .A0N(
DmP_mant_SFG_SWR[7]), .A1N(n2887), .Y(n2895) );
AOI2BB2X2TS U2327 ( .B0(n2896), .B1(DmP_mant_SFG_SWR[9]), .A0N(
DmP_mant_SFG_SWR[9]), .A1N(n2887), .Y(n2906) );
OAI211XLTS U2328 ( .A0(n2539), .A1(n2684), .B0(n2538), .C0(n2537), .Y(n1636)
);
OAI211XLTS U2329 ( .A0(n2525), .A1(n2684), .B0(n2524), .C0(n2523), .Y(n1635)
);
BUFX4TS U2330 ( .A(n1988), .Y(n3038) );
BUFX4TS U2331 ( .A(n1987), .Y(n3036) );
AOI22X2TS U2332 ( .A0(Data_array_SWR[37]), .A1(n2957), .B0(
Data_array_SWR[33]), .B1(n2956), .Y(n2945) );
CLKINVX6TS U2333 ( .A(n2910), .Y(n2932) );
BUFX4TS U2334 ( .A(n2938), .Y(n2910) );
BUFX3TS U2335 ( .A(n3305), .Y(n2842) );
INVX3TS U2336 ( .A(n2976), .Y(n3002) );
OAI211XLTS U2337 ( .A0(n2663), .A1(n2672), .B0(n2662), .C0(n2661), .Y(n1641)
);
OAI31XLTS U2338 ( .A0(n2442), .A1(n2441), .A2(n2839), .B0(n2440), .Y(n1543)
);
OAI222X1TS U2339 ( .A0(n2839), .A1(n3298), .B0(n3092), .B1(n1863), .C0(n3088), .C1(n2837), .Y(n1226) );
INVX3TS U2340 ( .A(n2367), .Y(n2839) );
CLKINVX6TS U2341 ( .A(OP_FLAG_SFG), .Y(n2853) );
BUFX6TS U2342 ( .A(OP_FLAG_SFG), .Y(n2887) );
INVX3TS U2343 ( .A(n3306), .Y(n3052) );
BUFX6TS U2344 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3306) );
CLKINVX6TS U2345 ( .A(n3300), .Y(n2828) );
NAND2X1TS U2346 ( .A(n2738), .B(n2507), .Y(n2742) );
NAND2X2TS U2347 ( .A(n2498), .B(n2738), .Y(n2743) );
BUFX6TS U2348 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2738) );
XOR2XLTS U2349 ( .A(n2935), .B(DMP_SFG[10]), .Y(n2936) );
NOR2X1TS U2350 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n2710) );
OAI211XLTS U2351 ( .A0(n2583), .A1(n2620), .B0(n2582), .C0(n2581), .Y(n1673)
);
OAI211XLTS U2352 ( .A0(n2647), .A1(n2681), .B0(n2646), .C0(n2645), .Y(n1672)
);
AOI22X2TS U2353 ( .A0(Data_array_SWR[34]), .A1(n2956), .B0(
Data_array_SWR[38]), .B1(n2957), .Y(n3035) );
AOI22X2TS U2354 ( .A0(Data_array_SWR[32]), .A1(n2918), .B0(
Data_array_SWR[36]), .B1(n2957), .Y(n3019) );
OAI211XLTS U2355 ( .A0(n2593), .A1(n2620), .B0(n2592), .C0(n2591), .Y(n1675)
);
NOR2X2TS U2356 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3252), .Y(n2754) );
OAI221X1TS U2357 ( .A0(n3255), .A1(intDX_EWSW[61]), .B0(n3253), .B1(
intDX_EWSW[60]), .C0(n1915), .Y(n1918) );
OAI221XLTS U2358 ( .A0(n3248), .A1(intDX_EWSW[0]), .B0(n3131), .B1(
intDX_EWSW[8]), .C0(n1964), .Y(n1965) );
NOR2X1TS U2359 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2698)
);
OAI2BB2XLTS U2360 ( .B0(n2491), .B1(n3109), .A0N(n2695), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n2153) );
AOI32X1TS U2361 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2695), .A2(n3109), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2695), .Y(n2147) );
OAI211XLTS U2362 ( .A0(n2557), .A1(n2672), .B0(n2550), .C0(n2549), .Y(n1665)
);
OAI211XLTS U2363 ( .A0(n2667), .A1(n2672), .B0(n2666), .C0(n2665), .Y(n1654)
);
NOR2BX1TS U2364 ( .AN(n2493), .B(Raw_mant_NRM_SWR[16]), .Y(n2459) );
OAI221X1TS U2365 ( .A0(n3124), .A1(intDX_EWSW[17]), .B0(n3238), .B1(
intDX_EWSW[24]), .C0(n1950), .Y(n1951) );
OAI221X1TS U2366 ( .A0(n3128), .A1(intDX_EWSW[3]), .B0(n3234), .B1(
intDX_EWSW[2]), .C0(n1963), .Y(n1966) );
OAI221X1TS U2367 ( .A0(n3126), .A1(intDX_EWSW[25]), .B0(n3241), .B1(
intDX_EWSW[32]), .C0(n1943), .Y(n1944) );
AOI211XLTS U2368 ( .A0(intDX_EWSW[16]), .A1(n3257), .B0(n2218), .C0(n2224),
.Y(n2215) );
OAI221X1TS U2369 ( .A0(n3231), .A1(intDX_EWSW[10]), .B0(n3235), .B1(
intDX_EWSW[12]), .C0(n1956), .Y(n1959) );
OAI221X1TS U2370 ( .A0(n3233), .A1(intDX_EWSW[21]), .B0(n3242), .B1(
intDX_EWSW[48]), .C0(n1948), .Y(n1953) );
OAI211XLTS U2371 ( .A0(n2594), .A1(n2620), .B0(n2585), .C0(n2584), .Y(n1662)
);
AOI211X2TS U2372 ( .A0(intDX_EWSW[44]), .A1(n3267), .B0(n2252), .C0(n2261),
.Y(n2259) );
AOI21X2TS U2373 ( .A0(Data_array_SWR[19]), .A1(n2957), .B0(n1846), .Y(n2993)
);
AOI211X1TS U2374 ( .A0(intDX_EWSW[52]), .A1(n3281), .B0(n2165), .C0(n2284),
.Y(n2286) );
AOI222X1TS U2375 ( .A0(n2410), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n1905), .C0(intDY_EWSW[52]), .C1(n2367), .Y(n2320) );
AOI21X2TS U2376 ( .A0(Data_array_SWR[18]), .A1(n2957), .B0(n1847), .Y(n2033)
);
OAI211XLTS U2377 ( .A0(n2565), .A1(n2620), .B0(n2564), .C0(n2563), .Y(n1651)
);
OAI211XLTS U2378 ( .A0(n2638), .A1(n2681), .B0(n2624), .C0(n2623), .Y(n1657)
);
NOR3X1TS U2379 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .C(
n2709), .Y(n2143) );
NOR2X1TS U2380 ( .A(Raw_mant_NRM_SWR[47]), .B(n2142), .Y(n2148) );
OAI221XLTS U2381 ( .A0(n3249), .A1(intDX_EWSW[5]), .B0(n3240), .B1(
intDX_EWSW[28]), .C0(n1962), .Y(n1967) );
NAND2X2TS U2382 ( .A(n3190), .B(shift_value_SHT2_EWR[5]), .Y(n3018) );
NOR2X2TS U2383 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n1993) );
NOR2X4TS U2384 ( .A(n3190), .B(shift_value_SHT2_EWR[5]), .Y(n3045) );
OAI21XLTS U2385 ( .A0(intDX_EWSW[1]), .A1(n3275), .B0(intDX_EWSW[0]), .Y(
n2187) );
OAI21XLTS U2386 ( .A0(intDY_EWSW[35]), .A1(n3111), .B0(intDY_EWSW[34]), .Y(
n2270) );
OAI21XLTS U2387 ( .A0(intDY_EWSW[33]), .A1(n3185), .B0(intDY_EWSW[32]), .Y(
n2269) );
NOR2XLTS U2388 ( .A(n2218), .B(intDX_EWSW[16]), .Y(n2219) );
OAI21XLTS U2389 ( .A0(intDY_EWSW[55]), .A1(n3299), .B0(intDY_EWSW[54]), .Y(
n2294) );
OAI21XLTS U2390 ( .A0(intDY_EWSW[23]), .A1(n3113), .B0(intDY_EWSW[22]), .Y(
n2225) );
NAND2X1TS U2391 ( .A(n2693), .B(n3086), .Y(n2158) );
OAI21XLTS U2392 ( .A0(n3282), .A1(n1978), .B0(n2065), .Y(n2066) );
NOR2BX1TS U2393 ( .AN(n2699), .B(n2700), .Y(n2493) );
NOR2XLTS U2394 ( .A(n2110), .B(n2749), .Y(n2113) );
OAI211XLTS U2395 ( .A0(DMP_SFG[5]), .A1(n2895), .B0(DMP_SFG[4]), .C0(n2901),
.Y(n2894) );
OAI211XLTS U2396 ( .A0(n2993), .A1(n1986), .B0(n2045), .C0(n2044), .Y(n2046)
);
NOR3X1TS U2397 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n2728), .Y(n2156) );
NAND2X1TS U2398 ( .A(n2459), .B(n3169), .Y(n2725) );
OAI211XLTS U2399 ( .A0(n3107), .A1(n2737), .B0(n2736), .C0(n2735), .Y(n2739)
);
OAI21XLTS U2400 ( .A0(n3137), .A1(n2838), .B0(n2342), .Y(n1261) );
OAI21XLTS U2401 ( .A0(n3262), .A1(n2435), .B0(n2428), .Y(n1563) );
OAI21XLTS U2402 ( .A0(n3142), .A1(n2427), .B0(n2386), .Y(n1577) );
OAI21XLTS U2403 ( .A0(n3124), .A1(n2412), .B0(n2409), .Y(n1591) );
OAI21XLTS U2404 ( .A0(n3128), .A1(n2412), .B0(n2392), .Y(n1605) );
OAI211XLTS U2405 ( .A0(n2580), .A1(n2620), .B0(n2579), .C0(n2578), .Y(n1638)
);
OAI211XLTS U2406 ( .A0(n2664), .A1(n2672), .B0(n2628), .C0(n2627), .Y(n1652)
);
BUFX3TS U2407 ( .A(n3335), .Y(n3332) );
BUFX3TS U2408 ( .A(n3340), .Y(n3331) );
BUFX3TS U2409 ( .A(n3354), .Y(n3341) );
BUFX3TS U2410 ( .A(n3353), .Y(n3339) );
BUFX3TS U2411 ( .A(n3353), .Y(n3319) );
BUFX3TS U2412 ( .A(n3311), .Y(n3321) );
BUFX3TS U2413 ( .A(n3335), .Y(n3327) );
BUFX3TS U2414 ( .A(n3340), .Y(n3325) );
BUFX3TS U2415 ( .A(n3335), .Y(n3350) );
BUFX3TS U2416 ( .A(n3354), .Y(n3349) );
BUFX3TS U2417 ( .A(n3354), .Y(n3351) );
BUFX3TS U2418 ( .A(n3347), .Y(n3324) );
BUFX3TS U2419 ( .A(n3340), .Y(n3346) );
BUFX3TS U2420 ( .A(n3326), .Y(n3312) );
BUFX3TS U2421 ( .A(n3317), .Y(n3307) );
BUFX3TS U2422 ( .A(n3354), .Y(n3322) );
INVX4TS U2423 ( .A(n2738), .Y(n2757) );
AO22XLTS U2424 ( .A0(n2738), .A1(SIGN_FLAG_NRM), .B0(n2757), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1206) );
AO22XLTS U2425 ( .A0(n2738), .A1(ZERO_FLAG_NRM), .B0(n2757), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1215) );
AOI22X1TS U2426 ( .A0(n3132), .A1(intDX_EWSW[11]), .B0(n3251), .B1(
intDX_EWSW[49]), .Y(n1909) );
OAI221XLTS U2427 ( .A0(n3132), .A1(intDX_EWSW[11]), .B0(n3251), .B1(
intDX_EWSW[49]), .C0(n1909), .Y(n1910) );
AOI221X1TS U2428 ( .A0(intDY_EWSW[1]), .A1(n3256), .B0(n3275), .B1(
intDX_EWSW[1]), .C0(n1910), .Y(n1924) );
OAI22X1TS U2429 ( .A0(n3281), .A1(intDX_EWSW[52]), .B0(n3088), .B1(
intDX_EWSW[53]), .Y(n1911) );
AOI221X1TS U2430 ( .A0(n3281), .A1(intDX_EWSW[52]), .B0(intDX_EWSW[53]),
.B1(n3088), .C0(n1911), .Y(n1923) );
OAI22X1TS U2431 ( .A0(n3269), .A1(intDX_EWSW[50]), .B0(n3135), .B1(
intDX_EWSW[51]), .Y(n1912) );
AOI221X1TS U2432 ( .A0(n3269), .A1(intDX_EWSW[50]), .B0(intDX_EWSW[51]),
.B1(n3135), .C0(n1912), .Y(n1922) );
AOI22X1TS U2433 ( .A0(n3250), .A1(intDX_EWSW[57]), .B0(n1853), .B1(
intDX_EWSW[56]), .Y(n1913) );
AOI22X1TS U2434 ( .A0(n1854), .A1(intDX_EWSW[55]), .B0(n3087), .B1(
intDX_EWSW[54]), .Y(n1914) );
OAI221XLTS U2435 ( .A0(n1854), .A1(intDX_EWSW[55]), .B0(n3087), .B1(
intDX_EWSW[54]), .C0(n1914), .Y(n1919) );
AOI22X1TS U2436 ( .A0(n3255), .A1(intDX_EWSW[61]), .B0(n3253), .B1(
intDX_EWSW[60]), .Y(n1915) );
AOI22X1TS U2437 ( .A0(n3133), .A1(intDX_EWSW[59]), .B0(n3254), .B1(
intDX_EWSW[58]), .Y(n1916) );
OAI221XLTS U2438 ( .A0(n3133), .A1(intDX_EWSW[59]), .B0(n3254), .B1(
intDX_EWSW[58]), .C0(n1916), .Y(n1917) );
NOR4X1TS U2439 ( .A(n1918), .B(n1919), .C(n1920), .D(n1917), .Y(n1921) );
NAND4XLTS U2440 ( .A(n1924), .B(n1923), .C(n1922), .D(n1921), .Y(n1976) );
OAI22X1TS U2441 ( .A0(n3266), .A1(intDX_EWSW[42]), .B0(n3139), .B1(
intDX_EWSW[43]), .Y(n1925) );
AOI221X1TS U2442 ( .A0(n3266), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3139), .C0(n1925), .Y(n1932) );
OAI22X1TS U2443 ( .A0(n3265), .A1(intDX_EWSW[40]), .B0(n3138), .B1(
intDX_EWSW[41]), .Y(n1926) );
AOI221X1TS U2444 ( .A0(n3265), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3138), .C0(n1926), .Y(n1931) );
OAI22X1TS U2445 ( .A0(n3268), .A1(intDX_EWSW[46]), .B0(n3134), .B1(
intDX_EWSW[47]), .Y(n1927) );
AOI221X1TS U2446 ( .A0(n3268), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3134), .C0(n1927), .Y(n1930) );
OAI22X1TS U2447 ( .A0(n3267), .A1(intDX_EWSW[44]), .B0(n3262), .B1(
intDX_EWSW[45]), .Y(n1928) );
AOI221X1TS U2448 ( .A0(n3267), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3262), .C0(n1928), .Y(n1929) );
NAND4XLTS U2449 ( .A(n1932), .B(n1931), .C(n1930), .D(n1929), .Y(n1975) );
OAI22X1TS U2450 ( .A0(n3263), .A1(intDX_EWSW[34]), .B0(n3137), .B1(
intDX_EWSW[35]), .Y(n1933) );
AOI221X1TS U2451 ( .A0(n3263), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3137), .C0(n1933), .Y(n1940) );
OAI22X1TS U2452 ( .A0(n3274), .A1(intDX_EWSW[62]), .B0(n3136), .B1(
intDX_EWSW[33]), .Y(n1934) );
AOI221X1TS U2453 ( .A0(n3274), .A1(intDX_EWSW[62]), .B0(intDX_EWSW[33]),
.B1(n3136), .C0(n1934), .Y(n1939) );
OAI22X1TS U2454 ( .A0(n3287), .A1(intDX_EWSW[38]), .B0(n3261), .B1(
intDX_EWSW[39]), .Y(n1935) );
OAI22X1TS U2455 ( .A0(n3264), .A1(intDX_EWSW[36]), .B0(n3260), .B1(
intDX_EWSW[37]), .Y(n1936) );
AOI221X1TS U2456 ( .A0(n3264), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3260), .C0(n1936), .Y(n1937) );
NAND4XLTS U2457 ( .A(n1940), .B(n1939), .C(n1938), .D(n1937), .Y(n1974) );
OA22X1TS U2458 ( .A0(n3191), .A1(intDY_EWSW[30]), .B0(n3112), .B1(
intDY_EWSW[31]), .Y(n2182) );
OAI221XLTS U2459 ( .A0(n3142), .A1(intDX_EWSW[31]), .B0(n3278), .B1(
intDX_EWSW[30]), .C0(n2182), .Y(n1947) );
AOI22X1TS U2460 ( .A0(n3129), .A1(intDX_EWSW[29]), .B0(n3237), .B1(
intDX_EWSW[20]), .Y(n1941) );
OAI221XLTS U2461 ( .A0(n3129), .A1(intDX_EWSW[29]), .B0(n3237), .B1(
intDX_EWSW[20]), .C0(n1941), .Y(n1946) );
AOI22X1TS U2462 ( .A0(n3127), .A1(intDX_EWSW[27]), .B0(n3239), .B1(
intDX_EWSW[26]), .Y(n1942) );
AOI22X1TS U2463 ( .A0(n3126), .A1(intDX_EWSW[25]), .B0(n3241), .B1(
intDX_EWSW[32]), .Y(n1943) );
NOR4X1TS U2464 ( .A(n1944), .B(n1946), .C(n1945), .D(n1947), .Y(n1972) );
OA22X1TS U2465 ( .A0(n3213), .A1(intDY_EWSW[22]), .B0(n3113), .B1(
intDY_EWSW[23]), .Y(n2229) );
OAI221XLTS U2466 ( .A0(n3141), .A1(intDX_EWSW[23]), .B0(n3277), .B1(
intDX_EWSW[22]), .C0(n2229), .Y(n1954) );
AOI22X1TS U2467 ( .A0(n3233), .A1(intDX_EWSW[21]), .B0(n3242), .B1(
intDX_EWSW[48]), .Y(n1948) );
AOI22X1TS U2468 ( .A0(n3125), .A1(intDX_EWSW[19]), .B0(n3236), .B1(
intDX_EWSW[18]), .Y(n1949) );
OAI221XLTS U2469 ( .A0(n3125), .A1(intDX_EWSW[19]), .B0(n3236), .B1(
intDX_EWSW[18]), .C0(n1949), .Y(n1952) );
AOI22X1TS U2470 ( .A0(n3124), .A1(intDX_EWSW[17]), .B0(n3238), .B1(
intDX_EWSW[24]), .Y(n1950) );
NOR4X1TS U2471 ( .A(n1953), .B(n1954), .C(n1951), .D(n1952), .Y(n1971) );
OA22X1TS U2472 ( .A0(n3192), .A1(intDY_EWSW[14]), .B0(n3106), .B1(
intDY_EWSW[15]), .Y(n2210) );
OAI221XLTS U2473 ( .A0(n3140), .A1(intDX_EWSW[15]), .B0(n3276), .B1(
intDX_EWSW[14]), .C0(n2210), .Y(n1961) );
AOI22X1TS U2474 ( .A0(n3232), .A1(intDX_EWSW[13]), .B0(n3130), .B1(
intDX_EWSW[4]), .Y(n1955) );
AOI22X1TS U2475 ( .A0(n3231), .A1(intDX_EWSW[10]), .B0(n3235), .B1(
intDX_EWSW[12]), .Y(n1956) );
AOI22X1TS U2476 ( .A0(n3230), .A1(intDX_EWSW[9]), .B0(n3257), .B1(
intDX_EWSW[16]), .Y(n1957) );
NOR4X1TS U2477 ( .A(n1960), .B(n1961), .C(n1959), .D(n1958), .Y(n1970) );
AOI22X1TS U2478 ( .A0(intDX_EWSW[7]), .A1(n3279), .B0(intDX_EWSW[6]), .B1(
n3143), .Y(n2193) );
AOI22X1TS U2479 ( .A0(n3249), .A1(intDX_EWSW[5]), .B0(n3240), .B1(
intDX_EWSW[28]), .Y(n1962) );
AOI22X1TS U2480 ( .A0(n3128), .A1(intDX_EWSW[3]), .B0(n3234), .B1(
intDX_EWSW[2]), .Y(n1963) );
AOI22X1TS U2481 ( .A0(n3248), .A1(intDX_EWSW[0]), .B0(n3131), .B1(
intDX_EWSW[8]), .Y(n1964) );
NOR4X1TS U2482 ( .A(n1968), .B(n1967), .C(n1966), .D(n1965), .Y(n1969) );
NAND4XLTS U2483 ( .A(n1972), .B(n1971), .C(n1970), .D(n1969), .Y(n1973) );
NOR4X1TS U2484 ( .A(n1976), .B(n1975), .C(n1974), .D(n1973), .Y(n2442) );
CLKXOR2X2TS U2485 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2436) );
OAI21XLTS U2486 ( .A0(n2436), .A1(intDX_EWSW[63]), .B0(n1863), .Y(n1977) );
AOI21X1TS U2487 ( .A0(n2436), .A1(intDX_EWSW[63]), .B0(n1977), .Y(n2815) );
AO22XLTS U2488 ( .A0(n2442), .A1(n2815), .B0(ZERO_FLAG_EXP), .B1(n1905), .Y(
n1544) );
NAND2X1TS U2489 ( .A(Shift_reg_FLAGS_7[3]), .B(n3052), .Y(n2863) );
BUFX4TS U2490 ( .A(n1829), .Y(n2845) );
NAND2X1TS U2491 ( .A(shift_value_SHT2_EWR[2]), .B(n3200), .Y(n1994) );
NOR2X1TS U2492 ( .A(shift_value_SHT2_EWR[2]), .B(n3200), .Y(n2013) );
INVX2TS U2493 ( .A(n2013), .Y(n2913) );
NAND2X1TS U2494 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2010) );
AOI22X1TS U2495 ( .A0(Data_array_SWR[14]), .A1(n2956), .B0(n1872), .B1(n2914), .Y(n1979) );
OAI2BB1X1TS U2496 ( .A0N(Data_array_SWR[21]), .A1N(n2954), .B0(n1979), .Y(
n1980) );
BUFX3TS U2497 ( .A(left_right_SHT2), .Y(n2952) );
INVX2TS U2498 ( .A(n2913), .Y(n2084) );
AOI22X1TS U2499 ( .A0(Data_array_SWR[29]), .A1(n2914), .B0(
Data_array_SWR[26]), .B1(n2954), .Y(n1985) );
AOI22X1TS U2500 ( .A0(n1872), .A1(n2915), .B0(Data_array_SWR[21]), .B1(n2918), .Y(n1984) );
NAND2X1TS U2501 ( .A(n1985), .B(n1984), .Y(n3020) );
NOR2XLTS U2502 ( .A(n3149), .B(n1986), .Y(n1987) );
INVX2TS U2503 ( .A(n3019), .Y(n2132) );
AOI22X1TS U2504 ( .A0(n1983), .A1(n3020), .B0(n3036), .B1(n2132), .Y(n1992)
);
NOR2XLTS U2505 ( .A(n2952), .B(n1986), .Y(n1988) );
AOI22X1TS U2506 ( .A0(Data_array_SWR[32]), .A1(n2954), .B0(
Data_array_SWR[36]), .B1(n2914), .Y(n1990) );
AOI22X1TS U2507 ( .A0(Data_array_SWR[29]), .A1(n2957), .B0(
Data_array_SWR[26]), .B1(n2918), .Y(n1989) );
NAND2X2TS U2508 ( .A(n1990), .B(n1989), .Y(n3021) );
NAND2X1TS U2509 ( .A(n3038), .B(n3021), .Y(n1991) );
OAI211X1TS U2510 ( .A0(n2135), .A1(n1981), .B0(n1992), .C0(n1991), .Y(n2127)
);
AO22XLTS U2511 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[23]), .B0(n2872), .B1(
n2127), .Y(n1068) );
AOI222X4TS U2512 ( .A0(Data_array_SWR[32]), .A1(n2915), .B0(
Data_array_SWR[29]), .B1(n2956), .C0(Data_array_SWR[36]), .C1(n2954),
.Y(n2933) );
INVX2TS U2513 ( .A(n1993), .Y(n1995) );
NOR2X1TS U2514 ( .A(n1995), .B(n2913), .Y(n3003) );
NOR2X1TS U2515 ( .A(n1978), .B(n1995), .Y(n2067) );
AOI22X1TS U2516 ( .A0(n1872), .A1(n3041), .B0(Data_array_SWR[17]), .B1(n1858), .Y(n1997) );
OR2X1TS U2517 ( .A(n1995), .B(n2010), .Y(n2968) );
NOR2X1TS U2518 ( .A(n1995), .B(n1994), .Y(n2083) );
AOI22X1TS U2519 ( .A0(Data_array_SWR[26]), .A1(n1828), .B0(
Data_array_SWR[21]), .B1(n3042), .Y(n1996) );
OAI211X1TS U2520 ( .A0(n2933), .A1(n1986), .B0(n1997), .C0(n1996), .Y(n2982)
);
AO22XLTS U2521 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[27]), .B0(n2872), .B1(
n2982), .Y(n1064) );
AOI22X1TS U2522 ( .A0(Data_array_SWR[22]), .A1(n2084), .B0(
Data_array_SWR[15]), .B1(n2956), .Y(n1998) );
AOI22X1TS U2523 ( .A0(Data_array_SWR[28]), .A1(n2914), .B0(n1865), .B1(n2954), .Y(n2001) );
AOI22X1TS U2524 ( .A0(Data_array_SWR[20]), .A1(n2918), .B0(
Data_array_SWR[23]), .B1(n2957), .Y(n2000) );
NAND2X1TS U2525 ( .A(n2001), .B(n2000), .Y(n2979) );
AOI22X1TS U2526 ( .A0(Data_array_SWR[37]), .A1(n2914), .B0(
Data_array_SWR[33]), .B1(n2954), .Y(n2003) );
AOI22X1TS U2527 ( .A0(Data_array_SWR[30]), .A1(n2957), .B0(n1867), .B1(n2918), .Y(n2002) );
NAND2X2TS U2528 ( .A(n2003), .B(n2002), .Y(n2980) );
AOI22X1TS U2529 ( .A0(n1999), .A1(n2979), .B0(n3036), .B1(n2980), .Y(n2005)
);
AOI222X4TS U2530 ( .A0(Data_array_SWR[39]), .A1(n2954), .B0(
Data_array_SWR[35]), .B1(n2915), .C0(Data_array_SWR[31]), .C1(n2918),
.Y(n2975) );
INVX2TS U2531 ( .A(n2975), .Y(n2006) );
NAND2X1TS U2532 ( .A(n3038), .B(n2006), .Y(n2004) );
OAI211X1TS U2533 ( .A0(n2033), .A1(n1982), .B0(n2005), .C0(n2004), .Y(n2978)
);
AO22XLTS U2534 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[30]), .B0(n3082), .B1(
n2978), .Y(n1061) );
AOI22X1TS U2535 ( .A0(n1983), .A1(n2979), .B0(n3036), .B1(n2006), .Y(n2008)
);
NAND2X1TS U2536 ( .A(n3038), .B(n2980), .Y(n2007) );
OAI211X1TS U2537 ( .A0(n2033), .A1(n1981), .B0(n2008), .C0(n2007), .Y(n2977)
);
AO22XLTS U2538 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[24]), .B0(n2872), .B1(
n2977), .Y(n1067) );
AOI22X1TS U2539 ( .A0(n1880), .A1(n2956), .B0(n1874), .B1(n2084), .Y(n2009)
);
AOI22X1TS U2540 ( .A0(Data_array_SWR[27]), .A1(n2914), .B0(
Data_array_SWR[25]), .B1(n2954), .Y(n2012) );
AOI22X1TS U2541 ( .A0(n1874), .A1(n2957), .B0(Data_array_SWR[19]), .B1(n2918), .Y(n2011) );
NAND2X1TS U2542 ( .A(n2012), .B(n2011), .Y(n2995) );
AOI222X4TS U2543 ( .A0(Data_array_SWR[34]), .A1(n2915), .B0(n1866), .B1(
n2918), .C0(Data_array_SWR[38]), .C1(n2013), .Y(n2998) );
INVX2TS U2544 ( .A(n2998), .Y(n2989) );
AOI22X1TS U2545 ( .A0(n1983), .A1(n2995), .B0(n3036), .B1(n2989), .Y(n2017)
);
AOI22X1TS U2546 ( .A0(Data_array_SWR[34]), .A1(n2954), .B0(
Data_array_SWR[38]), .B1(n2914), .Y(n2015) );
AOI22X1TS U2547 ( .A0(n1866), .A1(n2957), .B0(Data_array_SWR[27]), .B1(n2918), .Y(n2014) );
NAND2X2TS U2548 ( .A(n2015), .B(n2014), .Y(n2996) );
NAND2X1TS U2549 ( .A(n3038), .B(n2996), .Y(n2016) );
OAI211X1TS U2550 ( .A0(n2993), .A1(n1981), .B0(n2017), .C0(n2016), .Y(n2988)
);
AO22XLTS U2551 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[25]), .B0(n2872), .B1(
n2988), .Y(n1066) );
AOI22X1TS U2552 ( .A0(n1870), .A1(n3041), .B0(Data_array_SWR[11]), .B1(n3042), .Y(n2020) );
AOI22X1TS U2553 ( .A0(n1875), .A1(n1828), .B0(Data_array_SWR[7]), .B1(n1858),
.Y(n2019) );
OAI211XLTS U2554 ( .A0(n2135), .A1(n1986), .B0(n2020), .C0(n2019), .Y(n2021)
);
AOI21X1TS U2555 ( .A0(n2018), .A1(n3021), .B0(n2021), .Y(n2030) );
OAI22X1TS U2556 ( .A0(n2030), .A1(n3037), .B0(n3019), .B1(n1981), .Y(n2124)
);
AO22XLTS U2557 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[47]), .B0(n3084), .B1(
n2124), .Y(n1044) );
AOI22X1TS U2558 ( .A0(Data_array_SWR[31]), .A1(n2914), .B0(
Data_array_SWR[28]), .B1(n2084), .Y(n2023) );
AOI22X1TS U2559 ( .A0(Data_array_SWR[23]), .A1(n2956), .B0(n1865), .B1(n2957), .Y(n2022) );
NAND2X1TS U2560 ( .A(n2023), .B(n2022), .Y(n3011) );
AOI22X1TS U2561 ( .A0(Data_array_SWR[20]), .A1(n2914), .B0(
Data_array_SWR[16]), .B1(n2954), .Y(n2025) );
AOI22X1TS U2562 ( .A0(n1878), .A1(n2915), .B0(n1873), .B1(n2918), .Y(n2024)
);
AOI21X1TS U2563 ( .A0(n2025), .A1(n2024), .B0(n1986), .Y(n2029) );
NAND2X1TS U2564 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2054) );
AOI22X1TS U2565 ( .A0(n1871), .A1(n1828), .B0(Data_array_SWR[2]), .B1(n1858),
.Y(n2027) );
AOI22X1TS U2566 ( .A0(Data_array_SWR[10]), .A1(n3041), .B0(Data_array_SWR[6]), .B1(n3042), .Y(n2026) );
OAI211XLTS U2567 ( .A0(n3008), .A1(n2054), .B0(n2027), .C0(n2026), .Y(n2028)
);
AOI211X1TS U2568 ( .A0(n2018), .A1(n3011), .B0(n2029), .C0(n2028), .Y(n2138)
);
NAND2X1TS U2569 ( .A(n1858), .B(n3037), .Y(n2090) );
OAI22X1TS U2570 ( .A0(n2138), .A1(n3149), .B0(n3247), .B1(n2090), .Y(n2136)
);
AO22XLTS U2571 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[52]), .B0(n3084), .B1(
n2136), .Y(n1039) );
OAI22X1TS U2572 ( .A0(n2952), .A1(n2030), .B0(n3019), .B1(n1982), .Y(n2128)
);
AO22XLTS U2573 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[7]), .B0(n2872), .B1(n2128), .Y(n1143) );
AOI22X1TS U2574 ( .A0(n1876), .A1(n3041), .B0(n1869), .B1(n3042), .Y(n2032)
);
AOI22X1TS U2575 ( .A0(Data_array_SWR[12]), .A1(n1828), .B0(Data_array_SWR[8]), .B1(n1858), .Y(n2031) );
OAI211XLTS U2576 ( .A0(n2033), .A1(n1986), .B0(n2032), .C0(n2031), .Y(n2034)
);
AOI21X1TS U2577 ( .A0(n2018), .A1(n2980), .B0(n2034), .Y(n2047) );
OAI22X1TS U2578 ( .A0(n2047), .A1(n3037), .B0(n2975), .B1(n1981), .Y(n2986)
);
AO22XLTS U2579 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[46]), .B0(n2872), .B1(
n2986), .Y(n1045) );
BUFX4TS U2580 ( .A(n1829), .Y(n2829) );
AOI22X1TS U2581 ( .A0(Data_array_SWR[30]), .A1(n2914), .B0(n1867), .B1(n2084), .Y(n2036) );
AOI22X1TS U2582 ( .A0(Data_array_SWR[22]), .A1(n2956), .B0(
Data_array_SWR[24]), .B1(n2957), .Y(n2035) );
NAND2X1TS U2583 ( .A(n2036), .B(n2035), .Y(n2948) );
AOI22X1TS U2584 ( .A0(Data_array_SWR[18]), .A1(n2914), .B0(
Data_array_SWR[15]), .B1(n2954), .Y(n2038) );
AOI22X1TS U2585 ( .A0(n1876), .A1(n2918), .B0(Data_array_SWR[12]), .B1(n2957), .Y(n2037) );
AOI21X1TS U2586 ( .A0(n2038), .A1(n2037), .B0(n1986), .Y(n2042) );
AOI22X1TS U2587 ( .A0(n1869), .A1(n1828), .B0(Data_array_SWR[0]), .B1(n1858),
.Y(n2040) );
AOI22X1TS U2588 ( .A0(Data_array_SWR[8]), .A1(n3041), .B0(Data_array_SWR[4]),
.B1(n3042), .Y(n2039) );
OAI211XLTS U2589 ( .A0(n2945), .A1(n2054), .B0(n2040), .C0(n2039), .Y(n2041)
);
AOI211X1TS U2590 ( .A0(n2018), .A1(n2948), .B0(n2042), .C0(n2041), .Y(n2867)
);
OAI22X1TS U2591 ( .A0(n2867), .A1(n3037), .B0(n3272), .B1(n2090), .Y(n2043)
);
AO22XLTS U2592 ( .A0(n2829), .A1(DmP_mant_SFG_SWR[54]), .B0(n2872), .B1(
n2043), .Y(n1037) );
AOI22X1TS U2593 ( .A0(n1877), .A1(n3041), .B0(n1868), .B1(n3042), .Y(n2045)
);
AOI22X1TS U2594 ( .A0(Data_array_SWR[13]), .A1(n1828), .B0(Data_array_SWR[9]), .B1(n1858), .Y(n2044) );
AOI21X1TS U2595 ( .A0(n2018), .A1(n2996), .B0(n2046), .Y(n2999) );
OAI22X1TS U2596 ( .A0(left_right_SHT2), .A1(n2999), .B0(n2998), .B1(n1982),
.Y(n2987) );
AO22XLTS U2597 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[9]), .B0(n2872), .B1(n2987), .Y(n1139) );
OAI22X1TS U2598 ( .A0(n2952), .A1(n2047), .B0(n2975), .B1(n1982), .Y(n2985)
);
AO22XLTS U2599 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[8]), .B0(n2872), .B1(n2985), .Y(n1132) );
AOI22X1TS U2600 ( .A0(n1866), .A1(n2914), .B0(Data_array_SWR[27]), .B1(n2084), .Y(n2049) );
AOI22X1TS U2601 ( .A0(Data_array_SWR[25]), .A1(n2915), .B0(n1874), .B1(n2956), .Y(n2048) );
NAND2X1TS U2602 ( .A(n2049), .B(n2048), .Y(n3044) );
AOI22X1TS U2603 ( .A0(n1880), .A1(n2954), .B0(Data_array_SWR[19]), .B1(n2914), .Y(n2051) );
AOI22X1TS U2604 ( .A0(Data_array_SWR[13]), .A1(n2957), .B0(n1877), .B1(n2918), .Y(n2050) );
AOI21X1TS U2605 ( .A0(n2051), .A1(n2050), .B0(n1986), .Y(n2056) );
AOI22X1TS U2606 ( .A0(n1868), .A1(n1828), .B0(Data_array_SWR[1]), .B1(n1858),
.Y(n2053) );
AOI22X1TS U2607 ( .A0(Data_array_SWR[9]), .A1(n3041), .B0(Data_array_SWR[5]),
.B1(n3042), .Y(n2052) );
OAI211XLTS U2608 ( .A0(n3035), .A1(n2054), .B0(n2053), .C0(n2052), .Y(n2055)
);
AOI211X1TS U2609 ( .A0(n2018), .A1(n3044), .B0(n2056), .C0(n2055), .Y(n2862)
);
OAI22X1TS U2610 ( .A0(n2862), .A1(n3149), .B0(n3271), .B1(n2090), .Y(n2139)
);
AO22XLTS U2611 ( .A0(n2817), .A1(DmP_mant_SFG_SWR[53]), .B0(n2872), .B1(
n2139), .Y(n1038) );
BUFX3TS U2612 ( .A(n1829), .Y(n3085) );
AOI22X1TS U2613 ( .A0(Data_array_SWR[35]), .A1(n2914), .B0(
Data_array_SWR[31]), .B1(n2084), .Y(n2057) );
OAI2BB1X1TS U2614 ( .A0N(n1865), .A1N(n2956), .B0(n2057), .Y(n2058) );
AOI21X1TS U2615 ( .A0(Data_array_SWR[28]), .A1(n2957), .B0(n2058), .Y(n2944)
);
AO22XLTS U2616 ( .A0(Data_array_SWR[10]), .A1(n3042), .B0(Data_array_SWR[6]),
.B1(n1858), .Y(n2063) );
AOI22X1TS U2617 ( .A0(Data_array_SWR[20]), .A1(n2954), .B0(
Data_array_SWR[23]), .B1(n2914), .Y(n2061) );
AOI22X1TS U2618 ( .A0(n1871), .A1(n3041), .B0(n1873), .B1(n1828), .Y(n2060)
);
AOI22X1TS U2619 ( .A0(Data_array_SWR[16]), .A1(n2915), .B0(n1878), .B1(n2918), .Y(n2059) );
AOI32X1TS U2620 ( .A0(n2061), .A1(n2060), .A2(n2059), .B0(n1986), .B1(n2060),
.Y(n2062) );
AOI211X1TS U2621 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1861), .B0(n2063),
.C0(n2062), .Y(n2064) );
OAI22X1TS U2622 ( .A0(n2064), .A1(n3037), .B0(n2945), .B1(n1981), .Y(n2122)
);
AO22XLTS U2623 ( .A0(n3085), .A1(DmP_mant_SFG_SWR[48]), .B0(n3078), .B1(
n2122), .Y(n1043) );
OAI22X1TS U2624 ( .A0(n2952), .A1(n2064), .B0(n2945), .B1(n1982), .Y(n3001)
);
AO22XLTS U2625 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[6]), .B0(n2872), .B1(n3001), .Y(n1141) );
AOI22X1TS U2626 ( .A0(Data_array_SWR[34]), .A1(n2914), .B0(n1866), .B1(n2084), .Y(n2065) );
AOI21X1TS U2627 ( .A0(Data_array_SWR[27]), .A1(n2957), .B0(n2066), .Y(n3034)
);
AO22XLTS U2628 ( .A0(Data_array_SWR[9]), .A1(n3042), .B0(Data_array_SWR[5]),
.B1(n2067), .Y(n2072) );
AOI22X1TS U2629 ( .A0(n1874), .A1(n2914), .B0(Data_array_SWR[19]), .B1(n2954), .Y(n2070) );
AOI22X1TS U2630 ( .A0(n1877), .A1(n1828), .B0(n1868), .B1(n3041), .Y(n2069)
);
AOI22X1TS U2631 ( .A0(Data_array_SWR[13]), .A1(n2918), .B0(n1880), .B1(n2957), .Y(n2068) );
AOI32X1TS U2632 ( .A0(n2070), .A1(n2069), .A2(n2068), .B0(n1986), .B1(n2069),
.Y(n2071) );
OAI22X1TS U2633 ( .A0(n2098), .A1(n3037), .B0(n3035), .B1(n1981), .Y(n2137)
);
AO22XLTS U2634 ( .A0(n1829), .A1(DmP_mant_SFG_SWR[49]), .B0(n3078), .B1(
n2137), .Y(n1042) );
AOI22X1TS U2635 ( .A0(Data_array_SWR[33]), .A1(n2914), .B0(
Data_array_SWR[30]), .B1(n2084), .Y(n2073) );
OAI21XLTS U2636 ( .A0(n3283), .A1(n1978), .B0(n2073), .Y(n2074) );
AOI21X1TS U2637 ( .A0(n1867), .A1(n2957), .B0(n2074), .Y(n3007) );
AO22XLTS U2638 ( .A0(Data_array_SWR[8]), .A1(n3042), .B0(Data_array_SWR[4]),
.B1(n1858), .Y(n2079) );
AOI22X1TS U2639 ( .A0(Data_array_SWR[22]), .A1(n2914), .B0(
Data_array_SWR[18]), .B1(n2954), .Y(n2077) );
AOI22X1TS U2640 ( .A0(n1876), .A1(n1828), .B0(n1869), .B1(n3041), .Y(n2076)
);
AOI22X1TS U2641 ( .A0(Data_array_SWR[15]), .A1(n2915), .B0(
Data_array_SWR[12]), .B1(n2918), .Y(n2075) );
AOI32X1TS U2642 ( .A0(n2077), .A1(n2076), .A2(n2075), .B0(n1986), .B1(n2076),
.Y(n2078) );
AOI211X1TS U2643 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1862), .B0(n2079),
.C0(n2078), .Y(n2097) );
OAI22X1TS U2644 ( .A0(n2097), .A1(n3037), .B0(n3008), .B1(n1981), .Y(n2130)
);
AO22XLTS U2645 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[50]), .B0(n3084), .B1(
n2130), .Y(n1041) );
AOI22X1TS U2646 ( .A0(Data_array_SWR[32]), .A1(n2914), .B0(
Data_array_SWR[29]), .B1(n2084), .Y(n2080) );
OAI2BB1X1TS U2647 ( .A0N(Data_array_SWR[26]), .A1N(n2957), .B0(n2080), .Y(
n2081) );
AOI21X1TS U2648 ( .A0(n1872), .A1(n2918), .B0(n2081), .Y(n3026) );
AO22XLTS U2649 ( .A0(Data_array_SWR[7]), .A1(n2083), .B0(Data_array_SWR[3]),
.B1(n1858), .Y(n2089) );
AOI22X1TS U2650 ( .A0(Data_array_SWR[21]), .A1(n2914), .B0(
Data_array_SWR[17]), .B1(n2954), .Y(n2087) );
AOI22X1TS U2651 ( .A0(n1870), .A1(n1828), .B0(Data_array_SWR[11]), .B1(n3041), .Y(n2086) );
AOI22X1TS U2652 ( .A0(Data_array_SWR[14]), .A1(n2915), .B0(n1875), .B1(n2918), .Y(n2085) );
AOI32X1TS U2653 ( .A0(n2087), .A1(n2086), .A2(n2085), .B0(n1986), .B1(n2086),
.Y(n2088) );
OAI22X1TS U2654 ( .A0(n2096), .A1(n3149), .B0(n3270), .B1(n2090), .Y(n2129)
);
AO22XLTS U2655 ( .A0(n2817), .A1(DmP_mant_SFG_SWR[51]), .B0(n3084), .B1(
n2129), .Y(n1040) );
AOI22X1TS U2656 ( .A0(n1875), .A1(n3041), .B0(n1870), .B1(n3042), .Y(n2092)
);
AOI22X1TS U2657 ( .A0(Data_array_SWR[14]), .A1(n1828), .B0(
Data_array_SWR[11]), .B1(n1858), .Y(n2091) );
OAI211X1TS U2658 ( .A0(n2933), .A1(n3018), .B0(n2092), .C0(n2091), .Y(n2095)
);
AO22XLTS U2659 ( .A0(Data_array_SWR[26]), .A1(n2914), .B0(n1872), .B1(n2954),
.Y(n2094) );
AO22XLTS U2660 ( .A0(Data_array_SWR[21]), .A1(n2957), .B0(Data_array_SWR[17]), .B1(n2918), .Y(n2093) );
OAI32X1TS U2661 ( .A0(n2095), .A1(n2094), .A2(n2093), .B0(n3045), .B1(n2095),
.Y(n2934) );
OAI22X1TS U2662 ( .A0(n2933), .A1(n1981), .B0(n2934), .B1(n3037), .Y(n2984)
);
AO22XLTS U2663 ( .A0(n3085), .A1(DmP_mant_SFG_SWR[43]), .B0(n3084), .B1(
n2984), .Y(n1048) );
NAND2X1TS U2664 ( .A(n2952), .B(n1858), .Y(n2866) );
OAI22X1TS U2665 ( .A0(n2952), .A1(n2096), .B0(n3270), .B1(n2866), .Y(n2131)
);
AO22XLTS U2666 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[3]), .B0(n2872), .B1(n2131), .Y(n1150) );
OAI22X1TS U2667 ( .A0(n2952), .A1(n2097), .B0(n3008), .B1(n1982), .Y(n2123)
);
AO22XLTS U2668 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[4]), .B0(n2872), .B1(n2123), .Y(n1145) );
OAI22X1TS U2669 ( .A0(n3035), .A1(n1982), .B0(left_right_SHT2), .B1(n2098),
.Y(n2125) );
AO22XLTS U2670 ( .A0(n2845), .A1(DmP_mant_SFG_SWR[5]), .B0(n2872), .B1(n2125), .Y(n1147) );
INVX2TS U2671 ( .A(DP_OP_15J76_123_4372_n6), .Y(n2099) );
NAND2X1TS U2672 ( .A(n3244), .B(n2099), .Y(n2105) );
INVX2TS U2673 ( .A(n2105), .Y(n2100) );
NAND2X1TS U2674 ( .A(n3243), .B(n2100), .Y(n2108) );
INVX1TS U2675 ( .A(LZD_output_NRM2_EW[0]), .Y(n2691) );
NOR2XLTS U2676 ( .A(n2745), .B(exp_rslt_NRM2_EW1[1]), .Y(n2103) );
INVX2TS U2677 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2102) );
INVX2TS U2678 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2101) );
NAND4BXLTS U2679 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2103), .C(n2102), .D(n2101), .Y(n2104) );
NOR2XLTS U2680 ( .A(n2104), .B(exp_rslt_NRM2_EW1[5]), .Y(n2107) );
XNOR2X1TS U2681 ( .A(DMP_exp_NRM2_EW[7]), .B(n2105), .Y(n2747) );
INVX2TS U2682 ( .A(n2747), .Y(n2119) );
INVX2TS U2683 ( .A(n2746), .Y(n2106) );
NAND4BXLTS U2684 ( .AN(n2748), .B(n2107), .C(n2119), .D(n2106), .Y(n2110) );
INVX2TS U2685 ( .A(n2108), .Y(n2109) );
NAND2X1TS U2686 ( .A(n3258), .B(n2109), .Y(n2111) );
INVX2TS U2687 ( .A(n2111), .Y(n2112) );
NAND2X1TS U2688 ( .A(n3284), .B(n2112), .Y(n2115) );
NOR2BX1TS U2689 ( .AN(n2113), .B(n2126), .Y(n2114) );
INVX2TS U2690 ( .A(n2114), .Y(n2744) );
INVX2TS U2691 ( .A(n2744), .Y(n2851) );
INVX2TS U2692 ( .A(n2115), .Y(n2116) );
CLKAND2X2TS U2693 ( .A(n3292), .B(n2116), .Y(n2121) );
NAND4XLTS U2694 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n2745), .D(exp_rslt_NRM2_EW1[1]), .Y(n2117) );
NAND4BXLTS U2695 ( .AN(n2117), .B(n2746), .C(exp_rslt_NRM2_EW1[5]), .D(
exp_rslt_NRM2_EW1[4]), .Y(n2118) );
NOR3BXLTS U2696 ( .AN(n2748), .B(n2119), .C(n2118), .Y(n2120) );
NAND4XLTS U2697 ( .A(n2749), .B(n2121), .C(n2126), .D(n2120), .Y(n2850) );
NAND2X1TS U2698 ( .A(n3306), .B(n2850), .Y(n2841) );
INVX4TS U2699 ( .A(n2976), .Y(n2140) );
AO22XLTS U2700 ( .A0(n2140), .A1(n2126), .B0(n3052), .B1(
final_result_ieee[62]), .Y(n1609) );
AOI22X1TS U2701 ( .A0(n1999), .A1(n3020), .B0(n3036), .B1(n3021), .Y(n2134)
);
NAND2X1TS U2702 ( .A(n3038), .B(n2132), .Y(n2133) );
OAI211X1TS U2703 ( .A0(n2135), .A1(n1982), .B0(n2134), .C0(n2133), .Y(n3067)
);
OAI22X1TS U2704 ( .A0(n2952), .A1(n2138), .B0(n3247), .B1(n2866), .Y(n2871)
);
BUFX4TS U2705 ( .A(n3300), .Y(n2848) );
INVX4TS U2706 ( .A(n3300), .Y(n2849) );
BUFX4TS U2707 ( .A(n2787), .Y(n2668) );
NOR2X2TS U2708 ( .A(n2738), .B(n2848), .Y(n2790) );
AOI22X1TS U2709 ( .A0(n2668), .A1(shift_value_SHT2_EWR[3]), .B0(n2790), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2164) );
NAND2X1TS U2710 ( .A(n3096), .B(n3152), .Y(n2731) );
NOR2X2TS U2711 ( .A(n1879), .B(n2141), .Y(n2458) );
NOR2X2TS U2712 ( .A(Raw_mant_NRM_SWR[42]), .B(n2152), .Y(n2145) );
INVX2TS U2713 ( .A(n2461), .Y(n2716) );
NOR3X1TS U2714 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n2713), .Y(n2477) );
NOR2X2TS U2715 ( .A(Raw_mant_NRM_SWR[24]), .B(n2479), .Y(n2155) );
NAND2X2TS U2716 ( .A(n2144), .B(n3163), .Y(n2726) );
NOR3X2TS U2717 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n2726), .Y(n2699) );
NOR2X2TS U2718 ( .A(Raw_mant_NRM_SWR[12]), .B(n2737), .Y(n2693) );
NOR2X2TS U2719 ( .A(Raw_mant_NRM_SWR[10]), .B(n2158), .Y(n2694) );
NOR3X4TS U2720 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n2488),
.Y(n2695) );
AOI32X1TS U2721 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2145), .A2(n3193), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2145), .Y(n2146) );
OAI211X1TS U2722 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2147), .B0(n2717), .C0(
n2146), .Y(n2452) );
AOI32X1TS U2723 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2694), .A2(n3091), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2694), .Y(n2150) );
NAND2X1TS U2724 ( .A(Raw_mant_NRM_SWR[43]), .B(n2148), .Y(n2467) );
AOI21X1TS U2725 ( .A0(n2155), .A1(Raw_mant_NRM_SWR[23]), .B0(n2151), .Y(
n2464) );
OAI31X1TS U2726 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2153), .A2(
Raw_mant_NRM_SWR[40]), .B0(n2453), .Y(n2735) );
NOR3BX1TS U2727 ( .AN(n2458), .B(n2154), .C(Raw_mant_NRM_SWR[47]), .Y(n2161)
);
NAND2X1TS U2728 ( .A(n2155), .B(Raw_mant_NRM_SWR[22]), .Y(n2734) );
OAI2BB1X1TS U2729 ( .A0N(n2156), .A1N(Raw_mant_NRM_SWR[30]), .B0(n2734), .Y(
n2723) );
OAI22X1TS U2730 ( .A0(n3289), .A1(n2479), .B0(n3144), .B1(n2157), .Y(n2160)
);
OAI22X1TS U2731 ( .A0(n3091), .A1(n2488), .B0(n3288), .B1(n2158), .Y(n2159)
);
NOR4X1TS U2732 ( .A(n2161), .B(n2723), .C(n2160), .D(n2159), .Y(n2162) );
NAND4XLTS U2733 ( .A(n2464), .B(n2735), .C(n2162), .D(n2483), .Y(n2163) );
OAI21X1TS U2734 ( .A0(n2452), .A1(n2163), .B0(n2738), .Y(n2724) );
NAND2X1TS U2735 ( .A(n2164), .B(n2724), .Y(n1629) );
OAI21XLTS U2736 ( .A0(n2849), .A1(n3037), .B0(n2757), .Y(n1750) );
NOR2XLTS U2737 ( .A(n3298), .B(intDY_EWSW[53]), .Y(n2165) );
OAI22X1TS U2738 ( .A0(n3299), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3150), .Y(n2284) );
NOR2BX1TS U2739 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2166) );
NOR2X1TS U2740 ( .A(n3204), .B(intDY_EWSW[57]), .Y(n2238) );
NAND2BXLTS U2741 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2248) );
NAND2X1TS U2742 ( .A(n3255), .B(intDX_EWSW[61]), .Y(n2244) );
OAI211X1TS U2743 ( .A0(intDY_EWSW[60]), .A1(n3198), .B0(n2248), .C0(n2244),
.Y(n2250) );
NAND2BXLTS U2744 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2240) );
OAI21X1TS U2745 ( .A0(intDY_EWSW[58]), .A1(n3118), .B0(n2240), .Y(n2242) );
NOR2X1TS U2746 ( .A(n3218), .B(intDY_EWSW[49]), .Y(n2287) );
NAND2BXLTS U2747 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2289) );
OAI21X1TS U2748 ( .A0(intDY_EWSW[50]), .A1(n3117), .B0(n2289), .Y(n2293) );
AOI211X1TS U2749 ( .A0(intDX_EWSW[48]), .A1(n3242), .B0(n2287), .C0(n2293),
.Y(n2167) );
NAND3X1TS U2750 ( .A(n2286), .B(n2295), .C(n2167), .Y(n2303) );
NOR2BX1TS U2751 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2278) );
AOI21X1TS U2752 ( .A0(intDX_EWSW[38]), .A1(n3287), .B0(n2278), .Y(n2277) );
NAND2X1TS U2753 ( .A(n3260), .B(intDX_EWSW[37]), .Y(n2266) );
OAI211X1TS U2754 ( .A0(intDY_EWSW[36]), .A1(n3194), .B0(n2277), .C0(n2266),
.Y(n2268) );
NOR2X1TS U2755 ( .A(n3201), .B(intDY_EWSW[45]), .Y(n2252) );
NAND2BXLTS U2756 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2251) );
OAI21X1TS U2757 ( .A0(intDY_EWSW[46]), .A1(n3187), .B0(n2251), .Y(n2261) );
OA22X1TS U2758 ( .A0(n3209), .A1(intDY_EWSW[42]), .B0(n3110), .B1(
intDY_EWSW[43]), .Y(n2257) );
NAND2BXLTS U2759 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2169) );
NAND2BXLTS U2760 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2168) );
NAND4XLTS U2761 ( .A(n2259), .B(n2257), .C(n2169), .D(n2168), .Y(n2301) );
NAND2BXLTS U2762 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2170) );
OA22X1TS U2763 ( .A0(n3210), .A1(intDY_EWSW[34]), .B0(n3111), .B1(
intDY_EWSW[35]), .Y(n2272) );
OAI211XLTS U2764 ( .A0(n3185), .A1(intDY_EWSW[33]), .B0(n2170), .C0(n2272),
.Y(n2171) );
NOR4X1TS U2765 ( .A(n2303), .B(n2268), .C(n2301), .D(n2171), .Y(n2307) );
OAI21XLTS U2766 ( .A0(intDY_EWSW[29]), .A1(n3215), .B0(intDY_EWSW[28]), .Y(
n2172) );
OAI2BB2XLTS U2767 ( .B0(intDX_EWSW[28]), .B1(n2172), .A0N(intDY_EWSW[29]),
.A1N(n3215), .Y(n2181) );
NAND2BXLTS U2768 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2175) );
OAI21X1TS U2769 ( .A0(intDY_EWSW[26]), .A1(n3219), .B0(n2175), .Y(n2233) );
NAND2BXLTS U2770 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2173) );
NOR2X1TS U2771 ( .A(n3203), .B(intDY_EWSW[25]), .Y(n2230) );
NOR2XLTS U2772 ( .A(n2230), .B(intDX_EWSW[24]), .Y(n2174) );
AOI22X1TS U2773 ( .A0(n2174), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3203), .Y(n2177) );
AOI32X1TS U2774 ( .A0(n3219), .A1(n2175), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3119), .Y(n2176) );
OAI32X1TS U2775 ( .A0(n2233), .A1(n2232), .A2(n2177), .B0(n2176), .B1(n2232),
.Y(n2180) );
OAI21XLTS U2776 ( .A0(intDY_EWSW[31]), .A1(n3112), .B0(intDY_EWSW[30]), .Y(
n2178) );
OAI2BB2XLTS U2777 ( .B0(intDX_EWSW[30]), .B1(n2178), .A0N(intDY_EWSW[31]),
.A1N(n3112), .Y(n2179) );
AOI211X1TS U2778 ( .A0(n2182), .A1(n2181), .B0(n2180), .C0(n2179), .Y(n2237)
);
NAND2BXLTS U2779 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2183) );
NAND2BXLTS U2780 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2184) );
OAI2BB1X1TS U2781 ( .A0N(n3249), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2185) );
OAI22X1TS U2782 ( .A0(intDX_EWSW[4]), .A1(n2185), .B0(n3249), .B1(
intDX_EWSW[5]), .Y(n2196) );
OAI2BB1X1TS U2783 ( .A0N(n3279), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2186) );
OAI22X1TS U2784 ( .A0(intDX_EWSW[6]), .A1(n2186), .B0(n3279), .B1(
intDX_EWSW[7]), .Y(n2195) );
NAND2BXLTS U2785 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2189) );
AOI2BB2XLTS U2786 ( .B0(intDX_EWSW[1]), .B1(n3275), .A0N(intDY_EWSW[0]),
.A1N(n2187), .Y(n2188) );
OAI211XLTS U2787 ( .A0(n3184), .A1(intDY_EWSW[3]), .B0(n2189), .C0(n2188),
.Y(n2192) );
OAI21XLTS U2788 ( .A0(intDY_EWSW[3]), .A1(n3184), .B0(intDY_EWSW[2]), .Y(
n2190) );
AOI2BB2XLTS U2789 ( .B0(intDY_EWSW[3]), .B1(n3184), .A0N(intDX_EWSW[2]),
.A1N(n2190), .Y(n2191) );
OAI32X1TS U2790 ( .A0(n2196), .A1(n2195), .A2(n2194), .B0(n2193), .B1(n2195),
.Y(n2213) );
NAND2BXLTS U2791 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2200) );
NOR2X1TS U2792 ( .A(n3202), .B(intDY_EWSW[11]), .Y(n2198) );
AOI21X1TS U2793 ( .A0(intDX_EWSW[10]), .A1(n3231), .B0(n2198), .Y(n2203) );
OAI211XLTS U2794 ( .A0(intDY_EWSW[8]), .A1(n3221), .B0(n2200), .C0(n2203),
.Y(n2212) );
OAI21XLTS U2795 ( .A0(intDY_EWSW[13]), .A1(n3197), .B0(intDY_EWSW[12]), .Y(
n2197) );
OAI2BB2XLTS U2796 ( .B0(intDX_EWSW[12]), .B1(n2197), .A0N(intDY_EWSW[13]),
.A1N(n3197), .Y(n2209) );
NOR2XLTS U2797 ( .A(n2198), .B(intDX_EWSW[10]), .Y(n2199) );
AOI22X1TS U2798 ( .A0(intDY_EWSW[11]), .A1(n3202), .B0(intDY_EWSW[10]), .B1(
n2199), .Y(n2205) );
NAND3XLTS U2799 ( .A(n3221), .B(n2200), .C(intDY_EWSW[8]), .Y(n2202) );
AOI21X1TS U2800 ( .A0(n2202), .A1(n2201), .B0(n2214), .Y(n2204) );
OAI2BB2XLTS U2801 ( .B0(n2205), .B1(n2214), .A0N(n2204), .A1N(n2203), .Y(
n2208) );
OAI21XLTS U2802 ( .A0(intDY_EWSW[15]), .A1(n3106), .B0(intDY_EWSW[14]), .Y(
n2206) );
OAI2BB2XLTS U2803 ( .B0(intDX_EWSW[14]), .B1(n2206), .A0N(intDY_EWSW[15]),
.A1N(n3106), .Y(n2207) );
AOI211X1TS U2804 ( .A0(n2210), .A1(n2209), .B0(n2208), .C0(n2207), .Y(n2211)
);
OAI31X1TS U2805 ( .A0(n2214), .A1(n2213), .A2(n2212), .B0(n2211), .Y(n2216)
);
NOR2X1TS U2806 ( .A(n3217), .B(intDY_EWSW[17]), .Y(n2218) );
NAND2BXLTS U2807 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2220) );
OAI21X1TS U2808 ( .A0(intDY_EWSW[18]), .A1(n3220), .B0(n2220), .Y(n2224) );
NAND3BXLTS U2809 ( .AN(n2223), .B(n2216), .C(n2215), .Y(n2236) );
OAI21XLTS U2810 ( .A0(intDY_EWSW[21]), .A1(n3216), .B0(intDY_EWSW[20]), .Y(
n2217) );
OAI2BB2XLTS U2811 ( .B0(intDX_EWSW[20]), .B1(n2217), .A0N(intDY_EWSW[21]),
.A1N(n3216), .Y(n2228) );
AOI22X1TS U2812 ( .A0(n2219), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3217), .Y(n2222) );
AOI32X1TS U2813 ( .A0(n3220), .A1(n2220), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3120), .Y(n2221) );
OAI32X1TS U2814 ( .A0(n2224), .A1(n2223), .A2(n2222), .B0(n2221), .B1(n2223),
.Y(n2227) );
OAI2BB2XLTS U2815 ( .B0(intDX_EWSW[22]), .B1(n2225), .A0N(intDY_EWSW[23]),
.A1N(n3113), .Y(n2226) );
AOI211X1TS U2816 ( .A0(n2229), .A1(n2228), .B0(n2227), .C0(n2226), .Y(n2235)
);
NOR2BX1TS U2817 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2231) );
OR4X2TS U2818 ( .A(n2233), .B(n2232), .C(n2231), .D(n2230), .Y(n2234) );
AOI32X1TS U2819 ( .A0(n2237), .A1(n2236), .A2(n2235), .B0(n2234), .B1(n2237),
.Y(n2306) );
NOR2XLTS U2820 ( .A(n2238), .B(intDX_EWSW[56]), .Y(n2239) );
AOI22X1TS U2821 ( .A0(intDY_EWSW[57]), .A1(n3204), .B0(intDY_EWSW[56]), .B1(
n2239), .Y(n2243) );
AOI32X1TS U2822 ( .A0(n3118), .A1(n2240), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3226), .Y(n2241) );
OA21XLTS U2823 ( .A0(n2243), .A1(n2242), .B0(n2241), .Y(n2249) );
NAND3XLTS U2824 ( .A(n3198), .B(n2244), .C(intDY_EWSW[60]), .Y(n2245) );
OAI211XLTS U2825 ( .A0(intDX_EWSW[61]), .A1(n3255), .B0(n2246), .C0(n2245),
.Y(n2247) );
OAI2BB2XLTS U2826 ( .B0(n2250), .B1(n2249), .A0N(n2248), .A1N(n2247), .Y(
n2305) );
NOR2BX1TS U2827 ( .AN(n2251), .B(intDX_EWSW[46]), .Y(n2265) );
NOR2XLTS U2828 ( .A(n2252), .B(intDX_EWSW[44]), .Y(n2253) );
AOI22X1TS U2829 ( .A0(intDY_EWSW[45]), .A1(n3201), .B0(intDY_EWSW[44]), .B1(
n2253), .Y(n2262) );
OAI21XLTS U2830 ( .A0(intDY_EWSW[41]), .A1(n3196), .B0(intDY_EWSW[40]), .Y(
n2254) );
OAI2BB2XLTS U2831 ( .B0(intDX_EWSW[40]), .B1(n2254), .A0N(intDY_EWSW[41]),
.A1N(n3196), .Y(n2258) );
OAI21XLTS U2832 ( .A0(intDY_EWSW[43]), .A1(n3110), .B0(intDY_EWSW[42]), .Y(
n2255) );
OAI2BB2XLTS U2833 ( .B0(intDX_EWSW[42]), .B1(n2255), .A0N(intDY_EWSW[43]),
.A1N(n3110), .Y(n2256) );
AOI32X1TS U2834 ( .A0(n2259), .A1(n2258), .A2(n2257), .B0(n2256), .B1(n2259),
.Y(n2260) );
OAI21XLTS U2835 ( .A0(n2262), .A1(n2261), .B0(n2260), .Y(n2264) );
NOR2BX1TS U2836 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2263) );
AOI211XLTS U2837 ( .A0(intDY_EWSW[46]), .A1(n2265), .B0(n2264), .C0(n2263),
.Y(n2302) );
NAND3XLTS U2838 ( .A(n3194), .B(n2266), .C(intDY_EWSW[36]), .Y(n2267) );
OAI21XLTS U2839 ( .A0(intDX_EWSW[37]), .A1(n3260), .B0(n2267), .Y(n2276) );
INVX2TS U2840 ( .A(n2268), .Y(n2274) );
OAI2BB2XLTS U2841 ( .B0(intDX_EWSW[32]), .B1(n2269), .A0N(intDY_EWSW[33]),
.A1N(n3185), .Y(n2273) );
OAI2BB2XLTS U2842 ( .B0(intDX_EWSW[34]), .B1(n2270), .A0N(intDY_EWSW[35]),
.A1N(n3111), .Y(n2271) );
AOI32X1TS U2843 ( .A0(n2274), .A1(n2273), .A2(n2272), .B0(n2271), .B1(n2274),
.Y(n2275) );
OAI2BB1X1TS U2844 ( .A0N(n2277), .A1N(n2276), .B0(n2275), .Y(n2282) );
NOR2BX1TS U2845 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2281) );
NOR3X1TS U2846 ( .A(n3287), .B(n2278), .C(intDX_EWSW[38]), .Y(n2280) );
INVX2TS U2847 ( .A(n2303), .Y(n2279) );
OAI31X1TS U2848 ( .A0(n2282), .A1(n2281), .A2(n2280), .B0(n2279), .Y(n2300)
);
OAI21XLTS U2849 ( .A0(intDY_EWSW[53]), .A1(n3298), .B0(intDY_EWSW[52]), .Y(
n2283) );
AOI2BB2XLTS U2850 ( .B0(intDY_EWSW[53]), .B1(n3298), .A0N(intDX_EWSW[52]),
.A1N(n2283), .Y(n2285) );
NOR2XLTS U2851 ( .A(n2285), .B(n2284), .Y(n2298) );
INVX2TS U2852 ( .A(n2286), .Y(n2292) );
NOR2XLTS U2853 ( .A(n2287), .B(intDX_EWSW[48]), .Y(n2288) );
AOI22X1TS U2854 ( .A0(intDY_EWSW[49]), .A1(n3218), .B0(intDY_EWSW[48]), .B1(
n2288), .Y(n2291) );
AOI32X1TS U2855 ( .A0(n3117), .A1(n2289), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3211), .Y(n2290) );
OAI32X1TS U2856 ( .A0(n2293), .A1(n2292), .A2(n2291), .B0(n2290), .B1(n2292),
.Y(n2297) );
OAI2BB2XLTS U2857 ( .B0(intDX_EWSW[54]), .B1(n2294), .A0N(intDY_EWSW[55]),
.A1N(n3299), .Y(n2296) );
OAI31X1TS U2858 ( .A0(n2298), .A1(n2297), .A2(n2296), .B0(n2295), .Y(n2299)
);
OAI221XLTS U2859 ( .A0(n2303), .A1(n2302), .B0(n2301), .B1(n2300), .C0(n2299), .Y(n2304) );
AOI211X1TS U2860 ( .A0(n2307), .A1(n2306), .B0(n2305), .C0(n2304), .Y(n2308)
);
NOR2XLTS U2861 ( .A(n2308), .B(n1905), .Y(n2309) );
AOI22X1TS U2862 ( .A0(intDX_EWSW[10]), .A1(n2367), .B0(DmP_EXP_EWSW[10]),
.B1(n2417), .Y(n2310) );
OAI21XLTS U2863 ( .A0(n3231), .A1(n2318), .B0(n2310), .Y(n1311) );
AOI22X1TS U2864 ( .A0(intDX_EWSW[22]), .A1(n2367), .B0(DmP_EXP_EWSW[22]),
.B1(n2349), .Y(n2311) );
OAI21XLTS U2865 ( .A0(n3277), .A1(n2318), .B0(n2311), .Y(n1287) );
BUFX4TS U2866 ( .A(n2318), .Y(n2838) );
AOI22X1TS U2867 ( .A0(intDX_EWSW[30]), .A1(n2367), .B0(DmP_EXP_EWSW[30]),
.B1(n2349), .Y(n2312) );
OAI21XLTS U2868 ( .A0(n3278), .A1(n2838), .B0(n2312), .Y(n1271) );
AOI22X1TS U2869 ( .A0(DmP_EXP_EWSW[57]), .A1(n2349), .B0(intDX_EWSW[57]),
.B1(n2367), .Y(n2313) );
OAI21XLTS U2870 ( .A0(n3250), .A1(n2838), .B0(n2313), .Y(n1222) );
AOI22X1TS U2871 ( .A0(intDX_EWSW[28]), .A1(n2367), .B0(DmP_EXP_EWSW[28]),
.B1(n2438), .Y(n2314) );
OAI21XLTS U2872 ( .A0(n3240), .A1(n2838), .B0(n2314), .Y(n1275) );
BUFX4TS U2873 ( .A(n2318), .Y(n2837) );
AOI22X1TS U2874 ( .A0(intDX_EWSW[26]), .A1(n2367), .B0(DmP_EXP_EWSW[26]),
.B1(n2349), .Y(n2315) );
OAI21XLTS U2875 ( .A0(n3239), .A1(n2837), .B0(n2315), .Y(n1279) );
AOI22X1TS U2876 ( .A0(intDX_EWSW[7]), .A1(n2367), .B0(DmP_EXP_EWSW[7]), .B1(
n2438), .Y(n2316) );
OAI21XLTS U2877 ( .A0(n3279), .A1(n2318), .B0(n2316), .Y(n1317) );
AOI22X1TS U2878 ( .A0(intDX_EWSW[8]), .A1(n2367), .B0(DmP_EXP_EWSW[8]), .B1(
n2417), .Y(n2317) );
OAI21XLTS U2879 ( .A0(n3131), .A1(n2318), .B0(n2317), .Y(n1315) );
INVX2TS U2880 ( .A(n2319), .Y(n1227) );
INVX2TS U2881 ( .A(n2320), .Y(n1556) );
BUFX4TS U2882 ( .A(n2367), .Y(n2361) );
AOI22X1TS U2883 ( .A0(intDX_EWSW[14]), .A1(n2361), .B0(DmP_EXP_EWSW[14]),
.B1(n2349), .Y(n2321) );
OAI21XLTS U2884 ( .A0(n3276), .A1(n1827), .B0(n2321), .Y(n1303) );
BUFX4TS U2885 ( .A(n2367), .Y(n2354) );
AOI22X1TS U2886 ( .A0(intDX_EWSW[15]), .A1(n2354), .B0(DmP_EXP_EWSW[15]),
.B1(n2755), .Y(n2322) );
OAI21XLTS U2887 ( .A0(n3140), .A1(n1827), .B0(n2322), .Y(n1301) );
AOI22X1TS U2888 ( .A0(intDX_EWSW[12]), .A1(n2361), .B0(DmP_EXP_EWSW[12]),
.B1(n2417), .Y(n2323) );
OAI21XLTS U2889 ( .A0(n3235), .A1(n1827), .B0(n2323), .Y(n1307) );
AOI22X1TS U2890 ( .A0(intDX_EWSW[51]), .A1(n2354), .B0(DmP_EXP_EWSW[51]),
.B1(n2438), .Y(n2324) );
OAI21XLTS U2891 ( .A0(n3135), .A1(n1827), .B0(n2324), .Y(n1229) );
AOI22X1TS U2892 ( .A0(intDX_EWSW[49]), .A1(n2354), .B0(DmP_EXP_EWSW[49]),
.B1(n2438), .Y(n2325) );
OAI21XLTS U2893 ( .A0(n3251), .A1(n1827), .B0(n2325), .Y(n1233) );
AOI22X1TS U2894 ( .A0(intDX_EWSW[50]), .A1(n2354), .B0(DmP_EXP_EWSW[50]),
.B1(n2417), .Y(n2326) );
OAI21XLTS U2895 ( .A0(n3269), .A1(n1827), .B0(n2326), .Y(n1231) );
AOI22X1TS U2896 ( .A0(intDX_EWSW[43]), .A1(n2354), .B0(DmP_EXP_EWSW[43]),
.B1(n2438), .Y(n2327) );
OAI21XLTS U2897 ( .A0(n3139), .A1(n2837), .B0(n2327), .Y(n1245) );
AOI22X1TS U2898 ( .A0(intDX_EWSW[31]), .A1(n2361), .B0(DmP_EXP_EWSW[31]),
.B1(n2755), .Y(n2328) );
OAI21XLTS U2899 ( .A0(n3142), .A1(n2838), .B0(n2328), .Y(n1269) );
AOI22X1TS U2900 ( .A0(intDX_EWSW[33]), .A1(n2361), .B0(DmP_EXP_EWSW[33]),
.B1(n2755), .Y(n2329) );
OAI21XLTS U2901 ( .A0(n3136), .A1(n2838), .B0(n2329), .Y(n1265) );
AOI22X1TS U2902 ( .A0(intDX_EWSW[34]), .A1(n2361), .B0(DmP_EXP_EWSW[34]),
.B1(n2755), .Y(n2330) );
OAI21XLTS U2903 ( .A0(n3263), .A1(n2838), .B0(n2330), .Y(n1263) );
AOI22X1TS U2904 ( .A0(intDX_EWSW[42]), .A1(n2354), .B0(DmP_EXP_EWSW[42]),
.B1(n2755), .Y(n2331) );
OAI21XLTS U2905 ( .A0(n3266), .A1(n2837), .B0(n2331), .Y(n1247) );
AOI22X1TS U2906 ( .A0(intDX_EWSW[41]), .A1(n2361), .B0(DmP_EXP_EWSW[41]),
.B1(n2417), .Y(n2332) );
OAI21XLTS U2907 ( .A0(n3138), .A1(n2837), .B0(n2332), .Y(n1249) );
AOI22X1TS U2908 ( .A0(intDX_EWSW[29]), .A1(n2354), .B0(DmP_EXP_EWSW[29]),
.B1(n2438), .Y(n2333) );
OAI21XLTS U2909 ( .A0(n3129), .A1(n2838), .B0(n2333), .Y(n1273) );
AOI22X1TS U2910 ( .A0(intDX_EWSW[36]), .A1(n2361), .B0(DmP_EXP_EWSW[36]),
.B1(n2417), .Y(n2334) );
OAI21XLTS U2911 ( .A0(n3264), .A1(n2837), .B0(n2334), .Y(n1259) );
AOI22X1TS U2912 ( .A0(intDX_EWSW[19]), .A1(n2361), .B0(DmP_EXP_EWSW[19]),
.B1(n2349), .Y(n2335) );
OAI21XLTS U2913 ( .A0(n3125), .A1(n2837), .B0(n2335), .Y(n1293) );
AOI22X1TS U2914 ( .A0(intDX_EWSW[27]), .A1(n2354), .B0(DmP_EXP_EWSW[27]),
.B1(n2349), .Y(n2336) );
OAI21XLTS U2915 ( .A0(n3127), .A1(n2838), .B0(n2336), .Y(n1277) );
AOI22X1TS U2916 ( .A0(intDX_EWSW[45]), .A1(n2354), .B0(DmP_EXP_EWSW[45]),
.B1(n2417), .Y(n2337) );
OAI21XLTS U2917 ( .A0(n3262), .A1(n2837), .B0(n2337), .Y(n1241) );
AOI22X1TS U2918 ( .A0(intDX_EWSW[17]), .A1(n2361), .B0(DmP_EXP_EWSW[17]),
.B1(n2349), .Y(n2338) );
OAI21XLTS U2919 ( .A0(n3124), .A1(n2838), .B0(n2338), .Y(n1297) );
AOI22X1TS U2920 ( .A0(intDX_EWSW[25]), .A1(n2361), .B0(DmP_EXP_EWSW[25]),
.B1(n2438), .Y(n2339) );
OAI21XLTS U2921 ( .A0(n3126), .A1(n2837), .B0(n2339), .Y(n1281) );
AOI22X1TS U2922 ( .A0(intDX_EWSW[23]), .A1(n2354), .B0(DmP_EXP_EWSW[23]),
.B1(n2349), .Y(n2340) );
OAI21XLTS U2923 ( .A0(n3141), .A1(n2838), .B0(n2340), .Y(n1285) );
AOI22X1TS U2924 ( .A0(intDX_EWSW[20]), .A1(n2354), .B0(DmP_EXP_EWSW[20]),
.B1(n2349), .Y(n2341) );
OAI21XLTS U2925 ( .A0(n3237), .A1(n2837), .B0(n2341), .Y(n1291) );
AOI22X1TS U2926 ( .A0(intDX_EWSW[35]), .A1(n2361), .B0(DmP_EXP_EWSW[35]),
.B1(n2438), .Y(n2342) );
AOI22X1TS U2927 ( .A0(intDX_EWSW[46]), .A1(n2354), .B0(DmP_EXP_EWSW[46]),
.B1(n2438), .Y(n2343) );
OAI21XLTS U2928 ( .A0(n3268), .A1(n2837), .B0(n2343), .Y(n1239) );
AOI22X1TS U2929 ( .A0(intDX_EWSW[21]), .A1(n2354), .B0(DmP_EXP_EWSW[21]),
.B1(n2349), .Y(n2344) );
OAI21XLTS U2930 ( .A0(n3233), .A1(n2838), .B0(n2344), .Y(n1289) );
AOI22X1TS U2931 ( .A0(intDX_EWSW[18]), .A1(n2354), .B0(DmP_EXP_EWSW[18]),
.B1(n2349), .Y(n2345) );
OAI21XLTS U2932 ( .A0(n3236), .A1(n2838), .B0(n2345), .Y(n1295) );
AOI22X1TS U2933 ( .A0(intDX_EWSW[16]), .A1(n2361), .B0(DmP_EXP_EWSW[16]),
.B1(n2349), .Y(n2346) );
OAI21XLTS U2934 ( .A0(n3257), .A1(n1827), .B0(n2346), .Y(n1299) );
AOI22X1TS U2935 ( .A0(intDX_EWSW[48]), .A1(n2354), .B0(DmP_EXP_EWSW[48]),
.B1(n2755), .Y(n2347) );
OAI21XLTS U2936 ( .A0(n3242), .A1(n1827), .B0(n2347), .Y(n1235) );
AOI22X1TS U2937 ( .A0(intDX_EWSW[32]), .A1(n2361), .B0(DmP_EXP_EWSW[32]),
.B1(n2438), .Y(n2348) );
OAI21XLTS U2938 ( .A0(n3241), .A1(n2838), .B0(n2348), .Y(n1267) );
AOI22X1TS U2939 ( .A0(intDX_EWSW[24]), .A1(n2361), .B0(DmP_EXP_EWSW[24]),
.B1(n2349), .Y(n2350) );
OAI21XLTS U2940 ( .A0(n3238), .A1(n2838), .B0(n2350), .Y(n1283) );
AOI22X1TS U2941 ( .A0(intDX_EWSW[40]), .A1(n2361), .B0(DmP_EXP_EWSW[40]),
.B1(n2755), .Y(n2351) );
OAI21XLTS U2942 ( .A0(n3265), .A1(n2837), .B0(n2351), .Y(n1251) );
AOI22X1TS U2943 ( .A0(intDX_EWSW[39]), .A1(n2354), .B0(DmP_EXP_EWSW[39]),
.B1(n2417), .Y(n2352) );
OAI21XLTS U2944 ( .A0(n3261), .A1(n2837), .B0(n2352), .Y(n1253) );
AOI22X1TS U2945 ( .A0(intDX_EWSW[47]), .A1(n2354), .B0(DmP_EXP_EWSW[47]),
.B1(n2438), .Y(n2353) );
OAI21XLTS U2946 ( .A0(n3134), .A1(n2837), .B0(n2353), .Y(n1237) );
AOI22X1TS U2947 ( .A0(intDX_EWSW[44]), .A1(n2354), .B0(DmP_EXP_EWSW[44]),
.B1(n2417), .Y(n2355) );
OAI21XLTS U2948 ( .A0(n3267), .A1(n2837), .B0(n2355), .Y(n1243) );
AOI22X1TS U2949 ( .A0(intDX_EWSW[38]), .A1(n2361), .B0(DmP_EXP_EWSW[38]),
.B1(n2438), .Y(n2356) );
OAI21XLTS U2950 ( .A0(n3287), .A1(n2837), .B0(n2356), .Y(n1255) );
AOI22X1TS U2951 ( .A0(intDX_EWSW[37]), .A1(n2361), .B0(DmP_EXP_EWSW[37]),
.B1(n2755), .Y(n2357) );
OAI21XLTS U2952 ( .A0(n3260), .A1(n2837), .B0(n2357), .Y(n1257) );
AOI22X1TS U2953 ( .A0(intDX_EWSW[5]), .A1(n2367), .B0(DmP_EXP_EWSW[5]), .B1(
n2438), .Y(n2358) );
OAI21XLTS U2954 ( .A0(n3249), .A1(n1827), .B0(n2358), .Y(n1321) );
AOI22X1TS U2955 ( .A0(intDX_EWSW[1]), .A1(n2367), .B0(DmP_EXP_EWSW[1]), .B1(
n2417), .Y(n2359) );
OAI21XLTS U2956 ( .A0(n3275), .A1(n1827), .B0(n2359), .Y(n1329) );
AOI22X1TS U2957 ( .A0(intDX_EWSW[4]), .A1(n2367), .B0(DmP_EXP_EWSW[4]), .B1(
n2438), .Y(n2360) );
OAI21XLTS U2958 ( .A0(n3130), .A1(n1827), .B0(n2360), .Y(n1323) );
AOI22X1TS U2959 ( .A0(intDX_EWSW[13]), .A1(n2361), .B0(DmP_EXP_EWSW[13]),
.B1(n2755), .Y(n2362) );
OAI21XLTS U2960 ( .A0(n3232), .A1(n2837), .B0(n2362), .Y(n1305) );
AOI22X1TS U2961 ( .A0(intDX_EWSW[11]), .A1(n2367), .B0(DmP_EXP_EWSW[11]),
.B1(n2438), .Y(n2363) );
OAI21XLTS U2962 ( .A0(n3132), .A1(n2318), .B0(n2363), .Y(n1309) );
AOI22X1TS U2963 ( .A0(intDX_EWSW[0]), .A1(n2367), .B0(DmP_EXP_EWSW[0]), .B1(
n2755), .Y(n2364) );
OAI21XLTS U2964 ( .A0(n3248), .A1(n2318), .B0(n2364), .Y(n1331) );
AOI22X1TS U2965 ( .A0(intDX_EWSW[2]), .A1(n2367), .B0(DmP_EXP_EWSW[2]), .B1(
n2438), .Y(n2365) );
OAI21XLTS U2966 ( .A0(n3234), .A1(n2318), .B0(n2365), .Y(n1327) );
AOI22X1TS U2967 ( .A0(intDX_EWSW[9]), .A1(n2367), .B0(DmP_EXP_EWSW[9]), .B1(
n2755), .Y(n2366) );
OAI21XLTS U2968 ( .A0(n3230), .A1(n2318), .B0(n2366), .Y(n1313) );
AOI22X1TS U2969 ( .A0(intDX_EWSW[3]), .A1(n2367), .B0(DmP_EXP_EWSW[3]), .B1(
n2417), .Y(n2368) );
OAI21XLTS U2970 ( .A0(n3128), .A1(n2318), .B0(n2368), .Y(n1325) );
AOI22X1TS U2971 ( .A0(intDX_EWSW[6]), .A1(n2367), .B0(DmP_EXP_EWSW[6]), .B1(
n2438), .Y(n2369) );
OAI21XLTS U2972 ( .A0(n3143), .A1(n2318), .B0(n2369), .Y(n1319) );
AOI22X1TS U2973 ( .A0(intDX_EWSW[58]), .A1(n2433), .B0(DMP_EXP_EWSW[58]),
.B1(n2349), .Y(n2370) );
OAI21XLTS U2974 ( .A0(n3254), .A1(n2839), .B0(n2370), .Y(n1550) );
AOI22X1TS U2975 ( .A0(intDX_EWSW[62]), .A1(n2431), .B0(DMP_EXP_EWSW[62]),
.B1(n2417), .Y(n2371) );
OAI21XLTS U2976 ( .A0(n3274), .A1(n2839), .B0(n2371), .Y(n1546) );
AOI22X1TS U2977 ( .A0(intDX_EWSW[60]), .A1(n2433), .B0(DMP_EXP_EWSW[60]),
.B1(n2755), .Y(n2372) );
OAI21XLTS U2978 ( .A0(n3253), .A1(n2839), .B0(n2372), .Y(n1548) );
AOI22X1TS U2979 ( .A0(intDX_EWSW[0]), .A1(n2431), .B0(DMP_EXP_EWSW[0]), .B1(
n1905), .Y(n2373) );
OAI21XLTS U2980 ( .A0(n3248), .A1(n2839), .B0(n2373), .Y(n1608) );
INVX4TS U2981 ( .A(n2367), .Y(n2427) );
AOI22X1TS U2982 ( .A0(intDX_EWSW[5]), .A1(n2413), .B0(DMP_EXP_EWSW[5]), .B1(
n1905), .Y(n2374) );
OAI21XLTS U2983 ( .A0(n3249), .A1(n2427), .B0(n2374), .Y(n1603) );
INVX4TS U2984 ( .A(n2367), .Y(n2435) );
AOI22X1TS U2985 ( .A0(intDX_EWSW[61]), .A1(n2433), .B0(DMP_EXP_EWSW[61]),
.B1(n2755), .Y(n2375) );
OAI21XLTS U2986 ( .A0(n3255), .A1(n2435), .B0(n2375), .Y(n1547) );
INVX4TS U2987 ( .A(n2367), .Y(n2412) );
AOI22X1TS U2988 ( .A0(intDX_EWSW[7]), .A1(n2410), .B0(DMP_EXP_EWSW[7]), .B1(
n1905), .Y(n2376) );
OAI21XLTS U2989 ( .A0(n3279), .A1(n2412), .B0(n2376), .Y(n1601) );
AOI22X1TS U2990 ( .A0(intDX_EWSW[10]), .A1(n2413), .B0(DMP_EXP_EWSW[10]),
.B1(n2816), .Y(n2377) );
OAI21XLTS U2991 ( .A0(n3231), .A1(n2435), .B0(n2377), .Y(n1598) );
AOI22X1TS U2992 ( .A0(intDX_EWSW[15]), .A1(n2410), .B0(DMP_EXP_EWSW[15]),
.B1(n2816), .Y(n2378) );
OAI21XLTS U2993 ( .A0(n3140), .A1(n2412), .B0(n2378), .Y(n1593) );
AOI22X1TS U2994 ( .A0(intDX_EWSW[16]), .A1(n2413), .B0(DMP_EXP_EWSW[16]),
.B1(n2816), .Y(n2379) );
OAI21XLTS U2995 ( .A0(n3257), .A1(n2412), .B0(n2379), .Y(n1592) );
AOI22X1TS U2996 ( .A0(intDX_EWSW[44]), .A1(n2433), .B0(DMP_EXP_EWSW[44]),
.B1(n2417), .Y(n2380) );
OAI21XLTS U2997 ( .A0(n3267), .A1(n2435), .B0(n2380), .Y(n1564) );
AOI22X1TS U2998 ( .A0(intDX_EWSW[4]), .A1(n2410), .B0(DMP_EXP_EWSW[4]), .B1(
n1905), .Y(n2381) );
OAI21XLTS U2999 ( .A0(n3130), .A1(n2435), .B0(n2381), .Y(n1604) );
AOI22X1TS U3000 ( .A0(intDX_EWSW[59]), .A1(n2433), .B0(DMP_EXP_EWSW[59]),
.B1(n2438), .Y(n2382) );
OAI21XLTS U3001 ( .A0(n3133), .A1(n2435), .B0(n2382), .Y(n1549) );
AOI22X1TS U3002 ( .A0(intDX_EWSW[14]), .A1(n2410), .B0(DMP_EXP_EWSW[14]),
.B1(n2816), .Y(n2383) );
OAI21XLTS U3003 ( .A0(n3276), .A1(n2427), .B0(n2383), .Y(n1594) );
AOI22X1TS U3004 ( .A0(intDX_EWSW[1]), .A1(n2413), .B0(DMP_EXP_EWSW[1]), .B1(
n1905), .Y(n2384) );
OAI21XLTS U3005 ( .A0(n3275), .A1(n2427), .B0(n2384), .Y(n1607) );
AOI22X1TS U3006 ( .A0(intDX_EWSW[48]), .A1(n2433), .B0(DMP_EXP_EWSW[48]),
.B1(n2755), .Y(n2385) );
OAI21XLTS U3007 ( .A0(n3242), .A1(n2435), .B0(n2385), .Y(n1560) );
AOI22X1TS U3008 ( .A0(intDX_EWSW[31]), .A1(n2433), .B0(DMP_EXP_EWSW[31]),
.B1(n2755), .Y(n2386) );
AOI22X1TS U3009 ( .A0(intDX_EWSW[22]), .A1(n2413), .B0(DMP_EXP_EWSW[22]),
.B1(n2816), .Y(n2387) );
OAI21XLTS U3010 ( .A0(n3277), .A1(n2412), .B0(n2387), .Y(n1586) );
AOI22X1TS U3011 ( .A0(intDX_EWSW[23]), .A1(n2410), .B0(DMP_EXP_EWSW[23]),
.B1(n2816), .Y(n2388) );
OAI21XLTS U3012 ( .A0(n3141), .A1(n2412), .B0(n2388), .Y(n1585) );
AOI22X1TS U3013 ( .A0(intDX_EWSW[38]), .A1(n2431), .B0(DMP_EXP_EWSW[38]),
.B1(n2438), .Y(n2389) );
OAI21XLTS U3014 ( .A0(n3287), .A1(n2427), .B0(n2389), .Y(n1570) );
AOI22X1TS U3015 ( .A0(intDX_EWSW[37]), .A1(n2431), .B0(DMP_EXP_EWSW[37]),
.B1(n2816), .Y(n2390) );
OAI21XLTS U3016 ( .A0(n3260), .A1(n2427), .B0(n2390), .Y(n1571) );
AOI22X1TS U3017 ( .A0(intDX_EWSW[30]), .A1(n2413), .B0(DMP_EXP_EWSW[30]),
.B1(n2816), .Y(n2391) );
OAI21XLTS U3018 ( .A0(n3278), .A1(n2427), .B0(n2391), .Y(n1578) );
AOI22X1TS U3019 ( .A0(intDX_EWSW[3]), .A1(n2410), .B0(DMP_EXP_EWSW[3]), .B1(
n1905), .Y(n2392) );
AOI22X1TS U3020 ( .A0(intDX_EWSW[26]), .A1(n2410), .B0(DMP_EXP_EWSW[26]),
.B1(n1905), .Y(n2393) );
OAI21XLTS U3021 ( .A0(n3239), .A1(n2412), .B0(n2393), .Y(n1582) );
AOI22X1TS U3022 ( .A0(intDX_EWSW[19]), .A1(n2410), .B0(DMP_EXP_EWSW[19]),
.B1(n2816), .Y(n2394) );
OAI21XLTS U3023 ( .A0(n3125), .A1(n2412), .B0(n2394), .Y(n1589) );
AOI22X1TS U3024 ( .A0(intDX_EWSW[9]), .A1(n2433), .B0(DMP_EXP_EWSW[9]), .B1(
n1905), .Y(n2395) );
OAI21XLTS U3025 ( .A0(n3230), .A1(n2435), .B0(n2395), .Y(n1599) );
AOI22X1TS U3026 ( .A0(intDX_EWSW[21]), .A1(n2413), .B0(DMP_EXP_EWSW[21]),
.B1(n2816), .Y(n2396) );
OAI21XLTS U3027 ( .A0(n3233), .A1(n2412), .B0(n2396), .Y(n1587) );
AOI22X1TS U3028 ( .A0(intDX_EWSW[20]), .A1(n2410), .B0(DMP_EXP_EWSW[20]),
.B1(n2816), .Y(n2397) );
OAI21XLTS U3029 ( .A0(n3237), .A1(n2412), .B0(n2397), .Y(n1588) );
AOI22X1TS U3030 ( .A0(intDX_EWSW[11]), .A1(n2410), .B0(DMP_EXP_EWSW[11]),
.B1(n2816), .Y(n2398) );
OAI21XLTS U3031 ( .A0(n3132), .A1(n2427), .B0(n2398), .Y(n1597) );
AOI22X1TS U3032 ( .A0(intDX_EWSW[28]), .A1(n2413), .B0(DMP_EXP_EWSW[28]),
.B1(n2816), .Y(n2399) );
OAI21XLTS U3033 ( .A0(n3240), .A1(n2412), .B0(n2399), .Y(n1580) );
AOI22X1TS U3034 ( .A0(intDX_EWSW[18]), .A1(n2413), .B0(DMP_EXP_EWSW[18]),
.B1(n2816), .Y(n2400) );
OAI21XLTS U3035 ( .A0(n3236), .A1(n2412), .B0(n2400), .Y(n1590) );
AOI22X1TS U3036 ( .A0(intDX_EWSW[29]), .A1(n2410), .B0(DMP_EXP_EWSW[29]),
.B1(n1905), .Y(n2401) );
OAI21XLTS U3037 ( .A0(n3129), .A1(n2427), .B0(n2401), .Y(n1579) );
AOI22X1TS U3038 ( .A0(intDX_EWSW[12]), .A1(n2431), .B0(DMP_EXP_EWSW[12]),
.B1(n2816), .Y(n2402) );
OAI21XLTS U3039 ( .A0(n3235), .A1(n2427), .B0(n2402), .Y(n1596) );
AOI22X1TS U3040 ( .A0(intDX_EWSW[2]), .A1(n2413), .B0(DMP_EXP_EWSW[2]), .B1(
n1905), .Y(n2403) );
OAI21XLTS U3041 ( .A0(n3234), .A1(n2435), .B0(n2403), .Y(n1606) );
AOI22X1TS U3042 ( .A0(intDX_EWSW[13]), .A1(n2433), .B0(DMP_EXP_EWSW[13]),
.B1(n2816), .Y(n2404) );
OAI21XLTS U3043 ( .A0(n3232), .A1(n2412), .B0(n2404), .Y(n1595) );
AOI22X1TS U3044 ( .A0(intDX_EWSW[24]), .A1(n2413), .B0(DMP_EXP_EWSW[24]),
.B1(n2816), .Y(n2405) );
OAI21XLTS U3045 ( .A0(n3238), .A1(n2412), .B0(n2405), .Y(n1584) );
AOI22X1TS U3046 ( .A0(intDX_EWSW[25]), .A1(n2410), .B0(DMP_EXP_EWSW[25]),
.B1(n2349), .Y(n2406) );
OAI21XLTS U3047 ( .A0(n3126), .A1(n2412), .B0(n2406), .Y(n1583) );
AOI22X1TS U3048 ( .A0(intDX_EWSW[6]), .A1(n2410), .B0(DMP_EXP_EWSW[6]), .B1(
n1905), .Y(n2407) );
OAI21XLTS U3049 ( .A0(n3143), .A1(n2412), .B0(n2407), .Y(n1602) );
AOI22X1TS U3050 ( .A0(intDX_EWSW[32]), .A1(n2431), .B0(DMP_EXP_EWSW[32]),
.B1(n2816), .Y(n2408) );
OAI21XLTS U3051 ( .A0(n3241), .A1(n2427), .B0(n2408), .Y(n1576) );
AOI22X1TS U3052 ( .A0(intDX_EWSW[17]), .A1(n2413), .B0(DMP_EXP_EWSW[17]),
.B1(n2816), .Y(n2409) );
AOI22X1TS U3053 ( .A0(intDX_EWSW[27]), .A1(n2413), .B0(DMP_EXP_EWSW[27]),
.B1(n2816), .Y(n2411) );
OAI21XLTS U3054 ( .A0(n3127), .A1(n2412), .B0(n2411), .Y(n1581) );
AOI22X1TS U3055 ( .A0(DMP_EXP_EWSW[57]), .A1(n2438), .B0(intDX_EWSW[57]),
.B1(n2410), .Y(n2414) );
OAI21XLTS U3056 ( .A0(n3250), .A1(n2435), .B0(n2414), .Y(n1551) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[8]), .A1(n2431), .B0(DMP_EXP_EWSW[8]), .B1(
n2816), .Y(n2415) );
OAI21XLTS U3058 ( .A0(n3131), .A1(n2435), .B0(n2415), .Y(n1600) );
AOI22X1TS U3059 ( .A0(intDX_EWSW[49]), .A1(n2433), .B0(DMP_EXP_EWSW[49]),
.B1(n2816), .Y(n2416) );
OAI21XLTS U3060 ( .A0(n3251), .A1(n2435), .B0(n2416), .Y(n1559) );
AOI22X1TS U3061 ( .A0(intDX_EWSW[50]), .A1(n2433), .B0(DMP_EXP_EWSW[50]),
.B1(n2417), .Y(n2418) );
OAI21XLTS U3062 ( .A0(n3269), .A1(n2427), .B0(n2418), .Y(n1558) );
AOI22X1TS U3063 ( .A0(intDX_EWSW[33]), .A1(n2431), .B0(DMP_EXP_EWSW[33]),
.B1(n2755), .Y(n2419) );
OAI21XLTS U3064 ( .A0(n3136), .A1(n2427), .B0(n2419), .Y(n1575) );
AOI22X1TS U3065 ( .A0(intDX_EWSW[35]), .A1(n2431), .B0(DMP_EXP_EWSW[35]),
.B1(n2816), .Y(n2420) );
OAI21XLTS U3066 ( .A0(n3137), .A1(n2427), .B0(n2420), .Y(n1573) );
AOI22X1TS U3067 ( .A0(intDX_EWSW[34]), .A1(n2431), .B0(DMP_EXP_EWSW[34]),
.B1(n1905), .Y(n2421) );
OAI21XLTS U3068 ( .A0(n3263), .A1(n2427), .B0(n2421), .Y(n1574) );
AOI22X1TS U3069 ( .A0(intDX_EWSW[47]), .A1(n2433), .B0(DMP_EXP_EWSW[47]),
.B1(n2417), .Y(n2422) );
OAI21XLTS U3070 ( .A0(n3134), .A1(n2435), .B0(n2422), .Y(n1561) );
AOI22X1TS U3071 ( .A0(intDX_EWSW[42]), .A1(n2431), .B0(DMP_EXP_EWSW[42]),
.B1(n2438), .Y(n2423) );
OAI21XLTS U3072 ( .A0(n3266), .A1(n2435), .B0(n2423), .Y(n1566) );
AOI22X1TS U3073 ( .A0(intDX_EWSW[40]), .A1(n2431), .B0(DMP_EXP_EWSW[40]),
.B1(n2349), .Y(n2424) );
OAI21XLTS U3074 ( .A0(n3265), .A1(n2427), .B0(n2424), .Y(n1568) );
AOI22X1TS U3075 ( .A0(intDX_EWSW[36]), .A1(n2431), .B0(DMP_EXP_EWSW[36]),
.B1(n2755), .Y(n2425) );
OAI21XLTS U3076 ( .A0(n3264), .A1(n2427), .B0(n2425), .Y(n1572) );
AOI22X1TS U3077 ( .A0(intDX_EWSW[39]), .A1(n2431), .B0(DMP_EXP_EWSW[39]),
.B1(n2417), .Y(n2426) );
OAI21XLTS U3078 ( .A0(n3261), .A1(n2427), .B0(n2426), .Y(n1569) );
AOI22X1TS U3079 ( .A0(intDX_EWSW[45]), .A1(n2433), .B0(DMP_EXP_EWSW[45]),
.B1(n2438), .Y(n2428) );
AOI22X1TS U3080 ( .A0(intDX_EWSW[43]), .A1(n2431), .B0(DMP_EXP_EWSW[43]),
.B1(n2417), .Y(n2429) );
OAI21XLTS U3081 ( .A0(n3139), .A1(n2435), .B0(n2429), .Y(n1565) );
AOI22X1TS U3082 ( .A0(intDX_EWSW[51]), .A1(n2433), .B0(DMP_EXP_EWSW[51]),
.B1(n2438), .Y(n2430) );
OAI21XLTS U3083 ( .A0(n3135), .A1(n2435), .B0(n2430), .Y(n1557) );
AOI22X1TS U3084 ( .A0(intDX_EWSW[41]), .A1(n2431), .B0(DMP_EXP_EWSW[41]),
.B1(n2438), .Y(n2432) );
OAI21XLTS U3085 ( .A0(n3138), .A1(n2435), .B0(n2432), .Y(n1567) );
AOI22X1TS U3086 ( .A0(intDX_EWSW[46]), .A1(n2433), .B0(DMP_EXP_EWSW[46]),
.B1(n2755), .Y(n2434) );
OAI21XLTS U3087 ( .A0(n3268), .A1(n2435), .B0(n2434), .Y(n1562) );
INVX2TS U3088 ( .A(n2436), .Y(n2441) );
OAI21XLTS U3089 ( .A0(n2441), .A1(n1905), .B0(n2838), .Y(n2439) );
AOI22X1TS U3090 ( .A0(intDX_EWSW[63]), .A1(n2439), .B0(SIGN_FLAG_EXP), .B1(
n2438), .Y(n2440) );
AOI2BB2XLTS U3091 ( .B0(beg_OP), .B1(n3123), .A0N(n3123), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2443) );
NAND3XLTS U3092 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3123), .C(
n3252), .Y(n2751) );
OAI21XLTS U3093 ( .A0(n2754), .A1(n2443), .B0(n2751), .Y(n1823) );
BUFX3TS U3094 ( .A(OP_FLAG_SFG), .Y(n2896) );
CLKINVX6TS U3095 ( .A(OP_FLAG_SFG), .Y(n2869) );
NAND2X1TS U3096 ( .A(n2465), .B(n3121), .Y(n2450) );
NOR3X1TS U3097 ( .A(Raw_mant_NRM_SWR[32]), .B(n3108), .C(n2728), .Y(n2447)
);
AOI22X1TS U3098 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n2445), .B0(n2465), .B1(
Raw_mant_NRM_SWR[29]), .Y(n2712) );
OAI31X1TS U3099 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3186), .A2(n2726), .B0(
n2712), .Y(n2446) );
AOI211X1TS U3100 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2458), .B0(n2447), .C0(
n2446), .Y(n2449) );
NAND2X1TS U3101 ( .A(Raw_mant_NRM_SWR[13]), .B(n2448), .Y(n2703) );
AOI211X1TS U3102 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2693), .B0(n2452), .C0(
n2451), .Y(n2736) );
NOR2X1TS U3103 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2466) );
NAND4XLTS U3104 ( .A(n2466), .B(n2453), .C(Raw_mant_NRM_SWR[37]), .D(n3195),
.Y(n2456) );
AOI21X1TS U3105 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3096), .B0(
Raw_mant_NRM_SWR[51]), .Y(n2454) );
AOI2BB1XLTS U3106 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n2454), .B0(
Raw_mant_NRM_SWR[53]), .Y(n2455) );
OAI22X1TS U3107 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2456), .B0(
Raw_mant_NRM_SWR[54]), .B1(n2455), .Y(n2457) );
AOI31XLTS U3108 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2458), .A2(n3214), .B0(
n2457), .Y(n2460) );
NAND2X1TS U3109 ( .A(Raw_mant_NRM_SWR[15]), .B(n2459), .Y(n2486) );
NOR3X1TS U3110 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n2491),
.Y(n2478) );
NAND4X1TS U3111 ( .A(n2464), .B(n2736), .C(n2463), .D(n2702), .Y(n2498) );
NOR2X1TS U3112 ( .A(n2757), .B(n2498), .Y(n2540) );
NAND2X1TS U3113 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2757), .Y(n2551) );
AOI22X1TS U3114 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n1825), .B0(n2613), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2504) );
NAND2X1TS U3115 ( .A(n2465), .B(Raw_mant_NRM_SWR[28]), .Y(n2732) );
INVX2TS U3116 ( .A(n2466), .Y(n2708) );
INVX2TS U3117 ( .A(n2467), .Y(n2473) );
NAND2X1TS U3118 ( .A(n3199), .B(n3116), .Y(n2471) );
NOR2XLTS U3119 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2468) );
NOR2XLTS U3120 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2469) );
OAI32X1TS U3121 ( .A0(n2471), .A1(n2470), .A2(n2731), .B0(n2469), .B1(n2471),
.Y(n2472) );
AOI211XLTS U3122 ( .A0(n2474), .A1(n2708), .B0(n2473), .C0(n2472), .Y(n2495)
);
NAND2X1TS U3123 ( .A(n3090), .B(n3108), .Y(n2475) );
AOI22X1TS U3124 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2477), .B0(n2476), .B1(
n2475), .Y(n2485) );
INVX2TS U3125 ( .A(n2478), .Y(n2719) );
NOR4X2TS U3126 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n2719),
.D(n3114), .Y(n2707) );
OAI31X1TS U3127 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2707), .A2(
Raw_mant_NRM_SWR[24]), .B0(n2480), .Y(n2484) );
OAI21XLTS U3128 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n2481), .Y(n2482) );
NAND4X1TS U3129 ( .A(n2485), .B(n2484), .C(n2483), .D(n2482), .Y(n2722) );
AOI32X1TS U3130 ( .A0(n2486), .A1(n3086), .A2(n3107), .B0(n2737), .B1(n2486),
.Y(n2487) );
INVX2TS U3131 ( .A(n2487), .Y(n2490) );
OAI211X1TS U3132 ( .A0(n2492), .A1(n2491), .B0(n2490), .C0(n2489), .Y(n2706)
);
AOI211X1TS U3133 ( .A0(n2493), .A1(Raw_mant_NRM_SWR[16]), .B0(n2722), .C0(
n2706), .Y(n2494) );
OAI211X4TS U3134 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2732), .B0(n2495), .C0(
n2494), .Y(n2507) );
OAI2BB1X1TS U3135 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n2757), .B0(n2742),
.Y(n2497) );
NOR2BX4TS U3136 ( .AN(n2497), .B(n2496), .Y(n2782) );
AOI22X1TS U3137 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n1826), .B0(n2655), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2500) );
NOR2X1TS U3138 ( .A(n2738), .B(Shift_amount_SHT1_EWR[0]), .Y(n2514) );
INVX2TS U3139 ( .A(n2514), .Y(n2558) );
AOI22X1TS U3140 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n1825), .B0(n2612), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2499) );
NAND2X1TS U3141 ( .A(n2500), .B(n2499), .Y(n2515) );
AOI22X1TS U3142 ( .A0(n2787), .A1(Data_array_SWR[1]), .B0(n2782), .B1(n2515),
.Y(n2503) );
BUFX3TS U3143 ( .A(n2501), .Y(n2780) );
NAND2X1TS U3144 ( .A(Raw_mant_NRM_SWR[52]), .B(n2780), .Y(n2502) );
BUFX4TS U3145 ( .A(n1825), .Y(n2637) );
INVX2TS U3146 ( .A(n2782), .Y(n2681) );
BUFX6TS U3147 ( .A(n2681), .Y(n2672) );
AOI22X1TS U3148 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n1826), .B0(n2655), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2506) );
AOI22X1TS U3149 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n1825), .B0(n2612), .B1(
DmP_mant_SHT1_SW[7]), .Y(n2505) );
NAND2X1TS U3150 ( .A(n2506), .B(n2505), .Y(n2577) );
AOI22X1TS U3151 ( .A0(n2668), .A1(Data_array_SWR[9]), .B0(n2778), .B1(n2577),
.Y(n2509) );
NAND2X1TS U3152 ( .A(Raw_mant_NRM_SWR[42]), .B(n2526), .Y(n2508) );
AOI22X1TS U3153 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n1826), .B0(n2587), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2511) );
AOI22X1TS U3154 ( .A0(Raw_mant_NRM_SWR[52]), .A1(n1825), .B0(n2612), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2510) );
NAND2X1TS U3155 ( .A(n2511), .B(n2510), .Y(n2781) );
AOI22X1TS U3156 ( .A0(n2668), .A1(Data_array_SWR[2]), .B0(n2778), .B1(n2781),
.Y(n2513) );
NAND2X1TS U3157 ( .A(Raw_mant_NRM_SWR[49]), .B(n2526), .Y(n2512) );
AOI22X1TS U3158 ( .A0(n2791), .A1(Data_array_SWR[3]), .B0(n2778), .B1(n2515),
.Y(n2517) );
NAND2X1TS U3159 ( .A(n1879), .B(n2608), .Y(n2516) );
AOI22X1TS U3160 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n1826), .B0(n2655), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2519) );
AOI22X1TS U3161 ( .A0(n1879), .A1(n1825), .B0(n2612), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2518) );
NAND2X1TS U3162 ( .A(n2519), .B(n2518), .Y(n2522) );
AOI22X1TS U3163 ( .A0(n2787), .A1(Data_array_SWR[6]), .B0(n2778), .B1(n2522),
.Y(n2521) );
NAND2X1TS U3164 ( .A(Raw_mant_NRM_SWR[45]), .B(n2526), .Y(n2520) );
BUFX4TS U3165 ( .A(n2534), .Y(n2684) );
AOI22X1TS U3166 ( .A0(n2791), .A1(Data_array_SWR[4]), .B0(n2782), .B1(n2522),
.Y(n2524) );
NAND2X1TS U3167 ( .A(Raw_mant_NRM_SWR[49]), .B(n2780), .Y(n2523) );
AOI22X1TS U3168 ( .A0(n2787), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2526), .Y(n2528) );
AOI22X1TS U3169 ( .A0(n2791), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2608), .Y(n2531) );
BUFX4TS U3170 ( .A(n2672), .Y(n2689) );
AOI22X1TS U3171 ( .A0(n2668), .A1(n1873), .B0(Raw_mant_NRM_SWR[33]), .B1(
n2608), .Y(n2533) );
AOI21X1TS U3172 ( .A0(n2496), .A1(Data_array_SWR[39]), .B0(n2683), .Y(n2536)
);
AOI22X1TS U3173 ( .A0(n2787), .A1(Data_array_SWR[5]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2526), .Y(n2538) );
AOI22X1TS U3174 ( .A0(n2668), .A1(n1869), .B0(Raw_mant_NRM_SWR[39]), .B1(
n2608), .Y(n2542) );
BUFX4TS U3175 ( .A(n1825), .Y(n2656) );
AOI22X1TS U3176 ( .A0(n2668), .A1(n1876), .B0(Raw_mant_NRM_SWR[35]), .B1(
n2608), .Y(n2544) );
AOI22X1TS U3177 ( .A0(n2791), .A1(n1880), .B0(Raw_mant_NRM_SWR[26]), .B1(
n2608), .Y(n2547) );
AOI22X1TS U3178 ( .A0(n2791), .A1(Data_array_SWR[23]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n2526), .Y(n2550) );
AOI222X1TS U3179 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2677) );
AOI22X1TS U3180 ( .A0(n2496), .A1(Data_array_SWR[36]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2608), .Y(n2554) );
AOI22X1TS U3181 ( .A0(n1825), .A1(Raw_mant_NRM_SWR[1]), .B0(
DmP_mant_SHT1_SW[51]), .B1(n2757), .Y(n2552) );
NAND2X1TS U3182 ( .A(n2552), .B(n2551), .Y(n2777) );
AOI22X1TS U3183 ( .A0(n2782), .A1(n2777), .B0(DmP_mant_SHT1_SW[49]), .B1(
n2683), .Y(n2553) );
BUFX4TS U3184 ( .A(n2684), .Y(n2620) );
AOI22X1TS U3185 ( .A0(n2787), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n2526), .Y(n2556) );
AOI22X1TS U3186 ( .A0(n2496), .A1(Data_array_SWR[37]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2780), .Y(n2561) );
BUFX4TS U3187 ( .A(n2559), .Y(n2686) );
AOI22X1TS U3188 ( .A0(n2668), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2526), .Y(n2564) );
AOI22X1TS U3189 ( .A0(n2787), .A1(n1867), .B0(Raw_mant_NRM_SWR[11]), .B1(
n2608), .Y(n2567) );
AOI22X1TS U3190 ( .A0(n2787), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2526), .Y(n2569) );
AOI22X1TS U3191 ( .A0(n2496), .A1(Data_array_SWR[35]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2608), .Y(n2572) );
AOI22X1TS U3192 ( .A0(n2496), .A1(Data_array_SWR[33]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2526), .Y(n2575) );
AOI22X1TS U3193 ( .A0(n2668), .A1(Data_array_SWR[7]), .B0(n2782), .B1(n2577),
.Y(n2579) );
NAND2X1TS U3194 ( .A(Raw_mant_NRM_SWR[46]), .B(n2780), .Y(n2578) );
AOI22X1TS U3195 ( .A0(n2787), .A1(Data_array_SWR[28]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2526), .Y(n2582) );
AOI22X1TS U3196 ( .A0(n2791), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2526), .Y(n2585) );
AOI22X1TS U3197 ( .A0(n2668), .A1(n1868), .B0(Raw_mant_NRM_SWR[38]), .B1(
n2608), .Y(n2589) );
AOI22X1TS U3198 ( .A0(n2787), .A1(Data_array_SWR[30]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2526), .Y(n2592) );
AOI22X1TS U3199 ( .A0(n2791), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2608), .Y(n2596) );
AOI22X1TS U3200 ( .A0(n2668), .A1(n1878), .B0(Raw_mant_NRM_SWR[29]), .B1(
n2608), .Y(n2599) );
AOI22X1TS U3201 ( .A0(n2787), .A1(n1865), .B0(Raw_mant_NRM_SWR[13]), .B1(
n2608), .Y(n2603) );
AOI22X1TS U3202 ( .A0(n2668), .A1(n1870), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2608), .Y(n2606) );
AOI22X1TS U3203 ( .A0(n2791), .A1(n1874), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2608), .Y(n2610) );
AOI22X1TS U3204 ( .A0(n2791), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2526), .Y(n2615) );
AOI22X1TS U3205 ( .A0(n2668), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n2526), .Y(n2619) );
AOI22X1TS U3206 ( .A0(n2791), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2780), .Y(n2624) );
AOI22X1TS U3207 ( .A0(n2787), .A1(n1866), .B0(n2683), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2626) );
AOI222X1TS U3208 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2656), .C0(n2655), .C1(DmP_mant_SHT1_SW[44]), .Y(n2643) );
AOI22X1TS U3209 ( .A0(n2668), .A1(Data_array_SWR[13]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2628) );
AOI222X1TS U3210 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[40]), .Y(n2644) );
AOI22X1TS U3211 ( .A0(n2787), .A1(Data_array_SWR[26]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2630) );
AOI22X1TS U3212 ( .A0(n2668), .A1(n1877), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2501), .Y(n2633) );
AOI22X1TS U3213 ( .A0(n2787), .A1(n1872), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2780), .Y(n2636) );
AOI22X1TS U3214 ( .A0(n2791), .A1(Data_array_SWR[18]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2640) );
AOI22X1TS U3215 ( .A0(n2787), .A1(Data_array_SWR[29]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2642) );
AOI222X1TS U3216 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1826), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2656), .C0(n2655), .C1(
DmP_mant_SHT1_SW[42]), .Y(n2647) );
AOI22X1TS U3217 ( .A0(n2787), .A1(Data_array_SWR[27]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2646) );
AOI22X1TS U3218 ( .A0(n2791), .A1(Data_array_SWR[20]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2650) );
AOI22X1TS U3219 ( .A0(n2668), .A1(n1875), .B0(n2683), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2653) );
AOI22X1TS U3220 ( .A0(n2787), .A1(Data_array_SWR[32]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2659) );
AOI22X1TS U3221 ( .A0(n2668), .A1(Data_array_SWR[10]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2780), .Y(n2662) );
AOI22X1TS U3222 ( .A0(n2791), .A1(Data_array_SWR[14]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2666) );
AOI22X1TS U3223 ( .A0(n2668), .A1(n1871), .B0(Raw_mant_NRM_SWR[39]), .B1(
n2780), .Y(n2671) );
AOI22X1TS U3224 ( .A0(n2791), .A1(Data_array_SWR[22]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2676) );
AOI22X1TS U3225 ( .A0(n2787), .A1(Data_array_SWR[25]), .B0(n2683), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2680) );
AOI22X1TS U3226 ( .A0(n2496), .A1(Data_array_SWR[34]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n2683), .Y(n2688) );
INVX2TS U3227 ( .A(n2691), .Y(n2692) );
NAND2X1TS U3228 ( .A(n3205), .B(n2692), .Y(DP_OP_15J76_123_4372_n11) );
MX2X1TS U3229 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(n2738),
.Y(n1332) );
MX2X1TS U3230 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n2738),
.Y(n1337) );
MX2X1TS U3231 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n2738),
.Y(n1342) );
MX2X1TS U3232 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2738),
.Y(n1347) );
MX2X1TS U3233 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2738),
.Y(n1352) );
MX2X1TS U3234 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2738),
.Y(n1357) );
MX2X1TS U3235 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2738),
.Y(n1362) );
MX2X1TS U3236 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2738),
.Y(n1367) );
MX2X1TS U3237 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2738),
.Y(n1372) );
MX2X1TS U3238 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2738),
.Y(n1377) );
MX2X1TS U3239 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2738),
.Y(n1382) );
AOI22X1TS U3240 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2694), .B0(
Raw_mant_NRM_SWR[10]), .B1(n2693), .Y(n2697) );
AOI32X1TS U3241 ( .A0(n2698), .A1(n2697), .A2(n3122), .B0(n2696), .B1(n2697),
.Y(n2704) );
NAND4BXLTS U3242 ( .AN(n2704), .B(n2703), .C(n2702), .D(n2701), .Y(n2705) );
OAI31X1TS U3243 ( .A0(n2707), .A1(n2706), .A2(n2705), .B0(n2738), .Y(n2792)
);
OAI2BB1X1TS U3244 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n2757), .B0(n2792),
.Y(n1161) );
NOR2XLTS U3245 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2720)
);
OAI31X1TS U3246 ( .A0(n2710), .A1(n2709), .A2(n2708), .B0(n2732), .Y(n2715)
);
OAI211XLTS U3247 ( .A0(n3144), .A1(n2713), .B0(n2712), .C0(n2711), .Y(n2714)
);
AOI211X1TS U3248 ( .A0(n2716), .A1(Raw_mant_NRM_SWR[34]), .B0(n2715), .C0(
n2714), .Y(n2718) );
OAI211X1TS U3249 ( .A0(n2720), .A1(n2719), .B0(n2718), .C0(n2717), .Y(n2721)
);
OAI31X1TS U3250 ( .A0(n2723), .A1(n2722), .A2(n2721), .B0(n2738), .Y(n2788)
);
OAI2BB1X1TS U3251 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n2757), .B0(n2788),
.Y(n1155) );
OAI2BB1X1TS U3252 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n2757), .B0(n2724),
.Y(n1148) );
OAI22X1TS U3253 ( .A0(n3105), .A1(n2726), .B0(n2725), .B1(n3295), .Y(n2741)
);
OAI22X1TS U3254 ( .A0(n3090), .A1(n2728), .B0(n2727), .B1(n3146), .Y(n2730)
);
OAI31X1TS U3255 ( .A0(n2731), .A1(n2730), .A2(n1879), .B0(n2729), .Y(n2733)
);
OAI211XLTS U3256 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2734), .B0(n2733), .C0(
n2732), .Y(n2740) );
OAI31X1TS U3257 ( .A0(n2741), .A1(n2740), .A2(n2739), .B0(n2738), .Y(n2785)
);
OAI2BB1X1TS U3258 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n2757), .B0(n2785),
.Y(n1137) );
OAI2BB1X1TS U3259 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n2757), .B0(n2742),
.Y(n1151) );
OAI2BB1X1TS U3260 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n2757), .B0(n2743),
.Y(n1158) );
OA22X1TS U3261 ( .A0(n2750), .A1(n2745), .B0(n3306), .B1(
final_result_ieee[52]), .Y(n1619) );
OA22X1TS U3262 ( .A0(n2750), .A1(exp_rslt_NRM2_EW1[1]), .B0(n3306), .B1(
final_result_ieee[53]), .Y(n1618) );
OA22X1TS U3263 ( .A0(n2750), .A1(exp_rslt_NRM2_EW1[2]), .B0(n3306), .B1(
final_result_ieee[54]), .Y(n1617) );
OA22X1TS U3264 ( .A0(n2750), .A1(exp_rslt_NRM2_EW1[3]), .B0(n3306), .B1(
final_result_ieee[55]), .Y(n1616) );
OA22X1TS U3265 ( .A0(n2750), .A1(exp_rslt_NRM2_EW1[4]), .B0(n3306), .B1(
final_result_ieee[56]), .Y(n1615) );
OA22X1TS U3266 ( .A0(n2750), .A1(exp_rslt_NRM2_EW1[5]), .B0(n3306), .B1(
final_result_ieee[57]), .Y(n1614) );
OA22X1TS U3267 ( .A0(n2750), .A1(n2746), .B0(n3306), .B1(
final_result_ieee[58]), .Y(n1613) );
OA22X1TS U3268 ( .A0(n2750), .A1(n2747), .B0(n3306), .B1(
final_result_ieee[59]), .Y(n1612) );
OA22X1TS U3269 ( .A0(n2750), .A1(n2748), .B0(n3306), .B1(
final_result_ieee[60]), .Y(n1611) );
OA22X1TS U3270 ( .A0(n2750), .A1(n2749), .B0(n3306), .B1(
final_result_ieee[61]), .Y(n1610) );
INVX2TS U3271 ( .A(n2754), .Y(n2752) );
AOI22X1TS U3272 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2752), .B1(n3123), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3273 ( .A(n2752), .B(n2751), .Y(n1824) );
NOR2XLTS U3274 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2753) );
AOI32X4TS U3275 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2753), .B1(n3252), .Y(n2758)
);
INVX2TS U3276 ( .A(n2758), .Y(n2756) );
AOI22X1TS U3277 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2754), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3123), .Y(n2759) );
AO22XLTS U3278 ( .A0(n2756), .A1(n1863), .B0(n2758), .B1(n2759), .Y(n1822)
);
AOI22X1TS U3279 ( .A0(n2758), .A1(n2417), .B0(n2823), .B1(n2756), .Y(n1821)
);
AOI22X1TS U3280 ( .A0(n2758), .A1(n2842), .B0(n2818), .B1(n2756), .Y(n1820)
);
AOI22X1TS U3281 ( .A0(n2758), .A1(n2910), .B0(n2757), .B1(n2756), .Y(n1817)
);
AOI22X1TS U3282 ( .A0(n2758), .A1(n2757), .B0(n3052), .B1(n2756), .Y(n1816)
);
NAND2X1TS U3283 ( .A(beg_OP), .B(n2759), .Y(n2760) );
BUFX4TS U3284 ( .A(n2761), .Y(n2764) );
BUFX4TS U3285 ( .A(n2764), .Y(n2763) );
INVX4TS U3286 ( .A(n2764), .Y(n2776) );
INVX4TS U3287 ( .A(n2764), .Y(n2775) );
BUFX4TS U3288 ( .A(n2761), .Y(n2774) );
AO22XLTS U3289 ( .A0(n2775), .A1(intDX_EWSW[1]), .B0(n2774), .B1(Data_X[1]),
.Y(n1814) );
BUFX4TS U3290 ( .A(n2761), .Y(n2773) );
AO22XLTS U3291 ( .A0(n2761), .A1(Data_X[3]), .B0(n2765), .B1(intDX_EWSW[3]),
.Y(n1812) );
BUFX4TS U3292 ( .A(n2761), .Y(n2771) );
INVX4TS U3293 ( .A(n2763), .Y(n2765) );
AO22XLTS U3294 ( .A0(n2773), .A1(Data_X[8]), .B0(n2765), .B1(intDX_EWSW[8]),
.Y(n1807) );
AO22XLTS U3295 ( .A0(n2773), .A1(Data_X[11]), .B0(n2765), .B1(intDX_EWSW[11]), .Y(n1804) );
AO22XLTS U3296 ( .A0(n2773), .A1(Data_X[12]), .B0(n2765), .B1(intDX_EWSW[12]), .Y(n1803) );
AO22XLTS U3297 ( .A0(n2761), .A1(Data_X[13]), .B0(n2765), .B1(intDX_EWSW[13]), .Y(n1802) );
AO22XLTS U3298 ( .A0(n2761), .A1(Data_X[14]), .B0(n2765), .B1(intDX_EWSW[14]), .Y(n1801) );
AO22XLTS U3299 ( .A0(n2761), .A1(Data_X[15]), .B0(n2765), .B1(intDX_EWSW[15]), .Y(n1800) );
AO22XLTS U3300 ( .A0(n2771), .A1(Data_X[17]), .B0(n2765), .B1(intDX_EWSW[17]), .Y(n1798) );
AO22XLTS U3301 ( .A0(n2774), .A1(Data_X[18]), .B0(n2765), .B1(intDX_EWSW[18]), .Y(n1797) );
INVX4TS U3302 ( .A(n2763), .Y(n2766) );
AO22XLTS U3303 ( .A0(n2774), .A1(Data_X[19]), .B0(n2766), .B1(intDX_EWSW[19]), .Y(n1796) );
AO22XLTS U3304 ( .A0(n2774), .A1(Data_X[20]), .B0(n2766), .B1(intDX_EWSW[20]), .Y(n1795) );
AO22XLTS U3305 ( .A0(n2773), .A1(Data_X[21]), .B0(n2766), .B1(intDX_EWSW[21]), .Y(n1794) );
AO22XLTS U3306 ( .A0(n2774), .A1(Data_X[22]), .B0(n2766), .B1(intDX_EWSW[22]), .Y(n1793) );
AO22XLTS U3307 ( .A0(n2774), .A1(Data_X[23]), .B0(n2766), .B1(intDX_EWSW[23]), .Y(n1792) );
AO22XLTS U3308 ( .A0(n2771), .A1(Data_X[25]), .B0(n2766), .B1(intDX_EWSW[25]), .Y(n1790) );
AO22XLTS U3309 ( .A0(n2773), .A1(Data_X[26]), .B0(n2766), .B1(intDX_EWSW[26]), .Y(n1789) );
AO22XLTS U3310 ( .A0(n2763), .A1(Data_X[27]), .B0(n2766), .B1(intDX_EWSW[27]), .Y(n1788) );
AO22XLTS U3311 ( .A0(n2763), .A1(Data_X[28]), .B0(n2766), .B1(intDX_EWSW[28]), .Y(n1787) );
AO22XLTS U3312 ( .A0(n2763), .A1(Data_X[29]), .B0(n2766), .B1(intDX_EWSW[29]), .Y(n1786) );
AO22XLTS U3313 ( .A0(n2763), .A1(Data_X[30]), .B0(n2766), .B1(intDX_EWSW[30]), .Y(n1785) );
AO22XLTS U3314 ( .A0(n2763), .A1(Data_X[31]), .B0(n2766), .B1(intDX_EWSW[31]), .Y(n1784) );
INVX4TS U3315 ( .A(n2764), .Y(n2768) );
AO22XLTS U3316 ( .A0(n2763), .A1(Data_X[33]), .B0(n2768), .B1(intDX_EWSW[33]), .Y(n1782) );
AO22XLTS U3317 ( .A0(n2764), .A1(Data_X[34]), .B0(n2768), .B1(intDX_EWSW[34]), .Y(n1781) );
AO22XLTS U3318 ( .A0(n2764), .A1(Data_X[35]), .B0(n2768), .B1(intDX_EWSW[35]), .Y(n1780) );
AO22XLTS U3319 ( .A0(n2764), .A1(Data_X[36]), .B0(n2768), .B1(intDX_EWSW[36]), .Y(n1779) );
AO22XLTS U3320 ( .A0(n2761), .A1(Data_X[41]), .B0(n2768), .B1(intDX_EWSW[41]), .Y(n1774) );
AO22XLTS U3321 ( .A0(n2761), .A1(Data_X[42]), .B0(n2768), .B1(intDX_EWSW[42]), .Y(n1773) );
AO22XLTS U3322 ( .A0(n2761), .A1(Data_X[43]), .B0(n2768), .B1(intDX_EWSW[43]), .Y(n1772) );
INVX4TS U3323 ( .A(n2764), .Y(n2767) );
AO22XLTS U3324 ( .A0(n2761), .A1(Data_X[45]), .B0(n2767), .B1(intDX_EWSW[45]), .Y(n1770) );
AO22XLTS U3325 ( .A0(n2761), .A1(Data_X[46]), .B0(n2767), .B1(intDX_EWSW[46]), .Y(n1769) );
AO22XLTS U3326 ( .A0(n2763), .A1(Data_X[49]), .B0(n2767), .B1(intDX_EWSW[49]), .Y(n1766) );
AO22XLTS U3327 ( .A0(n2764), .A1(Data_X[50]), .B0(n2767), .B1(intDX_EWSW[50]), .Y(n1765) );
AO22XLTS U3328 ( .A0(n2764), .A1(Data_X[51]), .B0(n2767), .B1(intDX_EWSW[51]), .Y(n1764) );
CLKBUFX2TS U3329 ( .A(n2761), .Y(n2769) );
BUFX4TS U3330 ( .A(n2769), .Y(n2770) );
AO22XLTS U3331 ( .A0(n2768), .A1(intDX_EWSW[53]), .B0(n2770), .B1(Data_X[53]), .Y(n1762) );
AO22XLTS U3332 ( .A0(n2767), .A1(intDX_EWSW[54]), .B0(n2770), .B1(Data_X[54]), .Y(n1761) );
AO22XLTS U3333 ( .A0(n2767), .A1(intDX_EWSW[55]), .B0(n2770), .B1(Data_X[55]), .Y(n1760) );
AO22XLTS U3334 ( .A0(n2760), .A1(intDX_EWSW[56]), .B0(n2770), .B1(Data_X[56]), .Y(n1759) );
AO22XLTS U3335 ( .A0(n2764), .A1(Data_X[57]), .B0(n2767), .B1(intDX_EWSW[57]), .Y(n1758) );
AO22XLTS U3336 ( .A0(n2764), .A1(Data_X[58]), .B0(n2767), .B1(intDX_EWSW[58]), .Y(n1757) );
AO22XLTS U3337 ( .A0(n2764), .A1(Data_X[59]), .B0(n2767), .B1(intDX_EWSW[59]), .Y(n1756) );
AO22XLTS U3338 ( .A0(n2764), .A1(Data_X[60]), .B0(n2767), .B1(intDX_EWSW[60]), .Y(n1755) );
AO22XLTS U3339 ( .A0(n2763), .A1(add_subt), .B0(n2776), .B1(intAS), .Y(n1751) );
AO22XLTS U3340 ( .A0(n2776), .A1(intDY_EWSW[0]), .B0(n2770), .B1(Data_Y[0]),
.Y(n1749) );
AO22XLTS U3341 ( .A0(n2776), .A1(intDY_EWSW[1]), .B0(n2770), .B1(Data_Y[1]),
.Y(n1748) );
AO22XLTS U3342 ( .A0(n2776), .A1(intDY_EWSW[2]), .B0(n2770), .B1(Data_Y[2]),
.Y(n1747) );
AO22XLTS U3343 ( .A0(n2776), .A1(intDY_EWSW[3]), .B0(n2770), .B1(Data_Y[3]),
.Y(n1746) );
AO22XLTS U3344 ( .A0(n2776), .A1(intDY_EWSW[4]), .B0(n2770), .B1(Data_Y[4]),
.Y(n1745) );
AO22XLTS U3345 ( .A0(n2776), .A1(intDY_EWSW[5]), .B0(n2770), .B1(Data_Y[5]),
.Y(n1744) );
AO22XLTS U3346 ( .A0(n2776), .A1(intDY_EWSW[6]), .B0(n2770), .B1(Data_Y[6]),
.Y(n1743) );
AO22XLTS U3347 ( .A0(n2776), .A1(intDY_EWSW[7]), .B0(n2770), .B1(Data_Y[7]),
.Y(n1742) );
AO22XLTS U3348 ( .A0(n2767), .A1(intDY_EWSW[8]), .B0(n2773), .B1(Data_Y[8]),
.Y(n1741) );
AO22XLTS U3349 ( .A0(n2765), .A1(intDY_EWSW[9]), .B0(n2771), .B1(Data_Y[9]),
.Y(n1740) );
AO22XLTS U3350 ( .A0(n2776), .A1(intDY_EWSW[10]), .B0(n2770), .B1(Data_Y[10]), .Y(n1739) );
AO22XLTS U3351 ( .A0(n2766), .A1(intDY_EWSW[11]), .B0(n2774), .B1(Data_Y[11]), .Y(n1738) );
AO22XLTS U3352 ( .A0(n2776), .A1(intDY_EWSW[12]), .B0(n2771), .B1(Data_Y[12]), .Y(n1737) );
AO22XLTS U3353 ( .A0(n2768), .A1(intDY_EWSW[13]), .B0(n2761), .B1(Data_Y[13]), .Y(n1736) );
AO22XLTS U3354 ( .A0(n2765), .A1(intDY_EWSW[14]), .B0(n2771), .B1(Data_Y[14]), .Y(n1735) );
AO22XLTS U3355 ( .A0(n2765), .A1(intDY_EWSW[15]), .B0(n2770), .B1(Data_Y[15]), .Y(n1734) );
AO22XLTS U3356 ( .A0(n2775), .A1(intDY_EWSW[16]), .B0(n2761), .B1(Data_Y[16]), .Y(n1733) );
AO22XLTS U3357 ( .A0(n2767), .A1(intDY_EWSW[17]), .B0(n2770), .B1(Data_Y[17]), .Y(n1732) );
AO22XLTS U3358 ( .A0(n2766), .A1(intDY_EWSW[18]), .B0(n2761), .B1(Data_Y[18]), .Y(n1731) );
AO22XLTS U3359 ( .A0(n2766), .A1(intDY_EWSW[19]), .B0(n2770), .B1(Data_Y[19]), .Y(n1730) );
INVX4TS U3360 ( .A(n2764), .Y(n2772) );
AO22XLTS U3361 ( .A0(n2772), .A1(intDY_EWSW[20]), .B0(n2770), .B1(Data_Y[20]), .Y(n1729) );
AO22XLTS U3362 ( .A0(n2765), .A1(intDY_EWSW[21]), .B0(n2771), .B1(Data_Y[21]), .Y(n1728) );
AO22XLTS U3363 ( .A0(n2776), .A1(intDY_EWSW[22]), .B0(n2771), .B1(Data_Y[22]), .Y(n1727) );
AO22XLTS U3364 ( .A0(n2768), .A1(intDY_EWSW[23]), .B0(n2771), .B1(Data_Y[23]), .Y(n1726) );
AO22XLTS U3365 ( .A0(n2766), .A1(intDY_EWSW[24]), .B0(n2771), .B1(Data_Y[24]), .Y(n1725) );
AO22XLTS U3366 ( .A0(n2772), .A1(intDY_EWSW[25]), .B0(n2771), .B1(Data_Y[25]), .Y(n1724) );
AO22XLTS U3367 ( .A0(n2768), .A1(intDY_EWSW[26]), .B0(n2774), .B1(Data_Y[26]), .Y(n1723) );
AO22XLTS U3368 ( .A0(n2776), .A1(intDY_EWSW[27]), .B0(n2771), .B1(Data_Y[27]), .Y(n1722) );
AO22XLTS U3369 ( .A0(n2767), .A1(intDY_EWSW[28]), .B0(n2774), .B1(Data_Y[28]), .Y(n1721) );
AO22XLTS U3370 ( .A0(n2775), .A1(intDY_EWSW[29]), .B0(n2774), .B1(Data_Y[29]), .Y(n1720) );
AO22XLTS U3371 ( .A0(n2768), .A1(intDY_EWSW[30]), .B0(n2771), .B1(Data_Y[30]), .Y(n1719) );
AO22XLTS U3372 ( .A0(n2772), .A1(intDY_EWSW[31]), .B0(n2774), .B1(Data_Y[31]), .Y(n1718) );
AO22XLTS U3373 ( .A0(n2776), .A1(intDY_EWSW[32]), .B0(n2774), .B1(Data_Y[32]), .Y(n1717) );
AO22XLTS U3374 ( .A0(n2775), .A1(intDY_EWSW[33]), .B0(n2774), .B1(Data_Y[33]), .Y(n1716) );
AO22XLTS U3375 ( .A0(n2772), .A1(intDY_EWSW[34]), .B0(n2769), .B1(Data_Y[34]), .Y(n1715) );
AO22XLTS U3376 ( .A0(n2775), .A1(intDY_EWSW[35]), .B0(n2770), .B1(Data_Y[35]), .Y(n1714) );
AO22XLTS U3377 ( .A0(n2775), .A1(intDY_EWSW[36]), .B0(n2769), .B1(Data_Y[36]), .Y(n1713) );
AO22XLTS U3378 ( .A0(n2775), .A1(intDY_EWSW[37]), .B0(n2769), .B1(Data_Y[37]), .Y(n1712) );
AO22XLTS U3379 ( .A0(n2772), .A1(intDY_EWSW[38]), .B0(n2769), .B1(Data_Y[38]), .Y(n1711) );
AO22XLTS U3380 ( .A0(n2772), .A1(intDY_EWSW[39]), .B0(n2769), .B1(Data_Y[39]), .Y(n1710) );
AO22XLTS U3381 ( .A0(n2772), .A1(intDY_EWSW[40]), .B0(n2769), .B1(Data_Y[40]), .Y(n1709) );
AO22XLTS U3382 ( .A0(n2772), .A1(intDY_EWSW[41]), .B0(n2770), .B1(Data_Y[41]), .Y(n1708) );
AO22XLTS U3383 ( .A0(n2772), .A1(intDY_EWSW[42]), .B0(n2770), .B1(Data_Y[42]), .Y(n1707) );
AO22XLTS U3384 ( .A0(n2772), .A1(intDY_EWSW[43]), .B0(n2771), .B1(Data_Y[43]), .Y(n1706) );
AO22XLTS U3385 ( .A0(n2772), .A1(intDY_EWSW[44]), .B0(n2771), .B1(Data_Y[44]), .Y(n1705) );
AO22XLTS U3386 ( .A0(n2772), .A1(intDY_EWSW[45]), .B0(n2771), .B1(Data_Y[45]), .Y(n1704) );
AO22XLTS U3387 ( .A0(n2772), .A1(intDY_EWSW[46]), .B0(n2771), .B1(Data_Y[46]), .Y(n1703) );
AO22XLTS U3388 ( .A0(n2772), .A1(intDY_EWSW[47]), .B0(n2774), .B1(Data_Y[47]), .Y(n1702) );
AO22XLTS U3389 ( .A0(n2772), .A1(intDY_EWSW[48]), .B0(n2773), .B1(Data_Y[48]), .Y(n1701) );
AO22XLTS U3390 ( .A0(n2772), .A1(intDY_EWSW[49]), .B0(n2773), .B1(Data_Y[49]), .Y(n1700) );
AO22XLTS U3391 ( .A0(n2772), .A1(intDY_EWSW[50]), .B0(n2773), .B1(Data_Y[50]), .Y(n1699) );
AO22XLTS U3392 ( .A0(n2772), .A1(intDY_EWSW[51]), .B0(n2774), .B1(Data_Y[51]), .Y(n1698) );
AO22XLTS U3393 ( .A0(n2775), .A1(intDY_EWSW[52]), .B0(n2773), .B1(Data_Y[52]), .Y(n1697) );
AO22XLTS U3394 ( .A0(n2775), .A1(intDY_EWSW[53]), .B0(n2773), .B1(Data_Y[53]), .Y(n1696) );
AO22XLTS U3395 ( .A0(n2775), .A1(intDY_EWSW[54]), .B0(n2773), .B1(Data_Y[54]), .Y(n1695) );
AO22XLTS U3396 ( .A0(n2775), .A1(intDY_EWSW[55]), .B0(n2773), .B1(Data_Y[55]), .Y(n1694) );
AO22XLTS U3397 ( .A0(n2775), .A1(intDY_EWSW[56]), .B0(n2773), .B1(Data_Y[56]), .Y(n1693) );
AO22XLTS U3398 ( .A0(n2775), .A1(intDY_EWSW[57]), .B0(n2773), .B1(Data_Y[57]), .Y(n1692) );
AO22XLTS U3399 ( .A0(n2775), .A1(intDY_EWSW[58]), .B0(n2773), .B1(Data_Y[58]), .Y(n1691) );
AO22XLTS U3400 ( .A0(n2775), .A1(intDY_EWSW[59]), .B0(n2773), .B1(Data_Y[59]), .Y(n1690) );
AO22XLTS U3401 ( .A0(n2775), .A1(intDY_EWSW[60]), .B0(n2774), .B1(Data_Y[60]), .Y(n1689) );
AO22XLTS U3402 ( .A0(n2775), .A1(intDY_EWSW[61]), .B0(n2774), .B1(Data_Y[61]), .Y(n1688) );
AO22XLTS U3403 ( .A0(n2775), .A1(intDY_EWSW[62]), .B0(n2774), .B1(Data_Y[62]), .Y(n1687) );
AOI22X1TS U3404 ( .A0(n2496), .A1(Data_array_SWR[38]), .B0(n2778), .B1(n2777), .Y(n2779) );
OAI2BB1X1TS U3405 ( .A0N(Raw_mant_NRM_SWR[0]), .A1N(n2780), .B0(n2779), .Y(
n1684) );
AOI22X1TS U3406 ( .A0(n2787), .A1(Data_array_SWR[0]), .B0(n2782), .B1(n2781),
.Y(n2784) );
AOI22X1TS U3407 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n1825), .B0(
Raw_mant_NRM_SWR[53]), .B1(n2501), .Y(n2783) );
NAND2X1TS U3408 ( .A(n2784), .B(n2783), .Y(n1631) );
AOI22X1TS U3409 ( .A0(n2791), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n2790), .Y(n2786) );
NAND2X1TS U3410 ( .A(n2786), .B(n2785), .Y(n1630) );
AOI22X1TS U3411 ( .A0(n2787), .A1(shift_value_SHT2_EWR[4]), .B0(n2790), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2789) );
NAND2X1TS U3412 ( .A(n2789), .B(n2788), .Y(n1628) );
AOI22X1TS U3413 ( .A0(n2791), .A1(shift_value_SHT2_EWR[5]), .B0(n2790), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2793) );
NAND2X1TS U3414 ( .A(n2793), .B(n2792), .Y(n1626) );
NAND2X1TS U3415 ( .A(DmP_EXP_EWSW[52]), .B(n3291), .Y(n2798) );
OAI21XLTS U3416 ( .A0(DmP_EXP_EWSW[52]), .A1(n3291), .B0(n2798), .Y(n2794)
);
NAND2X1TS U3417 ( .A(DmP_EXP_EWSW[53]), .B(n3145), .Y(n2797) );
OAI21XLTS U3418 ( .A0(DmP_EXP_EWSW[53]), .A1(n3145), .B0(n2797), .Y(n2795)
);
XNOR2X1TS U3419 ( .A(n2798), .B(n2795), .Y(n2796) );
AO22XLTS U3420 ( .A0(n1864), .A1(n2796), .B0(n2820), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1624) );
AOI22X1TS U3421 ( .A0(DMP_EXP_EWSW[53]), .A1(n3092), .B0(n2798), .B1(n2797),
.Y(n2801) );
NOR2X1TS U3422 ( .A(n3093), .B(DMP_EXP_EWSW[54]), .Y(n2802) );
AOI21X1TS U3423 ( .A0(DMP_EXP_EWSW[54]), .A1(n3093), .B0(n2802), .Y(n2799)
);
XNOR2X1TS U3424 ( .A(n2801), .B(n2799), .Y(n2800) );
AO22XLTS U3425 ( .A0(n1864), .A1(n2800), .B0(n2820), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1623) );
OAI22X1TS U3426 ( .A0(n2802), .A1(n2801), .B0(DmP_EXP_EWSW[54]), .B1(n3147),
.Y(n2805) );
NAND2X1TS U3427 ( .A(DmP_EXP_EWSW[55]), .B(n3148), .Y(n2806) );
OAI21XLTS U3428 ( .A0(DmP_EXP_EWSW[55]), .A1(n3148), .B0(n2806), .Y(n2803)
);
XNOR2X1TS U3429 ( .A(n2805), .B(n2803), .Y(n2804) );
AO22XLTS U3430 ( .A0(n1864), .A1(n2804), .B0(n2820), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1622) );
AOI22X1TS U3431 ( .A0(DMP_EXP_EWSW[55]), .A1(n3095), .B0(n2806), .B1(n2805),
.Y(n2809) );
NOR2X1TS U3432 ( .A(n3089), .B(DMP_EXP_EWSW[56]), .Y(n2810) );
AOI21X1TS U3433 ( .A0(DMP_EXP_EWSW[56]), .A1(n3089), .B0(n2810), .Y(n2807)
);
XNOR2X1TS U3434 ( .A(n2809), .B(n2807), .Y(n2808) );
AO22XLTS U3435 ( .A0(n1864), .A1(n2808), .B0(n2820), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1621) );
OAI22X1TS U3436 ( .A0(n2810), .A1(n2809), .B0(DmP_EXP_EWSW[56]), .B1(n3151),
.Y(n2812) );
XNOR2X1TS U3437 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n2811) );
XOR2XLTS U3438 ( .A(n2812), .B(n2811), .Y(n2813) );
AO22XLTS U3439 ( .A0(n1864), .A1(n2813), .B0(n2820), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1620) );
OAI222X1TS U3440 ( .A0(n1827), .A1(n3298), .B0(n3145), .B1(n1863), .C0(n3088), .C1(n2839), .Y(n1555) );
OAI222X1TS U3441 ( .A0(n1827), .A1(n3150), .B0(n3147), .B1(n1863), .C0(n3087), .C1(n2839), .Y(n1554) );
OAI222X1TS U3442 ( .A0(n1827), .A1(n3299), .B0(n3148), .B1(n1863), .C0(n1854), .C1(n2839), .Y(n1553) );
OAI222X1TS U3443 ( .A0(n2837), .A1(n3094), .B0(n3151), .B1(n1863), .C0(n1853), .C1(n2839), .Y(n1552) );
AO21XLTS U3444 ( .A0(OP_FLAG_EXP), .A1(n2816), .B0(n2815), .Y(n1545) );
AO22XLTS U3445 ( .A0(n1864), .A1(DMP_EXP_EWSW[0]), .B0(n2842), .B1(
DMP_SHT1_EWSW[0]), .Y(n1542) );
BUFX3TS U3446 ( .A(n3300), .Y(n2819) );
AO22XLTS U3447 ( .A0(n2821), .A1(DMP_SHT1_EWSW[0]), .B0(n2848), .B1(
DMP_SHT2_EWSW[0]), .Y(n1541) );
BUFX3TS U3448 ( .A(n1829), .Y(n3065) );
AO22XLTS U3449 ( .A0(n1864), .A1(DMP_EXP_EWSW[1]), .B0(n2842), .B1(
DMP_SHT1_EWSW[1]), .Y(n1539) );
AO22XLTS U3450 ( .A0(n2821), .A1(DMP_SHT1_EWSW[1]), .B0(n2819), .B1(
DMP_SHT2_EWSW[1]), .Y(n1538) );
AO22XLTS U3451 ( .A0(n1864), .A1(DMP_EXP_EWSW[2]), .B0(n2842), .B1(
DMP_SHT1_EWSW[2]), .Y(n1536) );
AO22XLTS U3452 ( .A0(n2821), .A1(DMP_SHT1_EWSW[2]), .B0(n2848), .B1(
DMP_SHT2_EWSW[2]), .Y(n1535) );
AO22XLTS U3453 ( .A0(n1829), .A1(DMP_SFG[2]), .B0(n3082), .B1(
DMP_SHT2_EWSW[2]), .Y(n1534) );
AO22XLTS U3454 ( .A0(n1864), .A1(DMP_EXP_EWSW[3]), .B0(n2823), .B1(
DMP_SHT1_EWSW[3]), .Y(n1533) );
AO22XLTS U3455 ( .A0(n2821), .A1(DMP_SHT1_EWSW[3]), .B0(n2824), .B1(
DMP_SHT2_EWSW[3]), .Y(n1532) );
AO22XLTS U3456 ( .A0(n2829), .A1(DMP_SFG[3]), .B0(n3084), .B1(
DMP_SHT2_EWSW[3]), .Y(n1531) );
AO22XLTS U3457 ( .A0(n1864), .A1(DMP_EXP_EWSW[4]), .B0(n2820), .B1(
DMP_SHT1_EWSW[4]), .Y(n1530) );
AO22XLTS U3458 ( .A0(n2821), .A1(DMP_SHT1_EWSW[4]), .B0(n2848), .B1(
DMP_SHT2_EWSW[4]), .Y(n1529) );
AO22XLTS U3459 ( .A0(n1864), .A1(DMP_EXP_EWSW[5]), .B0(n2820), .B1(
DMP_SHT1_EWSW[5]), .Y(n1527) );
AO22XLTS U3460 ( .A0(n2821), .A1(DMP_SHT1_EWSW[5]), .B0(n2824), .B1(
DMP_SHT2_EWSW[5]), .Y(n1526) );
AO22XLTS U3461 ( .A0(n1906), .A1(DMP_EXP_EWSW[6]), .B0(n2820), .B1(
DMP_SHT1_EWSW[6]), .Y(n1524) );
AO22XLTS U3462 ( .A0(n2821), .A1(DMP_SHT1_EWSW[6]), .B0(n2848), .B1(
DMP_SHT2_EWSW[6]), .Y(n1523) );
AO22XLTS U3463 ( .A0(n2835), .A1(DMP_EXP_EWSW[7]), .B0(n2823), .B1(
DMP_SHT1_EWSW[7]), .Y(n1521) );
AO22XLTS U3464 ( .A0(n2821), .A1(DMP_SHT1_EWSW[7]), .B0(n2824), .B1(
DMP_SHT2_EWSW[7]), .Y(n1520) );
AO22XLTS U3465 ( .A0(n2832), .A1(DMP_EXP_EWSW[8]), .B0(n2823), .B1(
DMP_SHT1_EWSW[8]), .Y(n1518) );
AO22XLTS U3466 ( .A0(n2821), .A1(DMP_SHT1_EWSW[8]), .B0(n2848), .B1(
DMP_SHT2_EWSW[8]), .Y(n1517) );
AO22XLTS U3467 ( .A0(n2847), .A1(DMP_EXP_EWSW[9]), .B0(n2823), .B1(
DMP_SHT1_EWSW[9]), .Y(n1515) );
AO22XLTS U3468 ( .A0(n2821), .A1(DMP_SHT1_EWSW[9]), .B0(n2824), .B1(
DMP_SHT2_EWSW[9]), .Y(n1514) );
AO22XLTS U3469 ( .A0(n3085), .A1(DMP_SFG[9]), .B0(n3084), .B1(
DMP_SHT2_EWSW[9]), .Y(n1513) );
AO22XLTS U3470 ( .A0(n2847), .A1(DMP_EXP_EWSW[10]), .B0(n2823), .B1(
DMP_SHT1_EWSW[10]), .Y(n1512) );
AO22XLTS U3471 ( .A0(n2821), .A1(DMP_SHT1_EWSW[10]), .B0(n2848), .B1(
DMP_SHT2_EWSW[10]), .Y(n1511) );
AO22XLTS U3472 ( .A0(n2843), .A1(DMP_EXP_EWSW[11]), .B0(n2823), .B1(
DMP_SHT1_EWSW[11]), .Y(n1509) );
AO22XLTS U3473 ( .A0(n2821), .A1(DMP_SHT1_EWSW[11]), .B0(n2824), .B1(
DMP_SHT2_EWSW[11]), .Y(n1508) );
AO22XLTS U3474 ( .A0(n2847), .A1(DMP_EXP_EWSW[12]), .B0(n2823), .B1(
DMP_SHT1_EWSW[12]), .Y(n1506) );
AO22XLTS U3475 ( .A0(n2821), .A1(DMP_SHT1_EWSW[12]), .B0(n2848), .B1(
DMP_SHT2_EWSW[12]), .Y(n1505) );
AO22XLTS U3476 ( .A0(n2829), .A1(DMP_SFG[12]), .B0(n2822), .B1(
DMP_SHT2_EWSW[12]), .Y(n1504) );
AO22XLTS U3477 ( .A0(n1906), .A1(DMP_EXP_EWSW[13]), .B0(n2820), .B1(
DMP_SHT1_EWSW[13]), .Y(n1503) );
AO22XLTS U3478 ( .A0(n2821), .A1(DMP_SHT1_EWSW[13]), .B0(n2824), .B1(
DMP_SHT2_EWSW[13]), .Y(n1502) );
AO22XLTS U3479 ( .A0(n2829), .A1(DMP_SFG[13]), .B0(n3084), .B1(
DMP_SHT2_EWSW[13]), .Y(n1501) );
AO22XLTS U3480 ( .A0(n2843), .A1(DMP_EXP_EWSW[14]), .B0(n2823), .B1(
DMP_SHT1_EWSW[14]), .Y(n1500) );
AO22XLTS U3481 ( .A0(n2821), .A1(DMP_SHT1_EWSW[14]), .B0(n2848), .B1(
DMP_SHT2_EWSW[14]), .Y(n1499) );
AO22XLTS U3482 ( .A0(n2829), .A1(DMP_SFG[14]), .B0(n3084), .B1(
DMP_SHT2_EWSW[14]), .Y(n1498) );
AO22XLTS U3483 ( .A0(n1906), .A1(DMP_EXP_EWSW[15]), .B0(n2820), .B1(
DMP_SHT1_EWSW[15]), .Y(n1497) );
AO22XLTS U3484 ( .A0(n2821), .A1(DMP_SHT1_EWSW[15]), .B0(n2824), .B1(
DMP_SHT2_EWSW[15]), .Y(n1496) );
AO22XLTS U3485 ( .A0(n3085), .A1(DMP_SFG[15]), .B0(n2825), .B1(
DMP_SHT2_EWSW[15]), .Y(n1495) );
AO22XLTS U3486 ( .A0(n1906), .A1(DMP_EXP_EWSW[16]), .B0(n2820), .B1(
DMP_SHT1_EWSW[16]), .Y(n1494) );
AO22XLTS U3487 ( .A0(n2821), .A1(DMP_SHT1_EWSW[16]), .B0(n2848), .B1(
DMP_SHT2_EWSW[16]), .Y(n1493) );
AO22XLTS U3488 ( .A0(n1829), .A1(DMP_SFG[16]), .B0(n3084), .B1(
DMP_SHT2_EWSW[16]), .Y(n1492) );
AO22XLTS U3489 ( .A0(n2831), .A1(DMP_EXP_EWSW[17]), .B0(n2820), .B1(
DMP_SHT1_EWSW[17]), .Y(n1491) );
AO22XLTS U3490 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n2824), .B1(
DMP_SHT2_EWSW[17]), .Y(n1490) );
AO22XLTS U3491 ( .A0(n1829), .A1(DMP_SFG[17]), .B0(n2822), .B1(
DMP_SHT2_EWSW[17]), .Y(n1489) );
INVX4TS U3492 ( .A(n2842), .Y(n2835) );
AO22XLTS U3493 ( .A0(n2835), .A1(DMP_EXP_EWSW[18]), .B0(n2820), .B1(
DMP_SHT1_EWSW[18]), .Y(n1488) );
AO22XLTS U3494 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n2848), .B1(
DMP_SHT2_EWSW[18]), .Y(n1487) );
AO22XLTS U3495 ( .A0(n1829), .A1(DMP_SFG[18]), .B0(n3078), .B1(
DMP_SHT2_EWSW[18]), .Y(n1486) );
INVX4TS U3496 ( .A(n2842), .Y(n2832) );
AO22XLTS U3497 ( .A0(n2832), .A1(DMP_EXP_EWSW[19]), .B0(n2820), .B1(
DMP_SHT1_EWSW[19]), .Y(n1485) );
AO22XLTS U3498 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n2824), .B1(
DMP_SHT2_EWSW[19]), .Y(n1484) );
AO22XLTS U3499 ( .A0(n1829), .A1(DMP_SFG[19]), .B0(n3084), .B1(
DMP_SHT2_EWSW[19]), .Y(n1483) );
INVX4TS U3500 ( .A(n2842), .Y(n2831) );
AO22XLTS U3501 ( .A0(n2831), .A1(DMP_EXP_EWSW[20]), .B0(n2820), .B1(
DMP_SHT1_EWSW[20]), .Y(n1482) );
AO22XLTS U3502 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n2848), .B1(
DMP_SHT2_EWSW[20]), .Y(n1481) );
AO22XLTS U3503 ( .A0(n2829), .A1(DMP_SFG[20]), .B0(n3084), .B1(
DMP_SHT2_EWSW[20]), .Y(n1480) );
AO22XLTS U3504 ( .A0(n2835), .A1(DMP_EXP_EWSW[21]), .B0(n2820), .B1(
DMP_SHT1_EWSW[21]), .Y(n1479) );
AO22XLTS U3505 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n2824), .B1(
DMP_SHT2_EWSW[21]), .Y(n1478) );
AO22XLTS U3506 ( .A0(n1829), .A1(DMP_SFG[21]), .B0(n2822), .B1(
DMP_SHT2_EWSW[21]), .Y(n1477) );
AO22XLTS U3507 ( .A0(n2832), .A1(DMP_EXP_EWSW[22]), .B0(n2820), .B1(
DMP_SHT1_EWSW[22]), .Y(n1476) );
AO22XLTS U3508 ( .A0(n2821), .A1(DMP_SHT1_EWSW[22]), .B0(n2848), .B1(
DMP_SHT2_EWSW[22]), .Y(n1475) );
AO22XLTS U3509 ( .A0(n1829), .A1(DMP_SFG[22]), .B0(n2822), .B1(
DMP_SHT2_EWSW[22]), .Y(n1474) );
AO22XLTS U3510 ( .A0(n2831), .A1(DMP_EXP_EWSW[23]), .B0(n2820), .B1(
DMP_SHT1_EWSW[23]), .Y(n1473) );
AO22XLTS U3511 ( .A0(n2821), .A1(DMP_SHT1_EWSW[23]), .B0(n2824), .B1(
DMP_SHT2_EWSW[23]), .Y(n1472) );
AO22XLTS U3512 ( .A0(n2845), .A1(DMP_SFG[23]), .B0(n2822), .B1(
DMP_SHT2_EWSW[23]), .Y(n1471) );
AO22XLTS U3513 ( .A0(n2835), .A1(DMP_EXP_EWSW[24]), .B0(n2820), .B1(
DMP_SHT1_EWSW[24]), .Y(n1470) );
BUFX4TS U3514 ( .A(n3300), .Y(n2824) );
AO22XLTS U3515 ( .A0(n2821), .A1(DMP_SHT1_EWSW[24]), .B0(n2818), .B1(
DMP_SHT2_EWSW[24]), .Y(n1469) );
BUFX3TS U3516 ( .A(n1829), .Y(n2826) );
AO22XLTS U3517 ( .A0(n2826), .A1(DMP_SFG[24]), .B0(n2822), .B1(
DMP_SHT2_EWSW[24]), .Y(n1468) );
AO22XLTS U3518 ( .A0(n2832), .A1(DMP_EXP_EWSW[25]), .B0(n2820), .B1(
DMP_SHT1_EWSW[25]), .Y(n1467) );
AO22XLTS U3519 ( .A0(n2821), .A1(DMP_SHT1_EWSW[25]), .B0(n2824), .B1(
DMP_SHT2_EWSW[25]), .Y(n1466) );
AO22XLTS U3520 ( .A0(n3085), .A1(DMP_SFG[25]), .B0(n2822), .B1(
DMP_SHT2_EWSW[25]), .Y(n1465) );
AO22XLTS U3521 ( .A0(n2831), .A1(DMP_EXP_EWSW[26]), .B0(n2823), .B1(
DMP_SHT1_EWSW[26]), .Y(n1464) );
AO22XLTS U3522 ( .A0(n2821), .A1(DMP_SHT1_EWSW[26]), .B0(n2818), .B1(
DMP_SHT2_EWSW[26]), .Y(n1463) );
AO22XLTS U3523 ( .A0(n2826), .A1(DMP_SFG[26]), .B0(n2822), .B1(
DMP_SHT2_EWSW[26]), .Y(n1462) );
AO22XLTS U3524 ( .A0(n2835), .A1(DMP_EXP_EWSW[27]), .B0(n2823), .B1(
DMP_SHT1_EWSW[27]), .Y(n1461) );
AO22XLTS U3525 ( .A0(n2828), .A1(DMP_SHT1_EWSW[27]), .B0(n2819), .B1(
DMP_SHT2_EWSW[27]), .Y(n1460) );
AO22XLTS U3526 ( .A0(n2826), .A1(DMP_SFG[27]), .B0(n2822), .B1(
DMP_SHT2_EWSW[27]), .Y(n1459) );
AO22XLTS U3527 ( .A0(n2832), .A1(DMP_EXP_EWSW[28]), .B0(n2823), .B1(
DMP_SHT1_EWSW[28]), .Y(n1458) );
AO22XLTS U3528 ( .A0(n2828), .A1(DMP_SHT1_EWSW[28]), .B0(n2848), .B1(
DMP_SHT2_EWSW[28]), .Y(n1457) );
AO22XLTS U3529 ( .A0(n2829), .A1(DMP_SFG[28]), .B0(n2822), .B1(
DMP_SHT2_EWSW[28]), .Y(n1456) );
AO22XLTS U3530 ( .A0(n2831), .A1(DMP_EXP_EWSW[29]), .B0(n2823), .B1(
DMP_SHT1_EWSW[29]), .Y(n1455) );
AO22XLTS U3531 ( .A0(n2828), .A1(DMP_SHT1_EWSW[29]), .B0(n2824), .B1(
DMP_SHT2_EWSW[29]), .Y(n1454) );
AO22XLTS U3532 ( .A0(n1829), .A1(DMP_SFG[29]), .B0(n2822), .B1(
DMP_SHT2_EWSW[29]), .Y(n1453) );
INVX4TS U3533 ( .A(n2842), .Y(n2827) );
AO22XLTS U3534 ( .A0(n2827), .A1(DMP_EXP_EWSW[30]), .B0(n2823), .B1(
DMP_SHT1_EWSW[30]), .Y(n1452) );
AO22XLTS U3535 ( .A0(n2828), .A1(DMP_SHT1_EWSW[30]), .B0(n2818), .B1(
DMP_SHT2_EWSW[30]), .Y(n1451) );
AO22XLTS U3536 ( .A0(n2845), .A1(DMP_SFG[30]), .B0(n2822), .B1(
DMP_SHT2_EWSW[30]), .Y(n1450) );
AO22XLTS U3537 ( .A0(n2835), .A1(DMP_EXP_EWSW[31]), .B0(n2823), .B1(
DMP_SHT1_EWSW[31]), .Y(n1449) );
AO22XLTS U3538 ( .A0(n2828), .A1(DMP_SHT1_EWSW[31]), .B0(n2819), .B1(
DMP_SHT2_EWSW[31]), .Y(n1448) );
AO22XLTS U3539 ( .A0(n1829), .A1(DMP_SFG[31]), .B0(n2822), .B1(
DMP_SHT2_EWSW[31]), .Y(n1447) );
AO22XLTS U3540 ( .A0(n2827), .A1(DMP_EXP_EWSW[32]), .B0(n2823), .B1(
DMP_SHT1_EWSW[32]), .Y(n1446) );
AO22XLTS U3541 ( .A0(n2828), .A1(DMP_SHT1_EWSW[32]), .B0(n2848), .B1(
DMP_SHT2_EWSW[32]), .Y(n1445) );
AO22XLTS U3542 ( .A0(n2829), .A1(DMP_SFG[32]), .B0(n2822), .B1(
DMP_SHT2_EWSW[32]), .Y(n1444) );
AO22XLTS U3543 ( .A0(n2832), .A1(DMP_EXP_EWSW[33]), .B0(n2823), .B1(
DMP_SHT1_EWSW[33]), .Y(n1443) );
AO22XLTS U3544 ( .A0(n2828), .A1(DMP_SHT1_EWSW[33]), .B0(n2824), .B1(
DMP_SHT2_EWSW[33]), .Y(n1442) );
AO22XLTS U3545 ( .A0(n1829), .A1(DMP_SFG[33]), .B0(n2822), .B1(
DMP_SHT2_EWSW[33]), .Y(n1441) );
AO22XLTS U3546 ( .A0(n2827), .A1(DMP_EXP_EWSW[34]), .B0(n2823), .B1(
DMP_SHT1_EWSW[34]), .Y(n1440) );
AO22XLTS U3547 ( .A0(n2828), .A1(DMP_SHT1_EWSW[34]), .B0(n2818), .B1(
DMP_SHT2_EWSW[34]), .Y(n1439) );
AO22XLTS U3548 ( .A0(n2829), .A1(DMP_SFG[34]), .B0(n2822), .B1(
DMP_SHT2_EWSW[34]), .Y(n1438) );
AO22XLTS U3549 ( .A0(n2831), .A1(DMP_EXP_EWSW[35]), .B0(n2823), .B1(
DMP_SHT1_EWSW[35]), .Y(n1437) );
AO22XLTS U3550 ( .A0(n2849), .A1(DMP_SHT1_EWSW[35]), .B0(n2819), .B1(
DMP_SHT2_EWSW[35]), .Y(n1436) );
AO22XLTS U3551 ( .A0(n2826), .A1(DMP_SFG[35]), .B0(n2825), .B1(
DMP_SHT2_EWSW[35]), .Y(n1435) );
AO22XLTS U3552 ( .A0(n2827), .A1(DMP_EXP_EWSW[36]), .B0(n2823), .B1(
DMP_SHT1_EWSW[36]), .Y(n1434) );
AO22XLTS U3553 ( .A0(n2849), .A1(DMP_SHT1_EWSW[36]), .B0(n2848), .B1(
DMP_SHT2_EWSW[36]), .Y(n1433) );
AO22XLTS U3554 ( .A0(n2829), .A1(DMP_SFG[36]), .B0(n2825), .B1(
DMP_SHT2_EWSW[36]), .Y(n1432) );
BUFX3TS U3555 ( .A(n3305), .Y(n2833) );
AO22XLTS U3556 ( .A0(n2827), .A1(DMP_EXP_EWSW[37]), .B0(n2833), .B1(
DMP_SHT1_EWSW[37]), .Y(n1431) );
AO22XLTS U3557 ( .A0(n2849), .A1(DMP_SHT1_EWSW[37]), .B0(n2824), .B1(
DMP_SHT2_EWSW[37]), .Y(n1430) );
AO22XLTS U3558 ( .A0(n2829), .A1(DMP_SFG[37]), .B0(n2825), .B1(
DMP_SHT2_EWSW[37]), .Y(n1429) );
AO22XLTS U3559 ( .A0(n2827), .A1(DMP_EXP_EWSW[38]), .B0(n2833), .B1(
DMP_SHT1_EWSW[38]), .Y(n1428) );
AO22XLTS U3560 ( .A0(n2849), .A1(DMP_SHT1_EWSW[38]), .B0(n2848), .B1(
DMP_SHT2_EWSW[38]), .Y(n1427) );
AO22XLTS U3561 ( .A0(n2826), .A1(DMP_SFG[38]), .B0(n2825), .B1(
DMP_SHT2_EWSW[38]), .Y(n1426) );
INVX4TS U3562 ( .A(n2833), .Y(n2843) );
AO22XLTS U3563 ( .A0(n2843), .A1(DMP_EXP_EWSW[39]), .B0(n2833), .B1(
DMP_SHT1_EWSW[39]), .Y(n1425) );
AO22XLTS U3564 ( .A0(n2849), .A1(DMP_SHT1_EWSW[39]), .B0(n2824), .B1(
DMP_SHT2_EWSW[39]), .Y(n1424) );
AO22XLTS U3565 ( .A0(n2845), .A1(DMP_SFG[39]), .B0(n2825), .B1(
DMP_SHT2_EWSW[39]), .Y(n1423) );
INVX4TS U3566 ( .A(n2823), .Y(n2847) );
AO22XLTS U3567 ( .A0(n2847), .A1(DMP_EXP_EWSW[40]), .B0(n2833), .B1(
DMP_SHT1_EWSW[40]), .Y(n1422) );
AO22XLTS U3568 ( .A0(n2828), .A1(DMP_SHT1_EWSW[40]), .B0(n2848), .B1(
DMP_SHT2_EWSW[40]), .Y(n1421) );
AO22XLTS U3569 ( .A0(n2829), .A1(DMP_SFG[40]), .B0(n2825), .B1(
DMP_SHT2_EWSW[40]), .Y(n1420) );
AO22XLTS U3570 ( .A0(n2843), .A1(DMP_EXP_EWSW[41]), .B0(n2833), .B1(
DMP_SHT1_EWSW[41]), .Y(n1419) );
AO22XLTS U3571 ( .A0(n2828), .A1(DMP_SHT1_EWSW[41]), .B0(n2824), .B1(
DMP_SHT2_EWSW[41]), .Y(n1418) );
AO22XLTS U3572 ( .A0(n2829), .A1(DMP_SFG[41]), .B0(n2825), .B1(
DMP_SHT2_EWSW[41]), .Y(n1417) );
AO22XLTS U3573 ( .A0(n2827), .A1(DMP_EXP_EWSW[42]), .B0(n2833), .B1(
DMP_SHT1_EWSW[42]), .Y(n1416) );
AO22XLTS U3574 ( .A0(n2828), .A1(DMP_SHT1_EWSW[42]), .B0(n2848), .B1(
DMP_SHT2_EWSW[42]), .Y(n1415) );
AO22XLTS U3575 ( .A0(n2826), .A1(DMP_SFG[42]), .B0(n2825), .B1(
DMP_SHT2_EWSW[42]), .Y(n1414) );
AO22XLTS U3576 ( .A0(n2827), .A1(DMP_EXP_EWSW[43]), .B0(n2833), .B1(
DMP_SHT1_EWSW[43]), .Y(n1413) );
AO22XLTS U3577 ( .A0(n2828), .A1(DMP_SHT1_EWSW[43]), .B0(n2824), .B1(
DMP_SHT2_EWSW[43]), .Y(n1412) );
AO22XLTS U3578 ( .A0(n2829), .A1(DMP_SFG[43]), .B0(n2825), .B1(
DMP_SHT2_EWSW[43]), .Y(n1411) );
AO22XLTS U3579 ( .A0(n2827), .A1(DMP_EXP_EWSW[44]), .B0(n2833), .B1(
DMP_SHT1_EWSW[44]), .Y(n1410) );
AO22XLTS U3580 ( .A0(n2828), .A1(DMP_SHT1_EWSW[44]), .B0(n2818), .B1(
DMP_SHT2_EWSW[44]), .Y(n1409) );
AO22XLTS U3581 ( .A0(n2826), .A1(DMP_SFG[44]), .B0(n2825), .B1(
DMP_SHT2_EWSW[44]), .Y(n1408) );
AO22XLTS U3582 ( .A0(n2827), .A1(DMP_EXP_EWSW[45]), .B0(n2833), .B1(
DMP_SHT1_EWSW[45]), .Y(n1407) );
AO22XLTS U3583 ( .A0(n2828), .A1(DMP_SHT1_EWSW[45]), .B0(n2819), .B1(
DMP_SHT2_EWSW[45]), .Y(n1406) );
AO22XLTS U3584 ( .A0(n2826), .A1(DMP_SFG[45]), .B0(n2825), .B1(
DMP_SHT2_EWSW[45]), .Y(n1405) );
AO22XLTS U3585 ( .A0(n2827), .A1(DMP_EXP_EWSW[46]), .B0(n2833), .B1(
DMP_SHT1_EWSW[46]), .Y(n1404) );
AO22XLTS U3586 ( .A0(n2828), .A1(DMP_SHT1_EWSW[46]), .B0(n2818), .B1(
DMP_SHT2_EWSW[46]), .Y(n1403) );
AO22XLTS U3587 ( .A0(n2826), .A1(DMP_SFG[46]), .B0(n2825), .B1(
DMP_SHT2_EWSW[46]), .Y(n1402) );
AO22XLTS U3588 ( .A0(n2827), .A1(DMP_EXP_EWSW[47]), .B0(n2833), .B1(
DMP_SHT1_EWSW[47]), .Y(n1401) );
AO22XLTS U3589 ( .A0(n2828), .A1(DMP_SHT1_EWSW[47]), .B0(n2818), .B1(
DMP_SHT2_EWSW[47]), .Y(n1400) );
AO22XLTS U3590 ( .A0(n2829), .A1(DMP_SFG[47]), .B0(n2825), .B1(
DMP_SHT2_EWSW[47]), .Y(n1399) );
BUFX4TS U3591 ( .A(n2842), .Y(n2846) );
AO22XLTS U3592 ( .A0(n2827), .A1(DMP_EXP_EWSW[48]), .B0(n2846), .B1(
DMP_SHT1_EWSW[48]), .Y(n1398) );
AO22XLTS U3593 ( .A0(n2828), .A1(DMP_SHT1_EWSW[48]), .B0(n2819), .B1(
DMP_SHT2_EWSW[48]), .Y(n1397) );
AO22XLTS U3594 ( .A0(n2826), .A1(DMP_SFG[48]), .B0(n2825), .B1(
DMP_SHT2_EWSW[48]), .Y(n1396) );
AO22XLTS U3595 ( .A0(n2827), .A1(DMP_EXP_EWSW[49]), .B0(n2846), .B1(
DMP_SHT1_EWSW[49]), .Y(n1395) );
AO22XLTS U3596 ( .A0(n2828), .A1(DMP_SHT1_EWSW[49]), .B0(n2818), .B1(
DMP_SHT2_EWSW[49]), .Y(n1394) );
AO22XLTS U3597 ( .A0(n2826), .A1(DMP_SFG[49]), .B0(n3082), .B1(
DMP_SHT2_EWSW[49]), .Y(n1393) );
AO22XLTS U3598 ( .A0(n2827), .A1(DMP_EXP_EWSW[50]), .B0(n2846), .B1(
DMP_SHT1_EWSW[50]), .Y(n1392) );
AO22XLTS U3599 ( .A0(n2828), .A1(DMP_SHT1_EWSW[50]), .B0(n2819), .B1(
DMP_SHT2_EWSW[50]), .Y(n1391) );
AO22XLTS U3600 ( .A0(n2826), .A1(DMP_SFG[50]), .B0(n2872), .B1(
DMP_SHT2_EWSW[50]), .Y(n1390) );
AO22XLTS U3601 ( .A0(n2827), .A1(DMP_EXP_EWSW[51]), .B0(n2846), .B1(
DMP_SHT1_EWSW[51]), .Y(n1389) );
AO22XLTS U3602 ( .A0(n2828), .A1(DMP_SHT1_EWSW[51]), .B0(n2818), .B1(
DMP_SHT2_EWSW[51]), .Y(n1388) );
AO22XLTS U3603 ( .A0(n2826), .A1(DMP_SFG[51]), .B0(n3084), .B1(
DMP_SHT2_EWSW[51]), .Y(n1387) );
AO22XLTS U3604 ( .A0(n2827), .A1(DMP_EXP_EWSW[52]), .B0(n2846), .B1(
DMP_SHT1_EWSW[52]), .Y(n1386) );
AO22XLTS U3605 ( .A0(n2828), .A1(DMP_SHT1_EWSW[52]), .B0(n2819), .B1(
DMP_SHT2_EWSW[52]), .Y(n1385) );
AO22XLTS U3606 ( .A0(n3082), .A1(DMP_SHT2_EWSW[52]), .B0(n2826), .B1(
DMP_SFG[52]), .Y(n1384) );
AO22XLTS U3607 ( .A0(n2877), .A1(DMP_SFG[52]), .B0(n3302), .B1(
DMP_exp_NRM_EW[0]), .Y(n1383) );
AO22XLTS U3608 ( .A0(n2827), .A1(DMP_EXP_EWSW[53]), .B0(n2846), .B1(
DMP_SHT1_EWSW[53]), .Y(n1381) );
AO22XLTS U3609 ( .A0(n2828), .A1(DMP_SHT1_EWSW[53]), .B0(n3300), .B1(
DMP_SHT2_EWSW[53]), .Y(n1380) );
AO22XLTS U3610 ( .A0(n2825), .A1(DMP_SHT2_EWSW[53]), .B0(n2829), .B1(
DMP_SFG[53]), .Y(n1379) );
AO22XLTS U3611 ( .A0(n2904), .A1(DMP_SFG[53]), .B0(n3302), .B1(
DMP_exp_NRM_EW[1]), .Y(n1378) );
AO22XLTS U3612 ( .A0(n2831), .A1(DMP_EXP_EWSW[54]), .B0(n2846), .B1(
DMP_SHT1_EWSW[54]), .Y(n1376) );
AO22XLTS U3613 ( .A0(n2828), .A1(DMP_SHT1_EWSW[54]), .B0(n3300), .B1(
DMP_SHT2_EWSW[54]), .Y(n1375) );
AO22XLTS U3614 ( .A0(n3082), .A1(DMP_SHT2_EWSW[54]), .B0(n1829), .B1(
DMP_SFG[54]), .Y(n1374) );
AO22XLTS U3615 ( .A0(n2940), .A1(DMP_SFG[54]), .B0(n3302), .B1(
DMP_exp_NRM_EW[2]), .Y(n1373) );
AO22XLTS U3616 ( .A0(n2831), .A1(DMP_EXP_EWSW[55]), .B0(n2846), .B1(
DMP_SHT1_EWSW[55]), .Y(n1371) );
AO22XLTS U3617 ( .A0(n2849), .A1(DMP_SHT1_EWSW[55]), .B0(n2818), .B1(
DMP_SHT2_EWSW[55]), .Y(n1370) );
AO22XLTS U3618 ( .A0(n2822), .A1(DMP_SHT2_EWSW[55]), .B0(n3065), .B1(
DMP_SFG[55]), .Y(n1369) );
AO22XLTS U3619 ( .A0(n2877), .A1(DMP_SFG[55]), .B0(n3302), .B1(
DMP_exp_NRM_EW[3]), .Y(n1368) );
AO22XLTS U3620 ( .A0(n2831), .A1(DMP_EXP_EWSW[56]), .B0(n2846), .B1(
DMP_SHT1_EWSW[56]), .Y(n1366) );
AO22XLTS U3621 ( .A0(n2849), .A1(DMP_SHT1_EWSW[56]), .B0(n2819), .B1(
DMP_SHT2_EWSW[56]), .Y(n1365) );
AO22XLTS U3622 ( .A0(n3082), .A1(DMP_SHT2_EWSW[56]), .B0(n1829), .B1(
DMP_SFG[56]), .Y(n1364) );
AO22XLTS U3623 ( .A0(n2904), .A1(DMP_SFG[56]), .B0(n3302), .B1(
DMP_exp_NRM_EW[4]), .Y(n1363) );
AO22XLTS U3624 ( .A0(n2831), .A1(DMP_EXP_EWSW[57]), .B0(n2846), .B1(
DMP_SHT1_EWSW[57]), .Y(n1361) );
AO22XLTS U3625 ( .A0(n2849), .A1(DMP_SHT1_EWSW[57]), .B0(n2818), .B1(
DMP_SHT2_EWSW[57]), .Y(n1360) );
AO22XLTS U3626 ( .A0(n3084), .A1(DMP_SHT2_EWSW[57]), .B0(n2829), .B1(
DMP_SFG[57]), .Y(n1359) );
AO22XLTS U3627 ( .A0(n2940), .A1(DMP_SFG[57]), .B0(n3302), .B1(
DMP_exp_NRM_EW[5]), .Y(n1358) );
AO22XLTS U3628 ( .A0(n2831), .A1(DMP_EXP_EWSW[58]), .B0(n3305), .B1(
DMP_SHT1_EWSW[58]), .Y(n1356) );
AO22XLTS U3629 ( .A0(n2849), .A1(DMP_SHT1_EWSW[58]), .B0(n2819), .B1(
DMP_SHT2_EWSW[58]), .Y(n1355) );
AO22XLTS U3630 ( .A0(n3082), .A1(DMP_SHT2_EWSW[58]), .B0(n3071), .B1(
DMP_SFG[58]), .Y(n1354) );
AO22XLTS U3631 ( .A0(n2877), .A1(DMP_SFG[58]), .B0(n3302), .B1(
DMP_exp_NRM_EW[6]), .Y(n1353) );
AO22XLTS U3632 ( .A0(n2831), .A1(DMP_EXP_EWSW[59]), .B0(n3305), .B1(
DMP_SHT1_EWSW[59]), .Y(n1351) );
AO22XLTS U3633 ( .A0(n2849), .A1(DMP_SHT1_EWSW[59]), .B0(n2818), .B1(
DMP_SHT2_EWSW[59]), .Y(n1350) );
AO22XLTS U3634 ( .A0(n3084), .A1(DMP_SHT2_EWSW[59]), .B0(n2829), .B1(
DMP_SFG[59]), .Y(n1349) );
AO22XLTS U3635 ( .A0(n2904), .A1(DMP_SFG[59]), .B0(n3302), .B1(
DMP_exp_NRM_EW[7]), .Y(n1348) );
AO22XLTS U3636 ( .A0(n2831), .A1(DMP_EXP_EWSW[60]), .B0(n3305), .B1(
DMP_SHT1_EWSW[60]), .Y(n1346) );
AO22XLTS U3637 ( .A0(n2849), .A1(DMP_SHT1_EWSW[60]), .B0(n2819), .B1(
DMP_SHT2_EWSW[60]), .Y(n1345) );
AO22XLTS U3638 ( .A0(n3082), .A1(DMP_SHT2_EWSW[60]), .B0(n2829), .B1(
DMP_SFG[60]), .Y(n1344) );
AO22XLTS U3639 ( .A0(n2940), .A1(DMP_SFG[60]), .B0(n3302), .B1(
DMP_exp_NRM_EW[8]), .Y(n1343) );
AO22XLTS U3640 ( .A0(n2831), .A1(DMP_EXP_EWSW[61]), .B0(n3305), .B1(
DMP_SHT1_EWSW[61]), .Y(n1341) );
AO22XLTS U3641 ( .A0(n2849), .A1(DMP_SHT1_EWSW[61]), .B0(n2818), .B1(
DMP_SHT2_EWSW[61]), .Y(n1340) );
AO22XLTS U3642 ( .A0(n2830), .A1(DMP_SHT2_EWSW[61]), .B0(n1829), .B1(
DMP_SFG[61]), .Y(n1339) );
AO22XLTS U3643 ( .A0(n2877), .A1(DMP_SFG[61]), .B0(n3302), .B1(
DMP_exp_NRM_EW[9]), .Y(n1338) );
AO22XLTS U3644 ( .A0(n2831), .A1(DMP_EXP_EWSW[62]), .B0(n3305), .B1(
DMP_SHT1_EWSW[62]), .Y(n1336) );
AO22XLTS U3645 ( .A0(n2849), .A1(DMP_SHT1_EWSW[62]), .B0(n2819), .B1(
DMP_SHT2_EWSW[62]), .Y(n1335) );
AO22XLTS U3646 ( .A0(n3082), .A1(DMP_SHT2_EWSW[62]), .B0(n2829), .B1(
DMP_SFG[62]), .Y(n1334) );
AO22XLTS U3647 ( .A0(n2904), .A1(DMP_SFG[62]), .B0(n3302), .B1(
DMP_exp_NRM_EW[10]), .Y(n1333) );
BUFX3TS U3648 ( .A(n3305), .Y(n2836) );
BUFX4TS U3649 ( .A(n2836), .Y(n2844) );
AO22XLTS U3650 ( .A0(n2843), .A1(DmP_EXP_EWSW[50]), .B0(n2842), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1230) );
AO22XLTS U3651 ( .A0(n2843), .A1(DmP_EXP_EWSW[51]), .B0(n2842), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1228) );
OAI222X1TS U3652 ( .A0(n2839), .A1(n3150), .B0(n3093), .B1(n1863), .C0(n3087), .C1(n2838), .Y(n1225) );
OAI222X1TS U3653 ( .A0(n2839), .A1(n3299), .B0(n3095), .B1(n1863), .C0(n1854), .C1(n2838), .Y(n1224) );
OAI222X1TS U3654 ( .A0(n2839), .A1(n3094), .B0(n3089), .B1(n1863), .C0(n1853), .C1(n2838), .Y(n1223) );
NAND2X1TS U3655 ( .A(n3306), .B(n2851), .Y(n2840) );
OAI2BB1X1TS U3656 ( .A0N(underflow_flag), .A1N(n3000), .B0(n2840), .Y(n1221)
);
OA21XLTS U3657 ( .A0(n3306), .A1(overflow_flag), .B0(n2841), .Y(n1220) );
AO22XLTS U3658 ( .A0(n2843), .A1(ZERO_FLAG_EXP), .B0(n2842), .B1(
ZERO_FLAG_SHT1), .Y(n1219) );
AO22XLTS U3659 ( .A0(n2849), .A1(ZERO_FLAG_SHT1), .B0(n2818), .B1(
ZERO_FLAG_SHT2), .Y(n1218) );
AO22XLTS U3660 ( .A0(n2825), .A1(ZERO_FLAG_SHT2), .B0(n1829), .B1(
ZERO_FLAG_SFG), .Y(n1217) );
AO22XLTS U3661 ( .A0(n2940), .A1(ZERO_FLAG_SFG), .B0(n3302), .B1(
ZERO_FLAG_NRM), .Y(n1216) );
AO22XLTS U3662 ( .A0(n3306), .A1(ZERO_FLAG_SHT1SHT2), .B0(n3027), .B1(
zero_flag), .Y(n1214) );
AO22XLTS U3663 ( .A0(n2847), .A1(OP_FLAG_EXP), .B0(n2844), .B1(OP_FLAG_SHT1),
.Y(n1213) );
AO22XLTS U3664 ( .A0(n2849), .A1(OP_FLAG_SHT1), .B0(n2819), .B1(OP_FLAG_SHT2), .Y(n1212) );
AO22XLTS U3665 ( .A0(n2845), .A1(n2887), .B0(n2872), .B1(OP_FLAG_SHT2), .Y(
n1211) );
AO22XLTS U3666 ( .A0(n2847), .A1(SIGN_FLAG_EXP), .B0(n2846), .B1(
SIGN_FLAG_SHT1), .Y(n1210) );
AO22XLTS U3667 ( .A0(n2849), .A1(SIGN_FLAG_SHT1), .B0(n2819), .B1(
SIGN_FLAG_SHT2), .Y(n1209) );
AO22XLTS U3668 ( .A0(n3084), .A1(SIGN_FLAG_SHT2), .B0(n3065), .B1(
SIGN_FLAG_SFG), .Y(n1208) );
AO22XLTS U3669 ( .A0(n2877), .A1(SIGN_FLAG_SFG), .B0(n3302), .B1(
SIGN_FLAG_NRM), .Y(n1207) );
OAI211XLTS U3670 ( .A0(n2851), .A1(SIGN_FLAG_SHT1SHT2), .B0(n3306), .C0(
n2850), .Y(n2852) );
OAI2BB1X1TS U3671 ( .A0N(final_result_ieee[63]), .A1N(n3027), .B0(n2852),
.Y(n1205) );
AOI22X1TS U3672 ( .A0(n2896), .A1(n1901), .B0(DmP_mant_SFG_SWR[14]), .B1(
n2853), .Y(intadd_74_CI) );
AOI22X1TS U3673 ( .A0(n2932), .A1(intadd_74_SUM_0_), .B0(n3295), .B1(n2938),
.Y(n1204) );
AOI22X1TS U3674 ( .A0(n2896), .A1(n1902), .B0(DmP_mant_SFG_SWR[15]), .B1(
n2853), .Y(intadd_74_B_1_) );
AOI22X1TS U3675 ( .A0(n2932), .A1(intadd_74_SUM_1_), .B0(n3169), .B1(n2938),
.Y(n1203) );
AOI22X1TS U3676 ( .A0(n2887), .A1(n1903), .B0(DmP_mant_SFG_SWR[16]), .B1(
n2853), .Y(intadd_74_B_2_) );
AOI2BB2XLTS U3677 ( .B0(n2877), .B1(intadd_74_SUM_2_), .A0N(
Raw_mant_NRM_SWR[16]), .A1N(n2877), .Y(n1202) );
AOI22X1TS U3678 ( .A0(n2887), .A1(n1904), .B0(DmP_mant_SFG_SWR[17]), .B1(
n2853), .Y(intadd_74_B_3_) );
AOI22X1TS U3679 ( .A0(n2904), .A1(intadd_74_SUM_3_), .B0(n3166), .B1(n2938),
.Y(n1201) );
AOI22X1TS U3680 ( .A0(n2887), .A1(n1842), .B0(DmP_mant_SFG_SWR[18]), .B1(
n2853), .Y(intadd_74_B_4_) );
AOI22X1TS U3681 ( .A0(n2877), .A1(intadd_74_SUM_4_), .B0(n3103), .B1(n2938),
.Y(n1200) );
AOI22X1TS U3682 ( .A0(n2896), .A1(n1881), .B0(DmP_mant_SFG_SWR[19]), .B1(
n2853), .Y(intadd_74_B_5_) );
AOI22X1TS U3683 ( .A0(n2904), .A1(intadd_74_SUM_5_), .B0(n3186), .B1(n2938),
.Y(n1199) );
AOI22X1TS U3684 ( .A0(n2887), .A1(n1882), .B0(DmP_mant_SFG_SWR[20]), .B1(
n2853), .Y(intadd_74_B_6_) );
AOI22X1TS U3685 ( .A0(n2904), .A1(intadd_74_SUM_6_), .B0(n3105), .B1(n2938),
.Y(n1198) );
AOI22X1TS U3686 ( .A0(n2887), .A1(n1883), .B0(DmP_mant_SFG_SWR[21]), .B1(
n2853), .Y(intadd_74_B_7_) );
AOI22X1TS U3687 ( .A0(n2940), .A1(intadd_74_SUM_7_), .B0(n3163), .B1(n2938),
.Y(n1197) );
AOI22X1TS U3688 ( .A0(n2896), .A1(n1884), .B0(DmP_mant_SFG_SWR[22]), .B1(
n2853), .Y(intadd_74_B_8_) );
AOI2BB2XLTS U3689 ( .B0(n2940), .B1(intadd_74_SUM_8_), .A0N(
Raw_mant_NRM_SWR[22]), .A1N(n2932), .Y(n1196) );
AOI2BB2XLTS U3690 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n3102), .A0N(n2869),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_74_B_9_) );
AOI2BB2XLTS U3691 ( .B0(n2940), .B1(intadd_74_SUM_9_), .A0N(
Raw_mant_NRM_SWR[23]), .A1N(n2940), .Y(n1195) );
AOI2BB2XLTS U3692 ( .B0(DmP_mant_SFG_SWR[24]), .B1(n3102), .A0N(n2869),
.A1N(DmP_mant_SFG_SWR[24]), .Y(intadd_74_B_10_) );
AOI22X1TS U3693 ( .A0(n2940), .A1(intadd_74_SUM_10_), .B0(n3289), .B1(n2938),
.Y(n1194) );
AOI2BB2XLTS U3694 ( .B0(DmP_mant_SFG_SWR[25]), .B1(n2881), .A0N(n2869),
.A1N(DmP_mant_SFG_SWR[25]), .Y(intadd_74_B_11_) );
AOI22X1TS U3695 ( .A0(n2877), .A1(intadd_74_SUM_11_), .B0(n3161), .B1(n2938),
.Y(n1193) );
AOI2BB2XLTS U3696 ( .B0(DmP_mant_SFG_SWR[26]), .B1(n2881), .A0N(n2869),
.A1N(DmP_mant_SFG_SWR[26]), .Y(intadd_74_B_12_) );
AOI22X1TS U3697 ( .A0(n2904), .A1(intadd_74_SUM_12_), .B0(n3144), .B1(n2938),
.Y(n1192) );
AOI2BB2XLTS U3698 ( .B0(DmP_mant_SFG_SWR[27]), .B1(n2881), .A0N(n2869),
.A1N(DmP_mant_SFG_SWR[27]), .Y(intadd_74_B_13_) );
AOI22X1TS U3699 ( .A0(n2940), .A1(intadd_74_SUM_13_), .B0(n3101), .B1(n2938),
.Y(n1191) );
AOI2BB2XLTS U3700 ( .B0(DmP_mant_SFG_SWR[28]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[28]), .Y(intadd_74_B_14_) );
AOI22X1TS U3701 ( .A0(n2877), .A1(intadd_74_SUM_14_), .B0(n3121), .B1(n2938),
.Y(n1190) );
AOI2BB2XLTS U3702 ( .B0(DmP_mant_SFG_SWR[29]), .B1(n2881), .A0N(n2881),
.A1N(DmP_mant_SFG_SWR[29]), .Y(intadd_74_B_15_) );
AOI2BB2XLTS U3703 ( .B0(n2940), .B1(intadd_74_SUM_15_), .A0N(
Raw_mant_NRM_SWR[29]), .A1N(n2904), .Y(n1189) );
AOI2BB2XLTS U3704 ( .B0(DmP_mant_SFG_SWR[30]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[30]), .Y(intadd_74_B_16_) );
AOI22X1TS U3705 ( .A0(n2940), .A1(intadd_74_SUM_16_), .B0(n3100), .B1(n2938),
.Y(n1188) );
AOI2BB2XLTS U3706 ( .B0(DmP_mant_SFG_SWR[31]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[31]), .Y(intadd_74_B_17_) );
AOI22X1TS U3707 ( .A0(n2877), .A1(intadd_74_SUM_17_), .B0(n3108), .B1(n2938),
.Y(n1187) );
AOI22X1TS U3708 ( .A0(n2887), .A1(n1885), .B0(DmP_mant_SFG_SWR[32]), .B1(
n2869), .Y(intadd_74_B_18_) );
AOI22X1TS U3709 ( .A0(n2904), .A1(intadd_74_SUM_18_), .B0(n3090), .B1(n2938),
.Y(n1186) );
AOI22X1TS U3710 ( .A0(n2887), .A1(n1886), .B0(DmP_mant_SFG_SWR[33]), .B1(
n2869), .Y(intadd_74_B_19_) );
AOI22X1TS U3711 ( .A0(n2940), .A1(intadd_74_SUM_19_), .B0(n3099), .B1(n2938),
.Y(n1185) );
AOI22X1TS U3712 ( .A0(n2896), .A1(n1887), .B0(DmP_mant_SFG_SWR[34]), .B1(
n2869), .Y(intadd_74_B_20_) );
AOI22X1TS U3713 ( .A0(n2877), .A1(intadd_74_SUM_20_), .B0(n3146), .B1(n3302),
.Y(n1184) );
AOI22X1TS U3714 ( .A0(n2887), .A1(n1888), .B0(DmP_mant_SFG_SWR[35]), .B1(
n2869), .Y(intadd_74_B_21_) );
AOI22X1TS U3715 ( .A0(n2904), .A1(intadd_74_SUM_21_), .B0(n3098), .B1(n2938),
.Y(n1183) );
AOI22X1TS U3716 ( .A0(n2887), .A1(n1889), .B0(DmP_mant_SFG_SWR[36]), .B1(
n2869), .Y(intadd_74_B_22_) );
AOI22X1TS U3717 ( .A0(n2940), .A1(intadd_74_SUM_22_), .B0(n3097), .B1(n3302),
.Y(n1182) );
AOI22X1TS U3718 ( .A0(n2896), .A1(n1890), .B0(DmP_mant_SFG_SWR[37]), .B1(
n2869), .Y(intadd_74_B_23_) );
AOI2BB2XLTS U3719 ( .B0(n2877), .B1(intadd_74_SUM_23_), .A0N(
Raw_mant_NRM_SWR[37]), .A1N(n2932), .Y(n1181) );
AOI22X1TS U3720 ( .A0(n2887), .A1(n1891), .B0(DmP_mant_SFG_SWR[38]), .B1(
n2869), .Y(intadd_74_B_24_) );
AOI2BB2XLTS U3721 ( .B0(n2904), .B1(intadd_74_SUM_24_), .A0N(
Raw_mant_NRM_SWR[38]), .A1N(n2904), .Y(n1180) );
AOI22X1TS U3722 ( .A0(n2887), .A1(n1892), .B0(DmP_mant_SFG_SWR[39]), .B1(
n2869), .Y(intadd_74_B_25_) );
AOI2BB2XLTS U3723 ( .B0(n2940), .B1(intadd_74_SUM_25_), .A0N(
Raw_mant_NRM_SWR[39]), .A1N(n2940), .Y(n1179) );
AOI22X1TS U3724 ( .A0(n2896), .A1(n1893), .B0(DmP_mant_SFG_SWR[40]), .B1(
n2869), .Y(intadd_74_B_26_) );
AOI22X1TS U3725 ( .A0(n2940), .A1(intadd_74_SUM_26_), .B0(n3193), .B1(n2910),
.Y(n1178) );
AOI22X1TS U3726 ( .A0(n2887), .A1(n1895), .B0(DmP_mant_SFG_SWR[41]), .B1(
n2869), .Y(intadd_74_B_27_) );
AOI22X1TS U3727 ( .A0(n2877), .A1(intadd_74_SUM_27_), .B0(n3154), .B1(n2910),
.Y(n1177) );
AOI22X1TS U3728 ( .A0(n2887), .A1(n1896), .B0(DmP_mant_SFG_SWR[42]), .B1(
n2869), .Y(intadd_74_B_28_) );
AOI22X1TS U3729 ( .A0(n2877), .A1(intadd_74_SUM_28_), .B0(n3195), .B1(n2910),
.Y(n1176) );
AOI2BB2XLTS U3730 ( .B0(DmP_mant_SFG_SWR[43]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[43]), .Y(intadd_74_B_29_) );
AOI22X1TS U3731 ( .A0(n2904), .A1(intadd_74_SUM_29_), .B0(n3153), .B1(n2910),
.Y(n1175) );
AOI22X1TS U3732 ( .A0(n2896), .A1(n1898), .B0(DmP_mant_SFG_SWR[44]), .B1(
n2869), .Y(intadd_74_B_30_) );
AOI2BB2XLTS U3733 ( .B0(n2904), .B1(intadd_74_SUM_30_), .A0N(
Raw_mant_NRM_SWR[44]), .A1N(n2932), .Y(n1174) );
AOI2BB2XLTS U3734 ( .B0(DmP_mant_SFG_SWR[45]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[45]), .Y(intadd_74_B_31_) );
AOI2BB2XLTS U3735 ( .B0(n2877), .B1(intadd_74_SUM_31_), .A0N(
Raw_mant_NRM_SWR[45]), .A1N(n2877), .Y(n1173) );
AOI2BB2XLTS U3736 ( .B0(DmP_mant_SFG_SWR[46]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[46]), .Y(intadd_74_B_32_) );
AOI22X1TS U3737 ( .A0(n2932), .A1(intadd_74_SUM_32_), .B0(n3214), .B1(n2910),
.Y(n1172) );
AOI2BB2XLTS U3738 ( .B0(DmP_mant_SFG_SWR[47]), .B1(n2881), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[47]), .Y(intadd_74_B_33_) );
AOI2BB2XLTS U3739 ( .B0(DmP_mant_SFG_SWR[48]), .B1(n3102), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[48]), .Y(intadd_74_B_34_) );
AOI2BB2XLTS U3740 ( .B0(DmP_mant_SFG_SWR[49]), .B1(n3102), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[49]), .Y(intadd_74_B_35_) );
AOI22X1TS U3741 ( .A0(n2932), .A1(intadd_74_SUM_35_), .B0(n3152), .B1(n2910),
.Y(n1169) );
AOI2BB2XLTS U3742 ( .B0(DmP_mant_SFG_SWR[50]), .B1(n3102), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[50]), .Y(intadd_74_B_36_) );
AOI22X1TS U3743 ( .A0(n2940), .A1(intadd_74_SUM_36_), .B0(n3096), .B1(n2910),
.Y(n1168) );
AOI2BB2XLTS U3744 ( .B0(DmP_mant_SFG_SWR[51]), .B1(n3102), .A0N(n2881),
.A1N(DmP_mant_SFG_SWR[51]), .Y(intadd_74_B_37_) );
AOI2BB2XLTS U3745 ( .B0(DmP_mant_SFG_SWR[52]), .B1(n2853), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[52]), .Y(intadd_74_B_38_) );
AOI2BB2XLTS U3746 ( .B0(DmP_mant_SFG_SWR[53]), .B1(n2869), .A0N(n2853),
.A1N(DmP_mant_SFG_SWR[53]), .Y(intadd_74_B_39_) );
AOI22X1TS U3747 ( .A0(n2932), .A1(intadd_74_SUM_39_), .B0(n3116), .B1(n2910),
.Y(n1165) );
AOI2BB2XLTS U3748 ( .B0(n2887), .B1(DmP_mant_SFG_SWR[54]), .A0N(
DmP_mant_SFG_SWR[54]), .A1N(n2896), .Y(n2854) );
XNOR2X1TS U3749 ( .A(intadd_74_n1), .B(n2854), .Y(n2855) );
AOI22X1TS U3750 ( .A0(n2932), .A1(n2855), .B0(n3199), .B1(n2910), .Y(n1164)
);
AOI22X1TS U3751 ( .A0(Data_array_SWR[13]), .A1(n3041), .B0(n1880), .B1(n1828), .Y(n2857) );
AOI22X1TS U3752 ( .A0(n1877), .A1(n3042), .B0(n1868), .B1(n1858), .Y(n2856)
);
OAI211X1TS U3753 ( .A0(n2998), .A1(n3018), .B0(n2857), .C0(n2856), .Y(n2997)
);
AOI22X1TS U3754 ( .A0(n3078), .A1(n2994), .B0(n1894), .B1(n3085), .Y(n1163)
);
AOI22X1TS U3755 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[10]), .B0(n1897),
.B1(n2881), .Y(n2925) );
NAND2X1TS U3756 ( .A(n2925), .B(DMP_SFG[8]), .Y(n2858) );
XNOR2X1TS U3757 ( .A(DMP_SFG[11]), .B(n1859), .Y(n2859) );
XNOR2X1TS U3758 ( .A(n2860), .B(n2859), .Y(n2861) );
AOI22X1TS U3759 ( .A0(n2932), .A1(n2861), .B0(n3172), .B1(n2910), .Y(n1162)
);
OAI22X1TS U3760 ( .A0(n2952), .A1(n2862), .B0(n3271), .B1(n2866), .Y(n2864)
);
AOI2BB2XLTS U3761 ( .B0(DmP_mant_SFG_SWR[1]), .B1(n2869), .A0N(n2869), .A1N(
DmP_mant_SFG_SWR[1]), .Y(n2865) );
AOI2BB2XLTS U3762 ( .B0(n2877), .B1(n2865), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n2904), .Y(n1159) );
OAI22X1TS U3763 ( .A0(n2952), .A1(n2867), .B0(n3272), .B1(n2866), .Y(n2868)
);
AO22XLTS U3764 ( .A0(n2872), .A1(n2868), .B0(n3071), .B1(DmP_mant_SFG_SWR[0]), .Y(n1157) );
AOI2BB2XLTS U3765 ( .B0(DmP_mant_SFG_SWR[0]), .B1(n2869), .A0N(n2881), .A1N(
DmP_mant_SFG_SWR[0]), .Y(n2870) );
AOI22X1TS U3766 ( .A0(n2932), .A1(n2870), .B0(n3114), .B1(n2910), .Y(n1156)
);
AOI2BB2X1TS U3767 ( .B0(n2887), .B1(DmP_mant_SFG_SWR[2]), .A0N(
DmP_mant_SFG_SWR[2]), .A1N(n2887), .Y(n2873) );
NAND2X1TS U3768 ( .A(n2873), .B(DMP_SFG[0]), .Y(n2878) );
OAI21XLTS U3769 ( .A0(n2873), .A1(DMP_SFG[0]), .B0(n2878), .Y(n2874) );
AOI22X1TS U3770 ( .A0(n2932), .A1(n2874), .B0(n3122), .B1(n2910), .Y(n1153)
);
XNOR2X1TS U3771 ( .A(DMP_SFG[1]), .B(n2878), .Y(n2875) );
XNOR2X1TS U3772 ( .A(n2875), .B(n2879), .Y(n2876) );
AOI2BB2XLTS U3773 ( .B0(n2904), .B1(n2876), .A0N(Raw_mant_NRM_SWR[3]), .A1N(
n2940), .Y(n1152) );
AOI2BB2X1TS U3774 ( .B0(DmP_mant_SFG_SWR[4]), .B1(n3102), .A0N(n2881), .A1N(
DmP_mant_SFG_SWR[4]), .Y(n2892) );
INVX2TS U3775 ( .A(n2878), .Y(n2880) );
AOI2BB2XLTS U3776 ( .B0(DMP_SFG[3]), .B1(n2886), .A0N(n2886), .A1N(
DMP_SFG[3]), .Y(n2882) );
XNOR2X1TS U3777 ( .A(n2883), .B(n2882), .Y(n2884) );
AOI2BB2XLTS U3778 ( .B0(n2904), .B1(n2884), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n2877), .Y(n1149) );
AOI2BB2X1TS U3779 ( .B0(DmP_mant_SFG_SWR[6]), .B1(n2887), .A0N(n2896), .A1N(
DmP_mant_SFG_SWR[6]), .Y(n2901) );
NAND2BXLTS U3780 ( .AN(n2892), .B(DMP_SFG[2]), .Y(n2885) );
AOI222X1TS U3781 ( .A0(n3290), .A1(n2886), .B0(n3290), .B1(n2885), .C0(n2886), .C1(n2885), .Y(n2900) );
XNOR2X1TS U3782 ( .A(DMP_SFG[5]), .B(n2895), .Y(n2888) );
XOR2X1TS U3783 ( .A(n2889), .B(n2888), .Y(n2890) );
AOI22X1TS U3784 ( .A0(n2932), .A1(n2890), .B0(n3115), .B1(n3302), .Y(n1146)
);
CMPR32X2TS U3785 ( .A(n3301), .B(n2892), .C(n2891), .CO(n2883), .S(n2893) );
AOI22X1TS U3786 ( .A0(n2932), .A1(n2893), .B0(n3109), .B1(n3302), .Y(n1144)
);
OAI2BB1X1TS U3787 ( .A0N(n2895), .A1N(DMP_SFG[5]), .B0(n2894), .Y(n2930) );
AOI2BB2X1TS U3788 ( .B0(n2887), .B1(DmP_mant_SFG_SWR[8]), .A0N(
DmP_mant_SFG_SWR[8]), .A1N(n2887), .Y(n2929) );
XNOR2X1TS U3789 ( .A(DMP_SFG[7]), .B(n2906), .Y(n2897) );
XOR2X1TS U3790 ( .A(n2898), .B(n2897), .Y(n2899) );
AOI22X1TS U3791 ( .A0(n2932), .A1(n2899), .B0(n3104), .B1(n2938), .Y(n1142)
);
AO22XLTS U3792 ( .A0(n2940), .A1(n2903), .B0(n3302), .B1(Raw_mant_NRM_SWR[6]), .Y(n1140) );
OAI211XLTS U3793 ( .A0(DMP_SFG[7]), .A1(n2906), .B0(DMP_SFG[6]), .C0(n2929),
.Y(n2905) );
OAI2BB1X1TS U3794 ( .A0N(n2906), .A1N(DMP_SFG[7]), .B0(n2905), .Y(n2924) );
AOI2BB2XLTS U3795 ( .B0(n2907), .B1(n3273), .A0N(n3273), .A1N(n2907), .Y(
n2908) );
XNOR2X1TS U3796 ( .A(n2909), .B(n2908), .Y(n2911) );
AOI22X1TS U3797 ( .A0(n2932), .A1(n2911), .B0(n3086), .B1(n2910), .Y(n1138)
);
AOI22X1TS U3798 ( .A0(Data_array_SWR[33]), .A1(n2957), .B0(
Data_array_SWR[30]), .B1(n2956), .Y(n2912) );
AOI22X1TS U3799 ( .A0(n1871), .A1(n3042), .B0(n1873), .B1(n3041), .Y(n2923)
);
AOI22X1TS U3800 ( .A0(Data_array_SWR[10]), .A1(n1858), .B0(n1878), .B1(n1828), .Y(n2922) );
AOI22X1TS U3801 ( .A0(Data_array_SWR[23]), .A1(n2954), .B0(n1865), .B1(n2914), .Y(n2917) );
AOI22X1TS U3802 ( .A0(Data_array_SWR[20]), .A1(n2915), .B0(
Data_array_SWR[16]), .B1(n2956), .Y(n2916) );
NAND2X1TS U3803 ( .A(n2917), .B(n2916), .Y(n2962) );
AOI22X1TS U3804 ( .A0(Data_array_SWR[39]), .A1(n2914), .B0(
Data_array_SWR[35]), .B1(n2954), .Y(n2920) );
AOI22X1TS U3805 ( .A0(Data_array_SWR[31]), .A1(n2957), .B0(
Data_array_SWR[28]), .B1(n2956), .Y(n2919) );
NAND2X2TS U3806 ( .A(n2920), .B(n2919), .Y(n2971) );
AOI22X1TS U3807 ( .A0(n3045), .A1(n2962), .B0(n2018), .B1(n2971), .Y(n2921)
);
NAND3XLTS U3808 ( .A(n2923), .B(n2922), .C(n2921), .Y(n2928) );
AOI22X1TS U3809 ( .A0(n1983), .A1(n2965), .B0(n3149), .B1(n2928), .Y(n2927)
);
AOI22X1TS U3810 ( .A0(n3078), .A1(n2927), .B0(n1897), .B1(n3071), .Y(n1136)
);
AO22XLTS U3811 ( .A0(n2938), .A1(Raw_mant_NRM_SWR[10]), .B0(n2932), .B1(
n2926), .Y(n1135) );
OAI2BB2XLTS U3812 ( .B0(n2927), .B1(n2976), .A0N(final_result_ieee[8]),
.A1N(n3027), .Y(n1134) );
AOI22X1TS U3813 ( .A0(left_right_SHT2), .A1(n2928), .B0(n1999), .B1(n2965),
.Y(n3081) );
OAI2BB2XLTS U3814 ( .B0(n3081), .B1(n2976), .A0N(final_result_ieee[42]),
.A1N(n3027), .Y(n1133) );
AO22XLTS U3815 ( .A0(n2938), .A1(Raw_mant_NRM_SWR[8]), .B0(n2932), .B1(n2931), .Y(n1131) );
OA22X1TS U3816 ( .A0(left_right_SHT2), .A1(n2934), .B0(n2933), .B1(n1982),
.Y(n2983) );
AOI22X1TS U3817 ( .A0(n2830), .A1(n2983), .B0(n1899), .B1(n3071), .Y(n1130)
);
XNOR2X1TS U3818 ( .A(n2937), .B(n2936), .Y(n2939) );
AOI22X1TS U3819 ( .A0(n2904), .A1(n2939), .B0(n3107), .B1(n2938), .Y(n1129)
);
AOI22X1TS U3820 ( .A0(Data_array_SWR[16]), .A1(n3042), .B0(n1878), .B1(n1858), .Y(n2943) );
NAND2X1TS U3821 ( .A(n2956), .B(n2018), .Y(n3030) );
OAI2BB2XLTS U3822 ( .B0(n3272), .B1(n3030), .A0N(Data_array_SWR[20]), .A1N(
n3041), .Y(n2941) );
AOI21X1TS U3823 ( .A0(Data_array_SWR[23]), .A1(n1828), .B0(n2941), .Y(n2942)
);
OAI211X1TS U3824 ( .A0(n2944), .A1(n1986), .B0(n2943), .C0(n2942), .Y(n2946)
);
INVX2TS U3825 ( .A(n2945), .Y(n2947) );
OAI2BB2XLTS U3826 ( .B0(n3062), .B1(n2976), .A0N(final_result_ieee[20]),
.A1N(n3027), .Y(n1128) );
OAI2BB2XLTS U3827 ( .B0(n3068), .B1(n2976), .A0N(final_result_ieee[30]),
.A1N(n3027), .Y(n1127) );
NOR2X2TS U3828 ( .A(shift_value_SHT2_EWR[5]), .B(n3037), .Y(n3049) );
AOI22X1TS U3829 ( .A0(Data_array_SWR[15]), .A1(n3041), .B0(
Data_array_SWR[12]), .B1(n3042), .Y(n2951) );
AOI22X1TS U3830 ( .A0(Data_array_SWR[18]), .A1(n1828), .B0(n1876), .B1(n1858), .Y(n2950) );
AOI22X1TS U3831 ( .A0(n3045), .A1(n2948), .B0(n2018), .B1(n2947), .Y(n2949)
);
NAND3XLTS U3832 ( .A(n2951), .B(n2950), .C(n2949), .Y(n2953) );
AOI22X1TS U3833 ( .A0(n3049), .A1(n1861), .B0(n3037), .B1(n2953), .Y(n3056)
);
OAI2BB2XLTS U3834 ( .B0(n3056), .B1(n2976), .A0N(final_result_ieee[14]),
.A1N(n3027), .Y(n1126) );
NOR2X2TS U3835 ( .A(shift_value_SHT2_EWR[5]), .B(n2952), .Y(n3050) );
AOI22X1TS U3836 ( .A0(left_right_SHT2), .A1(n2953), .B0(n3050), .B1(n1861),
.Y(n3075) );
OAI2BB2XLTS U3837 ( .B0(n3075), .B1(n2976), .A0N(final_result_ieee[36]),
.A1N(n3027), .Y(n1125) );
AOI22X1TS U3838 ( .A0(n1867), .A1(n2914), .B0(Data_array_SWR[24]), .B1(n2954), .Y(n2959) );
AOI22X1TS U3839 ( .A0(Data_array_SWR[22]), .A1(n2957), .B0(
Data_array_SWR[18]), .B1(n2918), .Y(n2958) );
NAND2X1TS U3840 ( .A(n2959), .B(n2958), .Y(n2970) );
AOI22X1TS U3841 ( .A0(n1983), .A1(n2970), .B0(n3036), .B1(n2965), .Y(n2961)
);
AOI22X1TS U3842 ( .A0(n1999), .A1(n2962), .B0(n3038), .B1(n2971), .Y(n2960)
);
NAND2X1TS U3843 ( .A(n2961), .B(n2960), .Y(n3063) );
AOI22X1TS U3844 ( .A0(n1999), .A1(n2970), .B0(n3036), .B1(n2971), .Y(n2964)
);
AOI22X1TS U3845 ( .A0(n1983), .A1(n2962), .B0(n3038), .B1(n2965), .Y(n2963)
);
NAND2X1TS U3846 ( .A(n2964), .B(n2963), .Y(n3064) );
AOI22X1TS U3847 ( .A0(n1869), .A1(n1858), .B0(Data_array_SWR[12]), .B1(n3041), .Y(n2967) );
AOI22X1TS U3848 ( .A0(n1876), .A1(n3042), .B0(n2018), .B1(n2965), .Y(n2966)
);
OAI211X1TS U3849 ( .A0(n3280), .A1(n2968), .B0(n2967), .C0(n2966), .Y(n2972)
);
AOI22X1TS U3850 ( .A0(n3078), .A1(n2969), .B0(n1900), .B1(n3085), .Y(n1122)
);
OAI2BB2XLTS U3851 ( .B0(n2969), .B1(n2976), .A0N(final_result_ieee[10]),
.A1N(n3027), .Y(n1121) );
OAI2BB2XLTS U3852 ( .B0(n3080), .B1(n2976), .A0N(final_result_ieee[40]),
.A1N(n3027), .Y(n1120) );
AOI22X1TS U3853 ( .A0(n1871), .A1(n1858), .B0(n1878), .B1(n3041), .Y(n2974)
);
AOI22X1TS U3854 ( .A0(Data_array_SWR[16]), .A1(n1828), .B0(n1873), .B1(n3042), .Y(n2973) );
OAI211X1TS U3855 ( .A0(n2975), .A1(n3018), .B0(n2974), .C0(n2973), .Y(n2981)
);
OAI2BB2XLTS U3856 ( .B0(n3054), .B1(n2976), .A0N(final_result_ieee[12]),
.A1N(n3027), .Y(n1119) );
OAI2BB2XLTS U3857 ( .B0(n3077), .B1(n2976), .A0N(final_result_ieee[38]),
.A1N(n3027), .Y(n1116) );
BUFX3TS U3858 ( .A(n2976), .Y(n3053) );
OAI2BB2XLTS U3859 ( .B0(n2983), .B1(n3053), .A0N(final_result_ieee[9]),
.A1N(n3027), .Y(n1114) );
AO22XLTS U3860 ( .A0(n3002), .A1(n2985), .B0(final_result_ieee[6]), .B1(
n3000), .Y(n1112) );
AO22XLTS U3861 ( .A0(n3002), .A1(n2986), .B0(final_result_ieee[44]), .B1(
n3000), .Y(n1111) );
AO22XLTS U3862 ( .A0(n3002), .A1(n2987), .B0(final_result_ieee[7]), .B1(
n3000), .Y(n1110) );
AO22XLTS U3863 ( .A0(n3002), .A1(n2988), .B0(final_result_ieee[23]), .B1(
n3000), .Y(n1109) );
AOI22X1TS U3864 ( .A0(n1999), .A1(n2995), .B0(n3036), .B1(n2996), .Y(n2991)
);
NAND2X1TS U3865 ( .A(n3038), .B(n2989), .Y(n2990) );
OAI211X1TS U3866 ( .A0(n2993), .A1(n1982), .B0(n2991), .C0(n2990), .Y(n3066)
);
AO22XLTS U3867 ( .A0(n3002), .A1(n3066), .B0(final_result_ieee[27]), .B1(
n3000), .Y(n1108) );
OAI2BB2XLTS U3868 ( .B0(n2994), .B1(n3053), .A0N(final_result_ieee[11]),
.A1N(n3027), .Y(n1107) );
OAI2BB2XLTS U3869 ( .B0(n3079), .B1(n3053), .A0N(final_result_ieee[39]),
.A1N(n3027), .Y(n1106) );
OAI22X1TS U3870 ( .A0(n2999), .A1(n3149), .B0(n2998), .B1(n1981), .Y(n3083)
);
AO22XLTS U3871 ( .A0(n3002), .A1(n3083), .B0(final_result_ieee[43]), .B1(
n3000), .Y(n1105) );
AO22XLTS U3872 ( .A0(n3002), .A1(n3001), .B0(final_result_ieee[4]), .B1(
n3000), .Y(n1104) );
AOI22X1TS U3873 ( .A0(Data_array_SWR[15]), .A1(n3042), .B0(
Data_array_SWR[12]), .B1(n1858), .Y(n3006) );
OAI2BB2XLTS U3874 ( .B0(n3247), .B1(n3030), .A0N(Data_array_SWR[18]), .A1N(
n3003), .Y(n3004) );
AOI21X1TS U3875 ( .A0(Data_array_SWR[22]), .A1(n1828), .B0(n3004), .Y(n3005)
);
OAI211X1TS U3876 ( .A0(n3007), .A1(n1986), .B0(n3006), .C0(n3005), .Y(n3009)
);
INVX2TS U3877 ( .A(n3008), .Y(n3010) );
OAI2BB2XLTS U3878 ( .B0(n3060), .B1(n3053), .A0N(final_result_ieee[18]),
.A1N(n3052), .Y(n1102) );
OAI2BB2XLTS U3879 ( .B0(n3070), .B1(n3053), .A0N(final_result_ieee[32]),
.A1N(n3052), .Y(n1101) );
AOI22X1TS U3880 ( .A0(Data_array_SWR[16]), .A1(n3041), .B0(n1878), .B1(n3042), .Y(n3014) );
AOI22X1TS U3881 ( .A0(Data_array_SWR[20]), .A1(n1828), .B0(n1873), .B1(n1858), .Y(n3013) );
AOI22X1TS U3882 ( .A0(n3045), .A1(n3011), .B0(n2018), .B1(n3010), .Y(n3012)
);
NAND3XLTS U3883 ( .A(n3014), .B(n3013), .C(n3012), .Y(n3015) );
AOI22X1TS U3884 ( .A0(n3049), .A1(n1862), .B0(n3037), .B1(n3015), .Y(n3058)
);
OAI2BB2XLTS U3885 ( .B0(n3058), .B1(n3053), .A0N(final_result_ieee[16]),
.A1N(n3052), .Y(n1100) );
AOI22X1TS U3886 ( .A0(left_right_SHT2), .A1(n3015), .B0(n3050), .B1(n1862),
.Y(n3073) );
OAI2BB2XLTS U3887 ( .B0(n3073), .B1(n3053), .A0N(final_result_ieee[34]),
.A1N(n3052), .Y(n1099) );
AOI22X1TS U3888 ( .A0(Data_array_SWR[14]), .A1(n3041), .B0(n1870), .B1(n1858), .Y(n3017) );
AOI22X1TS U3889 ( .A0(n1875), .A1(n3042), .B0(Data_array_SWR[17]), .B1(n1828), .Y(n3016) );
OAI211X1TS U3890 ( .A0(n3019), .A1(n3018), .B0(n3017), .C0(n3016), .Y(n3022)
);
OAI2BB2XLTS U3891 ( .B0(n3055), .B1(n3053), .A0N(final_result_ieee[13]),
.A1N(n3052), .Y(n1095) );
OAI2BB2XLTS U3892 ( .B0(n3076), .B1(n3053), .A0N(final_result_ieee[37]),
.A1N(n3052), .Y(n1094) );
AOI22X1TS U3893 ( .A0(Data_array_SWR[14]), .A1(n3042), .B0(n1875), .B1(n1858), .Y(n3025) );
OAI2BB2XLTS U3894 ( .B0(n3270), .B1(n3030), .A0N(Data_array_SWR[17]), .A1N(
n3041), .Y(n3023) );
AOI21X1TS U3895 ( .A0(Data_array_SWR[21]), .A1(n1828), .B0(n3023), .Y(n3024)
);
OAI211X1TS U3896 ( .A0(n3026), .A1(n1986), .B0(n3025), .C0(n3024), .Y(n3029)
);
AOI22X1TS U3897 ( .A0(n3049), .A1(n3028), .B0(n3037), .B1(n3029), .Y(n3059)
);
OAI2BB2XLTS U3898 ( .B0(n3059), .B1(n3053), .A0N(final_result_ieee[17]),
.A1N(n3027), .Y(n1092) );
AOI22X1TS U3899 ( .A0(left_right_SHT2), .A1(n3029), .B0(n3050), .B1(n3028),
.Y(n3072) );
OAI2BB2XLTS U3900 ( .B0(n3072), .B1(n3053), .A0N(final_result_ieee[33]),
.A1N(n3052), .Y(n1091) );
AOI22X1TS U3901 ( .A0(Data_array_SWR[13]), .A1(n1858), .B0(n1880), .B1(n3042), .Y(n3033) );
OAI2BB2XLTS U3902 ( .B0(n3271), .B1(n3030), .A0N(Data_array_SWR[19]), .A1N(
n3041), .Y(n3031) );
AOI21X1TS U3903 ( .A0(n1874), .A1(n1828), .B0(n3031), .Y(n3032) );
OAI211X1TS U3904 ( .A0(n3034), .A1(n1986), .B0(n3033), .C0(n3032), .Y(n3040)
);
INVX2TS U3905 ( .A(n3035), .Y(n3043) );
OAI2BB2XLTS U3906 ( .B0(n3061), .B1(n3053), .A0N(final_result_ieee[19]),
.A1N(n3052), .Y(n1087) );
OAI2BB2XLTS U3907 ( .B0(n3069), .B1(n2976), .A0N(final_result_ieee[31]),
.A1N(n3052), .Y(n1086) );
AOI22X1TS U3908 ( .A0(Data_array_SWR[13]), .A1(n3042), .B0(n1880), .B1(n3041), .Y(n3048) );
AOI22X1TS U3909 ( .A0(n1877), .A1(n1858), .B0(Data_array_SWR[19]), .B1(n1828), .Y(n3047) );
AOI22X1TS U3910 ( .A0(n3045), .A1(n3044), .B0(n2018), .B1(n3043), .Y(n3046)
);
NAND3XLTS U3911 ( .A(n3048), .B(n3047), .C(n3046), .Y(n3051) );
AOI22X1TS U3912 ( .A0(n3049), .A1(n1860), .B0(n3149), .B1(n3051), .Y(n3057)
);
OAI2BB2XLTS U3913 ( .B0(n3057), .B1(n2976), .A0N(final_result_ieee[15]),
.A1N(n3052), .Y(n1085) );
AOI22X1TS U3914 ( .A0(left_right_SHT2), .A1(n3051), .B0(n3050), .B1(n1860),
.Y(n3074) );
OAI2BB2XLTS U3915 ( .B0(n3074), .B1(n3053), .A0N(final_result_ieee[35]),
.A1N(n3052), .Y(n1084) );
AOI22X1TS U3916 ( .A0(n2830), .A1(n3054), .B0(n1901), .B1(n2817), .Y(n1077)
);
AOI22X1TS U3917 ( .A0(n2830), .A1(n3055), .B0(n1902), .B1(n3085), .Y(n1076)
);
AOI22X1TS U3918 ( .A0(n3078), .A1(n3056), .B0(n1903), .B1(n3071), .Y(n1075)
);
AOI22X1TS U3919 ( .A0(n2830), .A1(n3057), .B0(n1904), .B1(n3071), .Y(n1074)
);
AOI22X1TS U3920 ( .A0(n3078), .A1(n3058), .B0(n1842), .B1(n3071), .Y(n1073)
);
AOI22X1TS U3921 ( .A0(n3078), .A1(n3059), .B0(n1881), .B1(n3085), .Y(n1072)
);
AOI22X1TS U3922 ( .A0(n2830), .A1(n3060), .B0(n1882), .B1(n3071), .Y(n1071)
);
AOI22X1TS U3923 ( .A0(n2830), .A1(n3061), .B0(n1883), .B1(n3085), .Y(n1070)
);
AOI22X1TS U3924 ( .A0(n3078), .A1(n3062), .B0(n1884), .B1(n3071), .Y(n1069)
);
AO22XLTS U3925 ( .A0(n3065), .A1(DmP_mant_SFG_SWR[26]), .B0(n3084), .B1(
n3063), .Y(n1065) );
AO22XLTS U3926 ( .A0(n3065), .A1(DmP_mant_SFG_SWR[28]), .B0(n3082), .B1(
n3064), .Y(n1063) );
AO22XLTS U3927 ( .A0(n3085), .A1(DmP_mant_SFG_SWR[29]), .B0(n2830), .B1(
n3066), .Y(n1062) );
AO22XLTS U3928 ( .A0(n3085), .A1(DmP_mant_SFG_SWR[31]), .B0(n3084), .B1(
n3067), .Y(n1060) );
AOI22X1TS U3929 ( .A0(n2830), .A1(n3068), .B0(n1885), .B1(n2817), .Y(n1059)
);
AOI22X1TS U3930 ( .A0(n3078), .A1(n3069), .B0(n1886), .B1(n3071), .Y(n1058)
);
AOI22X1TS U3931 ( .A0(n3078), .A1(n3070), .B0(n1887), .B1(n3071), .Y(n1057)
);
AOI22X1TS U3932 ( .A0(n2830), .A1(n3072), .B0(n1888), .B1(n3071), .Y(n1056)
);
AOI22X1TS U3933 ( .A0(n2830), .A1(n3073), .B0(n1889), .B1(n2817), .Y(n1055)
);
AOI22X1TS U3934 ( .A0(n3078), .A1(n3074), .B0(n1890), .B1(n2817), .Y(n1054)
);
AOI22X1TS U3935 ( .A0(n3078), .A1(n3075), .B0(n1891), .B1(n2817), .Y(n1053)
);
AOI22X1TS U3936 ( .A0(n3078), .A1(n3076), .B0(n1892), .B1(n2817), .Y(n1052)
);
AOI22X1TS U3937 ( .A0(n2830), .A1(n3077), .B0(n1893), .B1(n2817), .Y(n1051)
);
AOI22X1TS U3938 ( .A0(n2830), .A1(n3079), .B0(n1895), .B1(n2817), .Y(n1050)
);
AOI22X1TS U3939 ( .A0(n2830), .A1(n3080), .B0(n1896), .B1(n2817), .Y(n1049)
);
AOI22X1TS U3940 ( .A0(n3078), .A1(n3081), .B0(n1898), .B1(n2817), .Y(n1047)
);
AO22XLTS U3941 ( .A0(n3085), .A1(DmP_mant_SFG_SWR[45]), .B0(n3082), .B1(
n3083), .Y(n1046) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_ETAIIN16Q4_syn.sdf");
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_timer.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_timer -- Simple timer.
// _____________________________________________________________________________
//
`include "sys.h"
module jbi_timer (/*AUTOARG*/
// Outputs
busy, error,
// Inputs
start, stopnclear, tick, clk, rst_l
);
`include "jbi_mout.h"
input start; //
input stopnclear; //
output busy; //
output error; //
input tick; // Count timer by 1.
input clk; // Clock.
input rst_l; // Reset.
// Wires and Regs.
wire [1:0] state;
reg busy, error;
reg [1:0] next_state;
// States.
parameter UNUSED = 2'b00;
parameter COUNT_0 = 2'b01;
parameter COUNT_1 = 2'b10;
parameter OVERFLOW = 2'b11;
parameter STATE_x = 2'bxx;
// Machine State (initialize to IDLE).
dffrl_ns #(2) state_reg (.din(next_state), .q(state), .rst_l(rst_l), .clk(clk));
always @(/*AS*/start or state or stopnclear or tick) begin
`define out { next_state, error, busy }
casex ({ state, start, stopnclear, tick })
//
// stop ][
// Current n ][ Next
// State start clear tick ][ State error busy
// -----------------------------------++----------------------------------
// Counter not being used.
{ UNUSED, N, x, x }: `out = { UNUSED, N, N };
{ UNUSED, Y, x, x }: `out = { COUNT_0, N, N };
// Counter started. No counts yet.
{ COUNT_0, x, N, N }: `out = { COUNT_0, N, Y };
{ COUNT_0, x, Y, x }: `out = { UNUSED, N, Y };
{ COUNT_0, x, N, Y }: `out = { COUNT_1, N, Y };
// Counter started. Have seen one "tick".
{ COUNT_1, x, N, N }: `out = { COUNT_1, N, Y };
{ COUNT_1, x, Y, x }: `out = { UNUSED, N, Y };
{ COUNT_1, x, N, Y }: `out = { OVERFLOW, N, Y };
// Saw two "tick"s and have reported the overflow.
{ OVERFLOW, x, N, x }: `out = { OVERFLOW, Y, Y };
{ OVERFLOW, x, Y, x }: `out = { UNUSED, Y, Y };
default: `out = { STATE_x, x, x };
endcase
`undef out
end
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: 'Start' never asserted when in OVERFLOW state.
always @(posedge clk) begin
if (!(~rst_l) && state == OVERFLOW && start) begin
$dispmon ("jbi_mout_jbi_timer", 49, "%d %m: ERROR - JID reused before being released!", $time, state);
end
end
// Check: State machine has valid state.
always @(posedge clk) begin
if (!(~rst_l) && next_state === STATE_x) begin
$dispmon ("jbi_mout_jbi_timer", 49, "%d %m: ERROR - No state asserted! (state=%b)", $time, state);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_ncrd_timeout")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_2_V
`define SKY130_FD_SC_HDLL__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/01/06 11:13:56 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : Virtex-6
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
parameter REFCLK_FREQ = 200;
// # = 200 when design frequency < 533 MHz,
// = 300 when design frequency >= 533 MHz.
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
parameter IODELAY_GRP = "IODELAY_MIG";
//to phy_top
parameter nCK_PER_CLK = 2;
// # of memory CKs per fabric clock.
// # = 2, 1.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per Rank for
// phy.
parameter DQS_CNT_WIDTH = 3;
// # = ceil(log2(DQS_WIDTH)).
parameter RANK_WIDTH = 1;
// # = ceil(log2(RANKS)).
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter DM_WIDTH = 8;
// # of Data Mask bits.
parameter DQ_WIDTH = 64;
// # of Data (DQ) bits.
parameter DQS_WIDTH = 8;
// # of DQS/DQS# bits.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter BURST_MODE = "8";
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
parameter INPUT_CLK_TYPE = "DIFFERENTIAL";
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter BM_CNT_WIDTH = 2;
// # = ceil(log2(nBANK_MACHS)).
parameter ADDR_CMD_MODE = "1T" ;
// # = "2T", "1T".
parameter ORDERING = "STRICT";
// # = "NORM", "STRICT", "RELAXED".
parameter RTT_NOM = "60";
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF";
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter OUTPUT_DRV = "HIGH";
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CLKFBOUT_MULT_F = 6;
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 2;
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 3;
// VCO output divisor for fast (memory) clocks.
parameter tCK = 2500;
// memory tCK paramter.
// # = Clock Period.
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter tPRDI = 1_000_000;
// memory tPRDI paramter.
parameter tREFI = 7800000;
// memory tREFI paramter.
parameter tZQI = 128_000_000;
// memory tZQI paramter.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter STARVE_LIMIT = 2;
// # = 2,3,4.
parameter TCQ = 100;
parameter ECC_TEST = "OFF";
//***********************************************************************//
// Traffic Gen related parameters
//***********************************************************************//
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_RPBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter PRBS_SADDR_MASK_POS = 32'h00000000;
parameter END_ADDRESS = 32'h000003ff;
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00;
parameter SEL_VICTIM_LINE = 11;
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam real CLK_PERIOD = tCK;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam DRAM_DEVICE = "SODIMM";
// DRAM_TYPE: "UDIMM", "RDIMM", "COMPS"
// VT delay change options/settings
localparam VT_ENABLE = "OFF";
// Enable VT delay var's
localparam VT_RATE = CLK_PERIOD/500;
// Size of each VT step
localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50;
// Update interval
localparam VT_MAX = CLK_PERIOD/40;
// Maximum VT shift
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_clk;
reg clk_ref;
reg sys_rst_n;
wire sys_clk_p;
wire sys_clk_n;
wire clk_ref_p;
wire clk_ref_n;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
wire sys_rst;
wire error;
wire phy_init_done;
wire ddr3_parity;
wire ddr3_reset_n;
wire sda;
wire scl;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [BANK_WIDTH-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga;
wire [CKE_WIDTH-1:0] ddr3_cke_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram;
reg [BANK_WIDTH-1:0] ddr3_ba_sdram;
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram;
reg [CKE_WIDTH-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_r;
reg [BANK_WIDTH-1:0] ddr3_ba_r;
reg ddr3_ras_n_r;
reg ddr3_cas_n_r;
reg ddr3_we_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_r;
reg [CKE_WIDTH-1:0] ddr3_cke_r;
//**************************************************************************//
// Clock generation and reset
//**************************************************************************//
initial begin
sys_clk = 1'b0;
clk_ref = 1'b1;
sys_rst_n = 1'b0;
#120000
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
// Generate system clock = twice rate of CLK
always
sys_clk = #(CLK_PERIOD/2.0) ~sys_clk;
// Generate IDELAYCTRL reference clock (200MHz)
always
clk_ref = #REFCLK_PERIOD ~clk_ref;
assign sys_clk_p = sys_clk;
assign sys_clk_n = ~sys_clk;
assign clk_ref_p = clk_ref;
assign clk_ref_n = ~clk_ref;
//**************************************************************************//
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
end
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD)
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n)
);
end
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n)
);
end
endgenerate
assign sda = 1'b1;
assign scl = 1'b1;
example_top #
(
.nCK_PER_CLK (nCK_PER_CLK),
.tCK (tCK),
.RST_ACT_LOW (RST_ACT_LOW),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.CS_WIDTH (CS_WIDTH),
.BURST_MODE (BURST_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.DEBUG_PORT (DEBUG_PORT),
.tPRDI (tPRDI),
.tREFI (tREFI),
.tZQI (tZQI),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.ORDERING (ORDERING),
.STARVE_LIMIT (STARVE_LIMIT),
.ADDR_WIDTH (ADDR_WIDTH),
.ECC_TEST (ECC_TEST),
.TCQ (TCQ),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE)
)
u_ip_top
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.sys_rst (sys_rst),
.ddr3_ck_p (ddr3_ck_p_fpga),
.ddr3_ck_n (ddr3_ck_n_fpga),
.ddr3_addr (ddr3_addr_fpga),
.ddr3_ba (ddr3_ba_fpga),
.ddr3_ras_n (ddr3_ras_n_fpga),
.ddr3_cas_n (ddr3_cas_n_fpga),
.ddr3_we_n (ddr3_we_n_fpga),
.ddr3_cs_n (ddr3_cs_n_fpga),
.ddr3_cke (ddr3_cke_fpga),
.ddr3_odt (ddr3_odt_fpga),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_dm (ddr3_dm_fpga),
.ddr3_dq (ddr3_dq_fpga),
.ddr3_dqs_p (ddr3_dqs_p_fpga),
.ddr3_dqs_n (ddr3_dqs_n_fpga),
.error (error),
.sda (sda),
.scl (scl),
.phy_init_done (phy_init_done)
);
// Extra one clock pipelining for RDIMM address and
// control signals is implemented here (Implemented external to memory model)
always @( posedge ddr3_ck_p_sdram[0] ) begin
if ( ddr3_reset_n == 1'b0 ) begin
ddr3_ras_n_r <= 1'b1;
ddr3_cas_n_r <= 1'b1;
ddr3_we_n_r <= 1'b1;
ddr3_cs_n_r <= {(CS_WIDTH*nCS_PER_RANK){1'b1}};
ddr3_odt_r <= 1'b0;
end
else begin
ddr3_addr_r <= #(CLK_PERIOD/2) ddr3_addr_sdram;
ddr3_ba_r <= #(CLK_PERIOD/2) ddr3_ba_sdram;
ddr3_ras_n_r <= #(CLK_PERIOD/2) ddr3_ras_n_sdram;
ddr3_cas_n_r <= #(CLK_PERIOD/2) ddr3_cas_n_sdram;
ddr3_we_n_r <= #(CLK_PERIOD/2) ddr3_we_n_sdram;
ddr3_cs_n_r <= #(CLK_PERIOD/2) ddr3_cs_n_sdram;
ddr3_odt_r <= #(CLK_PERIOD/2) ddr3_odt_sdram;
end
end
// to avoid tIS violations on CKE when reset is deasserted
always @( posedge ddr3_ck_n_sdram[0] )
if ( ddr3_reset_n == 1'b0 )
ddr3_cke_r <= 1'b0;
else
ddr3_cke_r <= #(CLK_PERIOD) ddr3_cke_sdram;
//***************************************************************************
// Instantiate memories
//***************************************************************************
genvar r,i,dqs_x;
generate
if(DRAM_DEVICE == "COMP") begin : comp_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
end
end
else if(DRAM_DEVICE == "RDIMM") begin: rdimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_r),
.cas_n (ddr3_cas_n_r),
.we_n (ddr3_we_n_r),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_r),
.addr (ddr3_addr_r),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "UDIMM") begin: udimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "SODIMM") begin: sodimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (phy_init_done);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#1000000000;
if (!phy_init_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output wire [ 7:0 ] z
);
assign z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output reg [ 7:0 ] z
);
wire [7:0] zi;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:30:16 01/05/2017
// Design Name:
// Module Name: Final
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Final(
input rst,
input clk,
input PSCLK,
input PSDATA,
output R,
output G,
output B,
output hsync,
output vsync
);
//////////////////////////////////////////////////////////////////////////////////
// Parameter
//////////////////////////////////////////////////////////////////////////////////
//parameter PERIOD = 3000000;
parameter leftX = 104;
parameter rightX = 904;
parameter centerX = 504;
parameter topY = 20;
parameter downY = 632;
parameter wallW = 20;
parameter hp = 80;
parameter radius = 20;
parameter bInitX = 700;
parameter bInitY = 400;
parameter bStepX = 10;
parameter bStepY = 10;
//parameter StepXinit = 10;
//parameter StepYinit = 10;
//parameter MaxSpeedX = 50;
//parameter MaxSpeedY = 50;
//parameter barAx = 140;
//parameter barBx = 850;
//parameter barL = 100;
parameter barW = 20;
parameter MAX = 10000;
parameter poX = 300;
parameter poY = 200;
// bar
parameter initAX = 140;
parameter initBX = 850;
parameter initY = 300;
parameter uStepX = 20;
parameter uStepY = 20;
parameter leftAX = 140;
parameter rightBX = 850;
//////////////////////////////////////////////////////////////////////////////////
// Wire or Reg
//////////////////////////////////////////////////////////////////////////////////
reg [20:0] x, y;
wire [10:0] vis;
reg nState, cState;
reg [21:0] kReg;
reg [7:0] kData;
reg [3:0] kCounter;
wire check;
reg [30:0] counter;
//reg [4:0] time2;
reg timer;
reg isStop;
// keyboard
reg sig_f0;
reg up, down, right, left, w, s, a, d, sp;
reg [20:0] barAx, barBx;
// speed
//reg [20:0] bStepX, bStepY;
reg [30:0] PERIOD;
//reg [30:0] ppp;
// color
wire black, white;
reg mod1, mod2, mod3;
// object
reg barA, barB;
reg ball;
reg topWall, downWall, leftWall, rightWall;
wire wall;
reg [6:0] barL;
reg cLine;
// Center
reg [10:0] bCenterX, bCenterY;
wire [10:0] pCenterX, pCenterY;
reg bXd, bYd;
// keyboard
reg [30:0] barAy, barBy;
// final
reg aW, bW;
reg Awins, Bwins;
wire [400:0] B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35, B36, B37, B38, B39, B40, B41, B42, B43, B44, B45, B46, B47, B48, B49, B50, B51, B52, B53, B54, B55, B56, B57, B58, B59, B60, B61, B62, B63, B64;
wire [400:0] A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35, A36, A37, A38, A39, A40, A41, A42, A43, A44, A45, A46, A47, A48, A49, A50, A51, A52, A53, A54, A55, A56, A57, A58, A59, A60, A61, A62, A63, A64, A65, A66, A67;
//////////////////////////////////////////////////////////////////////////////////
// C C
//////////////////////////////////////////////////////////////////////////////////
assign hsync = ~( (x >= 919) && (x < 1039) );
assign vsync = ~( (y >= 659) && (y < 665) );
assign vis = ( (x >= 104) && (x < 904) && (y >= 23) && (y < 632) );
assign R = (aW|bW)? (bW? Awins&counter[23:22]:Bwins&counter[23:22]):(white & (~black|(ball&mod1)|(wall&mod1)));
assign G = (aW|bW)? (bW? Awins&counter[23:22]:Bwins&counter[23:22]):(white & (~black|(ball&mod2)|(wall&mod2)));
assign B = (aW|bW)? (bW? Awins&~counter[23:22]:Bwins&~counter[23:22]):(white & (~black|(ball&mod3)|(wall&mod3)));
assign wall = topWall | downWall | leftWall | rightWall;
assign black = barA | barB | ball | wall | cLine;
assign white = vis;
assign check = kReg[1]^kReg[2]^kReg[3]^kReg[4]^kReg[5]^kReg[6]^kReg[7]^kReg[8]^kReg[9];
//assign PERIOD = 5000000;
//////////////////////////////////////////////////////////////////////////////////
// Design
//////////////////////////////////////////////////////////////////////////////////
// FSM
always@(posedge clk, posedge rst)
begin
if(rst) cState <= 0;
else begin
cState <= nState;
nState <= PSCLK;
end
end
//x
always@(posedge clk, posedge rst)
begin
if(rst) x <= 0;
else begin
x <= (x < 1039)? x+1 : 0;
end
end
// y
always@(posedge clk, posedge rst)
begin
if(rst) y <= 0;
else begin
y <= (y == 665)? 0 : (x == 1039) ? y+1 : y;
end
end
// isStop
always@(posedge clk, posedge rst)
begin
if(rst) isStop <= 0;
else begin
if(sp) isStop <= ~isStop;
else isStop <= isStop;
end
end
// counter
always@(posedge clk, posedge rst)
begin
if(rst) counter <= 0;
else begin
if(isStop) counter <= counter;
else if(counter == PERIOD) counter <= 0;
else counter <= counter + 1;
end
end
/*
// ppp
always@(posedge clk, posedge rst)
begin
if(rst) ppp <= 500000;
else if(counter == 10) ppp <= ppp - 1;
else ppp <= ppp;
end
*/
// PERIOD
always@(posedge clk, posedge rst)
begin
if(rst) PERIOD <= 5000000;
else begin
if(counter == 5) PERIOD <= (PERIOD > 2000000)? PERIOD-20 : PERIOD;
else PERIOD <= PERIOD;
end
end
// timer
always@(posedge clk, posedge rst)
begin
if(rst) timer <= 0;
else begin
if(timer) timer <= 0;
else if(counter == PERIOD) timer <= 1;
else timer <= timer;
end
end
/*
// time2
always@(posedge clk, posedge rst)
begin
if(rst) time2 <= 0;
else begin
if(time2==16) time2 <= 0;
else if(timer) time2 <= time2+1;
else time2 <= time2;
end
end
*/
// kCounter
always@(posedge clk, posedge rst)
begin
if(rst) kCounter <= 0;
else begin
if({cState,nState} == 2'b10) begin
if(kCounter == 10) kCounter <= 0;
else kCounter <= kCounter + 1;
end else kCounter <= kCounter;
end
end
// kReg
always@(posedge clk, posedge rst)
begin
if(rst) kReg <= 0;
else begin
case({cState,nState})
2'b10: kReg <= {PSDATA, kReg[21:1]};
default: kReg <= kReg;
endcase
end
end
// kData
always@(posedge clk, posedge rst)
begin
if(rst) kData <= 0;
else begin
if(kCounter == 4'd0 && check == 1'b1) begin
if(kReg[11:1] == 11'hXX) kData <= 8'd0;
else kData <= kReg[19:12];
end
else kData <= kData;
end
end
// keyboard
always@(posedge clk, posedge rst)
begin
if(rst) sig_f0<=0;
else begin
if(kData==8'hf0)sig_f0<=1;
else if(sig_f0) begin
case(kData)
8'h75: up <= 1; // up
8'h72: down <= 1; // down
8'h6B: left <= 1; // left
8'h74: right <= 1; // right
8'h1d: w <= 1; // w
8'h1b: s <= 1; // s
8'h1c: a <= 1; // a
8'h23: d <= 1; // d
8'h29: sp <= 1; // space
endcase
sig_f0<=0;
end
else begin
sig_f0<=0;
up<=0;
down<=0;
right<=0;
left<=0;
w<=0;
s<=0;
a<=0;
d<=0;
sp<=0;
end
end
end
/*
// bStepX
always@(posedge clk, posedge rst)
begin
if(rst) bStepX <= StepXinit;
else begin
if(time2==16) bStepX <= (bStepX+1 < MaxSpeedX)? bStepX+1:bStepX;
else bStepX <= bStepX;
end
end
// bStepY
always@(posedge clk, posedge rst)
begin
if(rst) bStepY <= StepYinit;
else begin
if(time2==16) bStepY <= (bStepY+1 < MaxSpeedY)? bStepY+1:bStepY;
else bStepY <= bStepY;
end
end
*/
// cLine
always@(posedge clk, posedge rst)
begin
if(rst) cLine <= 0;
else begin
if(y > topY && y < downY && x < centerX+1 && x > centerX-1) cLine <= 1;
else cLine <= 0;
end
end
// topWall
always@(posedge clk, posedge rst)
begin
if(rst) topWall <= 0;
else begin
if(y > topY && y < topY+wallW && x > leftX && x < rightX) topWall <= 1;
else topWall <= 0;
end
end
// downWall
always@(posedge clk, posedge rst)
begin
if(rst) downWall <= 0;
else begin
if(y > downY-wallW && y < downY && x > leftX && x < rightX) downWall <= 1;
else downWall <= 0;
end
end
// leftWall
always@(posedge clk, posedge rst)
begin
if(rst) leftWall <= 0;
else begin
if((y > downY-hp || y < topY+hp) && (x > leftX && x < leftX+wallW)) leftWall <= 1;
else leftWall <= 0;
end
end
// rightWall
always@(posedge clk, posedge rst)
begin
if(rst) rightWall <= 0;
else begin
if((y > downY-hp || y < topY+hp) && (x > rightX-wallW && x < rightX)) rightWall <= 1;
else rightWall <= 0;
end
end
// mod1,mod2,mod3
always@(posedge clk, posedge rst)
begin
if(rst) begin mod1 <= 1; mod2 <= 0; mod3 <= 0; end
else begin
if(pCenterX > rightX-radius || pCenterX < leftX+wallW+radius ||
(pCenterY < barAy+barL+10 && pCenterY > barAy-10 && pCenterX < barAx+wallW+radius) ||
(pCenterY < barBy+barL+10 && pCenterY > barBy-10 && pCenterX > barBx-radius) ||
(pCenterY < topY+wallW+radius || pCenterY > downY-wallW-radius) ) begin
if(mod1) begin mod1 <= 0; mod2 <= 1; mod3 <=0; end
else if(mod2) begin mod1 <= 0; mod2 <= 0; mod3 <= 1; end
else begin mod1 <= 1; mod2 <= 0; mod3 <= 0; end
end else begin mod1 <= mod1; mod2 <= mod2; mod3 <= mod3; end
end
end
// ball
always@(posedge clk, posedge rst)
begin
if(rst) ball <= 0;
else begin
if((x-bCenterX)*(x-bCenterX) + (y-bCenterY)*(y-bCenterY) <= radius*radius) ball <= 1;
else ball <= 0;
end
end
// bXd
always@(posedge clk, posedge rst)
begin
if(rst) bXd <= 0;
else begin
if((pCenterY < topY+hp && pCenterY > topY && pCenterX > rightX-wallW-radius) ||
(pCenterY < topY+hp && pCenterY > topY && pCenterX < leftX+wallW+radius) ||
(pCenterY > downY-hp && pCenterY < downY && pCenterX > rightX-wallW-radius) ||
(pCenterY > downY-hp && pCenterY < downY && pCenterX < leftX+wallW+radius) ||
(pCenterY < barAy+barL+10 && pCenterY > barAy-10 && pCenterX < barAx+wallW+radius) ||
(pCenterY < barBy+barL+10 && pCenterY > barBy-10 && pCenterX > barBx-radius)) bXd <= ~bXd;
else bXd <= bXd;
end
end
// bYd
always@(posedge clk, posedge rst)
begin
if(rst) bYd <= 0;
else begin
if(pCenterY < topY+wallW+radius || pCenterY > downY-wallW-radius) bYd <= ~bYd;
else bYd <= bYd;
end
end
// bCenterX
always@(posedge clk, posedge rst)
begin
if(rst) bCenterX <= bInitX;
else begin
if(timer)
if(bXd) bCenterX <= bCenterX + bStepX;
else bCenterX <= bCenterX - bStepX;
else bCenterX <= bCenterX;
end
end
// bCenterY
always@(posedge clk, posedge rst)
begin
if(rst) bCenterY <= bInitY;
else begin
if(timer)
if(bYd) bCenterY <= bCenterY + bStepY;
else bCenterY <= bCenterY - bStepY;
else bCenterY <= bCenterY;
end
end
// pCenterX
assign pCenterX=(bXd)?(bCenterX + bStepX):(bCenterX - bStepX);
// pCenterY
assign pCenterY=(bYd)?(bCenterY + bStepY):(bCenterY - bStepY);
// barA
always@(posedge clk, posedge rst)
begin
if(rst) barA <= 0;
else begin
if((x < barAx+barW && x > barAx) && (y < barAy+barL && y > barAy)) barA <= 1;
else barA <= 0;
end
end
// barB
always@(posedge clk, posedge rst)
begin
if(rst) barB <= 0;
else begin
if((x < barBx+barW && x > barBx) && (y < barBy+barL && y > barBy)) barB <= 1;
else barB <= 0;
end
end
// barAx
always@(posedge clk, posedge rst)
begin
if(rst) barAx <= initAX;
else begin
if(isStop) barAx <= barAx;
else if(a) barAx <= (barAx-uStepX >= leftAX)? barAx-uStepX : barAx;
else if(d) barAx <= (barAx+wallW+uStepX <= centerX)? barAx+uStepX : barAx;
else barAx <= barAx;
end
end
// barAy
always@(posedge clk, posedge rst)
begin
if(rst) barAy <= initY;
else begin
if(isStop) barAy <= barAy;
else if(w) barAy <= (barAy-uStepY > topY)? barAy-uStepY : barAy;
else if(s) barAy <= (barAy+barL+uStepY < downY)? barAy+uStepY : barAy;
else barAy <= barAy;
end
end
// barBx
always@(posedge clk, posedge rst)
begin
if(rst) barBx <= initBX;
else begin
if(isStop) barBx <= barBx;
else if(left) barBx <= (barBx-uStepX >= centerX)? barBx-uStepX : barBx;
else if(right) barBx <= (barBx+uStepX <= rightBX)? barBx+uStepX : barBx;
else barBx <= barBx;
end
end
// barBy
always@(posedge clk, posedge rst)
begin
if(rst) barBy <= initY;
else begin
if(isStop) barBy <= barBy;
else if(up) barBy <= (barBy-uStepY > topY)? barBy-uStepY : barBy;
else if(down) barBy <= (barBy+barL+uStepY < downY)? barBy+uStepY : barBy;
else barBy <= barBy;
end
end
// barL
always@(posedge clk, posedge rst)
begin
if(rst) barL <= 120;
else begin
if((pCenterY < barAy+barL+10 && pCenterY > barAy-10 && pCenterX < barAx+wallW+radius) ||
(pCenterY < barBy+barL+10 && pCenterY > barBy-10 && pCenterX > barBx-radius)) barL <= (barL > 40)? barL-5:barL;
else barL <= barL;
end
end
// over
always@(posedge clk, posedge rst)
begin
if(rst) begin aW <= 0; bW <= 0; end
else begin
if(aW == 0 && bW == 0) begin
if(bCenterX < leftX+wallW+radius) aW <= 1;
else if(bCenterX > rightX-radius) bW <= 1;
else begin aW <= aW; bW <= bW; end
end else begin aW <= aW; bW <= bW; end
end
end
// Awins
always@(posedge clk, posedge rst)
begin
if(rst) Awins <= 0;
else begin
case(y-poY)
0: Awins <= A0[400+poX-x];
1: Awins <= A1[400+poX-x];
2: Awins <= A2[400+poX-x];
3: Awins <= A3[400+poX-x];
4: Awins <= A4[400+poX-x];
5: Awins <= A5[400+poX-x];
6: Awins <= A6[400+poX-x];
7: Awins <= A7[400+poX-x];
8: Awins <= A8[400+poX-x];
9: Awins <= A9[400+poX-x];
10: Awins <= A10[400+poX-x];
11: Awins <= A11[400+poX-x];
12: Awins <= A12[400+poX-x];
13: Awins <= A13[400+poX-x];
14: Awins <= A14[400+poX-x];
15: Awins <= A15[400+poX-x];
16: Awins <= A16[400+poX-x];
17: Awins <= A17[400+poX-x];
18: Awins <= A18[400+poX-x];
19: Awins <= A19[400+poX-x];
20: Awins <= A20[400+poX-x];
21: Awins <= A21[400+poX-x];
22: Awins <= A22[400+poX-x];
23: Awins <= A23[400+poX-x];
24: Awins <= A24[400+poX-x];
25: Awins <= A25[400+poX-x];
26: Awins <= A26[400+poX-x];
27: Awins <= A27[400+poX-x];
28: Awins <= A28[400+poX-x];
29: Awins <= A29[400+poX-x];
30: Awins <= A30[400+poX-x];
31: Awins <= A31[400+poX-x];
32: Awins <= A32[400+poX-x];
33: Awins <= A33[400+poX-x];
34: Awins <= A34[400+poX-x];
35: Awins <= A35[400+poX-x];
36: Awins <= A36[400+poX-x];
37: Awins <= A37[400+poX-x];
38: Awins <= A38[400+poX-x];
39: Awins <= A39[400+poX-x];
40: Awins <= A40[400+poX-x];
41: Awins <= A41[400+poX-x];
42: Awins <= A42[400+poX-x];
43: Awins <= A43[400+poX-x];
44: Awins <= A44[400+poX-x];
45: Awins <= A45[400+poX-x];
46: Awins <= A46[400+poX-x];
47: Awins <= A47[400+poX-x];
48: Awins <= A48[400+poX-x];
49: Awins <= A49[400+poX-x];
50: Awins <= A50[400+poX-x];
51: Awins <= A51[400+poX-x];
52: Awins <= A52[400+poX-x];
53: Awins <= A53[400+poX-x];
54: Awins <= A54[400+poX-x];
55: Awins <= A55[400+poX-x];
56: Awins <= A56[400+poX-x];
57: Awins <= A57[400+poX-x];
58: Awins <= A58[400+poX-x];
59: Awins <= A59[400+poX-x];
60: Awins <= A60[400+poX-x];
61: Awins <= A61[400+poX-x];
62: Awins <= A62[400+poX-x];
63: Awins <= A63[400+poX-x];
64: Awins <= A64[400+poX-x];
65: Awins <= A65[400+poX-x];
66: Awins <= A66[400+poX-x];
67: Awins <= A67[400+poX-x];
default: Awins <= 0;
endcase
end
end
// Bwins
always@(posedge clk, posedge rst)
begin
if(rst) Bwins <= 0;
else begin
case(y-poY)
0: Bwins <= B0[400+poX-x];
1: Bwins <= B1[400+poX-x];
2: Bwins <= B2[400+poX-x];
3: Bwins <= B3[400+poX-x];
4: Bwins <= B4[400+poX-x];
5: Bwins <= B5[400+poX-x];
6: Bwins <= B6[400+poX-x];
7: Bwins <= B7[400+poX-x];
8: Bwins <= B8[400+poX-x];
9: Bwins <= B9[400+poX-x];
10: Bwins <= B10[400+poX-x];
11: Bwins <= B11[400+poX-x];
12: Bwins <= B12[400+poX-x];
13: Bwins <= B13[400+poX-x];
14: Bwins <= B14[400+poX-x];
15: Bwins <= B15[400+poX-x];
16: Bwins <= B16[400+poX-x];
17: Bwins <= B17[400+poX-x];
18: Bwins <= B18[400+poX-x];
19: Bwins <= B19[400+poX-x];
20: Bwins <= B20[400+poX-x];
21: Bwins <= B21[400+poX-x];
22: Bwins <= B22[400+poX-x];
23: Bwins <= B23[400+poX-x];
24: Bwins <= B24[400+poX-x];
25: Bwins <= B25[400+poX-x];
26: Bwins <= B26[400+poX-x];
27: Bwins <= B27[400+poX-x];
28: Bwins <= B28[400+poX-x];
29: Bwins <= B29[400+poX-x];
30: Bwins <= B30[400+poX-x];
31: Bwins <= B31[400+poX-x];
32: Bwins <= B32[400+poX-x];
33: Bwins <= B33[400+poX-x];
34: Bwins <= B34[400+poX-x];
35: Bwins <= B35[400+poX-x];
36: Bwins <= B36[400+poX-x];
37: Bwins <= B37[400+poX-x];
38: Bwins <= B38[400+poX-x];
39: Bwins <= B39[400+poX-x];
40: Bwins <= B40[400+poX-x];
41: Bwins <= B41[400+poX-x];
42: Bwins <= B42[400+poX-x];
43: Bwins <= B43[400+poX-x];
44: Bwins <= B44[400+poX-x];
45: Bwins <= B45[400+poX-x];
46: Bwins <= B46[400+poX-x];
47: Bwins <= B47[400+poX-x];
48: Bwins <= B48[400+poX-x];
49: Bwins <= B49[400+poX-x];
50: Bwins <= B50[400+poX-x];
51: Bwins <= B51[400+poX-x];
52: Bwins <= B52[400+poX-x];
53: Bwins <= B53[400+poX-x];
54: Bwins <= B54[400+poX-x];
55: Bwins <= B55[400+poX-x];
56: Bwins <= B56[400+poX-x];
57: Bwins <= B57[400+poX-x];
58: Bwins <= B58[400+poX-x];
59: Bwins <= B59[400+poX-x];
60: Bwins <= B60[400+poX-x];
61: Bwins <= B61[400+poX-x];
62: Bwins <= B62[400+poX-x];
63: Bwins <= B63[400+poX-x];
64: Bwins <= B64[400+poX-x];
default: Bwins <= 0;
endcase
end
end
assign A0 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A1 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A2 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A3 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A4 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A5 = 400'b0000000000001111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000001111111111111111111100000000000000000000000000000000000000000001111111111111111111100000001111111111111111111100000001111111111111111111111111111100000000000000000000000000000000001111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A6 = 400'b0000000000001111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000001111111111111111111100000000000000000000000000000000000000000001111111111111111111100000001111111111111111111100000001111111111111111111111111111100000000000000000000000000000000001111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A7 = 400'b0000000110001111111111111111111111111111111111111111111111100000000000110000000110000000110000000110000000110001111111111111111111100000000000110000000110000000110000000110001111111111111111111100000001111111111111111111100000001111111111111111111111111111100000000000111000000111000000111001111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A8 = 400'b0000011111111111111111111111111111111111111111111111111111100000000011111110011111110011111110011111110011111111111111111111111111100000000011111110011111110011111110011111111111111111111111111100000001111111111111111111100000001111111111111111111111111111100000000011111110011111110011111111111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A9 = 400'b0000001111001111111111111111111111111111111111111111111111111111100001111000001111000001111000001111000001111001111111111111111111111111100001111100001111100001111100001111101111111111111111111111111101111111111111111111111111101111111111111111111111111111111111100001111100001111100001111101111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign A10 = 400'b0000001101101111111111111111111111111111111111111111111111111111100001101100001101100001101100001101100001101101111111111111111111111111100001101100001101100001101100001101101111111111111111111111111101111111111111111111111111101111111111111111111111111111111111100001101100001101100001101101111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A11 = 400'b0000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000001111111111111111111111111100000000000000000000000000000000000001111111111111111111111111101111111111111111111111111101111111111111111111111111111111111100000000000000000000000000001111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A12 = 400'b0000000000001111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111101111100000000000000000000000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A13 = 400'b0000011111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111110000000000000000000000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A14 = 400'b0001111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111100000000000000000000000001111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A15 = 400'b0001111111111111111111100000000000000000000000001111111111111111111100000000000110000000110000000110000000110001111111111111111111101111100000110000000110000000110000000110001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111100000000000010000000010001111111111111111111101111101111111111111111111100000000000000000000000000000000000000000000001111110000000000;
assign A16 = 400'b0001111111111111111111100000000000000000000000001111111111111111111100000000011111100011111100011111100011111111111111111111111111101111100011111100011111100011111100011111111111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111100000000011111110011111111111111111111111111101111101111111111111111111100000000000000000000000000000000000000000000001111110000000000;
assign A17 = 400'b0001111111111111111111100000000000000000000000001111111111111111111100000000011111100011111100011111100011111101111111111111111111101111100011111100011111100011111100011111101111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111100000000011111110011111111111111111111111111101111101111111111111111111100000000000000000000000000000000000000000000001111110000000000;
assign A18 = 400'b0001111111111111111111101111111111111111111111111111111111111111111111111100001111100001111100001111100001111101111111111111111111101111100001111100001111100001111100001111101111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111111111100001111100001111101111111111111111111101111101111111111111111111101111111111111111111111111111111111111111111111111110000000000;
assign A19 = 400'b0001111111111111111111101111111111111111111111111111111111111111111111111100001001000001001000001001000001001001111111111111111111101111100000001000000001000000001000000001001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111111111100000001000000001001111111111111111111101111101111111111111111111101111111111111111111111111111111111111111111111111100000000000;
assign A20 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111101111100000000000000000001111111111111111111101111101111111111111111111101111110000000000000000000000000000000000000000000000000000000;
assign A21 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111101111100000000000000000001111111111111111111101111101111111111111111111101111110000000000000000000000000000000000000000000000000000000;
assign A22 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000001111111111100000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111111111111100000000000000001111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A23 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000001111111111100000000000000001111111111111111111101111101111111111111111111101111101111111111111111111111111111111111111111111111100000000000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A24 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000110000000110000000110000000110001111111111111111111101111100000110001111111111100000000000110001111111111111111111101111101111111111111111111101111101111111111111111111100000001111111111111111111100000000000111001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A25 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100011111110011111110011111110011111111111111111111111111101111100011111111111111111100000000011111111111111111111111111101111101111111111111111111101111101111111111111111111100000001111111111111111111100000000011111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign A26 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100001111100001111100001111100001111101111111111111111111101111100001111101111111111111111100001111101111111111111111111101111101111111111111111111101111101111111111111111111101111111111111111111111111111111100001111101111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign A27 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100001111100001111100001111100001111101111111111111111111101111100001111101111111111111111100001111101111111111111111111101111101111111111111111111101111101111111111111111111101111111111111111111111111111111100001111101111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A28 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000001111111111111111100000000001111111111111111111101111101111111111111111111101111101111111111111111111101111111111111111111111111111111100000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A29 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000001111111111101111100000000001111111111111111111101111101111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A30 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111100000000001111111111101111100000000001111111111111111111101111101111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A31 = 400'b0001111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111111111111100000001111111111111111111101111101111111111111111111101111101111111111111111111101111101111111111111111111111111111100000001111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A32 = 400'b0001111111111111111111100000000000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111111111111100000001111111111111111111101111101111111111111111111101111101111111111111111111101111100001111101111111111111111111100000001111111111111111111101111100001111100000000000000000000000000000000000001111111111111111111101111110000000000;
assign A33 = 400'b0001111111111111111111100000000000000000000000001111111111111111111101111100011111100011111100011111100011111101111111111111111111101111101111111111111111111111111111100000001111111111111111111101111101111111111111111111101111101111111111111111111101111100001111101111111111111111111100000001111111111111111111101111100001111100000000000000000000000000000000000001111111111111111111101111110000000000;
assign A34 = 400'b0001111111111111111111100000000000000000000000001111111111111111111101111100011111110011111110011111110011111111111111111111111111101111101111111111111111111111111111100000001111111111111111111101111101111111111111111111101111101111111111111111111101111100001111101111111111111111111100000001111111111111111111101111100001111100000000000000000000000000000000000001111111111111111111101111110000000000;
assign A35 = 400'b0001111111111111111111101111111111111111111111111111111111111111111101111100001111000001111000001111000001111101111111111111111111101111101111111111111111111111111111111111101111111111111111111101111101111111111111111111101111101111111111111111111101111100001111111111111111111111111111111101111111111111111111101111100001111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A36 = 400'b0001111111111111111111101111111111111111111111111111111111111111111101111100001101000001101000001101000001101001111111111111111111101111101111111111111111111111111111111111101111111111111111111101111101111111111111111111101111101111111111111111111101111100001111111111111111111111111111111101111111111111111111101111100001111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A37 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111111111111101111101111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111101111101111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111101111110000000000;
assign A38 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111101111101111111111111111111111111111101111101111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111101111101111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111101111110000000000;
assign A39 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111111111111111111111111111111101111100111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A40 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111101111101111111111111111111101111101111111111111111111101111100000000001111111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A41 = 400'b0001111111111111111111101111100000110000000110001111111111111111111101111100000110000000110000000110000000110000001111101111111111111111111111111111100000001111111111111111111111111111100000000001111101111111111111111111101111101111111111111111111101111100000110000001111101111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A42 = 400'b0001111111111111111111101111100011111100011111111111111111111111111101111100011111110011111110011111110011111110001111101111111111111111111111111111100000001111111111111111111111111111100000000001111101111111111111111111101111101111111111111111111101111100011111110001111101111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A43 = 400'b0001111111111111111111101111100011111100011111101111111111111111111101111100011111100011111100011111100011111100001111111111111111111111111111111111101111111111111111111111111111111111101111111111111101111111111111111111101111101111111111111111111101111100011111100001111111111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A44 = 400'b0001111111111111111111101111100001111100001111101111111111111111111101111100001111100001111100001111100001111100001111111111111111111111111111111111101111111111111111111111111111111111101111111111111101111111111111111111101111101111111111111111111101111100001111100001111111111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A45 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000000001111111111111111111111111111111111101111111111111111111111111111111111101111111111111101111111111111111111101111101111111111111111111101111100000000000001111111111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A46 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111111111111101111101111111111111111111111111111101111100000000001111111111111111111101111101111111111111111111101111100000000000000000001111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A47 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111111111111101111101111111111111111111111111111101111100000000001111111111111111111101111101111111111111111111101111100000000000000000001111111111111111111111111111111111111101111101111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A48 = 400'b0001111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111111111111101111101111111111111111111111111111101111100000000001111111111111111111101111101111111111111111111101111100000000000000000001111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111110000000000;
assign A49 = 400'b0000111111111111111111001111100000000000000000000111111111111111111001111100000000000000000000000000000000000000000000000111111111111111111111111111001111100111111111111111111111111111001111100000000000111111111111111111001111100111111111111111111001111100000000000000000000111111111111111111111111111111111111001111100111111111111111111111111111111111111111111111111111111111111111001111110000000000;
assign A50 = 400'b0000001111100000000000001111100000110000000110000001111100000000000001111100000110000000110000000110000000110000000110000001111100000000000000000000001111100001111100000000000000000000001111100000111000001111100000000000001111100001111100000000000001111100000111000000111000001111100000000000000000000000000000001111100001111100000000000000000000000000000000000000000000000000000000001111110000000000;
assign A51 = 400'b0000001111100000000000001111100011111110011111110001111100000000000001111100011111110011111110011111110011111110011111110001111100000000000000000000001111100001111100000000000000000000001111100011111110001111100000000000001111100001111100000000000001111100011111110011111110001111100000000000000000000000000000001111100001111100000000000000000000000000000000000000000000000000000000001111110000000000;
assign A52 = 400'b0000001111111111111111111111100001111000001111000001111111111111111111111100001111000001111000001111000001111000001111000001111111111111111111111111111111100001111111111111111111111111111111100001111100001111111111111111111111100001111111111111111111111100001111100001111100001111111111111111111111111111111111111111100001111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A53 = 400'b0000001111111111111111111111100001111100001111100001111111111111111111111100001111100001111100001111100001111100001111100001111111111111111111111111111111100001111111111111111111111111111111100001111100001111111111111111111111100001111111111111111111111100001111100001111100001111111111111111111111111111111111111111100001111111111111111111111111111111111111111111111111111111111111111111110000000000;
assign A54 = 400'b0000000111111111111111111111000000000000000000000000011111111111111111111000000000000000000000000000000000000000000000000000011111111111111111111111111111000000011111111111111111111111111111000000000000000011111111111111111111000000011111111111111111111000000000000000000000000011111111111111111111111111111111111111000000011111111111111011111111011111111011111111011111111011111111011111000000000000;
assign A55 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A56 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A57 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A58 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A59 = 400'b0000011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111100011111110011111110011111110011111110011111110011111110011111110000000000;
assign A60 = 400'b0000011111100011111100011111100011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110011111110000000000;
assign A61 = 400'b0000001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100000000000;
assign A62 = 400'b0000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000001001000000001000000001000000001000000101000000101000000101000000101100000101100000101100000101100000000000;
assign A63 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A64 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A65 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A66 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign A67 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B0 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B1 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B2 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B3 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B4 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000001111111111111111111000000000000000000000000000000000000000000011111111111111111110000000011111111111111111110000000111111111111111111111111111110000000000000000000000000000000000111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111000000000000000000;
assign B5 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000001111111111111111111000000000000000000000000000000000000000000011111111111111111110000000011111111111111111110000000111111111111111111111111111110000000000000000000000000000000000111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B6 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000000110000000110000000110000001110000001110001111111111111111111000000000001100000001100000001100000001100011111111111111111110000000011111111111111111110000000111111111111111111111111111110000000000011000000011000000011000111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B7 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000011111100011111100011111100111111100111111111111111111111111111000000000111111100111111100111111100111111111111111111111111110000000011111111111111111110000000111111111111111111111111111110000000001111110001111110001111111111111111111111111100000001111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B8 = 400'b0000000111111111111111111111111111111111111111111111111111111111111100001111000001111000001111000011111000011111001111111111111111111111111000011110000011110000011110000011110011111111111111111111111111011111111111111111111111110111111111111111111111111111111111110000111100000111100000111100111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B9 = 400'b0000000111111111111111111111111111111111111111111111111111111111111100001111000001111000011111000011111000011111001111111111111111111111111000011111000011111000011111000011110011111111111111111111111111011111111111111111111111110111111111111111111111111111111111110000111100000111100001111100111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B10 = 400'b0000000111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000001111111111111111111111111000000000000000000000000000000000000011111111111111111111111111011111111111111111111111110111111111111111111111111111111111110000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B11 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111011111000000000000000000000000000000000000011111111111111111110111111011111111111111111110111110111111111111111111111111111110111110000000000000000000000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B12 = 400'b0000000111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000000000000001111111111111111111011111000000000000000000000000000000000000011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111100000000000000000000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B13 = 400'b0000001111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000011111111111111111111011111000000000000000000000000000000000000011111111111111111110111111111111111111111111110111110111111111111111111111111111111111111110000000000000000000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111011111100000000000;
assign B14 = 400'b0000000111111111111111111100000000000000000000000001111111111111111111100000000000100000000100000000100000000100001111111111111111111011111000001100000001100000001100000001100011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111110000000000010000000010000111111111111111111101111111111111111111111111100000000000000000000000000000000000000000000001111100000000000;
assign B15 = 400'b0000000111111111111111111100000000000000000000000001111111111111111111100000000011111100011111100011111100111111111111111111111111111011111000111111000111111000111111000111111111111111111111111110111111011111111111111111110111110111111111111111111111111111111111111110000000001111110001111111111111111111111111101111111111111111111111111100000000000000000000000000000000000000000000001111100000000000;
assign B16 = 400'b0000000111111111111111111100111111111111111111111111111111111111111111111111000011111100011111100011111100111111111111111111111111111011111000111111000111111000111111000111111111111111111111111110111111011111111111111111110111110111111111111111111111111111111111111111111100001111110001111111111111111111111111101111111111111111111111111100111111111111111111111111111111111111111111111111100000000000;
assign B17 = 400'b0000000111111111111111111101111111111111111111111111111111111111111111111111100001111000001111000011111000011111001111111111111111111011111000011111000011111000011110000011110011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111111111110000111100001111100111111111111111111101111111111111111111111111101111111111111111111111111111111111111111111111111100000000000;
assign B18 = 400'b0000000111111111111111111101111111111111111111111111111111111111111111111111100001001000001001000001011000001011001111111111111111111011111000010010000010010000010010000010010011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111111111110000100100000100100111111111111111111101111111111111111111111111101111111111111111111111111111111111111111111111111100000000000;
assign B19 = 400'b0000000111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111011111000000000000000000000000000000000000011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111110111110000000000000000000111111111111111111101111111111111111111111111101111100000000000000000000000000000000000000000000000000000000;
assign B20 = 400'b0000000111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111011111000000000000000000000000000000000000011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111110111110000000000000000000111111111111111111101111111111111111111111111101111100000000000000000000000000000000000000000000000000000000;
assign B21 = 400'b0000000111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000011111111111111111111011111000000000011111111111000000000000000011111111111111111110111111111111111111111111110111110111111111111111111111111111111111111111111111100000000000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111000000000000000000;
assign B22 = 400'b0000000111111111111111111111111111111111111111111111111111111111111111001111100000000000000000000000000000000000011111111111111111111011111000000000011111111111000000000000000011111111111111111110111111011111111111111111110111110111111111111111111111111111111111111111111111110000000000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B23 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000001111100000110000000110000001110000001110001111111111111111111011111000001100011111111111000000000001100011111111111111111110111111011111111111111111110111110111111111111111111110000000111111111111111111110000000000011000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B24 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000001111100011111100111111100111111100111111111111111111111111111011111000111111111111111111000000000111111111111111111111111110111111011111111111111111110111110111111111111111111110000000111111111111111111110000000011111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111100000000000000000;
assign B25 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111100001111000001111000011111000011111001111111111111111111011111000011110011111111111111111000011110011111111111111111110111111011111111111111111110111110111111111111111111110111111111111111111111111111111110000111100111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111000000000000;
assign B26 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111100001111000011111000011111000011111001111111111111111111011111000011111011111111111111111000011111011111111111111111110111111011111111111111111110111110111111111111111111110111111111111111111111111111111110001111100111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B27 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111000000000000000000000000000000000000001111111111111111111011111000000000011111111111111111000000000011111111111111111110111111011111111111111111110111110111111111111111111110111111111111111111111111111111110000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B28 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111011111000000000011111111111011111000000000011111111111111111110111111011111111111111111110111110111111111111111111110111110111111111111111111110111110000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B29 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000001111111111111111111011111000000000011111111111011111000000000011111111111111111110111111011111111111111111110111110111111111111111111110111110111111111111111111110111110000000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B30 = 400'b0000001111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000011111111111111111111011111011111111111111111111111111111000000011111111111111111110111111111111111111111111110111110111111111111111111110111110111111111111111111111111111110000000111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B31 = 400'b0000000111111111111111111100000000000000000000000001111111111111111111100000000000000000000000000000000000000000001111111111111111111011111011111111111111111111111111111000000011111111111111111110111111011111111111111111110111110111111111111111111110111110000111110111111111111111111110000000111111111111111111101111110001111100000000000000000000000000000000000001111111111111111111101111100000000000;
assign B32 = 400'b0000000111111111111111111100000000000000000000000001111111111111111111100000000010110000011110000011110000011111001111111111111111111011111011111111111111111111111111111000000011111111111111111110111111011111111111111111110111110111111111111111111110111110000111110111111111111111111110000000111111111111111111101111110001111100000000000000000000000000000000000001111111111111111111101111100000000000;
assign B33 = 400'b0000000111111111111111111100000000000000000000000001111111111111111111100000000011111100011111100111111100111111111111111111111111111011111011111111111111111111111111111000000011111111111111111110111111011111111111111111110111110111111111111111111110111110000111110111111111111111111110000000111111111111111111101111110001111100000000000000000000000000000000000001111111111111111111101111100000000000;
assign B34 = 400'b0000000111111111111111111101111111111111111111111111111111111111111111111111100001111000001111000011111000011111001111111111111111111011111011111111111111111111111111111111111011111111111111111110111111011111111111111111110111110111111111111111111110111110000111111111111111111111111111111110111111111111111111101111110001111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B35 = 400'b0000000111111111111111111101111111111111111111111111111111111111111111111111100001011000001011000001011000011011001111111111111111111011111011111111111111111111111111111111111011111111111111111110111111011111111111111111110111110111111111111111111110111110000111111111111111111111111111111110111111111111111111101111110001111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B36 = 400'b0000000111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111011111011111111111111111111111111111011111011111111111111111110111111011111111111111111110111110111111111111111111110111110000000000111111111111111111111111110111111111111111111101111110000000000000000000000000000000000000000000001111111111111111111101111100000000000;
assign B37 = 400'b0000000111111111111111111101111100000000000000000001111111111111111111101111100000000000000000000000000000000000001111111111111111111011111011111111111111111111111111111011111011111111111111111110111111011111111111111111110111110111111111111111111110111110000000000111111111111111111110111110111111111111111111101111110000000000000000000000000000000000000000000001111111111111111111101111100000000000;
assign B38 = 400'b0000000111111111111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111110111111011111111111111111110111110111111111111111111110111110000000000111111111111111111111111111111111111111111111101111110111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B39 = 400'b0000000111111111111111111111111111111111111111111111111111111111111111001111100000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111110111111011111111111111111110111110111111111111111111110111110000000000111111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B40 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000001111100000110000000110000000110000000110000011111111111111111111111111111111111000000011111111111111111111111111111000000000111111011111111111111111110111110111111111111111111110111110000011000000111110111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B41 = 400'b0000000111111111111111111111111111111111111111111111111111111100000000001111100011111100011111100011111100111111100011111111111111111111111111111111111000000011111111111111111111111111111000000000111111011111111111111111110111110111111111111111111110111110001111110000111110111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B42 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111100011111100011111100011111100011111100011111111111111111111111111111111111011111111111111111111111111111111111011111111111111011111111111111111110111110111111111111111111110111110001111110000111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B43 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111100001111000011111000011111000011111000011111111111111111111111111111111111011111111111111111111111111111111111011111111111111011111111111111111110111110111111111111111111110111110000111110000111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B44 = 400'b0000000111111111111111111111111111111111111111111111111111111101111111111111100000000000000000000000000000000000000011111111111111111111111111111111111011111111111111111111111111111111111011111111111110011111111111111111110111110111111111111111111110111110000000000000111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B45 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000000000000011111111111111111111111111111011111011111111111111111111111111111011111000000000011111111111111111110111110111111111111111111110111110000000000000000000111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B46 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000000000000011111111111111111111111111111011111011111111111111111111111111111011111000000000011111111111111111110111110111111111111111111110111110000000000000000000111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111101111100000000000;
assign B47 = 400'b0000000111111111111111111111111111111111111111111111111111111101111100000000000000000000000000000000000000000000000000000011111111111111111111111111111011111011111111111111111111111111111111111000000000011111111111111111110111110111111111111111111110111110000000000000000000111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B48 = 400'b0000000111111111111111111111111111111111111111111111111111110001111100000000000000000000000000000000000000000000000000000001111111111111111111111111110011111001111111111111111111111111100011111000000000011111111111111111100111110011111111111111111100111110000000000000000000011111111111111111111111111111111111001111110111111111111111111111111111111111111111111111111111111111111110001111100000000000;
assign B49 = 400'b0000000001111110000000000000000000000000000000000000000000000001111100010110100010110100011111100011111000011111000011111000011111000000000000000000000011111000011111000000000000000000000011111000111110000111111000000000000111110000111110000000000000111110001011010001011010000111110000000000000000000000000000001111110001111100000000000000000000000000000000000000000000000000000000001111100000000000;
assign B50 = 400'b0000000001111110000000000000000000000000000000000000000000000001111100011111100011111100011111100011111100111111100111111100011111000000000000000000000011111000011111000000000000000000000011111001111111000111111000000000000111110000111110000000000000111110001111110001111110000111110000000000000000000000000000001111110001111100000000000000000000000000000000000000000000000000000000001111100000000000;
assign B51 = 400'b0000000001111111111111111111111111111111111111111111111111111111111100001111000001111000001111000011111000011111000011111000011111111111111111111111111111111000011111111111111111111111111111111000111110000111111111111111111111110000111111111111111111111110000111100000111100000111111111111111111111111111111111111111110001111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B52 = 400'b0000000001111111111111111111111111111111111111111111111111111111111100001011000001011000001011000011011000011011000011011000011111111111111111111111111111111000011111111111111111111111111111111000110110000111111111111111111111110000111111111111111111111110000111100000101100000111111111111111111111111111111111111111100001111111111111111111111111111111111111111111111111111111111111111111100000000000;
assign B53 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B54 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B55 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B56 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B57 = 400'b0000000000010000000010000000010000000110000000110000000110000000110000000110000000110000000110000000100000000100000000100000000100000001100000001100000001100000001100000001100000001100000001100000001000000001000000001000000001000000011000000011000000011000000011000000011000000011000000011000000010000000010000000010000000010000000110000000110000000110000000110000000110000000110000000110000000000000;
assign B58 = 400'b0000000011111110011111110011111110011111110011111100011111100011111100011111100011111100011111100011111100111111100111111100111111100111111100111111000111111000111111000111111000111111000111111000111111001111111001111111001111111001111111001111110001111110001111110001111110001111110001111110001111110011111110011111110011111110011111110011111100011111100011111100011111100011111100011111100000000000;
assign B59 = 400'b0000000001111110011111110011111110011111100011111100011111100011111100011111100011111100011111100011111100011111100111111100111111100111111000111111000111111000111111000111111000111111000111111000111111000111111001111111001111111001111110001111110001111110001111110001111110001111110001111110001111110001111110011111110011111110011111100011111100011111100011111100011111100011111100011111100000000000;
assign B60 = 400'b0000000001111100001111100001111100001111100001111100001111100001111100001111100011111100011111000011111000011111000011111000011111000011111000011111000011111000011111000011111000111111000111110000111110000111110000111110000111110000111110000111110000111110000111110000111110001111110001111100001111100001111100001111100001111100001111100001111100001111100001111100001111100011111100011111000000000000;
assign B61 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B62 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B63 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign B64 = 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
endmodule
|
/* Copyright (c) 2015, William Breathitt Gray
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
module monostable(
input clk,
input reset,
input trigger,
output reg pulse = 0
);
parameter PULSE_WIDTH = 0;
reg [4:0] count = 0;
wire count_rst = reset | (count == PULSE_WIDTH);
always @ (posedge trigger, posedge count_rst) begin
if (count_rst) begin
pulse <= 1'b0;
end else begin
pulse <= 1'b1;
end
end
always @ (posedge clk, posedge count_rst) begin
if(count_rst) begin
count <= 0;
end else begin
if(pulse) begin
count <= count + 1'b1;
end
end
end
endmodule
module delayed_monostable(
input clk,
input reset,
input trigger,
output pulse
);
parameter DELAY_WIDTH = 0;
parameter SIGNAL_WIDTH = 0;
wire dly;
monostable #(.PULSE_WIDTH(DELAY_WIDTH)) delay(
.clk(clk),
.reset(reset),
.trigger(trigger),
.pulse(dly)
);
wire trig = ~dly;
monostable #(.PULSE_WIDTH(SIGNAL_WIDTH)) signal(
.clk(clk),
.reset(reset),
.trigger(trig),
.pulse(pulse)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ddr3_eim_burst(
input wire bclk,
// sync to bclk
input wire [15:0] bus_ad, // raw mux data
input wire [2:0] bus_a, // high address bits
input wire adv, // active high, so connect to !EIM_LBA
input wire rw, // low = write, high = read, so connect to EIM_RW
input wire cs, // active high, so connect to !EIM_CS[1]
output reg [15:0] rbk_d, // readback tri-state interface
// sync to bclk
output wire [2:0] ddr3_rd_cmd,
output wire [5:0] ddr3_rd_bl,
output reg [29:0] ddr3_rd_adr,
output reg ddr3_rd_cmd_en,
input wire ddr3_rd_cmd_empty,
input wire ddr3_rd_cmd_full,
// sync to bclk
input wire [31:0] ddr3_rd_data,
input wire [6:0] ddr3_rd_count,
input wire ddr3_rd_empty,
input wire ddr3_rd_full,
output wire ddr3_rd_en,
// async
input wire clear_error,
output reg full_error,
output reg empty_error,
input wire enable, // when high, enable page filling
input wire init, // when asserted, module resets and goes to zero-full page state
input wire [17:0] startpage, // address where to start reading from (4k page-aligned)
input wire [15:0] burstlen, // length of a burst
input wire bclk_reset
);
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
wire [15:0] rdata;
reg [1:0] reset_s;
reg [2:0] enable_s;
reg [2:0] init_s;
reg [17:0] startpage_s;
reg [1:0] clear_error_s;
wire fifo_prog_empty;
reg [15:0] burstlen_s;
// issue read commands to the memory interface
// read address is directly a register
assign ddr3_rd_cmd = 3'b001;
assign ddr3_rd_bl = 6'b011111; // 32-element burst read (x32 bits wide = 128 bytes)
reg [1:0] setup_ok; // assert when conditions are right to issue a read
always @(posedge bclk) begin
setup_ok[1:0] <= {setup_ok[0],
((ddr3_rd_count[6:0] == 7'b0) || ddr3_rd_empty) && fifo_prog_empty && enable_s[2]};
if( reset_s[1] ) begin
ddr3_rd_cmd_en <= 1'b0;
end else begin
if(!setup_ok[1] && setup_ok[0]) begin // issue only on rising edge of setup_ok
ddr3_rd_cmd_en <= 1'b1;
end else begin
ddr3_rd_cmd_en <= 1'b0;
end
end
if( reset_s[1] ) begin
ddr3_rd_adr[29:0] <= {startpage_s[17:0],12'b0}; // page-aligned address
end else begin
if( ddr3_rd_cmd_en ) begin // this is active for exactly one cycle
ddr3_rd_adr[29:0] <= ddr3_rd_adr[29:0] + 30'h80; // inc by one burst stride
// and we totally allow wrap-around, if you're not careful
end else begin
ddr3_rd_adr[29:0] <= ddr3_rd_adr[29:0];
end
end
end // always @ (posedge bclk)
wire [15:0] fifo_deb_dout;
assign ddr3_rd_en = 1'b1; // always read when data's present
wire full, empty;
fifo_ddr3_eim_burst fifo_deb (
.rst(reset_s[1]), // input rst
.wr_clk(bclk), // input wr_clk
.rd_clk(bclk), // input rd_clk
.din(ddr3_rd_data), // input [31 : 0] din
.wr_en(!ddr3_rd_empty), // input wr_en
.rd_en(activated && (burstlen_s[15:0] > burstcnt[15:0])), // input rd_en
.dout(fifo_deb_dout), // output [15 : 0] dout
.full(full), // output full
// .almost_full(almost_full), // output almost_full
.empty(empty), // output empty
// .almost_empty(almost_empty), // output almost_empty
.prog_empty(fifo_prog_empty) // output prog_empty
);
reg empty_d;
always @(posedge bclk) begin
empty_d <= empty; // prep rising edge det of empty
if(clear_error_s[1] || reset_s[1]) begin
full_error <= 1'b0;
end else begin
if( full ) begin
full_error <= 1'b1;
end else begin
full_error <= full_error;
end
end
if(clear_error_s[1] || reset_s[1]) begin
empty_error <= 1'b0;
end else begin
if( !empty_d && empty ) begin // empty should never rise once it falls
empty_error <= 1'b1;
end else begin
empty_error <= empty_error;
end
end
end // always @ (posedge bclk)
// incoming synchronizers
always @(posedge bclk) begin
init_s[2:0] <= {init_s[1:0], init};
reset_s[1:0] <= {reset_s[0], (!init_s[2] && init_s[1]) || bclk_reset};
enable_s[2:0] <= {enable_s[1:0], enable};
startpage_s <= startpage; // just one level of sync because this should be static at point of use
clear_error_s[1:0] <= {clear_error_s[0], clear_error};
end
reg [15:0] burstcnt;
////// address decode path
always @(posedge bclk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
burstlen_s <= burstlen;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r[15:12]} == 7'h4_F) ) begin // 0xc04_fxxx page for bursting
activated <= 1'b1;
end else if( !cs_r ) begin
activated <= 1'b0;
end else begin
activated <= activated;
end // else: !if( !cs )
if( !activated ) begin
burstcnt <= 16'h0;
end else begin
burstcnt <= burstcnt + 16'h1;
end
end // always @ (posedge clk)
always @(*) begin
if( activated && rw_r ) begin
rbk_d = fifo_deb_dout;
end else begin
rbk_d = 16'hZZZZ;
end
end
endmodule // ddr3_eim_burst
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
reg clk = 1'b0;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
wire resetn = ~reset;
reg failed = 1'b0;
initial
begin
$dumpfile (VCD_FILE);
$dumpvars;
`ifdef TIMEOUT
#`TIMEOUT
`else
#100000
`endif
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 3'b111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V
|
//#############################################################################
//# Function: MIO Configuration Registers #
//# (See README.md for complete documentation) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) #
//#############################################################################
`include "mio_regmap.vh"
module mio_regs #(parameter N = 8, // number of I/O pins
parameter AW = 32, // address width
parameter PW = 104, // packet width
parameter DEF_CFG = 0, // reset MIO_CONFIG value
parameter DEF_CLK = 0 // reset MIO_CLKDIV value
)
(
// clk,reset
input clk,
input nreset,
// register access interface
input access_in, // incoming access
input [PW-1:0] packet_in, // incoming packet
output wait_out,
output access_out, // outgoing read packet
output [PW-1:0] packet_out, // outgoing read packet
input wait_in,
// config outputs
output tx_en, // enable tx
output rx_en, // enable rx
output ddr_mode, // ddr mode for mio
output emode, // epiphany packet mode
output amode, // mio packet mode
output dmode, // mio packet mode
output [7:0] datasize, // mio datasize
output lsbfirst, // lsb shift first
output framepol, // framepolarity (0=actrive high)
output [4:0] ctrlmode, // emode ctrlmode
output [AW-1:0] dstaddr, // destination address for RX dmode
output clkchange, // indicates a clock change
output [7:0] clkdiv, // mio clk clock setting
output [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
output [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
// status inputs
input tx_full, //tx fifo is full (should not happen!)
input tx_prog_full, //tx fifo is nearing full
input tx_empty, //tx fifo is empty
input rx_full, //rx fifo is full (should not happen!)
input rx_prog_full, //rx fifo is nearing full
input rx_empty //rx fifo is empty
);
localparam DEF_RISE0 = 0; // 0 degrees
localparam DEF_FALL0 = ((DEF_CLK+8'd1)>>8'd1); // 180 degrees
localparam DEF_RISE1 = ((DEF_CLK+8'd1)>>8'd2); // 90 degrees
localparam DEF_FALL1 = ((DEF_CLK+8'd1)>>8'd2)+
((DEF_CLK+8'd1)>>8'd1); // 270 degrees
//##############
//# LOCAL WIRES
//##############
reg [20:0] config_reg;
reg [15:0] status_reg;
reg [31:0] clkdiv_reg;
reg [63:0] addr_reg;
reg [31:0] clkphase_reg;
wire [7:0] status_in;
wire reg_write;
wire config_write;
wire status_write;
wire clkdiv_write;
wire clkphase_write;
wire idelay_write;
wire odelay_write;
wire addr0_write;
wire addr1_write;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//#####################################
//# DECODE
//#####################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = write_in & access_in;
assign config_write = reg_write & (dstaddr_in[5:2]==`MIO_CONFIG);
assign status_write = reg_write & (dstaddr_in[5:2]==`MIO_STATUS);
assign clkdiv_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKDIV);
assign clkphase_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKPHASE);
assign idelay_write = reg_write & (dstaddr_in[5:2]==`MIO_IDELAY);
assign odelay_write = reg_write & (dstaddr_in[5:2]==`MIO_ODELAY);
assign addr0_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR0);
assign addr1_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR1);
assign clkchange = clkdiv_write | clkphase_write;
//################################
//# CONFIG
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
config_reg[20:0] <= DEF_CFG;
end
else if(config_write)
config_reg[20:0] <= data_in[20:0];
assign tx_en = ~config_reg[0]; // tx disable
assign rx_en = ~config_reg[1]; // rx disable
assign emode = config_reg[3:2]==2'b00; // emesh packets
assign dmode = config_reg[3:2]==2'b01; // data mode (streaming)
assign amode = config_reg[3:2]==2'b10; // auto address mode
assign datasize[7:0] = config_reg[11:4]; // number of flits per packet
assign ddr_mode = config_reg[12]; // dual data rate mode
assign lsbfirst = config_reg[13]; // lsb-first transmit
assign framepol = config_reg[14]; // frame polarity
assign ctrlmode[4:0] = config_reg[20:16]; // ctrlmode
//###############################
//# STATUS
//################################
assign status_in[7:0] = {2'b0, //7:6
tx_full, //5
tx_prog_full,//4
tx_empty, //3
rx_full, //2
rx_prog_full,//1
rx_empty //0
};
always @ (posedge clk or negedge nreset)
if(!nreset)
status_reg[15:0] <= 'b0;
else if(status_write)
status_reg[15:0] <= data_in[7:0];
else
status_reg[15:0] <= {(status_reg[15:8] | status_in[7:0]), // sticky bits
status_in[7:0]}; // immediate bits
//###############################
//# CLKDIV
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkdiv_reg[7:0] <= DEF_CLK;
else if(clkdiv_write)
clkdiv_reg[7:0] <= data_in[7:0];
assign clkdiv[7:0] = clkdiv_reg[7:0];
//###############################
//# CLKPHASE
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
clkphase_reg[7:0] <= DEF_RISE0;
clkphase_reg[15:8] <= DEF_FALL0;
clkphase_reg[23:16] <= DEF_RISE1;
clkphase_reg[31:24] <= DEF_FALL1;
end
else if(clkphase_write)
clkphase_reg[31:0] <= data_in[31:0];
assign clkphase0[15:0] = clkphase_reg[15:0];
assign clkphase1[15:0] = clkphase_reg[31:16];
//###############################
//# RX DESTINATION ADDR ("AMODE")
//################################
always @ (posedge clk)
if(addr0_write)
addr_reg[31:0] <= data_in[31:0];
else if(addr1_write)
addr_reg[63:32] <= data_in[31:0];
assign dstaddr[AW-1:0] = addr_reg[AW-1:0];
//###############################
//# READBACK
//################################
assign access_out ='b0;
assign wait_out ='b0;
assign packet_out ='b0;
endmodule
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../../oh/common/hdl")
// End:
|
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
// Takes input messages to set taps.
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output wire out_nd,
output wire [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire error
);
filterbank
#(`N_FILTERS, WIDTH, 1, `FILTER_LENGTH, `FILTERBANK_ID,
`FILTERBANK_MSG_BUFFER_LENGTH)
filterbank_0
(
.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_data),
.out_nd(out_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(error)
);
endmodule
|
module mult4(
a0,a1,a2,a3,
b0,b1,b2,b3,
z0,z1,z2,z3,z4,z5,z6,z7);
input a0,a1,a2,a3,b0,b1,b2,b3;
output z0,z1,z2,z3,z4,z5,z6,z7;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign z0 = a0&b0;
//HA
assign z1 = (a1&b0)^(a0&b1);
assign x1 = (a1&b0)&(a0&b1);
//FA
assign x2 = (a1&b2)^(a0&b2)^x1;
assign x3 = ((a1&b2)&(a0&b2)) | ((a1&b2)&x1) | ((a0&b2)&x1);
//FA
assign x4 = (a1&b2)^(a0&b3)^x3;
assign x5 = ((a1&b2)&(a0&b3)) | ((a1&b2)&x3) | ((a0&b3)&x3);
//HA
assign x6 = (a1&b3)^x5;
assign x7 = (a1&b3)&x5;
//HA
assign z2 = x2^(a2&b0);
assign x15 = x2&(a2&b0);
//FA
assign x14 = x4^(a2&b1)^x15;
assign x16 = (x4&(a2&b1)) | (x4&x15) | ((a2&b1)&x15);
//FA
assign x13 = x6^(a2&b1)^x15;
assign x17 = (x6&(a2&b1)) | (x6&x15) | ((a2&b1)&x15);
//FA
assign x9 = x7^(a2&b3)^x17;
assign x8 = (x7&(a2&b3)) | (x7&x17) | ((a2&b3)&x17);
//ha
assign z3 = x14^(a3&b0);
assign x12 = x14&(a3&b0);
//fa
assign z4 = x13^(a3&b1)^x12;
assign x11 = (x13&(a3&b1)) | (x13&x12) | ((a3&b1)&x12);
//fa
assign z5 = x9^(a3&b2)^x11;
assign x10 = (x9&(a3&b2)) | (x9&x11) | ((a3&b2)&x11);
//fa
assign z6 = x8^(a3&b3)^x10;
assign z7 = (x8&(a3&b3)) | (x8&x10) | ((a3&b3)&x10);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O311AI_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ls__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_BEHAVIORAL_PP_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_WRITE = 1,
WRITE_STATE_WAIT_BUSY = 2,
WRITE_STATE_WAIT_DONE = 3,
WRITE_STATE_RESET = 4,
WRITE_STATE_ERROR = 5;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_WAIT_BUSY = 1,
ERASE_STATE_WAIT_DONE = 2,
ERASE_STATE_RESET = 3,
ERASE_STATE_ERROR = 4;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_READ = 1,
READ_STATE_SETUP = 1,
READ_STATE_DUMMY = 2,
READ_STATE_READY = 3,
READ_STATE_FINAL = 4,
READ_STATE_CLEAR = 5;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [0:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_clear_busy;
reg write_clear_busy;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire [FLASH_ADDR_WIDTH-1:0] cur_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_erase_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign flash_addr_wire =
(valid_csr_erase && valid_csr_sector_erase_addr) ? { flash_sector_wire, 1'b0, {(19){1'b1}} } :
flash_page_addr_wire;
assign csr_write_protection_mode = csr_control[27:23];
// burst count check
assign is_valid_write_burst_count = (avmm_burstcount == 1);
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
assign flash_addr_wire = flash_page_addr_wire;
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1) || (avmm_read == 1);
assign flash_erase_addr = (valid_csr_sector_erase_addr) ? csr_sector_erase_addr : csr_page_erase_addr;
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_addr = (valid_csr_erase) ? flash_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && read_state == READ_STATE_FINAL);
assign flash_se = (is_read_busy && read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_addr = (valid_csr_erase) ? flash_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_ardin = flash_addr_wire;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
assign avmm_readdata = (csr_status_r_pass) ? flash_drdout : 32'hffffffff;
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_clear_busy = 0;
write_clear_busy = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= flash_arclk_arshft_en_w;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge erase_clear_busy or posedge write_clear_busy or posedge flash_osc) begin
if (~reset_n || erase_clear_busy || write_clear_busy) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_1 (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_2 (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_clear_busy <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_wait <= 1;
// address legality check
if (is_addr_writable && is_valid_write_burst_count) begin
write_state <= WRITE_STATE_WRITE;
write_count <= DATA_WIDTH[5:0];
end
else begin
write_state <= WRITE_STATE_ERROR;
write_wait <= 0;
write_count <= 2;
end
end
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_clear_busy <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[5:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_clear_busy <= 1'b1;
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_clear_busy <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (~flash_busy_sync && ~flash_busy_clear_sync) begin
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_clear_busy <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
// address legality check
if (is_addr_writable) begin
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_clear_busy <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[5:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_clear_busy <= 1'b1;
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_clear_busy <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (~flash_busy_sync && ~flash_busy_clear_sync) begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_SETUP;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
// incrementing read
READ_STATE_SETUP: begin
read_wait <= 1;
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_SETUP;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_READ;
avmm_burstcount_input_reg <= avmm_burstcount;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
end
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 4) begin
read_wait <= 0;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
avmm_burstcount_input_reg <= avmm_burstcount;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
end
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
altera_onchip_flash_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR),
.SECTOR_READ_PROTECTION_MODE(SECTOR_READ_PROTECTION_MODE)
) address_write_protection_checker (
.use_sector_addr(valid_csr_erase && valid_csr_sector_erase_addr),
.address(cur_addr),
.write_protection_mode(csr_write_protection_mode),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
module prometheus_fx3_loopback(
input rst_n,
input clk_100,
input loopback_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
input i_gpif_in_ch1_rdy_d,
input i_gpif_out_ch1_rdy_d,
input [31:0]data_in_loopback,
output o_gpif_re_n_loopback_,
output o_gpif_oe_n_loopback_,
output o_gpif_we_n_loopback_,
output loopback_rd_select_slavefifo_addr,
output [31:0] data_out_loopback
);
//internal fifo control signal
reg [1:0] oe_delay_cnt;
reg rd_oe_delay_cnt;
wire [31:0] fifo_data_in;
reg o_gpif_re_n_loopback_d1_;
reg o_gpif_re_n_loopback_d2_;
reg o_gpif_re_n_loopback_d3_;
reg o_gpif_re_n_loopback_d4_;
reg [3:0]current_loop_back_state;
reg [3:0]next_loop_back_state;
//parameters for LoopBack mode state machine
parameter [3:0] loop_back_idle = 4'd0;
parameter [3:0] loop_back_flagc_rcvd = 4'd1;
parameter [3:0] loop_back_wait_flagd = 4'd2;
parameter [3:0] loop_back_read = 4'd3;
parameter [3:0] loop_back_read_rd_and_oe_delay = 4'd4;
parameter [3:0] loop_back_read_oe_delay = 4'd5;
parameter [3:0] loop_back_wait_flaga = 4'd6;
parameter [3:0] loop_back_wait_flagb = 4'd7;
parameter [3:0] loop_back_write = 4'd8;
parameter [3:0] loop_back_write_wr_delay = 4'd9;
parameter [3:0] loop_back_flush_fifo = 4'd10;
assign o_gpif_re_n_loopback_ = ((current_loop_back_state == loop_back_read) | (current_loop_back_state == loop_back_read_rd_and_oe_delay)) ? 1'b0 : 1'b1;
assign o_gpif_oe_n_loopback_ = ((current_loop_back_state == loop_back_read) | (current_loop_back_state == loop_back_read_rd_and_oe_delay) | (current_loop_back_state == loop_back_read_oe_delay)) ? 1'b0 : 1'b1;
assign o_gpif_we_n_loopback_ = ((current_loop_back_state == loop_back_write)/* | (current_loop_back_state == loop_back_write_wr_delay)*/) ? 1'b0 : 1'b1;
//delay for reading from slave fifo(data will be available after two clk cycle)
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
o_gpif_re_n_loopback_d1_ <= 1'b1;
o_gpif_re_n_loopback_d2_ <= 1'b1;
o_gpif_re_n_loopback_d3_ <= 1'b1;
o_gpif_re_n_loopback_d4_ <= 1'b1;
end else begin
o_gpif_re_n_loopback_d1_ <= o_gpif_re_n_loopback_;
o_gpif_re_n_loopback_d2_ <= o_gpif_re_n_loopback_d1_;
o_gpif_re_n_loopback_d3_ <= o_gpif_re_n_loopback_d2_;
o_gpif_re_n_loopback_d4_ <= o_gpif_re_n_loopback_d3_;
end
end
//Control signal of fifo for LoopBack mode
assign fifo_push = (o_gpif_re_n_loopback_d4_ == 1'b0) & loopback_mode_selected;
assign fifo_pop = (current_loop_back_state == loop_back_write);
assign fifo_flush = (current_loop_back_state == loop_back_flush_fifo);
assign fifo_data_in = (o_gpif_re_n_loopback_d4_ == 1'b0) ? data_in_loopback : 32'd0;
assign loopback_rd_select_slavefifo_addr = ((current_loop_back_state == loop_back_flagc_rcvd) | (current_loop_back_state == loop_back_wait_flagd) | (current_loop_back_state == loop_back_read) | (current_loop_back_state == loop_back_read_rd_and_oe_delay) | (current_loop_back_state == loop_back_read_oe_delay));
//assign loopback_wr_select_fifo_addr =
//counter to delay the read and output enable signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
rd_oe_delay_cnt <= 1'b0;
end else if(current_loop_back_state == loop_back_read) begin
rd_oe_delay_cnt <= 1'b1;
end else if((current_loop_back_state == loop_back_read_rd_and_oe_delay) & (rd_oe_delay_cnt > 1'b0))begin
rd_oe_delay_cnt <= rd_oe_delay_cnt - 1'b1;
end else begin
rd_oe_delay_cnt <= rd_oe_delay_cnt;
end
end
//Counter to delay the OUTPUT Enable(oe) signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
oe_delay_cnt <= 2'd0;
end else if(current_loop_back_state == loop_back_read_rd_and_oe_delay) begin
oe_delay_cnt <= 2'd2;
end else if((current_loop_back_state == loop_back_read_oe_delay) & (oe_delay_cnt > 1'b0))begin
oe_delay_cnt <= oe_delay_cnt - 1'b1;
end else begin
oe_delay_cnt <= oe_delay_cnt;
end
end
//LoopBack state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_loop_back_state <= loop_back_idle;
end else begin
current_loop_back_state <= next_loop_back_state;
end
end
//LoopBack mode state machine combo
always @(*)begin
next_loop_back_state = current_loop_back_state;
case(current_loop_back_state)
loop_back_idle:begin
if(loopback_mode_selected & (i_gpif_in_ch1_rdy_d == 1'b1))begin
next_loop_back_state = loop_back_flagc_rcvd;
end else begin
next_loop_back_state = loop_back_idle;
end
end
loop_back_flagc_rcvd:begin
next_loop_back_state = loop_back_wait_flagd;
end
loop_back_wait_flagd:begin
if(i_gpif_out_ch1_rdy_d == 1'b1)begin
next_loop_back_state = loop_back_read;
end else begin
next_loop_back_state = loop_back_wait_flagd;
end
end
loop_back_read :begin
if(i_gpif_out_ch1_rdy_d == 1'b0)begin
next_loop_back_state = loop_back_read_rd_and_oe_delay;
end else begin
next_loop_back_state = loop_back_read;
end
end
loop_back_read_rd_and_oe_delay : begin
if(rd_oe_delay_cnt == 0)begin
next_loop_back_state = loop_back_read_oe_delay;
end else begin
next_loop_back_state = loop_back_read_rd_and_oe_delay;
end
end
loop_back_read_oe_delay : begin
if(oe_delay_cnt == 0)begin
next_loop_back_state = loop_back_wait_flaga;
end else begin
next_loop_back_state = loop_back_read_oe_delay;
end
end
loop_back_wait_flaga :begin
if (i_gpif_in_ch0_rdy_d == 1'b1)begin
next_loop_back_state = loop_back_wait_flagb;
end else begin
next_loop_back_state = loop_back_wait_flaga;
end
end
loop_back_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_loop_back_state = loop_back_write;
end else begin
next_loop_back_state = loop_back_wait_flagb;
end
end
loop_back_write:begin
if(i_gpif_out_ch0_rdy_d == 1'b0)begin
next_loop_back_state = loop_back_write_wr_delay;
end else begin
next_loop_back_state = loop_back_write;
end
end
loop_back_write_wr_delay:begin
next_loop_back_state = loop_back_flush_fifo;
end
loop_back_flush_fifo:begin
next_loop_back_state = loop_back_idle;
end
endcase
end
///fifo instantiation for loop back mode
fifo fifo_inst(
.din(fifo_data_in)
,.write_busy(fifo_push)
,.fifo_full()
,.dout(data_out_loopback)
,.read_busy(fifo_pop)
,.fifo_empty()
,.fifo_clk(clk_100)
,.rst_n(rst_n)
,.fifo_flush(fifo_flush)
);
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Digilite ZL top-level file.
//
//------------------------------------------------------------------------------
`ifndef _ZL_TOP_V_
`define _ZL_TOP_V_
`include "zl_sys_pll.v"
`include "zl_dvb_s_core.v"
`include "zl_fifo_dc.v"
`include "zl_usb_fifo.v"
`include "zl_reset_sync.v"
module zl_top
(
input ext_clk_50,
input ext_rst_button_n,
//
input usb_fifo_rxf_n,
output usb_fifo_rd_n,
input [7:0] usb_fifo_data,
//
output dac_clk,
output dac_i,
output dac_q,
output dac_i_pre,
output dac_q_pre,
//
output [7:0] debug_led
);
wire clk_50;
wire rst_50_n;
wire clk_dac_tx;
wire sys_pll_locked;
zl_sys_pll sys_pll
(
.rst_n(ext_rst_button_n),
.clk_ref(ext_clk_50),
.clk_sys(clk_50),
.clk_sample(clk_dac_tx),
.lock(sys_pll_locked)
);
zl_reset_sync sys_reset_sync
(
.clk(clk_50),
.in_rst_n(ext_rst_button_n & sys_pll_locked),
.out_rst_n(rst_50_n)
);
// USB FIFO interface
wire usb_fifo_out_req;
wire usb_fifo_out_ack;
wire [7:0] usb_fifo_out_data;
zl_usb_fifo usb_fifo
(
.clk(clk_50),
.rst_n(rst_50_n),
//
.usb_fifo_rxf_n(usb_fifo_rxf_n),
.usb_fifo_rd_n(usb_fifo_rd_n),
.usb_fifo_data(usb_fifo_data),
//
.usb_fifo_out_req(usb_fifo_out_req),
.usb_fifo_out_ack(usb_fifo_out_ack),
.usb_fifo_out_data(usb_fifo_out_data)
);
// DVB-S core
wire core_data_out_i;
wire core_data_out_q;
wire core_data_out_req;
wire core_data_out_ack;
zl_dvb_s_core dvb_s_core
(
.clk(clk_50),
.rst_n(rst_50_n),
//
.data_in(usb_fifo_out_data),
.data_in_req(usb_fifo_out_req),
.data_in_ack(usb_fifo_out_ack),
//
.data_out_i(core_data_out_i),
.data_out_q(core_data_out_q),
.data_out_req(core_data_out_req),
.data_out_ack(core_data_out_ack)
);
// system -> sample rate clock domain crossing
wire sample_out_valid;
wire sample_out_i;
wire sample_out_q;
zl_fifo_dc #
(
.Data_width(2),
.Addr_width(2)
)
sample_fifo
(
.clk_in(clk_50),
.rst_in_n(rst_50_n),
.clk_out(clk_dac_tx),
//
.in_req(core_data_out_req),
.in_ack(core_data_out_ack),
.in_data({core_data_out_i,core_data_out_q}),
.in_full(),
.in_empty(),
.in_used(),
//
.out_req(sample_out_valid),
.out_ack(sample_out_valid),
.out_data({sample_out_i,sample_out_q}),
.out_full(),
.out_empty(),
.out_used()
);
// create 1-cycle delayed copy and assign outputs
reg sample_out_i_d1;
reg sample_out_q_d1;
always @(posedge clk_dac_tx) begin
sample_out_i_d1 <= sample_out_i;
sample_out_q_d1 <= sample_out_q;
end
assign dac_clk = ~clk_dac_tx; // (inverted to center-align clock w/ data)
assign dac_i_pre = ~sample_out_i;
assign dac_q_pre = ~sample_out_q;
assign dac_i = sample_out_i_d1;
assign dac_q = sample_out_q_d1;
// Debugging LEDs
localparam Heartbeat_period = 25000000; // 500ms @ 50 MHz
localparam Heartbeat_count_width = 25;
reg [Heartbeat_count_width-1:0] heartbeat_count;
reg heartbeat_state;
assign debug_led[7:2] = 6'b0;
assign debug_led[0] = heartbeat_state;
assign debug_led[1] = sample_out_valid;
always @(posedge clk_50 or negedge rst_50_n) begin
if(!rst_50_n) begin
heartbeat_state <= 1'b0;
heartbeat_count <= {Heartbeat_count_width{1'b0}};
end
else begin
if(heartbeat_count == Heartbeat_period-1) begin
heartbeat_count <= {Heartbeat_count_width{1'b0}};
heartbeat_state <= ~heartbeat_state;
end
else begin
heartbeat_count <= heartbeat_count + 1'b1;
end
end
end
endmodule // zl_top
`endif // _ZL_TOP_V_
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_65x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_65x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [64:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [64:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire [64:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [6:0] usedw = sub_wire1[6:0];
wire empty = sub_wire2;
wire [64:0] q = sub_wire3[64:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 65,
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_widthu = 7,
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.almost_full_value = 3,
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "65"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "65"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 65 0 INPUT NODEFVAL data[64..0]
// Retrieval info: USED_PORT: q 0 0 65 0 OUTPUT NODEFVAL q[64..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 65 0 data 0 0 65 0
// Retrieval info: CONNECT: q 0 0 65 0 @q 0 0 65 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_wave*.jpg FALSE
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
) (
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK,
input wire DI,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire EXT_ENABLE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
timestamp_core #(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER)
) i_timestamp_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK(CLK),
.DI(DI),
.TIMESTAMP_OUT(TIMESTAMP_OUT),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.EXT_ENABLE(EXT_ENABLE),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
///////////////////////////////////////////////////////////////////////////////////////////////////
// vga: Generate XVGA display signals (640 x 480 @ 60Hz)
// essentially a copy of staff xvga module with different timings
// Credits: timings from Jose's project (Fall 2011),
// general code from staff xvga module (e.g Lab 3 - pong game)
///////////////////////////////////////////////////////////////////////////////////////////////////
module vga(input vclock,
output reg [9:0] hcount, // pixel number on current line
output reg [9:0] vcount, // line number
output reg vsync,hsync,blank);
// VGA (640x480) @ 60 Hz
parameter VGA_HBLANKON = 10'd639;
parameter VGA_HSYNCON = 10'd655;
parameter VGA_HSYNCOFF = 10'd751;
parameter VGA_HRESET = 10'd799;
parameter VGA_VBLANKON = 10'd479;
parameter VGA_VSYNCON = 10'd490;
parameter VGA_VSYNCOFF = 10'd492;
parameter VGA_VRESET = 10'd523;
// horizontal: 800 pixels total
// display 640 pixels per line
reg hblank,vblank;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = (hcount == VGA_HBLANKON);
assign hsyncon = (hcount == VGA_HSYNCON);
assign hsyncoff = (hcount == VGA_HSYNCOFF);
assign hreset = (hcount == VGA_HRESET);
// vertical: 524 lines total
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == VGA_VBLANKON);
assign vsyncon = hreset & (vcount == VGA_VSYNCON);
assign vsyncoff = hreset & (vcount == VGA_VSYNCOFF);
assign vreset = hreset & (vcount == VGA_VRESET);
// sync and blanking
wire next_hblank,next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule
|
//************************************************************
// CHECKS
// ______ _ _ _______ ______ _ _ _
// / _____) | | (_______) _____) | / ) | |
// | / | |__ | |_____ | / | | / / \ \
// | | | __)| | ___)| | | |< < \ \
// | \_____| | | | |____| \_____| | \ \ _____) )
// \______)_| |_|_______)______)_| \_|______/
//
//
// Logging.
//
// Allow you to see, in time, when values are transmitted and received.
//
//
// For this test, the number of cycles on the slowest clock should match the
// number of words transmitted plus a small constant.
//
`include "bsg_defines.v"
module test_bsg_comm_link_checker #(parameter `BSG_INV_PARAM(channel_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(ring_bytes_p)
, parameter `BSG_INV_PARAM(check_bytes_p)
, parameter `BSG_INV_PARAM(verbose_p)
, parameter `BSG_INV_PARAM(iterations_p)
, parameter `BSG_INV_PARAM(core_0_period_p)
, parameter `BSG_INV_PARAM(core_1_period_p)
, parameter `BSG_INV_PARAM(io_master_0_period_p)
, parameter `BSG_INV_PARAM(io_master_1_period_p)
, parameter chip_num_p=0
, parameter node_num_p=0
, parameter `BSG_INV_PARAM(cycle_counter_width_p)
, parameter skip_checks_p=0
)
(input clk
, input valid_in
, input ready_in
, input yumi_out
, input [ring_bytes_p*channel_width_p-1:0] data_in
, input [ring_bytes_p*channel_width_p-1:0] data_out
, input async_reset
, input slave_reset_tline
// , input [num_channels_p-1:0] io_clk_tline
, input [num_channels_p-1:0] io_valid_tline
, input [channel_width_p-1:0] io_data_tline [num_channels_p-1:0]
// , input [num_channels_p-1:0] token_clk_tline
, input [cycle_counter_width_p-1:0] core_ctr[1:0]
, input [cycle_counter_width_p-1:0] io_ctr [1:0]
, output done_o
);
localparam channel_verbose_p = 1'b0;
// non-synthesizeable; testing only
logic [5:0] top_bits = 0;
logic [31:0] words_received_r ;
wire [check_bytes_p*channel_width_p-1:0] data_in_check;
genvar j;
always_ff @(negedge clk)
if (async_reset)
words_received_r <= 0;
else
words_received_r <= words_received_r + (valid_in & ready_in);
logic done_r;
assign done_o = done_r;
test_bsg_data_gen #(.channel_width_p(channel_width_p)
,.num_channels_p(check_bytes_p)
) tbdg_receive
(.clk_i(clk )
,.reset_i(async_reset )
,.yumi_i (ready_in & valid_in)
,.o (data_in_check)
);
always_ff @(negedge clk)
begin
if (valid_in & ready_in)
begin
if (verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1]
, " ## chip %1d node %1d recv %-d, %x"
, chip_num_p, node_num_p, words_received_r, data_in);
if (!skip_checks_p)
assert (data_in_check == data_in[check_bytes_p*channel_width_p-1:0])
else
begin
$error("## transmission error %x, %x, difference = %x"
, data_in_check, data_in, data_in_check ^ data_in);
// $finish();
end
// we only terminate when all nodes on core 0 have received all the words
if ((words_received_r
>=
(iterations_p << (channel_width_p-$clog2(num_channels_p)))
) & (chip_num_p == 0) & ~done_r)
begin
done_r <= 1'b1;
$display("## DONE node = %-d words = %-d CHANNEL_BITWIDTH = %-d",node_num_p,words_received_r,channel_width_p
," RING_BYTES = %-d;",ring_bytes_p
," NUM_CHAN = %-d;",num_channels_p
," C0 = %-d;",core_0_period_p
," I0 = %-d; I1 = %-d;",io_master_0_period_p
,io_master_1_period_p
," C1 = %-d;",core_1_period_p,
," (Cycles Per Word) "
, real'(core_ctr[0])
/ real'(words_received_r)
," ", real'(io_ctr [0])
/ real'(words_received_r)
," ", real'(io_ctr [1])
/ real'(words_received_r)
," ", real'(core_ctr[1])
/ real'(words_received_r)
);
end
end
if (yumi_out)
if (verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1]
, " ## chip %1d node %1d sent %x",chip_num_p, node_num_p, data_out);
if (async_reset) done_r <= 1'b0;
end // always_ff @
`ifdef BSG_IP_CORES_UNIT_TEST
`define TEST_BSG_COMM_LINK_CHECKER_PREFIX core[chip_num_p].
`else
`define TEST_BSG_COMM_LINK_CHECKER_PREFIX
`endif
// avoid redundant printing of channel info
if (node_num_p == 0)
for (j = 0; j < num_channels_p; j=j+1)
begin
// in parent
always @(slave_reset_tline or io_valid_tline[j] or io_data_tline[j]
or `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.pos_credit_ctr.r_free_credits_r
or `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.neg_credit_ctr.r_free_credits_r
)
if (verbose_p)
begin
if (channel_verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1],
" ## chip %1d channel %1d", chip_num_p, j, " (p,n)=(%2d %2d)"
, `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.pos_credit_ctr.r_free_credits_r
, `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.neg_credit_ctr.r_free_credits_r
, " ## io xmit %1d,%x"
, io_valid_tline[j],io_data_tline[j]
);
end
end // for (j = 0; j < num_channels_p; j=j+1)
endmodule
`BSG_ABSTRACT_MODULE(test_bsg_comm_link_checker)
|
module cia_int
(
input clk, // clock
input clk7_en,
input wr, // write enable
input reset, // reset
input icrs, // intterupt control register select
input ta, // ta (set TA bit in ICR register)
input tb, // tb (set TB bit in ICR register)
input alrm, // alrm (set ALRM bit ICR register)
input flag, // flag (set FLG bit in ICR register)
input ser, // ser (set SP bit in ICR register)
input [7:0] data_in, // bus data in
output [7:0] data_out, // bus data out
output irq // intterupt out
);
reg [4:0] icr = 5'd0; // interrupt register
reg [4:0] icrmask = 5'd0; // interrupt mask register
// reading of interrupt data register
assign data_out[7:0] = icrs && !wr ? {irq,2'b00,icr[4:0]} : 8'b0000_0000;
// writing of interrupt mask register
always @(posedge clk)
if (clk7_en) begin
if (reset)
icrmask[4:0] <= 5'b0_0000;
else if (icrs && wr)
begin
if (data_in[7])
icrmask[4:0] <= icrmask[4:0] | data_in[4:0];
else
icrmask[4:0] <= icrmask[4:0] & (~data_in[4:0]);
end
end
// register new interrupts and/or changes by user reads
always @(posedge clk)
if (clk7_en) begin
if (reset)// synchronous reset
icr[4:0] <= 5'b0_0000;
else if (icrs && !wr)
begin// clear latched intterupts on read
icr[0] <= ta; // timer a
icr[1] <= tb; // timer b
icr[2] <= alrm; // timer tod
icr[3] <= ser; // external ser input
icr[4] <= flag; // external flag input
end
else
begin// keep latched intterupts
icr[0] <= icr[0] | ta; // timer a
icr[1] <= icr[1] | tb; // timer b
icr[2] <= icr[2] | alrm; // timer tod
icr[3] <= icr[3] | ser; // external ser input
icr[4] <= icr[4] | flag; // external flag input
end
end
// generate irq output (interrupt request)
assign irq = (icrmask[0] & icr[0])
| (icrmask[1] & icr[1])
| (icrmask[2] & icr[2])
| (icrmask[3] & icr[3])
| (icrmask[4] & icr[4]);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file read operands mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Mux for two register file read operands. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_operandmuxes.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:05 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_operandmuxes(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] ex_forw;
input [width-1:0] wb_forw;
input [width-1:0] simm;
input [`OR1200_SEL_WIDTH-1:0] sel_a;
input [`OR1200_SEL_WIDTH-1:0] sel_b;
output [width-1:0] operand_a;
output [width-1:0] operand_b;
output [width-1:0] muxed_b;
//
// Internal wires and regs
//
reg [width-1:0] operand_a;
reg [width-1:0] operand_b;
reg [width-1:0] muxed_a;
reg [width-1:0] muxed_b;
reg saved_a;
reg saved_b;
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_a <= #1 32'd0;
saved_a <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
saved_a <= #1 1'b1;
end else if (!ex_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
end else if (!ex_freeze && !id_freeze)
saved_a <= #1 1'b0;
end
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_b <= #1 32'd0;
saved_b <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
saved_b <= #1 1'b1;
end else if (!ex_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
end else if (!ex_freeze && !id_freeze)
saved_b <= #1 1'b0;
end
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_a = wb_forw;
default:
muxed_a = rf_dataa;
endcase
end
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
`OR1200_SEL_EX_FORW:
muxed_b = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_b = wb_forw;
default:
muxed_b = rf_datab;
endcase
end
endmodule
|
`timescale 1ns/10ps
module ssram
(
// global
input wire clk_i,
input wire clk_en_i,
input wire reset_i,
//
output wire treqready_o,
input wire treqvalid_i,
input wire treqdvalid_i,
input wire [31:0] treqaddr_i,
input wire [31:0] treqdata_i,
input wire trspready_i,
output reg trspvalid_o,
output reg [31:0] trspdata_o
);
//--------------------------------------------------------------
parameter C_SSRAM_SZBX = 22;
parameter C_SSRAM_SZB = 2**C_SSRAM_SZBX;
//
parameter C_VIRTUAL_UART = 32'h80000000;
//
reg [7:0] mem[0:C_SSRAM_SZB-1];
wire [C_SSRAM_SZBX-1:0] reqaddr;
//--------------------------------------------------------------
assign treqready_o = treqvalid_i;
initial
begin
$display("********************************************************");
$display("SSRAM Size = %0d Ki Bytes.", 2**(C_SSRAM_SZBX-10));
$display("\nWrites to address 0x%08X will be interpreted as\nASCII characters and will be printed to the console.", C_VIRTUAL_UART);
$display("\nWrites to address 0xFFFFFFFC will be end the simulation.");
$display("********************************************************");
$readmemh("mem.hex", mem);
end
//
//
assign reqaddr = treqaddr_i[C_SSRAM_SZBX-1:0];
always @ (posedge clk_i or posedge reset_i)
begin
if (reset_i) begin
trspvalid_o <= 1'b0;
trspdata_o <= 32'hbaadf00d;
end else if (clk_en_i) begin
if (treqvalid_i) begin
trspvalid_o <= 1'b0;
if (treqdvalid_i) begin
if (treqaddr_i == C_VIRTUAL_UART) begin
$write("%c", treqdata_i[7:0]);
$fflush();
end else if (treqaddr_i == 32'hfffffffc) begin
$display();
$display();
$display("(%0tns) Program wrote to address 0xFFFFFFFC => End of test!", $time/100.0);
$display("******************** SIMULATION END ********************");
$finish();
end else if (treqaddr_i == reqaddr) begin
mem[reqaddr+3] <= treqdata_i[31:24];
mem[reqaddr+2] <= treqdata_i[23:16];
mem[reqaddr+1] <= treqdata_i[15: 8];
mem[reqaddr+0] <= treqdata_i[ 7: 0];
`ifdef TESTBENCH_DBG_MSG
$display("SSRAM Write: ADDR=0x%08X, DATA=0x%08X", treqaddr_i, treqdata_i);
`endif
end else begin
$display("FATAL ERROR (%0t): Memory Write Out Of Range! Address 0x%08X", $time, treqaddr_i);
$fatal();
end
end else begin
trspvalid_o <= 1'b1;
if (treqaddr_i == reqaddr) begin
trspdata_o <= { mem[reqaddr+3], mem[reqaddr+2], mem[reqaddr+1], mem[reqaddr+0] };
`ifdef TESTBENCH_DBG_MSG
$display("SSRAM Read : ADDR=0x%08X, DATA=0x%08X", treqaddr_i, { mem[reqaddr+3], mem[reqaddr+2], mem[reqaddr+1], mem[reqaddr+0] });
`endif
end else begin
$display("FATAL ERROR (%0t): Memory Read Out Of Range! Address 0x%08X", $time, treqaddr_i);
$fatal();
end
end
end else begin
trspvalid_o <= 1'b0;
trspdata_o <= 32'hbaadf00d;
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9144 (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dma interface
dac_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_valid_2,
dac_enable_2,
dac_ddata_2,
dac_valid_3,
dac_enable_3,
dac_ddata_3,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_QUAD_DUAL_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data;
// dma interface
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
output dac_valid_2;
output dac_enable_2;
input [63:0] dac_ddata_2;
output dac_valid_3;
output dac_enable_3;
input [63:0] dac_ddata_3;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [255:0] tx_data_s;
wire [ 15:0] dac_data_0_0_s;
wire [ 15:0] dac_data_0_1_s;
wire [ 15:0] dac_data_0_2_s;
wire [ 15:0] dac_data_0_3_s;
wire [ 15:0] dac_data_1_0_s;
wire [ 15:0] dac_data_1_1_s;
wire [ 15:0] dac_data_1_2_s;
wire [ 15:0] dac_data_1_3_s;
wire [ 15:0] dac_data_2_0_s;
wire [ 15:0] dac_data_2_1_s;
wire [ 15:0] dac_data_2_2_s;
wire [ 15:0] dac_data_2_3_s;
wire [ 15:0] dac_data_3_0_s;
wire [ 15:0] dac_data_3_1_s;
wire [ 15:0] dac_data_3_2_s;
wire [ 15:0] dac_data_3_3_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// dual/quad cores
assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
// device interface
axi_ad9144_if i_if (
.tx_clk (tx_clk),
.tx_data (tx_data_s),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
.dac_data_0_1 (dac_data_0_1_s),
.dac_data_0_2 (dac_data_0_2_s),
.dac_data_0_3 (dac_data_0_3_s),
.dac_data_1_0 (dac_data_1_0_s),
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s),
.dac_data_2_0 (dac_data_2_0_s),
.dac_data_2_1 (dac_data_2_1_s),
.dac_data_2_2 (dac_data_2_2_s),
.dac_data_2_3 (dac_data_2_3_s),
.dac_data_3_0 (dac_data_3_0_s),
.dac_data_3_1 (dac_data_3_1_s),
.dac_data_3_2 (dac_data_3_2_s),
.dac_data_3_3 (dac_data_3_3_s));
// core
axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
.dac_data_0_1 (dac_data_0_1_s),
.dac_data_0_2 (dac_data_0_2_s),
.dac_data_0_3 (dac_data_0_3_s),
.dac_data_1_0 (dac_data_1_0_s),
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s),
.dac_data_2_0 (dac_data_2_0_s),
.dac_data_2_1 (dac_data_2_1_s),
.dac_data_2_2 (dac_data_2_2_s),
.dac_data_2_3 (dac_data_2_3_s),
.dac_data_3_0 (dac_data_3_0_s),
.dac_data_3_1 (dac_data_3_1_s),
.dac_data_3_2 (dac_data_3_2_s),
.dac_data_3_3 (dac_data_3_3_s),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_valid_2 (dac_valid_2),
.dac_enable_2 (dac_enable_2),
.dac_ddata_2 (dac_ddata_2),
.dac_valid_3 (dac_valid_3),
.dac_enable_3 (dac_enable_3),
.dac_ddata_3 (dac_ddata_3),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_6_V
`define SKY130_FD_SC_HD__INV_6_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_6 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_6 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_6_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_BEHAVIORAL_V
|
//==================================================================================================
// Filename : Mux_3x1_b.v
// Created On : 2016-10-03 16:53:16
// Last Modified : 2016-10-30 20:31:25
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Mux_3x1_bv2 #(parameter W=32)
(
//Input Signals
input wire [1:0] select,
input wire [W-1:0] ch_0,
input wire [W-1:0] ch_1,
input wire [W-1:0] ch_2,
//Output Signals
output reg [W-1:0] data_out
);
always @*
begin
case(select)
2'b00: data_out <= {W{1'b0}};
2'b01: data_out <= ch_0;
2'b10: data_out <= ch_1;
2'b11: data_out <= ch_2;
// default : data_out <= ch_0;
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig (
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// user interface signals
input [26:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [127:0] app_wdf_data,
input app_wdf_end,
input [15:0] app_wdf_mask,
input app_wdf_wren,
output [127:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
mig_mig u_mig_mig (
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive STRATIXII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive STRATIXII_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive STRATIXII_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module stratixii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
STRATIXII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** stratixii_mux21
module stratixii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** stratixii_mux41
module stratixii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** stratixii_and1
module stratixii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** stratixii_and16
module stratixii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** stratixii_bmux21
module stratixii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** stratixii_b17mux21
module stratixii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** stratixii_nmux21
module stratixii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** stratixii_b5mux21
module stratixii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//--------------------------------------------------------------------------
// Module Name : stratixii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : stratixii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : stratixii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module stratixii_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "stratixii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
parameter port_a_byte_size = 0;
parameter port_a_disable_ce_on_input_registers = "off";
parameter port_a_disable_ce_on_output_registers = "off";
parameter port_b_byte_size = 0;
parameter port_b_disable_ce_on_input_registers = "off";
parameter port_b_disable_ce_on_output_registers = "off";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbrewe_int;
assign portbrewe_int = portbrewe;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a, active_b;
wire active_a_in, active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0_int;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0_int : clr1_int);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0_int;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0_int : clr1_int);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0_int;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0_int : clr1_int);
assign active_a_in = ena0_int || (port_a_disable_ce_on_input_registers == "on");
assign active_b_in = ((port_b_read_enable_write_enable_clock == "clock0") ? ena0_int : ena1_int) ||
(port_b_disable_ce_on_input_registers == "on");
// Store clock enable value for SEAB/MEAB
// port A active
stratixii_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
stratixii_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
stratixii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
stratixii_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
stratixii_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
stratixii_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
stratixii_ram_register rewe_b_register (
.d(portbrewe_int),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
stratixii_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
stratixii_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
stratixii_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
stratixii_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
stratixii_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
stratixii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),
.cycle()
);
stratixii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),
.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime)
read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
stratixii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
stratixii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
ena0_int || (port_a_disable_ce_on_output_registers == "on") :
ena1_int || (port_a_disable_ce_on_output_registers == "on") ;
stratixii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
ena0_int || (port_b_disable_ce_on_output_registers == "on") :
ena1_int || (port_b_disable_ce_on_output_registers == "on") ;
stratixii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // stratixii_ram_block
//--------------------------------------------------------------------
//
// Module Name : stratixii_jtag
//
// Description : StratixII JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "stratixii_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : stratixii_crcblock
//
// Description : StratixII CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "stratixii_crcblock";
endmodule
//---------------------------------------------------------------------
//
// Module Name : stratixii_asmiblock
//
// Description : StratixII ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "stratixii_asmiblock";
endmodule // stratixii_asmiblock
//------------------------------------------------------------------
//
// Module Name : stratixii_lcell_ff
//
// Description : StratixII LCELL_FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_lcell_ff (
datain,
clk,
aclr,
aload,
sclr,
sload,
adatasdata,
ena,
devclrn,
devpor,
regout
);
parameter x_on_violation = "on";
parameter lpm_type = "stratixii_lcell_ff";
input datain;
input clk;
input aclr;
input aload;
input sclr;
input sload;
input adatasdata;
input ena;
input devclrn;
input devpor;
output regout;
tri1 devclrn;
tri1 devpor;
reg regout_tmp;
wire reset;
reg datain_viol;
reg sclr_viol;
reg sload_viol;
reg adatasdata_viol;
reg ena_viol;
reg violation;
wire wviolation;
reg clk_last_value;
reg ix_on_violation;
wire datain_in;
wire clk_in;
wire aclr_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire adatasdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf(wviolation, violation);
buf (datain_in, datain);
buf (clk_in, clk);
buf (aclr_in, aclr);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (adatasdata_in, adatasdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && (!aclr_in) && (ena_in);
assign nosloadsclr = reset && (!sload_in && !sclr_in &&!aload_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, adatasdata, 0, 0, adatasdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: regout_tmp)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: regout_tmp)) = (0, 0) ;
(adatasdata => regout) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
regout_tmp = 'b0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (datain_viol or sclr_viol or sload_viol or ena_viol or adatasdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (adatasdata_in or aclr_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
regout_tmp <= 'b0;
else if (devclrn == 'b0)
regout_tmp <= 'b0;
else if (aclr_in == 'b1)
regout_tmp <= 'b0;
else if (aload_in == 'b1)
regout_tmp <= adatasdata_in;
end
always @ (clk_in or posedge aclr_in or posedge aload_in or
devclrn or devpor or posedge wviolation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
regout_tmp <= 1'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || aclr_in === 'b1)
regout_tmp <= 'b0;
else if (aload_in === 'b1)
regout_tmp <= adatasdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
regout_tmp <= 'b0 ;
else if (sload_in === 'b1)
regout_tmp <= adatasdata_in;
else
regout_tmp <= datain_in;
end
end
clk_last_value = clk_in;
end
and (regout, regout_tmp, 'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : stratixii_lcell_comb
//
// Description : StratixII LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_lcell_comb (
dataa,
datab,
datac,
datad,
datae,
dataf,
datag,
cin,
sharein,
combout,
sumout,
cout,
shareout
);
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
input datag;
input cin;
input sharein;
output combout;
output sumout;
output cout;
output shareout;
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter shared_arith = "off";
parameter extended_lut = "off";
parameter lpm_type = "stratixii_lcell_comb";
// sub masks
wire [15:0] f0_mask;
wire [15:0] f1_mask;
wire [15:0] f2_mask;
wire [15:0] f3_mask;
// sub lut outputs
reg f0_out;
reg f1_out;
reg f2_out;
reg f3_out;
// mux output for extended mode
reg g0_out;
reg g1_out;
// either datac or datag
reg f2_input3;
// F2 output using dataf
reg f2_f;
// second input to the adder
reg adder_input2;
// tmp output variables
reg combout_tmp;
reg sumout_tmp;
reg cout_tmp;
// integer representations for string parameters
reg ishared_arith;
reg iextended_lut;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
// 5-input LUT function
function lut5;
input [31:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
reg e0_lut;
reg e1_lut;
reg [15:0] e0_mask;
reg [31:16] e1_mask;
begin
e0_mask = mask[15:0];
e1_mask = mask[31:16];
begin
e0_lut = lut4(e0_mask, dataa, datab, datac, datad);
e1_lut = lut4(e1_mask, dataa, datab, datac, datad);
if (datae === 1'bX) // X propogation
begin
if (e0_lut == e1_lut)
begin
lut5 = e0_lut;
end
else
begin
lut5 = 1'bX;
end
end
else
begin
lut5 = (datae == 1'b1) ? e1_lut : e0_lut;
end
end
end
endfunction
// 6-input LUT function
function lut6;
input [63:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
reg f0_lut;
reg f1_lut;
reg [31:0] f0_mask;
reg [63:32] f1_mask ;
begin
f0_mask = mask[31:0];
f1_mask = mask[63:32];
begin
lut6 = mask[{dataf, datae, datad, datac, datab, dataa}];
if (lut6 === 1'bX)
begin
f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae);
f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae);
if (dataf === 1'bX) // X propogation
begin
if (f0_lut == f1_lut)
begin
lut6 = f0_lut;
end
else
begin
lut6 = 1'bX;
end
end
else
begin
lut6 = (dataf == 1'b1) ? f1_lut : f0_lut;
end
end
end
end
endfunction
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire datae_in;
wire dataf_in;
wire datag_in;
wire cin_in;
wire sharein_in;
buf(dataa_in, dataa);
buf(datab_in, datab);
buf(datac_in, datac);
buf(datad_in, datad);
buf(datae_in, datae);
buf(dataf_in, dataf);
buf(datag_in, datag);
buf(cin_in, cin);
buf(sharein_in, sharein);
specify
(dataa => combout) = (0, 0);
(datab => combout) = (0, 0);
(datac => combout) = (0, 0);
(datad => combout) = (0, 0);
(datae => combout) = (0, 0);
(dataf => combout) = (0, 0);
(datag => combout) = (0, 0);
(dataa => sumout) = (0, 0);
(datab => sumout) = (0, 0);
(datac => sumout) = (0, 0);
(datad => sumout) = (0, 0);
(dataf => sumout) = (0, 0);
(cin => sumout) = (0, 0);
(sharein => sumout) = (0, 0);
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(datac => cout) = (0, 0);
(datad => cout) = (0, 0);
(dataf => cout) = (0, 0);
(cin => cout) = (0, 0);
(sharein => cout) = (0, 0);
(dataa => shareout) = (0, 0);
(datab => shareout) = (0, 0);
(datac => shareout) = (0, 0);
(datad => shareout) = (0, 0);
endspecify
initial
begin
if (shared_arith == "on")
ishared_arith = 1;
else
ishared_arith = 0;
if (extended_lut == "on")
iextended_lut = 1;
else
iextended_lut = 0;
f0_out = 1'b0;
f1_out = 1'b0;
f2_out = 1'b0;
f3_out = 1'b0;
g0_out = 1'b0;
g1_out = 1'b0;
f2_input3 = 1'b0;
adder_input2 = 1'b0;
f2_f = 1'b0;
combout_tmp = 1'b0;
sumout_tmp = 1'b0;
cout_tmp = 1'b0;
end
// sub masks and outputs
assign f0_mask = lut_mask[15:0];
assign f1_mask = lut_mask[31:16];
assign f2_mask = lut_mask[47:32];
assign f3_mask = lut_mask[63:48];
always @(datag_in or dataf_in or datae_in or datad_in or datac_in or
datab_in or dataa_in or cin_in or sharein_in)
begin
// check for extended LUT mode
if (iextended_lut == 1)
f2_input3 = datag_in;
else
f2_input3 = datac_in;
f0_out = lut4(f0_mask, dataa_in, datab_in, datac_in, datad_in);
f1_out = lut4(f1_mask, dataa_in, datab_in, f2_input3, datad_in);
f2_out = lut4(f2_mask, dataa_in, datab_in, datac_in, datad_in);
f3_out = lut4(f3_mask, dataa_in, datab_in, f2_input3, datad_in);
// combout is the 6-input LUT
if (iextended_lut == 1)
begin
if (datae_in == 1'b0)
begin
g0_out = f0_out;
g1_out = f2_out;
end
else if (datae_in == 1'b1)
begin
g0_out = f1_out;
g1_out = f3_out;
end
else
begin
if (f0_out == f1_out)
g0_out = f0_out;
else
g0_out = 1'bX;
if (f2_out == f3_out)
g1_out = f2_out;
else
g1_out = 1'bX;
end
if (dataf_in == 1'b0)
combout_tmp = g0_out;
else if ((dataf_in == 1'b1) || (g0_out == g1_out))
combout_tmp = g1_out;
else
combout_tmp = 1'bX;
end
else
combout_tmp = lut6(lut_mask, dataa_in, datab_in, datac_in,
datad_in, datae_in, dataf_in);
// check for shareed arithmetic mode
if (ishared_arith == 1)
adder_input2 = sharein_in;
else
begin
f2_f = lut4(f2_mask, dataa_in, datab_in, datac_in, dataf_in);
adder_input2 = !f2_f;
end
// sumout & cout
sumout_tmp = cin_in ^ f0_out ^ adder_input2;
cout_tmp = (cin_in & f0_out) | (cin_in & adder_input2) |
(f0_out & adder_input2);
end
and (combout, combout_tmp, 1'b1);
and (sumout, sumout_tmp, 1'b1);
and (cout, cout_tmp, 1'b1);
and (shareout, f2_out, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIXII_ASYNCH_IO
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_asynch_io (
datain,
oe,
regin,
ddioregin,
padio,
delayctrlin,
offsetctrlin,
dqsupdateen,
dqsbusout,
combout,
regout,
ddioregout
);
input datain;
input oe;
input regin;
input ddioregin;
input [5:0] delayctrlin;
input [5:0] offsetctrlin;
input dqsupdateen;
output dqsbusout;
output combout;
output regout;
output ddioregout;
inout padio;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter dqs_input_frequency = "10000 ps";
parameter dqs_out_mode = "none";
parameter dqs_delay_buffer_mode = "low";
parameter dqs_phase_shift = 0;
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
parameter dqs_edge_detect_enable = "false";
parameter sim_dqs_intrinsic_delay = 0;
parameter sim_dqs_delay_increment = 0;
parameter sim_dqs_offset_increment = 0;
parameter gated_dqs = "false";
reg buf_control;
reg prev_value;
reg tmp_padio;
tri padio_tmp;
reg tmp_combout;
reg combout_tmp;
reg tmp_dqsbusout;
wire dqsbusout_tmp;
reg [1:0] iop_mode;
integer dqs_delay;
integer tmp_delayctrl;
integer tmp_offsetctrl;
wire dqs_ctrl_latches_ena;
reg para_dqs_ctrl_latches_enable;
reg para_dqs_offsetctrl_enable;
reg para_dqs_edge_detect_enable;
wire [5:0] delayctrlin_in;
wire [5:0] offsetctrlin_in;
wire datain_in;
wire oe_in;
wire dqsupdateen_in;
wire delayctrlin_in0;
wire delayctrlin_in1;
wire delayctrlin_in2;
wire delayctrlin_in3;
wire delayctrlin_in4;
wire delayctrlin_in5;
wire offsetctrlin_in0;
wire offsetctrlin_in1;
wire offsetctrlin_in2;
wire offsetctrlin_in3;
wire offsetctrlin_in4;
wire offsetctrlin_in5;
buf(datain_in, datain);
buf(oe_in, oe);
buf(dqsupdateen_in, dqsupdateen);
buf(delayctrlin_in0, delayctrlin[0]);
buf(delayctrlin_in1, delayctrlin[1]);
buf(delayctrlin_in2, delayctrlin[2]);
buf(delayctrlin_in3, delayctrlin[3]);
buf(delayctrlin_in4, delayctrlin[4]);
buf(delayctrlin_in5, delayctrlin[5]);
buf(offsetctrlin_in0, offsetctrlin[0]);
buf(offsetctrlin_in1, offsetctrlin[1]);
buf(offsetctrlin_in2, offsetctrlin[2]);
buf(offsetctrlin_in3, offsetctrlin[3]);
buf(offsetctrlin_in4, offsetctrlin[4]);
buf(offsetctrlin_in5, offsetctrlin[5]);
assign delayctrlin_in = {delayctrlin_in5, delayctrlin_in4,
delayctrlin_in3, delayctrlin_in2,
delayctrlin_in1, delayctrlin_in0};
assign offsetctrlin_in = {offsetctrlin_in5, offsetctrlin_in4,
offsetctrlin_in3, offsetctrlin_in2,
offsetctrlin_in1, offsetctrlin_in0};
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
specify
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(ddioregin => ddioregout) = (0, 0);
(regin => regout) = (0, 0);
(padio => dqsbusout) = (0, 0);
(regin => dqsbusout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
if (operation_mode == "input")
iop_mode = 0;
else if (operation_mode == "output")
iop_mode = 1;
else if (operation_mode == "bidir")
iop_mode = 2;
else
begin
$display ("Error: Invalid operation_mode specified\n");
$display ("Time: %0t Instance: %m", $time);
iop_mode = 3;
end
dqs_delay = 0;
tmp_delayctrl = 0;
tmp_offsetctrl = 0;
para_dqs_ctrl_latches_enable = dqs_ctrl_latches_enable == "true" ? 1'b1 : 1'b0;
para_dqs_offsetctrl_enable = dqs_offsetctrl_enable == "true" ? 1'b1 : 1'b0;
para_dqs_edge_detect_enable = dqs_edge_detect_enable == "true" ? 1'b1 : 1'b0;
end
assign dqs_ctrl_latches_ena = dqs_ctrl_latches_enable == "false" ? 1'b1 :
dqs_edge_detect_enable == "false" ? dqsupdateen_in :
(~(combout_tmp ^ tmp_dqsbusout) & dqsupdateen_in);
always @(delayctrlin_in or offsetctrlin_in or dqs_ctrl_latches_ena)
begin
tmp_delayctrl = (dqs_delay_buffer_mode == "high" && delayctrlin_in[5] == 1'b1) ? 31 : delayctrlin_in;
tmp_offsetctrl = (para_dqs_offsetctrl_enable == 1'b0) ? 0 :
(dqs_delay_buffer_mode == "high" && offsetctrlin_in[5] == 1'b1) ? 31 : offsetctrlin_in;
if (dqs_ctrl_latches_ena === 1'b1)
dqs_delay = sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
if (dqs_delay_buffer_mode == "high" && delayctrlin_in[5] == 1'b1)
begin
$display($time, " Warning: delayctrlin of DQS I/O instannce %m exceeds a 5-bit range in high-frequency mode.");
end
if (dqs_delay_buffer_mode == "high" && offsetctrlin_in[5] == 1'b1)
begin
$display($time, " Warning: offsetctrlin of DQS I/O instannce %m exceeds a 5-bit range in high-frequency mode.");
end
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if (iop_mode == 0)
begin
if (padio == 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if (iop_mode == 1 || iop_mode == 2) // output or bidir
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if (iop_mode == 2) // bidir
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (iop_mode == 2) // bidir
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if (iop_mode == 1) // output
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if (iop_mode == 0) // input
begin
tmp_combout = padio;
end
else if (iop_mode == 1 || iop_mode == 2) // output or bidir
begin
if (iop_mode == 2) // bidir
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in stratixii io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
combout_tmp <= tmp_combout;
tmp_dqsbusout <= #(dqs_delay) tmp_combout;
end
assign dqsbusout_tmp = gated_dqs == "true" ? (tmp_dqsbusout & regin) : tmp_dqsbusout;
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, combout_tmp, 'b0);
pmos (dqsbusout, dqsbusout_tmp, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
and (ddioregout, ddioregin, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIXII_IO_REGISTER
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_io_register (
clk,
datain,
ena,
sreset,
areset,
devclrn,
devpor,
regout
);
parameter async_reset = 1'bx;
parameter sync_reset = "none";
parameter power_up = "low";
input clk;
input ena;
input datain;
input areset;
input sreset;
input devclrn;
input devpor ;
output regout;
reg iregout;
wire reset;
wire is_areset_clear;
wire is_areset_preset;
reg datain_viol;
reg sreset_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
wire w_violation;
wire clk_in;
wire idatain;
wire iareset;
wire isreset;
wire iena;
buf (clk_in, clk);
buf (idatain, datain);
buf (iareset, areset);
buf (isreset, sreset);
buf (iena, ena);
buf(w_violation, violation);
assign reset = devpor && devclrn && !(iareset && async_reset != 1'bx) && (iena);
assign is_areset_clear = (async_reset == 1'b0)?1'b1:1'b0;
assign is_areset_preset = (async_reset == 1'b1)?1'b1:1'b0;
specify
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sreset, 0, 0, sreset_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
if (is_areset_clear == 1'b1)
(posedge areset => (regout +: 1'b0)) = (0,0);
if ( is_areset_preset == 1'b1)
(posedge areset => (regout +: 1'b1)) = (0,0);
endspecify
initial
begin
violation = 0;
if (power_up == "low")
iregout <= 'b0;
else if (power_up == "high")
iregout <= 'b1;
end
always @ (datain_viol or sreset_viol or ena_viol)
begin
violation = 1;
end
always @ (clk_in or posedge iareset or negedge devclrn or negedge devpor or posedge w_violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout <= 1'bx;
end
else if (devpor == 'b0)
begin
if (power_up == "low")
iregout <= 'b0;
else if (power_up == "high")
iregout <= 'b1;
end
else if (devclrn == 'b0)
iregout <= 'b0;
else if (async_reset == "clear" && iareset == 'b1)
iregout <= 'b0 ;
else if (async_reset == "preset" && iareset == 'b1 )
iregout <= 'b1;
else if (iena == 'b1 && clk_in == 'b1 && clk_last_value == 'b0)
begin
if (sync_reset == "clear" && isreset == 'b1)
iregout <= 'b0 ;
else if (sync_reset == "preset" && isreset == 'b1)
iregout <= 'b1;
else
iregout <= idatain ;
end
clk_last_value = clk_in;
end
and (regout, iregout, 'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIXII_IO_LATCH
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_io_latch (
clk,
datain,
ena,
sreset,
areset,
devclrn,
devpor,
regout
);
parameter async_reset = 1'bx;
parameter sync_reset = "none";
parameter power_up = "low";
input clk;
input ena;
input datain;
input areset;
input sreset;
input devclrn;
input devpor ;
output regout;
reg iregout;
wire reset;
wire is_areset_clear;
wire is_areset_preset;
reg datain_viol;
reg sreset_viol;
reg ena_viol;
reg violation;
wire w_violation;
reg clk_last_value;
wire clk_in;
wire idatain;
wire iareset;
wire isreset;
wire iena;
buf (clk_in, clk);
buf (idatain, datain);
buf (iareset, areset);
buf (isreset, sreset);
buf (iena, ena);
buf(w_violation, violation);
assign reset = devpor && devclrn && !(iareset && async_reset != 1'bx) && (iena);
assign is_areset_clear = (async_reset == 1'b0)?1'b1:1'b0;
assign is_areset_preset = (async_reset == 1'b1)?1'b1:1'b0;
specify
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sreset, 0, 0, sreset_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
if (is_areset_clear == 1'b1)
(posedge areset => (regout +: 1'b0)) = (0,0);
if ( is_areset_preset == 1'b1)
(posedge areset => (regout +: 1'b1)) = (0,0);
endspecify
initial
begin
violation = 0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @ (datain_viol or sreset_viol or ena_viol)
begin
violation = 1;
end
always @ (idatain or clk_in or posedge iareset or negedge devclrn or negedge devpor or posedge w_violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout = 1'bx;
end
else if (devpor == 'b0)
begin
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
else if (devclrn == 'b0)
iregout = 'b0;
else if (async_reset == 1'b0 && iareset == 'b1)
iregout = 'b0 ;
else if (async_reset == 1'b1 && iareset == 'b1 )
iregout = 'b1;
else if (iena == 'b1 && clk_in == 'b1)
begin
if (sync_reset == "clear" && isreset == 'b1)
iregout = 'b0 ;
else if (sync_reset == "preset" && isreset == 'b1)
iregout = 'b1;
else
iregout = idatain ;
end
clk_last_value = clk_in;
end
and (regout, iregout, 'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIXII_IO
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_io (
datain,
ddiodatain,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
ddioinclk,
delayctrlin,
offsetctrlin,
dqsupdateen,
linkin,
terminationcontrol,
devclrn,
devpor,
devoe,
padio,
combout,
regout,
ddioregout,
dqsbusout,
linkout
);
parameter operation_mode = "input";
parameter ddio_mode = "none";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_power_up = "low";
parameter output_sync_reset = "none";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_power_up = "low";
parameter oe_sync_reset = "none";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_power_up = "low";
parameter input_sync_reset = "none";
parameter extend_oe_disable = "false";
parameter dqs_input_frequency = "10000 ps";
parameter dqs_out_mode = "none";
parameter dqs_delay_buffer_mode = "low";
parameter dqs_phase_shift = 0;
parameter inclk_input = "normal";
parameter ddioinclk_input = "negated_inclk";
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
parameter dqs_edge_detect_enable = "false";
parameter gated_dqs = "false";
parameter sim_dqs_intrinsic_delay = 0;
parameter sim_dqs_delay_increment = 0;
parameter sim_dqs_offset_increment = 0;
parameter lpm_type = "stratixii_io";
input datain;
input ddiodatain;
input oe;
input outclk;
input outclkena;
input inclk;
input inclkena;
input areset;
input sreset;
input ddioinclk;
input [5:0] delayctrlin;
input [5:0] offsetctrlin;
input dqsupdateen;
input linkin;
input [13:0] terminationcontrol;
input devclrn;
input devpor;
input devoe;
inout padio;
output combout;
output regout;
output ddioregout;
output dqsbusout;
output linkout;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire oe_reg_out, oe_pulse_reg_out;
wire in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out;
wire out_reg_out, out_ddio_reg_out;
wire out_clk_ena, oe_clk_ena;
wire tmp_datain;
wire ddio_data;
wire oe_out;
wire outclk_delayed;
wire para_ddioinclk_input;
wire neg_ireg_clk;
wire para_gated_dqs;
assign para_ddioinclk_input = ddioinclk_input == "dqsb_bus" ? 1'b1 : 1'b0;
assign neg_ireg_clk = para_ddioinclk_input === 1'b1 ? !ddioinclk : inclk;
assign para_gated_dqs = gated_dqs == "true" ? 1'b1 : 1'b0;
assign out_clk_ena = (tie_off_output_clock_enable == "false") ? outclkena : 1'b1;
assign oe_clk_ena = (tie_off_oe_clock_enable == "false") ? outclkena : 1'b1;
//input register
stratixii_io_register in_reg (
.regout(in_reg_out),
.clk(inclk),
.ena(inclkena),
.datain(padio),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_reg.async_reset = input_async_reset;
defparam in_reg.sync_reset = input_sync_reset;
defparam in_reg.power_up = input_power_up;
// in_ddio0_reg
stratixii_io_register in_ddio0_reg (
.regout(in_ddio0_reg_out),
.clk(!neg_ireg_clk),
.ena (inclkena),
.datain(padio),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_ddio0_reg.async_reset = input_async_reset;
defparam in_ddio0_reg.sync_reset = input_sync_reset;
defparam in_ddio0_reg.power_up = input_power_up;
// in_ddio1_latch
stratixii_io_latch in_ddio1_reg (
.regout(in_ddio1_reg_out),
.clk(inclk),
.ena(inclkena),
.datain(in_ddio0_reg_out),
.areset(areset),
.sreset(1'b0),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_ddio1_reg.async_reset = input_async_reset;
defparam in_ddio1_reg.sync_reset = "none"; // this register has no sync_reset
defparam in_ddio1_reg.power_up = input_power_up;
// out_reg
stratixii_io_register out_reg (
.regout(out_reg_out),
.clk(outclk),
.ena(out_clk_ena),
.datain(datain),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam out_reg.async_reset = output_async_reset;
defparam out_reg.sync_reset = output_sync_reset;
defparam out_reg.power_up = output_power_up;
// out ddio reg
stratixii_io_register out_ddio_reg (
.regout(out_ddio_reg_out),
.clk(outclk),
.ena(out_clk_ena),
.datain(ddiodatain),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam out_ddio_reg.async_reset = output_async_reset;
defparam out_ddio_reg.sync_reset = output_sync_reset;
defparam out_ddio_reg.power_up = output_power_up;
// oe reg
stratixii_io_register oe_reg (
.regout (oe_reg_out),
.clk(outclk),
.ena(oe_clk_ena),
.datain(oe),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam oe_reg.async_reset = oe_async_reset;
defparam oe_reg.sync_reset = oe_sync_reset;
defparam oe_reg.power_up = oe_power_up;
// oe_pulse reg
stratixii_io_register oe_pulse_reg (
.regout(oe_pulse_reg_out),
.clk(!outclk),
.ena(oe_clk_ena),
.datain(oe_reg_out),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam oe_pulse_reg.async_reset = oe_async_reset;
defparam oe_pulse_reg.sync_reset = oe_sync_reset;
defparam oe_pulse_reg.power_up = oe_power_up;
assign oe_out = (oe_register_mode == "register") ?
(extend_oe_disable == "true" ? oe_pulse_reg_out && oe_reg_out : oe_reg_out) : oe;
stratixii_and1 sel_delaybuf (.Y(outclk_delayed), .IN1(outclk));
stratixii_mux21 ddio_data_mux (
.MO (ddio_data),
.A (out_ddio_reg_out),
.B (out_reg_out),
.S (outclk_delayed)
);
assign tmp_datain = (ddio_mode == "output" || ddio_mode == "bidir") ?
ddio_data : ((operation_mode == "output" || operation_mode == "bidir") ?
((output_register_mode == "register") ? out_reg_out : datain) : 'b0);
// timing info in case output and/or input are not registered.
stratixii_asynch_io inst1 (
.datain(tmp_datain),
.oe(oe_out),
.regin(in_reg_out),
.ddioregin(in_ddio1_reg_out),
.padio(padio),
.delayctrlin(delayctrlin),
.offsetctrlin(offsetctrlin),
.dqsupdateen(dqsupdateen),
.dqsbusout(dqsbusout),
.combout(combout),
.regout(regout),
.ddioregout(ddioregout)
);
defparam inst1.operation_mode = operation_mode;
defparam inst1.bus_hold = bus_hold;
defparam inst1.open_drain_output = open_drain_output;
defparam inst1.dqs_input_frequency = dqs_input_frequency;
defparam inst1.dqs_out_mode = dqs_out_mode;
defparam inst1.dqs_delay_buffer_mode = dqs_delay_buffer_mode;
defparam inst1.dqs_phase_shift = dqs_phase_shift;
defparam inst1.dqs_offsetctrl_enable = dqs_offsetctrl_enable;
defparam inst1.dqs_ctrl_latches_enable = dqs_ctrl_latches_enable;
defparam inst1.dqs_edge_detect_enable = dqs_edge_detect_enable;
defparam inst1.sim_dqs_intrinsic_delay = sim_dqs_intrinsic_delay;
defparam inst1.sim_dqs_delay_increment = sim_dqs_delay_increment;
defparam inst1.sim_dqs_offset_increment = sim_dqs_offset_increment;
defparam inst1.gated_dqs = gated_dqs;
endmodule
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixII_dll
//
// Description : Simulation model for StratixII DLL block
//
// Outputs : delayctrlout - current delay chain settings for DQS pin
// offsetctrlout - current delay offset setting
// dqsupdate - update enable signal for delay setting latces
// upndnout - raw output of the phase comparator
//
// Inputs : clk - reference clock matching in frequency to DQS clock
// aload - asychronous load signal for delay setting counter
// when asserted, counter is loaded with initial value
// offset - offset added/subtracted from delayctrlout
// upndnin - up/down input port for delay setting counter in
// use_updndnin mode (user control mode)
// upndninclkena - clock enable for the delaying setting counter
// addnsub - dynamically control +/- on offsetctrlout
//
// Formulae : delay (input_period) = sim_loop_intrinsic_delay +
// sim_loop_delay_increment * dllcounter;
//
// Latency : 3 (clk8 cycles) = pc + dc + dr
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_dll (
clk,
aload,
offset,
upndnin,
upndninclkena,
addnsub,
delayctrlout,
offsetctrlout,
dqsupdate,
upndnout,
devclrn,
devpor);
// GLOBAL PARAMETERS - total 15
parameter input_frequency = "10000 ps";
parameter delay_chain_length = 16;
parameter delay_buffer_mode = "low"; // consistent with dqs
parameter delayctrlout_mode = "normal";
parameter static_delay_ctrl = 0; // for test
parameter offsetctrlout_mode = "static";
parameter static_offset = "0";
parameter jitter_reduction = "false";
parameter use_upndnin = "false";
parameter use_upndninclkena = "false";
parameter sim_valid_lock = 1;
parameter sim_loop_intrinsic_delay = 1000;
parameter sim_loop_delay_increment = 100;
parameter sim_valid_lockcount = 90; // 10000 = 1000 + 100*dllcounter
parameter lpm_type = "stratixii_dll";
// INPUT PORTS
input clk;
input aload;
input [5:0] offset;
input upndnin;
input upndninclkena;
input addnsub;
input devclrn;
input devpor;
// OUTPUT PORTS
output [5:0] delayctrlout;
output [5:0] offsetctrlout;
output dqsupdate;
output upndnout;
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
wire [5:0] offset_in;
// TMP OUTPUTS
wire [5:0] delayctrl_out;
wire [5:0] offsetctrl_out;
wire dqsupdate_out;
wire upndn_out;
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction // str2int
// Const VARIABLES to represent string parameters
reg [1:0] para_delay_buffer_mode;
reg [1:0] para_delayctrlout_mode;
reg [1:0] para_offsetctrlout_mode;
integer para_static_offset;
integer para_static_delay_ctrl;
reg para_jitter_reduction;
reg para_use_upndnin;
reg para_use_upndninclkena;
// INTERNAL NETS AND VARIABLES
// for functionality - by modules
// delay and offset control out resolver
wire [5:0] dr_delayctrl_out;
wire [5:0] dr_delayctrl_int;
wire [5:0] dr_offsetctrl_out;
wire [5:0] dr_offsetctrl_int;
wire [5:0] dr_offset_in;
wire [5:0] dr_dllcount_in;
wire dr_addnsub_in;
wire dr_clk8_in;
wire dr_aload_in;
reg [5:0] dr_reg_offset;
reg [5:0] dr_reg_dllcount;
// delay chain setting counter
wire [5:0] dc_dllcount_out;
wire dc_dqsupdate_out;
wire dc_upndn_in;
wire dc_aload_in;
wire dc_upndnclkena_in;
wire dc_clk8_in;
wire dc_clk1_in;
wire dc_dlltolock_in;
reg [5:0] dc_reg_dllcount;
reg dc_reg_dlltolock_pulse;
// jitter reduction counter
wire jc_upndn_out;
wire jc_upndnclkena_out;
wire jc_clk8_in;
wire jc_upndn_in;
wire jc_aload_in;
integer jc_count;
reg jc_reg_upndn;
reg jc_reg_upndnclkena;
// phase comparator
wire pc_upndn_out;
wire [5:0] pc_dllcount_in;
wire pc_clk1_in;
wire pc_clk8_in;
wire pc_aload_in;
reg pc_reg_upndn;
integer pc_delay;
// clock generator
wire cg_clk_in;
wire cg_aload_in;
wire cg_clk1_out;
wire cg_clk8a_out;
wire cg_clk8b_out;
reg cg_reg_1;
reg cg_rega_2;
reg cg_rega_3;
reg cg_regb_2;
reg cg_regb_3;
// for violation checks
reg clk_in_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg per_violation;
reg duty_violation;
reg sent_per_violation;
reg sent_duty_violation;
reg dll_to_lock; // exported signal
time clk_in_last_rising_edge;
time clk_in_last_falling_edge;
integer input_period;
integer clk_per_tolerance;
integer duty_cycle;
integer half_cycles_to_lock;
integer clk_in_period;
integer clk_in_duty_cycle;
// Timing hooks
// BUFFER INPUTS
wire clk_in;
wire aload_in;
wire offset_in5;
wire offset_in4;
wire offset_in3;
wire offset_in2;
wire offset_in1;
wire offset_in0;
wire upndn_in;
wire upndninclkena_in;
wire addnsub_in;
buf (clk_in, clk);
buf (aload_in, aload);
buf (offset_in5, offset[5]);
buf (offset_in4, offset[4]);
buf (offset_in3, offset[3]);
buf (offset_in2, offset[2]);
buf (offset_in1, offset[1]);
buf (offset_in0, offset[0]);
buf (upndn_in, upndnin);
buf (upndninclkena_in, upndninclkena);
buf (addnsub_in, addnsub);
assign offset_in = {offset_in5, offset_in4,
offset_in3, offset_in2,
offset_in1, offset_in0};
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (delayctrlout[0] +: delayctrl_out[0])) = (0, 0);
(posedge clk => (delayctrlout[1] +: delayctrl_out[1])) = (0, 0);
(posedge clk => (delayctrlout[2] +: delayctrl_out[2])) = (0, 0);
(posedge clk => (delayctrlout[3] +: delayctrl_out[3])) = (0, 0);
(posedge clk => (delayctrlout[4] +: delayctrl_out[4])) = (0, 0);
(posedge clk => (delayctrlout[5] +: delayctrl_out[5])) = (0, 0);
(posedge clk => (upndnout +: upndn_out)) = (0, 0);
(offset => delayctrlout) = (0, 0);
$setuphold(posedge clk, offset[0], 0, 0);
$setuphold(posedge clk, offset[1], 0, 0);
$setuphold(posedge clk, offset[2], 0, 0);
$setuphold(posedge clk, offset[3], 0, 0);
$setuphold(posedge clk, offset[4], 0, 0);
$setuphold(posedge clk, offset[5], 0, 0);
$setuphold(posedge clk, upndnin, 0, 0);
$setuphold(posedge clk, upndninclkena, 0, 0);
$setuphold(posedge clk, addnsub, 0, 0);
endspecify
// DRIVERs FOR outputs
and (delayctrlout[0], delayctrl_out[0], 1'b1);
and (delayctrlout[1], delayctrl_out[1], 1'b1);
and (delayctrlout[2], delayctrl_out[2], 1'b1);
and (delayctrlout[3], delayctrl_out[3], 1'b1);
and (delayctrlout[4], delayctrl_out[4], 1'b1);
and (delayctrlout[5], delayctrl_out[5], 1'b1);
and (offsetctrlout[0], offsetctrl_out[0], 1'b1);
and (offsetctrlout[1], offsetctrl_out[1], 1'b1);
and (offsetctrlout[2], offsetctrl_out[2], 1'b1);
and (offsetctrlout[3], offsetctrl_out[3], 1'b1);
and (offsetctrlout[4], offsetctrl_out[4], 1'b1);
and (offsetctrlout[5], offsetctrl_out[5], 1'b1);
and (dqsupdate, dqsupdate_out, 1'b1);
and (upndnout, upndn_out, 1'b1);
// INITIAL BLOCK - info messsage and legaity checks
initial
begin
input_period = str2int(input_frequency);
$display("Note: DLL instance %m has input frequency %0d ps", input_period);
$display(" sim_valid_lock %0d", sim_valid_lock);
$display(" sim_valid_lockcount %0d", sim_valid_lockcount);
$display(" sim_loop_intrinsic_delay %0d", sim_loop_intrinsic_delay);
$display(" sim_loop_delay_increment %0d", sim_loop_delay_increment);
clk_in_last_value = 0;
clk_in_last_rising_edge = 0;
clk_in_last_falling_edge = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
per_violation = 1'b0;
duty_violation = 1'b0;
sent_per_violation = 1'b0;
sent_duty_violation = 1'b0;
duty_cycle = input_period/2;
clk_per_tolerance = 2;
clk_in_period = 0;
clk_in_duty_cycle = 0;
dll_to_lock = 0;
half_cycles_to_lock = 0;
// Resolve string parameters
para_delay_buffer_mode = delay_buffer_mode == "auto" ? 2'b00 :
delay_buffer_mode == "low" ? 2'b01 : 2'b10;
para_delayctrlout_mode = delayctrlout_mode == "offset_only" ? 2'b01 :
delayctrlout_mode == "normal_offset" ? 2'b10 :
delayctrlout_mode == "static" ? 2'b11 : 2'b00;
para_offsetctrlout_mode = offsetctrlout_mode == "dynamic_addnsub" ? 2'b11 :
offsetctrlout_mode == "dynamic_sub" ? 2'b10 :
offsetctrlout_mode == "dynamic_add" ? 2'b01 : 2'b00;
para_static_offset = str2int(static_offset);
para_static_delay_ctrl = static_delay_ctrl;
para_jitter_reduction = jitter_reduction == "true" ? 1'b1 : 1'b0;
para_use_upndnin = use_upndnin == "true" ? 1'b1 : 1'b0;
para_use_upndninclkena = use_upndninclkena == "true" ? 1'b1 : 1'b0;
$display(" delay_buffer_mode %0s", delay_buffer_mode);
$display(" delayctrlout_mode %0s", delayctrlout_mode);
$display(" static_delay_ctrl %0d", para_static_delay_ctrl);
$display(" offsetctrlout_mode %0s", offsetctrlout_mode);
$display(" static_offset %0d", para_static_offset);
$display(" use_jitter_reduction %0s", jitter_reduction);
$display(" use_upndnin %0s", use_upndnin);
$display(" use_upndninclkena %0s", use_upndninclkena);
end
// CLOCK PERIOD and DUTY CYCLE VIOLATION CHECKS and DLL_TO_LOCK
// exported signals to outside of this block:
// - dll_to_lock
always @(clk_in)
begin
if (clk_in == 1'b1 && clk_in != clk_in_last_value) // rising edge
begin
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge <= 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
else // subsequent rising edge
begin
// check for clk_period violation and duty cycle violation
clk_in_period = $time - clk_in_last_rising_edge;
clk_in_duty_cycle = $time - clk_in_last_falling_edge;
if ( (clk_in_period < (input_period - clk_per_tolerance)) ||
(clk_in_period > (input_period + clk_per_tolerance)) )
begin
per_violation = 1'b1;
if (sent_per_violation != 1'b1)
begin
$display($time, " Warning : Input frequency violation on DLL instance %m. Specified input period is %0d ps but actual is %0d ps",
input_period, clk_in_period);
sent_per_violation = 1'b1;
end
end
else if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
begin
if (per_violation === 1'b1)
begin
$display($time, " Note : Input frequency on DLL instance %m now matches with specified clock frequency.");
sent_per_violation = 1'b0;
end
per_violation = 1'b0;
duty_violation = 1'b0;
end
if ((duty_violation == 1'b0) && (per_violation == 1'b0) && (dll_to_lock == 1'b0))
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
end
clk_in_last_rising_edge = $time;
end
else if (clk_in == 1'b0 && clk_in != clk_in_last_value) // falling edge
begin
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
clk_in_duty_cycle = $time - clk_in_last_rising_edge;
if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
duty_violation = 1'b0;
if (dll_to_lock == 1'b0 && duty_violation == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_in_last_falling_edge = $time;
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// 1 or 0 to X transitions - illegal
// reset lock and unlock counters
half_cycles_to_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
if (dll_to_lock)
begin
dll_to_lock <= 0;
$display($time, " Warning : clock switches from 0/1 to X. DLL instance %m will lose lock.");
end
else
begin
$display($time, " Warning : clock switches from 0/1 to X on DLL instance %m");
end
end
clk_in_last_value <= clk_in;
end
// CONNCECTING the DLL outputs ------------------------------------------------
assign delayctrl_out = dr_delayctrl_out;
assign offsetctrl_out = dr_offsetctrl_out;
assign dqsupdate_out = cg_clk8a_out;
assign upndn_out = pc_upndn_out;
// Delay and offset ctrl out resolver -----------------------------------------
// inputs
assign dr_clk8_in = ~cg_clk8b_out; // inverted
assign dr_offset_in = ((offsetctrlout_mode == "dynamic_addnsub" && dr_addnsub_in === 1'b0) || (offsetctrlout_mode == "dynamic_sub")) ?
(6'b111111 - offset_in + 6'b000001) : offset_in;
assign dr_dllcount_in = dc_dllcount_out;
assign dr_addnsub_in = addnsub_in;
assign dr_aload_in = aload_in;
// outputs
assign dr_delayctrl_out = (delayctrlout_mode == "test") ? {cg_clk1_out,aload,addnsub,dr_reg_dllcount[2:0]} :
(delayctrlout_mode == "offset_only") ? dr_offset_in :
(delayctrlout_mode == "normal_offset") ? dr_reg_offset
: dr_reg_dllcount; // both static and normal
assign dr_offsetctrl_out = dr_reg_offset;
// model
assign dr_delayctrl_int = (delayctrlout_mode == "static") ? para_static_delay_ctrl : dr_dllcount_in;
assign dr_offsetctrl_int = (offsetctrlout_mode == "static") ? para_static_offset : dr_offset_in;
// por
initial
begin
dr_reg_offset = 6'b000000;
dr_reg_dllcount = 6'b000000;
end
always @(posedge dr_clk8_in or posedge dr_aload_in )
begin
if (dr_aload_in === 1'b1)
dr_reg_dllcount <= 6'b000000;
else
dr_reg_dllcount <= dr_delayctrl_int;
end
always @(posedge dr_clk8_in or posedge dr_aload_in)
begin
if (dr_aload_in === 1'b1)
begin
dr_reg_offset <= 6'b000000;
end
else if (offsetctrlout_mode == "dynamic_addnsub") // addnsub
begin
if (dr_addnsub_in === 1'b1)
if (dr_delayctrl_int < 6'b111111 - dr_offset_in)
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 6'b111111;
else if (dr_addnsub_in === 1'b0)
if (dr_delayctrl_int > dr_offset_in)
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 6'b000000;
end
else if (offsetctrlout_mode == "dynamic_sub") // sub
begin
if (dr_delayctrl_int > dr_offset_in)
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 6'b000000;
end
else if (offsetctrlout_mode == "dynamic_add") // add
begin
if (dr_delayctrl_int < 6'b111111 - dr_offset_in)
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 6'b111111;
end
else if (offsetctrlout_mode == "static") // static
begin
if (para_static_offset >= 0)
if (para_static_offset < 64 && para_static_offset < 6'b111111 - dr_delayctrl_int)
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 6'b111111;
else
if (para_static_offset > -63 && dr_delayctrl_int > (-1)*para_static_offset)
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 6'b000000;
end
else
dr_reg_offset <= 6'b001110; // Error
end
// Delay Setting Control Counter ----------------------------------------------
//inputs
assign dc_dlltolock_in = dll_to_lock;
assign dc_aload_in = aload_in;
assign dc_clk1_in = cg_clk1_out;
assign dc_clk8_in = ~cg_clk8b_out; // inverted
assign dc_upndnclkena_in = (para_jitter_reduction === 1'b1) ? jc_upndnclkena_out :
(para_use_upndninclkena === 1'b1) ? upndninclkena : 1'b1;
assign dc_upndn_in = (para_use_upndnin === 1'b1) ? upndnin :
(para_jitter_reduction === 1'b1) ? jc_upndn_out : pc_upndn_out;
// outputs
assign dc_dllcount_out = dc_reg_dllcount;
// parameters used
// sim_valid_lockcount - ideal dll count value
// delay_buffer_mode -
// Model
initial
begin
// low=32=6'b100000 others=16
dc_reg_dllcount = delay_buffer_mode == "low" ? 6'b100000 : 6'b010000;
dc_reg_dlltolock_pulse = 1'b0;
end
// dll counter logic
always @(posedge dc_clk8_in or posedge dc_aload_in or posedge dc_dlltolock_in)
begin
if (dc_aload_in === 1'b1)
dc_reg_dllcount <= delay_buffer_mode == "low" ? 6'b100000 : 6'b010000;
else if (dc_dlltolock_in === 1'b1 && dc_upndnclkena_in === 1'b1 &&
para_use_upndnin === 1'b0 && dc_reg_dlltolock_pulse != 1'b1)
begin
dc_reg_dllcount <= sim_valid_lockcount;
dc_reg_dlltolock_pulse <= 1'b1;
end
else if (dc_upndnclkena_in === 1'b1) // posedge clk
begin
if (dc_upndn_in === 1'b1)
begin
if ((para_delay_buffer_mode == 2'b01 && dc_reg_dllcount < 6'b111111) ||
(para_delay_buffer_mode != 2'b01 && dc_reg_dllcount < 6'b011111))
dc_reg_dllcount <= dc_reg_dllcount + 1'b1;
end
else if (dc_upndn_in === 1'b0)
begin
if (dc_reg_dllcount > 6'b000000)
dc_reg_dllcount <= dc_reg_dllcount - 1'b1;
end
end
end
// Jitter reduction counter ---------------------------------------------------
// inputs
assign jc_clk8_in = ~cg_clk8b_out; // inverted
assign jc_upndn_in = pc_upndn_out;
assign jc_aload_in = aload_in;
// outputs
assign jc_upndn_out = jc_reg_upndn;
assign jc_upndnclkena_out = jc_reg_upndnclkena;
// Model
initial
begin
jc_count = 8;
jc_reg_upndnclkena = 1'b0;
jc_reg_upndn = 1'b0;
end
always @(posedge jc_clk8_in or posedge jc_aload_in)
begin
if (jc_aload_in === 1'b1)
jc_count <= 8;
else if (jc_count == 12)
begin
jc_reg_upndn <= 1'b1;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else if (jc_count == 4)
begin
jc_reg_upndn <= 1'b0;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else // increment/decrement counter
begin
jc_reg_upndnclkena <= 1'b0;
if (jc_upndn_in === 1'b1)
jc_count <= jc_count + 1;
else if (jc_upndn_in === 1'b0)
jc_count <= jc_count - 1;
end
end
// Phase comparator -----------------------------------------------------------
// inputs
assign pc_clk1_in = cg_clk1_out;
assign pc_clk8_in = cg_clk8b_out; // positive edge
assign pc_dllcount_in = dc_dllcount_out; // for phase loop calculation
assign pc_aload_in = aload_in;
// outputs
assign pc_upndn_out = pc_reg_upndn;
// parameter used
// sim_loop_intrinsic_delay, sim_loop_delay_increment
// Model
initial
begin
pc_reg_upndn = 1'b1;
pc_delay = 0;
end
always @(posedge pc_clk8_in or posedge pc_aload_in)
begin
if (pc_aload_in === 1'b1)
pc_reg_upndn <= 1'b1;
else
pc_delay = sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_delay > input_period)
pc_reg_upndn <= 1'b0;
else
pc_reg_upndn <= 1'b1;
end
// Clock Generator -----------------------------------------------------------
// inputs
assign cg_clk_in = clk_in;
assign cg_aload_in = aload_in;
// outputs
assign cg_clk8a_out = cg_rega_3;
assign cg_clk8b_out = cg_regb_3;
assign cg_clk1_out = (cg_aload_in === 1'b1) ? 1'b0 : cg_clk_in;
// Model
// por
initial
begin
cg_reg_1 = 1'b0;
cg_rega_2 = 1'b0;
cg_rega_3 = 1'b0;
cg_regb_2 = 1'b1;
cg_regb_3 = 1'b0;
end
always @(posedge cg_clk1_out or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_reg_1 <= 1'b0;
else
cg_reg_1 <= ~cg_reg_1;
end
always @(posedge cg_reg_1 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
begin
cg_rega_2 <= 1'b0;
cg_regb_2 <= 1'b1;
end
else
begin
cg_rega_2 <= ~cg_rega_2;
cg_regb_2 <= ~cg_regb_2;
end
end
always @(posedge cg_rega_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_rega_3 <= 1'b0;
else
cg_rega_3 <= ~cg_rega_3;
end
always @(posedge cg_regb_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_regb_3 <= 1'b0;
else if ($time != 0)
cg_regb_3 <= ~cg_regb_3;
end
endmodule
//------------------------------------------------------------------
//
// Module Name : ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module stratixii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk_in;
end
always @ (clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1'b1) & (clk_last_value == 1'b0) & (ena == 1'b1))
q_tmp <= d_in;
clk_last_value = clk_in;
end
and (q, q_tmp, 'b1);
endmodule // ena_reg
//------------------------------------------------------------------
//
// Module Name : stratixii_clkctrl
//
// Description : StratixII CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
parameter clock_type = "auto";
parameter lpm_type = "stratixii_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg_out; // output of ENA register
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
tri1 devclrn;
tri1 devpor;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
stratixii_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
stratixii_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg_out)
);
and (outclk, cereg_out, clkmux_out);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_tx_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module stratixii_lvds_tx_reg (q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1))
q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // stratixii_lvds_tx_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_tx_parallel_register
//
// Description : Register for the 10 data input channels of the StratixII
// LVDS Tx
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_tx_parallel_register (clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or enable_ipd or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd))
begin
if (enable_ipd === 1'b1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end // always
assign dataout_opd = dataout_tmp;
endmodule //stratixii_lvds_tx_parallel_register
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_tx_out_block
//
// Description : Negative edge triggered register on the Tx output.
// Also, optionally generates an identical/inverted output clock
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_tx_out_block (clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// BUFFER INPUTS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
// TEST PARAMETER VALUES
assign falling_clk_out = (use_falling_clock_edge == "true")?1'b1:1'b0;
assign bypass_mode = (bypass_serializer == "true")?1'b1:1'b0;
assign invert_mode = (invert_clock == "true")?1'b1:1'b0;
// TIMING PATHS
specify
if (bypass_mode == 1'b1)
(clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 0;
end
else begin
if (bypass_serializer == "false")
begin
if (use_falling_clock_edge == "false")
dataout_tmp <= datain_in;
if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
begin
if (use_falling_clock_edge == "true")
dataout_tmp <= datain_in;
end
end // bypass is off
else begin
// generate clk_out
if (invert_clock == "false")
dataout_tmp <= clk_in;
else
dataout_tmp <= !clk_in;
end // clk output
end
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule //stratixii_lvds_tx_out_block
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_transmitter
//
// Description : Timing simulation model for the StratixII LVDS Tx WYSIWYG.
// It instantiates the following sub-modules :
// 1) primitive DFFE
// 2) StratixII_lvds_tx_parallel_register and
// 3) StratixII_lvds_tx_out_block
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_transmitter (clk0,
enable0,
datain,
serialdatain,
postdpaserialdatain,
dataout,
serialfdbkout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
parameter use_serial_data_input = "false";
parameter use_post_dpa_serial_data_input = "false";
parameter preemphasis_setting = 0;
parameter vod_setting = 0;
parameter differential_drive = 0;
parameter lpm_type = "stratixii_lvds_transmitter";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk0;
input enable0;
input serialdatain;
input postdpaserialdatain;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
output serialfdbkout;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES AND NETS
integer i;
wire dataout_tmp;
wire dataout_wire;
wire shift_out;
reg clk0_last_value;
wire [channel_width - 1:0] input_data;
reg [channel_width - 1:0] shift_data;
wire txload0;
reg [channel_width - 1:0] datain_dly;
wire bypass_mode;
wire [channel_width - 1:0] datain_in;
wire serial_din_mode;
wire postdpa_serial_din_mode;
wire clk0_in;
wire serialdatain_in;
wire postdpaserialdatain_in;
buf (clk0_in, clk0);
buf datain_buf [channel_width - 1:0] (datain_in, datain);
buf (serialdatain_in, serialdatain);
buf (postdpaserialdatain_in, postdpaserialdatain);
// TEST PARAMETER VALUES
assign serial_din_mode = (use_serial_data_input == "true") ? 1'b1 : 1'b0;
assign postdpa_serial_din_mode = (use_post_dpa_serial_data_input == "true") ? 1'b1 : 1'b0;
// TIMING PATHS
specify
if (serial_din_mode == 1'b1)
(serialdatain => dataout) = (0, 0);
if (postdpa_serial_din_mode == 1'b1)
(postdpaserialdatain => dataout) = (0, 0);
endspecify
initial
begin
i = 0;
clk0_last_value = 0;
shift_data = 'b0;
end
stratixii_lvds_tx_reg txload0_reg (.d(enable0),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(clk0_in),
.q(txload0)
);
stratixii_lvds_tx_out_block output_module (.clk(clk0_in),
.datain(shift_out),
.dataout(dataout_tmp),
.devclrn(devclrn),
.devpor(devpor)
);
defparam output_module.bypass_serializer = bypass_serializer;
defparam output_module.invert_clock = invert_clock;
defparam output_module.use_falling_clock_edge = use_falling_clock_edge;
stratixii_lvds_tx_parallel_register input_reg (.clk(txload0),
.enable(1'b1),
.datain(datain_dly),
.dataout(input_data),
.devclrn(devclrn),
.devpor(devpor)
);
defparam input_reg.channel_width = channel_width;
always @(datain_in)
begin
datain_dly <= #1 datain_in;
end
assign shift_out = shift_data[channel_width - 1];
always @(clk0_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
shift_data <= 'b0;
end
else begin
if (bypass_serializer == "false")
begin
if ((clk0_in === 1'b1) && (clk0_last_value !== clk0_in))
begin
if (txload0 === 1'b1)
begin
for (i = 0; i < channel_width; i = i + 1)
shift_data[i] <= input_data[i];
end
else begin
for (i = (channel_width - 1); i > 0; i = i - 1 )
shift_data[i] <= shift_data[i-1];
end
end
end // bypass is off
end // devpor
clk0_last_value <= clk0_in;
end // always
assign dataout_wire = (use_serial_data_input == "true") ? serialdatain_in :
(use_post_dpa_serial_data_input == "true") ? postdpaserialdatain_in :
dataout_tmp;
and (dataout, dataout_wire, 1'b1);
and (serialfdbkout, dataout_wire, 1'b1);
endmodule // stratixii_lvds_transmitter
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the StratixII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratixii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
end
and (cout, cout_tmp, 1'b1);
endmodule // stratixii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the StratixII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratixii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg clk_last_valid_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'bx)
begin
$display("Warning : Invalid transition to 'X' detected on StratixII PLL input clk. This edge will be ignored.");
$display("Time: %0t Instance: %m", $time);
end
else if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
if (clk !== 1'bx)
clk_last_valid_value = clk;
end
assign cout = tmp_cout;
endmodule // stratixii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0, C1, C2, C3, C4 and
// C5 output counters of the StratixII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratixii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // stratixii_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module stratixii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // stratixii_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_pll
//
// Description : Timing simulation model for the StratixII PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 6 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module stratixii_pll (inclk,
fbin,
ena,
clkswitch,
areset,
pfdena,
scanclk,
scanread,
scanwrite,
scandata,
testin,
clk,
clkbad,
activeclock,
locked,
clkloss,
scandataout,
scandone,
enable0,
enable1,
testupout,
testdownout,
sclkout
);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clk0";
parameter feedback_source = "clk0";
parameter qualify_conf_done = "off";
parameter test_input_comp_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter self_reset_on_gated_loss_lock = "off";
parameter valid_lock_multiplier = 1;
parameter invalid_lock_multiplier = 5;
parameter switch_over_type = "auto";
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "on";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter use_dc_coupling = "false";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "c0";
parameter clk1_counter = "c1";
parameter clk2_counter = "c2";
parameter clk3_counter = "c3";
parameter clk4_counter = "c4";
parameter clk5_counter = "c5";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter m_test_source = 5;
parameter c0_test_source = 5;
parameter c1_test_source = 5;
parameter c2_test_source = 5;
parameter c3_test_source = 5;
parameter c4_test_source = 5;
parameter c5_test_source = 5;
// LVDS mode parameters
parameter enable0_counter = "c0";
parameter enable1_counter = "c1";
parameter sclkout0_phase_shift = "0";
parameter sclkout1_phase_shift = "0";
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter charge_pump_current = 52;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 16;
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "stratixii_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter family_name = "StratixII";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
// SIMULATION_ONLY_PARAMETERS_END
parameter scan_chain_mif_file = "";
// INPUT PORTS
input [1:0] inclk;
input fbin;
input ena;
input clkswitch;
input areset;
input pfdena;
input scanclk;
input scanread;
input scanwrite;
input scandata;
input [3:0] testin;
// OUTPUT PORTS
output [5:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output clkloss;
output scandataout;
output scandone;
// lvds specific output ports
output enable0;
output enable1;
output [1:0] sclkout;
// test ports
output testupout;
output testdownout;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire clkswitch_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire scanclk_ipd;
wire scanread_ipd;
wire scanwrite_ipd;
wire scandata_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, fbin);
buf (clkswitch_ipd, clkswitch);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (scanclk_ipd, scanclk);
buf (scanread_ipd, scanread);
buf (scanwrite_ipd, scanwrite);
buf (scandata_ipd, scandata);
// TIMING CHECKS
specify
$setuphold(posedge scanclk, scanread, 0, 0);
$setuphold(posedge scanclk, scanwrite, 0, 0);
$setuphold(posedge scanclk, scandata, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer c0_count;
integer c0_initial_count;
integer c1_count;
integer c1_initial_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time next_vco_sched_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg c0_got_first_rising_edge;
reg c1_got_first_rising_edge;
reg vco_c0_last_value;
reg vco_c1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:5];
reg [31:0] c_low_val[0:5];
reg [8*6:1] c_mode_val[0:5];
reg [31:0] c_initial_val[0:5];
integer c_ph_val[0:5];
// temporary registers for reprogramming
integer c_ph_val_tmp[0:5];
reg [31:0] c_high_val_tmp[0:5];
reg [31:0] c_low_val_tmp[0:5];
reg [8*6:1] c_mode_val_tmp[0:5];
// hold registers for reprogramming
integer c_ph_val_hold[0:5];
reg [31:0] c_high_val_hold[0:5];
reg [31:0] c_low_val_hold[0:5];
reg [8*6:1] c_mode_val_hold[0:5];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:5];
reg [31:0] c_low_val_old[0:5];
reg [8*6:1] c_mode_val_old[0:5];
integer c_ph_val_old[0:5];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [31:0] m_hi;
reg [31:0] m_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:5];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
reg inclk_c0_from_vco;
reg inclk_c1_from_vco;
reg inclk_c2_from_vco;
reg inclk_c3_from_vco;
reg inclk_c4_from_vco;
reg inclk_c5_from_vco;
reg inclk_m_from_vco;
reg inclk_sclkout0_from_vco;
reg inclk_sclkout1_from_vco;
wire inclk_m;
wire [5:0] clk_tmp;
wire ena_pll;
wire n_cntr_inclk;
reg sclkout0_tmp;
reg sclkout1_tmp;
reg vco_c0;
reg vco_c1;
wire [5:0] clk_out;
wire sclkout0;
wire sclkout1;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg c0_tmp;
reg c1_tmp;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
integer ext_fbk_cntr_index;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandone_tmp;
reg scandone_tmp_last_value;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
reg scanread_reg;
reg scanwrite_reg;
reg scanwrite_enabled;
reg scanwrite_last_value;
reg [173:0] scan_data;
reg [173:0] tmp_scan_data;
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// LOCAL_PARAMETERS_BEGIN
parameter GPP_SCAN_CHAIN = 174;
parameter FAST_SCAN_CHAIN = 75;
// primary clk is always inclk0
parameter prim_clk = "inclk0";
parameter GATE_LOCK_CYCLES = 7;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_c_high[0:5];
integer i_c_low[0:5];
integer i_c_initial[0:5];
integer i_c_ph[0:5];
reg [8*6:1] i_c_mode[0:5];
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg [9*8:1] loop_filter_r_arr[0:39];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_is_disabled;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_enable0_counter;
reg [8*`WORD_LENGTH:1] l_enable1_counter;
integer current_clock;
integer ena0_cntr;
integer ena1_cntr;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg op_mode;
reg init;
reg tap0_is_active;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if ((2 * refclk) > (refclk * max_modulus *2 / m_mod))
slowest_clk = 2 * refclk;
else
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
integer counter_l, tmp_counter_low;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
tmp_counter_low = output_counter_value - counter_h;
if (tmp_counter_low == 0)
counter_l = 1;
else counter_l = tmp_counter_low;
counter_low = counter_l;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for stratixii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_primary_clock = alpha_tolower(prim_clk);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_switch_over_type = alpha_tolower(switch_over_type);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_enable0_counter = alpha_tolower(enable0_counter);
l_enable1_counter = alpha_tolower(enable1_counter);
if (l_enable0_counter == "c0")
ena0_cntr = 0;
else
ena0_cntr = 1;
if (l_enable1_counter == "c0")
ena1_cntr = 0;
else
ena1_cntr = 1;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 57;
loop_filter_c_arr[1] = 16;
loop_filter_c_arr[2] = 36;
loop_filter_c_arr[3] = 5;
fpll_loop_filter_c_arr[0] = 18;
fpll_loop_filter_c_arr[1] = 13;
fpll_loop_filter_c_arr[2] = 8;
fpll_loop_filter_c_arr[3] = 2;
charge_pump_curr_arr[0] = 6;
charge_pump_curr_arr[1] = 12;
charge_pump_curr_arr[2] = 30;
charge_pump_curr_arr[3] = 36;
charge_pump_curr_arr[4] = 52;
charge_pump_curr_arr[5] = 57;
charge_pump_curr_arr[6] = 72;
charge_pump_curr_arr[7] = 77;
charge_pump_curr_arr[8] = 92;
charge_pump_curr_arr[9] = 96;
charge_pump_curr_arr[10] = 110;
charge_pump_curr_arr[11] = 114;
charge_pump_curr_arr[12] = 127;
charge_pump_curr_arr[13] = 131;
charge_pump_curr_arr[14] = 144;
charge_pump_curr_arr[15] = 148;
loop_filter_r_arr[0] = " 1.000000";
loop_filter_r_arr[1] = " 1.500000";
loop_filter_r_arr[2] = " 2.000000";
loop_filter_r_arr[3] = " 2.500000";
loop_filter_r_arr[4] = " 3.000000";
loop_filter_r_arr[5] = " 3.500000";
loop_filter_r_arr[6] = " 4.000000";
loop_filter_r_arr[7] = " 4.500000";
loop_filter_r_arr[8] = " 5.000000";
loop_filter_r_arr[9] = " 5.500000";
loop_filter_r_arr[10] = " 6.000000";
loop_filter_r_arr[11] = " 6.500000";
loop_filter_r_arr[12] = " 7.000000";
loop_filter_r_arr[13] = " 7.500000";
loop_filter_r_arr[14] = " 8.000000";
loop_filter_r_arr[15] = " 8.500000";
loop_filter_r_arr[16] = " 9.000000";
loop_filter_r_arr[17] = " 9.500000";
loop_filter_r_arr[18] = "10.000000";
loop_filter_r_arr[19] = "10.500000";
loop_filter_r_arr[20] = "11.000000";
loop_filter_r_arr[21] = "11.500000";
loop_filter_r_arr[22] = "12.000000";
loop_filter_r_arr[23] = "12.500000";
loop_filter_r_arr[24] = "13.000000";
loop_filter_r_arr[25] = "13.500000";
loop_filter_r_arr[26] = "14.000000";
loop_filter_r_arr[27] = "14.500000";
loop_filter_r_arr[28] = "15.000000";
loop_filter_r_arr[29] = "15.500000";
loop_filter_r_arr[30] = "16.000000";
loop_filter_r_arr[31] = "16.500000";
loop_filter_r_arr[32] = "17.000000";
loop_filter_r_arr[33] = "17.500000";
loop_filter_r_arr[34] = "18.000000";
loop_filter_r_arr[35] = "18.500000";
loop_filter_r_arr[36] = "19.000000";
loop_filter_r_arr[37] = "19.500000";
loop_filter_r_arr[38] = "20.000000";
loop_filter_r_arr[39] = "20.500000";
if (m == 0)
begin
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
// VCO feedback loop settings for external feedback mode
// first find which counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
op_mode = 1;
if (l_feedback_source == "clk0")
ext_fbk_cntr = i_clk0_counter;
else if (l_feedback_source == "clk1")
ext_fbk_cntr = i_clk1_counter;
else if (l_feedback_source == "clk2")
ext_fbk_cntr = i_clk2_counter;
else if (l_feedback_source == "clk3")
ext_fbk_cntr = i_clk3_counter;
else if (l_feedback_source == "clk4")
ext_fbk_cntr = i_clk4_counter;
else if (l_feedback_source == "clk5")
ext_fbk_cntr = i_clk5_counter;
else ext_fbk_cntr = "c0";
if (ext_fbk_cntr == "c0")
ext_fbk_cntr_index = 0;
else if (ext_fbk_cntr == "c1")
ext_fbk_cntr_index = 1;
else if (ext_fbk_cntr == "c2")
ext_fbk_cntr_index = 2;
else if (ext_fbk_cntr == "c3")
ext_fbk_cntr_index = 3;
else if (ext_fbk_cntr == "c4")
ext_fbk_cntr_index = 4;
else if (ext_fbk_cntr == "c5")
ext_fbk_cntr_index = 5;
end
else
begin
op_mode = 0;
ext_fbk_cntr_index = 0;
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
// convert user parameters to advanced
if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (i_c_mode[ext_fbk_cntr_index] == "bypass")
output_count = 1;
else
output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index];
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
refclk_period = inclk0_input_frequency * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
c0_got_first_rising_edge = 0;
c1_got_first_rising_edge = 0;
vco_c0_last_value = 0;
c0_count = 2;
c0_initial_count = 1;
c1_count = 2;
c1_initial_count = 1;
c0_tmp = 0;
c1_tmp = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_c0 = 0;
vco_c1 = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandone_tmp = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
m_val[1] = m2;
n_val[1] = n2;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 6; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
if (l_primary_clock == "inclk0")
current_clock = 0;
else current_clock = 1;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast")
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
end
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
scanread_active_edge = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 4;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 6;
end
scanread_reg = 0;
scanwrite_reg = 0;
scanwrite_enabled = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
// initialize the scan_chain contents
// CP/LF bits
scan_data[11:0] = 12'b0;
for (i = 0; i <= 3; i = i + 1)
begin
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
if (fpll_loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
else begin
if (loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
end
for (i = 0; i <= 15; i = i + 1)
begin
if (charge_pump_curr_arr[i] == charge_pump_current)
scan_data[3:0] = i;
end
for (i = 0; i <= 39; i = i + 1)
begin
if (loop_filter_r_arr[i] == loop_filter_r)
begin
if ((i >= 16) && (i <= 23))
scan_data[9:4] = i+8;
else if ((i >= 24) && (i <= 31))
scan_data[9:4] = i+16;
else if (i >= 32)
scan_data[9:4] = i+24;
else
scan_data[9:4] = i;
end
end
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
scan_data[21:12] = 10'b0; // M, C3-C0 ph
// C0-C3 high
scan_data[25:22] = c_high_val[0];
scan_data[35:32] = c_high_val[1];
scan_data[45:42] = c_high_val[2];
scan_data[55:52] = c_high_val[3];
// C0-C3 low
scan_data[30:27] = c_low_val[0];
scan_data[40:37] = c_low_val[1];
scan_data[50:47] = c_low_val[2];
scan_data[60:57] = c_low_val[3];
// C0-C3 mode
for (i = 0; i < 4; i = i + 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[26 + (10*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
else begin
scan_data[26 + (10*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
end
// M
if (m_mode_val[0] == "bypass")
begin
scan_data[66] = 1;
scan_data[71] = 0;
scan_data[65:62] = 4'b0;
scan_data[70:67] = 4'b0;
end
else begin
scan_data[66] = 0; // set BYPASS bit to 0
scan_data[70:67] = m_val[0]/2; // set M low
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[65:62] = scan_data[70:67];
scan_data[71] = 0;
end
else begin // M is odd : M high = low + 1
scan_data[65:62] = (m_val[0]/2) + 1;
scan_data[71] = 1;
end
end
// N
scan_data[73:72] = n_val[0];
if (n_mode_val[0] == "bypass")
begin
scan_data[74] = 1;
scan_data[73:72] = 2'b0;
end
end
else begin // PLL type is enhanced/auto
scan_data[25:12] = 14'b0;
// C5-C0 high
scan_data[33:26] = c_high_val[5];
scan_data[51:44] = c_high_val[4];
scan_data[69:62] = c_high_val[3];
scan_data[87:80] = c_high_val[2];
scan_data[105:98] = c_high_val[1];
scan_data[123:116] = c_high_val[0];
// C5-C0 low
scan_data[42:35] = c_low_val[5];
scan_data[60:53] = c_low_val[4];
scan_data[78:71] = c_low_val[3];
scan_data[96:89] = c_low_val[2];
scan_data[114:107] = c_low_val[1];
scan_data[132:125] = c_low_val[0];
for (i = 5; i >= 0; i = i - 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[124 - (18*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
else begin
scan_data[124 - (18*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
end
scan_data[142:134] = m_val[0];
scan_data[143] = 0;
scan_data[152:144] = m_val[1];
scan_data[153] = 0;
if (m_mode_val[0] == "bypass")
begin
scan_data[143] = 1;
scan_data[142:134] = 9'b0;
end
if (m_mode_val[1] == "bypass")
begin
scan_data[153] = 1;
scan_data[152:144] = 9'b0;
end
scan_data[162:154] = n_val[0];
scan_data[172:164] = n_val[1];
if (n_mode_val[0] == "bypass")
begin
scan_data[163] = 1;
scan_data[162:154] = 9'b0;
end
if (n_mode_val[1] == "bypass")
begin
scan_data[173] = 1;
scan_data[172:164] = 9'b0;
end
end
// now save this counter's parameters
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 1'b0;
// check if pll is in test mode
if (m_test_source != 5 || c0_test_source != 5 || c1_test_source != 5 || c2_test_source != 5 || c3_test_source != 5 || c4_test_source != 5 || c5_test_source != 5)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_is_disabled = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
tap0_is_active = 1;
next_vco_sched_time = 0;
end
always @(clkswitch_ipd)
begin
if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if (clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
inclk_n = inclk1_ipd;
end
else if (clkswitch_ipd === 1'b0)
begin
current_clock = 0;
active_clock = 0;
inclk_n = inclk0_ipd;
end
end
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk0_ipd !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && (clkswitch_ipd !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
else clkloss_tmp = clkswitch_ipd;
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
and (clkloss, clkloss_tmp, 1'b1);
stratixii_pll_reg ena_reg ( .clk(!inclk_n),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(1'b1),
.q(pllena_reg));
and (test_mode_inclk, inclk_n, pllena_reg);
assign n_cntr_inclk = (pll_in_test_mode === 1'b1) ? test_mode_inclk : inclk_n;
assign ena_pll = (pll_in_test_mode === 1'b1) ? pllena_reg : ena_ipd;
assign inclk_m = (m_test_source == 0) ? n_cntr_inclk : op_mode == 1 ? (l_feedback_source == "clk0" ? clk_tmp[0] :
l_feedback_source == "clk1" ? clk_tmp[1] :
l_feedback_source == "clk2" ? clk_tmp[2] :
l_feedback_source == "clk3" ? clk_tmp[3] :
l_feedback_source == "clk4" ? clk_tmp[4] :
l_feedback_source == "clk5" ? clk_tmp[5] : 1'b0) :
inclk_m_from_vco;
stratixii_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
stratixii_n_cntr n1 (.clk(n_cntr_inclk),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val[0]));
always @(vco_out[0])
begin
// now schedule the other taps with the appropriate phase-shift
for (k = 1; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(phase_shift[k]) vco_out[0];
end
end
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (!pll_is_disabled) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_tap[x] !== vco_tap_last_value[x])
begin
if (c_ph_val[0] == x)
begin
inclk_c0_from_vco <= vco_tap[x];
if (is_fast_pll == 1'b1)
begin
if (ena0_cntr == 0)
inclk_sclkout0_from_vco <= vco_tap[x];
if (ena1_cntr == 0)
inclk_sclkout1_from_vco <= vco_tap[x];
end
end
if (c_ph_val[1] == x)
begin
inclk_c1_from_vco <= vco_tap[x];
if (is_fast_pll == 1'b1)
begin
if (ena0_cntr == 1)
inclk_sclkout0_from_vco <= vco_tap[x];
if (ena1_cntr == 1)
inclk_sclkout1_from_vco <= vco_tap[x];
end
end
if (c_ph_val[2] == x)
inclk_c2_from_vco <= vco_tap[x];
if (c_ph_val[3] == x)
inclk_c3_from_vco <= vco_tap[x];
if (c_ph_val[4] == x)
inclk_c4_from_vco <= vco_tap[x];
if (c_ph_val[5] == x)
inclk_c5_from_vco <= vco_tap[x];
if (m_ph_val == x)
inclk_m_from_vco <= vco_tap[x];
end
end
if (scanwrite_enabled === 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y <= 5; y = y + 1)
begin
if (c_ph_val[y] == x)
c_ph_val[y] <= c_ph_val_tmp[y];
end
if (m_ph_val == x)
m_ph_val <= m_ph_val_tmp;
end
end
end
// reset all counter phase tap values to POF programmed values
if (areset_ipd === 1'b1)
begin
m_ph_val <= m_ph_val_orig;
m_ph_val_tmp <= m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
begin
c_ph_val[i] <= c_ph_val_orig[i];
c_ph_val_tmp[i] <= c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
always @(inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end
always @(inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end
assign inclk_c0 = (c0_test_source == 0) ? n_cntr_inclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
stratixii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
always @(posedge c0_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge c0_clk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? n_cntr_inclk : (c1_test_source == 2) ? fbclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
stratixii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge c1_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge c1_clk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? n_cntr_inclk : (ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
stratixii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge c2_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge c2_clk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
stratixii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge c3_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge c3_clk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? n_cntr_inclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
stratixii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge c4_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge c4_clk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign inclk_c5 = ((c5_test_source == 0) ? n_cntr_inclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco);
stratixii_scale_cntr c5 (.clk(inclk_c5),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge c5_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val[5] <= c_high_val_tmp[5];
c_mode_val[5] <= c_mode_val_tmp[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge c5_clk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val[5] <= c_low_val_tmp[5];
end
end
always @(vco_tap[c_ph_val[0]] or posedge areset_ipd or negedge ena_pll or stop_vco)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
c0_count = 2;
c0_initial_count = 1;
c0_got_first_rising_edge = 0;
end
else begin
if (c0_got_first_rising_edge == 1'b0)
begin
if (vco_tap[c_ph_val[0]] == 1'b1 && vco_tap[c_ph_val[0]] != vco_c0_last_value)
begin
if (c0_initial_count == c_initial_val[0])
c0_got_first_rising_edge = 1;
else
c0_initial_count = c0_initial_count + 1;
end
end
else if (vco_tap[c_ph_val[0]] != vco_c0_last_value)
begin
c0_count = c0_count + 1;
if (c0_count == (c_high_val[0] + c_low_val[0]) * 2)
c0_count = 1;
end
if (vco_tap[c_ph_val[0]] == 1'b0 && vco_tap[c_ph_val[0]] != vco_c0_last_value)
begin
if (c0_count == 1)
begin
c0_tmp = 1;
c0_got_first_rising_edge = 0;
end
else c0_tmp = 0;
end
end
vco_c0_last_value = vco_tap[c_ph_val[0]];
end
always @(vco_tap[c_ph_val[1]] or posedge areset_ipd or negedge ena_pll or stop_vco)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
c1_count = 2;
c1_initial_count = 1;
c1_got_first_rising_edge = 0;
end
else begin
if (c1_got_first_rising_edge == 1'b0)
begin
if (vco_tap[c_ph_val[1]] == 1'b1 && vco_tap[c_ph_val[1]] != vco_c1_last_value)
begin
if (c1_initial_count == c_initial_val[1])
c1_got_first_rising_edge = 1;
else
c1_initial_count = c1_initial_count + 1;
end
end
else if (vco_tap[c_ph_val[1]] != vco_c1_last_value)
begin
c1_count = c1_count + 1;
if (c1_count == (c_high_val[1] + c_low_val[1]) * 2)
c1_count = 1;
end
if (vco_tap[c_ph_val[1]] == 1'b0 && vco_tap[c_ph_val[1]] != vco_c1_last_value)
begin
if (c1_count == 1)
begin
c1_tmp = 1;
c1_got_first_rising_edge = 0;
end
else c1_tmp = 0;
end
end
vco_c1_last_value = vco_tap[c_ph_val[1]];
end
assign enable0_tmp = (ena0_cntr == 0) ? c0_tmp : c1_tmp;
assign enable1_tmp = (ena1_cntr == 0) ? c0_tmp : c1_tmp;
always @ (inclk_n or ena_pll or areset_ipd)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 1'b1 && inclk_last_value != inclk_n)
begin
gate_count = gate_count + 1;
if (l_sim_gate_lock_device_behavior == "on")
begin
if (gate_count == gate_lock_counter)
gate_out = 1;
end
else begin
if (gate_count == GATE_LOCK_CYCLES)
gate_out = 1;
end
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @(posedge scanread_ipd)
begin
scanread_active_edge = $time;
end
always @ (scanclk_ipd)
begin
if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1)
begin
// enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end
if (scanread_reg === 1'b1)
gated_scanclk <= scanclk_ipd && scanread_reg;
else
gated_scanclk <= 1'b1;
if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0)
begin
// register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk)
scanclk_period = $time - scanclk_last_rising_edge;
else begin
got_first_scanclk = 1;
end
// reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd == 1'b0 && scanread_reg == 1'b1)
begin
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
end
scanclk_last_rising_edge = $time;
end
scanclk_last_value = scanclk_ipd;
end
always @(posedge gated_scanclk)
begin
if ($time > 0)
begin
if (!got_first_gated_scanclk)
begin
got_first_gated_scanclk = 1;
// if ($time - scanread_active_edge < scanclk_period)
// begin
// scanread_setup_violation = 1;
// $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in.");
// $display ("Time: %0t Instance: %m", $time);
// end
end
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] <= scandata_ipd;
end
end
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1];
always @(posedge scandone_tmp)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : %s PLL Reprogramming completed with the following values (Values in parantheses are original values) : ", family_name);
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
$display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old);
if (ss > 0)
begin
$display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]);
$display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]);
end
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]);
end
// display Charge pump and loop filter values
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(scanwrite_enabled)
begin
if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1)
begin
// falling edge : deassert scandone
scandone_tmp <= #(1.5*scanclk_period) 1'b0;
// reset counter transfer flags
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
end
if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled)
begin
$display ("NOTE : %s PLL Reprogramming initiated ....", family_name);
$display ("Time: %0t Instance: %m", $time);
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// make temp. copy of scan_data for processing
tmp_scan_data = scan_data;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
// CP
// Bits 0-3 : all values are legal
cp_curr_val = charge_pump_curr_arr[scan_data[3:0]];
// LF Resistance : bits 4-9
// values from 010000 - 010111, 100000 - 100111,
// 110000- 110111 are illegal
if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) ||
((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) ||
((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111)))
begin
$display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
reconfig_err = 1;
end
else begin
i = scan_data[9:4];
if (i >= 56 )
i = i - 24;
else if ((i >= 40) && (i <= 47))
i = i - 16;
else if ((i >= 24) && (i <= 31))
i = i - 8;
lfr_val = loop_filter_r_arr[i];
end
// LF Capacitance : bits 10,11 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]];
else
lfc_val = loop_filter_c_arr[scan_data[11:10]];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
m_ph_val_old = m_ph_val;
for (i=0; i<=5; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_ph_val_old[i] = c_ph_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// first the M counter phase : bit order same for fast and GPP
if (scan_data[12] == 1'b0)
begin
// do nothing
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1)
begin
m_ph_val_tmp = m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7)
m_ph_val_tmp = 0;
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0)
begin
m_ph_val_tmp = m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0)
m_ph_val_tmp = 7;
end
else
begin
$display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
reconfig_err = 1;
end
// read the fast PLL bits.
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
// C3-C0 phase bits
for (i = 3; i >= 0; i=i-1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
// C0-C3 counter moduli
tmp_scan_data = scan_data;
for (i = 0; i < 4; i=i+1)
begin
if (tmp_scan_data[26] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[31] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
$display ("Time: %0t Instance: %m", $time);
end
end
else if (tmp_scan_data[31] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[25:22] === 4'b0000)
c_high_val_tmp[i] = 5'b10000;
else
c_high_val_tmp[i] = {1'b0, tmp_scan_data[25:22]};
if (tmp_scan_data[30:27] === 4'b0000)
c_low_val_tmp[i] = 5'b10000;
else
c_low_val_tmp[i] = {1'b0, tmp_scan_data[30:27]};
tmp_scan_data = tmp_scan_data >> 10;
end
// M
error = 0;
// some temporary storage
if (scan_data[65:62] == 4'b0000)
m_hi = 5'b10000;
else
m_hi = {1'b0, scan_data[65:62]};
if (scan_data[70:67] == 4'b0000)
m_lo = 5'b10000;
else
m_lo = {1'b0, scan_data[70:67]};
m_val_tmp[0] = m_hi + m_lo;
if (scan_data[66] === 1'b1)
begin
if (scan_data[71] === 1'b1)
begin
// this will turn off the M counter : error
reconfig_err = 1;
error = 1;
$display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
// M counter is being bypassed
if (m_mode_val[0] !== "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 4);
end
m_val_tmp[0] = 32'b1;
m_mode_val[0] = "bypass";
end
end
else begin
if (m_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 1);
end
m_mode_val[0] = "";
if (scan_data[71] === 1'b1)
begin
// odd : check for duty cycle, if not 50% -- error
if (m_hi - m_lo !== 1)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
end
else begin // even mode
if (m_hi !== m_lo)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
end
end
// N
error = 0;
n_val[0] = {1'b0, scan_data[73:72]};
if (scan_data[74] !== 1'b1)
begin
if (scan_data[73:72] == 2'b01)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 2);
end
else if (scan_data[73:72] == 2'b00)
n_val[0] = 3'b100;
if (error == 1'b0)
begin
if (n_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 1);
end
n_mode_val[0] = "";
end
end
else if (scan_data[74] == 1'b1) // bypass
begin
if (scan_data[72] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 3);
end
else begin
if (n_mode_val[0] != "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 4);
end
n_val[0] = 2'b01;
n_mode_val[0] = "bypass";
end
end
end
else begin // pll type is auto or enhanced
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[124] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[133] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
$display ("Time: %0t Instance: %m", $time);
end
end
else if (tmp_scan_data[133] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[123:116] === 8'b00000000)
c_high_val_tmp[i] = 9'b100000000;
else
c_high_val_tmp[i] = {1'b0, tmp_scan_data[123:116]};
if (tmp_scan_data[132:125] === 8'b00000000)
c_low_val_tmp[i] = 9'b100000000;
else
c_low_val_tmp[i] = {1'b0, tmp_scan_data[132:125]};
tmp_scan_data = tmp_scan_data << 18;
end
// the phase_taps
tmp_scan_data = scan_data;
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
// cntrs M/M2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
m_val_tmp[i] = {1'b0, tmp_scan_data[142:134]};
if (tmp_scan_data[143] !== 1'b1)
begin
if (tmp_scan_data[142:134] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 2);
else
d_msg = display_msg("M2", 2);
end
else if (tmp_scan_data[142:134] == 9'b000000000)
m_val_tmp[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" M", 1);
else
d_msg = display_msg("M2", 1);
end
m_mode_val[i] = "";
end
end
else if (tmp_scan_data[143] == 1'b1)
begin
if (tmp_scan_data[134] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 3);
else
d_msg = display_msg("M2", 3);
end
else begin
if (m_mode_val[i] !== "bypass")
begin
// Mode is switched: give warning
if (i == 0)
d_msg = display_msg(" M", 4);
else
d_msg = display_msg("M2", 4);
end
m_val_tmp[i] = 10'b0000000001;
m_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (m_mode_val[0] != m_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
// cntrs N/N2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
n_val[i] = 0;
n_val[i] = {1'b0, tmp_scan_data[162:154]};
if (tmp_scan_data[163] !== 1'b1)
begin
if (tmp_scan_data[162:154] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 2);
else
d_msg = display_msg("N2", 2);
end
else if (tmp_scan_data[162:154] == 9'b000000000)
n_val[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 1);
else
d_msg = display_msg("N2", 1);
end
n_mode_val[i] = "";
end
end
else if (tmp_scan_data[163] == 1'b1) // bypass
begin
if (tmp_scan_data[154] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 3);
else
d_msg = display_msg("N2", 3);
end
else begin
if (n_mode_val[i] != "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 4);
else
d_msg = display_msg("N2", 4);
end
n_val[i] = 10'b0000000001;
n_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (n_mode_val[0] != n_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val_tmp[0], c_mode_val_tmp[0],
c_high_val_tmp[1]+c_low_val_tmp[1], c_mode_val_tmp[1],
c_high_val_tmp[2]+c_low_val_tmp[2], c_mode_val_tmp[2],
c_high_val_tmp[3]+c_low_val_tmp[3], c_mode_val_tmp[3],
c_high_val_tmp[4]+c_low_val_tmp[4], c_mode_val_tmp[4],
c_high_val_tmp[5]+c_low_val_tmp[5], c_mode_val_tmp[5],
refclk_period, m_val_tmp[0]);
quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old;
// get quiet time in terms of scanclk cycles
my_rem = quiet_time % scanclk_period;
scanclk_cycles = quiet_time/scanclk_period;
if (my_rem != 0)
scanclk_cycles = scanclk_cycles + 1;
scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1;
end
scanwrite_last_value = scanwrite_enabled;
end
always @(schedule_vco or areset_ipd or ena_pll)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
pll_is_in_reset = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// areset deasserted : note time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
if ((ena_pll === 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time <= $time))
schedule_vco = ~ schedule_vco;
end
// if ena was deasserted
if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : %s PLL is disabled", family_name);
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
if (ena_pll == 1'b1 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : %s PLL is enabled", family_name);
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 0;
if ((areset_ipd !== 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
if ( ($time == 0 && first_schedule == 1'b1) || (schedule_vco !== schedule_vco_last_value && (stop_vco !== 1'b1) && (ena_pll === 1'b1) && (areset_ipd !== 1'b1)) )
begin
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
if (op_mode == 1)
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val[0] * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus);
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (op_mode == 1)
begin
pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_M = initial_delay + fbk_phase;
end
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
if (op_mode == 1)
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule tap 0
vco_out[0] <= #(sched_time) vco_val;
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule tap 0
vco_out[0] <= #(sched_time) vco_val;
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
next_vco_sched_time = $time + sched_time;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_pll;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : %s PFDENA was deasserted", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (scanwrite_enabled === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
else if (!pll_is_locked && ($time - refclk_time > 2 * refclk_period) && pfdena_ipd === 1'b1)
begin
inclk_out_of_range = 1;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 1'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 1'b0;
assign clk_out[0] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx;
assign clk_out[1] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx;
assign clk_out[2] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx;
assign clk_out[3] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx;
assign clk_out[4] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx;
assign clk_out[5] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[5] : 1'bx;
assign sclkout0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout0_tmp : 1'bx;
assign sclkout1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout1_tmp : 1'bx;
assign enable_0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable0_tmp : 1'bx;
assign enable_1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable1_tmp : 1'bx;
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (clk[5], 1'b1, clk_out[5]);
and (sclkout[0], 1'b1, sclkout0);
and (sclkout[1], 1'b1, sclkout1);
and (enable0, 1'b1, enable_0);
and (enable1, 1'b1, enable_1);
and (scandataout, 1'b1, scandataout_tmp);
and (scandone, 1'b1, scandone_tmp);
endmodule // stratixii_pll
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_REGISTER
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_register (
datain,
clk,
aclr,
ena,
bypass_register,
dataout
);
//PARAMETER
parameter data_width = 18;
//INPUT PORTS
input[data_width -1 :0] datain;
input clk;
input aclr;
input ena;
input bypass_register;
//OUTPUT PORTS
output [data_width -1 :0] dataout;
//INTERNAL SIGNALS
wire [data_width -1:0] dataout_tmp;
reg [data_width -1:0] dataout_reg; //registered data
reg viol_notifier;
reg prev_clk_val;
wire [data_width -1 :0] datain_ipd;
wire clk_ipd;
wire aclr_ipd;
wire ena_ipd;
buf buf_datain [data_width -1 :0] (datain_ipd,datain);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_ena (ena_ipd,ena);
wire [data_width -1 :0] dataout_opd;
buf buf_dataout [data_width -1 :0] (dataout,dataout_opd);
//TIMING SPECIFICATION
specify
specparam TSU = 0; // Set up time
specparam TH = 0; // Hold time
specparam TCO = 0; // Clock to Output time
specparam TCLR = 0; // Clear time
specparam TCLR_MIN_PW = 0; // Minimum pulse width of clear
specparam TPRE = 0; // Preset time
specparam TPRE_MIN_PW = 0; // Minimum pulse width of preset
specparam TCLK_MIN_PW = 0; // Minimum pulse width of clock
specparam TCE_MIN_PW = 0; // Minimum pulse width of clock enable
specparam TCLKL = 0; // Minimum clock low time
specparam TCLKH = 0; // Minimum clock high time
$setup (datain, posedge clk, 0, viol_notifier);
$hold (posedge clk, datain, 0, viol_notifier);
$setup (ena, posedge clk, 0, viol_notifier );
$hold (posedge clk, ena, 0, viol_notifier );
(posedge aclr => (dataout +: 'b0)) = (0,0);
(posedge clk => (dataout +: dataout_tmp)) = (0,0);
endspecify
initial
begin
dataout_reg = 0;
end
//Register the datain
always @(clk_ipd or posedge aclr_ipd)
begin
if (aclr_ipd == 1'b1)
dataout_reg <= 0;
else if (prev_clk_val == 1'b0 && clk_ipd == 1'b1)
begin
if (ena_ipd == 1'b1)
dataout_reg <= datain_ipd;
else
dataout_reg <= dataout_reg;
end
prev_clk_val = clk_ipd;
end
//assign the dataout depending on the bypass_register value
assign dataout_opd = bypass_register ? datain_ipd :dataout_reg ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_MULT_BLOCK
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_mult_block (
dataa,
datab,
signa,
signb,
bypass_multiplier,
scanouta,
scanoutb,
dataout
);
//PARAMETER
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
parameter dynamic_mode = "no";
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input bypass_multiplier;
//OUTPUT PORTS
output [dataa_width-1:0] scanouta;
output [datab_width-1:0] scanoutb;
output [dataout_width -1 :0] dataout;
//INTERNAL SIGNALS
wire [dataout_width -1:0] product; //product of dataa and datab
wire [dataout_width -1:0] abs_product; //|product| of dataa and datab
wire [dataa_width-1:0] abs_a; //absolute value of dataa
wire [datab_width-1:0] abs_b; //absolute value of dadab
wire product_sign; // product sign bit
wire dataa_sign; //dataa sign bit
wire datab_sign; //datab sign bit
wire [dataa_width-1:0] dataa_ipd;
wire [datab_width-1:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire bypass_multiplier_ipd;
buf buf_dataa [dataa_width-1:0] (dataa_ipd,dataa);
buf buf_datab [datab_width-1:0] (datab_ipd,datab);
buf buf_signa (signa_ipd,signa);
buf buf_signb (signb_ipd,signb);
buf buf_bypass_multiplier (bypass_multiplier_ipd,bypass_multiplier);
wire [dataa_width-1:0] scanouta_opd;
wire [datab_width-1:0] scanoutb_opd;
wire [dataout_width -1 :0] dataout_opd;
buf buf_scanouta [dataa_width-1:0] (scanouta,scanouta_opd);
buf buf_scanoutb [datab_width-1:0] (scanoutb,scanoutb_opd);
buf buf_dataout [dataout_width -1 :0] (dataout,dataout_opd);
//TIMING SPECIFICATION
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(bypass_multiplier *> dataout) = (0, 0);
(dataa => scanouta) = (0, 0);
(datab => scanoutb) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
//Output assignment
assign scanouta_opd = dataa_ipd;
assign scanoutb_opd = datab_ipd;
assign dataa_sign = dataa_ipd[dataa_width-1] && signa_ipd;
assign datab_sign = datab_ipd[datab_width-1] && signb_ipd;
assign product_sign = dataa_sign ^ datab_sign;
assign abs_a = dataa_sign ? (~dataa_ipd + 1) : dataa_ipd;
assign abs_b = datab_sign ? (~datab_ipd + 1) : datab_ipd;
assign abs_product = abs_a * abs_b;
assign product = product_sign ? (~abs_product + 1) : abs_product;
assign dataout_opd = ((dynamic_mode == "yes") && (bypass_multiplier_ipd)) ? {datab_ipd, dataa_ipd} : ((bypass_multiplier_ipd) ? {dataa_ipd,datab_ipd} : product);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_RS_BLOCK
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_rs_block(
operation,
round,
saturate,
addnsub,
signa,
signb,
signsize,
roundsize,
dataoutsize,
dataa,
datab,
datain,
dataout
);
//PARAMETERS
parameter block_type = "mac_mult";
parameter dataa_width = 18;
parameter datab_width = 18;
//INPUT PORTS
input round;
input saturate;
input addnsub;
input signa;
input signb;
input [3:0] operation;
input [5:0] signsize;
input [7:0] roundsize;
input [7:0] dataoutsize;
input [71:0] dataa;
input [71:0] datab;
input [71:0] datain;
//OUTPUT PORTS
output [71:0] dataout;
//INTERNAL SIGNALS
reg [71:0] dataout_round;
reg [71:0] dataout_saturate;
reg [71:0] dataout_dly;
reg saturated;
reg [71:0] min;
reg [71:0] max;
wire [71:0] rs_saturate;
wire [71:0] rs_mac_mult;
wire [71:0] rs_mac_out;
reg msb;
integer i;
reg [6:0] dataa_local;
reg [6 :0] datab_local;
reg [6:0] width_local;
reg[72:0] dataout_saturate_tmp;
reg[73:0] max_tmp;
reg[73:0] min_tmp;
wire round_ipd;
wire saturate_ipd;
wire addnsub_ipd;
wire signa_ipd;
wire signb_ipd;
wire [71:0]dataa_ipd;
wire [71:0]datab_ipd;
wire [71:0]datain_ipd;
buf buf_round (round_ipd,round);
buf buf_saturate (saturate_ipd,saturate);
buf buf_addnsub (addnsub_ipd,addnsub);
buf buf_signa (signa_ipd,signa);
buf buf_signb (signb_ipd,signb);
buf buf_dataa [71:0](dataa_ipd,dataa);
buf buf_datab [71:0](datab_ipd,datab);
buf buf_datain [71:0](datain_ipd,datain);
wire [71:0] dataout_opd;
buf buf_dataout [71:0] (dataout,dataout_opd);
initial
begin
dataa_local = 7'd0;
datab_local = 7'd0;
width_local = 7'd0;
end
// TIMING SPECIFICATION
specify
(round *> dataout) = (0, 0);
(saturate *> dataout) = (0, 0);
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(datain *> dataout) = (0, 0);
endspecify
always @ (datain_ipd or round_ipd)
begin
if(round_ipd)
dataout_round = datain_ipd +(1 << (dataoutsize - signsize - roundsize -1));
else
dataout_round = datain_ipd;
end
always @ (operation or dataa_ipd or datab_ipd or datain_ipd or signa_ipd or signb_ipd or round_ipd or saturate_ipd or addnsub_ipd or dataout_round)
begin
if(saturate_ipd)
begin
if (block_type == "mac_mult")
begin
if (!dataout_round[dataa_width+datab_width-1] &&
dataout_round[dataa_width+datab_width-2])
begin
dataout_saturate_tmp[72:0] = {{(74-dataa_width-datab_width){1'b0}},{(dataa_width+datab_width-1){1'b1}}};
dataout_saturate[71:0] = dataout_saturate_tmp[72:1];
min = dataout_saturate;
max = dataout_saturate;
saturated = 1'b1;
end
else
begin
dataout_saturate = dataout_round;
saturated = 1'b0;
end
end
else if ((operation[2] == 1'b1) &&
((block_type == "R") ||
(block_type == "T")))
begin
saturated = 1'b0;
if(datab_width > 1)
datab_local = datab_width-2;
for (i = datab_local; i < (datab_width + signsize - 2); i = i + 1)
begin
if(dataout_round[datab_local] != dataout_round[i])
saturated = 1'b1;
end
if(saturated)
begin
max_tmp[73:0] = {{(74 - datab_width){1'b1}},{(datab_width){1'b0}}};
min_tmp[73:0] = {{(74 - datab_width){1'b0}},{(datab_width){1'b1}}};
max[71:0] = max_tmp[73:2];
min[71:0] = min_tmp[73:2];
end
else
begin
dataout_saturate = dataout_round;
end
msb = dataout_round[datab_width+15];
end
else
begin
if(signa_ipd || signb_ipd || ~addnsub_ipd)
begin
min = 1 << dataa_width;
max = (1 << dataa_width)-1;
end
else
begin
min = 0;
max = (1 << (dataa_width + 1))-1;
end
saturated = 1'b0;
if(dataa_width > 1 )
dataa_local = dataa_width-2;
for (i = dataa_local; i < (dataa_width + signsize - 1); i = i + 1)
begin
if(dataout_round[dataa_local] != dataout_round[i])
saturated = 1'b1;
end
msb = dataout_round[i];
end
if(saturated)
begin
if(msb)
dataout_saturate = max;
else
dataout_saturate = min;
end
else
dataout_saturate = dataout_round;
end
else
begin
saturated = 1'b0;
dataout_saturate = dataout_round;
end
end
always @ (round_ipd or dataout_saturate)
begin
if(round_ipd)
begin
dataout_dly = dataout_saturate;
width_local = dataoutsize - signsize - roundsize;
if(width_local > 0)
begin
for (i = 0; i < width_local; i = i + 1)
dataout_dly[i] = 1'b0;
end
end
else
dataout_dly = dataout_saturate;
end
assign rs_mac_mult = (saturate_ipd && (block_type == "mac_mult") && saturated)
?({dataout_dly[71:3], 2'b0, saturated})
: rs_mac_out;
assign rs_mac_out = (saturate_ipd && (block_type != "mac_mult"))
? ({dataout_dly[71:3],saturated, datain_ipd[1:0]})
: dataout_dly;
assign rs_saturate = saturate_ipd ? rs_mac_mult : rs_mac_out;
assign dataout_opd = ((operation == 4'b0000) || (operation == 4'b0111)) ? datain_ipd : rs_saturate;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_MULT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_mult(
dataa,
datab,
scanina,
scaninb,
sourcea,
sourceb,
signa,
signb,
round,
saturate,
clk,
aclr,
ena,
mode,
zeroacc,
dataout,
scanouta,
scanoutb,
devclrn,
devpor
);
//PARAMETERS
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter round_clock = "none";
parameter saturate_clock = "none";
parameter output_clock = "none";
parameter dataa_clear = "none";
parameter datab_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter round_clear = "none";
parameter saturate_clear = "none";
parameter output_clear = "none";
parameter bypass_multiplier = "no";
parameter mode_clock = "none";
parameter zeroacc_clock = "none";
parameter mode_clear = "none";
parameter zeroacc_clear = "none";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter signa_internally_grounded = "false";
parameter signb_internally_grounded = "false";
parameter lpm_hint = "true";
parameter lpm_type = "stratixii_mac_mult";
parameter dynamic_mode = "no";
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input [dataa_width-1:0] scanina;
input [datab_width-1:0] scaninb;
input sourcea;
input sourceb;
input signa;
input signb;
input round;
input saturate;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input mode;
input zeroacc;
input devclrn;
input devpor;
//OUTPUT PORTS
output [dataout_width-1:0] dataout;
output [dataa_width-1:0] scanouta;
output [datab_width-1:0] scanoutb;
tri1 devclrn;
tri1 devpor;
//Internal Signals
wire [dataa_width-1:0] dataa_in; //dataa or scaninA depending on sourceA
wire [datab_width-1:0] datab_in;//datab or scaninB depending on sourceB
//Internal signals to instantiate the dataa input register unit
wire [3:0] dataa_clk_value;
wire [3:0] dataa_aclr_value;
wire dataa_clk;
wire dataa_aclr;
wire dataa_ena;
wire dataa_bypass_register;
wire [dataa_width-1:0] dataa_in_reg;
//Internal signals to instantiate the datab input register unit
wire [3:0] datab_clk_value;
wire [3:0] datab_aclr_value;
wire datab_clk;
wire datab_aclr;
wire datab_ena;
wire datab_bypass_register;
wire [datab_width-1:0] datab_in_reg;
//Internal signals to instantiate the signa input register unit
wire [3:0] signa_clk_value;
wire [3:0] signa_aclr_value;
wire signa_clk;
wire signa_aclr;
wire signa_ena;
wire signa_bypass_register;
wire signa_in_reg;
//Internal signals to instantiate the signb input register unit
wire [3:0] signb_clk_value;
wire [3:0] signb_aclr_value;
wire signb_clk;
wire signb_aclr;
wire signb_ena;
wire signb_bypass_register;
wire signb_in_reg;
//Internal signals to instantiate the round input register unit
wire [3:0] round_clk_value;
wire [3:0] round_aclr_value;
wire round_clk;
wire round_aclr;
wire round_ena;
wire round_bypass_register;
wire round_in_reg;
//Internal signals to instantiate the saturate input register unit
wire [3:0] saturate_clk_value;
wire [3:0] saturate_aclr_value;
wire saturate_clk;
wire saturate_aclr;
wire saturate_ena;
wire saturate_bypass_register;
wire saturate_in_reg;
//Internal signals to instantiate the mode input register unit
wire [3:0] mode_clk_value;
wire [3:0] mode_aclr_value;
wire mode_clk;
wire mode_aclr;
wire mode_ena;
wire mode_bypass_register;
wire mode_in_reg;
//Internal signals to instantiate the zeroacc input register unit
wire [3:0] zeroacc_clk_value;
wire [3:0] zeroacc_aclr_value;
wire zeroacc_clk;
wire zeroacc_aclr;
wire zeroacc_ena;
wire zeroacc_bypass_register;
wire zeroacc_in_reg;
//Internal signals to instantiate the multiplier block
wire bypass_mult;
wire signa_mult;
wire signb_mult;
wire [dataa_width-1:0] scanouta_mult;
wire [datab_width-1:0] scanoutb_mult;
wire [dataout_width-1:0] dataout_mult;
//Internal signals to instantiate round and saturate block
wire[7:0] mac_rs_dataout_size;
wire [71:0] mac_rs_dataa;
wire [71:0] mac_rs_datab;
wire [71:0] mac_rs_datain;
wire [71:0] mac_rs_dataout;
wire [71:0] dataout_reg;
//Internal signals to instantiate the output register unit
wire [3:0] output_clk_value;
wire [3:0] output_aclr_value;
wire output_clk;
wire output_aclr;
wire output_ena;
wire output_bypass_register;
//Select the scanin data or the multiplier data
assign dataa_in = (sourcea == 1'b1) ? scanina : dataa;
assign datab_in = (sourceb == 1'b1) ? scaninb : datab;
//Instantiate the dataa input Register
stratixii_mac_register dataa_input_register (
.datain(dataa_in),
.clk(dataa_clk),
.aclr(dataa_aclr),
.ena(dataa_ena),
.bypass_register(dataa_bypass_register),
.dataout(dataa_in_reg)
);
defparam dataa_input_register.data_width = dataa_width;
//decode the clk and aclr values
assign dataa_clk_value =((dataa_clock == "0") || (dataa_clock == "none")) ? 4'b0000 :
(dataa_clock == "1") ? 4'b0001 :
(dataa_clock == "2") ? 4'b0010 :
(dataa_clock == "3") ? 4'b0011 : 4'b0000;
assign dataa_aclr_value = ((dataa_clear == "0") ||(dataa_clear == "none")) ? 4'b0000 :
(dataa_clear == "1") ? 4'b0001 :
(dataa_clear == "2") ? 4'b0010 :
(dataa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign dataa_clk = clk[dataa_clk_value] ? 'b1 : 'b0;
assign dataa_aclr = aclr[dataa_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign dataa_ena = ena[dataa_clk_value] ? 'b1 : 'b0;
assign dataa_bypass_register = (dataa_clock == "none") ? 'b1 : 'b0;
//Instantiate the datab input Register
stratixii_mac_register datab_input_register (
.datain(datab_in),
.clk(datab_clk),
.aclr(datab_aclr),
.ena(datab_ena),
.bypass_register(datab_bypass_register),
.dataout(datab_in_reg)
);
defparam datab_input_register.data_width = datab_width;
//decode the clk and aclr values
assign datab_clk_value =((datab_clock == "0") || (datab_clock == "none")) ? 4'b0000 :
(datab_clock == "1") ? 4'b0001 :
(datab_clock == "2") ? 4'b0010 :
(datab_clock == "3") ? 4'b0011 : 4'b0000;
assign datab_aclr_value = ((datab_clear == "0") ||(datab_clear == "none")) ? 4'b0000 :
(datab_clear == "1") ? 4'b0001 :
(datab_clear == "2") ? 4'b0010 :
(datab_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign datab_clk = clk[datab_clk_value] ? 'b1 : 'b0;
assign datab_aclr = aclr[datab_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign datab_ena = ena[datab_clk_value] ? 'b1 : 'b0;
assign datab_bypass_register = (datab_clock == "none") ? 'b1 : 'b0;
//Instantiate the signa input Register
stratixii_mac_register signa_input_register (
.datain(signa),
.clk(signa_clk),
.aclr(signa_aclr),
.ena(signa_ena),
.bypass_register(signa_bypass_register),
.dataout(signa_in_reg)
);
defparam signa_input_register.data_width = 1;
//decode the clk and aclr values
assign signa_clk_value =((signa_clock == "0") || (signa_clock == "none")) ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclr_value = ((signa_clear == "0") ||(signa_clear == "none")) ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk = clk[signa_clk_value] ? 'b1 : 'b0;
assign signa_aclr = aclr[signa_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signa_ena = ena[signa_clk_value] ? 'b1 : 'b0;
assign signa_bypass_register = (signa_clock == "none") ? 'b1 : 'b0;
//Instantiate the signb input Register
stratixii_mac_register signb_input_register (
.datain(signb),
.clk(signb_clk),
.aclr(signb_aclr),
.ena(signb_ena),
.bypass_register(signb_bypass_register),
.dataout(signb_in_reg)
);
defparam signb_input_register.data_width = 1;
//decode the clk and aclr values
assign signb_clk_value =((signb_clock == "0") || (signb_clock == "none")) ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclr_value = ((signb_clear == "0") ||(signb_clear == "none")) ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk = clk[signb_clk_value] ? 'b1 : 'b0;
assign signb_aclr = aclr[signb_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signb_ena = ena[signb_clk_value] ? 'b1 : 'b0;
assign signb_bypass_register = (signb_clock == "none") ? 'b1 : 'b0;
//Instantiate the round input Register
stratixii_mac_register round_input_register (
.datain(round),
.clk(round_clk),
.aclr(round_aclr),
.ena(round_ena),
.bypass_register(round_bypass_register),
.dataout(round_in_reg)
);
defparam round_input_register.data_width = 1;
//decode the clk and aclr values
assign round_clk_value =((round_clock == "0") || (round_clock == "none")) ? 4'b0000 :
(round_clock == "1") ? 4'b0001 :
(round_clock == "2") ? 4'b0010 :
(round_clock == "3") ? 4'b0011 : 4'b0000;
assign round_aclr_value = ((round_clear == "0") ||(round_clear == "none")) ? 4'b0000 :
(round_clear == "1") ? 4'b0001 :
(round_clear == "2") ? 4'b0010 :
(round_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round_clk = clk[round_clk_value] ? 'b1 : 'b0;
assign round_aclr = aclr[round_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign round_ena = ena[round_clk_value] ? 'b1 : 'b0;
assign round_bypass_register = (round_clock == "none") ? 'b1 : 'b0;
//Instantiate the saturate input Register
stratixii_mac_register saturate_input_register (
.datain(saturate),
.clk(saturate_clk),
.aclr(saturate_aclr),
.ena(saturate_ena),
.bypass_register(saturate_bypass_register),
.dataout(saturate_in_reg)
);
defparam saturate_input_register.data_width = 1;
//decode the clk and aclr values
assign saturate_clk_value =((saturate_clock == "0") || (saturate_clock == "none")) ? 4'b0000 :
(saturate_clock == "1") ? 4'b0001 :
(saturate_clock == "2") ? 4'b0010 :
(saturate_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_aclr_value = ((saturate_clear == "0") ||(saturate_clear == "none")) ? 4'b0000 :
(saturate_clear == "1") ? 4'b0001 :
(saturate_clear == "2") ? 4'b0010 :
(saturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_clk = clk[saturate_clk_value] ? 'b1 : 'b0;
assign saturate_aclr = aclr[saturate_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign saturate_ena = ena[saturate_clk_value] ? 'b1 : 'b0;
assign saturate_bypass_register = (saturate_clock == "none") ? 'b1 : 'b0;
//Instantiate the mode input Register
stratixii_mac_register mode_input_register (
.datain(mode),
.clk(mode_clk),
.aclr(mode_aclr),
.ena(mode_ena),
.bypass_register(mode_bypass_register),
.dataout(mode_in_reg)
);
defparam mode_input_register.data_width = 1;
//decode the clk and aclr values
assign mode_clk_value =((mode_clock == "0") || (mode_clock == "none")) ? 4'b0000 :
(mode_clock == "1") ? 4'b0001 :
(mode_clock == "2") ? 4'b0010 :
(mode_clock == "3") ? 4'b0011 : 4'b0000;
assign mode_aclr_value = ((mode_clear == "0") ||(mode_clear == "none")) ? 4'b0000 :
(mode_clear == "1") ? 4'b0001 :
(mode_clear == "2") ? 4'b0010 :
(mode_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign mode_clk = clk[mode_clk_value] ? 'b1 : 'b0;
assign mode_aclr = aclr[mode_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign mode_ena = ena[mode_clk_value] ? 'b1 : 'b0;
assign mode_bypass_register = (mode_clock == "none") ? 'b1 : 'b0;
//Instantiate the zeroacc input Register
stratixii_mac_register zeroacc_input_register (
.datain(zeroacc),
.clk(zeroacc_clk),
.aclr(zeroacc_aclr),
.ena(zeroacc_ena),
.bypass_register(zeroacc_bypass_register),
.dataout(zeroacc_in_reg)
);
defparam zeroacc_input_register.data_width = 1;
//decode the clk and aclr values
assign zeroacc_clk_value =((zeroacc_clock == "0") || (zeroacc_clock == "none")) ? 4'b0000 :
(zeroacc_clock == "1") ? 4'b0001 :
(zeroacc_clock == "2") ? 4'b0010 :
(zeroacc_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_aclr_value = ((zeroacc_clear == "0") ||(zeroacc_clear == "none")) ? 4'b0000 :
(zeroacc_clear == "1") ? 4'b0001 :
(zeroacc_clear == "2") ? 4'b0010 :
(zeroacc_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_clk = clk[zeroacc_clk_value] ? 'b1 : 'b0;
assign zeroacc_aclr = aclr[zeroacc_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign zeroacc_ena = ena[zeroacc_clk_value] ? 'b1 : 'b0;
assign zeroacc_bypass_register = (zeroacc_clock == "none") ? 'b1 : 'b0;
//Instantiate mac_multiplier block
stratixii_mac_mult_block mac_multiplier (
.dataa(dataa_in_reg),
.datab(datab_in_reg),
.signa(signa_mult),
.signb(signb_mult),
.bypass_multiplier(bypass_mult),
.scanouta(scanouta_mult),
.scanoutb(scanoutb_mult),
.dataout(dataout_mult)
);
defparam mac_multiplier.dataa_width = dataa_width;
defparam mac_multiplier.datab_width = datab_width;
defparam mac_multiplier.dynamic_mode = dynamic_mode;
assign signa_mult = ((signa_internally_grounded == "true")
&&(dynamic_mode == "no")) ||
((signa_internally_grounded == "true") &&
(dynamic_mode == "yes")
&&(zeroacc_in_reg == 1'b1)
&&(mode_in_reg == 1'b0)
) ? 1'b0 : signa_in_reg;
assign signb_mult = ((signb_internally_grounded == "true")
&&(dynamic_mode == "no")) ||
((signb_internally_grounded == "true") &&
(dynamic_mode == "yes")
&&(zeroacc_in_reg == 1'b1)
&&(mode_in_reg == 1'b0)
) ? 1'b0 : signb_in_reg;
assign bypass_mult = ((bypass_multiplier == "yes")
&&(dynamic_mode == "no")) ||
((bypass_multiplier == "yes")&&
(dynamic_mode == "yes")
&&(mode_in_reg == 'b1)
) ? 1'b1 : 1'b0;
//Instantiate round and saturate block
stratixii_mac_rs_block mac_rs_block(
.operation(4'b1111),
.round(round_in_reg),
.saturate(saturate_in_reg),
.addnsub(1'b0),
.signa(signa_in_reg),
.signb(signb_in_reg),
.signsize(6'd2),
.roundsize(8'd15),
.dataoutsize(mac_rs_dataout_size),
.dataa(mac_rs_dataa),
.datab(mac_rs_datab),
.datain(mac_rs_datain),
.dataout(mac_rs_dataout)
);
defparam mac_rs_block.block_type = "mac_mult";
defparam mac_rs_block.dataa_width = dataa_width;
defparam mac_rs_block.datab_width = datab_width;
assign mac_rs_dataout_size = dataa_width + datab_width;
assign mac_rs_dataa = scanouta_mult;
assign mac_rs_datab = scanoutb_mult;
assign mac_rs_datain = dataout_mult;
assign dataout_reg = (bypass_mult == 1'b1) ? mac_rs_datain : mac_rs_dataout;
stratixii_mac_register mult_output_register(
.datain(dataout_reg[dataout_width -1:0]),
.clk(output_clk),
.aclr(output_aclr),
.ena(output_ena),
.bypass_register(output_bypass_register),
.dataout(dataout)
);
defparam mult_output_register.data_width = dataout_width;
//decode the clk and aclr values
assign output_clk_value =((output_clock == "0") || (output_clock == "none")) ? 4'b0000 :
(output_clock == "1") ? 4'b0001 :
(output_clock == "2") ? 4'b0010 :
(output_clock == "3") ? 4'b0011 : 4'b0000;
assign output_aclr_value = ((output_clear == "0") ||(output_clear == "none")) ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign output_clk = clk[output_clk_value] ? 'b1 : 'b0;
assign output_aclr = aclr[output_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign output_ena = ena[output_clk_value] ? 'b1 : 'b0;
assign output_bypass_register = (output_clock == "none") ? 'b1 : 'b0;
//assign the scanout values
assign scanouta = dataa_in_reg;
assign scanoutb = datab_in_reg;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_OUT_Input_Interface
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_mac_out_input_interface(
accuma,
accumc,
dataa,
datab,
datac,
datad,
sign,
multabsaturate,
multcdsaturate,
zeroacc,
zeroacc1,
operation,
outa,
outb,
outc,
outd,
sata,
satb,
satc,
satd,
satab,
satcd
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter accuma_width = datab_width + 16;
parameter accumc_width = datad_width + 16;
// INPUT PORTS
input [51:0] accuma;
input [51:0] accumc;
input [71:0] dataa;
input [71:0] datab;
input [71:0] datac;
input [71:0] datad;
input sign;
input multabsaturate;
input multcdsaturate;
input zeroacc;
input zeroacc1;
input [3:0] operation;
// OUTPUT PORTS
output [71:0] outa;
output [71:0] outb;
output [71:0] outc;
output [71:0] outd;
output sata;
output satb;
output satc;
output satd;
output satab;
output satcd;
// INTERNAL SIGNALS
reg [71:0] outa_tmp;
reg [71:0] outb_tmp;
reg [71:0] outc_tmp;
reg [71:0] outd_tmp;
reg sata_tmp;
reg satb_tmp;
reg satc_tmp;
reg satd_tmp;
reg satab_tmp;
reg satcd_tmp;
integer i,j;
reg[6:0] width_tmp;
//sign extended signals
wire [71:0] dataa_se;
wire [71:0] datab_se;
wire [71:0] datac_se;
wire [71:0] datad_se;
wire [71:0] accuma_se;
wire [71:0] accumc_se;
initial
begin
width_tmp = 7'd0;
end
assign outa = outa_tmp;
assign outb = outb_tmp;
assign outc = outc_tmp;
assign outd = outd_tmp;
assign sata = sata_tmp;
assign satb = satb_tmp;
assign satc = satc_tmp;
assign satd = satd_tmp;
assign satab = satab_tmp;
assign satcd = satcd_tmp;
//Sign Extension for inputs
assign dataa_se = (dataa[dataa_width-1]&& sign)
?{{(72-dataa_width){1'b1}},dataa[dataa_width -1 : 0]}
:{{(72-dataa_width){1'b0}},dataa[dataa_width -1 : 0]} ;
assign datab_se = (datab[datab_width-1]&& sign)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]} ;
assign datac_se = (datac[datac_width-1]&& sign)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]} ;
assign datad_se = (datad[datad_width-1]&& sign)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]} ;
assign accuma_se = (accuma[accuma_width-1]&& sign)
?{{(72-accuma_width){1'b1}},accuma[accuma_width -1 : 0]}
:{{(72-accuma_width){1'b0}},accuma[accuma_width -1 : 0]} ;
assign accumc_se = (accumc[accumc_width-1]&& sign)
?{{(72-accumc_width){1'b1}},accumc[accumc_width -1 : 0]}
:{{(72-accumc_width){1'b0}},accumc[accumc_width -1 : 0]} ;
always @ (accuma_se or
accumc_se or
dataa_se or
datab_se or
datac_se or
datad_se or
multabsaturate or
multcdsaturate or
zeroacc or
zeroacc1 or
operation)
begin
case (operation)
//Output Only
4'b0000 :
begin
outa_tmp = dataa_se;
outb_tmp = datab_se;
outc_tmp = datac_se;
outd_tmp = datad_se;
end
// ACCUMULATOR
4'b0100 :
begin
if(zeroacc == 1'b1)
begin
if(accuma_width > dataa_width)
width_tmp = accuma_width - dataa_width;
if(accuma_width > dataa_width)
begin
outa_tmp[71:accuma_width] = dataa_se[71:accuma_width];
j= 0;
for ( i = width_tmp; i < accuma_width; i = i+1)
begin
outa_tmp[i] = dataa[j];
j= j+1;
end
for( i = 0; i < width_tmp; i = i +1)
begin
outa_tmp[i]=1'b0;
end
end
else
begin
outa_tmp[71:accuma_width] = dataa_se[71:accuma_width];
j = dataa_width - accuma_width;
for( i = 0 ; i < accuma_width; i = i + 1)
begin
outa_tmp[i] = dataa[j];
j = j + 1;
end
end
end
else
outa_tmp = accuma_se;
outb_tmp = datab_se;
outc_tmp = datac_se;
outd_tmp = datad_se;
end
// TWO ACCUMULATORS
4'b1100 :
begin
case ({zeroacc1, zeroacc})
2'b00:
begin
outa_tmp = accuma_se;
outc_tmp = accumc_se;
end
2'b01:
begin
outa_tmp = {dataa_se[71:52],dataa[15:0],dataa[35:18],dataa[17:16],16'h0000};
outc_tmp = accumc_se;
end
2'b10:
begin
outa_tmp = accuma_se;
outc_tmp = {datac_se[71:52],datac[15:0],datac[35:18],datac[17:16],16'h0000};
end
2'b11:
begin
outa_tmp = {dataa_se[71:52],dataa[15:0],dataa[35:18],dataa[17:16],16'h0000};
outc_tmp = {datac_se[71:52],datac[15:0],datac[35:18],datac[17:16],16'h0000};
end
default :
begin
outa_tmp = accuma_se;
outc_tmp = accumc_se;
end
endcase
outb_tmp = datab_se;
outd_tmp = datad_se;
end
// OUTPUT_ONLY / ACCUMULATOR -- Dynamic Mode
4'b1101 :
begin
if(zeroacc == 1'b1)
outa_tmp = {dataa_se[71:52],dataa[15:0],dataa[35:18],dataa[17:16],16'h0000};
else
outa_tmp= accuma_se;
outb_tmp = datab_se;
outc_tmp = datac_se;
outd_tmp = datad_se;
end
//Accumulator /Output Only --Dynamic Mode
4'b1110 :
begin
if(zeroacc1 == 1'b1)
outc_tmp = {datac_se[71:52],datac[15:0],datac[35:18],datac[17:16],16'h0000};
else
outc_tmp = accumc_se;
outa_tmp = dataa_se;
outb_tmp = datab_se;
outd_tmp = datad_se;
end
default :
begin
outa_tmp = dataa_se;
outb_tmp = datab_se;
outc_tmp = datac_se;
outd_tmp = datad_se;
end
endcase
// MULTABSATURATE
if(multabsaturate)
begin
if(outa_tmp[0] == 1'b1 && ((zeroacc && operation[2]) || ~operation[2]))
begin
sata_tmp = 1'b1;
outa_tmp[0] = 1'b0;
end
else
sata_tmp = 1'b0;
if(outb_tmp[0] == 1'b1)
begin
satb_tmp = 1'b1;
outb_tmp[0] = 1'b0;
end
else
satb_tmp = 1'b0;
end
else
begin
sata_tmp = 1'b0;
satb_tmp = 1'b0;
end
// MULTCDSATURATE
if(multcdsaturate)
begin
if(outc_tmp[0] == 1'b1 && ((zeroacc1 && operation[2]) || ~operation[2]))
begin
satc_tmp = 1'b1;
outc_tmp[0] = 1'b0;
end
else
satc_tmp = 1'b0;
if(outd_tmp[0] == 1'b1)
begin
satd_tmp = 1'b1;
outd_tmp[0] = 1'b0;
end
else
satd_tmp = 1'b0;
end
else
begin
satc_tmp = 1'b0;
satd_tmp = 1'b0;
end
// SATURATE (A || B)
if(sata_tmp || satb_tmp)
satab_tmp = 1'b1;
else
satab_tmp = 1'b0;
// SATURATE (C || D)
if(satc_tmp || satd_tmp)
satcd_tmp = 1'b1;
else
satcd_tmp = 1'b0;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_OUT_ADD_SUB_ACC_UNIT
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_mac_out_add_sub_acc_unit(
dataa,
datab,
datac,
datad,
signa,
signb,
operation,
addnsub,
dataout,
overflow
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter accuma_width = datab_width + 16;
parameter accumc_width = datad_width + 16;
parameter block_type = "R";
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ]datab;
input [71 :0] datac;
input [71:0]datad;
input signa;
input signb;
input [3:0] operation;
input addnsub;
// OUTPUT PORTS
output [71 :0] dataout;
output overflow;
//INTERNAL SIGNALS
reg[71:0] dataout_tmp;
reg overflow_tmp;
reg sign_a;
reg sign_b;
reg [71 :0] abs_a;
reg [71 :0 ] abs_b;
reg [71:0] datac_s;
reg [71:0] datad_s;
//assign the output values
assign dataout = dataout_tmp;
assign overflow = overflow_tmp;
always @(dataa or datab or datac or datad or signa or signb or operation or addnsub)
begin
//36 bit multiply
if(operation == 4'b0111)
begin
datac_s = signa ? {{(18){datac[35]}}, datac[35:0]} : {{18'b0, datac[35:0]}};
datad_s = signb ? {{(18){datad[35]}}, datad[35:0]} : {{18'b0, datad[35:0]}};
dataout_tmp = ({datab[35:0],36'b0}) + ({datac_s,18'b0}) + ({datad_s,18'b0}) + ({36'b0,dataa[35:0]});
overflow_tmp = 1'b0;
end
// Accumulator, Block R
else if ((block_type == "R") &&(operation[2]))
begin
sign_a = (signa && dataa[accuma_width -1]);
abs_a = (sign_a) ? (~dataa[accuma_width -1 :0] + 1'b1) : dataa[accuma_width -1 :0];
sign_b = (signb && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab[datab_width -1 :0] + 1'b1) : datab[datab_width -1 :0];
if (addnsub == 1'b0)
dataout_tmp = (sign_a ? -abs_a[accuma_width -1 :0] : abs_a[accuma_width -1 :0]) - (sign_b ? -abs_b[datab_width -1 :0] : abs_b[datab_width -1 :0]);
else
dataout_tmp = (sign_a ? -abs_a[accuma_width -1 :0] : abs_a[accuma_width -1 :0]) + (sign_b ? -abs_b[datab_width -1 :0] : abs_b[datab_width -1 :0]);
if(signa || signb)
overflow_tmp = dataout_tmp[accuma_width] ^ dataout_tmp[accuma_width -1];
else
overflow_tmp = dataout_tmp[accuma_width];
end
//ACCUMULATOR, Block S
else if ((block_type == "S") &&(operation[2]))
begin
sign_a = (signa && datac[accumc_width -1]);
abs_a = (sign_a) ? (~datac[accumc_width -1 :0] + 1'b1) : datac[accumc_width -1 :0];
sign_b = (signb && datad[datad_width-1]);
abs_b = (sign_b) ? (~datad[datad_width -1 :0] + 1'b1) : datad[datad_width -1 :0];
if (addnsub == 1'b0)
dataout_tmp = (sign_a ? -abs_a[accumc_width -1 :0] : abs_a[accumc_width -1 :0]) - (sign_b ? -abs_b[datad_width -1 :0] : abs_b[datad_width -1 :0]);
else
dataout_tmp = (sign_a ? -abs_a[accumc_width -1 :0] : abs_a[accumc_width -1 :0]) + (sign_b ? -abs_b[datad_width -1 :0] : abs_b[datad_width -1 :0]);
if(signa || signb)
overflow_tmp = dataout_tmp[accumc_width] ^ dataout_tmp[accumc_width -1];
else
overflow_tmp = dataout_tmp[accumc_width];
end
// Two level adder
else if(block_type == "T")
begin
sign_a = ( signa && dataa[dataa_width]);
sign_b = ( signb && datab[datab_width]);
abs_a = ( sign_a ) ? (~dataa[dataa_width:0] + 1'b1) : dataa[dataa_width:0];
abs_b = ( sign_b ) ? (~datab[datab_width:0] + 1'b1) : datab[datab_width:0];
if (addnsub == 1'b0)
dataout_tmp = (sign_a ? -abs_a[dataa_width:0]: abs_a[dataa_width:0]) - (sign_b ? -abs_b[datab_width:0] : abs_b[datab_width:0]);
else
dataout_tmp = (sign_a ? -abs_a[dataa_width:0]: abs_a[dataa_width:0]) + (sign_b ? -abs_b[datab_width:0] : abs_b[datab_width:0]);
overflow_tmp = 1'b0;
end
//One level Adder S block
else if (block_type == "S")
begin
sign_a = (signa && datac[datac_width -1]);
abs_a = (sign_a) ? (~datac[datac_width -1:0]+ 1'b1) : datac[datac_width -1:0];
sign_b = (signb && datad[datad_width-1]);
abs_b = (sign_b) ? (~datad[datad_width -1:0] + 1'b1) : datad[datad_width -1:0];
if (addnsub == 1'b0)
dataout_tmp = (sign_a ? -abs_a[datac_width -1:0] : abs_a[datac_width -1:0]) - (sign_b ? -abs_b[datad_width -1:0] : abs_b[datad_width -1:0]);
else
dataout_tmp = (sign_a ? -abs_a[datac_width -1:0] : abs_a[datac_width -1:0]) + (sign_b ? -abs_b[datad_width -1:0] : abs_b[datad_width -1:0]);
if(signa || signb)
overflow_tmp = dataout_tmp[datac_width + 1] ^ dataout_tmp[datac_width];
else
overflow_tmp = dataout_tmp[datac_width + 1];
end
//One level Adder R block. Default
else
begin
sign_a = (signa && dataa[dataa_width -1]);
abs_a = (sign_a) ? (~dataa[dataa_width -1:0]+ 1'b1) : dataa[dataa_width -1:0];
sign_b = (signb && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab[datab_width -1:0] + 1'b1) : datab[datab_width -1:0];
if (addnsub == 1'b0)
dataout_tmp = (sign_a ? -abs_a[dataa_width -1:0] : abs_a[dataa_width -1:0]) - (sign_b ? -abs_b[datab_width -1:0] : abs_b[datab_width -1:0]);
else
dataout_tmp = (sign_a ? -abs_a[dataa_width -1:0] : abs_a[dataa_width -1:0]) + (sign_b ? -abs_b[datab_width -1:0] : abs_b[datab_width -1:0]);
if(signa || signb)
overflow_tmp = dataout_tmp[dataa_width + 1] ^ dataout_tmp[dataa_width];
else
overflow_tmp = dataout_tmp[dataa_width + 1];
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_OUT_Output_Interface
//
///////////////////////////////////////////////////////////////////////////////
module stratixii_mac_out_output_interface(
dataa,
datab,
datac,
datad,
datar,
datas,
datat,
data_36_mult,
sata,
satb,
satc,
satd,
satab,
satcd,
satr,
sats,
multabsaturate,
multcdsaturate,
saturate0,
saturate1,
overflowr,
overflows,
operation,
dataout,
accoverflow
);
// INPUT PORTS
input [35:0] dataa;
input [35:0] datab;
input [35:0] datac;
input [35:0] datad;
input [71:0] datar;
input [71:0] datas;
input [71:0] datat;
input [71:0] data_36_mult;
input sata;
input satb;
input satc;
input satd;
input satab;
input satcd;
input satr;
input sats;
input multabsaturate;
input multcdsaturate;
input saturate0;
input saturate1;
input overflowr;
input overflows;
input [3:0] operation;
// OUTPUT PORTS
output [143:0] dataout;
output accoverflow;
//INTERNAL SIGNALS
reg [143:0] dataout_tmp;
reg accoverflow_tmp;
always @( dataa or datab or datac or datad or data_36_mult or datar or datas or datat or
sata or satb or satc or satd or satab or satcd or satr or sats or multabsaturate or
multcdsaturate or saturate0 or saturate1 or overflowr or overflows or operation)
begin
case (operation)
//Output Only
4'b0000 :
begin
dataout_tmp = {datad,datac,datab,dataa};
accoverflow_tmp = 1'b0;
end
//Accumulator
4'b0100 :
begin
case ({saturate0, multabsaturate})
2'b00 :dataout_tmp ={datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:0]};
2'b01 :dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:2], satab, datar[0]};
2'b10 :dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:3], satr, datar[1:0]};
2'b11 : dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:3], satr, satab, datar[0]};
default : dataout_tmp = {datad,datac, datar[71:53], overflowr, datar[51:36], datar[35:0]};
endcase
accoverflow_tmp = overflowr;
end
// ONE LEVEL ADDER
4'b0001 :
begin
if (multabsaturate)
dataout_tmp = {datad,datac, datar[71:2], satb, sata};
else
dataout_tmp = {datad,datac, datar[71:0]};
accoverflow_tmp = 1'b0;
end
// TWO LEVEL ADDER
4'b0010 :
begin
case ({satcd, satab})
2'b00 :
begin
dataout_tmp = {datad,datac, datat[71:0]};
accoverflow_tmp = 1'b0;
end
2'b01 :
begin
dataout_tmp = {datad,datac, datat[71:2], satb, sata};
accoverflow_tmp = 1'b0;
end
2'b10 :
begin
dataout_tmp = {datad,datac, datat[71:3], satc, datat[1:0]};
accoverflow_tmp = satd;
end
2'b11 :
begin
dataout_tmp = {datad,datac, datat[71:3], satc, satb, sata};
accoverflow_tmp = satd;
end
default :
begin
dataout_tmp = {datad,datac, datat[71:0]};
accoverflow_tmp = 1'b0;
end
endcase
end
// 36-BIT MULTIPLY
4'b0111 :
begin
dataout_tmp = {datad,datac,data_36_mult};
accoverflow_tmp = 1'b0;
end
// TWO ACCUMULATORS
4'b1100 :
begin
case ({saturate1, saturate0, satcd, satab})
4'b0000 : dataout_tmp = {datas[71:53], overflows, datas[51:0],datar[71:53], overflowr, datar[51:0]};
4'b0001 : dataout_tmp = {datas[71:53], overflows, datas[51:0], datar[71:53], overflowr, datar[51:2], satab, datar[0]};
4'b0010 : dataout_tmp = {datas[71:53], overflows, datas[51:2], satcd, datas[0],datar[71:53], overflowr, datar[51:0]};
4'b0011 : dataout_tmp = {datas[71:53], overflows, datas[51:2], satcd, datas[0],datar[71:53], overflowr, datar[51:2], satab, datar[0]};
4'b0100 :dataout_tmp = {datas[71:53], overflows, datas[51:0], datar[71:53], overflowr, datar[51:3], satr, datar[1:0]};
4'b0101 :dataout_tmp = {datas[71:53], overflows, datas[51:0], datar[71:53], overflowr, datar[51:3], satr, satab, datar[0]};
4'b0110 :dataout_tmp = {datas[71:53], overflows, datas[51:2], satcd, datas[0],datar[71:53], overflowr, datar[51:3], satr, datar[1:0]};
4'b0111 :dataout_tmp = {datas[71:53], overflows, datas[51:2], satcd, datas[0],datar[71:53], overflowr, datar[51:3], satr, satab, datar[0]};
4'b1000 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, datas[1:0], datar[71:53], overflowr, datar[51:0]};
4'b1001 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, datas[1:0], datar[71:53], overflowr, datar[51:2], satab, datar[0]};
4'b1010 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, satcd, datas[0],datar[71:53], overflowr, datar[51:0]};
4'b1011 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, satcd, datas[0],datar[71:53], overflowr, datar[51:2], satab, datar[0]};
4'b1100 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, datas[1:0], datar[71:53], overflowr, datar[51:3], satr, datar[1:0]};
4'b1101 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, datas[1:0], datar[71:53], overflowr, datar[51:3], satr, satab, datar[0]};
4'b1110 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, satcd, datas[0],datar[71:53], overflowr, datar[51:3], satr, datar[1:0]};
4'b1111 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, satcd, datas[0],datar[71:53], overflowr, datar[51:3], satr, satab, datar[0]};
default :dataout_tmp = {datas[71:53], overflows, datas[51:0],datar[71:53], overflowr, datar[51:0]};
endcase
accoverflow_tmp = overflowr;
end
// OUTPUT ONLY / ACCUMULATOR
4'b1101 :
begin
case ({saturate0, multabsaturate})
2'b00 :dataout_tmp ={datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:0]};
2'b01 :dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:2], satab, datar[0]};
2'b10 :dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:3], satr, datar[1:0]};
2'b11 : dataout_tmp = {datad,datac, datar[71:53], overflowr,datar[51:36], datar[35:3], satr, satab, datar[0]};
default : dataout_tmp = {datad,datac, datar[71:53], overflowr, datar[51:36], datar[35:0]};
endcase
accoverflow_tmp = overflowr;
end
// ACCUMULATOR / OUTPUT ONLY
4'b1110 :
begin
case ({saturate1, multcdsaturate})
2'b00 :dataout_tmp = {datas[71:53], overflows, datas[51:0],datab,dataa};
2'b01 : dataout_tmp = {datas[71:53], overflows, datas[51:2], satcd, datas[0],datab,dataa};
2'b10 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, datas[1:0],datab,dataa};
2'b11 :dataout_tmp = {datas[71:53], overflows, datas[51:3], sats, satcd, datas[0],datab,dataa};
default :dataout_tmp = {datas[71:53], overflows, datas[51:0],datab,dataa};
endcase
accoverflow_tmp = overflows;
end
default :
begin
dataout_tmp = {datad,datac,datab,dataa};
accoverflow_tmp = 1'b0;
end
endcase
end
assign dataout = dataout_tmp;
assign accoverflow = accoverflow_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_Reooder_Output
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_reorder_output(
datain,
addnsub,
operation,
dataout
);
//PARAMETERS
parameter operation_mode = "dynamic";
//INPUT PORTS
input [143:0] datain;
input [3:0] operation;
input addnsub;
//OUTPUT PORTS
output [143:0] dataout;
//INTERNAL SIGNALS
reg [143:0] dataout_tmp;
wire [3:0] operation;
//Output Assignment
assign dataout = dataout_tmp;
always @ (datain or addnsub)
begin
if(operation_mode == "dynamic")
begin
case (operation)
4'b1100 : // TWO ACCUMULATORS
dataout_tmp = {18'bX, datain[124:108],1'bX, datain[107:72],18'bX, datain[52:36], 1'bX, datain[35:0]};
4'b1101 : // OUTPUT ONLY / ACCUMULATOR
dataout_tmp = {datain[143:72], 18'bX, datain[52:36], 1'bX, datain[35:0]};
4'b1110 :// ACCUMULATOR / OUTPUT ONLY
dataout_tmp = {18'bX, datain[124:108], 1'bX, datain[107:0]};
4'b0111 :
begin // 36 BIT MULTIPLY
dataout_tmp[17:0] = (addnsub) ? datain[17:0] : 18'bX;
dataout_tmp[35:18] = (addnsub) ? datain[53:36] : 18'bX;
dataout_tmp[53:36] = (addnsub) ? datain[35:18] : 18'bX;
dataout_tmp[71:54] = (addnsub) ? datain[71:54] : 18'bX;
dataout_tmp[143:72] = 72'bX;
end
default :
dataout_tmp = datain;
endcase
end
else
dataout_tmp = datain;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_OUT_Internal_Logic
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_out_internal (
dataa,
datab,
datac,
datad,
mode0,
mode1,
roundab,
saturateab,
roundcd,
saturatecd,
multabsaturate,
multcdsaturate,
signa,
signb,
addnsub0,
addnsub1,
zeroacc,
zeroacc1,
feedback,
dataout,
accoverflow
);
//Parameter Declaration
parameter operation_mode = "output_only";
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
//Input Ports
input [35:0] dataa;
input [35:0] datab;
input [35:0] datac;
input [35:0] datad;
input mode0;
input mode1;
input roundab;
input roundcd;
input saturateab;
input saturatecd;
input multabsaturate;
input multcdsaturate;
input signa;
input signb;
input addnsub0;
input addnsub1;
input zeroacc;
input zeroacc1;
input [143:0] feedback;
//Output Ports
output [143:0] dataout;
output accoverflow;
//Internal Signal Declaration
wire [143:0] dataout_tmp;
wire accoverflow_tmp;
wire [5:0] sign_size;
//Define the signals for instantiating the input interface block(iib)
wire[51:0] iib_accuma;
wire[51:0] iib_accumc;
wire[71:0] iib_dataa;
wire[71:0] iib_datab;
wire[71:0] iib_datac;
wire[71:0] iib_datad;
wire iib_sata;
wire iib_satb;
wire iib_satc;
wire iib_satd;
wire iib_satab;
wire iib_satcd;
wire[71:0] iib_outa;
wire[71:0] iib_outb;
wire[71:0] iib_outc;
wire[71:0] iib_outd;
//Define the signals for the R add_sub_acc block(rb)
wire rb_signa;
wire rb_signb;
wire [71:0] rb_dataout;
wire rb_overflow;
//Define the signals for the round_saturate R block(rs_rb)
wire [7:0] rs_rb_dataout_size;
wire [71:0] rs_rb_dataout;
wire rs_rb_saturate_overflow;
//Define the signals for the S add_sub_acc block(sb)
wire [71:0] sb_dataout;
wire sb_overflow;
//Define the signals for the round_saturate S block(rs_sb)
wire [7:0] rs_sb_dataout_size;
wire [71:0] rs_sb_dataout;
wire rs_sb_saturate_overflow;
//Define the signals for the t add_sub_acc block(tb)
wire tb_signa;
wire tb_signb;
wire [71:0] tb_dataout;
wire tb_overflow;
//Define signals for instantiating the output interface block
wire [143:0] oib_dataout;
wire [35:0] oib_dataa;
wire [35:0] oib_datab;
wire [35:0] oib_datac;
wire [35:0] oib_datad;
//Define signals for instantiating the reorder output block
wire ro_addnsub;
wire [3:0] operation;
wire signab;
wire [35:0] dataa_ipd;
wire [35:0] datab_ipd;
wire [35:0] datac_ipd;
wire [35:0] datad_ipd;
wire [143:0] feedback_ipd;
buf buf_dataa [35:0] (dataa_ipd,dataa);
buf buf_datab [35:0] (datab_ipd,datab);
buf buf_datac [35:0] (datac_ipd,datac);
buf buf_datad [35:0] (datad_ipd,datad);
buf buf_feedback [143:0] (feedback_ipd,feedback);
wire [143:0] dataout_opd;
wire accoverflow_opd;
buf buf_dataout [143:0] (dataout,dataout_opd);
buf buf_accoverflow (accoverflow,accoverflow_opd);
// TIMING SPECIFICATION
specify
(dataa *> dataout) = (0,0);
(datab *> dataout) = (0,0);
(datac *> dataout) = (0,0);
(datad *> dataout) = (0,0);
(signa *> dataout) = (0,0);
(signb *> dataout) = (0,0);
(mode0 *> dataout) = (0,0);
(mode1 *> dataout) = (0,0);
(addnsub0 *> dataout) = (0,0);
(addnsub1 *> dataout) = (0,0);
(zeroacc *> dataout) = (0,0);
(zeroacc1 *> dataout) = (0,0);
(multabsaturate *> dataout) = (0,0);
(multcdsaturate *> dataout) = (0,0);
(feedback *> dataout) = (0,0);
(dataa *> accoverflow) = (0,0);
(datab *> accoverflow) = (0,0);
(datac *> accoverflow) = (0,0);
(datad *> accoverflow) = (0,0);
(signa *> accoverflow) = (0,0);
(signb *> accoverflow) = (0,0);
(mode0 *> accoverflow) = (0,0);
(mode1 *> accoverflow) = (0,0);
(addnsub0 *> accoverflow) = (0,0);
(addnsub1 *> accoverflow) = (0,0);
(zeroacc *> accoverflow) = (0,0);
(zeroacc1 *> accoverflow) = (0,0);
(feedback *> accoverflow) = (0,0);
endspecify
//Decode the operation value depending on the operation mode
assign operation = (operation_mode == "output_only") ? 4'b0000 :
(operation_mode == "one_level_adder") ? 4'b0001 :
(operation_mode == "two_level_adder") ? 4'b0010 :
(operation_mode == "accumulator") ? 4'b0100 :
(operation_mode == "36_bit_multiply") ? 4'b0111 :
((operation_mode == "dynamic") && (mode0== 1'b0) && (mode1== 1'b0) &&(zeroacc == 1'b0) && (zeroacc1== 1'b0)) ? 4'b0000 :
((operation_mode == "dynamic") &&(mode0 == 1'b1) && (mode1 == 1'b1)) ? 4'b1100 :
((operation_mode == "dynamic") &&(mode0 == 1'b1) && (mode1 == 1'b0)) ? 4'b1101 :
((operation_mode == "dynamic") &&(mode0 == 1'b0) && (mode1 == 1'b1)) ? 4'b1110 :
((operation_mode == "dynamic") &&(mode0 == 1'b0) && (mode1 == 1'b0) && (zeroacc == 1'b1) && (zeroacc1 == 1'b1)) ? 4'b0111 : 4'b0000;
//Assign the sign size depending on the mode of operation
assign sign_size =((operation[2] == 1'b1) ? 18 :
(operation == 4'b0001) ||(operation == 4'b0010) ? 3 : 2);
//Instantiate stratixii_Input_Interface
stratixii_mac_out_input_interface input_interface(
.accuma(iib_accuma),
.accumc(iib_accumc),
.dataa(iib_dataa),
.datab(iib_datab),
.datac(iib_datac),
.datad(iib_datad),
.sign(signab),
.multabsaturate(multabsaturate),
.multcdsaturate(multcdsaturate),
.zeroacc(zeroacc),
.zeroacc1(zeroacc1),
.operation(operation),
.outa(iib_outa),
.outb(iib_outb),
.outc(iib_outc),
.outd(iib_outd),
.sata(iib_sata),
.satb(iib_satb),
.satc(iib_satc),
.satd(iib_satd),
.satab(iib_satab),
.satcd(iib_satcd)
);
defparam input_interface.dataa_width = dataa_width;
defparam input_interface.datab_width = datab_width;
defparam input_interface.datac_width = datac_width;
defparam input_interface.datad_width = datad_width;
assign signab = signa || signb;
assign iib_accuma = (operation_mode == "dynamic") ? {feedback_ipd[52:37], feedback_ipd[35:0]} : feedback_ipd[51:0];
assign iib_accumc = (operation_mode == "dynamic") ? {feedback_ipd[124:109], feedback_ipd[107:72]} :feedback_ipd[123:72];
assign iib_dataa = {36'b0, dataa_ipd};
assign iib_datab = {36'b0, datab_ipd};
assign iib_datac = {36'b0, datac_ipd};
assign iib_datad = {36'b0, datad_ipd};
//Instantiate the Add_Sub_Acc Block R (upper half of operations)
stratixii_mac_out_add_sub_acc_unit block_r(
.dataa(iib_outa),
.datab(iib_outb),
.datac(iib_outc),
.datad(iib_outd),
.signa(rb_signa),
.signb(rb_signb),
.operation(operation),
.addnsub(addnsub0),
.dataout(rb_dataout),
.overflow(rb_overflow)
);
defparam block_r.dataa_width = dataa_width;
defparam block_r.datab_width = datab_width;
defparam block_r.datac_width = datac_width;
defparam block_r.datad_width = datad_width;
defparam block_r.block_type = "R";
assign rb_signa =(operation_mode == "36_bit_multiply") ? signa :
((operation_mode == "dynamic") &&(mode0 == 1'b0) && (mode1 == 1'b0) && (zeroacc == 1'b1) && (zeroacc1 == 1'b1)) ? signa : signab;
assign rb_signb =(operation_mode == "36_bit_multiply") ? signb :
((operation_mode == "dynamic") &&(mode0 == 1'b0) && (mode1 == 1'b0) && (zeroacc == 1'b1) && (zeroacc1 == 1'b1)) ? signb : signab;
//Instantiate the Add_Sub_Acc Block S (sb--lower half of operations)
stratixii_mac_out_add_sub_acc_unit block_s(
.dataa(iib_outa),
.datab(iib_outb),
.datac(iib_outc),
.datad(iib_outd),
.signa(signab),
.signb(signab),
.operation(operation),
.addnsub(addnsub1),
.dataout(sb_dataout),
.overflow(sb_overflow)
);
defparam block_s.dataa_width = dataa_width;
defparam block_s.datab_width = datab_width;
defparam block_s.datac_width = datac_width;
defparam block_s.datad_width = datad_width;
defparam block_s.block_type = "S";
//Instantiate Round_Saturate block for the R block
stratixii_mac_rs_block mac_rs_rb(
.operation(operation),
.round(roundab),
.saturate(saturateab),
.addnsub(addnsub0),
.signa(signab),
.signb(signab),
.signsize(sign_size),
.roundsize(8'hf),
.dataoutsize(rs_rb_dataout_size),
.dataa(iib_outa),
.datab(iib_outb),
.datain(rb_dataout),
.dataout(rs_rb_dataout)
);
defparam mac_rs_rb.block_type = "R";
defparam mac_rs_rb.dataa_width = dataa_width;
defparam mac_rs_rb.datab_width = datab_width;
assign rs_rb_dataout_size = ((operation[2] == 1'b1) ? (datab_width + 16) :
(operation == 4'b0001) ? (dataa_width + 1) :
(operation == 4'b0010) ? (dataa_width + 1) : 36);
//Instantiate Round_Saturate block for the S block
stratixii_mac_rs_block mac_rs_sb(
.operation(operation),
.round(roundcd),
.saturate(saturatecd),
.addnsub(addnsub1),
.signa(signab),
.signb(signab),
.signsize(sign_size),
.roundsize(8'hf),
.dataoutsize(rs_sb_dataout_size),
.dataa(iib_outc),
.datab(iib_outd),
.datain(sb_dataout),
.dataout(rs_sb_dataout)
);
defparam mac_rs_sb.block_type = "S";
defparam mac_rs_sb.dataa_width = datac_width;
defparam mac_rs_sb.datab_width = datad_width;
assign rs_sb_dataout_size = ((operation[2] == 1'b1) ? (datad_width + 16) :
(operation == 4'b0001) ? (datac_width + 1) :
(operation == 4'b0010) ? (datac_width + 1) : 36);
//Instantiate the second level adder T(tb--t block)
stratixii_mac_out_add_sub_acc_unit block_t(
.dataa(rs_rb_dataout),
.datab(rs_sb_dataout),
.datac(iib_outc),
.datad(iib_outd),
.signa(tb_signa),
.signb(tb_signb),
.operation(operation),
.addnsub(1'b1),
.dataout(tb_dataout),
.overflow(tb_overflow)
);
defparam block_t.dataa_width = dataa_width;
defparam block_t.datab_width = datab_width;
defparam block_t.datac_width = datac_width;
defparam block_t.datad_width = datad_width;
defparam block_t.block_type = "T";
assign tb_signa = signab || ~addnsub0;
assign tb_signb = signab || ~addnsub1;
//Instantiate the oputput interface block
stratixii_mac_out_output_interface output_interface(
.dataa(oib_dataa),
.datab(oib_datab),
.datac(oib_datac),
.datad(oib_datad),
.datar(rs_rb_dataout),
.datas(rs_sb_dataout),
.datat(tb_dataout),
.data_36_mult(rb_dataout),
.sata(iib_sata),
.satb(iib_satb),
.satc(iib_satc),
.satd(iib_satd),
.satab(iib_satab),
.satcd(iib_satcd),
.satr(rs_rb_dataout[2]),
.sats(rs_sb_dataout[2]),
.multabsaturate(multabsaturate),
.multcdsaturate(multcdsaturate),
.saturate0(saturateab),
.saturate1(saturatecd),
.overflowr(rb_overflow),
.overflows(sb_overflow),
.operation(operation),
.dataout(oib_dataout),
.accoverflow(accoverflow_tmp)
);
assign oib_dataa = dataa_ipd;
assign oib_datab = datab_ipd;
assign oib_datac = datac_ipd;
assign oib_datad = datad_ipd;
//Instantiate the reorder block
stratixii_reorder_output reorder_unit(
.datain(oib_dataout),
.addnsub(ro_addnsub),
.operation(operation),
.dataout(dataout_tmp)
);
defparam reorder_unit.operation_mode = operation_mode;
assign ro_addnsub = addnsub0 && addnsub1;
assign accoverflow_opd = accoverflow_tmp;
assign dataout_opd = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// stratixii_MAC_OUT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_mac_out(
dataa,
datab,
datac,
datad,
zeroacc,
addnsub0,
addnsub1,
round0,
round1,
saturate,
multabsaturate,
multcdsaturate,
signa,
signb,
clk,
aclr,
ena,
mode0,
mode1,
zeroacc1,
saturate1,
dataout,
accoverflow,
devclrn,
devpor
);
parameter operation_mode = "output_only";
parameter dataa_width = 1;
parameter datab_width = 1;
parameter datac_width = 1;
parameter datad_width = 1;
parameter dataout_width = 144;
parameter addnsub0_clock = "none";
parameter addnsub1_clock = "none";
parameter zeroacc_clock = "none";
parameter round0_clock= "none";
parameter round1_clock= "none";
parameter saturate_clock = "none";
parameter multabsaturate_clock = "none";
parameter multcdsaturate_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter output_clock = "none";
parameter addnsub0_clear = "none";
parameter addnsub1_clear = "none";
parameter zeroacc_clear = "none";
parameter round0_clear = "none";
parameter round1_clear = "none";
parameter saturate_clear = "none";
parameter multabsaturate_clear = "none";
parameter multcdsaturate_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter output_clear = "none";
parameter addnsub0_pipeline_clock = "none";
parameter addnsub1_pipeline_clock = "none";
parameter round0_pipeline_clock = "none";
parameter round1_pipeline_clock = "none";
parameter saturate_pipeline_clock= "none";
parameter multabsaturate_pipeline_clock = "none";
parameter multcdsaturate_pipeline_clock = "none";
parameter zeroacc_pipeline_clock = "none";
parameter signa_pipeline_clock = "none";
parameter signb_pipeline_clock = "none";
parameter addnsub0_pipeline_clear = "none";
parameter addnsub1_pipeline_clear = "none";
parameter round0_pipeline_clear = "none";
parameter round1_pipeline_clear = "none";
parameter saturate_pipeline_clear= "none";
parameter multabsaturate_pipeline_clear = "none";
parameter multcdsaturate_pipeline_clear = "none";
parameter zeroacc_pipeline_clear = "none";
parameter signa_pipeline_clear = "none";
parameter signb_pipeline_clear = "none";
parameter mode0_clock = "none";
parameter mode1_clock = "none";
parameter zeroacc1_clock = "none";
parameter saturate1_clock= "none";
parameter output1_clock = "none";
parameter output2_clock = "none";
parameter output3_clock = "none";
parameter output4_clock = "none";
parameter output5_clock = "none";
parameter output6_clock = "none";
parameter output7_clock = "none";
parameter mode0_clear = "none";
parameter mode1_clear = "none";
parameter zeroacc1_clear = "none";
parameter saturate1_clear= "none";
parameter output1_clear = "none";
parameter output2_clear = "none";
parameter output3_clear = "none";
parameter output4_clear = "none";
parameter output5_clear = "none";
parameter output6_clear = "none";
parameter output7_clear = "none";
parameter mode0_pipeline_clock = "none";
parameter mode1_pipeline_clock = "none";
parameter zeroacc1_pipeline_clock = "none";
parameter saturate1_pipeline_clock = "none";
parameter mode0_pipeline_clear = "none";
parameter mode1_pipeline_clear = "none";
parameter zeroacc1_pipeline_clear = "none";
parameter saturate1_pipeline_clear = "none";
parameter dataa_forced_to_zero= "no";
parameter datac_forced_to_zero= "no";
parameter lpm_hint = "true";
parameter lpm_type = "stratixii_mac_out";
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input [datac_width-1:0] datac;
input [datad_width-1:0] datad;
input zeroacc;
input addnsub0;
input addnsub1;
input round0;
input round1;
input saturate;
input saturate1;
input mode0;
input mode1;
input zeroacc1;
input multabsaturate;
input multcdsaturate;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
output accoverflow;
tri1 devclrn;
tri1 devpor;
//Internal signals to instantiate the signa input register unit
wire [3:0] signa_inreg_clk_value;
wire [3:0] signa_inreg_aclr_value;
wire signa_inreg_clk;
wire signa_inreg_aclr;
wire signa_inreg_ena;
wire signa_inreg_bypass_register;
wire signa_inreg_pipreg;
//Internal signals to instantiate the signa pipeline register unit
wire [3:0] signa_pipreg_clk_value;
wire [3:0] signa_pipreg_aclr_value;
wire signa_pipreg_clk;
wire signa_pipreg_aclr;
wire signa_pipreg_ena;
wire signa_pipreg_bypass_register;
wire signa_pipreg_out;
//Internal signals to instantiate the signb input register unit
wire [3:0] signb_inreg_clk_value;
wire [3:0] signb_inreg_aclr_value;
wire signb_inreg_clk;
wire signb_inreg_aclr;
wire signb_inreg_ena;
wire signb_inreg_bypass_register;
wire signb_inreg_pipreg;
//Internal signals to instantiate the signb pipeline register unit
wire [3:0] signb_pipreg_clk_value;
wire [3:0] signb_pipreg_aclr_value;
wire signb_pipreg_clk;
wire signb_pipreg_aclr;
wire signb_pipreg_ena;
wire signb_pipreg_bypass_register;
wire signb_pipreg_out;
//Internal signals to instantiate the zeroacc input register unit
wire [3:0] zeroacc_inreg_clk_value;
wire [3:0] zeroacc_inreg_aclr_value;
wire zeroacc_inreg_clk;
wire zeroacc_inreg_aclr;
wire zeroacc_inreg_ena;
wire zeroacc_inreg_bypass_register;
wire zeroacc_inreg_pipreg;
//Internal signals to instantiate the zeroacc pipeline register unit
wire [3:0] zeroacc_pipreg_clk_value;
wire [3:0] zeroacc_pipreg_aclr_value;
wire zeroacc_pipreg_clk;
wire zeroacc_pipreg_aclr;
wire zeroacc_pipreg_ena;
wire zeroacc_pipreg_bypass_register;
wire zeroacc_pipreg_out;
//Internal signals to instantiate the zeroacc1 input register unit
wire [3:0] zeroacc1_inreg_clk_value;
wire [3:0] zeroacc1_inreg_aclr_value;
wire zeroacc1_inreg_clk;
wire zeroacc1_inreg_aclr;
wire zeroacc1_inreg_ena;
wire zeroacc1_inreg_bypass_register;
wire zeroacc1_inreg_pipreg;
//Internal signals to instantiate the zeroacc1 pipeline register unit
wire [3:0] zeroacc1_pipreg_clk_value;
wire [3:0] zeroacc1_pipreg_aclr_value;
wire zeroacc1_pipreg_clk;
wire zeroacc1_pipreg_aclr;
wire zeroacc1_pipreg_ena;
wire zeroacc1_pipreg_bypass_register;
wire zeroacc1_pipreg_out;
//Internal signals to instantiate the addnsub0 input register unit
wire [3:0] addnsub0_inreg_clk_value;
wire [3:0] addnsub0_inreg_aclr_value;
wire addnsub0_inreg_clk;
wire addnsub0_inreg_aclr;
wire addnsub0_inreg_ena;
wire addnsub0_inreg_bypass_register;
wire addnsub0_inreg_pipreg;
//Internal signals to instantiate the addnsub0 pipeline register unit
wire [3:0] addnsub0_pipreg_clk_value;
wire [3:0] addnsub0_pipreg_aclr_value;
wire addnsub0_pipreg_clk;
wire addnsub0_pipreg_aclr;
wire addnsub0_pipreg_ena;
wire addnsub0_pipreg_bypass_register;
wire addnsub0_pipreg_out;
//Internal signals to instantiate the addnsub1 input register unit
wire [3:1] addnsub1_inreg_clk_value;
wire [3:1] addnsub1_inreg_aclr_value;
wire addnsub1_inreg_clk;
wire addnsub1_inreg_aclr;
wire addnsub1_inreg_ena;
wire addnsub1_inreg_bypass_register;
wire addnsub1_inreg_pipreg;
//Internal signals to instantiate the addnsub1 pipeline register unit
wire [3:1] addnsub1_pipreg_clk_value;
wire [3:1] addnsub1_pipreg_aclr_value;
wire addnsub1_pipreg_clk;
wire addnsub1_pipreg_aclr;
wire addnsub1_pipreg_ena;
wire addnsub1_pipreg_bypass_register;
wire addnsub1_pipreg_out;
//Internal signals to instantiate the round0 input register unit
wire [3:0] round0_inreg_clk_value;
wire [3:0] round0_inreg_aclr_value;
wire round0_inreg_clk;
wire round0_inreg_aclr;
wire round0_inreg_ena;
wire round0_inreg_bypass_register;
wire round0_inreg_pipreg;
//Internal signals to instantiate the round0 pipeline register unit
wire [3:0] round0_pipreg_clk_value;
wire [3:0] round0_pipreg_aclr_value;
wire round0_pipreg_clk;
wire round0_pipreg_aclr;
wire round0_pipreg_ena;
wire round0_pipreg_bypass_register;
wire round0_pipreg_out;
//Internal signals to instantiate the round1 input register unit
wire [3:1] round1_inreg_clk_value;
wire [3:1] round1_inreg_aclr_value;
wire round1_inreg_clk;
wire round1_inreg_aclr;
wire round1_inreg_ena;
wire round1_inreg_bypass_register;
wire round1_inreg_pipreg;
//Internal signals to instantiate the round1 pipeline register unit
wire [3:1] round1_pipreg_clk_value;
wire [3:1] round1_pipreg_aclr_value;
wire round1_pipreg_clk;
wire round1_pipreg_aclr;
wire round1_pipreg_ena;
wire round1_pipreg_bypass_register;
wire round1_pipreg_out;
// Internal signals to instantiate the saturate input register unit
wire [3:0] saturate_inreg_clk_value;
wire [3:0] saturate_inreg_aclr_value;
wire saturate_inreg_clk;
wire saturate_inreg_aclr;
wire saturate_inreg_ena;
wire saturate_inreg_bypass_register;
wire saturate_inreg_pipreg;
//Internal signals to instantiate the saturate pipeline register unit
wire [3:0] saturate_pipreg_clk_value;
wire [3:0] saturate_pipreg_aclr_value;
wire saturate_pipreg_clk;
wire saturate_pipreg_aclr;
wire saturate_pipreg_ena;
wire saturate_pipreg_bypass_register;
wire saturate_pipreg_out;
//Internal signals to instantiate the saturate1 input register unit
wire [3:1] saturate1_inreg_clk_value;
wire [3:1] saturate1_inreg_aclr_value;
wire saturate1_inreg_clk;
wire saturate1_inreg_aclr;
wire saturate1_inreg_ena;
wire saturate1_inreg_bypass_register;
wire saturate1_inreg_pipreg;
//Internal signals to instantiate the saturate1 pipeline register unit
wire [3:1] saturate1_pipreg_clk_value;
wire [3:1] saturate1_pipreg_aclr_value;
wire saturate1_pipreg_clk;
wire saturate1_pipreg_aclr;
wire saturate1_pipreg_ena;
wire saturate1_pipreg_bypass_register;
wire saturate1_pipreg_out;
//Internal signals to instantiate the mode0 input register unit
wire [3:0] mode0_inreg_clk_value;
wire [3:0] mode0_inreg_aclr_value;
wire mode0_inreg_clk;
wire mode0_inreg_aclr;
wire mode0_inreg_ena;
wire mode0_inreg_bypass_register;
wire mode0_inreg_pipreg;
//Internal signals to instantiate the mode0 pipeline register unit
wire [3:0] mode0_pipreg_clk_value;
wire [3:0] mode0_pipreg_aclr_value;
wire mode0_pipreg_clk;
wire mode0_pipreg_aclr;
wire mode0_pipreg_ena;
wire mode0_pipreg_bypass_register;
wire mode0_pipreg_out;
//Internal signals to instantiate the mode1 input register unit
wire [3:1] mode1_inreg_clk_value;
wire [3:1] mode1_inreg_aclr_value;
wire mode1_inreg_clk;
wire mode1_inreg_aclr;
wire mode1_inreg_ena;
wire mode1_inreg_bypass_register;
wire mode1_inreg_pipreg;
//Internal signals to instantiate the mode1 pipeline register unit
wire [3:1] mode1_pipreg_clk_value;
wire [3:1] mode1_pipreg_aclr_value;
wire mode1_pipreg_clk;
wire mode1_pipreg_aclr;
wire mode1_pipreg_ena;
wire mode1_pipreg_bypass_register;
wire mode1_pipreg_out;
//Internal signals to instantiate the multabsaturate input register unit
wire [3:0] multabsaturate_inreg_clk_value;
wire [3:0] multabsaturate_inreg_aclr_value;
wire multabsaturate_inreg_clk;
wire multabsaturate_inreg_aclr;
wire multabsaturate_inreg_ena;
wire multabsaturate_inreg_bypass_register;
wire multabsaturate_inreg_pipreg;
//Internal signals to instantiate the multabsaturate pipeline register unit
wire [3:0] multabsaturate_pipreg_clk_value;
wire [3:0] multabsaturate_pipreg_aclr_value;
wire multabsaturate_pipreg_clk;
wire multabsaturate_pipreg_aclr;
wire multabsaturate_pipreg_ena;
wire multabsaturate_pipreg_bypass_register;
wire multabsaturate_pipreg_out;
//Internal signals to instantiate the multcdsaturate input register unit
wire [3:1] multcdsaturate_inreg_clk_value;
wire [3:1] multcdsaturate_inreg_aclr_value;
wire multcdsaturate_inreg_clk;
wire multcdsaturate_inreg_aclr;
wire multcdsaturate_inreg_ena;
wire multcdsaturate_inreg_bypass_register;
wire multcdsaturate_inreg_pipreg;
//Internal signals to instantiate the multcdsaturate pipeline register unit
wire [3:1] multcdsaturate_pipreg_clk_value;
wire [3:1] multcdsaturate_pipreg_aclr_value;
wire multcdsaturate_pipreg_clk;
wire multcdsaturate_pipreg_aclr;
wire multcdsaturate_pipreg_ena;
wire multcdsaturate_pipreg_bypass_register;
wire multcdsaturate_pipreg_out;
//Declare the signals for instantiating the mac_out internal logic
wire[35:0] mac_out_dataa;
wire[35:0] mac_out_datab;
wire[35:0] mac_out_datac;
wire[35:0] mac_out_datad;
wire [143:0] mac_out_feedback;
wire[143:0] mac_out_dataout;
wire mac_out_accoverflow;
//Internal signals to instantiate the output register unit
wire [3:1] outreg_clk_value;
wire [3:1] outreg_aclr_value;
wire outreg_clk;
wire outreg_aclr;
wire outreg_ena;
wire outreg_bypass_register;
wire [71:0] outreg_dataout;
wire outreg_accoverflow;
//Internal signals to instantiate the output register1 unit
wire [3:1] outreg1_clk_value;
wire [3:1] outreg1_aclr_value;
wire outreg1_clk;
wire outreg1_aclr;
wire outreg1_ena;
wire outreg1_bypass_register;
wire [17:0] outreg1_dataout;
//Internal signals to instantiate the output register2 unit
wire [3:1] outreg2_clk_value;
wire [3:1] outreg2_aclr_value;
wire outreg2_clk;
wire outreg2_aclr;
wire outreg2_ena;
wire outreg2_bypass_register;
wire [17:0] outreg2_dataout;
//Internal signals to instantiate the output register3 unit
wire [3:1] outreg3_clk_value;
wire [3:1] outreg3_aclr_value;
wire outreg3_clk;
wire outreg3_aclr;
wire outreg3_ena;
wire outreg3_bypass_register;
wire [17:0] outreg3_dataout;
//Internal signals to instantiate the output register4 unit
wire [3:1] outreg4_clk_value;
wire [3:1] outreg4_aclr_value;
wire outreg4_clk;
wire outreg4_aclr;
wire outreg4_ena;
wire outreg4_bypass_register;
wire [17:0] outreg4_dataout;
//Internal signals to instantiate the output register5 unit
wire [3:1] outreg5_clk_value;
wire [3:1] outreg5_aclr_value;
wire outreg5_clk;
wire outreg5_aclr;
wire outreg5_ena;
wire outreg5_bypass_register;
wire [17:0] outreg5_dataout;
//Internal signals to instantiate the output register6 unit
wire [3:1] outreg6_clk_value;
wire [3:1] outreg6_aclr_value;
wire outreg6_clk;
wire outreg6_aclr;
wire outreg6_ena;
wire outreg6_bypass_register;
wire [17:0] outreg6_dataout;
//Internal signals to instantiate the output register7 unit
wire [3:1] outreg7_clk_value;
wire [3:1] outreg7_aclr_value;
wire outreg7_clk;
wire outreg7_aclr;
wire outreg7_ena;
wire outreg7_bypass_register;
wire [17:0] outreg7_dataout;
//Define the internal signals
wire [143:0] dataout_dynamic;
wire [143:0] dataout_tmp;
//Instantiate signa input register
stratixii_mac_register signa_inreg(
.datain(signa),
.clk(signa_inreg_clk),
.aclr(signa_inreg_aclr),
.ena(signa_inreg_ena),
.bypass_register(signa_inreg_bypass_register),
.dataout(signa_inreg_pipreg)
);
defparam signa_inreg.data_width = 1;
//decode the clk and aclr values
assign signa_inreg_clk_value =((signa_clock == "0") || (signa_clock == "none")) ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_inreg_aclr_value = ((signa_clear == "0") ||(signa_clear == "none")) ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_inreg_clk = clk[signa_inreg_clk_value] ? 'b1 : 'b0;
assign signa_inreg_aclr = aclr[signa_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signa_inreg_ena = ena[signa_inreg_clk_value] ? 'b1 : 'b0;
assign signa_inreg_bypass_register = (signa_clock == "none") ? 'b1 : 'b0;
//Instantiate signa pipeline register
stratixii_mac_register signa_pipreg(
.datain(signa_inreg_pipreg),
.clk(signa_pipreg_clk),
.aclr(signa_pipreg_aclr),
.ena(signa_pipreg_ena),
.bypass_register(signa_pipreg_bypass_register),
.dataout(signa_pipreg_out)
);
defparam signa_pipreg.data_width = 1;
//decode the clk and aclr values
assign signa_pipreg_clk_value =((signa_pipeline_clock == "0") || (signa_pipeline_clock == "none")) ? 4'b0000 :
(signa_pipeline_clock == "1") ? 4'b0001 :
(signa_pipeline_clock == "2") ? 4'b0010 :
(signa_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_pipreg_aclr_value = ((signa_pipeline_clear == "0") ||(signa_pipeline_clear == "none")) ? 4'b0000 :
(signa_pipeline_clear == "1") ? 4'b0001 :
(signa_pipeline_clear == "2") ? 4'b0010 :
(signa_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_pipreg_clk = clk[signa_pipreg_clk_value] ? 'b1 : 'b0;
assign signa_pipreg_aclr = aclr[signa_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signa_pipreg_ena = ena[signa_pipreg_clk_value] ? 'b1 : 'b0;
assign signa_pipreg_bypass_register = (signa_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate signb input register
stratixii_mac_register signb_inreg(
.datain(signb),
.clk(signb_inreg_clk),
.aclr(signb_inreg_aclr),
.ena(signb_inreg_ena),
.bypass_register(signb_inreg_bypass_register),
.dataout(signb_inreg_pipreg)
);
defparam signb_inreg.data_width = 1;
//decode the clk and aclr values
assign signb_inreg_clk_value =((signb_clock == "0") || (signb_clock == "none")) ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_inreg_aclr_value = ((signb_clear == "0") ||(signb_clear == "none")) ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_inreg_clk = clk[signb_inreg_clk_value] ? 'b1 : 'b0;
assign signb_inreg_aclr = aclr[signb_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signb_inreg_ena = ena[signb_inreg_clk_value] ? 'b1 : 'b0;
assign signb_inreg_bypass_register = (signb_clock == "none") ? 'b1 : 'b0;
//Instantiate signb pipeline register
stratixii_mac_register signb_pipreg(
.datain(signb_inreg_pipreg),
.clk(signb_pipreg_clk),
.aclr(signb_pipreg_aclr),
.ena(signb_pipreg_ena),
.bypass_register(signb_pipreg_bypass_register),
.dataout(signb_pipreg_out)
);
defparam signb_pipreg.data_width = 1;
//decode the clk and aclr values
assign signb_pipreg_clk_value =((signb_pipeline_clock == "0") || (signb_pipeline_clock == "none")) ? 4'b0000 :
(signb_pipeline_clock == "1") ? 4'b0001 :
(signb_pipeline_clock == "2") ? 4'b0010 :
(signb_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_pipreg_aclr_value = ((signb_pipeline_clear == "0") ||(signb_pipeline_clear == "none")) ? 4'b0000 :
(signb_pipeline_clear == "1") ? 4'b0001 :
(signb_pipeline_clear == "2") ? 4'b0010 :
(signb_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_pipreg_clk = clk[signb_pipreg_clk_value] ? 'b1 : 'b0;
assign signb_pipreg_aclr = aclr[signb_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign signb_pipreg_ena = ena[signb_pipreg_clk_value] ? 'b1 : 'b0;
assign signb_pipreg_bypass_register = (signb_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate zeroacc input register
stratixii_mac_register zeroacc_inreg(
.datain(zeroacc),
.clk(zeroacc_inreg_clk),
.aclr(zeroacc_inreg_aclr),
.ena(zeroacc_inreg_ena),
.bypass_register(zeroacc_inreg_bypass_register),
.dataout(zeroacc_inreg_pipreg)
);
defparam zeroacc_inreg.data_width = 1;
//decode the clk and aclr values
assign zeroacc_inreg_clk_value =((zeroacc_clock == "0") || (zeroacc_clock == "none")) ? 4'b0000 :
(zeroacc_clock == "1") ? 4'b0001 :
(zeroacc_clock == "2") ? 4'b0010 :
(zeroacc_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_inreg_aclr_value = ((zeroacc_clear == "0") ||(zeroacc_clear == "none")) ? 4'b0000 :
(zeroacc_clear == "1") ? 4'b0001 :
(zeroacc_clear == "2") ? 4'b0010 :
(zeroacc_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_inreg_clk = clk[zeroacc_inreg_clk_value] ? 'b1 : 'b0;
assign zeroacc_inreg_aclr = aclr[zeroacc_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign zeroacc_inreg_ena = ena[zeroacc_inreg_clk_value] ? 'b1 : 'b0;
assign zeroacc_inreg_bypass_register = (zeroacc_clock == "none") ? 'b1 : 'b0;
//Instantiate zeroacc pipeline register
stratixii_mac_register zeroacc_pipreg(
.datain(zeroacc_inreg_pipreg),
.clk(zeroacc_pipreg_clk),
.aclr(zeroacc_pipreg_aclr),
.ena(zeroacc_pipreg_ena),
.bypass_register(zeroacc_pipreg_bypass_register),
.dataout(zeroacc_pipreg_out)
);
defparam zeroacc_pipreg.data_width = 1;
//decode the clk and aclr values
assign zeroacc_pipreg_clk_value =((zeroacc_pipeline_clock == "0") || (zeroacc_pipeline_clock == "none")) ? 4'b0000 :
(zeroacc_pipeline_clock == "1") ? 4'b0001 :
(zeroacc_pipeline_clock == "2") ? 4'b0010 :
(zeroacc_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_pipreg_aclr_value = ((zeroacc_pipeline_clear == "0") ||(zeroacc_pipeline_clear == "none")) ? 4'b0000 :
(zeroacc_pipeline_clear == "1") ? 4'b0001 :
(zeroacc_pipeline_clear == "2") ? 4'b0010 :
(zeroacc_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_pipreg_clk = clk[zeroacc_pipreg_clk_value] ? 'b1 : 'b0;
assign zeroacc_pipreg_aclr = aclr[zeroacc_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign zeroacc_pipreg_ena = ena[zeroacc_pipreg_clk_value] ? 'b1 : 'b0;
assign zeroacc_pipreg_bypass_register = (zeroacc_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate zeroacc1 input register
stratixii_mac_register zeroacc1_inreg (
.datain(zeroacc1),
.clk(zeroacc1_inreg_clk),
.aclr(zeroacc1_inreg_aclr),
.ena(zeroacc1_inreg_ena),
.bypass_register(zeroacc1_inreg_bypass_register),
.dataout(zeroacc1_inreg_pipreg)
);
defparam zeroacc1_inreg.data_width = 1;
//decode the clk and aclr values
assign zeroacc1_inreg_clk_value =((zeroacc1_clock == "0") || (zeroacc1_clock == "none")) ? 4'b0000 :
(zeroacc1_clock == "1") ? 4'b0001 :
(zeroacc1_clock == "2") ? 4'b0010 :
(zeroacc1_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc1_inreg_aclr_value = ((zeroacc1_clear == "0") ||(zeroacc1_clear == "none")) ? 4'b0000 :
(zeroacc1_clear == "1") ? 4'b0001 :
(zeroacc1_clear == "2") ? 4'b0010 :
(zeroacc1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc1_inreg_clk = clk[zeroacc1_inreg_clk_value] ? 'b1 : 'b0;
assign zeroacc1_inreg_aclr = aclr[zeroacc1_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign zeroacc1_inreg_ena = ena[zeroacc1_inreg_clk_value] ? 'b1 : 'b0;
assign zeroacc1_inreg_bypass_register = (zeroacc1_clock == "none") ? 'b1 : 'b0;
//Instantiate zeroacc1 pipeline register
stratixii_mac_register zeroacc1_pipreg(
.datain(zeroacc1_inreg_pipreg),
.clk(zeroacc1_pipreg_clk),
.aclr(zeroacc1_pipreg_aclr),
.ena(zeroacc1_pipreg_ena),
.bypass_register(zeroacc1_pipreg_bypass_register),
.dataout(zeroacc1_pipreg_out)
);
defparam zeroacc1_pipreg.data_width = 1;
//decode the clk and aclr values
assign zeroacc1_pipreg_clk_value =((zeroacc1_pipeline_clock == "0") || (zeroacc1_pipeline_clock == "none")) ? 4'b0000 :
(zeroacc1_pipeline_clock == "1") ? 4'b0001 :
(zeroacc1_pipeline_clock == "2") ? 4'b0010 :
(zeroacc1_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc1_pipreg_aclr_value = ((zeroacc1_pipeline_clear == "0") ||(zeroacc1_pipeline_clear == "none")) ? 4'b0000 :
(zeroacc1_pipeline_clear == "1") ? 4'b0001 :
(zeroacc1_pipeline_clear == "2") ? 4'b0010 :
(zeroacc1_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc1_pipreg_clk = clk[zeroacc1_pipreg_clk_value] ? 'b1 : 'b0;
assign zeroacc1_pipreg_aclr = aclr[zeroacc1_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign zeroacc1_pipreg_ena = ena[zeroacc1_pipreg_clk_value] ? 'b1 : 'b0;
assign zeroacc1_pipreg_bypass_register = (zeroacc1_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate addnsub0 input register
stratixii_mac_register addnsub0_inreg(
.datain(addnsub0),
.clk(addnsub0_inreg_clk),
.aclr(addnsub0_inreg_aclr),
.ena(addnsub0_inreg_ena),
.bypass_register(addnsub0_inreg_bypass_register),
.dataout(addnsub0_inreg_pipreg)
);
defparam addnsub0_inreg.data_width = 1;
//decode the clk and aclr values
assign addnsub0_inreg_clk_value =((addnsub0_clock == "0") || (addnsub0_clock == "none")) ? 4'b0000 :
(addnsub0_clock == "1") ? 4'b0001 :
(addnsub0_clock == "2") ? 4'b0010 :
(addnsub0_clock == "3") ? 4'b0011 : 4'b0000;
assign addnsub0_inreg_aclr_value = ((addnsub0_clear == "0") ||(addnsub0_clear == "none")) ? 4'b0000 :
(addnsub0_clear == "1") ? 4'b0001 :
(addnsub0_clear == "2") ? 4'b0010 :
(addnsub0_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign addnsub0_inreg_clk = clk[addnsub0_inreg_clk_value] ? 'b1 : 'b0;
assign addnsub0_inreg_aclr = aclr[addnsub0_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign addnsub0_inreg_ena = ena[addnsub0_inreg_clk_value] ? 'b1 : 'b0;
assign addnsub0_inreg_bypass_register = (addnsub0_clock == "none") ? 'b1 : 'b0;
//Instantiate addnsub0 pipeline register
stratixii_mac_register addnsub0_pipreg(
.datain(addnsub0_inreg_pipreg),
.clk(addnsub0_pipreg_clk),
.aclr(addnsub0_pipreg_aclr),
.ena(addnsub0_pipreg_ena),
.bypass_register(addnsub0_pipreg_bypass_register),
.dataout(addnsub0_pipreg_out)
);
defparam addnsub0_pipreg.data_width = 1;
//decode the clk and aclr values
assign addnsub0_pipreg_clk_value =((addnsub0_pipeline_clock == "0") || (addnsub0_pipeline_clock == "none")) ? 4'b0000 :
(addnsub0_pipeline_clock == "1") ? 4'b0001 :
(addnsub0_pipeline_clock == "2") ? 4'b0010 :
(addnsub0_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign addnsub0_pipreg_aclr_value = ((addnsub0_pipeline_clear == "0") ||(addnsub0_pipeline_clear == "none")) ? 4'b0000 :
(addnsub0_pipeline_clear == "1") ? 4'b0001 :
(addnsub0_pipeline_clear == "2") ? 4'b0010 :
(addnsub0_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign addnsub0_pipreg_clk = clk[addnsub0_pipreg_clk_value] ? 'b1 : 'b0;
assign addnsub0_pipreg_aclr = aclr[addnsub0_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign addnsub0_pipreg_ena = ena[addnsub0_pipreg_clk_value] ? 'b1 : 'b0;
assign addnsub0_pipreg_bypass_register = (addnsub0_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate addnsub1 input register
stratixii_mac_register addnsub1_inreg(
.datain(addnsub1),
.clk(addnsub1_inreg_clk),
.aclr(addnsub1_inreg_aclr),
.ena(addnsub1_inreg_ena),
.bypass_register(addnsub1_inreg_bypass_register),
.dataout(addnsub1_inreg_pipreg)
);
defparam addnsub1_inreg.data_width = 1;
//decode the clk and aclr values
assign addnsub1_inreg_clk_value =((addnsub1_clock == "0") || (addnsub1_clock == "none")) ? 4'b0000 :
(addnsub1_clock == "1") ? 4'b0001 :
(addnsub1_clock == "2") ? 4'b0010 :
(addnsub1_clock == "3") ? 4'b0011 : 4'b0000;
assign addnsub1_inreg_aclr_value = ((addnsub1_clear == "0") ||(addnsub1_clear == "none")) ? 4'b0000 :
(addnsub1_clear == "1") ? 4'b0001 :
(addnsub1_clear == "2") ? 4'b0010 :
(addnsub1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign addnsub1_inreg_clk = clk[addnsub1_inreg_clk_value] ? 'b1 : 'b0;
assign addnsub1_inreg_aclr = aclr[addnsub1_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign addnsub1_inreg_ena = ena[addnsub1_inreg_clk_value] ? 'b1 : 'b0;
assign addnsub1_inreg_bypass_register = (addnsub1_clock == "none") ? 'b1 : 'b0;
//Instantiate addnsub1 pipeline register
stratixii_mac_register addnsub1_pipreg(
.datain(addnsub1_inreg_pipreg),
.clk(addnsub1_pipreg_clk),
.aclr(addnsub1_pipreg_aclr),
.ena(addnsub1_pipreg_ena),
.bypass_register(addnsub1_pipreg_bypass_register),
.dataout(addnsub1_pipreg_out)
);
defparam addnsub1_pipreg.data_width = 1;
//decode the clk and aclr values
assign addnsub1_pipreg_clk_value =((addnsub1_pipeline_clock == "0") || (addnsub1_pipeline_clock == "none")) ? 4'b0000 :
(addnsub1_pipeline_clock == "1") ? 4'b0001 :
(addnsub1_pipeline_clock == "2") ? 4'b0010 :
(addnsub1_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign addnsub1_pipreg_aclr_value = ((addnsub1_pipeline_clear == "0") ||(addnsub1_pipeline_clear == "none")) ? 4'b0000 :
(addnsub1_pipeline_clear == "1") ? 4'b0001 :
(addnsub1_pipeline_clear == "2") ? 4'b0010 :
(addnsub1_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign addnsub1_pipreg_clk = clk[addnsub1_pipreg_clk_value] ? 'b1 : 'b0;
assign addnsub1_pipreg_aclr = aclr[addnsub1_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign addnsub1_pipreg_ena = ena[addnsub1_pipreg_clk_value] ? 'b1 : 'b0;
assign addnsub1_pipreg_bypass_register = (addnsub1_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate round0 input register
stratixii_mac_register round0_inreg(
.datain(round0),
.clk(round0_inreg_clk),
.aclr(round0_inreg_aclr),
.ena(round0_inreg_ena),
.bypass_register(round0_inreg_bypass_register),
.dataout(round0_inreg_pipreg)
);
defparam round0_inreg.data_width = 1;
//decode the clk and aclr values
assign round0_inreg_clk_value =((round0_clock == "0") || (round0_clock == "none")) ? 4'b0000 :
(round0_clock == "1") ? 4'b0001 :
(round0_clock == "2") ? 4'b0010 :
(round0_clock == "3") ? 4'b0011 : 4'b0000;
assign round0_inreg_aclr_value = ((round0_clear == "0") ||(round0_clear == "none")) ? 4'b0000 :
(round0_clear == "1") ? 4'b0001 :
(round0_clear == "2") ? 4'b0010 :
(round0_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round0_inreg_clk = clk[round0_inreg_clk_value] ? 'b1 : 'b0;
assign round0_inreg_aclr = aclr[round0_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign round0_inreg_ena = ena[round0_inreg_clk_value] ? 'b1 : 'b0;
assign round0_inreg_bypass_register = (round0_clock == "none") ? 'b1 : 'b0;
//Instantiate round0 pipeline register
stratixii_mac_register round0_pipreg(
.datain(round0_inreg_pipreg),
.clk(round0_pipreg_clk),
.aclr(round0_pipreg_aclr),
.ena(round0_pipreg_ena),
.bypass_register(round0_pipreg_bypass_register),
.dataout(round0_pipreg_out)
);
defparam round0_pipreg.data_width = 1;
//decode the clk and aclr values
assign round0_pipreg_clk_value =((round0_pipeline_clock == "0") || (round0_pipeline_clock == "none")) ? 4'b0000 :
(round0_pipeline_clock == "1") ? 4'b0001 :
(round0_pipeline_clock == "2") ? 4'b0010 :
(round0_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign round0_pipreg_aclr_value = ((round0_pipeline_clear == "0") ||(round0_pipeline_clear == "none")) ? 4'b0000 :
(round0_pipeline_clear == "1") ? 4'b0001 :
(round0_pipeline_clear == "2") ? 4'b0010 :
(round0_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round0_pipreg_clk = clk[round0_pipreg_clk_value] ? 'b1 : 'b0;
assign round0_pipreg_aclr = aclr[round0_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign round0_pipreg_ena = ena[round0_pipreg_clk_value] ? 'b1 : 'b0;
assign round0_pipreg_bypass_register = (round0_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate round1 input register
stratixii_mac_register round1_inreg(
.datain(round1),
.clk(round1_inreg_clk),
.aclr(round1_inreg_aclr),
.ena(round1_inreg_ena),
.bypass_register(round1_inreg_bypass_register),
.dataout(round1_inreg_pipreg)
);
defparam round1_inreg.data_width = 1;
//decode the clk and aclr values
assign round1_inreg_clk_value =((round1_clock == "0") || (round1_clock == "none")) ? 4'b0000 :
(round1_clock == "1") ? 4'b0001 :
(round1_clock == "2") ? 4'b0010 :
(round1_clock == "3") ? 4'b0011 : 4'b0000;
assign round1_inreg_aclr_value = ((round1_clear == "0") ||(round1_clear == "none")) ? 4'b0000 :
(round1_clear == "1") ? 4'b0001 :
(round1_clear == "2") ? 4'b0010 :
(round1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round1_inreg_clk = clk[round1_inreg_clk_value] ? 'b1 : 'b0;
assign round1_inreg_aclr = aclr[round1_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign round1_inreg_ena = ena[round1_inreg_clk_value] ? 'b1 : 'b0;
assign round1_inreg_bypass_register = (round1_clock == "none") ? 'b1 : 'b0;
//Instantiate round1 pipeline register
stratixii_mac_register round1_pipreg(
.datain(round1_inreg_pipreg),
.clk(round1_pipreg_clk),
.aclr(round1_pipreg_aclr),
.ena(round1_pipreg_ena),
.bypass_register(round1_pipreg_bypass_register),
.dataout(round1_pipreg_out)
);
defparam round1_pipreg.data_width = 1;
//decode the clk and aclr values
assign round1_pipreg_clk_value =((round1_pipeline_clock == "0") || (round1_pipeline_clock == "none")) ? 4'b0000 :
(round1_pipeline_clock == "1") ? 4'b0001 :
(round1_pipeline_clock == "2") ? 4'b0010 :
(round1_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign round1_pipreg_aclr_value = ((round1_pipeline_clear == "0") ||(round1_pipeline_clear == "none")) ? 4'b0000 :
(round1_pipeline_clear == "1") ? 4'b0001 :
(round1_pipeline_clear == "2") ? 4'b0010 :
(round1_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round1_pipreg_clk = clk[round1_pipreg_clk_value] ? 'b1 : 'b0;
assign round1_pipreg_aclr = aclr[round1_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign round1_pipreg_ena = ena[round1_pipreg_clk_value] ? 'b1 : 'b0;
assign round1_pipreg_bypass_register = (round1_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate saturate input register
stratixii_mac_register saturate_inreg(
.datain(saturate),
.clk(saturate_inreg_clk),
.aclr(saturate_inreg_aclr),
.ena(saturate_inreg_ena),
.bypass_register(saturate_inreg_bypass_register),
.dataout(saturate_inreg_pipreg)
);
defparam saturate_inreg.data_width = 1;
//decode the clk and aclr values
assign saturate_inreg_clk_value =((saturate_clock == "0") || (saturate_clock == "none")) ? 4'b0000 :
(saturate_clock == "1") ? 4'b0001 :
(saturate_clock == "2") ? 4'b0010 :
(saturate_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_inreg_aclr_value = ((saturate_clear == "0") ||(saturate_clear == "none")) ? 4'b0000 :
(saturate_clear == "1") ? 4'b0001 :
(saturate_clear == "2") ? 4'b0010 :
(saturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_inreg_clk = clk[saturate_inreg_clk_value] ? 'b1 : 'b0;
assign saturate_inreg_aclr = aclr[saturate_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign saturate_inreg_ena = ena[saturate_inreg_clk_value] ? 'b1 : 'b0;
assign saturate_inreg_bypass_register = (saturate_clock == "none") ? 'b1 : 'b0;
//Instantiate saturate pipeline register
stratixii_mac_register saturate_pipreg(
.datain(saturate_inreg_pipreg),
.clk(saturate_pipreg_clk),
.aclr(saturate_pipreg_aclr),
.ena(saturate_pipreg_ena),
.bypass_register(saturate_pipreg_bypass_register),
.dataout(saturate_pipreg_out)
);
defparam saturate_pipreg.data_width = 1;
//decode the clk and aclr values
assign saturate_pipreg_clk_value =((saturate_pipeline_clock == "0") || (saturate_pipeline_clock == "none")) ? 4'b0000 :
(saturate_pipeline_clock == "1") ? 4'b0001 :
(saturate_pipeline_clock == "2") ? 4'b0010 :
(saturate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_pipreg_aclr_value = ((saturate_pipeline_clear == "0") ||(saturate_pipeline_clear == "none")) ? 4'b0000 :
(saturate_pipeline_clear == "1") ? 4'b0001 :
(saturate_pipeline_clear == "2") ? 4'b0010 :
(saturate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_pipreg_clk = clk[saturate_pipreg_clk_value] ? 'b1 : 'b0;
assign saturate_pipreg_aclr = aclr[saturate_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign saturate_pipreg_ena = ena[saturate_pipreg_clk_value] ? 'b1 : 'b0;
assign saturate_pipreg_bypass_register = (saturate_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate saturate1 input register
stratixii_mac_register saturate1_inreg(
.datain(saturate1),
.clk(saturate1_inreg_clk),
.aclr(saturate1_inreg_aclr),
.ena(saturate1_inreg_ena),
.bypass_register(saturate1_inreg_bypass_register),
.dataout(saturate1_inreg_pipreg)
);
defparam saturate1_inreg.data_width = 1;
//decode the clk and aclr values
assign saturate1_inreg_clk_value =((saturate1_clock == "0") || (saturate1_clock == "none")) ? 4'b0000 :
(saturate1_clock == "1") ? 4'b0001 :
(saturate1_clock == "2") ? 4'b0010 :
(saturate1_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate1_inreg_aclr_value = ((saturate1_clear == "0") ||(saturate1_clear == "none")) ? 4'b0000 :
(saturate1_clear == "1") ? 4'b0001 :
(saturate1_clear == "2") ? 4'b0010 :
(saturate1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate1_inreg_clk = clk[saturate1_inreg_clk_value] ? 'b1 : 'b0;
assign saturate1_inreg_aclr = aclr[saturate1_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign saturate1_inreg_ena = ena[saturate1_inreg_clk_value] ? 'b1 : 'b0;
assign saturate1_inreg_bypass_register = (saturate1_clock == "none") ? 'b1 : 'b0;
//Instantiate saturate1 pipeline register
stratixii_mac_register saturate1_pipreg(
.datain(saturate1_inreg_pipreg),
.clk(saturate1_pipreg_clk),
.aclr(saturate1_pipreg_aclr),
.ena(saturate1_pipreg_ena),
.bypass_register(saturate1_pipreg_bypass_register),
.dataout(saturate1_pipreg_out)
);
defparam saturate1_pipreg.data_width = 1;
//decode the clk and aclr values
assign saturate1_pipreg_clk_value =((saturate1_pipeline_clock == "0") || (saturate1_pipeline_clock == "none")) ? 4'b0000 :
(saturate1_pipeline_clock == "1") ? 4'b0001 :
(saturate1_pipeline_clock == "2") ? 4'b0010 :
(saturate1_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate1_pipreg_aclr_value = ((saturate1_pipeline_clear == "0") ||(saturate1_pipeline_clear == "none")) ? 4'b0000 :
(saturate1_pipeline_clear == "1") ? 4'b0001 :
(saturate1_pipeline_clear == "2") ? 4'b0010 :
(saturate1_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate1_pipreg_clk = clk[saturate1_pipreg_clk_value] ? 'b1 : 'b0;
assign saturate1_pipreg_aclr = aclr[saturate1_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign saturate1_pipreg_ena = ena[saturate1_pipreg_clk_value] ? 'b1 : 'b0;
assign saturate1_pipreg_bypass_register = (saturate1_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate mode0 input register
stratixii_mac_register mode0_inreg(
.datain(mode0),
.clk(mode0_inreg_clk),
.aclr(mode0_inreg_aclr),
.ena(mode0_inreg_ena),
.bypass_register(mode0_inreg_bypass_register),
.dataout(mode0_inreg_pipreg)
);
defparam mode0_inreg.data_width = 1;
//decode the clk and aclr values
assign mode0_inreg_clk_value =((mode0_clock == "0") || (mode0_clock == "none")) ? 4'b0000 :
(mode0_clock == "1") ? 4'b0001 :
(mode0_clock == "2") ? 4'b0010 :
(mode0_clock == "3") ? 4'b0011 : 4'b0000;
assign mode0_inreg_aclr_value = ((mode0_clear == "0") ||(mode0_clear == "none")) ? 4'b0000 :
(mode0_clear == "1") ? 4'b0001 :
(mode0_clear == "2") ? 4'b0010 :
(mode0_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign mode0_inreg_clk = clk[mode0_inreg_clk_value] ? 'b1 : 'b0;
assign mode0_inreg_aclr = aclr[mode0_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign mode0_inreg_ena = ena[mode0_inreg_clk_value] ? 'b1 : 'b0;
assign mode0_inreg_bypass_register = (mode0_clock == "none") ? 'b1 : 'b0;
//Instantiate mode0 pipeline register
stratixii_mac_register mode0_pipreg(
.datain(mode0_inreg_pipreg),
.clk(mode0_pipreg_clk),
.aclr(mode0_pipreg_aclr),
.ena(mode0_pipreg_ena),
.bypass_register(mode0_pipreg_bypass_register),
.dataout(mode0_pipreg_out)
);
defparam mode0_pipreg.data_width = 1;
//decode the clk and aclr values
assign mode0_pipreg_clk_value =((mode0_pipeline_clock == "0") || (mode0_pipeline_clock == "none")) ? 4'b0000 :
(mode0_pipeline_clock == "1") ? 4'b0001 :
(mode0_pipeline_clock == "2") ? 4'b0010 :
(mode0_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign mode0_pipreg_aclr_value = ((mode0_pipeline_clear == "0") ||(mode0_pipeline_clear == "none")) ? 4'b0000 :
(mode0_pipeline_clear == "1") ? 4'b0001 :
(mode0_pipeline_clear == "2") ? 4'b0010 :
(mode0_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign mode0_pipreg_clk = clk[mode0_pipreg_clk_value] ? 'b1 : 'b0;
assign mode0_pipreg_aclr = aclr[mode0_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign mode0_pipreg_ena = ena[mode0_pipreg_clk_value] ? 'b1 : 'b0;
assign mode0_pipreg_bypass_register = (mode0_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate mode1 input register
stratixii_mac_register mode1_inreg (
.datain(mode1),
.clk(mode1_inreg_clk),
.aclr(mode1_inreg_aclr),
.ena(mode1_inreg_ena),
.bypass_register(mode1_inreg_bypass_register),
.dataout(mode1_inreg_pipreg)
);
defparam mode1_inreg.data_width = 1;
//decode the clk and aclr values
assign mode1_inreg_clk_value =((mode1_clock == "0") || (mode1_clock == "none")) ? 4'b0000 :
(mode1_clock == "1") ? 4'b0001 :
(mode1_clock == "2") ? 4'b0010 :
(mode1_clock == "3") ? 4'b0011 : 4'b0000;
assign mode1_inreg_aclr_value = ((mode1_clear == "0") ||(mode1_clear == "none")) ? 4'b0000 :
(mode1_clear == "1") ? 4'b0001 :
(mode1_clear == "2") ? 4'b0010 :
(mode1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign mode1_inreg_clk = clk[mode1_inreg_clk_value] ? 'b1 : 'b0;
assign mode1_inreg_aclr = aclr[mode1_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign mode1_inreg_ena = ena[mode1_inreg_clk_value] ? 'b1 : 'b0;
assign mode1_inreg_bypass_register = (mode1_clock == "none") ? 'b1 : 'b0;
//Instantiate mode1 pipeline register
stratixii_mac_register mode1_pipreg (
.datain(mode1_inreg_pipreg),
.clk(mode1_pipreg_clk),
.aclr(mode1_pipreg_aclr),
.ena(mode1_pipreg_ena),
.bypass_register(mode1_pipreg_bypass_register),
.dataout(mode1_pipreg_out)
);
defparam mode1_pipreg.data_width = 1;
//decode the clk and aclr values
assign mode1_pipreg_clk_value =((mode1_pipeline_clock == "0") || (mode1_pipeline_clock == "none")) ? 4'b0000 :
(mode1_pipeline_clock == "1") ? 4'b0001 :
(mode1_pipeline_clock == "2") ? 4'b0010 :
(mode1_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign mode1_pipreg_aclr_value = ((mode1_pipeline_clear == "0") ||(mode1_pipeline_clear == "none")) ? 4'b0000 :
(mode1_pipeline_clear == "1") ? 4'b0001 :
(mode1_pipeline_clear == "2") ? 4'b0010 :
(mode1_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign mode1_pipreg_clk = clk[mode1_pipreg_clk_value] ? 'b1 : 'b0;
assign mode1_pipreg_aclr = aclr[mode1_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign mode1_pipreg_ena = ena[mode1_pipreg_clk_value] ? 'b1 : 'b0;
assign mode1_pipreg_bypass_register = (mode1_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate multabsaturate input register
stratixii_mac_register multabsaturate_inreg(
.datain(multabsaturate),
.clk(multabsaturate_inreg_clk),
.aclr(multabsaturate_inreg_aclr),
.ena(multabsaturate_inreg_ena),
.bypass_register(multabsaturate_inreg_bypass_register),
.dataout(multabsaturate_inreg_pipreg)
);
defparam multabsaturate_inreg.data_width = 1;
//decode the clk and aclr values
assign multabsaturate_inreg_clk_value =((multabsaturate_clock == "0") || (multabsaturate_clock == "none")) ? 4'b0000 :
(multabsaturate_clock == "1") ? 4'b0001 :
(multabsaturate_clock == "2") ? 4'b0010 :
(multabsaturate_clock == "3") ? 4'b0011 : 4'b0000;
assign multabsaturate_inreg_aclr_value = ((multabsaturate_clear == "0") ||(multabsaturate_clear == "none")) ? 4'b0000 :
(multabsaturate_clear == "1") ? 4'b0001 :
(multabsaturate_clear == "2") ? 4'b0010 :
(multabsaturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign multabsaturate_inreg_clk = clk[multabsaturate_inreg_clk_value] ? 'b1 : 'b0;
assign multabsaturate_inreg_aclr = aclr[multabsaturate_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign multabsaturate_inreg_ena = ena[multabsaturate_inreg_clk_value] ? 'b1 : 'b0;
assign multabsaturate_inreg_bypass_register = (multabsaturate_clock == "none") ? 'b1 : 'b0;
//Instantiate multabsaturate pipeline register
stratixii_mac_register multabsaturate_pipreg(
.datain(multabsaturate_inreg_pipreg),
.clk(multabsaturate_pipreg_clk),
.aclr(multabsaturate_pipreg_aclr),
.ena(multabsaturate_pipreg_ena),
.bypass_register(multabsaturate_pipreg_bypass_register),
.dataout(multabsaturate_pipreg_out)
);
defparam multabsaturate_pipreg.data_width = 1;
//decode the clk and aclr values
assign multabsaturate_pipreg_clk_value =((multabsaturate_pipeline_clock == "0") || (multabsaturate_pipeline_clock == "none")) ? 4'b0000 :
(multabsaturate_pipeline_clock == "1") ? 4'b0001 :
(multabsaturate_pipeline_clock == "2") ? 4'b0010 :
(multabsaturate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign multabsaturate_pipreg_aclr_value = ((multabsaturate_pipeline_clear == "0") ||(multabsaturate_pipeline_clear == "none")) ? 4'b0000 :
(multabsaturate_pipeline_clear == "1") ? 4'b0001 :
(multabsaturate_pipeline_clear == "2") ? 4'b0010 :
(multabsaturate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign multabsaturate_pipreg_clk = clk[multabsaturate_pipreg_clk_value] ? 'b1 : 'b0;
assign multabsaturate_pipreg_aclr = aclr[multabsaturate_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign multabsaturate_pipreg_ena = ena[multabsaturate_pipreg_clk_value] ? 'b1 : 'b0;
assign multabsaturate_pipreg_bypass_register = (multabsaturate_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate multcdsaturate input register
stratixii_mac_register multcdsaturate_inreg(
.datain(multcdsaturate),
.clk(multcdsaturate_inreg_clk),
.aclr(multcdsaturate_inreg_aclr),
.ena(multcdsaturate_inreg_ena),
.bypass_register(multcdsaturate_inreg_bypass_register),
.dataout(multcdsaturate_inreg_pipreg)
);
defparam multcdsaturate_inreg.data_width = 1;
//decode the clk and aclr values
assign multcdsaturate_inreg_clk_value =((multcdsaturate_clock == "0") || (multcdsaturate_clock == "none")) ? 4'b0000 :
(multcdsaturate_clock == "1") ? 4'b0001 :
(multcdsaturate_clock == "2") ? 4'b0010 :
(multcdsaturate_clock == "3") ? 4'b0011 : 4'b0000;
assign multcdsaturate_inreg_aclr_value = ((multcdsaturate_clear == "0") ||(multcdsaturate_clear == "none")) ? 4'b0000 :
(multcdsaturate_clear == "1") ? 4'b0001 :
(multcdsaturate_clear == "2") ? 4'b0010 :
(multcdsaturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign multcdsaturate_inreg_clk = clk[multcdsaturate_inreg_clk_value] ? 'b1 : 'b0;
assign multcdsaturate_inreg_aclr = aclr[multcdsaturate_inreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign multcdsaturate_inreg_ena = ena[multcdsaturate_inreg_clk_value] ? 'b1 : 'b0;
assign multcdsaturate_inreg_bypass_register = (multcdsaturate_clock == "none") ? 'b1 : 'b0;
//Instantiate multcdsaturate pipeline register
stratixii_mac_register multcdsaturate_pipreg(
.datain(multcdsaturate_inreg_pipreg),
.clk(multcdsaturate_pipreg_clk),
.aclr(multcdsaturate_pipreg_aclr),
.ena(multcdsaturate_pipreg_ena),
.bypass_register(multcdsaturate_pipreg_bypass_register),
.dataout(multcdsaturate_pipreg_out)
);
defparam multcdsaturate_pipreg.data_width = 1;
//decode the clk and aclr values
assign multcdsaturate_pipreg_clk_value =((multcdsaturate_pipeline_clock == "0") || (multcdsaturate_pipeline_clock == "none")) ? 4'b0000 :
(multcdsaturate_pipeline_clock == "1") ? 4'b0001 :
(multcdsaturate_pipeline_clock == "2") ? 4'b0010 :
(multcdsaturate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign multcdsaturate_pipreg_aclr_value = ((multcdsaturate_pipeline_clear == "0") ||(multcdsaturate_pipeline_clear == "none")) ? 4'b0000 :
(multcdsaturate_pipeline_clear == "1") ? 4'b0001 :
(multcdsaturate_pipeline_clear == "2") ? 4'b0010 :
(multcdsaturate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign multcdsaturate_pipreg_clk = clk[multcdsaturate_pipreg_clk_value] ? 'b1 : 'b0;
assign multcdsaturate_pipreg_aclr = aclr[multcdsaturate_pipreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign multcdsaturate_pipreg_ena = ena[multcdsaturate_pipreg_clk_value] ? 'b1 : 'b0;
assign multcdsaturate_pipreg_bypass_register = (multcdsaturate_pipeline_clock == "none") ? 'b1 : 'b0;
//Instantiate the mac_out internal logic
stratixii_mac_out_internal mac_out_block(
.dataa(mac_out_dataa),
.datab(mac_out_datab),
.datac(mac_out_datac),
.datad(mac_out_datad),
.mode0(mode0_pipreg_out),
.mode1(mode1_pipreg_out),
.roundab(round0_pipreg_out),
.saturateab(saturate_pipreg_out),
.roundcd(round1_pipreg_out),
.saturatecd(saturate1_pipreg_out),
.multabsaturate(multabsaturate_pipreg_out),
.multcdsaturate(multcdsaturate_pipreg_out),
.signa(signa_pipreg_out),
.signb(signb_pipreg_out),
.addnsub0(addnsub0_pipreg_out),
.addnsub1(addnsub1_pipreg_out),
.zeroacc(zeroacc_pipreg_out),
.zeroacc1(zeroacc1_pipreg_out),
.feedback(mac_out_feedback),
.dataout(mac_out_dataout),
.accoverflow(mac_out_accoverflow)
);
defparam mac_out_block.operation_mode = operation_mode;
defparam mac_out_block.dataa_width = dataa_width;
defparam mac_out_block.datab_width = datab_width;
defparam mac_out_block.datac_width = datac_width;
defparam mac_out_block.datad_width = datad_width;
assign mac_out_dataa = (dataa_forced_to_zero == "yes") ? 36'b0 : dataa;
assign mac_out_datac = (datac_forced_to_zero == "yes") ? 36'b0 : datac;
assign mac_out_datab = datab;
assign mac_out_datad = datad;
//Instantiate the output register
stratixii_mac_register output_register(
.datain(mac_out_dataout[71:0]),
.clk(outreg_clk),
.aclr(outreg_aclr),
.ena(outreg_ena),
.bypass_register(outreg_bypass_register),
.dataout(outreg_dataout)
);
defparam output_register.data_width = 72;
//decode the clk and aclr values
assign outreg_clk_value =((output_clock== "0") || (output_clock== "none")) ? 4'b0000 :
(output_clock== "1") ? 4'b0001 :
(output_clock== "2") ? 4'b0010 :
(output_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg_aclr_value = ((output_clear == "0") ||(output_clear == "none")) ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg_clk = clk[outreg_clk_value] ? 'b1 : 'b0;
assign outreg_aclr = aclr[outreg_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg_ena = ena[outreg_clk_value] ? 'b1 : 'b0;
assign outreg_bypass_register = (output_clock== "none") ? 'b1 : 'b0;
//Instantiate the accum overflow register
stratixii_mac_register accoverflow_register(
.datain(mac_out_accoverflow),
.clk(outreg_clk),
.aclr(outreg_aclr),
.ena(outreg_ena),
.bypass_register(outreg_bypass_register),
.dataout(accoverflow)
);
defparam accoverflow_register.data_width = 1;
//Instantiate the output register1
stratixii_mac_register output_register1(
.datain(mac_out_dataout[35:18]),
.clk(outreg1_clk),
.aclr(outreg1_aclr),
.ena(outreg1_ena),
.bypass_register(outreg1_bypass_register),
.dataout(outreg1_dataout)
);
defparam output_register1.data_width = 18;
//decode the clk and aclr values
assign outreg1_clk_value =((output1_clock== "0") || (output1_clock== "none")) ? 4'b0000 :
(output1_clock== "1") ? 4'b0001 :
(output1_clock== "2") ? 4'b0010 :
(output1_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg1_aclr_value = ((output1_clear == "0") ||(output1_clear == "none")) ? 4'b0000 :
(output1_clear == "1") ? 4'b0001 :
(output1_clear == "2") ? 4'b0010 :
(output1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg1_clk = clk[outreg1_clk_value] ? 'b1 : 'b0;
assign outreg1_aclr = aclr[outreg1_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg1_ena = ena[outreg1_clk_value] ? 'b1 : 'b0;
assign outreg1_bypass_register = (output1_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register2
stratixii_mac_register output_register2(
.datain(mac_out_dataout[53:36]),
.clk(outreg2_clk),
.aclr(outreg2_aclr),
.ena(outreg2_ena),
.bypass_register(outreg2_bypass_register),
.dataout(outreg2_dataout)
);
defparam output_register2.data_width = 18;
//decode the clk and aclr values
assign outreg2_clk_value =((output2_clock== "0") || (output2_clock== "none")) ? 4'b0000 :
(output2_clock== "1") ? 4'b0001 :
(output2_clock== "2") ? 4'b0010 :
(output2_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg2_aclr_value = ((output2_clear == "0") ||(output2_clear == "none")) ? 4'b0000 :
(output2_clear == "1") ? 4'b0001 :
(output2_clear == "2") ? 4'b0010 :
(output2_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg2_clk = clk[outreg2_clk_value] ? 'b1 : 'b0;
assign outreg2_aclr = aclr[outreg2_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg2_ena = ena[outreg2_clk_value] ? 'b1 : 'b0;
assign outreg2_bypass_register = (output2_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register3
stratixii_mac_register output_register3(
.datain(mac_out_dataout[71:54]),
.clk(outreg3_clk),
.aclr(outreg3_aclr),
.ena(outreg3_ena),
.bypass_register(outreg3_bypass_register),
.dataout(outreg3_dataout)
);
defparam output_register3.data_width = 18;
//decode the clk and aclr values
assign outreg3_clk_value =((output3_clock== "0") || (output3_clock== "none")) ? 4'b0000 :
(output3_clock== "1") ? 4'b0001 :
(output3_clock== "2") ? 4'b0010 :
(output3_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg3_aclr_value = ((output3_clear == "0") ||(output3_clear == "none")) ? 4'b0000 :
(output3_clear == "1") ? 4'b0001 :
(output3_clear == "2") ? 4'b0010 :
(output3_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg3_clk = clk[outreg3_clk_value] ? 'b1 : 'b0;
assign outreg3_aclr = aclr[outreg3_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg3_ena = ena[outreg3_clk_value] ? 'b1 : 'b0;
assign outreg3_bypass_register = (output3_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register4
stratixii_mac_register output_register4(
.datain(mac_out_dataout[89:72]),
.clk(outreg4_clk),
.aclr(outreg4_aclr),
.ena(outreg4_ena),
.bypass_register(outreg4_bypass_register),
.dataout(outreg4_dataout)
);
defparam output_register4.data_width = 18;
//decode the clk and aclr values
assign outreg4_clk_value =((output4_clock== "0") || (output4_clock== "none")) ? 4'b0000 :
(output4_clock== "1") ? 4'b0001 :
(output4_clock== "2") ? 4'b0010 :
(output4_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg4_aclr_value = ((output4_clear == "0") ||(output4_clear == "none")) ? 4'b0000 :
(output4_clear == "1") ? 4'b0001 :
(output4_clear == "2") ? 4'b0010 :
(output4_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg4_clk = clk[outreg4_clk_value] ? 'b1 : 'b0;
assign outreg4_aclr = aclr[outreg4_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg4_ena = ena[outreg4_clk_value] ? 'b1 : 'b0;
assign outreg4_bypass_register = (output4_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register5
stratixii_mac_register output_register5(
.datain(mac_out_dataout[107:90]),
.clk(outreg5_clk),
.aclr(outreg5_aclr),
.ena(outreg5_ena),
.bypass_register(outreg5_bypass_register),
.dataout(outreg5_dataout)
);
defparam output_register5.data_width = 18;
//decode the clk and aclr values
assign outreg5_clk_value =((output5_clock== "0") || (output5_clock== "none")) ? 4'b0000 :
(output5_clock== "1") ? 4'b0001 :
(output5_clock== "2") ? 4'b0010 :
(output5_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg5_aclr_value = ((output5_clear == "0") ||(output5_clear == "none")) ? 4'b0000 :
(output5_clear == "1") ? 4'b0001 :
(output5_clear == "2") ? 4'b0010 :
(output5_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg5_clk = clk[outreg5_clk_value] ? 'b1 : 'b0;
assign outreg5_aclr = aclr[outreg5_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg5_ena = ena[outreg5_clk_value] ? 'b1 : 'b0;
assign outreg5_bypass_register = (output5_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register6
stratixii_mac_register output_register6(
.datain(mac_out_dataout[125:108]),
.clk(outreg6_clk),
.aclr(outreg6_aclr),
.ena(outreg6_ena),
.bypass_register(outreg6_bypass_register),
.dataout(outreg6_dataout)
);
defparam output_register6.data_width = 18;
//decode the clk and aclr values
assign outreg6_clk_value =((output6_clock== "0") || (output6_clock== "none")) ? 4'b0000 :
(output6_clock== "1") ? 4'b0001 :
(output6_clock== "2") ? 4'b0010 :
(output6_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg6_aclr_value = ((output6_clear == "0") ||(output6_clear == "none")) ? 4'b0000 :
(output6_clear == "1") ? 4'b0001 :
(output6_clear == "2") ? 4'b0010 :
(output6_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg6_clk = clk[outreg6_clk_value] ? 'b1 : 'b0;
assign outreg6_aclr = aclr[outreg6_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg6_ena = ena[outreg6_clk_value] ? 'b1 : 'b0;
assign outreg6_bypass_register = (output6_clock== "none") ? 'b1 : 'b0;
//Instantiate the output register7
stratixii_mac_register output_register7(
.datain(mac_out_dataout[143:126]),
.clk(outreg7_clk),
.aclr(outreg7_aclr),
.ena(outreg7_ena),
.bypass_register(outreg7_bypass_register),
.dataout(outreg7_dataout)
);
defparam output_register7.data_width = 18;
//decode the clk and aclr values
assign outreg7_clk_value =((output7_clock== "0") || (output7_clock== "none")) ? 4'b0000 :
(output7_clock== "1") ? 4'b0001 :
(output7_clock== "2") ? 4'b0010 :
(output7_clock== "3") ? 4'b0011 : 4'b0000;
assign outreg7_aclr_value = ((output7_clear == "0") ||(output7_clear == "none")) ? 4'b0000 :
(output7_clear == "1") ? 4'b0001 :
(output7_clear == "2") ? 4'b0010 :
(output7_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign outreg7_clk = clk[outreg7_clk_value] ? 'b1 : 'b0;
assign outreg7_aclr = aclr[outreg7_aclr_value] || ~devclrn || ~devpor ? 'b1 : 'b0;
assign outreg7_ena = ena[outreg7_clk_value] ? 'b1 : 'b0;
assign outreg7_bypass_register = (output7_clock== "none") ? 'b1 : 'b0;
//assign the dynamic-mode output
assign dataout_dynamic = {outreg7_dataout,outreg6_dataout,outreg5_dataout,outreg4_dataout,
outreg3_dataout,outreg2_dataout,outreg1_dataout,outreg_dataout[17:0]};
//assign the dataout depending on the mode of operation
assign dataout_tmp = (operation_mode == "dynamic") ? dataout_dynamic : outreg_dataout;
assign dataout = dataout_tmp;
//assign the feedback for accumulator mode of operation
assign mac_out_feedback = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_rx_fifo_sync_ram
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_rx_fifo_sync_ram (clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// parameter ram_width = 10;
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg [0:5] ram_d;
reg [0:5] ram_q;
wire [0:5] data_reg;
integer i;
initial
begin
dataout_tmp = 0;
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
// Write port
always @(posedge clk or posedge write_reset)
begin
if(write_reset == 1'b1)
begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
else begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= ram_d[i];
end
end
always @(we or data_reg or ram_q)
begin
if(we === 1'b1)
begin
ram_d <= data_reg;
end
else begin
ram_d <= ram_q;
end
end
// Read port
assign data_reg[0] = ( waddr == 3'b000 ) ? datain : ram_q[0];
assign data_reg[1] = ( waddr == 3'b001 ) ? datain : ram_q[1];
assign data_reg[2] = ( waddr == 3'b010 ) ? datain : ram_q[2];
assign data_reg[3] = ( waddr == 3'b011 ) ? datain : ram_q[3];
assign data_reg[4] = ( waddr == 3'b100 ) ? datain : ram_q[4];
assign data_reg[5] = ( waddr == 3'b101 ) ? datain : ram_q[5];
always @(ram_q or we or waddr or raddr)
begin
case ( raddr )
3'b000 : dataout_tmp = ram_q[0];
3'b001 : dataout_tmp = ram_q[1];
3'b010 : dataout_tmp = ram_q[2];
3'b011 : dataout_tmp = ram_q[3];
3'b100 : dataout_tmp = ram_q[4];
3'b101 : dataout_tmp = ram_q[5];
default : dataout_tmp = 0;
endcase
end
// set output
assign dataout = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_rx_fifo
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_rx_fifo (wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
wire data_out;
integer i;
reg ram_datain;
wire ram_dataout;
reg [2:0] wrPtr,rdPtr; // writer pointer, read pointer
wire [2:0] rdAddr; // read address
reg ram_we;
reg wclk_last_value, rclk_last_value;
reg write_side_sync_reset;
reg read_side_sync_reset;
// BUFFER INPUTS
wire wclk_in;
wire rclk_in;
wire dparst_in;
wire fiforst_in;
wire datain_in;
buf (wclk_in, wclk);
buf (rclk_in, rclk);
buf (dparst_in, dparst);
buf (fiforst_in, fiforst);
buf (datain_in, datain);
specify
(posedge rclk => (dataout +: data_out)) = (0, 0);
(posedge dparst => (dataout +: data_out)) = (0, 0);
endspecify
initial
begin
dataout_tmp = 0;
wrPtr = 2'b00;
rdPtr = 2'b11;
write_side_sync_reset = 1'b0;
read_side_sync_reset = 1'b0;
end
assign rdAddr = rdPtr;
stratixii_lvds_rx_fifo_sync_ram s_fifo_ram (.clk(wclk_in),
.datain(ram_datain),
.write_reset(write_side_sync_reset),
.waddr(wrPtr),
.raddr(rdAddr), // rdPtr ??
.we(ram_we),
.dataout(ram_dataout)
);
// update pointer and RAM input
always @(wclk_in or dparst_in)
begin
if (dparst_in === 1'b1 || (fiforst_in === 1'b1 && wclk_in === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b1;
ram_datain <= 1'b0;
wrPtr <= 0;
ram_we <= 'b0;
end
else if (dparst_in === 1'b0 && (fiforst_in === 1'b0 && wclk_in === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b0;
end
if (wclk_in === 1'b1 && wclk_last_value === 1'b0 && write_side_sync_reset === 1'b0 && fiforst_in === 1'b0 && dparst_in === 1'b0)
begin
ram_datain <= datain_in; // input register
ram_we <= 'b1;
wrPtr <= wrPtr + 1;
if (wrPtr == 5)
wrPtr <= 0;
end
wclk_last_value = wclk_in;
end
always @(rclk_in or dparst_in)
begin
if (dparst_in === 1'b1 || (fiforst_in === 1'b1 && rclk_in === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 1'b1;
rdPtr <= 3;
dataout_tmp <= 0;
end
else if (dparst_in === 1'b0 && (fiforst_in === 1'b0 && rclk_in === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 0;
end
if (rclk_in === 1'b1 && rclk_last_value === 1'b0 && read_side_sync_reset === 1'b0 && fiforst_in === 1'b0 && dparst_in === 1'b0)
begin
rdPtr <= rdPtr + 1;
if (rdPtr == 5)
rdPtr <= 0;
dataout_tmp <= ram_dataout; // output register
end
rclk_last_value = rclk_in;
end
assign data_out = dataout_tmp;
buf (dataout, data_out);
endmodule // stratixii_lvds_rx_fifo
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_rx_bitslip
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_rx_bitslip (clk0,
bslipcntl,
bsliprst,
datain,
bslipmax,
dataout
);
parameter channel_width = 10;
parameter bitslip_rollover = 12;
parameter x_on_bitslip = "on";
// INPUT PORTS
input clk0;
input bslipcntl;
input bsliprst;
input datain;
// OUTPUT PORTS
output bslipmax;
output dataout;
// INTERNAL VARIABLES AND NETS
integer slip_count;
integer i, j;
wire dataout_tmp;
wire dataout_wire;
wire bslipmax_wire;
reg clk0_last_value;
reg bsliprst_last_value;
reg bslipcntl_last_value;
reg start_corrupt_bits;
reg [1:0] num_corrupt_bits;
reg [11:0] bitslip_arr;
reg bslipmax_tmp;
reg ix_on_bitslip;
// BUFFER INPUTS
wire clk0_in;
wire bslipcntl_in;
wire bsliprst_in;
wire datain_in;
buf (clk0_in, clk0);
buf (bslipcntl_in, bslipcntl);
buf (bsliprst_in, bsliprst);
buf (datain_in, datain);
wire bslipcntl_reg;
// TIMING PATHS
specify
(posedge clk0 => (bslipmax +: bslipmax_tmp)) = (0, 0);
(posedge bsliprst => (bslipmax +: bslipmax_tmp)) = (0, 0);
endspecify
initial
begin
slip_count = 0;
bslipmax_tmp = 0;
bitslip_arr = 12'b0;
start_corrupt_bits = 0;
num_corrupt_bits = 0;
if (x_on_bitslip == "on")
ix_on_bitslip = 1;
else
ix_on_bitslip = 0;
end
stratixii_lvds_reg bslipcntlreg (.d(bslipcntl_in),
.clk(clk0_in),
.ena(1'b1),
.clrn(!bsliprst_in),
.prn(1'b1),
.q(bslipcntl_reg)
);
// 4-bit slip counter
always @(bslipcntl_reg or bsliprst_in)
begin
if (bsliprst_in === 1'b1)
begin
slip_count <= 0;
bslipmax_tmp <= 1'b0;
if (bsliprst_in === 1'b1 && bsliprst_last_value === 1'b0)
begin
$display("Note: Bit Slip Circuit was reset. Serial Data stream will have 0 latency");
$display("Time: %0t, Instance: %m", $time);
end
end
else if (bslipcntl_reg === 1'b1 && bslipcntl_last_value === 1'b0)
begin
if (ix_on_bitslip == 1)
start_corrupt_bits <= 1;
num_corrupt_bits <= 0;
if (slip_count == bitslip_rollover)
begin
$display("Note: Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency.");
$display("Time: %0t, Instance: %m", $time);
slip_count <= 0;
bslipmax_tmp <= 1'b0;
end
else begin
slip_count <= slip_count + 1;
if ((slip_count+1) == bitslip_rollover)
begin
$display("Note: The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip.");
$display("Time: %0t, Instance: %m", $time);
bslipmax_tmp <= 1'b1;
end
end
end
else if (bslipcntl_reg === 1'b0 && bslipcntl_last_value === 1'b1)
begin
start_corrupt_bits <= 0;
num_corrupt_bits <= 0;
end
bslipcntl_last_value <= bslipcntl_reg;
bsliprst_last_value <= bsliprst_in;
end
// Bit Slip shift register
always @(clk0_in)
begin
if (clk0_in === 1'b1 && clk0_last_value === 1'b0)
begin
bitslip_arr[0] <= datain_in;
for (i = 0; i < bitslip_rollover; i=i+1)
bitslip_arr[i+1] <= bitslip_arr[i];
if (start_corrupt_bits == 1'b1)
num_corrupt_bits <= num_corrupt_bits + 1;
if (num_corrupt_bits+1 == 3)
start_corrupt_bits <= 0;
end
clk0_last_value <= clk0_in;
end
stratixii_lvds_reg dataoutreg (.d(bitslip_arr[slip_count]),
.clk(clk0_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(dataout_tmp)
);
assign dataout_wire = (start_corrupt_bits == 1'b0) ? dataout_tmp : (num_corrupt_bits < 3) ? 1'bx : dataout_tmp;
assign bslipmax_wire = bslipmax_tmp;
and (dataout, dataout_wire, 1'b1);
and (bslipmax, bslipmax_wire, 1'b1);
endmodule // stratixii_lvds_rx_bitslip
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_rx_deser
//
// Description : Timing simulation model for the STRATIXII LVDS RECEIVER
// Deserializer. This module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_rx_deser (clk,
datain,
devclrn,
devpor,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input clk;
input datain;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg [channel_width - 1:0] dataout_tmp;
reg clk_last_value;
integer i;
wire clk_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or devclrn or devpor)
begin
if (devclrn === 1'b0 || devpor === 1'b0)
begin
dataout_tmp <= 'b0;
end
else if (clk_ipd === 1'b1 && clk_last_value === 1'b0)
begin
for (i = (channel_width-1); i > 0; i=i-1)
dataout_tmp[i] <= dataout_tmp[i-1];
dataout_tmp[0] <= datain_ipd;
end
clk_last_value <= clk_ipd;
end
assign dataout_opd = dataout_tmp;
endmodule //stratixii_lvds_rx_deser
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_rx_parallel_reg
//
// Description : Timing simulation model for the STRATIXII LVDS RECEIVER
// PARALLEL REGISTER. The data width equals max. channel width,
// which is 10.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_rx_parallel_reg (clk,
enable,
datain,
dataout,
// reset,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
// input reset;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else begin
if ((clk_ipd === 1) && (clk_last_value !== clk_ipd))
begin
// if (reset === 1)
// begin
// dataout_tmp <= 10'b0;
// end
// else if (enable_in === 1)
if (enable_ipd === 1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end //always
assign dataout_opd = dataout_tmp;
endmodule //stratixii_lvds_rx_parallel_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratixii_lvds_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module stratixii_lvds_reg (q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1))
q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // stratixii_lvds_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : STRATIXII_LVDS_RECEIVER
//
// Description : Timing simulation model for the STRATIXII LVDS RECEIVER
// atom. This module instantiates the following sub-modules :
// 1) stratixii_lvds_rx_fifo
// 2) stratixii_lvds_rx_bitslip
// 3) DFFEs for the LOADEN signals
// 4) stratixii_lvds_rx_deser
// 5) stratixii_lvds_rx_parallel_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_lvds_receiver (clk0,
datain,
enable0,
dpareset,
dpahold,
dpaswitch,
fiforeset,
bitslip,
bitslipreset,
serialfbk,
dataout,
dpalock,
bitslipmax,
serialdataout,
postdpaserialdataout,
devclrn,
devpor
);
parameter data_align_rollover = 2;
parameter enable_dpa = "off";
parameter lose_lock_on_one_change = "off";
parameter reset_fifo_at_first_lock = "on";
parameter align_to_rising_edge_only = "on";
parameter use_serial_feedback_input = "off";
parameter dpa_debug = "off";
parameter x_on_bitslip = "on";
parameter lpm_type = "stratixii_lvds_receiver";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input clk0;
input datain;
input enable0;
input dpareset;
input dpahold;
input dpaswitch;
input fiforeset;
input bitslip;
input bitslipreset;
input serialfbk;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
output dpalock;
output bitslipmax;
output serialdataout;
output postdpaserialdataout;
tri1 devclrn;
tri1 devpor;
// BUFFER INPUTS
wire clk0_in;
wire datain_in;
wire enable0_in;
wire dpareset_in;
wire dpahold_in;
wire dpaswitch_ipd;
wire fiforeset_in;
wire bitslip_in;
wire bitslipreset_in;
wire serialfbk_in;
buf (clk0_in, clk0);
buf (datain_in, datain);
buf (enable0_in, enable0);
buf (dpareset_in, dpareset);
buf (dpahold_in, dpahold);
buf (dpaswitch_ipd, dpaswitch);
buf (fiforeset_in, fiforeset);
buf (bitslip_in, bitslip);
buf (bitslipreset_in, bitslipreset);
buf (serialfbk_in, serialfbk);
// INTERNAL NETS AND VARIABLES
wire fifo_wclk;
wire fifo_rclk;
wire fifo_datain;
wire fifo_dataout;
wire fifo_reset;
wire slip_datain;
wire slip_dataout;
wire bitslip_reset;
wire [channel_width - 1:0] deser_dataout;
wire dpareg0_out;
wire dpareg1_out;
wire dpa_clk;
wire dpa_rst;
wire datain_reg;
wire datain_reg_neg;
wire datain_reg_tmp;
reg clk0_last_value;
reg dpa_is_locked;
reg dparst_msg;
reg reset_fifo;
reg first_dpa_lock;
reg [3:0] dpa_lock_count;
wire reset_int;
wire gnd;
wire serialdataout_tmp;
wire postdpaserialdataout_tmp;
wire in_reg_data;
wire datain_tmp;
wire dpalock_tmp;
wire rxload;
wire slip_datain_tmp;
wire s_bitslip_clk;
wire loaden;
integer i;
// LOCAL_PARAMETERS_BEGIN
parameter DPA_CYCLES_TO_LOCK = 2;
// LOCAL_PARAMETERS_END
// TIMING PATHS
specify
(posedge clk0 => (dpalock +: dpalock_tmp)) = (0, 0);
endspecify
assign gnd = 1'b0;
// fifo read and write clks
assign fifo_rclk = (enable_dpa == "on") ? clk0_in : gnd;
assign fifo_wclk = dpa_clk;
assign fifo_datain = (enable_dpa == "on") ? dpareg1_out : gnd;
assign reset_int = (!devpor) || (!devclrn);
assign fifo_reset = (!devpor) || (!devclrn) || fiforeset_in || reset_fifo;
assign bitslip_reset = (!devpor) || (!devclrn) || bitslipreset_in;
assign in_reg_data = (use_serial_feedback_input == "on") ? serialfbk_in : datain_in;
initial
begin
dpa_is_locked = 0;
dparst_msg = 0;
first_dpa_lock = 1;
dpa_lock_count = 0;
if (reset_fifo_at_first_lock == "on")
reset_fifo = 1;
else
reset_fifo = 0;
if (enable_dpa == "on")
begin
$display("Warning : DPA Phase tracking is not modeled and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the StratixII device handbook for further details.");
$display("Time: %0t, Instance: %m", $time);
end
end
// SUB-MODULE INSTANTIATION
// input register in non-DPA mode for sampling incoming data
stratixii_lvds_reg in_reg (.d(in_reg_data),
.clk(clk0_in),
.ena(1'b1),
.clrn(devclrn || devpor),
.prn(1'b1),
.q(datain_reg)
);
assign datain_reg_tmp = datain_reg;
assign dpa_clk = (enable_dpa == "on") ? clk0_in : 1'b0;
assign dpa_rst = (enable_dpa == "on") ? dpareset_in : 1'b0;
always @(posedge dpa_clk or posedge dpa_rst)
begin
if (dpa_rst === 1'b1)
begin
dpa_is_locked <= 0;
dpa_lock_count = 0;
// give message only once
if (dparst_msg === 1'b0)
begin
$display("DPA was reset");
$display("Time: %0t, Instance: %m", $time);
dparst_msg = 1;
end
end
else begin
dparst_msg = 0;
if (dpa_is_locked === 1'b0)
begin
dpa_lock_count = dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK)
begin
dpa_is_locked <= 1;
$display("DPA locked");
$display("Time: %0t, Instance: %m", $time);
reset_fifo <= 0;
end
end
end
end
// ?????????? insert delay to mimic DPLL dataout ?????????
// DPA registers
stratixii_lvds_reg dpareg0 (.d(in_reg_data),
.clk(dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg0_out)
);
stratixii_lvds_reg dpareg1 (.d(dpareg0_out),
.clk(dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg1_out)
);
stratixii_lvds_rx_fifo s_fifo (.wclk(fifo_wclk),
.rclk(fifo_rclk),
.fiforst(fifo_reset),
.dparst(dpa_rst),
.datain(fifo_datain),
.dataout(fifo_dataout)
);
defparam s_fifo.channel_width = channel_width;
assign slip_datain_tmp = (enable_dpa == "on" && dpaswitch_ipd === 1'b1) ? fifo_dataout : datain_reg_tmp;
assign slip_datain = slip_datain_tmp;
assign s_bitslip_clk = clk0_in;
stratixii_lvds_rx_bitslip s_bslip (.clk0(s_bitslip_clk),
.bslipcntl(bitslip_in),
.bsliprst(bitslip_reset),
.datain(slip_datain),
.bslipmax(bitslipmax),
.dataout(slip_dataout)
);
defparam s_bslip.channel_width = channel_width;
defparam s_bslip.bitslip_rollover = data_align_rollover;
defparam s_bslip.x_on_bitslip = x_on_bitslip;
//********* DESERIALISER *********//
assign loaden = enable0_in;
// only 1 enable signal used for StratixII
stratixii_lvds_reg rxload_reg (.d(loaden),
.clk(s_bitslip_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(rxload)
);
stratixii_lvds_rx_deser s_deser (.clk(s_bitslip_clk),
.datain(slip_dataout),
.devclrn(devclrn),
.devpor(devpor),
.dataout(deser_dataout)
);
defparam s_deser.channel_width = channel_width;
stratixii_lvds_rx_parallel_reg output_reg (.clk(s_bitslip_clk),
.enable(rxload),
.datain(deser_dataout),
.devpor(devpor),
.devclrn(devclrn),
.dataout(dataout)
);
defparam output_reg.channel_width = channel_width;
// generate outputs
assign dpalock_tmp = (enable_dpa == "on") ? dpa_is_locked : gnd;
assign postdpaserialdataout_tmp = dpareg1_out;
assign datain_tmp = datain_in;
and (postdpaserialdataout, postdpaserialdataout_tmp, 1'b1);
and (serialdataout, datain_tmp, 1'b1);
and (dpalock, dpalock_tmp, 1'b1);
endmodule // stratixii_lvds_receiver
///////////////////////////////////////////////////////////////////////
//
// STRATIXII RUBLOCK ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixii_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout,
pgmout
);
parameter operation_mode = "remote";
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_page_select = 0;
parameter sim_init_status = 0;
parameter lpm_type = "stratixii_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
output [2:0] pgmout;
reg [20:0] update_reg;
reg [4:0] status_reg;
reg [25:0] shift_reg;
reg [2:0] pgmout_update;
integer i;
// initialize registers
initial
begin
if (operation_mode == "local")
// PGM[] output
pgmout_update = 1;
else if (operation_mode == "remote")
// PGM[] output
pgmout_update = 0;
else
pgmout_update <= 'bx;
// Shift reg
shift_reg = 0;
// Status reg
status_reg = sim_init_status;
// wd_timeout field
update_reg[20:9] = sim_init_watchdog_value;
// wd enable field
if (sim_init_watchdog_value > 0)
update_reg[8] = 1;
else
update_reg[8] = 0;
// PGM[] field
update_reg[7:1] = sim_init_page_select;
// AnF bit
if (sim_init_config == "factory")
update_reg[0] = 0;
else
update_reg[0] = 1;
$display("Info: Remote Update Block: Initial configuration:");
$display ("Time: %0t Instance: %m", $time);
$display(" -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to %s", status_reg[0] ? "True" : "False");
$display(" -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False");
$display(" -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False");
$display(" -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False");
$display(" -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False");
$display(" -> Field Configuration Mode is set to %s", update_reg[0] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
$display(" -> Field User Watchdog is set to %s", update_reg[8] ? "Enabled" : "Disabled");
$display(" -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9]);
end
// regout is output of shift-reg bit 0
// note that in Stratix, there is an inverter to regout.
// but in Stratix II, there is no inverter.
assign regout = shift_reg[0];
// pgmout is set when reconfig is asserted
assign pgmout = pgmout_update;
always @(clk)
begin
if (clk == 1)
begin
if (shiftnld == 1)
begin
// register shifting
for (i=0; i<=24; i=i+1)
begin
shift_reg[i] <= shift_reg[i+1];
end
shift_reg[25] <= regin;
end
else if (shiftnld == 0)
begin
// register loading
if (captnupdt == 1)
begin
// capture data into shift register
shift_reg <= {update_reg, status_reg};
end
else if (captnupdt == 0)
begin
// update data from shift into Update Register
if ( (operation_mode == "remote" || operation_mode =="active_serial_remote")
&& sim_init_config == "factory")
begin
// every bit in Update Reg gets updated
update_reg[20:0] <= shift_reg[25:5];
$display("Info: Remote Update Block: Update Register updated at time %d ps", $time);
$display(" -> Field Configuration Mode is set to %s", shift_reg[5] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", shift_reg[12:6]);
$display(" -> Field User Watchdog is set to %s", (shift_reg[13] == 1) ? "Enabled" : (shift_reg[13] == 0) ? "Disabled" : "x");
$display(" -> Field User Watchdog Timeout Value is set to %d", shift_reg[25:14]);
end
else
begin
// trying to do update in Application mode
$display("Warning: Remote Update Block: Attempted update of Update Register at time %d ps when Configuration is set to Application", $time);
end
end
else
begin
// invalid captnupdt
// destroys update and shift regs
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[20:1] <= 'bx;
end
end
end
else
begin
// invalid shiftnld: destroys update and shift regs
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[20:1] <= 'bx;
end
end
end
else if (clk != 0)
begin
// invalid clk: destroys registers
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[20:1] <= 'bx;
end
end
end
always @(rconfig)
begin
if (rconfig == 1)
begin
// start reconfiguration
$display("Info: Remote Update Block: Reconfiguration initiated at time %d ps", $time);
$display(" -> Field Configuration Mode is set to %s", update_reg[0] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
$display(" -> Field User Watchdog is set to %s", (update_reg[8] == 1) ? "Enabled" : (update_reg[8] == 0) ? "Disabled" : "x");
$display(" -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9]);
if (operation_mode == "remote")
begin
// set pgm[] to page as set in Update Register
pgmout_update <= update_reg[3:1];
end
else if (operation_mode == "local")
begin
// set pgm[] to page as 001
pgmout_update <= 'b001;
end
else
begin
// invalid rconfig: destroys pgmout
pgmout_update <= 'bx;
end
end
else if (rconfig != 0)
begin
// invalid rconfig: destroys pgmout
pgmout_update <= 'bx;
end
end
endmodule
//------------------------------------------------------------------
//
// Module Name : stratixii_termination_digital
//
// Description : Simualtion model for digital portion of
// StratixII Calibration Block
//
// ** Note ** : Termination calibration block does not have
// digital outputs that are observable in PLD by
// users. The model below is for internal verification.
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_termination_digital (
rin,
clk,
clr,
ena,
padder,
devpor,
devclrn,
ctrlout);
input rin;
input clk;
input clr;
input ena;
input [6:0] padder;
input devpor;
input devclrn;
output [6:0] ctrlout;
parameter runtime_control = "false";
parameter use_core_control = "false";
parameter use_both_compares = "false";
parameter pull_adder = 0;
parameter power_down = "true";
parameter left_shift = "false";
parameter test_mode = "false";
// internal variables
reg rin_reg_n;
reg [6:0] counter1;
// pattern detect
reg pdetect_reg_n;
reg pdetect_reg_1;
reg pdetect_reg_2;
wire pdetect_out;
wire pre_adder_reg_n_ena;
reg [6:0] pre_adder_reg_n;
wire pre_adder_reg_ena;
reg [6:0] pre_adder_reg;
wire [6:0] adder_in;
wire [6:0] adder1;
// Model
initial
begin
rin_reg_n = 1'b0;
counter1 = 7'b1000000;
pdetect_reg_n = 1'b0;
pdetect_reg_1 = 1'b0;
pdetect_reg_2 = 1'b0;
pre_adder_reg_n = 7'b0100000;
pre_adder_reg = 7'b0100000;
end
assign ctrlout = (use_core_control == "true") ? padder : adder1;
// negative-edge register
always @(negedge clk or posedge clr)
begin
if (clr === 1'b1)
rin_reg_n <= 1'b0;
else
rin_reg_n <= rin;
end
// counter
always @(posedge clk or posedge clr)
begin
if (clr === 1'b1)
counter1 <= 7'b1000000;
else if (ena === 1'b1)
begin
if (rin_reg_n === 1'b0 && counter1 > 7'b000000)
counter1 <= counter1 - 7'b0000001;
else if (rin_reg_n === 1'b1 && counter1 < 7'b1111111)
counter1 <= counter1 + 7'b0000001;
end
end
// 01 patter detector
assign pdetect_out = ((pdetect_reg_2 === 1'b0) && (pdetect_reg_1 === 1'b1))? 1'b1 : 1'b0;
always @(negedge clk)
pdetect_reg_n <= rin_reg_n;
always @(posedge clk)
begin
pdetect_reg_1 <= rin_reg_n;
pdetect_reg_2 <= pdetect_reg_1;
end
// pre adder registers
assign pre_adder_reg_n_ena = (test_mode === "true") ? ena
: (ena && pdetect_out);
always @(negedge clk or posedge clr)
begin
if (clr === 1'b1)
pre_adder_reg_n <= 7'b0100000;
else if (pre_adder_reg_n_ena === 1'b1)
pre_adder_reg_n <= counter1;
end
// 0101/1010 pdetector always returns false
// adder
assign adder_in = (left_shift === "false") ? pre_adder_reg_n
: (pre_adder_reg_n << 1);
// no clock for adder
assign adder1 = adder_in + pull_adder;
endmodule
//------------------------------------------------------------------
//
// Module Name : stratixii_termination
//
// Description : StratixII Termination Atom Verilog simulation model
//
// ** Note ** : Termination calibration block does not have
// digital outputs that are observable in PLD by
// users. The model below is for internal verification.
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixii_termination (
rup,
rdn,
terminationclock,
terminationclear,
terminationenable,
terminationpullup,
terminationpulldown,
devpor,
devclrn,
incrup,
incrdn,
terminationcontrol,
terminationcontrolprobe);
input rup;
input rdn;
input terminationclock;
input terminationclear;
input terminationenable;
input [6:0] terminationpullup;
input [6:0] terminationpulldown;
input devpor;
input devclrn;
output incrup;
output incrdn;
output [13:0] terminationcontrol;
output [6:0] terminationcontrolprobe;
parameter runtime_control = "false";
parameter use_core_control = "false";
parameter pullup_control_to_core = "true";
parameter use_high_voltage_compare = "true";
parameter use_both_compares = "false";
parameter pullup_adder = 0;
parameter pulldown_adder = 0;
parameter half_rate_clock = "false";
parameter power_down = "true";
parameter left_shift = "false";
parameter test_mode = "false";
parameter lpm_type = "stratixii_termination";
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
wire rup_in;
wire rdn_in;
wire clock_in;
wire clear_in;
wire enable_in;
wire [6:0] pullup_in;
wire [6:0] pulldown_in;
// TMP OUTPUTS
wire incrup_out;
wire incrdn_out;
wire [13:0] control_out;
wire [6:0] controlprobe_out;
wire [6:0] rup_control_out;
wire [6:0] rdn_control_out;
wire ena1;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
// TIMING HOOKS
buf (rup_in, rup);
buf (rdn_in, rdn);
buf (clock_in,terminationclock);
buf (clear_in,terminationclear);
buf (enable_in,terminationenable);
buf buf_pullup [6:0] (pullup_in, terminationpullup);
buf buf_pulldn [6:0] (pulldown_in, terminationpulldown);
specify
(posedge terminationclock => (terminationcontrol +: control_out)) = (0,0);
(posedge terminationclock => (terminationcontrolprobe +: controlprobe_out)) = (0,0);
endspecify
// output driver
buf buf_ctrl_out [13:0] (terminationcontrol,control_out);
buf buf_ctrlprobe_out [6:0] (terminationcontrolprobe,controlprobe_out);
// MODEL
assign incrup = incrup_out;
assign incrdn = incrdn_out;
assign incrup_out = (power_down == "true") ? (enable_in & rup_in) : rup_in;
assign incrdn_out = (power_down == "true") ? ~(enable_in & rdn_in) : ~rdn_in;
assign control_out = {rup_control_out, rdn_control_out};
assign controlprobe_out = pullup_control_to_core == "true" ?
rdn_control_out : rup_control_out;
assign ena1 = (runtime_control === "true")? enable_in : 1'b0;
stratixii_termination_digital rup_block(
.rin(incrup_out),
.clk(clock_in),
.clr(clear_in),
.ena(ena1),
.padder(pulldown_in),
.devpor(devpor),
.devclrn(devclrn),
.ctrlout(rup_control_out)
);
defparam rup_block.runtime_control = runtime_control;
defparam rup_block.use_core_control = use_core_control;
defparam rup_block.use_both_compares = use_both_compares;
defparam rup_block.pull_adder = pulldown_adder;
defparam rup_block.power_down = power_down;
defparam rup_block.left_shift = left_shift;
defparam rup_block.test_mode = test_mode;
stratixii_termination_digital rdn_block(
.rin(incrdn_out),
.clk(clock_in),
.clr(clear_in),
.ena(ena1),
.padder(pullup_in),
.devpor(devpor),
.devclrn(devclrn),
.ctrlout(rdn_control_out)
);
defparam rdn_block.runtime_control = runtime_control;
defparam rdn_block.use_core_control = use_core_control;
defparam rdn_block.use_both_compares = use_both_compares;
defparam rdn_block.pull_adder = pullup_adder;
defparam rdn_block.power_down = power_down;
defparam rdn_block.left_shift = left_shift;
defparam rdn_block.test_mode = test_mode;
endmodule
//------------------------------------------------------------------
//
// Module Name : stratixii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module stratixii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // stratixii_routing_wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_vref_logic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_vref_logic(a ,vrefcode ,c ,b ,vdd18 );
output [7:0] vrefcode ;
input a ;
input c ;
input b ;
input vdd18 ;
wire net202 ;
wire net185 ;
wire net190 ;
wire net193 ;
wire net0106 ;
wire net196 ;
wire net0107 ;
wire net198 ;
wire net0109 ;
wire net0120 ;
wire net181 ;
bw_u1_nand3_1x I1 (
.z (net202 ),
.a (a ),
.b (b ),
.c (c ) );
bw_u1_nand2_1x I2 (
.z (net196 ),
.a (a ),
.b (b ) );
bw_u1_nand2_1x I3 (
.z (net193 ),
.a (net0107 ),
.b (a ) );
bw_u1_nor2_2x I4 (
.z (net190 ),
.a (c ),
.b (b ) );
bw_u1_nand2_1x I9 (
.z (net198 ),
.a (b ),
.b (c ) );
bw_u1_nor2_1x I12 (
.z (net185 ),
.a (b ),
.b (a ) );
bw_u1_nor3_1x I13 (
.z (net181 ),
.a (c ),
.b (b ),
.c (a ) );
bw_u1_inv_1x I47 (
.z (net0106 ),
.a (a ) );
bw_u1_inv_1x I52 (
.z (net0109 ),
.a (net0120 ) );
bw_u1_nand2_1x I53 (
.z (net0120 ),
.a (net0106 ),
.b (net198 ) );
bw_u1_inv_1x I54 (
.z (net0107 ),
.a (net190 ) );
bw_io_ddr_vref_logic_high x0 (
.in ({net202 ,net196 ,net193 ,net0106 ,net0109 ,net185
,net181 } ),
.vrefcode ({vrefcode } ),
.vdd18 (vdd18 ) );
endmodule
|
module latch_ex_mem(
input clock ,
input reset ,
input [ 5:0] stall ,
input [31:0] ex_instruction ,
output reg [31:0] mem_instruction ,
input [ 7:0] ex_operator ,
output reg [ 7:0] mem_operator ,
input [31:0] ex_operand_a ,
output reg [31:0] mem_operand_a ,
input [31:0] ex_operand_b ,
output reg [31:0] mem_operand_b ,
input ex_register_write_enable ,
output reg mem_register_write_enable ,
input [ 4:0] ex_register_write_address ,
output reg [ 4:0] mem_register_write_address ,
input [31:0] ex_register_write_data ,
output reg [31:0] mem_register_write_data ,
input ex_register_hi_write_enable ,
output reg mem_register_hi_write_enable,
input [31:0] ex_register_hi_write_data ,
output reg [31:0] mem_register_hi_write_data ,
input ex_register_lo_write_enable ,
output reg mem_register_lo_write_enable,
input [31:0] ex_register_lo_write_data ,
output reg [31:0] mem_register_lo_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[3] == `STALL_ENABLE && stall[4] == `STALL_DISABLE)) begin
mem_instruction <= 32'b0 ;
mem_operator <= `OPERATOR_NOP ;
mem_operand_a <= 32'b0 ;
mem_operand_b <= 32'b0 ;
mem_register_write_enable <= `WRITE_DISABLE;
mem_register_write_address <= 5'b0 ;
mem_register_write_data <= 32'b0 ;
mem_register_hi_write_enable <= `WRITE_DISABLE;
mem_register_hi_write_data <= 32'b0 ;
mem_register_lo_write_enable <= `WRITE_DISABLE;
mem_register_lo_write_data <= 32'b0 ;
end
else if (stall[3] == `STALL_DISABLE) begin
mem_instruction <= ex_instruction ;
mem_operator <= ex_operator ;
mem_operand_a <= ex_operand_a ;
mem_operand_b <= ex_operand_b ;
mem_register_write_enable <= ex_register_write_enable ;
mem_register_write_address <= ex_register_write_address ;
mem_register_write_data <= ex_register_write_data ;
mem_register_hi_write_enable <= ex_register_hi_write_enable;
mem_register_hi_write_data <= ex_register_hi_write_data ;
mem_register_lo_write_enable <= ex_register_lo_write_enable;
mem_register_lo_write_data <= ex_register_lo_write_data ;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 08:18:10 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire d_ff1_operation_out, d_ff3_sign_out,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_intAS,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n922,
n923, n924, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n981, n982, n983, n984, n985, n986, n988, n989, n990, n991, n992,
n993, n995, n996, n997, n998, n999, n1000, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, DP_OP_33J13_122_2179_n18, DP_OP_33J13_122_2179_n17,
DP_OP_33J13_122_2179_n16, DP_OP_33J13_122_2179_n15,
DP_OP_33J13_122_2179_n14, DP_OP_33J13_122_2179_n8,
DP_OP_33J13_122_2179_n7, DP_OP_33J13_122_2179_n6,
DP_OP_33J13_122_2179_n5, DP_OP_33J13_122_2179_n4,
DP_OP_33J13_122_2179_n3, DP_OP_33J13_122_2179_n2,
DP_OP_33J13_122_2179_n1, intadd_42_B_1_, intadd_42_CI,
intadd_42_SUM_2_, intadd_42_SUM_1_, intadd_42_SUM_0_, intadd_42_n3,
intadd_42_n2, intadd_42_n1, intadd_43_CI, intadd_43_SUM_2_,
intadd_43_SUM_1_, intadd_43_SUM_0_, intadd_43_n3, intadd_43_n2,
intadd_43_n1, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3053, n3054, n3055, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [31:0] result_add_subt;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS ITER_CONT_temp_reg_2_ ( .D(n1618), .CK(clk), .RN(n3264), .Q(
cont_iter_out[2]), .QN(n1712) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3264), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n3075) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2091), .CK(clk), .RN(
n3265), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1590), .CK(clk), .RN(n3263), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1589), .CK(clk), .RN(n3263), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1588), .CK(clk), .RN(n3263), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1587), .CK(clk), .RN(n3263), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1586), .CK(clk), .RN(n3263), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1585), .CK(clk), .RN(n3263), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3262), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1583), .CK(clk), .RN(n3262), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1582), .CK(clk), .RN(n3262), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1581), .CK(clk), .RN(n3262), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1580), .CK(clk), .RN(n3262), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1579), .CK(clk), .RN(n3262), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1578), .CK(clk), .RN(n3262), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1577), .CK(clk), .RN(n3262), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1576), .CK(clk), .RN(n3262), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1575), .CK(clk), .RN(n3262), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1574), .CK(clk), .RN(n3265), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1573), .CK(clk), .RN(n3264), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n3265), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1571), .CK(clk), .RN(n3264), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1570), .CK(clk), .RN(n1172), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1569), .CK(clk), .RN(n1172), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1568), .CK(clk), .RN(n1172), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1567), .CK(clk), .RN(n1172), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1566), .CK(clk), .RN(n1172), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1565), .CK(clk), .RN(n1172), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1564), .CK(clk), .RN(n3261), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1563), .CK(clk), .RN(n3261), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1562), .CK(clk), .RN(n3261), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1561), .CK(clk), .RN(n3261), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1560), .CK(clk), .RN(n3261), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1559), .CK(clk), .RN(n3261), .Q(d_ff1_Z[31])
);
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n3261), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n1627),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n1714) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n1626),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n3170) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n1624),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n1622),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n1701) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n1608), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n1606), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1602), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n1613), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n1597), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[3]), .QN(n3176) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n1607), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[15]), .QN(n3175) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n1603), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[9]), .QN(n3174) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1429), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1428), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1427), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1426), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1425), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1424), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1338), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1336), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1334), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1332), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1330), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1328), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1326), .CK(clk), .RN(n3257), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1297), .CK(clk), .RN(n3257), .Q(
d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1229), .CK(clk), .RN(n3257),
.Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1294), .CK(clk), .RN(n3256), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1227), .CK(clk), .RN(n3256),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1291), .CK(clk), .RN(n3255), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1225), .CK(clk), .RN(n3255),
.Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1288), .CK(clk), .RN(n3255), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1223), .CK(clk), .RN(n3255),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1285), .CK(clk), .RN(n3254), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1221), .CK(clk), .RN(n3254),
.Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1282), .CK(clk), .RN(n3253), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1219), .CK(clk), .RN(n3253),
.Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1279), .CK(clk), .RN(n3253), .Q(
d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1217), .CK(clk), .RN(n3252),
.Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1276), .CK(clk), .RN(n3252), .Q(
d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1215), .CK(clk), .RN(n3252),
.Q(d_ff2_Z[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n1327), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .QN(n3083) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1487), .CK(clk), .RN(n3251), .Q(
d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1231), .CK(clk), .RN(n3251),
.Q(d_ff2_Z[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1350), .CK(clk), .RN(n3251), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1439), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1508), .CK(clk), .RN(n3250), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1245), .CK(clk), .RN(n3250),
.Q(d_ff2_Z[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1371), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1453), .CK(clk), .RN(n3250), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1499), .CK(clk), .RN(n3250), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1239), .CK(clk), .RN(n3249),
.Q(d_ff2_Z[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n3249), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1447), .CK(clk), .RN(n3249), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1490), .CK(clk), .RN(n3249), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1233), .CK(clk), .RN(n3249),
.Q(d_ff2_Z[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1353), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1441), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1496), .CK(clk), .RN(n3248), .Q(
d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1237), .CK(clk), .RN(n3248),
.Q(d_ff2_Z[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n3248), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1445), .CK(clk), .RN(n3247), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1493), .CK(clk), .RN(n3247), .Q(
d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1235), .CK(clk), .RN(n3247),
.Q(d_ff2_Z[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1356), .CK(clk), .RN(n3247), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1443), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1502), .CK(clk), .RN(n3246), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1241), .CK(clk), .RN(n3246),
.Q(d_ff2_Z[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1365), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1449), .CK(clk), .RN(n3246), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1541), .CK(clk), .RN(n3246), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1267), .CK(clk), .RN(n3245), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1404), .CK(clk), .RN(n3245), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1475), .CK(clk), .RN(n3245), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1535), .CK(clk), .RN(n3245), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n3245), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1398), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1471), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1514), .CK(clk), .RN(n3244), .Q(
d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1249), .CK(clk), .RN(n3244),
.Q(d_ff2_Z[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1377), .CK(clk), .RN(n3244), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n1457), .CK(clk), .RN(n3243), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1505), .CK(clk), .RN(n3243), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1243), .CK(clk), .RN(n3243),
.Q(d_ff2_Z[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1368), .CK(clk), .RN(n3243), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1451), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1529), .CK(clk), .RN(n3242), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1259), .CK(clk), .RN(n3242), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1392), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1467), .CK(clk), .RN(n3242), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1520), .CK(clk), .RN(n3242), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1253), .CK(clk), .RN(n3241),
.Q(d_ff2_Z[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1383), .CK(clk), .RN(n3241), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1461), .CK(clk), .RN(n3241), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1511), .CK(clk), .RN(n3241), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1247), .CK(clk), .RN(n3241),
.Q(d_ff2_Z[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1374), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1455), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1523), .CK(clk), .RN(n3240), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n3240),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1386), .CK(clk), .RN(n3240), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1463), .CK(clk), .RN(n3239), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1517), .CK(clk), .RN(n3239), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1251), .CK(clk), .RN(n3239),
.Q(d_ff2_Z[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1380), .CK(clk), .RN(n3239), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1459), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1419), .CK(clk), .RN(n3238), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1208), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(n1206), .CK(clk), .RN(n3238), .Q(
d_ff_Xn[31]), .QN(n3173) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1421), .CK(clk), .RN(n3238), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1544), .CK(clk), .RN(n3237), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1269), .CK(clk), .RN(n3237), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1407), .CK(clk), .RN(n3237), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1477), .CK(clk), .RN(n3237), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(n3237), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1271), .CK(clk), .RN(n3236), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1410), .CK(clk), .RN(n3236), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(n3236), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1532), .CK(clk), .RN(n3236), .Q(d_ff_Zn[7])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1261), .CK(clk), .RN(n3236), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1395), .CK(clk), .RN(n3235), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1469), .CK(clk), .RN(n3235), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(
n1394), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n1633) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1553), .CK(clk), .RN(n3235), .Q(d_ff_Zn[0])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1275), .CK(clk), .RN(n3235), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1416), .CK(clk), .RN(n3234), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n1483), .CK(clk), .RN(n3234), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n3234), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1273), .CK(clk), .RN(n3234), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1413), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1481), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1526), .CK(clk), .RN(n3233), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1257), .CK(clk), .RN(n3233), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1389), .CK(clk), .RN(n3233), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1465), .CK(clk), .RN(n3232), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1538), .CK(clk), .RN(n3232), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1265), .CK(clk), .RN(n3232), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1401), .CK(clk), .RN(n3232), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1473), .CK(clk), .RN(n3231), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
n1171), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
n1167), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1153),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1152),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1151),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1148),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1147),
.CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1143),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1142),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1138),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1137),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1133),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1132),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1128),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1127),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1123),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1118),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1113),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1102), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1100),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1097),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1094),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1091),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1088),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1085),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1082),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1079),
.CK(clk), .RN(n3201), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1076),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1073),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1070),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1067),
.CK(clk), .RN(n1920), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1064),
.CK(clk), .RN(n3227), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1061),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1058),
.CK(clk), .RN(n3208), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1055),
.CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1052),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1049), .CK(clk), .RN(n3202), .Q(result_add_subt[31]), .QN(n3090) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1048),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1044),
.CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.QN(n3108) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1034),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n3074) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1033),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n3096) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1028), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]),
.QN(n3091) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1024), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]),
.QN(n3106) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
n1023), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1021),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1019),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
n1015), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
n1011), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1005),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1003),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n998), .CK(
clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n996), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n991), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n989), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n984), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n982), .CK(
clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n977), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n975), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n970), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n968), .CK(
clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n964),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n961),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n957),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n955),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n951),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n947),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n943),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n939), .CK(
clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n935),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n931),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n927), .CK(
clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n923), .CK(
clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n919),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n915),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n911),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n907),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n903),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n899),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n895),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n891),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n3172) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n866),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n3164) );
CMPR32X2TS DP_OP_33J13_122_2179_U9 ( .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(n3094), .C(
DP_OP_33J13_122_2179_n18), .CO(DP_OP_33J13_122_2179_n8), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n3253),
.Q(d_ff2_X[28]), .QN(n3142) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1343), .CK(clk), .RN(n3253),
.Q(d_ff2_Y[28]), .QN(n3141) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1592), .CK(clk), .RN(n3263), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n3133) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1158),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]),
.QN(n3129) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
n1043), .CK(clk), .RN(n3213), .Q(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .QN(n3094) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1591), .CK(clk), .RN(n3263), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n3085) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1322),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .QN(n3082) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n3261), .Q(
inst_CORDIC_FSM_v3_state_reg[4]), .QN(n3077) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1593), .CK(clk), .RN(n3263), .Q(
d_ff1_operation_out), .QN(n3070) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1105),
.CK(clk), .RN(n3200), .Q(underflow_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1104),
.CK(clk), .RN(n3212), .Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(n3256), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(n3255), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(n3255), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1179), .CK(clk), .RN(n3254), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1178), .CK(clk), .RN(n3253), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1177), .CK(clk), .RN(n3253), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1176), .CK(clk), .RN(n3252), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1175), .CK(clk), .RN(n3251), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(n3237), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(n3236), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(n3235), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(n3234), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(n3233), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(n3232), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(n3231), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(n3231), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(n3231), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(n3231), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(n3231), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(n3231), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(n3231), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(n3230), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(n3230), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(n3230), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(n3230), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(n3230), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(n3230), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(n3230), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(n3230), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(n3230), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1173), .CK(clk), .RN(n3231), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(n3230), .Q(
data_output[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n1420), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .QN(n3137) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n1218), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n3100) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n877),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n3163) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n876),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3150) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n1337), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .QN(n3069) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n1325), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n3140) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n1324), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n3105) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(
n1388), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n3123) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1916), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n3104) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(
n1415), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .QN(n3120) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n889),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n3157) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n888),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n3156) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n886),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3155) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n884),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3154) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n882),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3153) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n887),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n3145) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n885),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n3144) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n883),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n3143) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n3263), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n3265), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n1370), .CK(clk), .RN(n3188), .QN(n3111) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(
n1406), .CK(clk), .RN(n3193), .QN(n3112) );
CMPR32X2TS DP_OP_33J13_122_2179_U3 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .C(
DP_OP_33J13_122_2179_n3), .CO(DP_OP_33J13_122_2179_n2), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_33J13_122_2179_U5 ( .A(DP_OP_33J13_122_2179_n14), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .C(
DP_OP_33J13_122_2179_n5), .CO(DP_OP_33J13_122_2179_n4), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_33J13_122_2179_U7 ( .A(DP_OP_33J13_122_2179_n16), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .C(
DP_OP_33J13_122_2179_n7), .CO(DP_OP_33J13_122_2179_n6), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_33J13_122_2179_U8 ( .A(DP_OP_33J13_122_2179_n17), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .C(
DP_OP_33J13_122_2179_n8), .CO(DP_OP_33J13_122_2179_n7), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(
n1268), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1000),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n979), .CK(
clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n1616), .CK(clk), .RN(n3261), .Q(
cont_var_out[0]), .QN(n3097) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n1619), .CK(clk), .RN(n3264), .Q(
cont_iter_out[1]), .QN(n3098) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1027), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.QN(n3171) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
n1556), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3067) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
n1555), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n3068) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n1226), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n3134) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n1254), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n3093) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(
n1264), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .QN(n3126) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n1333), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .QN(n3117) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n1335), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .QN(n3118) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n1352), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .QN(n3124) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n1339), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .QN(n3125) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n1379), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .QN(n3119) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(
n1391), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .QN(n3122) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(
n1400), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n3103) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n1355), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .QN(n3110) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n892),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n912),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n900),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n904),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n908),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n932),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n944),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n952),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n916),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n896),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n928),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n940),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n948),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_),
.CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n3266) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1103), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n3182),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n933),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n997),
.CK(clk), .RN(n3206), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1139),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1150),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1066), .CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
n1169), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n956), .CK(clk), .RN(n2084), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1122),
.CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS ITER_CONT_temp_reg_0_ ( .D(n1620), .CK(clk), .RN(n3265), .Q(n1709),
.QN(n3185) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n1228), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n1244), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n1248), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n1232), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n1252), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n1240), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(
n1258), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
n1554), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n1639) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n1234), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(
n1256), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n1220), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(
n1270), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n1615), .CK(clk), .RN(n3261), .Q(
cont_var_out[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(
n1274), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1035),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n1625),
.CK(clk), .RN(n3186), .Q(busy), .QN(n3228) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1314),
.CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1319),
.CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1310),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(
n1260), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .QN(n3095) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1313),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1312),
.CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n1224), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n3086) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1040),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1434), .CK(clk), .RN(n3253),
.Q(d_ff2_X[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(
n1403), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n1640) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n1629), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(
n3132) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1037),
.CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3073) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(
n1397), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n1653) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1039),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n1634) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1315),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .QN(n3127) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1308),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1309),
.CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n1385), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n1654) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1036),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3092) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1342), .CK(clk), .RN(n3252),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n3252),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1438), .CK(clk), .RN(n3256),
.Q(d_ff2_X[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1163), .CK(clk), .RN(n3212), .Q(result_add_subt[26]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1164), .CK(clk), .RN(n3212), .Q(result_add_subt[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n971),
.CK(clk), .RN(n3207), .Q(result_add_subt[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n978),
.CK(clk), .RN(n3207), .Q(result_add_subt[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n985),
.CK(clk), .RN(n3206), .Q(result_add_subt[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n992),
.CK(clk), .RN(n3206), .Q(result_add_subt[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n999),
.CK(clk), .RN(n3205), .Q(result_add_subt[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1006),
.CK(clk), .RN(n3205), .Q(result_add_subt[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1022),
.CK(clk), .RN(n3205), .Q(result_add_subt[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1056), .CK(clk), .RN(n3204), .Q(result_add_subt[12]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1059), .CK(clk), .RN(n3208), .Q(result_add_subt[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1062), .CK(clk), .RN(n3202), .Q(result_add_subt[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1065), .CK(clk), .RN(n3204), .Q(result_add_subt[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1068),
.CK(clk), .RN(n1921), .Q(result_add_subt[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1071), .CK(clk), .RN(n1919), .Q(result_add_subt[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1074), .CK(clk), .RN(n2084), .Q(result_add_subt[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1077),
.CK(clk), .RN(n3208), .Q(result_add_subt[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1080),
.CK(clk), .RN(n3201), .Q(result_add_subt[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1083), .CK(clk), .RN(n3201), .Q(result_add_subt[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1086), .CK(clk), .RN(n3201), .Q(result_add_subt[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1089), .CK(clk), .RN(n3201), .Q(result_add_subt[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1092), .CK(clk), .RN(n3201), .Q(result_add_subt[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1095), .CK(clk), .RN(n3200), .Q(result_add_subt[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1098), .CK(clk), .RN(n3200), .Q(result_add_subt[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1101), .CK(clk), .RN(n3200), .Q(result_add_subt[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1159), .CK(clk), .RN(n3212), .Q(result_add_subt[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(
n1207), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1038),
.CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n3102) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(
n1262), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n3076) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n1329), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .QN(n1656) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1032), .CK(clk), .RN(n3217), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1041),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n1645) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n881),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n1644) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n1367), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n3254),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1347), .CK(clk), .RN(n3256),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1435), .CK(clk), .RN(n3254),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1436), .CK(clk), .RN(n3255),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1437), .CK(clk), .RN(n3256),
.Q(d_ff2_X[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1303),
.CK(clk), .RN(n3188), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1214), .CK(clk), .RN(n3238),
.Q(d_ff2_Z[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n879),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n3152) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1341), .CK(clk), .RN(n3252),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n3251),
.Q(d_ff2_X[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1157),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]),
.QN(n3084) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1280), .CK(clk), .RN(n3253), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n1418), .CK(clk), .RN(n3238), .Q(
d_ff_Yn[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1402), .CK(clk), .RN(n3232), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n3234), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1408), .CK(clk), .RN(n3237), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1381), .CK(clk), .RN(n3239),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1387), .CK(clk), .RN(n3240),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1375), .CK(clk), .RN(n3240),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1369), .CK(clk), .RN(n3243),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1405), .CK(clk), .RN(n3245), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n3248),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1363), .CK(clk), .RN(n3249),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1351), .CK(clk), .RN(n3251),
.Q(d_ff2_Y[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n1284), .CK(clk), .RN(n3254), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n1296), .CK(clk), .RN(n3257), .Q(
d_ff_Yn[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1474), .CK(clk), .RN(n3231), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1482), .CK(clk), .RN(n3233), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1470), .CK(clk), .RN(n3235), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1480), .CK(clk), .RN(n3236), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(n3237), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1460), .CK(clk), .RN(n3239),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1464), .CK(clk), .RN(n3239),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1456), .CK(clk), .RN(n3240),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1452), .CK(clk), .RN(n3243),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1458), .CK(clk), .RN(n3243),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1472), .CK(clk), .RN(n3244), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1450), .CK(clk), .RN(n3246),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1444), .CK(clk), .RN(n3247),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1446), .CK(clk), .RN(n3247),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1466), .CK(clk), .RN(n3232), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1484), .CK(clk), .RN(n3234), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1462), .CK(clk), .RN(n3241),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1468), .CK(clk), .RN(n3242), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(n3245), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1442), .CK(clk), .RN(n3248),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1448), .CK(clk), .RN(n3249),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1454), .CK(clk), .RN(n3250),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1440), .CK(clk), .RN(n3251),
.Q(d_ff2_X[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n1281), .CK(clk), .RN(n3253), .Q(
d_ff_Yn[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1160), .CK(clk), .RN(n3212), .Q(result_add_subt[29]), .QN(n3169) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1165), .CK(clk), .RN(n3212), .Q(result_add_subt[24]), .QN(n3166) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n993), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1016),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n920), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n924), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n965), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n986), .CK(
clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n972), .CK(
clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1320),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1321),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(
n1412), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n3121) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n1358), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .QN(n3116) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n1373), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .QN(n3078) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1299),
.CK(clk), .RN(n3188), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(n3258), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n1598), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[4]) );
DFFRX1TS reg_LUT_Q_reg_12_ ( .D(n1605), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[12]) );
DFFRX1TS reg_LUT_Q_reg_21_ ( .D(n1609), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[21]) );
DFFRX1TS reg_LUT_Q_reg_24_ ( .D(n1611), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n1610), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n1596), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n1600), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n1612), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1298),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n1604), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n3259), .Q(
d_ff3_LUT_out[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n1238), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(
n1272), .CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n1250), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n1236), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n1230), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n1246), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n1216), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n1242), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n3099) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(
n1266), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .QN(n3071) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1311),
.CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n1222), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n3087) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n3254),
.Q(d_ff2_Y[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1307),
.CK(clk), .RN(n3192), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1306),
.CK(clk), .RN(n3195), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(
n1409), .CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .QN(n1655) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1348), .CK(clk), .RN(n3256),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1346), .CK(clk), .RN(n3255),
.Q(d_ff2_Y[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1302),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1318),
.CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .QN(n3128) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1316),
.CK(clk), .RN(n3195), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .QN(n3131) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1304),
.CK(clk), .RN(n3190), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n1349), .CK(clk), .RN(n3188), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .QN(n3080) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n1361), .CK(clk), .RN(n3189), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .QN(n3079) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n1364), .CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .QN(n3115) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1323),
.CK(clk), .RN(n3194), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .QN(n3081) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1317),
.CK(clk), .RN(n3190), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .QN(n3130) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1110),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1156),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]),
.QN(n1706) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1154),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n871),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n3160) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n869),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n3159) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n875),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n3162) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n873),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n3161) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(n3233), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1536), .CK(clk), .RN(n3232), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1545), .CK(clk), .RN(n3236), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1530), .CK(clk), .RN(n3235), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1515), .CK(clk), .RN(n3239), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1542), .CK(clk), .RN(n3237), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1509), .CK(clk), .RN(n3240), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1521), .CK(clk), .RN(n3239), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1512), .CK(clk), .RN(n3243), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1503), .CK(clk), .RN(n3243), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1500), .CK(clk), .RN(n3246), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1533), .CK(clk), .RN(n3244), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1494), .CK(clk), .RN(n3247), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1491), .CK(clk), .RN(n3247), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1286), .CK(clk), .RN(n3254), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1277), .CK(clk), .RN(n3252), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1292), .CK(clk), .RN(n3256), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1289), .CK(clk), .RN(n3255), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n3234), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1524), .CK(clk), .RN(n3232), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1527), .CK(clk), .RN(n3242), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1518), .CK(clk), .RN(n3241), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1488), .CK(clk), .RN(n3248), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1539), .CK(clk), .RN(n3245), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1506), .CK(clk), .RN(n3250), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1497), .CK(clk), .RN(n3249), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1210), .CK(clk), .RN(n3251), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1485), .CK(clk), .RN(n3251), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1283), .CK(clk), .RN(n3254), .Q(
d_ff_Xn[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n867),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n3158) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n1537), .CK(clk), .RN(n3232), .Q(d_ff_Yn[5])
);
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n1549), .CK(clk), .RN(n3234), .Q(d_ff_Yn[1])
);
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n1525), .CK(clk), .RN(n3233), .Q(d_ff_Yn[9])
);
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n1531), .CK(clk), .RN(n3235), .Q(d_ff_Yn[7])
);
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n1552), .CK(clk), .RN(n3235), .Q(d_ff_Yn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n1543), .CK(clk), .RN(n3237), .Q(d_ff_Yn[3])
);
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n1546), .CK(clk), .RN(n3236), .Q(d_ff_Yn[2])
);
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n1522), .CK(clk), .RN(n3240), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n1516), .CK(clk), .RN(n3239), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n1519), .CK(clk), .RN(n3241), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n1510), .CK(clk), .RN(n3241), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n1504), .CK(clk), .RN(n3243), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n1528), .CK(clk), .RN(n3242), .Q(d_ff_Yn[8])
);
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n1534), .CK(clk), .RN(n3245), .Q(d_ff_Yn[6])
);
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n1513), .CK(clk), .RN(n3244), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n1501), .CK(clk), .RN(n3246), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n1540), .CK(clk), .RN(n3245), .Q(d_ff_Yn[4])
);
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n1293), .CK(clk), .RN(n3256), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n1290), .CK(clk), .RN(n3255), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n1287), .CK(clk), .RN(n3254), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n1278), .CK(clk), .RN(n3252), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n1211), .CK(clk), .RN(n3252), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n1486), .CK(clk), .RN(n3251), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n1507), .CK(clk), .RN(n3250), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n1498), .CK(clk), .RN(n3249), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n1489), .CK(clk), .RN(n3249), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n1495), .CK(clk), .RN(n3248), .Q(
d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n1492), .CK(clk), .RN(n3247), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1295), .CK(clk), .RN(n3256), .Q(
d_ff_Xn[23]) );
DFFRX4TS ITER_CONT_temp_reg_3_ ( .D(n1617), .CK(clk), .RN(n1917), .Q(
cont_iter_out[3]), .QN(n3072) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1166), .CK(clk), .RN(n3213), .Q(result_add_subt[23]), .QN(n3165) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1162), .CK(clk), .RN(n3212), .Q(result_add_subt[27]), .QN(n3167) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1161), .CK(clk), .RN(n3212), .Q(result_add_subt[28]), .QN(n3168) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n936), .CK(
clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1109),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]),
.QN(n1657) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1107),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]),
.QN(n1658) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(
n1558), .CK(clk), .RN(n3193), .Q(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .QN(n1649) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1212),
.CK(clk), .RN(n3193), .Q(inst_FPU_PIPELINED_FPADDSUB_intAS) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n1376), .CK(clk), .RN(n3191), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .QN(n3114) );
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n1430), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n1595), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1300),
.CK(clk), .RN(n3189), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1301),
.CK(clk), .RN(n3189), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n890),
.CK(clk), .RN(n3219), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n3089) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1106),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1108),
.CK(clk), .RN(n3200), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]),
.QN(n3136) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n1340), .CK(clk), .RN(n3258), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n1382), .CK(clk), .RN(n3192), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .QN(n3113) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n1628), .CK(clk), .RN(n3186), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(
n1643) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1305),
.CK(clk), .RN(n3191), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n1331), .CK(clk), .RN(n3187), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n878),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3151) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n874),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3149) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n872),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3148) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n870),
.CK(clk), .RN(n3221), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3147) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n868),
.CK(clk), .RN(n3222), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3146) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1372), .CK(clk), .RN(n3250),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1354), .CK(clk), .RN(n3248),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n3247),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1366), .CK(clk), .RN(n3246),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1399), .CK(clk), .RN(n3244), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1378), .CK(clk), .RN(n3244),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1393), .CK(clk), .RN(n3242), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1384), .CK(clk), .RN(n3241),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1209), .CK(clk), .RN(n3238),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n3236), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1396), .CK(clk), .RN(n3235), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1417), .CK(clk), .RN(n3234), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1390), .CK(clk), .RN(n3233), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n1213), .CK(clk), .RN(n3238), .Q(
d_ff3_sign_out) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n880),
.CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n1707) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1422), .CK(clk), .RN(n3238),
.Q(d_ff2_X[31]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n3265), .Q(
inst_CORDIC_FSM_v3_state_reg[0]), .QN(n3101) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1025), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1014), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1013), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1012), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]),
.QN(n3109) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1010), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1009), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1008), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1029), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.QN(n3139) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1030), .CK(clk), .RN(n3217), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.QN(n3138) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1031), .CK(clk), .RN(n3218), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.QN(n3088) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n3186), .QN(n3267) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1111), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1116), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1136), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1141), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1146), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1042),
.CK(clk), .RN(n3217), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n3229) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1121), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1131), .CK(clk), .RN(n3214), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n901),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n905),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n913),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n909),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n917),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n945),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n929),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n941),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n949),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n937),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1149),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n3178),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n3179),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n3177),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n995),
.CK(clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1018),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1002),
.CK(clk), .RN(n3205), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n981),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n988),
.CK(clk), .RN(n3206), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1020), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n983),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n990),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1004), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1053),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n962),
.CK(clk), .RN(n1920), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1114),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1119),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1124),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1129),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1134),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1046),
.CK(clk), .RN(n1921), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n953),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n973),
.CK(clk), .RN(n3224), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1144),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n893),
.CK(clk), .RN(n3226), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n897),
.CK(clk), .RN(n3225), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n3184),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n3183),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n3180),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n3181),
.CK(clk), .RN(n3222), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n894),
.CK(clk), .RN(n3212), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n898),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1051),
.CK(clk), .RN(n1919), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n958),
.CK(clk), .RN(n3202), .Q(zero_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
n1050), .CK(clk), .RN(n3212), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n959), .CK(clk), .RN(n3204), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
n1168), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1047),
.CK(clk), .RN(n2084), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1054),
.CK(clk), .RN(n3202), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
n1099), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
n1090), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
n1084), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
n1087), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
n1093), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
n1081), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
n1069), .CK(clk), .RN(n1921), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
n1096), .CK(clk), .RN(n3216), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
n1060), .CK(clk), .RN(n3204), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
n1072), .CK(clk), .RN(n1919), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
n1063), .CK(clk), .RN(n3208), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
n1057), .CK(clk), .RN(n3203), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1075), .CK(clk), .RN(n3216), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1078), .CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1115),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1120),
.CK(clk), .RN(n3199), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1125),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1130),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1135),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1145),
.CK(clk), .RN(n3197), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1140),
.CK(clk), .RN(n3198), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n963),
.CK(clk), .RN(n3208), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n934),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n946),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n930),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n954),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n942),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n950),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n974),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n938),
.CK(clk), .RN(n3209), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n926),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n967),
.CK(clk), .RN(n3207), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n922),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n976),
.CK(clk), .RN(n3207), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n969),
.CK(clk), .RN(n3215), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n906),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n914),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n910),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n902),
.CK(clk), .RN(n3211), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n918),
.CK(clk), .RN(n3210), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1045),
.CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
n1170), .CK(clk), .RN(n3196), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n1614), .CK(clk), .RN(n3260), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n960),
.CK(clk), .RN(n3203), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1112),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1117),
.CK(clk), .RN(n3215), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1155),
.CK(clk), .RN(n3196), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]),
.QN(n3135) );
ADDFHX2TS DP_OP_33J13_122_2179_U4 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .CI(
DP_OP_33J13_122_2179_n4), .CO(DP_OP_33J13_122_2179_n3), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1026), .CK(clk), .RN(n3219), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.QN(n3107) );
ADDFHX2TS DP_OP_33J13_122_2179_U6 ( .A(DP_OP_33J13_122_2179_n15), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .CI(
DP_OP_33J13_122_2179_n6), .CO(DP_OP_33J13_122_2179_n5), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1007), .CK(clk), .RN(n3213), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0])
);
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(
n1557), .CK(clk), .RN(n3220), .Q(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .QN(n1637) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n1623),
.CK(clk), .RN(n3227), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n1713) );
CMPR32X2TS DP_OP_33J13_122_2179_U2 ( .A(n3094), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .C(
DP_OP_33J13_122_2179_n2), .CO(DP_OP_33J13_122_2179_n1), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n1621),
.CK(clk), .RN(n3226), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n1638) );
CMPR32X2TS intadd_42_U4 ( .A(d_ff2_Y[24]), .B(n3098), .C(intadd_42_CI), .CO(
intadd_42_n3), .S(intadd_42_SUM_0_) );
CMPR32X2TS intadd_43_U4 ( .A(d_ff2_X[24]), .B(n3098), .C(intadd_43_CI), .CO(
intadd_43_n3), .S(intadd_43_SUM_0_) );
CMPR32X2TS intadd_43_U3 ( .A(d_ff2_X[25]), .B(intadd_42_B_1_), .C(
intadd_43_n3), .CO(intadd_43_n2), .S(intadd_43_SUM_1_) );
CMPR32X2TS intadd_42_U3 ( .A(d_ff2_Y[25]), .B(intadd_42_B_1_), .C(
intadd_42_n3), .CO(intadd_42_n2), .S(intadd_42_SUM_1_) );
CMPR32X2TS intadd_43_U2 ( .A(d_ff2_X[26]), .B(n3072), .C(intadd_43_n2), .CO(
intadd_43_n1), .S(intadd_43_SUM_2_) );
CMPR32X2TS intadd_42_U2 ( .A(d_ff2_Y[26]), .B(n3072), .C(intadd_42_n2), .CO(
intadd_42_n1), .S(intadd_42_SUM_2_) );
AOI32X1TS U1643 ( .A0(n3072), .A1(n2842), .A2(n2835), .B0(d_ff3_LUT_out[26]),
.B1(n2834), .Y(n2837) );
AOI222X1TS U1644 ( .A0(n2123), .A1(d_ff2_Z[1]), .B0(n2108), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2987), .Y(n2109) );
AOI222X1TS U1645 ( .A0(n2123), .A1(d_ff2_Z[3]), .B0(n2108), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2987), .Y(n2110) );
AOI222X1TS U1646 ( .A0(n2986), .A1(d_ff2_Z[2]), .B0(n2108), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2122), .Y(n2119) );
AOI222X1TS U1647 ( .A0(n2986), .A1(d_ff2_Z[12]), .B0(n2114), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2122), .Y(n2115) );
AOI222X1TS U1648 ( .A0(n2921), .A1(d_ff2_Z[10]), .B0(n2108), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2122), .Y(n2124) );
AOI222X1TS U1649 ( .A0(n2897), .A1(d_ff2_Z[11]), .B0(n2108), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2104), .Y(n2105) );
AOI222X1TS U1650 ( .A0(n2914), .A1(d_ff2_Z[8]), .B0(n2102), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2122), .Y(n2117) );
AOI222X1TS U1651 ( .A0(n2871), .A1(d_ff2_Z[6]), .B0(n2102), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2122), .Y(n2111) );
AOI222X1TS U1652 ( .A0(n2123), .A1(d_ff2_Z[4]), .B0(n2108), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2122), .Y(n2118) );
AOI222X1TS U1653 ( .A0(n2112), .A1(d_ff2_Z[13]), .B0(n2114), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2122), .Y(n2113) );
AOI222X1TS U1654 ( .A0(n2112), .A1(d_ff2_Z[22]), .B0(n2134), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2104), .Y(n2103) );
AOI222X1TS U1655 ( .A0(n2112), .A1(d_ff2_Z[21]), .B0(n2114), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2104), .Y(n2101) );
AOI222X1TS U1656 ( .A0(n2112), .A1(d_ff2_Z[20]), .B0(n2114), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2104), .Y(n2100) );
AOI222X1TS U1657 ( .A0(n2112), .A1(d_ff2_Z[16]), .B0(n2114), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2104), .Y(n2099) );
AOI222X1TS U1658 ( .A0(n2112), .A1(d_ff2_Z[14]), .B0(n2114), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2104), .Y(n2098) );
AOI222X1TS U1659 ( .A0(n2112), .A1(d_ff2_Z[18]), .B0(n2114), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2104), .Y(n2097) );
AOI222X1TS U1660 ( .A0(n2112), .A1(d_ff2_Z[15]), .B0(n2114), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2104), .Y(n2096) );
AOI222X1TS U1661 ( .A0(n2112), .A1(d_ff2_Z[17]), .B0(n2114), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2104), .Y(n2095) );
AOI222X1TS U1662 ( .A0(n2986), .A1(d_ff2_Z[19]), .B0(n2114), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2104), .Y(n2094) );
AOI222X1TS U1663 ( .A0(n2135), .A1(d_ff2_Z[26]), .B0(n2134), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2133), .Y(n2136) );
AOI222X1TS U1664 ( .A0(n2135), .A1(d_ff2_Z[25]), .B0(n2134), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2133), .Y(n2127) );
AOI222X1TS U1665 ( .A0(n2135), .A1(d_ff2_Z[24]), .B0(n2134), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2133), .Y(n2130) );
AOI222X1TS U1666 ( .A0(n2135), .A1(d_ff2_Z[23]), .B0(n2134), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2133), .Y(n2132) );
AOI222X1TS U1667 ( .A0(n2135), .A1(d_ff2_Z[28]), .B0(n2134), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2133), .Y(n2129) );
AOI222X1TS U1668 ( .A0(n2921), .A1(d_ff2_Z[0]), .B0(n2133), .B1(d_ff_Zn[0]),
.C0(n2108), .C1(d_ff1_Z[0]), .Y(n2107) );
BUFX3TS U1669 ( .A(n1825), .Y(n2505) );
INVX2TS U1670 ( .A(n1642), .Y(n1690) );
INVX2TS U1671 ( .A(n1641), .Y(n1695) );
CLKBUFX2TS U1672 ( .A(n1823), .Y(n2475) );
AND2X2TS U1673 ( .A(n3012), .B(n1824), .Y(n1825) );
NAND2BX2TS U1674 ( .AN(n2264), .B(n2261), .Y(n3015) );
INVX2TS U1675 ( .A(n1687), .Y(n1688) );
AOI32X1TS U1676 ( .A0(n1822), .A1(n1821), .A2(n1820), .B0(n1819), .B1(n1822),
.Y(n1824) );
CLKBUFX2TS U1677 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n1674) );
INVX2TS U1678 ( .A(n3012), .Y(n2306) );
INVX4TS U1679 ( .A(n2875), .Y(n1687) );
INVX4TS U1680 ( .A(n2031), .Y(n2975) );
BUFX3TS U1681 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .Y(
n3012) );
BUFX3TS U1682 ( .A(n2093), .Y(n2875) );
NAND4BX1TS U1683 ( .AN(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]),
.B(n2257), .C(n2301), .D(n2297), .Y(n2258) );
NAND2X2TS U1684 ( .A(n2092), .B(n2874), .Y(n2093) );
NAND4X1TS U1685 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1895), .C(n3077),
.D(n3101), .Y(n2814) );
NOR2X1TS U1686 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2152) );
INVX2TS U1687 ( .A(n3054), .Y(n2330) );
BUFX3TS U1688 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n3054) );
OAI21XLTS U1689 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n3121),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n1772) );
OAI21XLTS U1690 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n3111), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n1792) );
NOR2XLTS U1691 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2257) );
NOR2X1TS U1692 ( .A(n1644), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1842) );
NOR2X6TS U1693 ( .A(n1735), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n1725) );
CLKINVX3TS U1694 ( .A(n2377), .Y(n2361) );
OAI21X1TS U1695 ( .A0(n2773), .A1(n1828), .B0(n1827), .Y(n1923) );
NAND2X1TS U1696 ( .A(n2329), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n2333) );
OR3X1TS U1697 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .C(n3068), .Y(
n1636) );
NOR2XLTS U1698 ( .A(n1697), .B(n2570), .Y(n2557) );
INVX2TS U1699 ( .A(n1641), .Y(n1694) );
CLKINVX3TS U1700 ( .A(n2205), .Y(n2291) );
BUFX3TS U1701 ( .A(n2091), .Y(n2874) );
NOR2X1TS U1702 ( .A(n3015), .B(n3055), .Y(n3014) );
INVX1TS U1703 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(
n2522) );
OAI211XLTS U1704 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3168), .B0(n2303), .C0(n2295), .Y(n1161) );
OAI211XLTS U1705 ( .A0(n2391), .A1(n1671), .B0(n2390), .C0(n2389), .Y(n1317)
);
OAI211XLTS U1706 ( .A0(n2429), .A1(n1670), .B0(n2425), .C0(n2424), .Y(n1311)
);
OAI211XLTS U1707 ( .A0(n2345), .A1(n1642), .B0(n2322), .C0(n2321), .Y(n1298)
);
OAI211XLTS U1708 ( .A0(n2403), .A1(n1667), .B0(n2402), .C0(n2401), .Y(n1320)
);
OAI211XLTS U1709 ( .A0(n2983), .A1(n2494), .B0(n2240), .C0(n2247), .Y(n1367)
);
OAI211XLTS U1710 ( .A0(n2297), .A1(n3055), .B0(n2303), .C0(n2296), .Y(n1164)
);
OAI211XLTS U1711 ( .A0(n2442), .A1(n1666), .B0(n2441), .C0(n2440), .Y(n1312)
);
OAI21XLTS U1712 ( .A0(n2181), .A1(n2377), .B0(n2180), .Y(n1554) );
OAI211XLTS U1713 ( .A0(n2983), .A1(n3112), .B0(n2248), .C0(n2247), .Y(n1406)
);
OAI21XLTS U1714 ( .A0(n2181), .A1(n2824), .B0(n2179), .Y(n1023) );
INVX2TS U1715 ( .A(n3049), .Y(n1692) );
OAI211X1TS U1716 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3167), .B0(n2303), .C0(n2294), .Y(n1162) );
OAI211X1TS U1717 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1(n3166), .B0(n2303), .C0(n2299), .Y(n1165) );
AO22X1TS U1718 ( .A0(n3016), .A1(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(
result_add_subt[30]), .B1(n3055), .Y(n1159) );
INVX4TS U1719 ( .A(n2505), .Y(n3011) );
OAI21X1TS U1720 ( .A0(n2468), .A1(n3039), .B0(n2465), .Y(n2466) );
OAI2BB1X2TS U1721 ( .A0N(n1711), .A1N(n2264), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n2265) );
INVX4TS U1722 ( .A(n1823), .Y(n3013) );
NAND3X1TS U1723 ( .A(n1725), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n3096), .Y(n1726)
);
AO22X1TS U1724 ( .A0(n2989), .A1(n2883), .B0(n2988), .B1(d_ff3_sh_x_out[30]),
.Y(n1423) );
OAI21X1TS U1725 ( .A0(n2204), .A1(n2205), .B0(n2203), .Y(n1173) );
AO22X1TS U1726 ( .A0(n2980), .A1(n2942), .B0(n2979), .B1(d_ff3_sh_y_out[30]),
.Y(n1326) );
NOR2X1TS U1727 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
n1735), .Y(n1739) );
INVX4TS U1728 ( .A(n2205), .Y(n2287) );
OAI21X1TS U1729 ( .A0(n2830), .A1(n2190), .B0(n2189), .Y(n1598) );
INVX4TS U1730 ( .A(n2253), .Y(n2079) );
INVX4TS U1731 ( .A(n2253), .Y(n2965) );
BUFX3TS U1732 ( .A(n2033), .Y(n2062) );
OAI211X1TS U1733 ( .A0(n2194), .A1(n2190), .B0(n2163), .C0(n2162), .Y(n1604)
);
OAI211X1TS U1734 ( .A0(n2194), .A1(n1635), .B0(n2193), .C0(n2192), .Y(n1599)
);
OAI211X1TS U1735 ( .A0(n2842), .A1(n3174), .B0(n2193), .C0(n2191), .Y(n1603)
);
OAI211X1TS U1736 ( .A0(n2842), .A1(n3175), .B0(n2187), .C0(n2843), .Y(n1607)
);
OAI211X1TS U1737 ( .A0(n2842), .A1(n3176), .B0(n2187), .C0(n2191), .Y(n1597)
);
INVX4TS U1738 ( .A(n2406), .Y(n2423) );
INVX4TS U1739 ( .A(n3037), .Y(n2558) );
INVX4TS U1740 ( .A(n2874), .Y(n2135) );
NAND3X1TS U1741 ( .A(n2813), .B(n2826), .C(n3267), .Y(n2833) );
INVX4TS U1742 ( .A(n2947), .Y(n2349) );
OR2X2TS U1743 ( .A(cont_iter_out[1]), .B(n2840), .Y(n1635) );
OAI211X1TS U1744 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n3122), .B0(n1785), .C0(n1788), .Y(n1767) );
NAND2BX1TS U1745 ( .AN(d_ff3_LUT_out[27]), .B(n2866), .Y(n1614) );
NOR2X1TS U1746 ( .A(n1717), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n1721) );
NOR2X1TS U1747 ( .A(n1783), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]),
.Y(n1784) );
NOR2X1TS U1748 ( .A(n1817), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]),
.Y(n1754) );
INVX4TS U1749 ( .A(n2830), .Y(intadd_42_B_1_) );
INVX4TS U1750 ( .A(n2196), .Y(n2827) );
INVX4TS U1751 ( .A(n1712), .Y(n2830) );
OAI211X1TS U1752 ( .A0(n2435), .A1(n1667), .B0(n2408), .C0(n2407), .Y(n1308)
);
OAI211X1TS U1753 ( .A0(n2396), .A1(n1671), .B0(n2395), .C0(n2394), .Y(n1303)
);
OAI21X1TS U1754 ( .A0(n2305), .A1(n1671), .B0(n2304), .Y(n1322) );
OAI211X1TS U1755 ( .A0(n2380), .A1(n1671), .B0(n2379), .C0(n2378), .Y(n1305)
);
OAI211X1TS U1756 ( .A0(n2386), .A1(n1670), .B0(n2385), .C0(n2384), .Y(n1301)
);
OAI211X1TS U1757 ( .A0(n2356), .A1(n1671), .B0(n2351), .C0(n2350), .Y(n1315)
);
OAI211X1TS U1758 ( .A0(n2345), .A1(n1671), .B0(n2341), .C0(n2340), .Y(n1300)
);
OAI211X1TS U1759 ( .A0(n2356), .A1(n1667), .B0(n2355), .C0(n2354), .Y(n1314)
);
OAI211X1TS U1760 ( .A0(n2374), .A1(n1671), .B0(n2373), .C0(n2372), .Y(n1319)
);
OAI211X1TS U1761 ( .A0(n2345), .A1(n1667), .B0(n2344), .C0(n2343), .Y(n1299)
);
OAI211X1TS U1762 ( .A0(n2416), .A1(n1671), .B0(n2410), .C0(n2409), .Y(n1307)
);
OAI211X1TS U1763 ( .A0(n2435), .A1(n1671), .B0(n2433), .C0(n2432), .Y(n1309)
);
OAI211X1TS U1764 ( .A0(n2380), .A1(n1667), .B0(n2365), .C0(n2364), .Y(n1304)
);
OAI211X1TS U1765 ( .A0(n2391), .A1(n1667), .B0(n2335), .C0(n2334), .Y(n1316)
);
OAI211X1TS U1766 ( .A0(n2416), .A1(n1666), .B0(n2415), .C0(n2414), .Y(n1306)
);
OAI211X1TS U1767 ( .A0(n2374), .A1(n1667), .B0(n2368), .C0(n2367), .Y(n1318)
);
OAI211X1TS U1768 ( .A0(n2396), .A1(n1667), .B0(n2370), .C0(n2369), .Y(n1302)
);
INVX4TS U1769 ( .A(n1672), .Y(n1665) );
INVX2TS U1770 ( .A(n2327), .Y(n2434) );
INVX2TS U1771 ( .A(n1751), .Y(n1672) );
OAI21X1TS U1772 ( .A0(n2330), .A1(n2146), .B0(n2145), .Y(n1011) );
OAI211X2TS U1773 ( .A0(n1743), .A1(n1742), .B0(n1741), .C0(n2149), .Y(n2517)
);
OAI21X1TS U1774 ( .A0(n2146), .A1(n2377), .B0(n2144), .Y(n1556) );
OAI21X1TS U1775 ( .A0(n2160), .A1(n2377), .B0(n2159), .Y(n1555) );
OAI21X1TS U1776 ( .A0(n2160), .A1(n2824), .B0(n2158), .Y(n1015) );
OAI211X1TS U1777 ( .A0(n1684), .A1(n3169), .B0(n2303), .C0(n2302), .Y(n1160)
);
OAI211X1TS U1778 ( .A0(n2301), .A1(n3055), .B0(n2303), .C0(n2300), .Y(n1163)
);
OAI211X1TS U1779 ( .A0(n1684), .A1(n3165), .B0(n2303), .C0(n2298), .Y(n1166)
);
OAI21X1TS U1780 ( .A0(n3080), .A1(n2465), .B0(n2460), .Y(n1100) );
OAI21X1TS U1781 ( .A0(n3124), .A1(n2463), .B0(n2452), .Y(n1091) );
NAND2X6TS U1782 ( .A(n3016), .B(n3015), .Y(n3049) );
OAI21X1TS U1783 ( .A0(n2511), .A1(n3011), .B0(n2510), .Y(n1106) );
OAI21X1TS U1784 ( .A0(n2266), .A1(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n3016), .Y(n2267)
);
OAI211X1TS U1785 ( .A0(n2253), .A1(n2451), .B0(n2230), .C0(n2231), .Y(n1358)
);
OAI211X1TS U1786 ( .A0(n2253), .A1(n2511), .B0(n2242), .C0(n2241), .Y(n1331)
);
OAI211X1TS U1787 ( .A0(n2253), .A1(n2225), .B0(n2224), .C0(n2238), .Y(n1361)
);
OAI211X1TS U1788 ( .A0(n2253), .A1(n2233), .B0(n2232), .C0(n2231), .Y(n1349)
);
OAI21X1TS U1789 ( .A0(n3079), .A1(n2501), .B0(n2470), .Y(n903) );
OAI21X1TS U1790 ( .A0(n3124), .A1(n3013), .B0(n2472), .Y(n907) );
OAI21X1TS U1791 ( .A0(n3116), .A1(n2499), .B0(n2487), .Y(n911) );
OAI21X1TS U1792 ( .A0(n2494), .A1(n2499), .B0(n2493), .Y(n935) );
OAI21X1TS U1793 ( .A0(n3122), .A1(n2499), .B0(n2498), .Y(n939) );
OAI21X1TS U1794 ( .A0(n3113), .A1(n2501), .B0(n2471), .Y(n943) );
OAI211X1TS U1795 ( .A0(n2253), .A1(n1656), .B0(n2234), .C0(n2241), .Y(n1329)
);
OAI21X1TS U1796 ( .A0(n2253), .A1(n3140), .B0(n2210), .Y(n1325) );
OAI21X1TS U1797 ( .A0(n3126), .A1(n3011), .B0(n2506), .Y(n968) );
OAI21X1TS U1798 ( .A0(n2511), .A1(n2501), .B0(n2500), .Y(n1154) );
OAI21X1TS U1799 ( .A0(n3103), .A1(n3011), .B0(n2508), .Y(n970) );
OAI21X1TS U1800 ( .A0(n3110), .A1(n2499), .B0(n2477), .Y(n915) );
OAI211X1TS U1801 ( .A0(n2983), .A1(n3111), .B0(n2246), .C0(n2251), .Y(n1370)
);
OAI211X1TS U1802 ( .A0(n2983), .A1(n1699), .B0(n2236), .C0(n2235), .Y(n1394)
);
OAI21X1TS U1803 ( .A0(n3123), .A1(n3011), .B0(n2509), .Y(n977) );
OAI21X1TS U1804 ( .A0(n2489), .A1(n2463), .B0(n2459), .Y(n1073) );
OAI21X1TS U1805 ( .A0(n1656), .A1(n3013), .B0(n2464), .Y(n1153) );
OAI211X1TS U1806 ( .A0(n2253), .A1(n3110), .B0(n2252), .C0(n2251), .Y(n1355)
);
OAI21X1TS U1807 ( .A0(n1655), .A1(n2504), .B0(n2483), .Y(n1003) );
NAND2X6TS U1808 ( .A(n2173), .B(n3092), .Y(n2140) );
OAI211X1TS U1809 ( .A0(n2983), .A1(n3103), .B0(n2245), .C0(n2244), .Y(n1400)
);
OAI21X1TS U1810 ( .A0(n2482), .A1(n2504), .B0(n2481), .Y(n982) );
OAI211X1TS U1811 ( .A0(n2253), .A1(n2229), .B0(n2228), .C0(n2241), .Y(n1327)
);
OAI21X1TS U1812 ( .A0(n1653), .A1(n2463), .B0(n2444), .Y(n1076) );
OAI21X1TS U1813 ( .A0(n1640), .A1(n2463), .B0(n2446), .Y(n1079) );
OAI21X1TS U1814 ( .A0(n3140), .A1(n2499), .B0(n2478), .Y(n1151) );
OAI21X1TS U1815 ( .A0(n2494), .A1(n2463), .B0(n2454), .Y(n1070) );
OAI21X1TS U1816 ( .A0(n3113), .A1(n2457), .B0(n1892), .Y(n1064) );
OAI21X1TS U1817 ( .A0(n3120), .A1(n2504), .B0(n2480), .Y(n989) );
OAI21X1TS U1818 ( .A0(n1699), .A1(n2504), .B0(n2492), .Y(n996) );
OAI21X1TS U1819 ( .A0(n3112), .A1(n2504), .B0(n2503), .Y(n1019) );
AO22XLTS U1820 ( .A0(n2987), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n2986),
.Y(n1347) );
AO22XLTS U1821 ( .A0(n2987), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n2986),
.Y(n1341) );
OAI21X1TS U1822 ( .A0(n1699), .A1(n2457), .B0(n2310), .Y(n998) );
AOI222X1TS U1823 ( .A0(n2135), .A1(d_ff2_Z[31]), .B0(n2134), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2133), .Y(n2128) );
OAI21X1TS U1824 ( .A0(n1655), .A1(n2457), .B0(n2309), .Y(n1005) );
OAI21X1TS U1825 ( .A0(n3120), .A1(n2457), .B0(n2307), .Y(n991) );
OAI21X1TS U1826 ( .A0(n2482), .A1(n2457), .B0(n2308), .Y(n984) );
AO22XLTS U1827 ( .A0(n2922), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n2986),
.Y(n1448) );
AO22XLTS U1828 ( .A0(n2913), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n2986),
.Y(n1393) );
INVX2TS U1829 ( .A(n1825), .Y(n2457) );
INVX2TS U1830 ( .A(n1825), .Y(n2463) );
AO22XLTS U1831 ( .A0(n2906), .A1(d_ff_Xn[30]), .B0(d_ff2_X[30]), .B1(n2986),
.Y(n1431) );
NOR2X1TS U1832 ( .A(n2258), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n2259) );
BUFX3TS U1833 ( .A(n2062), .Y(n2209) );
INVX4TS U1834 ( .A(n1688), .Y(n2906) );
AO22XLTS U1835 ( .A0(n1687), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n2986),
.Y(n1411) );
AO22XLTS U1836 ( .A0(n1687), .A1(d_ff_Xn[31]), .B0(d_ff2_X[31]), .B1(n2986),
.Y(n1422) );
NOR2X1TS U1837 ( .A(n1696), .B(n2570), .Y(n2564) );
OAI21X1TS U1838 ( .A0(n1799), .A1(n1798), .B0(n1797), .Y(n1800) );
OAI21X1TS U1839 ( .A0(intadd_42_B_1_), .A1(n2836), .B0(n2170), .Y(n1596) );
OAI21X1TS U1840 ( .A0(n2834), .A1(n2161), .B0(n2088), .Y(n1610) );
NOR2X1TS U1841 ( .A(n1647), .B(n2570), .Y(n2535) );
NOR2X1TS U1842 ( .A(n2593), .B(n2570), .Y(n2567) );
NOR2X1TS U1843 ( .A(n2598), .B(n2570), .Y(n2561) );
INVX2TS U1844 ( .A(n2534), .Y(n2572) );
NOR2X1TS U1845 ( .A(n2588), .B(n2570), .Y(n2571) );
NOR2X1TS U1846 ( .A(n1703), .B(n2570), .Y(n2544) );
NOR2X1TS U1847 ( .A(n1719), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1720) );
NOR2X1TS U1848 ( .A(n2609), .B(n2570), .Y(n2539) );
NOR2X1TS U1849 ( .A(n2603), .B(n2570), .Y(n2554) );
NOR2X4TS U1850 ( .A(n2802), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n1944) );
OAI21X1TS U1851 ( .A0(n2834), .A1(intadd_42_CI), .B0(n2085), .Y(n1340) );
OAI21X1TS U1852 ( .A0(n2834), .A1(intadd_43_CI), .B0(n2086), .Y(n1430) );
AOI211X1TS U1853 ( .A0(n1796), .A1(n1795), .B0(n1794), .C0(n1793), .Y(n1797)
);
NOR2X1TS U1854 ( .A(n1696), .B(n2617), .Y(n2596) );
INVX2TS U1855 ( .A(n2915), .Y(n2123) );
INVX3TS U1856 ( .A(n2938), .Y(n2834) );
INVX3TS U1857 ( .A(n2315), .Y(n2421) );
NOR2X1TS U1858 ( .A(n1697), .B(n2617), .Y(n2601) );
NOR2X1TS U1859 ( .A(n1703), .B(n2617), .Y(n2607) );
NOR2X1TS U1860 ( .A(n2609), .B(n2617), .Y(n2610) );
NOR2X1TS U1861 ( .A(n2593), .B(n2617), .Y(n2594) );
NOR2X1TS U1862 ( .A(n2598), .B(n2617), .Y(n2599) );
NOR2X1TS U1863 ( .A(n2603), .B(n2617), .Y(n2604) );
NOR2X1TS U1864 ( .A(n2588), .B(n2617), .Y(n2591) );
AND2X4TS U1865 ( .A(n2167), .B(n2819), .Y(n2031) );
NAND4XLTS U1866 ( .A(n2008), .B(n2007), .C(n2006), .D(n2005), .Y(n2027) );
AND2X2TS U1867 ( .A(n1674), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n2702) );
NOR2X4TS U1868 ( .A(n2522), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n2524) );
NAND4XLTS U1869 ( .A(n2016), .B(n2015), .C(n2014), .D(n2013), .Y(n2026) );
AOI21X2TS U1870 ( .A0(n1923), .A1(n1832), .B0(n1831), .Y(n1934) );
AOI21X2TS U1871 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n2543), .Y(n1647)
);
INVX2TS U1872 ( .A(n2856), .Y(n2858) );
AOI31X2TS U1873 ( .A0(n2827), .A1(n3072), .A2(intadd_42_B_1_), .B0(n2195),
.Y(n2839) );
AOI32X2TS U1874 ( .A0(n2830), .A1(n2842), .A2(n3072), .B0(n2183), .B1(n2842),
.Y(n2187) );
OR2X2TS U1875 ( .A(n2357), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n2315) );
CLKAND2X4TS U1876 ( .A(n2590), .B(n1686), .Y(n2618) );
NAND4XLTS U1877 ( .A(n2000), .B(n1999), .C(n1998), .D(n1997), .Y(n2028) );
AOI211X1TS U1878 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n3100), .B0(n1761), .C0(n1759), .Y(n1816) );
OAI211X2TS U1879 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(
n3110), .B0(n1814), .C0(n1764), .Y(n1808) );
OR2X2TS U1880 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n2551), .Y(n1909) );
AOI32X2TS U1881 ( .A0(n2196), .A1(n3072), .A2(intadd_42_B_1_), .B0(n2830),
.B1(cont_iter_out[3]), .Y(n2841) );
BUFX3TS U1882 ( .A(n2861), .Y(n2856) );
NAND3X1TS U1883 ( .A(n3117), .B(n1755), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1757) );
OAI211X2TS U1884 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(
n3119), .B0(n1796), .C0(n1766), .Y(n1790) );
INVX1TS U1885 ( .A(n2812), .Y(n1898) );
OAI21X1TS U1886 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n3125), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n1810) );
NAND2BX1TS U1887 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n1755) );
NAND2BX1TS U1888 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1764) );
NAND2BX1TS U1889 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n1785) );
NAND2BX1TS U1890 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n1756) );
NAND2BX1TS U1891 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1766) );
NAND2BX1TS U1892 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1805) );
OR3X2TS U1893 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n3267), .Y(
n2855) );
CLKINVX2TS U1894 ( .A(n1633), .Y(n1700) );
NAND2BX1TS U1895 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1815) );
CLKBUFX2TS U1896 ( .A(n1633), .Y(n1699) );
OAI2BB1X2TS U1897 ( .A0N(n2701), .A1N(n1891), .B0(n1890), .Y(n1103) );
AOI22X2TS U1898 ( .A0(n1889), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2822), .Y(
n1890) );
AOI21X2TS U1899 ( .A0(n1904), .A1(n1900), .B0(n1888), .Y(n1893) );
XNOR2X2TS U1900 ( .A(DP_OP_33J13_122_2179_n1), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2264) );
NOR2X4TS U1901 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1730) );
OAI21X2TS U1902 ( .A0(n2678), .A1(n2672), .B0(n2673), .Y(n2687) );
OAI21X1TS U1903 ( .A0(n2659), .A1(n2653), .B0(n2654), .Y(n1904) );
OAI21X4TS U1904 ( .A0(n2630), .A1(n2624), .B0(n2625), .Y(n2639) );
OAI21X2TS U1905 ( .A0(n1842), .A1(n2748), .B0(n1841), .Y(n2733) );
NAND2X1TS U1906 ( .A(n3153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n2748) );
OAI21X2TS U1907 ( .A0(n2657), .A1(n1869), .B0(n1868), .Y(n1902) );
AOI21X4TS U1908 ( .A0(n2666), .A1(n1867), .B0(n1866), .Y(n2657) );
CLKINVX12TS U1909 ( .A(n2140), .Y(n2178) );
OAI211X1TS U1910 ( .A0(n2429), .A1(n1666), .B0(n2428), .C0(n2427), .Y(n1310)
);
OAI21X2TS U1911 ( .A0(n2676), .A1(n1861), .B0(n1860), .Y(n2685) );
AOI21X4TS U1912 ( .A0(n2706), .A1(n1859), .B0(n1858), .Y(n2676) );
OAI21X2TS U1913 ( .A0(n2695), .A1(n1865), .B0(n1864), .Y(n2666) );
AOI21X4TS U1914 ( .A0(n2685), .A1(n1863), .B0(n1862), .Y(n2695) );
OAI21X2TS U1915 ( .A0(n2725), .A1(n1849), .B0(n1848), .Y(n2715) );
AOI21X2TS U1916 ( .A0(n2731), .A1(n1847), .B0(n1846), .Y(n2725) );
OAI21X2TS U1917 ( .A0(n2628), .A1(n1853), .B0(n1852), .Y(n2637) );
AOI21X4TS U1918 ( .A0(n2715), .A1(n1851), .B0(n1850), .Y(n2628) );
OAI21X4TS U1919 ( .A0(n2697), .A1(n2691), .B0(n2692), .Y(n2668) );
AOI21X4TS U1920 ( .A0(n2687), .A1(n2683), .B0(n1886), .Y(n2697) );
OAI21X4TS U1921 ( .A0(n2649), .A1(n2643), .B0(n2644), .Y(n2708) );
AOI21X4TS U1922 ( .A0(n2639), .A1(n2635), .B0(n1884), .Y(n2649) );
OAI21X4TS U1923 ( .A0(n1955), .A1(n1878), .B0(n1877), .Y(n2740) );
AOI21X2TS U1924 ( .A0(n1929), .A1(n1874), .B0(n1873), .Y(n1955) );
OAI21X2TS U1925 ( .A0(n2647), .A1(n1857), .B0(n1856), .Y(n2706) );
AOI21X4TS U1926 ( .A0(n2637), .A1(n1855), .B0(n1854), .Y(n2647) );
NOR2X1TS U1927 ( .A(n1925), .B(n1830), .Y(n1832) );
OAI21X1TS U1928 ( .A0(n1830), .A1(n1924), .B0(n1829), .Y(n1831) );
NAND2X1TS U1929 ( .A(n3156), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1924) );
NOR2X1TS U1930 ( .A(n3145), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1830) );
AOI21X2TS U1931 ( .A0(n1902), .A1(n1871), .B0(n1870), .Y(n1872) );
CLKAND2X2TS U1932 ( .A(n3163), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]),
.Y(n1850) );
OR2X1TS U1933 ( .A(n3163), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .Y(
n1851) );
CLKAND2X2TS U1934 ( .A(n3159), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]),
.Y(n1866) );
CLKAND2X2TS U1935 ( .A(n3161), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]),
.Y(n1858) );
AOI2BB2XLTS U1936 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(
n3112), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1N(n1775),
.Y(n1776) );
AOI21X2TS U1937 ( .A0(n2717), .A1(n2713), .B0(n1883), .Y(n2630) );
AOI21X2TS U1938 ( .A0(n2668), .A1(n2664), .B0(n1887), .Y(n2659) );
AOI21X2TS U1939 ( .A0(n2708), .A1(n2704), .B0(n1885), .Y(n2678) );
CLKAND2X2TS U1940 ( .A(n3160), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]),
.Y(n1862) );
CLKAND2X2TS U1941 ( .A(n3162), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]),
.Y(n1854) );
NAND2BXLTS U1942 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n1787) );
NAND3XLTS U1943 ( .A(n3122), .B(n1785), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .Y(n1786) );
OAI2BB2XLTS U1944 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(
n1782), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1N(n3114),
.Y(n1795) );
OAI2BB2XLTS U1945 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B1(
n1792), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1N(n3111),
.Y(n1793) );
OAI2BB2XLTS U1946 ( .B0(n1791), .B1(n1790), .A0N(n1789), .A1N(n1788), .Y(
n1794) );
OAI32X1TS U1947 ( .A0(n1781), .A1(n1780), .A2(n1779), .B0(n1778), .B1(n1780),
.Y(n1798) );
INVX2TS U1948 ( .A(n1769), .Y(n1799) );
NOR2BX1TS U1949 ( .AN(n1768), .B(n1767), .Y(n1769) );
INVX2TS U1950 ( .A(n1790), .Y(n1768) );
AOI2BB1XLTS U1951 ( .A0N(n1716), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1717) );
AOI2BB1XLTS U1952 ( .A0N(n3107), .A1N(n1722), .B0(n1718), .Y(n1719) );
NOR3XLTS U1953 ( .A(n2150), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n3091), .Y(n1718) );
AOI211X2TS U1954 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n2547), .B0(n2531), .C0(n2530), .Y(n2593) );
OAI211X1TS U1955 ( .A0(n2606), .A1(n1668), .B0(n2560), .C0(n2559), .Y(n2600)
);
AO21XLTS U1956 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .A1(
n2547), .B0(n2546), .Y(n1650) );
NOR2X1TS U1957 ( .A(n2749), .B(n1842), .Y(n2732) );
AOI2BB2X1TS U1958 ( .B0(n1763), .B1(n1816), .A0N(n1762), .A1N(n1761), .Y(
n1822) );
INVX2TS U1959 ( .A(n3185), .Y(n2196) );
NOR2BX2TS U1960 ( .AN(n2200), .B(n2216), .Y(n2255) );
INVX2TS U1961 ( .A(n2721), .Y(n2723) );
INVX2TS U1962 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(
n2767) );
BUFX3TS U1963 ( .A(n1825), .Y(n2514) );
BUFX3TS U1964 ( .A(n1825), .Y(n2496) );
NOR2XLTS U1965 ( .A(n3146), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .Y(
n1869) );
NOR2XLTS U1966 ( .A(n3147), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .Y(
n1865) );
NOR2XLTS U1967 ( .A(n3148), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .Y(
n1861) );
INVX2TS U1968 ( .A(n2475), .Y(n2504) );
NOR2XLTS U1969 ( .A(n3149), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .Y(
n1857) );
NOR2XLTS U1970 ( .A(n3150), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .Y(
n1853) );
NOR2XLTS U1971 ( .A(n3151), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .Y(
n1849) );
OAI21XLTS U1972 ( .A0(n2799), .A1(n2798), .B0(n2797), .Y(n2801) );
BUFX3TS U1973 ( .A(n1823), .Y(n2458) );
BUFX3TS U1974 ( .A(n2475), .Y(n2513) );
INVX2TS U1975 ( .A(n2475), .Y(n2499) );
OAI211XLTS U1976 ( .A0(n2031), .A1(n2227), .B0(n2226), .C0(n2251), .Y(n1364)
);
AO22XLTS U1977 ( .A0(n2987), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n2897),
.Y(n1344) );
OAI222X1TS U1978 ( .A0(n3011), .A1(n3087), .B0(n3135), .B1(n3012), .C0(n3117), .C1(n3013), .Y(n1155) );
AO22XLTS U1979 ( .A0(n2987), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n2123),
.Y(n1342) );
AO21XLTS U1980 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(
n2558), .B0(n2529), .Y(n866) );
AOI2BB2XLTS U1981 ( .B0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .B1(
n2621), .A0N(n2616), .A1N(n2570), .Y(n2528) );
NAND2BXLTS U1982 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1773) );
NAND2X1TS U1983 ( .A(n1801), .B(n1800), .Y(n1821) );
NOR2BX1TS U1984 ( .AN(n1765), .B(n1803), .Y(n1801) );
NAND2X4TS U1985 ( .A(n1740), .B(n3091), .Y(n2137) );
OAI21XLTS U1986 ( .A0(n1836), .A1(n1963), .B0(n1835), .Y(n1837) );
INVX2TS U1987 ( .A(n1659), .Y(n1660) );
AO21XLTS U1988 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n2547), .B0(n2536), .Y(n1651) );
INVX2TS U1989 ( .A(n2740), .Y(n2786) );
AOI21X1TS U1990 ( .A0(n2733), .A1(n1710), .B0(n1843), .Y(n2777) );
CLKAND2X2TS U1991 ( .A(n1707), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]),
.Y(n1843) );
OR2X1TS U1992 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2664) );
NOR3X2TS U1993 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n2138) );
NOR2X1TS U1994 ( .A(n1715), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n2151) );
OR2X1TS U1995 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2704) );
OR2X1TS U1996 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n2713) );
OAI21X1TS U1997 ( .A0(n2727), .A1(n2721), .B0(n2722), .Y(n2717) );
OR2X1TS U1998 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1900) );
NAND4XLTS U1999 ( .A(n2024), .B(n2023), .C(n2022), .D(n2021), .Y(n2025) );
INVX2TS U2000 ( .A(n2855), .Y(n2854) );
AND3X1TS U2001 ( .A(n2313), .B(n2312), .C(n2311), .Y(n2345) );
OAI21XLTS U2002 ( .A0(n2796), .A1(n2749), .B0(n2748), .Y(n2753) );
OAI21XLTS U2003 ( .A0(n2762), .A1(n1925), .B0(n1924), .Y(n1928) );
NAND3XLTS U2004 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n3266), .C(n1643), .Y(n2817) );
INVX2TS U2005 ( .A(n1665), .Y(n1666) );
INVX2TS U2006 ( .A(n1641), .Y(n1693) );
INVX2TS U2007 ( .A(n2809), .Y(n2818) );
BUFX3TS U2008 ( .A(n2063), .Y(n2972) );
BUFX3TS U2009 ( .A(n2066), .Y(n2971) );
AOI31X1TS U2010 ( .A0(n1727), .A1(n2143), .A2(n1726), .B0(n2821), .Y(n2808)
);
BUFX3TS U2011 ( .A(n2243), .Y(n2961) );
BUFX3TS U2012 ( .A(n2209), .Y(n2931) );
BUFX3TS U2013 ( .A(n2066), .Y(n2930) );
NOR2X1TS U2014 ( .A(n2826), .B(n2815), .Y(n2197) );
OAI21XLTS U2015 ( .A0(n2786), .A1(n2741), .B0(n2750), .Y(n2743) );
INVX2TS U2016 ( .A(n2732), .Y(n2735) );
OAI21XLTS U2017 ( .A0(n2786), .A1(n2785), .B0(n2784), .Y(n2788) );
INVX2TS U2018 ( .A(n2779), .Y(n2781) );
NAND2X1TS U2019 ( .A(n1705), .B(n2590), .Y(n2534) );
OAI21XLTS U2020 ( .A0(n1978), .A1(n1964), .B0(n1963), .Y(n1967) );
INVX2TS U2021 ( .A(n1734), .Y(n1742) );
AOI211X1TS U2022 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n1739), .B0(n1738), .C0(n2177), .Y(n1741) );
NAND3X1TS U2023 ( .A(cont_iter_out[1]), .B(n2196), .C(n2195), .Y(n2815) );
INVX2TS U2024 ( .A(n2828), .Y(n2826) );
AO22XLTS U2025 ( .A0(n2980), .A1(d_ff2_Z[31]), .B0(n2840), .B1(
d_ff3_sign_out), .Y(n1213) );
AO22XLTS U2026 ( .A0(n2913), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n2921),
.Y(n1390) );
AO22XLTS U2027 ( .A0(n1687), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n2123),
.Y(n1417) );
AO22XLTS U2028 ( .A0(n2913), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n2123),
.Y(n1396) );
AO22XLTS U2029 ( .A0(n2987), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n2921),
.Y(n1209) );
AO22XLTS U2030 ( .A0(n2913), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n2897),
.Y(n1384) );
AO22XLTS U2031 ( .A0(n2913), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n2914),
.Y(n1378) );
AO22XLTS U2032 ( .A0(n2913), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n2871),
.Y(n1399) );
AO22XLTS U2033 ( .A0(n2920), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n2921),
.Y(n1366) );
AO22XLTS U2034 ( .A0(n2920), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n2897),
.Y(n1357) );
AO22XLTS U2035 ( .A0(n2920), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n2914),
.Y(n1354) );
AO22XLTS U2036 ( .A0(n2920), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n2871),
.Y(n1372) );
OAI211XLTS U2037 ( .A0(n2031), .A1(n2223), .B0(n2222), .C0(n2235), .Y(n1382)
);
NOR2XLTS U2038 ( .A(n2617), .B(n1647), .Y(n2613) );
AO22XLTS U2039 ( .A0(n2983), .A1(n2982), .B0(n2981), .B1(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n1212) );
AOI2BB2XLTS U2040 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(n2982) );
OAI21XLTS U2041 ( .A0(n2947), .A1(n1649), .B0(n2423), .Y(n1558) );
MX2X1TS U2042 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .S0(n3009), .Y(n936) );
AO22XLTS U2043 ( .A0(n2991), .A1(result_add_subt[23]), .B0(n2950), .B1(
d_ff_Xn[23]), .Y(n1295) );
AO22XLTS U2044 ( .A0(n2952), .A1(result_add_subt[20]), .B0(n2984), .B1(
d_ff_Yn[20]), .Y(n1492) );
AO22XLTS U2045 ( .A0(n2952), .A1(result_add_subt[19]), .B0(n2984), .B1(
d_ff_Yn[19]), .Y(n1495) );
AO22XLTS U2046 ( .A0(n2985), .A1(result_add_subt[21]), .B0(n2984), .B1(
d_ff_Yn[21]), .Y(n1489) );
AO22XLTS U2047 ( .A0(n2952), .A1(result_add_subt[18]), .B0(n2984), .B1(
d_ff_Yn[18]), .Y(n1498) );
AO22XLTS U2048 ( .A0(n2952), .A1(result_add_subt[15]), .B0(n2984), .B1(
d_ff_Yn[15]), .Y(n1507) );
AO22XLTS U2049 ( .A0(n2985), .A1(result_add_subt[22]), .B0(n2984), .B1(
d_ff_Yn[22]), .Y(n1486) );
AO22XLTS U2050 ( .A0(n2985), .A1(result_add_subt[30]), .B0(n2984), .B1(
d_ff_Yn[30]), .Y(n1211) );
AO22XLTS U2051 ( .A0(n2985), .A1(result_add_subt[29]), .B0(n2955), .B1(
d_ff_Yn[29]), .Y(n1278) );
AO22XLTS U2052 ( .A0(n2952), .A1(result_add_subt[26]), .B0(n2955), .B1(
d_ff_Yn[26]), .Y(n1287) );
AO22XLTS U2053 ( .A0(n2985), .A1(result_add_subt[25]), .B0(n2955), .B1(
d_ff_Yn[25]), .Y(n1290) );
AO22XLTS U2054 ( .A0(n2985), .A1(result_add_subt[24]), .B0(n2955), .B1(
d_ff_Yn[24]), .Y(n1293) );
AO22XLTS U2055 ( .A0(n2858), .A1(result_add_subt[4]), .B0(n2856), .B1(
d_ff_Yn[4]), .Y(n1540) );
AO22XLTS U2056 ( .A0(n2952), .A1(result_add_subt[17]), .B0(n2984), .B1(
d_ff_Yn[17]), .Y(n1501) );
AO22XLTS U2057 ( .A0(n2952), .A1(result_add_subt[13]), .B0(n2861), .B1(
d_ff_Yn[13]), .Y(n1513) );
AO22XLTS U2058 ( .A0(n2858), .A1(result_add_subt[6]), .B0(n2856), .B1(
d_ff_Yn[6]), .Y(n1534) );
AO22XLTS U2059 ( .A0(n2858), .A1(result_add_subt[8]), .B0(n2861), .B1(
d_ff_Yn[8]), .Y(n1528) );
AO22XLTS U2060 ( .A0(n2952), .A1(result_add_subt[16]), .B0(n2984), .B1(
d_ff_Yn[16]), .Y(n1504) );
AO22XLTS U2061 ( .A0(n2952), .A1(result_add_subt[14]), .B0(n2861), .B1(
d_ff_Yn[14]), .Y(n1510) );
AO22XLTS U2062 ( .A0(n2858), .A1(result_add_subt[11]), .B0(n2861), .B1(
d_ff_Yn[11]), .Y(n1519) );
AO22XLTS U2063 ( .A0(n2952), .A1(result_add_subt[12]), .B0(n2861), .B1(
d_ff_Yn[12]), .Y(n1516) );
AO22XLTS U2064 ( .A0(n2858), .A1(result_add_subt[10]), .B0(n2861), .B1(
d_ff_Yn[10]), .Y(n1522) );
AO22XLTS U2065 ( .A0(n2858), .A1(result_add_subt[2]), .B0(n2955), .B1(
d_ff_Yn[2]), .Y(n1546) );
AO22XLTS U2066 ( .A0(n2858), .A1(result_add_subt[3]), .B0(n2856), .B1(
d_ff_Yn[3]), .Y(n1543) );
AO22XLTS U2067 ( .A0(n2985), .A1(result_add_subt[0]), .B0(n2955), .B1(
d_ff_Yn[0]), .Y(n1552) );
AO22XLTS U2068 ( .A0(n2858), .A1(result_add_subt[7]), .B0(n2861), .B1(
d_ff_Yn[7]), .Y(n1531) );
AO22XLTS U2069 ( .A0(n2858), .A1(result_add_subt[9]), .B0(n2861), .B1(
d_ff_Yn[9]), .Y(n1525) );
AO22XLTS U2070 ( .A0(n2886), .A1(result_add_subt[1]), .B0(n2955), .B1(
d_ff_Yn[1]), .Y(n1549) );
AO22XLTS U2071 ( .A0(n2858), .A1(result_add_subt[5]), .B0(n2856), .B1(
d_ff_Yn[5]), .Y(n1537) );
AO22XLTS U2072 ( .A0(n2991), .A1(result_add_subt[27]), .B0(n2990), .B1(
d_ff_Xn[27]), .Y(n1283) );
AO22XLTS U2073 ( .A0(n2991), .A1(result_add_subt[22]), .B0(n2950), .B1(
d_ff_Xn[22]), .Y(n1485) );
AO22XLTS U2074 ( .A0(n2991), .A1(result_add_subt[30]), .B0(n2990), .B1(
d_ff_Xn[30]), .Y(n1210) );
AO22XLTS U2075 ( .A0(n2865), .A1(result_add_subt[18]), .B0(n2950), .B1(
d_ff_Xn[18]), .Y(n1497) );
AO22XLTS U2076 ( .A0(n2865), .A1(result_add_subt[15]), .B0(n2950), .B1(
d_ff_Xn[15]), .Y(n1506) );
AO22XLTS U2077 ( .A0(n2859), .A1(result_add_subt[4]), .B0(n2990), .B1(
d_ff_Xn[4]), .Y(n1539) );
AO22XLTS U2078 ( .A0(n2865), .A1(result_add_subt[21]), .B0(n2950), .B1(
d_ff_Xn[21]), .Y(n1488) );
AO22XLTS U2079 ( .A0(n2859), .A1(result_add_subt[11]), .B0(n2860), .B1(
d_ff_Xn[11]), .Y(n1518) );
AO22XLTS U2080 ( .A0(n2859), .A1(result_add_subt[8]), .B0(n2860), .B1(
d_ff_Xn[8]), .Y(n1527) );
AO22XLTS U2081 ( .A0(n2859), .A1(result_add_subt[9]), .B0(n2860), .B1(
d_ff_Xn[9]), .Y(n1524) );
AO22XLTS U2082 ( .A0(n2854), .A1(result_add_subt[0]), .B0(n2855), .B1(
d_ff_Xn[0]), .Y(n1551) );
AO22XLTS U2083 ( .A0(n2991), .A1(result_add_subt[25]), .B0(n2990), .B1(
d_ff_Xn[25]), .Y(n1289) );
AO22XLTS U2084 ( .A0(n2991), .A1(result_add_subt[24]), .B0(n2950), .B1(
d_ff_Xn[24]), .Y(n1292) );
AO22XLTS U2085 ( .A0(n2991), .A1(result_add_subt[29]), .B0(n2990), .B1(
d_ff_Xn[29]), .Y(n1277) );
AO22XLTS U2086 ( .A0(n2991), .A1(result_add_subt[26]), .B0(n2990), .B1(
d_ff_Xn[26]), .Y(n1286) );
AO22XLTS U2087 ( .A0(n2865), .A1(result_add_subt[20]), .B0(n2950), .B1(
d_ff_Xn[20]), .Y(n1491) );
AO22XLTS U2088 ( .A0(n2865), .A1(result_add_subt[19]), .B0(n2950), .B1(
d_ff_Xn[19]), .Y(n1494) );
AO22XLTS U2089 ( .A0(n2859), .A1(result_add_subt[6]), .B0(n2860), .B1(
d_ff_Xn[6]), .Y(n1533) );
AO22XLTS U2090 ( .A0(n2865), .A1(result_add_subt[17]), .B0(n2950), .B1(
d_ff_Xn[17]), .Y(n1500) );
AO22XLTS U2091 ( .A0(n2865), .A1(result_add_subt[16]), .B0(n2950), .B1(
d_ff_Xn[16]), .Y(n1503) );
AO22XLTS U2092 ( .A0(n2865), .A1(result_add_subt[13]), .B0(n2860), .B1(
d_ff_Xn[13]), .Y(n1512) );
AO22XLTS U2093 ( .A0(n2859), .A1(result_add_subt[10]), .B0(n2860), .B1(
d_ff_Xn[10]), .Y(n1521) );
AO22XLTS U2094 ( .A0(n2865), .A1(result_add_subt[14]), .B0(n2860), .B1(
d_ff_Xn[14]), .Y(n1509) );
AO22XLTS U2095 ( .A0(n2859), .A1(result_add_subt[3]), .B0(n2855), .B1(
d_ff_Xn[3]), .Y(n1542) );
AO22XLTS U2096 ( .A0(n2865), .A1(result_add_subt[12]), .B0(n2860), .B1(
d_ff_Xn[12]), .Y(n1515) );
AO22XLTS U2097 ( .A0(n2859), .A1(result_add_subt[7]), .B0(n2860), .B1(
d_ff_Xn[7]), .Y(n1530) );
AO22XLTS U2098 ( .A0(n2859), .A1(result_add_subt[2]), .B0(n2855), .B1(
d_ff_Xn[2]), .Y(n1545) );
AO22XLTS U2099 ( .A0(n2859), .A1(result_add_subt[5]), .B0(n2860), .B1(
d_ff_Xn[5]), .Y(n1536) );
AO22XLTS U2100 ( .A0(n2854), .A1(result_add_subt[1]), .B0(n2990), .B1(
d_ff_Xn[1]), .Y(n1548) );
AO22XLTS U2101 ( .A0(n2987), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n2921),
.Y(n1346) );
AO22XLTS U2102 ( .A0(n2920), .A1(d_ff_Yn[23]), .B0(d_ff2_Y[23]), .B1(n2921),
.Y(n1348) );
MX2X1TS U2103 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .S0(n3009), .Y(n972) );
MX2X1TS U2104 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .S0(n3037), .Y(n986) );
MX2X1TS U2105 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .S0(n3009), .Y(n965) );
MX2X1TS U2106 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .S0(n3009), .Y(n924) );
MX2X1TS U2107 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .S0(n3009), .Y(n920) );
MX2X1TS U2108 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .S0(n3009), .Y(n1016)
);
MX2X1TS U2109 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .S0(n3009), .Y(n993) );
AO22XLTS U2110 ( .A0(n2985), .A1(result_add_subt[28]), .B0(n2955), .B1(
d_ff_Yn[28]), .Y(n1281) );
AO22XLTS U2111 ( .A0(n1687), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n2123),
.Y(n1440) );
AO22XLTS U2112 ( .A0(n2922), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n2123),
.Y(n1454) );
AO22XLTS U2113 ( .A0(n1687), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n2921),
.Y(n1442) );
AO22XLTS U2114 ( .A0(n1687), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n2921),
.Y(n1476) );
AO22XLTS U2115 ( .A0(n2922), .A1(d_ff_Xn[8]), .B0(d_ff2_X[8]), .B1(n2897),
.Y(n1468) );
AO22XLTS U2116 ( .A0(n2922), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n2871),
.Y(n1462) );
AO22XLTS U2117 ( .A0(n2987), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n2914),
.Y(n1484) );
AO22XLTS U2118 ( .A0(n2922), .A1(d_ff_Xn[9]), .B0(d_ff2_X[9]), .B1(n2914),
.Y(n1466) );
AO22XLTS U2119 ( .A0(n2985), .A1(result_add_subt[23]), .B0(n2984), .B1(
d_ff_Yn[23]), .Y(n1296) );
AO22XLTS U2120 ( .A0(n2985), .A1(result_add_subt[27]), .B0(n2955), .B1(
d_ff_Yn[27]), .Y(n1284) );
AO22XLTS U2121 ( .A0(n2920), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n2123),
.Y(n1351) );
AO22XLTS U2122 ( .A0(n2920), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n2914),
.Y(n1363) );
AO22XLTS U2123 ( .A0(n2920), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n2871),
.Y(n1360) );
AO22XLTS U2124 ( .A0(n1687), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n2914),
.Y(n1405) );
AO22XLTS U2125 ( .A0(n2920), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n2897),
.Y(n1369) );
AO22XLTS U2126 ( .A0(n2913), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n2871),
.Y(n1375) );
AO22XLTS U2127 ( .A0(n2920), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n2897),
.Y(n1387) );
AO22XLTS U2128 ( .A0(n2913), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n2914),
.Y(n1381) );
AO22XLTS U2129 ( .A0(n2913), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n2897),
.Y(n1408) );
AO22XLTS U2130 ( .A0(n1687), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n2921),
.Y(n1414) );
AO22XLTS U2131 ( .A0(n2913), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n2871),
.Y(n1402) );
AO22XLTS U2132 ( .A0(n2991), .A1(result_add_subt[28]), .B0(n2990), .B1(
d_ff_Xn[28]), .Y(n1280) );
AO22XLTS U2133 ( .A0(n2987), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n2871),
.Y(n1345) );
AO22XLTS U2134 ( .A0(n2922), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n2123),
.Y(n1438) );
XOR2XLTS U2135 ( .A(n1954), .B(n1953), .Y(n1959) );
XOR2XLTS U2136 ( .A(n2762), .B(n2761), .Y(n2766) );
XOR2XLTS U2137 ( .A(n2774), .B(n2773), .Y(n2776) );
CLKAND2X2TS U2138 ( .A(n2772), .B(n2771), .Y(n2774) );
XOR2XLTS U2139 ( .A(n1978), .B(n1977), .Y(n1987) );
AO22XLTS U2140 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1122) );
AO22XLTS U2141 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n956) );
AO22XLTS U2142 ( .A0(n3010), .A1(n2999), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1169) );
AO22XLTS U2143 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1066)
);
AO22XLTS U2144 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1150) );
AO22XLTS U2145 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1139) );
AO22XLTS U2146 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n997)
);
AO22XLTS U2147 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n933) );
AO22XLTS U2148 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n1661), .Y(n3182)
);
XOR2XLTS U2149 ( .A(n1872), .B(n3164), .Y(n1891) );
AO22XLTS U2150 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B0(n1713), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1117) );
AO22XLTS U2151 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B0(n1713), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1112) );
AO22XLTS U2152 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .Y(n960) );
AO22XLTS U2153 ( .A0(n3010), .A1(n2995), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1170) );
MX2X1TS U2154 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .S0(n2523), .Y(n948)
);
MX2X1TS U2155 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .S0(n2523), .Y(n940)
);
MX2X1TS U2156 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .S0(n2523), .Y(n928)
);
MX2X1TS U2157 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n2523), .Y(n896)
);
MX2X1TS U2158 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n2523), .Y(n916)
);
MX2X1TS U2159 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .S0(n2523), .Y(n952)
);
MX2X1TS U2160 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n2523), .Y(n944)
);
MX2X1TS U2161 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n2523), .Y(n932)
);
MX2X1TS U2162 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .B(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .S0(n3037), .Y(n1045) );
AO22XLTS U2163 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n918) );
AO22XLTS U2164 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n902) );
AO22XLTS U2165 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n910) );
AO22XLTS U2166 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n914) );
AO22XLTS U2167 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B0(n3061), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n906) );
AO22XLTS U2168 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n969)
);
AO22XLTS U2169 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n976)
);
AO22XLTS U2170 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n922) );
AO22XLTS U2171 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n967) );
AO22XLTS U2172 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n926) );
AO22XLTS U2173 ( .A0(n3062), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B0(n3060), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n938) );
AO22XLTS U2174 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n974) );
AO22XLTS U2175 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n950) );
AO22XLTS U2176 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n942) );
AO22XLTS U2177 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n954) );
AO22XLTS U2178 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n930) );
AO22XLTS U2179 ( .A0(n3058), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n946) );
AO22XLTS U2180 ( .A0(n3062), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B0(n3060), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n934) );
AO22XLTS U2181 ( .A0(n3058), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP),
.B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .Y(n963)
);
MX2X1TS U2182 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n2524), .Y(n908)
);
MX2X1TS U2183 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n2524), .Y(n904)
);
MX2X1TS U2184 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n2524), .Y(n900)
);
MX2X1TS U2185 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n2524), .Y(n912)
);
MX2X1TS U2186 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n2524), .Y(n892)
);
AO22XLTS U2187 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1140) );
AO22XLTS U2188 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1145) );
AO22XLTS U2189 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1135) );
AO22XLTS U2190 ( .A0(n3010), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1130) );
AO22XLTS U2191 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1125) );
AO22XLTS U2192 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1120) );
AO22XLTS U2193 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1115) );
AO22XLTS U2194 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1078)
);
AO22XLTS U2195 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B0(n3033), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1075)
);
AO22XLTS U2196 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1057) );
AO22XLTS U2197 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1063) );
AO22XLTS U2198 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1072) );
AO22XLTS U2199 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1060) );
AO22XLTS U2200 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1096) );
AO22XLTS U2201 ( .A0(n3041), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1069) );
AO22XLTS U2202 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1081) );
AO22XLTS U2203 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1093) );
AO22XLTS U2204 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1087) );
AO22XLTS U2205 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1084) );
AO22XLTS U2206 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B0(n3033), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1090) );
AO22XLTS U2207 ( .A0(n3025), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B0(n3020), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1099) );
AO22XLTS U2208 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP),
.B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .Y(n1054)
);
AO22XLTS U2209 ( .A0(n3041), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP),
.B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .Y(n1047)
);
AO22XLTS U2210 ( .A0(n3010), .A1(n3001), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1168) );
AO22XLTS U2211 ( .A0(n3054), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM),
.B0(n3053), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .Y(
n959) );
AO22XLTS U2212 ( .A0(n3054), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM),
.B0(n3053), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(
n1050) );
AO22XLTS U2213 ( .A0(n1684), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .B0(n3055), .B1(
zero_flag), .Y(n958) );
AO22XLTS U2214 ( .A0(n1674), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG),
.B0(n2822), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .Y(n1051)
);
AO22XLTS U2215 ( .A0(n3065), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B0(n3064), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n898) );
AO22XLTS U2216 ( .A0(n3065), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B0(n3040), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n894) );
AO22XLTS U2217 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n3066), .Y(n3181) );
AO22XLTS U2218 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n3066), .Y(n3180) );
AO22XLTS U2219 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n3066), .Y(n3183)
);
AO22XLTS U2220 ( .A0(n1659), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n3066), .Y(n3184)
);
AO22XLTS U2221 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n897) );
AO22XLTS U2222 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n893) );
AO22XLTS U2223 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n3066), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1144) );
AO22XLTS U2224 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n973) );
AO22XLTS U2225 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n953) );
AO22XLTS U2226 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .Y(n1046)
);
AO22XLTS U2227 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1134) );
AO22XLTS U2228 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1129) );
AO22XLTS U2229 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1124) );
AO22XLTS U2230 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1119) );
AO22XLTS U2231 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1114) );
AO22XLTS U2232 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .Y(n962)
);
AO22XLTS U2233 ( .A0(n3059), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1),
.B0(n3228), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .Y(n1053)
);
AO22XLTS U2234 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1004)
);
AO22XLTS U2235 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n990)
);
AO22XLTS U2236 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n983)
);
AO22XLTS U2237 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1020)
);
AO22XLTS U2238 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n988) );
AO22XLTS U2239 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n981) );
AO22XLTS U2240 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1002) );
AO22XLTS U2241 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B0(n3040), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1018) );
AO22XLTS U2242 ( .A0(n1922), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B0(n3051), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n995) );
AO22XLTS U2243 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n1661), .Y(n3177) );
AO22XLTS U2244 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n1661), .Y(n3179) );
AO22XLTS U2245 ( .A0(busy), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n1661), .Y(n3178) );
AO22XLTS U2246 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1149) );
AO22XLTS U2247 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n937) );
AO22XLTS U2248 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n3228), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n949) );
AO22XLTS U2249 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n941) );
AO22XLTS U2250 ( .A0(n3059), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n929) );
AO22XLTS U2251 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n945) );
AO22XLTS U2252 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n917) );
AO22XLTS U2253 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n909) );
AO22XLTS U2254 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n913) );
AO22XLTS U2255 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n1660), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n905) );
AO22XLTS U2256 ( .A0(n3063), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n1661), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n901) );
MX2X1TS U2257 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n3054), .Y(n1131)
);
MX2X1TS U2258 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n3054), .Y(n1121)
);
MX2X1TS U2259 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n1702), .Y(n1146)
);
MX2X1TS U2260 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n1702), .Y(n1141)
);
MX2X1TS U2261 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n3054), .Y(n1136)
);
MX2X1TS U2262 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n3054), .Y(n1126)
);
MX2X1TS U2263 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n3054), .Y(n1116)
);
MX2X1TS U2264 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n3054), .Y(n1111)
);
XOR2XLTS U2265 ( .A(n2628), .B(n2627), .Y(n2633) );
MX2X1TS U2266 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .S0(n3037), .Y(n979) );
MX2X1TS U2267 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .S0(n3009), .Y(n1000)
);
AO21XLTS U2268 ( .A0(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]),
.A1(n2824), .B0(n2808), .Y(n1007) );
AO21XLTS U2269 ( .A0(n2828), .A1(n2815), .B0(n2811), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
NOR2XLTS U2270 ( .A(n2814), .B(n2862), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
AOI2BB1XLTS U2271 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.A1N(overflow_flag), .B0(n3016), .Y(n1104) );
AO21XLTS U2272 ( .A0(underflow_flag), .A1(n1683), .B0(n3014), .Y(n1105) );
AO22XLTS U2273 ( .A0(n2846), .A1(d_ff1_operation_out), .B0(n2845), .B1(
operation), .Y(n1593) );
OAI21XLTS U2274 ( .A0(n1898), .A1(n2813), .B0(n2868), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
AO22XLTS U2275 ( .A0(n2846), .A1(d_ff1_shift_region_flag_out[1]), .B0(n2845),
.B1(shift_region_flag[1]), .Y(n1591) );
AO22XLTS U2276 ( .A0(n2846), .A1(d_ff1_shift_region_flag_out[0]), .B0(n2845),
.B1(shift_region_flag[0]), .Y(n1592) );
XOR2XLTS U2277 ( .A(n2725), .B(n2724), .Y(n2730) );
AO22XLTS U2278 ( .A0(d_ff2_Y[28]), .A1(n2897), .B0(n2922), .B1(d_ff_Yn[28]),
.Y(n1343) );
OAI21XLTS U2279 ( .A0(n3080), .A1(n2504), .B0(n2497), .Y(n895) );
OAI21XLTS U2280 ( .A0(n3111), .A1(n2499), .B0(n1826), .Y(n899) );
OAI21XLTS U2281 ( .A0(n3115), .A1(n2499), .B0(n2495), .Y(n919) );
OAI21XLTS U2282 ( .A0(n1640), .A1(n2499), .B0(n2486), .Y(n923) );
OAI21XLTS U2283 ( .A0(n1653), .A1(n2499), .B0(n2485), .Y(n927) );
OAI21XLTS U2284 ( .A0(n2489), .A1(n2499), .B0(n2488), .Y(n931) );
OAI21XLTS U2285 ( .A0(n2491), .A1(n2504), .B0(n2490), .Y(n947) );
OAI21XLTS U2286 ( .A0(n1654), .A1(n2504), .B0(n2484), .Y(n951) );
OAI21XLTS U2287 ( .A0(n3119), .A1(n2504), .B0(n2476), .Y(n955) );
OAI21XLTS U2288 ( .A0(n3119), .A1(n2457), .B0(n2448), .Y(n957) );
AO22XLTS U2289 ( .A0(n2524), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2),
.B0(n2558), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .Y(n961)
);
AO22XLTS U2290 ( .A0(n3038), .A1(n2469), .B0(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .B1(n3039), .Y(n964) );
OAI21XLTS U2291 ( .A0(n3123), .A1(n2504), .B0(n2479), .Y(n975) );
XOR2XLTS U2292 ( .A(n2657), .B(n2656), .Y(n2662) );
XOR2XLTS U2293 ( .A(n2695), .B(n2694), .Y(n2700) );
XOR2XLTS U2294 ( .A(n2676), .B(n2675), .Y(n2681) );
OAI21XLTS U2295 ( .A0(n3112), .A1(n2457), .B0(n2455), .Y(n1021) );
XOR2XLTS U2296 ( .A(n2647), .B(n2646), .Y(n2652) );
XOR2XLTS U2297 ( .A(n2796), .B(n2795), .Y(n2806) );
AO22X1TS U2298 ( .A0(n1894), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .B1(n2822), .Y(n1044) );
AO21XLTS U2299 ( .A0(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .A1(n3039),
.B0(n3038), .Y(n1048) );
AO22XLTS U2300 ( .A0(n3037), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2),
.B0(n2585), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .Y(n1052)
);
OAI21XLTS U2301 ( .A0(n1654), .A1(n2457), .B0(n2443), .Y(n1058) );
OAI21XLTS U2302 ( .A0(n2491), .A1(n2457), .B0(n2456), .Y(n1061) );
OAI21XLTS U2303 ( .A0(n3122), .A1(n2457), .B0(n2449), .Y(n1067) );
OAI21XLTS U2304 ( .A0(n3110), .A1(n2463), .B0(n2445), .Y(n1085) );
OAI21XLTS U2305 ( .A0(n2451), .A1(n2463), .B0(n2450), .Y(n1088) );
OAI21XLTS U2306 ( .A0(n3111), .A1(n2463), .B0(n2453), .Y(n1097) );
MX2X1TS U2307 ( .A(n2517), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n2824), .Y(
n1102) );
AO22XLTS U2308 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .Y(n1113) );
AO22XLTS U2309 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .Y(n1118) );
AO22XLTS U2310 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n2612), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .Y(n1123) );
AO22XLTS U2311 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1127) );
AO22XLTS U2312 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n2622), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .Y(n1128) );
AO22XLTS U2313 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1132) );
AO22XLTS U2314 ( .A0(n3037), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n2585), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .Y(n1133) );
AO22XLTS U2315 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1137) );
AO22XLTS U2316 ( .A0(n2523), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n2558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .Y(n1138) );
AO22XLTS U2317 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1142) );
AO22XLTS U2318 ( .A0(n3009), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n2622), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .Y(n1143) );
AO22XLTS U2319 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B0(n3008), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1147) );
AO22XLTS U2320 ( .A0(n2523), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n2558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .Y(n1148) );
AO22XLTS U2321 ( .A0(n3010), .A1(n3006), .B0(n3007), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1167) );
AO22XLTS U2322 ( .A0(n3010), .A1(n1989), .B0(n3064), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1171) );
OAI21XLTS U2323 ( .A0(beg_fsm_cordic), .A1(n2810), .B0(n2169), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AO22XLTS U2324 ( .A0(n2870), .A1(d_ff2_X[5]), .B0(n2866), .B1(
d_ff3_sh_x_out[5]), .Y(n1473) );
AO22XLTS U2325 ( .A0(n2980), .A1(d_ff2_Y[5]), .B0(n2912), .B1(
d_ff3_sh_y_out[5]), .Y(n1401) );
AO22XLTS U2326 ( .A0(n2857), .A1(result_add_subt[5]), .B0(n2862), .B1(
d_ff_Zn[5]), .Y(n1538) );
AO22XLTS U2327 ( .A0(n2940), .A1(d_ff2_X[9]), .B0(n2866), .B1(
d_ff3_sh_x_out[9]), .Y(n1465) );
AO22XLTS U2328 ( .A0(n2903), .A1(d_ff2_Y[9]), .B0(n2912), .B1(
d_ff3_sh_y_out[9]), .Y(n1389) );
AO22XLTS U2329 ( .A0(n2864), .A1(result_add_subt[9]), .B0(n2863), .B1(
d_ff_Zn[9]), .Y(n1526) );
AO22XLTS U2330 ( .A0(n2870), .A1(d_ff2_X[1]), .B0(n2868), .B1(
d_ff3_sh_x_out[1]), .Y(n1481) );
AO22XLTS U2331 ( .A0(n2980), .A1(d_ff2_Y[1]), .B0(n2988), .B1(
d_ff3_sh_y_out[1]), .Y(n1413) );
AO22XLTS U2332 ( .A0(n2857), .A1(result_add_subt[1]), .B0(n2862), .B1(
d_ff_Zn[1]), .Y(n1550) );
AO22XLTS U2333 ( .A0(n2870), .A1(d_ff2_X[0]), .B0(n2979), .B1(
d_ff3_sh_x_out[0]), .Y(n1483) );
AO22XLTS U2334 ( .A0(n2989), .A1(d_ff2_Y[0]), .B0(n2988), .B1(
d_ff3_sh_y_out[0]), .Y(n1416) );
AO22XLTS U2335 ( .A0(n2857), .A1(result_add_subt[0]), .B0(n2954), .B1(
d_ff_Zn[0]), .Y(n1553) );
AO22XLTS U2336 ( .A0(n2929), .A1(d_ff2_X[7]), .B0(n2979), .B1(
d_ff3_sh_x_out[7]), .Y(n1469) );
AO22XLTS U2337 ( .A0(n2938), .A1(d_ff2_Y[7]), .B0(n2912), .B1(
d_ff3_sh_y_out[7]), .Y(n1395) );
AO22XLTS U2338 ( .A0(n2857), .A1(result_add_subt[7]), .B0(n2863), .B1(
d_ff_Zn[7]), .Y(n1532) );
AO22XLTS U2339 ( .A0(n2870), .A1(d_ff2_X[2]), .B0(n2866), .B1(
d_ff3_sh_x_out[2]), .Y(n1479) );
AO22XLTS U2340 ( .A0(n2989), .A1(d_ff2_Y[2]), .B0(n2988), .B1(
d_ff3_sh_y_out[2]), .Y(n1410) );
AO22XLTS U2341 ( .A0(n2857), .A1(result_add_subt[2]), .B0(n2862), .B1(
d_ff_Zn[2]), .Y(n1547) );
AO22XLTS U2342 ( .A0(n2870), .A1(d_ff2_X[3]), .B0(n2840), .B1(
d_ff3_sh_x_out[3]), .Y(n1477) );
AO22XLTS U2343 ( .A0(n2980), .A1(d_ff2_Y[3]), .B0(n2988), .B1(
d_ff3_sh_y_out[3]), .Y(n1407) );
AO22XLTS U2344 ( .A0(n2857), .A1(result_add_subt[3]), .B0(n2862), .B1(
d_ff_Zn[3]), .Y(n1544) );
OAI21XLTS U2345 ( .A0(n2947), .A1(n1685), .B0(n2377), .Y(n1557) );
AO22XLTS U2346 ( .A0(n2989), .A1(d_ff2_X[31]), .B0(n2988), .B1(
d_ff3_sh_x_out[31]), .Y(n1421) );
AO22XLTS U2347 ( .A0(n2989), .A1(d_ff2_Y[31]), .B0(n2988), .B1(
d_ff3_sh_y_out[31]), .Y(n1208) );
AO22XLTS U2348 ( .A0(n2953), .A1(result_add_subt[31]), .B0(n2951), .B1(
d_ff_Zn[31]), .Y(n1419) );
AO22XLTS U2349 ( .A0(n2879), .A1(d_ff2_X[12]), .B0(n2868), .B1(
d_ff3_sh_x_out[12]), .Y(n1459) );
AO22XLTS U2350 ( .A0(n2989), .A1(d_ff2_Y[12]), .B0(n2912), .B1(
d_ff3_sh_y_out[12]), .Y(n1380) );
AO22XLTS U2351 ( .A0(n2864), .A1(result_add_subt[12]), .B0(n2863), .B1(
d_ff_Zn[12]), .Y(n1517) );
AO22XLTS U2352 ( .A0(n2940), .A1(d_ff2_X[10]), .B0(n2840), .B1(
d_ff3_sh_x_out[10]), .Y(n1463) );
AO22XLTS U2353 ( .A0(n2938), .A1(d_ff2_Y[10]), .B0(n2912), .B1(
d_ff3_sh_y_out[10]), .Y(n1386) );
AO22XLTS U2354 ( .A0(n2864), .A1(result_add_subt[10]), .B0(n2863), .B1(
d_ff_Zn[10]), .Y(n1523) );
AO22XLTS U2355 ( .A0(n2903), .A1(d_ff2_X[14]), .B0(n2872), .B1(
d_ff3_sh_x_out[14]), .Y(n1455) );
AO22XLTS U2356 ( .A0(n2989), .A1(d_ff2_Y[14]), .B0(n2919), .B1(
d_ff3_sh_y_out[14]), .Y(n1374) );
AO22XLTS U2357 ( .A0(n2864), .A1(result_add_subt[14]), .B0(n2954), .B1(
d_ff_Zn[14]), .Y(n1511) );
AO22XLTS U2358 ( .A0(n2989), .A1(d_ff2_X[11]), .B0(n2979), .B1(
d_ff3_sh_x_out[11]), .Y(n1461) );
AO22XLTS U2359 ( .A0(n2938), .A1(d_ff2_Y[11]), .B0(n2912), .B1(
d_ff3_sh_y_out[11]), .Y(n1383) );
AO22XLTS U2360 ( .A0(n2864), .A1(result_add_subt[11]), .B0(n2863), .B1(
d_ff_Zn[11]), .Y(n1520) );
AO22XLTS U2361 ( .A0(n2879), .A1(d_ff2_X[8]), .B0(n2868), .B1(
d_ff3_sh_x_out[8]), .Y(n1467) );
AO22XLTS U2362 ( .A0(n2938), .A1(d_ff2_Y[8]), .B0(n2912), .B1(
d_ff3_sh_y_out[8]), .Y(n1392) );
AO22XLTS U2363 ( .A0(n2857), .A1(result_add_subt[8]), .B0(n2863), .B1(
d_ff_Zn[8]), .Y(n1529) );
AO22XLTS U2364 ( .A0(n2870), .A1(d_ff2_X[16]), .B0(n2872), .B1(
d_ff3_sh_x_out[16]), .Y(n1451) );
AO22XLTS U2365 ( .A0(n2980), .A1(d_ff2_Y[16]), .B0(n2919), .B1(
d_ff3_sh_y_out[16]), .Y(n1368) );
AO22XLTS U2366 ( .A0(n2864), .A1(result_add_subt[16]), .B0(n2862), .B1(
d_ff_Zn[16]), .Y(n1505) );
AO22XLTS U2367 ( .A0(n2940), .A1(d_ff2_X[13]), .B0(n2866), .B1(
d_ff3_sh_x_out[13]), .Y(n1457) );
AO22XLTS U2368 ( .A0(n2938), .A1(d_ff2_Y[13]), .B0(n2912), .B1(
d_ff3_sh_y_out[13]), .Y(n1377) );
AO22XLTS U2369 ( .A0(n2864), .A1(result_add_subt[13]), .B0(n2954), .B1(
d_ff_Zn[13]), .Y(n1514) );
AO22XLTS U2370 ( .A0(n2879), .A1(d_ff2_X[6]), .B0(n2840), .B1(
d_ff3_sh_x_out[6]), .Y(n1471) );
AO22XLTS U2371 ( .A0(n2989), .A1(d_ff2_Y[6]), .B0(n2912), .B1(
d_ff3_sh_y_out[6]), .Y(n1398) );
AO22XLTS U2372 ( .A0(n2857), .A1(result_add_subt[6]), .B0(n2862), .B1(
d_ff_Zn[6]), .Y(n1535) );
AO22XLTS U2373 ( .A0(n2870), .A1(d_ff2_X[4]), .B0(n2868), .B1(
d_ff3_sh_x_out[4]), .Y(n1475) );
AO22XLTS U2374 ( .A0(n2980), .A1(d_ff2_Y[4]), .B0(n2912), .B1(
d_ff3_sh_y_out[4]), .Y(n1404) );
AO22XLTS U2375 ( .A0(n2857), .A1(result_add_subt[4]), .B0(n2862), .B1(
d_ff_Zn[4]), .Y(n1541) );
AO22XLTS U2376 ( .A0(n2929), .A1(d_ff2_X[17]), .B0(n2872), .B1(
d_ff3_sh_x_out[17]), .Y(n1449) );
AO22XLTS U2377 ( .A0(n2989), .A1(d_ff2_Y[17]), .B0(n2919), .B1(
d_ff3_sh_y_out[17]), .Y(n1365) );
AO22XLTS U2378 ( .A0(n2864), .A1(result_add_subt[17]), .B0(n2951), .B1(
d_ff_Zn[17]), .Y(n1502) );
AO22XLTS U2379 ( .A0(n2870), .A1(d_ff2_X[20]), .B0(n2872), .B1(
d_ff3_sh_x_out[20]), .Y(n1443) );
AO22XLTS U2380 ( .A0(n2929), .A1(d_ff2_Y[20]), .B0(n2919), .B1(
d_ff3_sh_y_out[20]), .Y(n1356) );
AO22XLTS U2381 ( .A0(n2953), .A1(result_add_subt[20]), .B0(n2951), .B1(
d_ff_Zn[20]), .Y(n1493) );
AO22XLTS U2382 ( .A0(n2879), .A1(d_ff2_X[19]), .B0(n2872), .B1(
d_ff3_sh_x_out[19]), .Y(n1445) );
AO22XLTS U2383 ( .A0(n2929), .A1(d_ff2_Y[19]), .B0(n2919), .B1(
d_ff3_sh_y_out[19]), .Y(n1359) );
AO22XLTS U2384 ( .A0(n2953), .A1(result_add_subt[19]), .B0(n2951), .B1(
d_ff_Zn[19]), .Y(n1496) );
AO22XLTS U2385 ( .A0(n2879), .A1(d_ff2_X[21]), .B0(n2872), .B1(
d_ff3_sh_x_out[21]), .Y(n1441) );
AO22XLTS U2386 ( .A0(n2929), .A1(d_ff2_Y[21]), .B0(n2919), .B1(
d_ff3_sh_y_out[21]), .Y(n1353) );
AO22XLTS U2387 ( .A0(n2953), .A1(result_add_subt[21]), .B0(n2951), .B1(
d_ff_Zn[21]), .Y(n1490) );
AO22XLTS U2388 ( .A0(n2879), .A1(d_ff2_X[18]), .B0(n2872), .B1(
d_ff3_sh_x_out[18]), .Y(n1447) );
AO22XLTS U2389 ( .A0(n2929), .A1(d_ff2_Y[18]), .B0(n2919), .B1(
d_ff3_sh_y_out[18]), .Y(n1362) );
AO22XLTS U2390 ( .A0(n2864), .A1(result_add_subt[18]), .B0(n2951), .B1(
d_ff_Zn[18]), .Y(n1499) );
AO22XLTS U2391 ( .A0(n2869), .A1(d_ff2_X[15]), .B0(n2872), .B1(
d_ff3_sh_x_out[15]), .Y(n1453) );
AO22XLTS U2392 ( .A0(n2980), .A1(d_ff2_Y[15]), .B0(n2919), .B1(
d_ff3_sh_y_out[15]), .Y(n1371) );
AO22XLTS U2393 ( .A0(n2864), .A1(result_add_subt[15]), .B0(n2862), .B1(
d_ff_Zn[15]), .Y(n1508) );
AO22XLTS U2394 ( .A0(n2879), .A1(d_ff2_X[22]), .B0(n2872), .B1(
d_ff3_sh_x_out[22]), .Y(n1439) );
AO22XLTS U2395 ( .A0(n2929), .A1(d_ff2_Y[22]), .B0(n2919), .B1(
d_ff3_sh_y_out[22]), .Y(n1350) );
AO22XLTS U2396 ( .A0(n2953), .A1(result_add_subt[22]), .B0(n2951), .B1(
d_ff_Zn[22]), .Y(n1487) );
AO22XLTS U2397 ( .A0(n2956), .A1(result_add_subt[30]), .B0(n2954), .B1(
d_ff_Zn[30]), .Y(n1276) );
AO22XLTS U2398 ( .A0(n2956), .A1(result_add_subt[29]), .B0(n2863), .B1(
d_ff_Zn[29]), .Y(n1279) );
AO22XLTS U2399 ( .A0(n2956), .A1(result_add_subt[28]), .B0(n2954), .B1(
d_ff_Zn[28]), .Y(n1282) );
AO22XLTS U2400 ( .A0(n2953), .A1(result_add_subt[27]), .B0(n2954), .B1(
d_ff_Zn[27]), .Y(n1285) );
AO22XLTS U2401 ( .A0(n2953), .A1(result_add_subt[26]), .B0(n2954), .B1(
d_ff_Zn[26]), .Y(n1288) );
AO22XLTS U2402 ( .A0(n2953), .A1(result_add_subt[25]), .B0(n2951), .B1(
d_ff_Zn[25]), .Y(n1291) );
AO22XLTS U2403 ( .A0(n2953), .A1(result_add_subt[24]), .B0(n2951), .B1(
d_ff_Zn[24]), .Y(n1294) );
AO22XLTS U2404 ( .A0(n2953), .A1(result_add_subt[23]), .B0(n2951), .B1(
d_ff_Zn[23]), .Y(n1297) );
AOI2BB2XLTS U2405 ( .B0(n2940), .B1(n2939), .A0N(d_ff3_sh_y_out[29]), .A1N(
n2938), .Y(n1328) );
AO22XLTS U2406 ( .A0(n2980), .A1(n2936), .B0(n2979), .B1(d_ff3_sh_y_out[28]),
.Y(n1330) );
OAI21XLTS U2407 ( .A0(n2935), .A1(n3141), .B0(n2937), .Y(n2936) );
AOI2BB2XLTS U2408 ( .B0(n2940), .B1(n2934), .A0N(d_ff3_sh_y_out[27]), .A1N(
n2938), .Y(n1332) );
AO22XLTS U2409 ( .A0(n2929), .A1(intadd_42_SUM_2_), .B0(n2866), .B1(
d_ff3_sh_y_out[26]), .Y(n1334) );
AO22XLTS U2410 ( .A0(n2929), .A1(intadd_42_SUM_1_), .B0(n2868), .B1(
d_ff3_sh_y_out[25]), .Y(n1336) );
AO22XLTS U2411 ( .A0(n2929), .A1(intadd_42_SUM_0_), .B0(n2919), .B1(
d_ff3_sh_y_out[24]), .Y(n1338) );
AOI2BB2XLTS U2412 ( .B0(n2940), .B1(n2881), .A0N(d_ff3_sh_x_out[29]), .A1N(
n2938), .Y(n1424) );
AO22XLTS U2413 ( .A0(n2879), .A1(n2878), .B0(n2988), .B1(d_ff3_sh_x_out[28]),
.Y(n1425) );
OAI21XLTS U2414 ( .A0(n2877), .A1(n3142), .B0(n2880), .Y(n2878) );
AOI2BB2XLTS U2415 ( .B0(n2940), .B1(n2876), .A0N(d_ff3_sh_x_out[27]), .A1N(
n2938), .Y(n1426) );
AO22XLTS U2416 ( .A0(n2879), .A1(intadd_43_SUM_2_), .B0(n2988), .B1(
d_ff3_sh_x_out[26]), .Y(n1427) );
AO22XLTS U2417 ( .A0(n2870), .A1(intadd_43_SUM_1_), .B0(n2988), .B1(
d_ff3_sh_x_out[25]), .Y(n1428) );
AO22XLTS U2418 ( .A0(n2879), .A1(intadd_43_SUM_0_), .B0(n2872), .B1(
d_ff3_sh_x_out[24]), .Y(n1429) );
AO22XLTS U2419 ( .A0(n2870), .A1(intadd_42_B_1_), .B0(n2979), .B1(
d_ff3_LUT_out[8]), .Y(n1602) );
AO22XLTS U2420 ( .A0(n2940), .A1(n2839), .B0(n2840), .B1(d_ff3_LUT_out[13]),
.Y(n1606) );
AO22XLTS U2421 ( .A0(n2980), .A1(n2838), .B0(n2840), .B1(d_ff3_LUT_out[19]),
.Y(n1608) );
AO22XLTS U2422 ( .A0(n2825), .A1(n1659), .B0(n2823), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n1624) );
AO22XLTS U2423 ( .A0(n2823), .A1(n3012), .B0(n2825), .B1(n2819), .Y(n1627)
);
AO22XLTS U2424 ( .A0(n2853), .A1(d_ff1_Z[31]), .B0(n2852), .B1(data_in[31]),
.Y(n1559) );
AO22XLTS U2425 ( .A0(n2853), .A1(d_ff1_Z[0]), .B0(n2852), .B1(data_in[0]),
.Y(n1560) );
AO22XLTS U2426 ( .A0(n2853), .A1(d_ff1_Z[1]), .B0(n2852), .B1(data_in[1]),
.Y(n1561) );
AO22XLTS U2427 ( .A0(n2853), .A1(d_ff1_Z[2]), .B0(n2852), .B1(data_in[2]),
.Y(n1562) );
AO22XLTS U2428 ( .A0(n2853), .A1(d_ff1_Z[3]), .B0(n2851), .B1(data_in[3]),
.Y(n1563) );
AO22XLTS U2429 ( .A0(n2853), .A1(d_ff1_Z[4]), .B0(n2852), .B1(data_in[4]),
.Y(n1564) );
AO22XLTS U2430 ( .A0(n2850), .A1(d_ff1_Z[5]), .B0(n2852), .B1(data_in[5]),
.Y(n1565) );
AO22XLTS U2431 ( .A0(n2850), .A1(d_ff1_Z[6]), .B0(n2849), .B1(data_in[6]),
.Y(n1566) );
AO22XLTS U2432 ( .A0(n2850), .A1(d_ff1_Z[7]), .B0(n2849), .B1(data_in[7]),
.Y(n1567) );
AO22XLTS U2433 ( .A0(n2850), .A1(d_ff1_Z[8]), .B0(n2849), .B1(data_in[8]),
.Y(n1568) );
AO22XLTS U2434 ( .A0(n2850), .A1(d_ff1_Z[9]), .B0(n2849), .B1(data_in[9]),
.Y(n1569) );
AO22XLTS U2435 ( .A0(n2850), .A1(d_ff1_Z[10]), .B0(n2849), .B1(data_in[10]),
.Y(n1570) );
AO22XLTS U2436 ( .A0(n2850), .A1(d_ff1_Z[11]), .B0(n2849), .B1(data_in[11]),
.Y(n1571) );
AO22XLTS U2437 ( .A0(n2850), .A1(d_ff1_Z[12]), .B0(n2849), .B1(data_in[12]),
.Y(n1572) );
AO22XLTS U2438 ( .A0(n2850), .A1(d_ff1_Z[13]), .B0(n2849), .B1(data_in[13]),
.Y(n1573) );
AO22XLTS U2439 ( .A0(n2850), .A1(d_ff1_Z[14]), .B0(n2849), .B1(data_in[14]),
.Y(n1574) );
AO22XLTS U2440 ( .A0(n2848), .A1(d_ff1_Z[15]), .B0(n2849), .B1(data_in[15]),
.Y(n1575) );
AO22XLTS U2441 ( .A0(n2848), .A1(d_ff1_Z[16]), .B0(n2847), .B1(data_in[16]),
.Y(n1576) );
AO22XLTS U2442 ( .A0(n2848), .A1(d_ff1_Z[17]), .B0(n2847), .B1(data_in[17]),
.Y(n1577) );
AO22XLTS U2443 ( .A0(n2848), .A1(d_ff1_Z[18]), .B0(n2847), .B1(data_in[18]),
.Y(n1578) );
AO22XLTS U2444 ( .A0(n2848), .A1(d_ff1_Z[19]), .B0(n2847), .B1(data_in[19]),
.Y(n1579) );
AO22XLTS U2445 ( .A0(n2848), .A1(d_ff1_Z[20]), .B0(n2847), .B1(data_in[20]),
.Y(n1580) );
AO22XLTS U2446 ( .A0(n2848), .A1(d_ff1_Z[21]), .B0(n2847), .B1(data_in[21]),
.Y(n1581) );
AO22XLTS U2447 ( .A0(n2848), .A1(d_ff1_Z[22]), .B0(n2847), .B1(data_in[22]),
.Y(n1582) );
AO22XLTS U2448 ( .A0(n2848), .A1(d_ff1_Z[23]), .B0(n2847), .B1(data_in[23]),
.Y(n1583) );
AO22XLTS U2449 ( .A0(n2848), .A1(d_ff1_Z[24]), .B0(n2847), .B1(data_in[24]),
.Y(n1584) );
AO22XLTS U2450 ( .A0(n2846), .A1(d_ff1_Z[25]), .B0(n2847), .B1(data_in[25]),
.Y(n1585) );
AO22XLTS U2451 ( .A0(n2846), .A1(d_ff1_Z[26]), .B0(n2845), .B1(data_in[26]),
.Y(n1586) );
AO22XLTS U2452 ( .A0(n2846), .A1(d_ff1_Z[27]), .B0(n2845), .B1(data_in[27]),
.Y(n1587) );
AO22XLTS U2453 ( .A0(n2846), .A1(d_ff1_Z[28]), .B0(n2845), .B1(data_in[28]),
.Y(n1588) );
AO22XLTS U2454 ( .A0(n2846), .A1(d_ff1_Z[29]), .B0(n2845), .B1(data_in[29]),
.Y(n1589) );
AO22XLTS U2455 ( .A0(n2846), .A1(d_ff1_Z[30]), .B0(n2845), .B1(data_in[30]),
.Y(n1590) );
AOI2BB2XLTS U2456 ( .B0(n2830), .B1(n2829), .A0N(n2829), .A1N(
cont_iter_out[2]), .Y(n1618) );
INVX2TS U2457 ( .A(n1642), .Y(n1691) );
CLKBUFX2TS U2458 ( .A(n1686), .Y(n2620) );
INVX2TS U2459 ( .A(n3228), .Y(n1659) );
NOR2X1TS U2460 ( .A(n2314), .B(n2948), .Y(n2327) );
OR2X2TS U2461 ( .A(n2317), .B(n2316), .Y(n1641) );
OR2X2TS U2462 ( .A(n2314), .B(n2316), .Y(n1642) );
NOR2X2TS U2463 ( .A(n2196), .B(n2979), .Y(n1646) );
OR2X1TS U2464 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n2545), .Y(n1648) );
OR3X1TS U2465 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n3067), .C(n3068), .Y(n1652) );
INVX2TS U2466 ( .A(n1659), .Y(n1661) );
INVX2TS U2467 ( .A(n2434), .Y(n1662) );
INVX2TS U2468 ( .A(n1692), .Y(n1663) );
INVX2TS U2469 ( .A(n1692), .Y(n1664) );
INVX4TS U2470 ( .A(n1665), .Y(n1667) );
INVX2TS U2471 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .Y(
n1668) );
INVX2TS U2472 ( .A(n2434), .Y(n1669) );
INVX2TS U2473 ( .A(n1669), .Y(n1670) );
INVX2TS U2474 ( .A(n1669), .Y(n1671) );
INVX4TS U2475 ( .A(n1672), .Y(n1673) );
INVX2TS U2476 ( .A(n1652), .Y(n1675) );
INVX2TS U2477 ( .A(n1652), .Y(n1676) );
INVX2TS U2478 ( .A(n1909), .Y(n1677) );
INVX2TS U2479 ( .A(n1909), .Y(n1678) );
INVX2TS U2480 ( .A(n1636), .Y(n1679) );
INVX2TS U2481 ( .A(n1636), .Y(n1680) );
INVX2TS U2482 ( .A(n1648), .Y(n1681) );
INVX2TS U2483 ( .A(n1648), .Y(n1682) );
INVX2TS U2484 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
n1683) );
INVX2TS U2485 ( .A(n1683), .Y(n1684) );
INVX2TS U2486 ( .A(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n1685)
);
INVX2TS U2487 ( .A(n1685), .Y(n1686) );
INVX4TS U2488 ( .A(n1642), .Y(n1689) );
OAI21X2TS U2489 ( .A0(n1634), .A1(n2377), .B0(n2366), .Y(n2397) );
OAI21X2TS U2490 ( .A0(n3171), .A1(n2377), .B0(n2376), .Y(n2411) );
OAI21X2TS U2491 ( .A0(n3107), .A1(n2423), .B0(n2352), .Y(n2436) );
OAI21X2TS U2492 ( .A0(n3138), .A1(n2423), .B0(n2405), .Y(n2431) );
OAI21X2TS U2493 ( .A0(n3091), .A1(n2423), .B0(n2422), .Y(n2439) );
OAI21X2TS U2494 ( .A0(n3092), .A1(n2423), .B0(n2363), .Y(n2393) );
OAI21X2TS U2495 ( .A0(n2423), .A1(n3106), .B0(n2328), .Y(n2418) );
OAI21XLTS U2496 ( .A0(n1684), .A1(n3090), .B0(n2267), .Y(n1049) );
OAI21XLTS U2497 ( .A0(n3083), .A1(n3013), .B0(n2474), .Y(n1152) );
CLKBUFX3TS U2498 ( .A(n1918), .Y(n1917) );
OAI31XLTS U2499 ( .A0(n2469), .A1(n3013), .A2(n2468), .B0(n2467), .Y(n1055)
);
AOI222X4TS U2500 ( .A0(n2897), .A1(d_ff2_Z[5]), .B0(n2102), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2122), .Y(n2116) );
AOI222X4TS U2501 ( .A0(n2914), .A1(d_ff2_Z[9]), .B0(n2108), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2122), .Y(n2121) );
AOI222X4TS U2502 ( .A0(n2871), .A1(d_ff2_Z[7]), .B0(n2108), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2122), .Y(n2120) );
AOI222X4TS U2503 ( .A0(n2135), .A1(d_ff2_Z[30]), .B0(n2134), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2133), .Y(n2125) );
AOI222X4TS U2504 ( .A0(n2135), .A1(d_ff2_Z[29]), .B0(n2134), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2133), .Y(n2131) );
AOI222X4TS U2505 ( .A0(n2135), .A1(d_ff2_Z[27]), .B0(n2134), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2133), .Y(n2126) );
OAI211XLTS U2506 ( .A0(n2031), .A1(n2489), .B0(n2239), .C0(n2238), .Y(n1376)
);
OAI33X4TS U2507 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n3133), .B0(n3085), .B1(n3070), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n2201) );
AOI211X1TS U2508 ( .A0(cont_iter_out[1]), .A1(n2196), .B0(n2830), .C0(n2834),
.Y(n2089) );
INVX2TS U2509 ( .A(n1651), .Y(n1696) );
NOR2XLTS U2510 ( .A(n2617), .B(n2616), .Y(n2619) );
AOI21X2TS U2511 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B0(n2543), .Y(n2616)
);
AOI21X2TS U2512 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n2543), .Y(n2609)
);
INVX2TS U2513 ( .A(n1650), .Y(n1697) );
NAND3X2TS U2514 ( .A(n2320), .B(n2319), .C(n2318), .Y(n2381) );
OAI21X2TS U2515 ( .A0(n2377), .A1(n3229), .B0(n1728), .Y(n2399) );
NAND2X4TS U2516 ( .A(n1668), .B(n1704), .Y(n2570) );
INVX2TS U2517 ( .A(n1635), .Y(n1698) );
NAND2BX2TS U2518 ( .AN(n1747), .B(n2947), .Y(n2948) );
NAND2X2TS U2519 ( .A(n1747), .B(n2947), .Y(n2316) );
AOI32X1TS U2520 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]),
.A1(n2947), .A2(n2824), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n2398), .Y(
n2180) );
NAND2X4TS U2521 ( .A(n3053), .B(n3066), .Y(n2947) );
AOI222X1TS U2522 ( .A0(n2285), .A1(data_output[23]), .B0(n2292), .B1(
d_ff_Yn[23]), .C0(n2291), .C1(d_ff_Xn[23]), .Y(n2269) );
AOI222X1TS U2523 ( .A0(n2285), .A1(data_output[20]), .B0(n2284), .B1(
d_ff_Yn[20]), .C0(n2291), .C1(d_ff_Xn[20]), .Y(n2270) );
AOI222X1TS U2524 ( .A0(n2285), .A1(data_output[19]), .B0(n2284), .B1(
d_ff_Yn[19]), .C0(n2287), .C1(d_ff_Xn[19]), .Y(n2283) );
AOI222X1TS U2525 ( .A0(n2285), .A1(data_output[21]), .B0(n2284), .B1(
d_ff_Yn[21]), .C0(n2291), .C1(d_ff_Xn[21]), .Y(n2268) );
AOI222X1TS U2526 ( .A0(n2285), .A1(data_output[18]), .B0(n2284), .B1(
d_ff_Yn[18]), .C0(n2287), .C1(d_ff_Xn[18]), .Y(n2278) );
AOI222X1TS U2527 ( .A0(n2285), .A1(data_output[15]), .B0(n2284), .B1(
d_ff_Yn[15]), .C0(n2287), .C1(d_ff_Xn[15]), .Y(n2256) );
AOI222X1TS U2528 ( .A0(n2216), .A1(data_output[22]), .B0(n2292), .B1(
d_ff_Yn[22]), .C0(n2291), .C1(d_ff_Xn[22]), .Y(n2293) );
AOI222X1TS U2529 ( .A0(n2254), .A1(data_output[30]), .B0(n2292), .B1(
d_ff_Yn[30]), .C0(n2206), .C1(d_ff_Xn[30]), .Y(n2207) );
AOI222X1TS U2530 ( .A0(n2254), .A1(data_output[29]), .B0(n2292), .B1(
d_ff_Yn[29]), .C0(n2291), .C1(d_ff_Xn[29]), .Y(n2271) );
AOI222X1TS U2531 ( .A0(n2254), .A1(data_output[26]), .B0(n2292), .B1(
d_ff_Yn[26]), .C0(n2291), .C1(d_ff_Xn[26]), .Y(n2276) );
AOI222X1TS U2532 ( .A0(n2254), .A1(data_output[25]), .B0(n2292), .B1(
d_ff_Yn[25]), .C0(n2291), .C1(d_ff_Xn[25]), .Y(n2274) );
AOI222X1TS U2533 ( .A0(n2254), .A1(data_output[24]), .B0(n2292), .B1(
d_ff_Yn[24]), .C0(n2291), .C1(d_ff_Xn[24]), .Y(n2273) );
AOI222X1TS U2534 ( .A0(n2289), .A1(data_output[4]), .B0(n2288), .B1(
d_ff_Yn[4]), .C0(n2206), .C1(d_ff_Xn[4]), .Y(n2214) );
AOI222X1TS U2535 ( .A0(n2285), .A1(data_output[17]), .B0(n2284), .B1(
d_ff_Yn[17]), .C0(n2287), .C1(d_ff_Xn[17]), .Y(n2282) );
AOI222X1TS U2536 ( .A0(n2285), .A1(data_output[13]), .B0(n2284), .B1(
d_ff_Yn[13]), .C0(n2287), .C1(d_ff_Xn[13]), .Y(n2279) );
AOI222X1TS U2537 ( .A0(n2289), .A1(data_output[6]), .B0(n2288), .B1(
d_ff_Yn[6]), .C0(n2199), .C1(d_ff_Xn[6]), .Y(n2220) );
AOI222X1TS U2538 ( .A0(n2289), .A1(data_output[8]), .B0(n2288), .B1(
d_ff_Yn[8]), .C0(n2206), .C1(d_ff_Xn[8]), .Y(n2213) );
AOI222X1TS U2539 ( .A0(n2285), .A1(data_output[16]), .B0(n2284), .B1(
d_ff_Yn[16]), .C0(n2287), .C1(d_ff_Xn[16]), .Y(n2286) );
AOI222X1TS U2540 ( .A0(n2289), .A1(data_output[11]), .B0(n2288), .B1(
d_ff_Yn[11]), .C0(n2287), .C1(d_ff_Xn[11]), .Y(n2277) );
AOI222X1TS U2541 ( .A0(n2285), .A1(data_output[14]), .B0(n2284), .B1(
d_ff_Yn[14]), .C0(n2287), .C1(d_ff_Xn[14]), .Y(n2281) );
AOI222X1TS U2542 ( .A0(n2289), .A1(data_output[12]), .B0(n2284), .B1(
d_ff_Yn[12]), .C0(n2287), .C1(d_ff_Xn[12]), .Y(n2280) );
AOI222X1TS U2543 ( .A0(n2289), .A1(data_output[10]), .B0(n2288), .B1(
d_ff_Yn[10]), .C0(n2287), .C1(d_ff_Xn[10]), .Y(n2290) );
AOI222X1TS U2544 ( .A0(n2216), .A1(data_output[2]), .B0(n2288), .B1(
d_ff_Yn[2]), .C0(n2206), .C1(d_ff_Xn[2]), .Y(n2215) );
AOI222X1TS U2545 ( .A0(n2289), .A1(data_output[3]), .B0(n2288), .B1(
d_ff_Yn[3]), .C0(n2199), .C1(d_ff_Xn[3]), .Y(n2221) );
AOI222X1TS U2546 ( .A0(n2254), .A1(data_output[0]), .B0(n2255), .B1(
d_ff_Yn[0]), .C0(n2206), .C1(d_ff_Xn[0]), .Y(n2212) );
AOI222X1TS U2547 ( .A0(n2289), .A1(data_output[7]), .B0(n2288), .B1(
d_ff_Yn[7]), .C0(n2206), .C1(d_ff_Xn[7]), .Y(n2218) );
AOI222X1TS U2548 ( .A0(n2289), .A1(data_output[9]), .B0(n2288), .B1(
d_ff_Yn[9]), .C0(n2206), .C1(d_ff_Xn[9]), .Y(n2211) );
AOI222X1TS U2549 ( .A0(n2216), .A1(data_output[1]), .B0(n2255), .B1(
d_ff_Yn[1]), .C0(n2206), .C1(d_ff_Xn[1]), .Y(n2217) );
CLKBUFX3TS U2550 ( .A(n2084), .Y(n1920) );
AOI222X1TS U2551 ( .A0(n2289), .A1(data_output[5]), .B0(n2288), .B1(
d_ff_Yn[5]), .C0(n2206), .C1(d_ff_Xn[5]), .Y(n2219) );
AOI222X1TS U2552 ( .A0(n2254), .A1(data_output[27]), .B0(n2292), .B1(
d_ff_Yn[27]), .C0(n2291), .C1(d_ff_Xn[27]), .Y(n2275) );
OR2X1TS U2553 ( .A(n3162), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .Y(
n1855) );
OR2X1TS U2554 ( .A(n3161), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .Y(
n1859) );
OR2X1TS U2555 ( .A(n3160), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .Y(
n1863) );
OR2X1TS U2556 ( .A(n3159), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .Y(
n1867) );
OAI222X1TS U2557 ( .A0(n3011), .A1(n3086), .B0(n1706), .B1(n3012), .C0(n3118), .C1(n3013), .Y(n1156) );
OAI21X1TS U2558 ( .A0(n2545), .A1(n3130), .B0(n2550), .Y(n2540) );
OAI21XLTS U2559 ( .A0(n3115), .A1(n2463), .B0(n2461), .Y(n1082) );
OAI21XLTS U2560 ( .A0(n3079), .A1(n2463), .B0(n2462), .Y(n1094) );
OAI21XLTS U2561 ( .A0(n2545), .A1(n3131), .B0(n2550), .Y(n2536) );
CLKBUFX3TS U2562 ( .A(n1920), .Y(n3227) );
OR2X1TS U2563 ( .A(d_ff2_Y[23]), .B(n2827), .Y(intadd_42_CI) );
AOI221X1TS U2564 ( .A0(n3118), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .B1(n3117), .C0(n1995),
.Y(n1999) );
AOI221X1TS U2565 ( .A0(n1655), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n1640), .C0(n2018), .Y(
n2023) );
AOI221X1TS U2566 ( .A0(n2494), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B1(n3125), .C0(n2002),
.Y(n2007) );
AOI221X1TS U2567 ( .A0(n3124), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2229), .C0(n2001),
.Y(n2008) );
NOR2X1TS U2568 ( .A(n2229), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]),
.Y(n1759) );
AOI221X1TS U2569 ( .A0(n2489), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(n2491), .C0(n2012),
.Y(n2013) );
AOI221X1TS U2570 ( .A0(n3122), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(n2233), .C0(n2009), .Y(
n2016) );
AOI32X1TS U2571 ( .A0(n2225), .A1(n1805), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n2451), .Y(n1806) );
AOI221X1TS U2572 ( .A0(n2451), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(n3110), .C0(n2004),
.Y(n2005) );
AOI221X1TS U2573 ( .A0(n2223), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(n3119), .C0(n2011),
.Y(n2014) );
OAI2BB2XLTS U2574 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(
n1772), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1N(n3121),
.Y(n1774) );
AOI221X1TS U2575 ( .A0(n2482), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .B1(n3111), .C0(n2017), .Y(
n2024) );
AOI221X1TS U2576 ( .A0(n2227), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B1(n2225), .C0(n2003),
.Y(n2006) );
OAI21X2TS U2577 ( .A0(n1934), .A1(n1840), .B0(n1839), .Y(n2731) );
NOR3X1TS U2578 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.Y(n1897) );
OAI211XLTS U2579 ( .A0(n2196), .A1(n2836), .B0(n2185), .C0(n2184), .Y(n1600)
);
OAI21XLTS U2580 ( .A0(n2195), .A1(n2190), .B0(n2087), .Y(n1609) );
CLKBUFX3TS U2581 ( .A(n1915), .Y(n1916) );
OAI211XLTS U2582 ( .A0(n2031), .A1(n2491), .B0(n2237), .C0(n2244), .Y(n1373)
);
NOR4BX2TS U2583 ( .AN(n2143), .B(n2147), .C(n2142), .D(n2141), .Y(n2146) );
INVX2TS U2584 ( .A(n1701), .Y(n1702) );
OAI21XLTS U2585 ( .A0(n3054), .A1(n3094), .B0(n2423), .Y(n1043) );
AOI211X2TS U2586 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B0(n2531), .C0(n2525), .Y(n2588) );
NOR2X2TS U2587 ( .A(n3067), .B(n2550), .Y(n2531) );
AOI21X2TS U2588 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n2547), .B0(n2540), .Y(n2598) );
AOI21X1TS U2589 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n2543), .Y(n1703)
);
OAI21XLTS U2590 ( .A0(n1941), .A1(n1940), .B0(n1939), .Y(n1943) );
NOR2XLTS U2591 ( .A(n1940), .B(n1935), .Y(n1874) );
NOR2X2TS U2592 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1940) );
OR2X1TS U2593 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n2737) );
NOR2XLTS U2594 ( .A(n3157), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1828) );
NOR2X2TS U2595 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1974) );
NOR2X2TS U2596 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n2798) );
OAI32X1TS U2597 ( .A0(n2829), .A1(n2826), .A2(n2827), .B0(n3098), .B1(n2829),
.Y(n1619) );
NOR3X4TS U2598 ( .A(n2826), .B(n3098), .C(n2827), .Y(n2829) );
AOI222X1TS U2599 ( .A0(n2254), .A1(data_output[28]), .B0(n2292), .B1(
d_ff_Yn[28]), .C0(n2291), .C1(d_ff_Xn[28]), .Y(n2272) );
OAI222X1TS U2600 ( .A0(n3011), .A1(n3134), .B0(n3084), .B1(n3012), .C0(n3069), .C1(n3013), .Y(n1157) );
NAND2X1TS U2601 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B(
n1725), .Y(n2153) );
OAI21X2TS U2602 ( .A0(n3102), .A1(n2423), .B0(n2336), .Y(n2383) );
OAI21X2TS U2603 ( .A0(n3073), .A1(n2377), .B0(n2326), .Y(n2388) );
OAI21X2TS U2604 ( .A0(n3074), .A1(n2423), .B0(n2362), .Y(n2413) );
INVX2TS U2605 ( .A(n2620), .Y(n1704) );
INVX2TS U2606 ( .A(n2620), .Y(n1705) );
XNOR2X2TS U2607 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n2468) );
BUFX3TS U2608 ( .A(n2084), .Y(n1919) );
NOR2X4TS U2609 ( .A(n2828), .B(rst), .Y(n2084) );
OR2X1TS U2610 ( .A(d_ff2_X[23]), .B(n2827), .Y(intadd_43_CI) );
OAI21X1TS U2611 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n1736), .Y(n1737) );
AOI22X1TS U2612 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2809), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(
n3266), .Y(n2819) );
AOI222X1TS U2613 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n3071), .B0(n1777), .B1(n1776), .C0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C1(
n3126), .Y(n1779) );
OAI211XLTS U2614 ( .A0(n2442), .A1(n1670), .B0(n2420), .C0(n2419), .Y(n1313)
);
AOI21X2TS U2615 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n2553), .B0(n2552), .Y(n2603) );
OAI31X1TS U2616 ( .A0(n2832), .A1(cont_var_out[1]), .A2(n3097), .B0(n2516),
.Y(n1615) );
OAI21XLTS U2617 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n3112),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n1775) );
NOR2X1TS U2618 ( .A(n2227), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]),
.Y(n1803) );
NOR2X1TS U2619 ( .A(n2223), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]),
.Y(n1783) );
OAI21XLTS U2620 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n3124), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n1802) );
OAI21XLTS U2621 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n3114), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n1782) );
OA22X1TS U2622 ( .A0(n3078), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]),
.B0(n3111), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n1796)
);
OA22X1TS U2623 ( .A0(n2233), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]),
.B0(n3125), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n1814)
);
OR2X1TS U2624 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1708) );
OR2X1TS U2625 ( .A(n1707), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n1710) );
AND2X2TS U2626 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
n2263), .Y(n1711) );
CLKBUFX2TS U2627 ( .A(n2889), .Y(n2894) );
BUFX3TS U2628 ( .A(n2032), .Y(n2889) );
CLKBUFX2TS U2629 ( .A(n2243), .Y(n2066) );
BUFX3TS U2630 ( .A(n2030), .Y(n2243) );
BUFX3TS U2631 ( .A(n2031), .Y(n2983) );
NOR2XLTS U2632 ( .A(n1803), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]),
.Y(n1804) );
OAI21XLTS U2633 ( .A0(n2792), .A1(n2797), .B0(n2793), .Y(n1875) );
INVX2TS U2634 ( .A(n2624), .Y(n2626) );
OR2X1TS U2635 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n2683) );
OR2X1TS U2636 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n2635) );
OAI21XLTS U2637 ( .A0(n2545), .A1(n3128), .B0(n2550), .Y(n2546) );
NAND2X1TS U2638 ( .A(n2732), .B(n1710), .Y(n2778) );
NOR2BX1TS U2639 ( .AN(n2260), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n2261) );
INVX2TS U2640 ( .A(n2317), .Y(n2314) );
OAI21XLTS U2641 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .A1(
n1706), .B0(n2992), .Y(n2993) );
OAI21XLTS U2642 ( .A0(n2796), .A1(n2735), .B0(n2734), .Y(n2739) );
XOR2X1TS U2643 ( .A(n1893), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1889) );
OAI21XLTS U2644 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .A1(
n3129), .B0(n3000), .Y(n3001) );
INVX2TS U2645 ( .A(n3014), .Y(n2303) );
BUFX3TS U2646 ( .A(n2983), .Y(n2253) );
BUFX3TS U2647 ( .A(n2330), .Y(n2824) );
INVX2TS U2648 ( .A(n1730), .Y(n1715) );
NOR2X2TS U2649 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1734) );
NOR2X2TS U2650 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n1731) );
AND2X4TS U2651 ( .A(n1734), .B(n1731), .Y(n2139) );
NAND2X4TS U2652 ( .A(n2139), .B(n2138), .Y(n1722) );
OR2X8TS U2653 ( .A(n1722), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n2150) );
NOR2BX4TS U2654 ( .AN(n2151), .B(n2150), .Y(n1740) );
NOR2X8TS U2655 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
n2137), .Y(n2157) );
INVX6TS U2656 ( .A(n2157), .Y(n1735) );
NOR3BX4TS U2657 ( .AN(n1725), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2172) );
NAND2X1TS U2658 ( .A(n3096), .B(n3074), .Y(n2171) );
NOR2BX4TS U2659 ( .AN(n2172), .B(n2171), .Y(n1736) );
NOR2BX4TS U2660 ( .AN(n1736), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n2173) );
AOI21X1TS U2661 ( .A0(n3109), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n1716) );
AOI211X1TS U2662 ( .A0(n2173), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n1721), .C0(
n1720), .Y(n1727) );
OAI22X1TS U2663 ( .A0(n2153), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n3106), .B1(
n1722), .Y(n1738) );
AOI32X1TS U2664 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(
n1634), .A2(n1645), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n1634), .Y(n1723) );
AOI211X2TS U2665 ( .A0(n3102), .A1(n1723), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .C0(n2140), .Y(n1724) );
AOI211X2TS U2666 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n2157), .B0(n1738), .C0(n1724), .Y(n2143) );
BUFX3TS U2667 ( .A(n2330), .Y(n2821) );
BUFX3TS U2668 ( .A(n2330), .Y(n2357) );
NOR2X1TS U2669 ( .A(n2357), .B(n3108), .Y(n2329) );
INVX2TS U2670 ( .A(n2329), .Y(n1729) );
INVX2TS U2671 ( .A(n1729), .Y(n2406) );
AOI211X4TS U2672 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]),
.A1(n2824), .B0(n2808), .C0(n2406), .Y(n2317) );
BUFX3TS U2673 ( .A(n2315), .Y(n2377) );
AOI21X1TS U2674 ( .A0(n2377), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n2824), .Y(
n1728) );
INVX2TS U2675 ( .A(n1729), .Y(n2417) );
AOI21X1TS U2676 ( .A0(n2317), .A1(n2399), .B0(n2417), .Y(n2949) );
BUFX3TS U2677 ( .A(n2330), .Y(n3053) );
INVX2TS U2678 ( .A(n2315), .Y(n2404) );
AOI21X1TS U2679 ( .A0(n1730), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n1732) );
OAI31X1TS U2680 ( .A0(n1732), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n1731), .Y(
n1733) );
INVX2TS U2681 ( .A(n1733), .Y(n1743) );
NAND3X4TS U2682 ( .A(n2178), .B(n3073), .C(n3102), .Y(n2174) );
OAI21X4TS U2683 ( .A0(n2152), .A1(n2174), .B0(n1737), .Y(n2177) );
NAND2X1TS U2684 ( .A(n1740), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n2149) );
AO22X4TS U2685 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]),
.A1(n3053), .B0(n2404), .B1(n2517), .Y(n1747) );
BUFX3TS U2686 ( .A(n1660), .Y(n3066) );
NAND2X1TS U2687 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1746) );
NAND2X1TS U2688 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n1745) );
NAND2X1TS U2689 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1744) );
NAND3X1TS U2690 ( .A(n1746), .B(n1745), .C(n1744), .Y(n2371) );
INVX2TS U2691 ( .A(n2371), .Y(n2403) );
NAND2X1TS U2692 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n1750) );
NAND2X1TS U2693 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n1749) );
NAND2X1TS U2694 ( .A(n3053), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1748) );
NAND3X1TS U2695 ( .A(n1750), .B(n1749), .C(n1748), .Y(n2400) );
INVX2TS U2696 ( .A(n2400), .Y(n2305) );
NOR2X2TS U2697 ( .A(n2948), .B(n2317), .Y(n1751) );
OAI22X1TS U2698 ( .A0(n2403), .A1(n1670), .B0(n2305), .B1(n1666), .Y(n1752)
);
AOI21X1TS U2699 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n1752), .Y(n1753)
);
OAI21X2TS U2700 ( .A0(n2949), .A1(n2316), .B0(n1753), .Y(n1321) );
NOR2X1TS U2701 ( .A(n3118), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]),
.Y(n1817) );
AOI22X1TS U2702 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n3118), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n1754), .Y(n1758) );
OAI21X1TS U2703 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n3117), .B0(n1755), .Y(n1818) );
OAI211X1TS U2704 ( .A0(n1758), .A1(n1818), .B0(n1757), .C0(n1756), .Y(n1763)
);
NOR2X1TS U2705 ( .A(n3140), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]),
.Y(n1761) );
INVX2TS U2706 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(n2229) );
NOR3X1TS U2707 ( .A(n3100), .B(n1759), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n1760) );
AOI221X1TS U2708 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(
n3140), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2229),
.C0(n1760), .Y(n1762) );
INVX2TS U2709 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n2233) );
INVX2TS U2710 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .Y(n2225) );
OAI21X1TS U2711 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2225), .B0(n1805), .Y(n1809) );
AOI211X1TS U2712 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(
n3099), .B0(n1808), .C0(n1809), .Y(n1765) );
INVX2TS U2713 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .Y(n2227) );
INVX2TS U2714 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .Y(n2223) );
AOI21X1TS U2715 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n3093), .B0(n1783), .Y(n1788) );
OAI2BB1X1TS U2716 ( .A0N(n3126), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n1770) );
OAI22X1TS U2717 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1770),
.B0(n3126), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n1781)
);
OAI2BB1X1TS U2718 ( .A0N(n3095), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .Y(n1771) );
OAI22X1TS U2719 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n1771),
.B0(n3095), .B1(n1700), .Y(n1780) );
OAI211X1TS U2720 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(n1774), .C0(n1773), .Y(n1777) );
AOI22X1TS U2721 ( .A0(n1700), .A1(n3095), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n3076), .Y(n1778) );
AOI22X1TS U2722 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2223), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1784), .Y(n1791) );
AOI21X1TS U2723 ( .A0(n1787), .A1(n1786), .B0(n1790), .Y(n1789) );
OAI2BB2XLTS U2724 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B1(
n1802), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1N(n3124),
.Y(n1813) );
AOI22X1TS U2725 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2227), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n1804), .Y(n1807) );
INVX2TS U2726 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n2451) );
OAI32X1TS U2727 ( .A0(n1809), .A1(n1808), .A2(n1807), .B0(n1806), .B1(n1808),
.Y(n1812) );
OAI2BB2XLTS U2728 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B1(
n1810), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1N(n3125),
.Y(n1811) );
AOI211X1TS U2729 ( .A0(n1814), .A1(n1813), .B0(n1812), .C0(n1811), .Y(n1820)
);
NAND4BBX1TS U2730 ( .AN(n1818), .BN(n1817), .C(n1816), .D(n1815), .Y(n1819)
);
BUFX3TS U2731 ( .A(n2306), .Y(n3039) );
NOR2X4TS U2732 ( .A(n1824), .B(n3039), .Y(n1823) );
CLKBUFX2TS U2733 ( .A(n2306), .Y(n2447) );
BUFX3TS U2734 ( .A(n2447), .Y(n2820) );
AOI22X1TS U2735 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B1(n2820), .Y(n1826) );
BUFX3TS U2736 ( .A(n2702), .Y(n2701) );
NAND2X1TS U2737 ( .A(n3089), .B(n2767), .Y(n2773) );
NAND2X1TS U2738 ( .A(n3157), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1827) );
NOR2X1TS U2739 ( .A(n3156), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1925) );
NAND2X1TS U2740 ( .A(n3145), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1829) );
NOR2X1TS U2741 ( .A(n3155), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1948) );
NOR2X1TS U2742 ( .A(n3144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1834) );
NOR2X1TS U2743 ( .A(n1948), .B(n1834), .Y(n1961) );
NOR2X1TS U2744 ( .A(n3154), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1964) );
NOR2X1TS U2745 ( .A(n3143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1836) );
NOR2X1TS U2746 ( .A(n1964), .B(n1836), .Y(n1838) );
NAND2X1TS U2747 ( .A(n1961), .B(n1838), .Y(n1840) );
NAND2X1TS U2748 ( .A(n3155), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1949) );
NAND2X1TS U2749 ( .A(n3144), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1833) );
OAI21X1TS U2750 ( .A0(n1834), .A1(n1949), .B0(n1833), .Y(n1960) );
NAND2X1TS U2751 ( .A(n3154), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1963) );
NAND2X1TS U2752 ( .A(n3143), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1835) );
AOI21X1TS U2753 ( .A0(n1960), .A1(n1838), .B0(n1837), .Y(n1839) );
NOR2X1TS U2754 ( .A(n3153), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n2749) );
NOR2X1TS U2755 ( .A(n3152), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .Y(
n1845) );
NOR2X2TS U2756 ( .A(n2778), .B(n1845), .Y(n1847) );
NAND2X1TS U2757 ( .A(n1644), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1841) );
NAND2X1TS U2758 ( .A(n3152), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.Y(n1844) );
OAI21X1TS U2759 ( .A0(n2777), .A1(n1845), .B0(n1844), .Y(n1846) );
NAND2X1TS U2760 ( .A(n3151), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.Y(n1848) );
NAND2X1TS U2761 ( .A(n3150), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.Y(n1852) );
NAND2X1TS U2762 ( .A(n3149), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]),
.Y(n1856) );
NAND2X1TS U2763 ( .A(n3148), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]),
.Y(n1860) );
NAND2X1TS U2764 ( .A(n3147), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]),
.Y(n1864) );
NAND2X1TS U2765 ( .A(n3146), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]),
.Y(n1868) );
OR2X1TS U2766 ( .A(n3158), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .Y(
n1871) );
CLKAND2X2TS U2767 ( .A(n3158), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]),
.Y(n1870) );
NOR2X1TS U2768 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n2758) );
NAND2X1TS U2769 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2771) );
NAND2X1TS U2770 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n2759) );
OAI21X1TS U2771 ( .A0(n2758), .A1(n2771), .B0(n2759), .Y(n1929) );
NOR2X2TS U2772 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1935) );
NAND2X1TS U2773 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1939) );
NAND2X1TS U2774 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1936) );
OAI21X1TS U2775 ( .A0(n1935), .A1(n1939), .B0(n1936), .Y(n1873) );
NOR2X1TS U2776 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1952) );
NOR2X1TS U2777 ( .A(n1952), .B(n1974), .Y(n1969) );
NOR2X2TS U2778 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2792) );
NOR2X1TS U2779 ( .A(n2798), .B(n2792), .Y(n1876) );
NAND2X1TS U2780 ( .A(n1969), .B(n1876), .Y(n1878) );
NAND2X1TS U2781 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1979) );
NAND2X1TS U2782 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1975) );
OAI21X1TS U2783 ( .A0(n1974), .A1(n1979), .B0(n1975), .Y(n1968) );
NAND2X1TS U2784 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n2797) );
NAND2X1TS U2785 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2793) );
AOI21X1TS U2786 ( .A0(n1968), .A1(n1876), .B0(n1875), .Y(n1877) );
NOR2X1TS U2787 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n2741) );
INVX2TS U2788 ( .A(n2741), .Y(n2751) );
NAND2X1TS U2789 ( .A(n2751), .B(n2737), .Y(n2785) );
NOR2X2TS U2790 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n2779) );
NOR2X1TS U2791 ( .A(n2785), .B(n2779), .Y(n1882) );
NAND2X1TS U2792 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n2750) );
INVX2TS U2793 ( .A(n2750), .Y(n1880) );
NAND2X1TS U2794 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n2736) );
INVX2TS U2795 ( .A(n2736), .Y(n1879) );
AOI21X1TS U2796 ( .A0(n2737), .A1(n1880), .B0(n1879), .Y(n2784) );
NAND2X1TS U2797 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n2780) );
OAI21X1TS U2798 ( .A0(n2784), .A1(n2779), .B0(n2780), .Y(n1881) );
AOI21X2TS U2799 ( .A0(n2740), .A1(n1882), .B0(n1881), .Y(n2727) );
NOR2X1TS U2800 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n2721) );
NAND2X1TS U2801 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n2722) );
NAND2X1TS U2802 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n2712) );
INVX2TS U2803 ( .A(n2712), .Y(n1883) );
NOR2X1TS U2804 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2624) );
NAND2X1TS U2805 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2625) );
NAND2X1TS U2806 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n2634) );
INVX2TS U2807 ( .A(n2634), .Y(n1884) );
NOR2X1TS U2808 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n2643) );
NAND2X1TS U2809 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n2644) );
NAND2X1TS U2810 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2703) );
INVX2TS U2811 ( .A(n2703), .Y(n1885) );
NOR2X1TS U2812 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n2672) );
NAND2X1TS U2813 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n2673) );
NAND2X1TS U2814 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n2682) );
INVX2TS U2815 ( .A(n2682), .Y(n1886) );
NOR2X1TS U2816 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2691) );
NAND2X1TS U2817 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2692) );
NAND2X1TS U2818 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2663) );
INVX2TS U2819 ( .A(n2663), .Y(n1887) );
NOR2X1TS U2820 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n2653) );
NAND2X1TS U2821 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n2654) );
NAND2X1TS U2822 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1899) );
INVX2TS U2823 ( .A(n1899), .Y(n1888) );
INVX2TS U2824 ( .A(n1674), .Y(n3008) );
BUFX3TS U2825 ( .A(n3008), .Y(n2802) );
BUFX3TS U2826 ( .A(n3008), .Y(n2822) );
BUFX3TS U2827 ( .A(n2447), .Y(n2502) );
AOI22X1TS U2828 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B1(n2502), .Y(n1892) );
NAND2X1TS U2829 ( .A(n1893), .B(n3164), .Y(n1894) );
NOR3X2TS U2830 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n1896) );
NOR3BX1TS U2831 ( .AN(n1896), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1895) );
NAND2X1TS U2832 ( .A(cont_var_out[1]), .B(n3097), .Y(n2029) );
OR2X2TS U2833 ( .A(n2029), .B(n3267), .Y(n2863) );
BUFX3TS U2834 ( .A(n2863), .Y(n2862) );
NOR4X2TS U2835 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1913) );
NAND3X1TS U2836 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1913), .C(n1896),
.Y(n2816) );
INVX2TS U2837 ( .A(n2816), .Y(ready_cordic) );
NAND2X1TS U2838 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n2812) );
NOR4BX2TS U2839 ( .AN(n1896), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[5]), .D(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2164) );
NAND3X2TS U2840 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(n2164), .C(n3101),
.Y(n2813) );
AND4X2TS U2841 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(n1897), .C(n1896),
.D(n3075), .Y(n2869) );
INVX2TS U2842 ( .A(n2869), .Y(n2840) );
NAND2X1TS U2843 ( .A(n1900), .B(n1899), .Y(n1903) );
INVX2TS U2844 ( .A(n1903), .Y(n1901) );
XNOR2X1TS U2845 ( .A(n1902), .B(n1901), .Y(n1907) );
XNOR2X1TS U2846 ( .A(n1904), .B(n1903), .Y(n1905) );
AOI22X1TS U2847 ( .A0(n1905), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n2822), .Y(
n1906) );
OAI2BB1X1TS U2848 ( .A0N(n2701), .A1N(n1907), .B0(n1906), .Y(n1008) );
NAND3X1TS U2849 ( .A(n3075), .B(n1913), .C(n3104), .Y(n2165) );
NOR3BX2TS U2850 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n2165), .Y(n2091) );
BUFX3TS U2851 ( .A(n2091), .Y(n2915) );
NOR2X2TS U2852 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n1643), .Y(n2809) );
NAND2X2TS U2853 ( .A(n2814), .B(n2813), .Y(n2167) );
AOI22X1TS U2854 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n3132), .B0(n2167), .B1(n3266), .Y(n1908) );
OAI21XLTS U2855 ( .A0(n2809), .A1(n1908), .B0(n2817), .Y(n1628) );
NOR2X2TS U2856 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(n3067), .Y(n2547) );
INVX2TS U2857 ( .A(n2547), .Y(n2551) );
NOR2X4TS U2858 ( .A(n1668), .B(n1649), .Y(n2590) );
NAND2X2TS U2859 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n2550) );
NOR2X1TS U2860 ( .A(n2590), .B(n2531), .Y(n2578) );
NAND2X2TS U2861 ( .A(n3067), .B(n3068), .Y(n2545) );
AOI22X1TS U2862 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B1(n1682), .Y(n1910) );
OAI211X1TS U2863 ( .A0(n3130), .A1(n1909), .B0(n2578), .C0(n1910), .Y(n2573)
);
AOI21X1TS U2864 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1678), .B0(n2590), .Y(n1912) );
AOI22X1TS U2865 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n1682), .Y(n1911) );
OAI211X1TS U2866 ( .A0(n3131), .A1(n1636), .B0(n1912), .C0(n1911), .Y(n2574)
);
AOI22X1TS U2867 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2573), .B0(n2574), .B1(n1704), .Y(n3031) );
INVX2TS U2868 ( .A(n2524), .Y(n2612) );
BUFX3TS U2869 ( .A(n2612), .Y(n2585) );
MXI2X1TS U2870 ( .A(n3031), .B(n1644), .S0(n2585), .Y(n881) );
INVX2TS U2871 ( .A(rst), .Y(n1172) );
CLKBUFX2TS U2872 ( .A(n1172), .Y(n1918) );
BUFX3TS U2873 ( .A(n1918), .Y(n3250) );
NAND2X1TS U2874 ( .A(n3075), .B(n1913), .Y(n1914) );
NOR4X4TS U2875 ( .A(n1914), .B(inst_CORDIC_FSM_v3_state_reg[2]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .D(n3104), .Y(n2828) );
CLKBUFX3TS U2876 ( .A(n2084), .Y(n1921) );
BUFX3TS U2877 ( .A(n1919), .Y(n3199) );
BUFX3TS U2878 ( .A(n3203), .Y(n3198) );
BUFX3TS U2879 ( .A(n3202), .Y(n3214) );
BUFX3TS U2880 ( .A(n3204), .Y(n3197) );
BUFX3TS U2881 ( .A(n1917), .Y(n3249) );
BUFX3TS U2882 ( .A(n3208), .Y(n3201) );
BUFX3TS U2883 ( .A(n3208), .Y(n3216) );
CLKBUFX2TS U2884 ( .A(n1172), .Y(n1915) );
BUFX3TS U2885 ( .A(n1915), .Y(n3238) );
BUFX3TS U2886 ( .A(n1918), .Y(n3245) );
BUFX3TS U2887 ( .A(n1916), .Y(n3239) );
BUFX3TS U2888 ( .A(n1916), .Y(n3240) );
BUFX3TS U2889 ( .A(n1917), .Y(n3244) );
BUFX3TS U2890 ( .A(n1915), .Y(n3241) );
BUFX3TS U2891 ( .A(n1918), .Y(n3243) );
BUFX3TS U2892 ( .A(n1918), .Y(n3242) );
BUFX3TS U2893 ( .A(n1917), .Y(n3248) );
BUFX3TS U2894 ( .A(n1917), .Y(n3247) );
BUFX3TS U2895 ( .A(n1917), .Y(n3246) );
BUFX3TS U2896 ( .A(n1919), .Y(n3210) );
BUFX3TS U2897 ( .A(n1915), .Y(n3230) );
BUFX3TS U2898 ( .A(n1915), .Y(n3231) );
BUFX3TS U2899 ( .A(n1916), .Y(n3232) );
BUFX3TS U2900 ( .A(n1915), .Y(n3233) );
BUFX3TS U2901 ( .A(n1921), .Y(n3211) );
BUFX3TS U2902 ( .A(n1916), .Y(n3234) );
BUFX3TS U2903 ( .A(n1916), .Y(n3235) );
BUFX3TS U2904 ( .A(n1916), .Y(n3236) );
BUFX3TS U2905 ( .A(n1916), .Y(n3237) );
BUFX3TS U2906 ( .A(n3203), .Y(n3226) );
BUFX3TS U2907 ( .A(n1917), .Y(n3251) );
BUFX3TS U2908 ( .A(n1917), .Y(n3252) );
BUFX3TS U2909 ( .A(n1916), .Y(n3264) );
BUFX3TS U2910 ( .A(n3264), .Y(n3258) );
BUFX3TS U2911 ( .A(n3204), .Y(n3212) );
BUFX3TS U2912 ( .A(n1918), .Y(n3253) );
BUFX3TS U2913 ( .A(n3203), .Y(n3217) );
BUFX3TS U2914 ( .A(n3208), .Y(n3213) );
BUFX3TS U2915 ( .A(n3208), .Y(n3218) );
BUFX3TS U2916 ( .A(n1917), .Y(n3265) );
BUFX3TS U2917 ( .A(n3265), .Y(n3261) );
BUFX3TS U2918 ( .A(n3264), .Y(n3259) );
BUFX3TS U2919 ( .A(n3265), .Y(n3260) );
BUFX3TS U2920 ( .A(n1172), .Y(n3254) );
BUFX3TS U2921 ( .A(n1920), .Y(n3205) );
BUFX3TS U2922 ( .A(n3203), .Y(n3220) );
BUFX3TS U2923 ( .A(n1919), .Y(n3219) );
BUFX3TS U2924 ( .A(n3203), .Y(n3206) );
BUFX3TS U2925 ( .A(n1919), .Y(n3194) );
BUFX3TS U2926 ( .A(n1921), .Y(n3222) );
BUFX3TS U2927 ( .A(n3264), .Y(n3255) );
BUFX3TS U2928 ( .A(n3265), .Y(n3263) );
BUFX3TS U2929 ( .A(n3202), .Y(n3215) );
BUFX3TS U2930 ( .A(n1921), .Y(n3195) );
BUFX3TS U2931 ( .A(n3202), .Y(n3223) );
BUFX3TS U2932 ( .A(n3264), .Y(n3257) );
BUFX3TS U2933 ( .A(n3204), .Y(n3225) );
BUFX3TS U2934 ( .A(n3202), .Y(n3221) );
BUFX3TS U2935 ( .A(n1920), .Y(n3188) );
BUFX3TS U2936 ( .A(n3208), .Y(n3224) );
BUFX3TS U2937 ( .A(n3204), .Y(n3209) );
BUFX3TS U2938 ( .A(n1920), .Y(n3189) );
BUFX3TS U2939 ( .A(n1920), .Y(n3191) );
BUFX3TS U2940 ( .A(n1920), .Y(n3186) );
BUFX3TS U2941 ( .A(n3264), .Y(n3256) );
BUFX3TS U2942 ( .A(n3265), .Y(n3262) );
BUFX3TS U2943 ( .A(n1920), .Y(n3190) );
BUFX3TS U2944 ( .A(n1920), .Y(n3187) );
INVX2TS U2945 ( .A(n3170), .Y(n1922) );
INVX2TS U2946 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .Y(
n3057) );
BUFX3TS U2947 ( .A(n3057), .Y(n3051) );
BUFX3TS U2948 ( .A(n3057), .Y(n3040) );
CLKBUFX2TS U2949 ( .A(n3057), .Y(n3064) );
INVX2TS U2950 ( .A(n3064), .Y(n3065) );
BUFX3TS U2951 ( .A(n2524), .Y(n2523) );
BUFX3TS U2952 ( .A(n2524), .Y(n3037) );
INVX2TS U2953 ( .A(n1923), .Y(n2762) );
INVX2TS U2954 ( .A(n1940), .Y(n1926) );
NAND2X1TS U2955 ( .A(n1926), .B(n1939), .Y(n1930) );
INVX2TS U2956 ( .A(n1930), .Y(n1927) );
XNOR2X1TS U2957 ( .A(n1928), .B(n1927), .Y(n1933) );
INVX2TS U2958 ( .A(n1929), .Y(n1941) );
XOR2X1TS U2959 ( .A(n1941), .B(n1930), .Y(n1931) );
BUFX3TS U2960 ( .A(n1944), .Y(n2803) );
AOI22X1TS U2961 ( .A0(n1931), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n2802), .Y(n1932) );
OAI2BB1X1TS U2962 ( .A0N(n2702), .A1N(n1933), .B0(n1932), .Y(n1038) );
INVX2TS U2963 ( .A(n1934), .Y(n1962) );
INVX2TS U2964 ( .A(n1935), .Y(n1937) );
NAND2X1TS U2965 ( .A(n1937), .B(n1936), .Y(n1942) );
INVX2TS U2966 ( .A(n1942), .Y(n1938) );
XNOR2X1TS U2967 ( .A(n1962), .B(n1938), .Y(n1947) );
XNOR2X1TS U2968 ( .A(n1943), .B(n1942), .Y(n1945) );
BUFX3TS U2969 ( .A(n1944), .Y(n2744) );
AOI22X1TS U2970 ( .A0(n1945), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n2802), .Y(n1946) );
OAI2BB1X1TS U2971 ( .A0N(n2702), .A1N(n1947), .B0(n1946), .Y(n1037) );
INVX2TS U2972 ( .A(n1948), .Y(n1951) );
INVX2TS U2973 ( .A(n1949), .Y(n1950) );
AOI21X1TS U2974 ( .A0(n1962), .A1(n1951), .B0(n1950), .Y(n1954) );
INVX2TS U2975 ( .A(n1952), .Y(n1981) );
NAND2X1TS U2976 ( .A(n1981), .B(n1979), .Y(n1956) );
INVX2TS U2977 ( .A(n1956), .Y(n1953) );
INVX2TS U2978 ( .A(n1955), .Y(n1982) );
XNOR2X1TS U2979 ( .A(n1982), .B(n1956), .Y(n1957) );
AOI22X1TS U2980 ( .A0(n1957), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2802), .Y(n1958) );
OAI2BB1X1TS U2981 ( .A0N(n2702), .A1N(n1959), .B0(n1958), .Y(n1036) );
AOI21X1TS U2982 ( .A0(n1962), .A1(n1961), .B0(n1960), .Y(n1978) );
INVX2TS U2983 ( .A(n2798), .Y(n1965) );
NAND2X1TS U2984 ( .A(n1965), .B(n2797), .Y(n1970) );
INVX2TS U2985 ( .A(n1970), .Y(n1966) );
XNOR2X1TS U2986 ( .A(n1967), .B(n1966), .Y(n1973) );
AOI21X1TS U2987 ( .A0(n1982), .A1(n1969), .B0(n1968), .Y(n2799) );
XOR2X1TS U2988 ( .A(n2799), .B(n1970), .Y(n1971) );
AOI22X1TS U2989 ( .A0(n1971), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n2802), .Y(n1972) );
OAI2BB1X1TS U2990 ( .A0N(n2702), .A1N(n1973), .B0(n1972), .Y(n1034) );
INVX2TS U2991 ( .A(n1974), .Y(n1976) );
NAND2X1TS U2992 ( .A(n1976), .B(n1975), .Y(n1983) );
INVX2TS U2993 ( .A(n1983), .Y(n1977) );
INVX2TS U2994 ( .A(n1979), .Y(n1980) );
AOI21X1TS U2995 ( .A0(n1982), .A1(n1981), .B0(n1980), .Y(n1984) );
XOR2X1TS U2996 ( .A(n1984), .B(n1983), .Y(n1985) );
AOI22X1TS U2997 ( .A0(n1985), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n2802), .Y(n1986) );
OAI2BB1X1TS U2998 ( .A0N(n2702), .A1N(n1987), .B0(n1986), .Y(n1035) );
BUFX3TS U2999 ( .A(n3057), .Y(n3061) );
INVX2TS U3000 ( .A(n3061), .Y(n3010) );
NAND2X1TS U3001 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .B(n1706), .Y(n2992) );
NAND2X1TS U3002 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B(n3129), .Y(n3000) );
INVX2TS U3003 ( .A(n3000), .Y(n2998) );
NOR2X1TS U3004 ( .A(n1657), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]),
.Y(n2996) );
OAI22X1TS U3005 ( .A0(n2998), .A1(n2996), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B1(n3084), .Y(n2994)
);
AOI22X1TS U3006 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .A1(
n3136), .B0(n2992), .B1(n2994), .Y(n3002) );
NOR2X1TS U3007 ( .A(n1658), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]),
.Y(n3003) );
AOI21X1TS U3008 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .A1(
n1658), .B0(n3003), .Y(n1988) );
XNOR2X1TS U3009 ( .A(n3002), .B(n1988), .Y(n1989) );
CLKBUFX2TS U3010 ( .A(n2869), .Y(n2867) );
BUFX3TS U3011 ( .A(n2867), .Y(n2879) );
CLKBUFX2TS U3012 ( .A(n2869), .Y(n2903) );
INVX2TS U3013 ( .A(n2903), .Y(n2872) );
BUFX3TS U3014 ( .A(n2867), .Y(n2870) );
INVX2TS U3015 ( .A(n2903), .Y(n2988) );
BUFX3TS U3016 ( .A(n2867), .Y(n2929) );
INVX2TS U3017 ( .A(n2903), .Y(n2919) );
INVX2TS U3018 ( .A(n2869), .Y(n2979) );
BUFX3TS U3019 ( .A(n2867), .Y(n2938) );
AOI22X1TS U3020 ( .A0(n1698), .A1(n2841), .B0(d_ff3_LUT_out[1]), .B1(n2834),
.Y(n1990) );
BUFX3TS U3021 ( .A(n2869), .Y(n2842) );
NOR2X2TS U3022 ( .A(n2830), .B(n3072), .Y(n2183) );
NAND2X1TS U3023 ( .A(n1990), .B(n2187), .Y(n1595) );
NOR2X4TS U3024 ( .A(n3072), .B(intadd_42_B_1_), .Y(n2195) );
BUFX3TS U3025 ( .A(n2869), .Y(n2940) );
NAND2X2TS U3026 ( .A(n2940), .B(cont_iter_out[1]), .Y(n2190) );
INVX2TS U3027 ( .A(n2190), .Y(n2186) );
AOI22X1TS U3028 ( .A0(n2839), .A1(n2186), .B0(d_ff3_LUT_out[0]), .B1(n2868),
.Y(n1991) );
OAI211X1TS U3029 ( .A0(cont_iter_out[3]), .A1(n2827), .B0(n1698), .C0(
intadd_42_B_1_), .Y(n2162) );
NAND2X1TS U3030 ( .A(n1991), .B(n2162), .Y(n1594) );
AOI22X1TS U3031 ( .A0(n2842), .A1(n2183), .B0(d_ff3_LUT_out[12]), .B1(n2834),
.Y(n1992) );
NAND2X1TS U3032 ( .A(n2186), .B(n2841), .Y(n2193) );
NAND2X1TS U3033 ( .A(n1992), .B(n2193), .Y(n1605) );
INVX2TS U3034 ( .A(n2468), .Y(n1993) );
AOI221X1TS U3035 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(
n1993), .B0(n3137), .B1(n2468), .C0(n2820), .Y(n3038) );
OAI22X1TS U3036 ( .A0(n3120), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]),
.B0(n3069), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .Y(n1994)
);
AOI221X1TS U3037 ( .A0(n3120), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n3069), .C0(n1994), .Y(
n2000) );
OAI22X1TS U3038 ( .A0(n3118), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B0(n3117), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1995) );
INVX2TS U3039 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n2511) );
OAI22X1TS U3040 ( .A0(n2511), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B0(n1656), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .Y(n1996) );
AOI221X1TS U3041 ( .A0(n2511), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(n1656), .C0(n1996),
.Y(n1998) );
AOI22X1TS U3042 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n3126),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n3103), .Y(n1997)
);
OAI22X1TS U3043 ( .A0(n3124), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B0(n3083), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .Y(n2001) );
INVX2TS U3044 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .Y(n2494) );
OAI22X1TS U3045 ( .A0(n2494), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B0(n3125), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n2002) );
OAI22X1TS U3046 ( .A0(n3115), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B0(n3079), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .Y(n2003) );
OAI22X1TS U3047 ( .A0(n3116), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B0(n3110), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n2004) );
OAI22X1TS U3048 ( .A0(n3122), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]),
.B0(n3080), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n2009)
);
OAI22X1TS U3049 ( .A0(n3123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]),
.B0(n1654), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .Y(n2010)
);
AOI221X1TS U3050 ( .A0(n3123), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1654), .C0(n2010), .Y(
n2015) );
OAI22X1TS U3051 ( .A0(n3113), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B0(n3119), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n2011) );
INVX2TS U3052 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n2489) );
INVX2TS U3053 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n2491) );
OAI22X1TS U3054 ( .A0(n2489), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B0(n2491), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n2012) );
INVX2TS U3055 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .Y(n2482) );
OAI22X1TS U3056 ( .A0(n2482), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]),
.B0(n3111), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n2017)
);
OAI22X1TS U3057 ( .A0(n1655), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]),
.B0(n1640), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n2018)
);
OAI22X1TS U3058 ( .A0(n1653), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]),
.B0(n3105), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n2019)
);
AOI221X1TS U3059 ( .A0(n1653), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .B1(n3105), .C0(n2019), .Y(
n2022) );
OAI22X1TS U3060 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]),
.B0(n1699), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .Y(n2020)
);
AOI221X1TS U3061 ( .A0(n3112), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B1(n1699), .C0(n2020), .Y(
n2021) );
NOR4X1TS U3062 ( .A(n2028), .B(n2027), .C(n2026), .D(n2025), .Y(n2469) );
NOR2X2TS U3063 ( .A(n2975), .B(n2029), .Y(n2030) );
AOI22X1TS U3064 ( .A0(d_ff2_Y[4]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n2965), .Y(n2035) );
NOR2X2TS U3065 ( .A(n2975), .B(n2812), .Y(n2032) );
BUFX3TS U3066 ( .A(n2894), .Y(n2962) );
NOR3X1TS U3067 ( .A(cont_var_out[1]), .B(n3097), .C(n2975), .Y(n2033) );
AOI22X1TS U3068 ( .A0(n2962), .A1(d_ff2_Z[4]), .B0(n2062), .B1(d_ff2_X[4]),
.Y(n2034) );
NAND2X1TS U3069 ( .A(n2035), .B(n2034), .Y(n1266) );
INVX2TS U3070 ( .A(n2983), .Y(n2943) );
AOI22X1TS U3071 ( .A0(d_ff2_Y[0]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .B1(n2916), .Y(n2037) );
AOI22X1TS U3072 ( .A0(n2962), .A1(d_ff2_Z[0]), .B0(n2062), .B1(d_ff2_X[0]),
.Y(n2036) );
NAND2X1TS U3073 ( .A(n2037), .B(n2036), .Y(n1274) );
AOI22X1TS U3074 ( .A0(d_ff2_Y[16]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n2079), .Y(n2039) );
BUFX3TS U3075 ( .A(n2894), .Y(n2966) );
AOI22X1TS U3076 ( .A0(n2966), .A1(d_ff2_Z[16]), .B0(n2063), .B1(d_ff2_X[16]),
.Y(n2038) );
NAND2X1TS U3077 ( .A(n2039), .B(n2038), .Y(n1242) );
AOI22X1TS U3078 ( .A0(d_ff2_Y[9]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B1(n2965), .Y(n2041) );
AOI22X1TS U3079 ( .A0(n2966), .A1(d_ff2_Z[9]), .B0(n2063), .B1(d_ff2_X[9]),
.Y(n2040) );
NAND2X1TS U3080 ( .A(n2041), .B(n2040), .Y(n1256) );
AOI22X1TS U3081 ( .A0(d_ff2_Y[2]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B1(n2943), .Y(n2043) );
AOI22X1TS U3082 ( .A0(n2962), .A1(d_ff2_Z[2]), .B0(n2209), .B1(d_ff2_X[2]),
.Y(n2042) );
NAND2X1TS U3083 ( .A(n2043), .B(n2042), .Y(n1270) );
AOI22X1TS U3084 ( .A0(d_ff2_Y[1]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B1(n2916), .Y(n2045) );
AOI22X1TS U3085 ( .A0(n2962), .A1(d_ff2_Z[1]), .B0(n2209), .B1(d_ff2_X[1]),
.Y(n2044) );
NAND2X1TS U3086 ( .A(n2045), .B(n2044), .Y(n1272) );
AOI22X1TS U3087 ( .A0(d_ff2_Y[14]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(n2079), .Y(n2047) );
AOI22X1TS U3088 ( .A0(n2966), .A1(d_ff2_Z[14]), .B0(n2063), .B1(d_ff2_X[14]),
.Y(n2046) );
NAND2X1TS U3089 ( .A(n2047), .B(n2046), .Y(n1246) );
AOI22X1TS U3090 ( .A0(d_ff2_Y[11]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .B1(n2965), .Y(n2049) );
AOI22X1TS U3091 ( .A0(n2966), .A1(d_ff2_Z[11]), .B0(n2063), .B1(d_ff2_X[11]),
.Y(n2048) );
NAND2X1TS U3092 ( .A(n2049), .B(n2048), .Y(n1252) );
AOI22X1TS U3093 ( .A0(d_ff2_Y[12]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(n2965), .Y(n2051) );
AOI22X1TS U3094 ( .A0(n2966), .A1(d_ff2_Z[12]), .B0(n2063), .B1(d_ff2_X[12]),
.Y(n2050) );
NAND2X1TS U3095 ( .A(n2051), .B(n2050), .Y(n1250) );
AOI22X1TS U3096 ( .A0(d_ff2_Y[17]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .B1(n2079), .Y(n2053) );
AOI22X1TS U3097 ( .A0(n2966), .A1(d_ff2_Z[17]), .B0(n2063), .B1(d_ff2_X[17]),
.Y(n2052) );
NAND2X1TS U3098 ( .A(n2053), .B(n2052), .Y(n1240) );
AOI22X1TS U3099 ( .A0(d_ff2_Y[8]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .B1(n2965), .Y(n2055) );
AOI22X1TS U3100 ( .A0(n2962), .A1(d_ff2_Z[8]), .B0(n2063), .B1(d_ff2_X[8]),
.Y(n2054) );
NAND2X1TS U3101 ( .A(n2055), .B(n2054), .Y(n1258) );
AOI22X1TS U3102 ( .A0(d_ff2_Y[15]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .B1(n2079), .Y(n2057) );
AOI22X1TS U3103 ( .A0(n2966), .A1(d_ff2_Z[15]), .B0(n2063), .B1(d_ff2_X[15]),
.Y(n2056) );
NAND2X1TS U3104 ( .A(n2057), .B(n2056), .Y(n1244) );
AOI22X1TS U3105 ( .A0(d_ff2_Y[13]), .A1(n2030), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B1(n2079), .Y(n2059) );
AOI22X1TS U3106 ( .A0(n2966), .A1(d_ff2_Z[13]), .B0(n2063), .B1(d_ff2_X[13]),
.Y(n2058) );
NAND2X1TS U3107 ( .A(n2059), .B(n2058), .Y(n1248) );
AOI22X1TS U3108 ( .A0(d_ff2_Y[3]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(n2981), .Y(n2061) );
AOI22X1TS U3109 ( .A0(n2962), .A1(d_ff2_Z[3]), .B0(n2209), .B1(d_ff2_X[3]),
.Y(n2060) );
NAND2X1TS U3110 ( .A(n2061), .B(n2060), .Y(n1268) );
BUFX3TS U3111 ( .A(n2243), .Y(n2976) );
AOI22X1TS U3112 ( .A0(d_ff2_Y[29]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n2975), .Y(n2065) );
BUFX3TS U3113 ( .A(n2062), .Y(n2063) );
AOI22X1TS U3114 ( .A0(n2962), .A1(d_ff2_Z[29]), .B0(n2062), .B1(d_ff2_X[29]),
.Y(n2064) );
NAND2X1TS U3115 ( .A(n2065), .B(n2064), .Y(n1216) );
AOI22X1TS U3116 ( .A0(d_ff2_Y[26]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .B1(n2975), .Y(n2068) );
AOI22X1TS U3117 ( .A0(n2032), .A1(d_ff2_Z[26]), .B0(n2972), .B1(d_ff2_X[26]),
.Y(n2067) );
NAND2X1TS U3118 ( .A(n2068), .B(n2067), .Y(n1222) );
AOI22X1TS U3119 ( .A0(d_ff2_Y[22]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(n2079), .Y(n2070) );
AOI22X1TS U3120 ( .A0(n2894), .A1(d_ff2_Z[22]), .B0(n2972), .B1(d_ff2_X[22]),
.Y(n2069) );
NAND2X1TS U3121 ( .A(n2070), .B(n2069), .Y(n1230) );
AOI22X1TS U3122 ( .A0(d_ff2_Y[19]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n2965), .Y(n2072) );
AOI22X1TS U3123 ( .A0(n2894), .A1(d_ff2_Z[19]), .B0(n2972), .B1(d_ff2_X[19]),
.Y(n2071) );
NAND2X1TS U3124 ( .A(n2072), .B(n2071), .Y(n1236) );
AOI22X1TS U3125 ( .A0(d_ff2_Y[18]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B1(n2079), .Y(n2074) );
AOI22X1TS U3126 ( .A0(n2966), .A1(d_ff2_Z[18]), .B0(n2972), .B1(d_ff2_X[18]),
.Y(n2073) );
NAND2X1TS U3127 ( .A(n2074), .B(n2073), .Y(n1238) );
AOI22X1TS U3128 ( .A0(d_ff2_Y[20]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(n2079), .Y(n2076) );
AOI22X1TS U3129 ( .A0(n2900), .A1(d_ff2_Z[20]), .B0(n2972), .B1(d_ff2_X[20]),
.Y(n2075) );
NAND2X1TS U3130 ( .A(n2076), .B(n2075), .Y(n1234) );
AOI22X1TS U3131 ( .A0(d_ff2_Y[21]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B1(n2079), .Y(n2078) );
AOI22X1TS U3132 ( .A0(n2900), .A1(d_ff2_Z[21]), .B0(n2972), .B1(d_ff2_X[21]),
.Y(n2077) );
NAND2X1TS U3133 ( .A(n2078), .B(n2077), .Y(n1232) );
AOI22X1TS U3134 ( .A0(d_ff2_Y[23]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B1(n2079), .Y(n2081) );
AOI22X1TS U3135 ( .A0(n2894), .A1(d_ff2_Z[23]), .B0(n2972), .B1(d_ff2_X[23]),
.Y(n2080) );
NAND2X1TS U3136 ( .A(n2081), .B(n2080), .Y(n1228) );
AOI22X1TS U3137 ( .A0(d_ff2_Y[27]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B1(n2975), .Y(n2083) );
AOI22X1TS U3138 ( .A0(n2889), .A1(d_ff2_Z[27]), .B0(n2972), .B1(d_ff2_X[27]),
.Y(n2082) );
NAND2X1TS U3139 ( .A(n2083), .B(n2082), .Y(n1220) );
BUFX3TS U3140 ( .A(n2084), .Y(n3204) );
BUFX3TS U3141 ( .A(n2084), .Y(n3203) );
BUFX3TS U3142 ( .A(n2084), .Y(n3202) );
BUFX3TS U3143 ( .A(n3227), .Y(n3200) );
BUFX3TS U3144 ( .A(n3227), .Y(n3196) );
BUFX3TS U3145 ( .A(n3227), .Y(n3193) );
BUFX3TS U3146 ( .A(n3227), .Y(n3207) );
BUFX3TS U3147 ( .A(n3227), .Y(n3192) );
BUFX3TS U3148 ( .A(n2084), .Y(n3208) );
AOI22X1TS U3149 ( .A0(n1646), .A1(d_ff2_Y[23]), .B0(d_ff3_sh_y_out[23]),
.B1(n2866), .Y(n2085) );
AOI22X1TS U3150 ( .A0(n1646), .A1(d_ff2_X[23]), .B0(d_ff3_sh_x_out[23]),
.B1(n2868), .Y(n2086) );
AOI22X1TS U3151 ( .A0(n2842), .A1(n2839), .B0(d_ff3_LUT_out[21]), .B1(n2834),
.Y(n2087) );
INVX2TS U3152 ( .A(n2195), .Y(n2838) );
NAND2X1TS U3153 ( .A(n2196), .B(n2838), .Y(n2161) );
AOI22X1TS U3154 ( .A0(n1646), .A1(n2195), .B0(d_ff3_LUT_out[23]), .B1(n2834),
.Y(n2088) );
NAND2X1TS U3155 ( .A(n2196), .B(n2830), .Y(n2835) );
AOI21X1TS U3156 ( .A0(d_ff3_LUT_out[25]), .A1(n2840), .B0(n2089), .Y(n2090)
);
OAI31X1TS U3157 ( .A0(cont_iter_out[3]), .A1(n2190), .A2(n2835), .B0(n2090),
.Y(n1612) );
INVX2TS U3158 ( .A(n2874), .Y(n2112) );
NAND4X1TS U3159 ( .A(n3098), .B(n2827), .C(n3072), .D(intadd_42_B_1_), .Y(
n2092) );
NOR2X2TS U3160 ( .A(n2135), .B(n2092), .Y(n2102) );
BUFX3TS U3161 ( .A(n2102), .Y(n2114) );
BUFX3TS U3162 ( .A(n2906), .Y(n2104) );
INVX2TS U3163 ( .A(n2094), .Y(n1237) );
INVX2TS U3164 ( .A(n2095), .Y(n1241) );
INVX2TS U3165 ( .A(n2096), .Y(n1245) );
INVX2TS U3166 ( .A(n2097), .Y(n1239) );
INVX2TS U3167 ( .A(n2098), .Y(n1247) );
INVX2TS U3168 ( .A(n2099), .Y(n1243) );
INVX2TS U3169 ( .A(n2100), .Y(n1235) );
INVX2TS U3170 ( .A(n2101), .Y(n1233) );
BUFX3TS U3171 ( .A(n2102), .Y(n2108) );
BUFX3TS U3172 ( .A(n2108), .Y(n2134) );
INVX2TS U3173 ( .A(n2103), .Y(n1231) );
INVX2TS U3174 ( .A(n2105), .Y(n1253) );
NAND2X1TS U3175 ( .A(n1698), .B(n2838), .Y(n2191) );
AOI22X1TS U3176 ( .A0(n1698), .A1(n2161), .B0(d_ff3_LUT_out[24]), .B1(n2834),
.Y(n2106) );
OAI31X1TS U3177 ( .A0(n2195), .A1(n2827), .A2(n2190), .B0(n2106), .Y(n1611)
);
INVX2TS U3178 ( .A(n2915), .Y(n2986) );
BUFX4TS U3179 ( .A(n2906), .Y(n2922) );
BUFX3TS U3180 ( .A(n2922), .Y(n2133) );
INVX2TS U3181 ( .A(n2107), .Y(n1275) );
BUFX3TS U3182 ( .A(n2922), .Y(n2987) );
INVX2TS U3183 ( .A(n2109), .Y(n1273) );
INVX2TS U3184 ( .A(n2110), .Y(n1269) );
BUFX3TS U3185 ( .A(n2922), .Y(n2122) );
INVX2TS U3186 ( .A(n2111), .Y(n1263) );
INVX2TS U3187 ( .A(n2113), .Y(n1249) );
INVX2TS U3188 ( .A(n2115), .Y(n1251) );
INVX2TS U3189 ( .A(n2116), .Y(n1265) );
INVX2TS U3190 ( .A(n2117), .Y(n1259) );
INVX2TS U3191 ( .A(n2118), .Y(n1267) );
INVX2TS U3192 ( .A(n2119), .Y(n1271) );
INVX2TS U3193 ( .A(n2120), .Y(n1261) );
INVX2TS U3194 ( .A(n2121), .Y(n1257) );
INVX2TS U3195 ( .A(n2124), .Y(n1255) );
INVX2TS U3196 ( .A(n2125), .Y(n1215) );
INVX2TS U3197 ( .A(n2126), .Y(n1221) );
INVX2TS U3198 ( .A(n2127), .Y(n1225) );
INVX2TS U3199 ( .A(n2128), .Y(n1214) );
INVX2TS U3200 ( .A(n2129), .Y(n1219) );
INVX2TS U3201 ( .A(n2130), .Y(n1227) );
INVX2TS U3202 ( .A(n2131), .Y(n1217) );
INVX2TS U3203 ( .A(n2132), .Y(n1229) );
INVX2TS U3204 ( .A(n2136), .Y(n1223) );
AOI21X1TS U3205 ( .A0(n3139), .A1(n3088), .B0(n2137), .Y(n2147) );
NOR2BX1TS U3206 ( .AN(n2139), .B(n2138), .Y(n2142) );
OAI22X1TS U3207 ( .A0(n3073), .A1(n2140), .B0(n2174), .B1(n1634), .Y(n2141)
);
BUFX3TS U3208 ( .A(n2349), .Y(n2398) );
AOI32X1TS U3209 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]),
.A1(n2947), .A2(n2821), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n2398), .Y(
n2144) );
NAND2X1TS U3210 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n2145) );
INVX2TS U3211 ( .A(n2147), .Y(n2148) );
OAI211XLTS U3212 ( .A0(n2151), .A1(n2150), .B0(n2149), .C0(n2148), .Y(n2156)
);
INVX2TS U3213 ( .A(n2152), .Y(n2154) );
OAI31X1TS U3214 ( .A0(n2174), .A1(n2154), .A2(n1645), .B0(n2153), .Y(n2155)
);
AOI211X1TS U3215 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n2157), .B0(n2156), .C0(n2155), .Y(n2160) );
NAND2X1TS U3216 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n2158) );
AOI32X1TS U3217 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]),
.A1(n2947), .A2(n2824), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n2398), .Y(
n2159) );
NOR2BX1TS U3218 ( .AN(n2161), .B(n2183), .Y(n2194) );
NAND2X1TS U3219 ( .A(d_ff3_LUT_out[10]), .B(n2840), .Y(n2163) );
NAND3X1TS U3220 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n2164), .C(n3077),
.Y(n2810) );
NOR3BX1TS U3221 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2165), .Y(n2811) );
NOR2BX1TS U3222 ( .AN(n2810), .B(n2811), .Y(n2166) );
INVX2TS U3223 ( .A(n2166), .Y(n2851) );
BUFX3TS U3224 ( .A(n2851), .Y(n2845) );
INVX2TS U3225 ( .A(n2845), .Y(n2846) );
NOR4X1TS U3226 ( .A(n2828), .B(n2874), .C(n2940), .D(n2167), .Y(n2168) );
AOI32X1TS U3227 ( .A0(n2846), .A1(n2816), .A2(n2168), .B0(ready_cordic),
.B1(ack_cordic), .Y(n2169) );
NAND2X1TS U3228 ( .A(n1698), .B(n3072), .Y(n2836) );
NOR3X1TS U3229 ( .A(n2830), .B(n2827), .C(n2190), .Y(n2182) );
AOI21X1TS U3230 ( .A0(d_ff3_LUT_out[2]), .A1(n2979), .B0(n2182), .Y(n2170)
);
AOI22X1TS U3231 ( .A0(n2173), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n2172), .B1(
n2171), .Y(n2175) );
AOI32X1TS U3232 ( .A0(n1645), .A1(n2175), .A2(n3229), .B0(n2174), .B1(n2175),
.Y(n2176) );
AOI211X1TS U3233 ( .A0(n2178), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n2177), .C0(
n2176), .Y(n2181) );
NAND2X1TS U3234 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n2179) );
AOI21X1TS U3235 ( .A0(d_ff3_LUT_out[6]), .A1(n2866), .B0(n2182), .Y(n2185)
);
OAI211XLTS U3236 ( .A0(cont_iter_out[1]), .A1(n2196), .B0(n2842), .C0(n2183),
.Y(n2184) );
NAND2X1TS U3237 ( .A(n2186), .B(n2838), .Y(n2843) );
INVX2TS U3238 ( .A(n2836), .Y(n2188) );
AOI22X1TS U3239 ( .A0(n2188), .A1(n2835), .B0(d_ff3_LUT_out[4]), .B1(n2868),
.Y(n2189) );
NAND2X1TS U3240 ( .A(d_ff3_LUT_out[5]), .B(n2979), .Y(n2192) );
XNOR2X1TS U3241 ( .A(n2201), .B(d_ff_Xn[31]), .Y(n2204) );
NOR2X4TS U3242 ( .A(ready_cordic), .B(n2197), .Y(n2216) );
BUFX3TS U3243 ( .A(n2216), .Y(n2254) );
XNOR2X1TS U3244 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n2198) );
XNOR2X1TS U3245 ( .A(d_ff1_shift_region_flag_out[0]), .B(n2198), .Y(n2200)
);
NOR2X2TS U3246 ( .A(n2216), .B(n2200), .Y(n2199) );
INVX2TS U3247 ( .A(n2199), .Y(n2205) );
BUFX3TS U3248 ( .A(n2255), .Y(n2292) );
XOR2X1TS U3249 ( .A(d_ff_Yn[31]), .B(n2201), .Y(n2202) );
AOI22X1TS U3250 ( .A0(n2254), .A1(data_output[31]), .B0(n2292), .B1(n2202),
.Y(n2203) );
INVX2TS U3251 ( .A(n2205), .Y(n2206) );
INVX2TS U3252 ( .A(n2207), .Y(n1175) );
INVX2TS U3253 ( .A(n2983), .Y(n2916) );
AOI222X1TS U3254 ( .A0(n2943), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(n2243), .B1(
d_ff3_sh_x_out[31]), .C0(d_ff3_sh_y_out[31]), .C1(n2062), .Y(n2208) );
INVX2TS U3255 ( .A(n2208), .Y(n1207) );
BUFX3TS U3256 ( .A(n2209), .Y(n2250) );
AOI22X1TS U3257 ( .A0(n2250), .A1(d_ff3_sh_y_out[30]), .B0(n2030), .B1(
d_ff3_sh_x_out[30]), .Y(n2210) );
BUFX3TS U3258 ( .A(n2216), .Y(n2289) );
BUFX3TS U3259 ( .A(n2255), .Y(n2288) );
INVX2TS U3260 ( .A(n2211), .Y(n1196) );
INVX2TS U3261 ( .A(n2212), .Y(n1205) );
INVX2TS U3262 ( .A(n2213), .Y(n1197) );
INVX2TS U3263 ( .A(n2214), .Y(n1201) );
INVX2TS U3264 ( .A(n2215), .Y(n1203) );
INVX2TS U3265 ( .A(n2217), .Y(n1204) );
INVX2TS U3266 ( .A(n2218), .Y(n1198) );
INVX2TS U3267 ( .A(n2219), .Y(n1200) );
INVX2TS U3268 ( .A(n2220), .Y(n1199) );
INVX2TS U3269 ( .A(n2221), .Y(n1202) );
BUFX3TS U3270 ( .A(n2209), .Y(n2909) );
AOI22X1TS U3271 ( .A0(n2909), .A1(d_ff3_sh_y_out[11]), .B0(n2243), .B1(
d_ff3_sh_x_out[11]), .Y(n2222) );
BUFX3TS U3272 ( .A(n2889), .Y(n2900) );
NAND2X1TS U3273 ( .A(n2900), .B(d_ff3_LUT_out[7]), .Y(n2235) );
BUFX3TS U3274 ( .A(n2243), .Y(n2249) );
AOI22X1TS U3275 ( .A0(n2250), .A1(d_ff3_sh_y_out[18]), .B0(n2249), .B1(
d_ff3_sh_x_out[18]), .Y(n2224) );
NAND2X1TS U3276 ( .A(n2900), .B(d_ff3_LUT_out[13]), .Y(n2238) );
AOI22X1TS U3277 ( .A0(n2250), .A1(d_ff3_sh_y_out[17]), .B0(n2249), .B1(
d_ff3_sh_x_out[17]), .Y(n2226) );
NAND2X1TS U3278 ( .A(n2889), .B(d_ff3_LUT_out[15]), .Y(n2251) );
AOI22X1TS U3279 ( .A0(n2250), .A1(d_ff3_sh_y_out[29]), .B0(n2243), .B1(
d_ff3_sh_x_out[29]), .Y(n2228) );
NAND2X1TS U3280 ( .A(n2889), .B(d_ff3_LUT_out[27]), .Y(n2241) );
AOI22X1TS U3281 ( .A0(n2250), .A1(d_ff3_sh_y_out[19]), .B0(n2249), .B1(
d_ff3_sh_x_out[19]), .Y(n2230) );
NAND2X1TS U3282 ( .A(n2889), .B(d_ff3_LUT_out[19]), .Y(n2231) );
AOI22X1TS U3283 ( .A0(n2250), .A1(d_ff3_sh_y_out[22]), .B0(n2249), .B1(
d_ff3_sh_x_out[22]), .Y(n2232) );
AOI22X1TS U3284 ( .A0(n2250), .A1(d_ff3_sh_y_out[28]), .B0(n2249), .B1(
d_ff3_sh_x_out[28]), .Y(n2234) );
AOI22X1TS U3285 ( .A0(n2909), .A1(d_ff3_sh_y_out[7]), .B0(n2243), .B1(
d_ff3_sh_x_out[7]), .Y(n2236) );
AOI22X1TS U3286 ( .A0(n2909), .A1(d_ff3_sh_y_out[14]), .B0(n2249), .B1(
d_ff3_sh_x_out[14]), .Y(n2237) );
NAND2X1TS U3287 ( .A(n2889), .B(d_ff3_LUT_out[5]), .Y(n2244) );
AOI22X1TS U3288 ( .A0(n2909), .A1(d_ff3_sh_y_out[13]), .B0(n2249), .B1(
d_ff3_sh_x_out[13]), .Y(n2239) );
AOI22X1TS U3289 ( .A0(n2250), .A1(d_ff3_sh_y_out[16]), .B0(n2249), .B1(
d_ff3_sh_x_out[16]), .Y(n2240) );
NAND2X1TS U3290 ( .A(n2889), .B(d_ff3_LUT_out[3]), .Y(n2247) );
AOI22X1TS U3291 ( .A0(n2250), .A1(d_ff3_sh_y_out[27]), .B0(n2249), .B1(
d_ff3_sh_x_out[27]), .Y(n2242) );
AOI22X1TS U3292 ( .A0(n2909), .A1(d_ff3_sh_y_out[5]), .B0(n2243), .B1(
d_ff3_sh_x_out[5]), .Y(n2245) );
AOI22X1TS U3293 ( .A0(n2909), .A1(d_ff3_sh_y_out[15]), .B0(n2066), .B1(
d_ff3_sh_x_out[15]), .Y(n2246) );
AOI22X1TS U3294 ( .A0(n2909), .A1(d_ff3_sh_y_out[3]), .B0(n2243), .B1(
d_ff3_sh_x_out[3]), .Y(n2248) );
AOI22X1TS U3295 ( .A0(n2250), .A1(d_ff3_sh_y_out[20]), .B0(n2249), .B1(
d_ff3_sh_x_out[20]), .Y(n2252) );
BUFX3TS U3296 ( .A(n2254), .Y(n2285) );
BUFX3TS U3297 ( .A(n2255), .Y(n2284) );
INVX2TS U3298 ( .A(n2256), .Y(n1190) );
INVX2TS U3299 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
n2301) );
INVX2TS U3300 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
n2297) );
NOR2BX1TS U3301 ( .AN(n2259), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n2260) );
INVX2TS U3302 ( .A(n3015), .Y(n2266) );
AND4X1TS U3303 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n2262) );
AND4X1TS U3304 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(n2262), .Y(n2263) );
INVX4TS U3305 ( .A(n2265), .Y(n3016) );
INVX2TS U3306 ( .A(n2268), .Y(n1184) );
INVX2TS U3307 ( .A(n2269), .Y(n1182) );
INVX2TS U3308 ( .A(n2270), .Y(n1185) );
INVX2TS U3309 ( .A(n2271), .Y(n1176) );
INVX2TS U3310 ( .A(n2272), .Y(n1177) );
INVX2TS U3311 ( .A(n2273), .Y(n1181) );
INVX2TS U3312 ( .A(n2274), .Y(n1180) );
INVX2TS U3313 ( .A(n2275), .Y(n1178) );
INVX2TS U3314 ( .A(n2276), .Y(n1179) );
INVX2TS U3315 ( .A(n2277), .Y(n1194) );
INVX2TS U3316 ( .A(n2278), .Y(n1187) );
INVX2TS U3317 ( .A(n2279), .Y(n1192) );
INVX2TS U3318 ( .A(n2280), .Y(n1193) );
INVX2TS U3319 ( .A(n2281), .Y(n1191) );
INVX2TS U3320 ( .A(n2282), .Y(n1188) );
INVX2TS U3321 ( .A(n2283), .Y(n1186) );
INVX2TS U3322 ( .A(n2286), .Y(n1189) );
INVX2TS U3323 ( .A(n2290), .Y(n1195) );
INVX2TS U3324 ( .A(n2293), .Y(n1183) );
BUFX3TS U3325 ( .A(n1638), .Y(n3055) );
NAND2X1TS U3326 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(
n1684), .Y(n2294) );
NAND2X1TS U3327 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(
n1684), .Y(n2295) );
NAND2X1TS U3328 ( .A(n3055), .B(result_add_subt[25]), .Y(n2296) );
NAND2X1TS U3329 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
n1684), .Y(n2298) );
NAND2X1TS U3330 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .B(
n1684), .Y(n2299) );
NAND2X1TS U3331 ( .A(n3055), .B(result_add_subt[26]), .Y(n2300) );
NAND2X1TS U3332 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
n1684), .Y(n2302) );
AOI22X1TS U3333 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n1673), .B1(n2399), .Y(n2304) );
AOI22X1TS U3334 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B1(n2306), .Y(n2307) );
AOI22X1TS U3335 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B1(n2447), .Y(n2308) );
AOI22X1TS U3336 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B1(n2306), .Y(n2309) );
AOI22X1TS U3337 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B1(n2306), .Y(n2310) );
NAND2X1TS U3338 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2313) );
NAND2X1TS U3339 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2312) );
NAND2X1TS U3340 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n2311) );
AOI22X1TS U3341 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B1(n2398), .Y(n2322)
);
NAND2X1TS U3342 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n2320) );
NAND2X1TS U3343 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n2319) );
NAND2X1TS U3344 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n2318) );
OAI2BB2X1TS U3345 ( .B0(n2423), .B1(n1645), .A0N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n2421), .Y(
n2342) );
AOI21X1TS U3346 ( .A0(n1694), .A1(n2381), .B0(n2342), .Y(n2321) );
NAND2X1TS U3347 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n2325) );
NAND2X1TS U3348 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n2324) );
NAND2X1TS U3349 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n2323) );
NAND3X1TS U3350 ( .A(n2325), .B(n2324), .C(n2323), .Y(n2353) );
INVX2TS U3351 ( .A(n2353), .Y(n2391) );
AOI22X1TS U3352 ( .A0(n2406), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n3053), .Y(
n2326) );
AOI22X1TS U3353 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B0(n1690), .B1(n2388), .Y(n2335) );
AOI22X1TS U3354 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2330), .Y(
n2328) );
NAND2X1TS U3355 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n2332) );
NAND2X1TS U3356 ( .A(n2330), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n2331) );
NAND3X1TS U3357 ( .A(n2333), .B(n2332), .C(n2331), .Y(n2387) );
AOI22X1TS U3358 ( .A0(n1662), .A1(n2418), .B0(n1694), .B1(n2387), .Y(n2334)
);
AOI22X1TS U3359 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n3053), .Y(n2336) );
AOI22X1TS U3360 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B0(n1690), .B1(n2383),
.Y(n2341) );
NAND2X1TS U3361 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n2339) );
NAND2X1TS U3362 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n2338) );
NAND2X1TS U3363 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n2337) );
NAND3X1TS U3364 ( .A(n2339), .B(n2338), .C(n2337), .Y(n2382) );
AOI22X1TS U3365 ( .A0(n1673), .A1(n2381), .B0(n1693), .B1(n2382), .Y(n2340)
);
AOI22X1TS U3366 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B0(n1690), .B1(n2381),
.Y(n2344) );
AOI22X1TS U3367 ( .A0(n1662), .A1(n2342), .B0(n1693), .B1(n2383), .Y(n2343)
);
NAND2X1TS U3368 ( .A(n2406), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n2348) );
NAND2X1TS U3369 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2347) );
NAND2X1TS U3370 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n2346) );
NAND3X1TS U3371 ( .A(n2348), .B(n2347), .C(n2346), .Y(n2438) );
INVX2TS U3372 ( .A(n2438), .Y(n2356) );
BUFX3TS U3373 ( .A(n2349), .Y(n2437) );
AOI22X1TS U3374 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B0(n1690), .B1(n2353), .Y(n2351) );
AOI22X1TS U3375 ( .A0(n1673), .A1(n2418), .B0(n1694), .B1(n2388), .Y(n2350)
);
AOI22X1TS U3376 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B0(n1691), .B1(n2418), .Y(n2355) );
AOI22X1TS U3377 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(
n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(
n2821), .Y(n2352) );
AOI22X1TS U3378 ( .A0(n1662), .A1(n2436), .B0(n1694), .B1(n2353), .Y(n2354)
);
NAND2X1TS U3379 ( .A(n2417), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n2360) );
NAND2X1TS U3380 ( .A(n2361), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n2359) );
NAND2X1TS U3381 ( .A(n2357), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n2358) );
NAND3X1TS U3382 ( .A(n2360), .B(n2359), .C(n2358), .Y(n2392) );
INVX2TS U3383 ( .A(n2392), .Y(n2380) );
AOI22X1TS U3384 ( .A0(n2361), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n3053), .Y(n2362) );
AOI22X1TS U3385 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B0(n1691), .B1(n2413),
.Y(n2365) );
AOI22X1TS U3386 ( .A0(n2421), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n3053), .Y(n2363) );
AOI222X4TS U3387 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n2406), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n2404), .Y(
n2416) );
INVX2TS U3388 ( .A(n2416), .Y(n2375) );
AOI22X1TS U3389 ( .A0(n1662), .A1(n2393), .B0(n1695), .B1(n2375), .Y(n2364)
);
INVX2TS U3390 ( .A(n2387), .Y(n2374) );
AOI22X1TS U3391 ( .A0(n2417), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2824), .Y(
n2366) );
AOI22X1TS U3392 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B0(n1690), .B1(n2397), .Y(n2368) );
AOI22X1TS U3393 ( .A0(n1662), .A1(n2388), .B0(n1695), .B1(n2371), .Y(n2367)
);
INVX2TS U3394 ( .A(n2382), .Y(n2396) );
AOI22X1TS U3395 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B0(n1690), .B1(n2393),
.Y(n2370) );
AOI22X1TS U3396 ( .A0(n1662), .A1(n2383), .B0(n1694), .B1(n2392), .Y(n2369)
);
AOI22X1TS U3397 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B0(n1690), .B1(n2371), .Y(n2373) );
AOI22X1TS U3398 ( .A0(n1673), .A1(n2397), .B0(n1695), .B1(n2400), .Y(n2372)
);
AOI22X1TS U3399 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B0(n1689), .B1(n2375),
.Y(n2379) );
AOI22X1TS U3400 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]),
.A1(n2417), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(
n2821), .Y(n2376) );
AOI22X1TS U3401 ( .A0(n1673), .A1(n2413), .B0(n1694), .B1(n2411), .Y(n2378)
);
INVX2TS U3402 ( .A(n2381), .Y(n2386) );
AOI22X1TS U3403 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B0(n1689), .B1(n2382),
.Y(n2385) );
AOI22X1TS U3404 ( .A0(n1673), .A1(n2383), .B0(n1694), .B1(n2393), .Y(n2384)
);
AOI22X1TS U3405 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B0(n1691), .B1(n2387), .Y(n2390) );
AOI22X1TS U3406 ( .A0(n1673), .A1(n2388), .B0(n1695), .B1(n2397), .Y(n2389)
);
AOI22X1TS U3407 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B0(n1691), .B1(n2392),
.Y(n2395) );
AOI22X1TS U3408 ( .A0(n1673), .A1(n2393), .B0(n1695), .B1(n2413), .Y(n2394)
);
AOI22X1TS U3409 ( .A0(n2398), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n1662), .B1(n2397), .Y(n2402) );
AOI22X1TS U3410 ( .A0(n1689), .A1(n2400), .B0(n1695), .B1(n2399), .Y(n2401)
);
AOI222X4TS U3411 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n2417), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n2404), .Y(
n2435) );
AOI22X1TS U3412 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.A1(n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]),
.B1(n2821), .Y(n2405) );
AOI22X1TS U3413 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B0(n1691), .B1(n2431), .Y(n2408) );
AOI222X4TS U3414 ( .A0(n3053), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2406), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n2421), .Y(
n2429) );
INVX2TS U3415 ( .A(n2429), .Y(n2430) );
AOI22X1TS U3416 ( .A0(n2327), .A1(n2411), .B0(n1693), .B1(n2430), .Y(n2407)
);
INVX2TS U3417 ( .A(n2435), .Y(n2412) );
AOI22X1TS U3418 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B0(n1690), .B1(n2412),
.Y(n2410) );
AOI22X1TS U3419 ( .A0(n1673), .A1(n2411), .B0(n1694), .B1(n2431), .Y(n2409)
);
AOI22X1TS U3420 ( .A0(n2349), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B0(n1689), .B1(n2411),
.Y(n2415) );
AOI22X1TS U3421 ( .A0(n1669), .A1(n2413), .B0(n1695), .B1(n2412), .Y(n2414)
);
AOI222X4TS U3422 ( .A0(n2821), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n2421), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n2417), .Y(
n2442) );
AOI22X1TS U3423 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B0(n1689), .B1(n2438), .Y(n2420) );
AOI22X1TS U3424 ( .A0(n1751), .A1(n2436), .B0(n1693), .B1(n2418), .Y(n2419)
);
INVX2TS U3425 ( .A(n2442), .Y(n2426) );
AOI22X1TS U3426 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B0(n1689), .B1(n2426), .Y(n2425) );
AOI22X1TS U3427 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n2421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n2821), .Y(n2422) );
AOI22X1TS U3428 ( .A0(n1751), .A1(n2439), .B0(n1693), .B1(n2436), .Y(n2424)
);
AOI22X1TS U3429 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B0(n1689), .B1(n2439), .Y(n2428) );
AOI22X1TS U3430 ( .A0(n1662), .A1(n2431), .B0(n1693), .B1(n2426), .Y(n2427)
);
AOI22X1TS U3431 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B0(n1691), .B1(n2430), .Y(n2433) );
AOI22X1TS U3432 ( .A0(n1673), .A1(n2431), .B0(n1695), .B1(n2439), .Y(n2432)
);
AOI22X1TS U3433 ( .A0(n2437), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B0(n1689), .B1(n2436), .Y(n2441) );
AOI22X1TS U3434 ( .A0(n1662), .A1(n2439), .B0(n1693), .B1(n2438), .Y(n2440)
);
AOI22X1TS U3435 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B1(n2502), .Y(n2443) );
BUFX3TS U3436 ( .A(n2447), .Y(n2473) );
AOI22X1TS U3437 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B1(n2473), .Y(n2444) );
AOI22X1TS U3438 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B1(n2502), .Y(n2445) );
AOI22X1TS U3439 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B1(n2473), .Y(n2446) );
BUFX3TS U3440 ( .A(n2447), .Y(n2507) );
AOI22X1TS U3441 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B1(n2507), .Y(n2448) );
AOI22X1TS U3442 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B1(n2502), .Y(n2449) );
AOI22X1TS U3443 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B1(n2473), .Y(n2450) );
AOI22X1TS U3444 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B1(n2473), .Y(n2452) );
AOI22X1TS U3445 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B1(n2473), .Y(n2453) );
AOI22X1TS U3446 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B1(n2473), .Y(n2454) );
AOI22X1TS U3447 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n2458),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B1(n2502), .Y(n2455) );
AOI22X1TS U3448 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B1(n2502), .Y(n2456) );
AOI22X1TS U3449 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n2458), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B1(n2502), .Y(n2459) );
INVX2TS U3450 ( .A(n1825), .Y(n2465) );
AOI22X1TS U3451 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B1(n2473), .Y(n2460) );
AOI22X1TS U3452 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B1(n2473), .Y(n2461) );
AOI22X1TS U3453 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B1(n2473), .Y(n2462) );
AOI22X1TS U3454 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B1(n3039), .Y(n2464) );
AOI22X1TS U3455 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(n2466), .B0(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .B1(n2502), .Y(n2467) );
INVX2TS U3456 ( .A(n2475), .Y(n2501) );
AOI22X1TS U3457 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B1(n2820), .Y(n2470) );
AOI22X1TS U3458 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B1(n2507), .Y(n2471) );
AOI22X1TS U3459 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B1(n2820), .Y(n2472) );
AOI22X1TS U3460 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B1(n2473), .Y(n2474) );
AOI22X1TS U3461 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B1(n2507), .Y(n2476) );
AOI22X1TS U3462 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B1(n2820), .Y(n2477) );
AOI22X1TS U3463 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B1(n3039), .Y(n2478) );
AOI22X1TS U3464 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B1(n1714), .Y(n2479) );
AOI22X1TS U3465 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B1(n2306), .Y(n2480) );
AOI22X1TS U3466 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B1(n2447), .Y(n2481) );
AOI22X1TS U3467 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B1(n2306), .Y(n2483) );
AOI22X1TS U3468 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B1(n2507), .Y(n2484) );
AOI22X1TS U3469 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n2514),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B1(n2820), .Y(n2485) );
AOI22X1TS U3470 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n2514),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B1(n2820), .Y(n2486) );
AOI22X1TS U3471 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B1(n2820), .Y(n2487) );
AOI22X1TS U3472 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B1(n2507), .Y(n2488) );
AOI22X1TS U3473 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B1(n2507), .Y(n2490) );
AOI22X1TS U3474 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n2496),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B1(n2306), .Y(n2492) );
AOI22X1TS U3475 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B1(n2507), .Y(n2493) );
AOI22X1TS U3476 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n2514), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B1(n2820), .Y(n2495) );
AOI22X1TS U3477 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n2496), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B1(n2502), .Y(n2497) );
AOI22X1TS U3478 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n2505),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B1(n2507), .Y(n2498) );
AOI22X1TS U3479 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n2505), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B1(n3039), .Y(n2500) );
AOI22X1TS U3480 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n2505),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B1(n2502), .Y(n2503) );
AOI22X1TS U3481 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B1(n2507), .Y(n2506) );
AOI22X1TS U3482 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B1(n2507), .Y(n2508) );
AOI22X1TS U3483 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n1823),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B1(n1714), .Y(n2509) );
AOI22X1TS U3484 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n2513), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3039), .Y(n2510) );
AOI222X1TS U3485 ( .A0(n2513), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B1(n3039), .C0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .C1(n1825), .Y(n2512) );
INVX2TS U3486 ( .A(n2512), .Y(n1110) );
AOI222X1TS U3487 ( .A0(n2514), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B1(n3039), .C0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .C1(n2513), .Y(n2515) );
INVX2TS U3488 ( .A(n2515), .Y(n1158) );
INVX2TS U3489 ( .A(n2833), .Y(n2832) );
OAI21XLTS U3490 ( .A0(n2832), .A1(n3097), .B0(cont_var_out[1]), .Y(n2516) );
NOR2BX1TS U3491 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2518) );
XOR2X1TS U3492 ( .A(n3094), .B(n2518), .Y(DP_OP_33J13_122_2179_n14) );
NOR2BX1TS U3493 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2519) );
XOR2X1TS U3494 ( .A(n3094), .B(n2519), .Y(DP_OP_33J13_122_2179_n15) );
NOR2BX1TS U3495 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2520) );
XOR2X1TS U3496 ( .A(n3094), .B(n2520), .Y(DP_OP_33J13_122_2179_n16) );
NOR2BX1TS U3497 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2521) );
XOR2X1TS U3498 ( .A(n3094), .B(n2521), .Y(DP_OP_33J13_122_2179_n17) );
XOR2X1TS U3499 ( .A(n3094), .B(n1708), .Y(DP_OP_33J13_122_2179_n18) );
OAI33X4TS U3500 ( .A0(n3132), .A1(n3266), .A2(n1643), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2823) );
MXI2X1TS U3501 ( .A(n2522), .B(n2802), .S0(n2823), .Y(n1623) );
BUFX3TS U3502 ( .A(n2524), .Y(n3009) );
INVX2TS U3503 ( .A(n2545), .Y(n2553) );
OAI33X1TS U3504 ( .A0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]),
.A1(n3082), .A2(n3068), .B0(n3067), .B1(n3128), .B2(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2525) );
AOI22X1TS U3505 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B1(n1682),
.Y(n2527) );
AOI22X1TS U3506 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B1(n1678),
.Y(n2526) );
OAI211X1TS U3507 ( .A0(n2588), .A1(n1639), .B0(n2527), .C0(n2526), .Y(n2621)
);
NOR2X2TS U3508 ( .A(n2553), .B(n1649), .Y(n2543) );
AOI21X1TS U3509 ( .A0(n2528), .A1(n2534), .B0(n2558), .Y(n2529) );
AOI221X1TS U3510 ( .A0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.A1(n3081), .B0(n3068), .B1(n3127), .C0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2530) );
AOI22X1TS U3511 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n1678),
.Y(n2533) );
AOI22X1TS U3512 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B1(n1681),
.Y(n2532) );
OAI211X1TS U3513 ( .A0(n2593), .A1(n1639), .B0(n2533), .C0(n2532), .Y(n2614)
);
AOI211X1TS U3514 ( .A0(n2620), .A1(n2614), .B0(n2572), .C0(n2535), .Y(n3017)
);
MXI2X1TS U3515 ( .A(n3017), .B(n3158), .S0(n2558), .Y(n867) );
AOI22X1TS U3516 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B1(n1681),
.Y(n2538) );
AOI22X1TS U3517 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n1677),
.Y(n2537) );
OAI211X1TS U3518 ( .A0(n1696), .A1(n1639), .B0(n2538), .C0(n2537), .Y(n2611)
);
AOI211X1TS U3519 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2611), .B0(n2572), .C0(n2539), .Y(n3021) );
MXI2X1TS U3520 ( .A(n3021), .B(n3146), .S0(n2558), .Y(n868) );
AOI22X1TS U3521 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B1(n1681),
.Y(n2542) );
AOI22X1TS U3522 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n1677),
.Y(n2541) );
OAI211X1TS U3523 ( .A0(n2598), .A1(n1639), .B0(n2542), .C0(n2541), .Y(n2608)
);
AOI21X1TS U3524 ( .A0(n2553), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n2543), .Y(n2606)
);
AOI211X1TS U3525 ( .A0(n1686), .A1(n2608), .B0(n2572), .C0(n2544), .Y(n3023)
);
MXI2X1TS U3526 ( .A(n3023), .B(n3159), .S0(n2558), .Y(n869) );
AOI22X1TS U3527 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .B1(n1681),
.Y(n2549) );
AOI22X1TS U3528 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n1677),
.Y(n2548) );
OAI211X1TS U3529 ( .A0(n1697), .A1(n1639), .B0(n2549), .C0(n2548), .Y(n2605)
);
OAI21X1TS U3530 ( .A0(n3081), .A1(n2551), .B0(n2550), .Y(n2552) );
AOI211X1TS U3531 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2605), .B0(n2572), .C0(n2554), .Y(n3022) );
MXI2X1TS U3532 ( .A(n3022), .B(n3147), .S0(n2558), .Y(n870) );
AOI22X1TS U3533 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n1681),
.Y(n2556) );
AOI22X1TS U3534 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n1677),
.Y(n2555) );
OAI211X1TS U3535 ( .A0(n2603), .A1(n1639), .B0(n2556), .C0(n2555), .Y(n2602)
);
AOI211X1TS U3536 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2602), .B0(n2572), .C0(n2557), .Y(n3019) );
MXI2X1TS U3537 ( .A(n3019), .B(n3160), .S0(n2558), .Y(n871) );
AOI22X1TS U3538 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n1678), .Y(n2560) );
AOI22X1TS U3539 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n1682),
.Y(n2559) );
AOI211X1TS U3540 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2600), .B0(n2572), .C0(n2561), .Y(n3024) );
MXI2X1TS U3541 ( .A(n3024), .B(n3148), .S0(n2585), .Y(n872) );
AOI22X1TS U3542 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n1678), .Y(n2563) );
AOI22X1TS U3543 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n1681),
.Y(n2562) );
OAI211X1TS U3544 ( .A0(n2609), .A1(n1639), .B0(n2563), .C0(n2562), .Y(n2597)
);
AOI211X1TS U3545 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2597), .B0(n2572), .C0(n2564), .Y(n3030) );
MXI2X1TS U3546 ( .A(n3030), .B(n3161), .S0(n2585), .Y(n873) );
AOI22X1TS U3547 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n1678), .Y(n2566) );
AOI22X1TS U3548 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n1681),
.Y(n2565) );
OAI211X1TS U3549 ( .A0(n1647), .A1(n1639), .B0(n2566), .C0(n2565), .Y(n2595)
);
AOI211X1TS U3550 ( .A0(n1686), .A1(n2595), .B0(n2572), .C0(n2567), .Y(n3018)
);
MXI2X1TS U3551 ( .A(n3018), .B(n3149), .S0(n2585), .Y(n874) );
AOI22X1TS U3552 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n1678), .Y(n2569) );
AOI22X1TS U3553 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1679), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n1681),
.Y(n2568) );
OAI211X1TS U3554 ( .A0(n2616), .A1(n1639), .B0(n2569), .C0(n2568), .Y(n2592)
);
AOI211X1TS U3555 ( .A0(n1686), .A1(n2592), .B0(n2572), .C0(n2571), .Y(n3034)
);
MXI2X1TS U3556 ( .A(n3034), .B(n3162), .S0(n2585), .Y(n875) );
AOI22X1TS U3557 ( .A0(n1686), .A1(n2574), .B0(n2573), .B1(n1705), .Y(n3028)
);
MXI2X1TS U3558 ( .A(n3028), .B(n3150), .S0(n2585), .Y(n876) );
AOI21X1TS U3559 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .A1(
n1678), .B0(n2590), .Y(n2576) );
AOI22X1TS U3560 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .A1(
n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n1682), .Y(n2575) );
OAI211X1TS U3561 ( .A0(n3130), .A1(n1636), .B0(n2576), .C0(n2575), .Y(n2586)
);
AOI22X1TS U3562 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B1(n1682), .Y(n2577) );
OAI211X1TS U3563 ( .A0(n3131), .A1(n1909), .B0(n2578), .C0(n2577), .Y(n2587)
);
AOI22X1TS U3564 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2586), .B0(n2587), .B1(n1704), .Y(n3036) );
MXI2X1TS U3565 ( .A(n3036), .B(n3163), .S0(n2612), .Y(n877) );
AOI22X1TS U3566 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n1682), .Y(n2580) );
AOI22X1TS U3567 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .A1(
n1677), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B1(n1676), .Y(n2579) );
NAND2X1TS U3568 ( .A(n2580), .B(n2579), .Y(n2583) );
AOI22X1TS U3569 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .A1(
n1680), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n1682), .Y(n2582) );
AOI22X1TS U3570 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .A1(
n1677), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B1(n1676), .Y(n2581) );
NAND2X1TS U3571 ( .A(n2582), .B(n2581), .Y(n2584) );
AOI221X1TS U3572 ( .A0(n1686), .A1(n2583), .B0(n1704), .B1(n2584), .C0(n2590), .Y(n3032) );
MXI2X1TS U3573 ( .A(n3032), .B(n3151), .S0(n2585), .Y(n878) );
AOI221X1TS U3574 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n2584), .B0(n1705), .B1(n2583), .C0(n2590), .Y(n3035) );
MXI2X1TS U3575 ( .A(n3035), .B(n3152), .S0(n2585), .Y(n879) );
AOI22X1TS U3576 ( .A0(n2620), .A1(n2587), .B0(n2586), .B1(n1705), .Y(n3048)
);
MXI2X1TS U3577 ( .A(n3048), .B(n1707), .S0(n2612), .Y(n880) );
NAND2X4TS U3578 ( .A(n1686), .B(n1668), .Y(n2617) );
AOI211X1TS U3579 ( .A0(n2592), .A1(n1704), .B0(n2591), .C0(n2618), .Y(n3044)
);
BUFX3TS U3580 ( .A(n2612), .Y(n2622) );
MXI2X1TS U3581 ( .A(n3044), .B(n3153), .S0(n2622), .Y(n882) );
AOI211X1TS U3582 ( .A0(n2595), .A1(n1705), .B0(n2594), .C0(n2618), .Y(n3027)
);
MXI2X1TS U3583 ( .A(n3027), .B(n3143), .S0(n2612), .Y(n883) );
AOI211X1TS U3584 ( .A0(n2597), .A1(n1637), .B0(n2596), .C0(n2618), .Y(n3050)
);
MXI2X1TS U3585 ( .A(n3050), .B(n3154), .S0(n2622), .Y(n884) );
AOI211X1TS U3586 ( .A0(n2600), .A1(n1705), .B0(n2599), .C0(n2618), .Y(n3026)
);
MXI2X1TS U3587 ( .A(n3026), .B(n3144), .S0(n2622), .Y(n885) );
AOI211X1TS U3588 ( .A0(n2602), .A1(n1704), .B0(n2601), .C0(n2618), .Y(n3042)
);
MXI2X1TS U3589 ( .A(n3042), .B(n3155), .S0(n2622), .Y(n886) );
AOI211X1TS U3590 ( .A0(n2605), .A1(n1705), .B0(n2604), .C0(n2618), .Y(n3043)
);
MXI2X1TS U3591 ( .A(n3043), .B(n3145), .S0(n2622), .Y(n887) );
AOI211X1TS U3592 ( .A0(n2608), .A1(n1704), .B0(n2607), .C0(n2618), .Y(n3047)
);
MXI2X1TS U3593 ( .A(n3047), .B(n3156), .S0(n2622), .Y(n888) );
AOI211X1TS U3594 ( .A0(n2611), .A1(n1705), .B0(n2610), .C0(n2618), .Y(n3045)
);
MXI2X1TS U3595 ( .A(n3045), .B(n3157), .S0(n2612), .Y(n889) );
AOI211X1TS U3596 ( .A0(n2614), .A1(n1704), .B0(n2613), .C0(n2618), .Y(n2615)
);
MXI2X1TS U3597 ( .A(n2615), .B(n3089), .S0(n2622), .Y(n890) );
AOI211X1TS U3598 ( .A0(n2621), .A1(n1705), .B0(n2619), .C0(n2618), .Y(n2623)
);
MXI2X1TS U3599 ( .A(n2623), .B(n2767), .S0(n2622), .Y(n891) );
NAND2X1TS U3600 ( .A(n2626), .B(n2625), .Y(n2629) );
INVX2TS U3601 ( .A(n2629), .Y(n2627) );
XOR2X1TS U3602 ( .A(n2630), .B(n2629), .Y(n2631) );
AOI22X1TS U3603 ( .A0(n2631), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n2822), .Y(
n2632) );
OAI2BB1X1TS U3604 ( .A0N(n2701), .A1N(n2633), .B0(n2632), .Y(n1027) );
NAND2X1TS U3605 ( .A(n2635), .B(n2634), .Y(n2638) );
INVX2TS U3606 ( .A(n2638), .Y(n2636) );
XNOR2X1TS U3607 ( .A(n2637), .B(n2636), .Y(n2642) );
XNOR2X1TS U3608 ( .A(n2639), .B(n2638), .Y(n2640) );
AOI22X1TS U3609 ( .A0(n2640), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B1(n2822), .Y(
n2641) );
OAI2BB1X1TS U3610 ( .A0N(n2701), .A1N(n2642), .B0(n2641), .Y(n1026) );
INVX2TS U3611 ( .A(n2643), .Y(n2645) );
NAND2X1TS U3612 ( .A(n2645), .B(n2644), .Y(n2648) );
INVX2TS U3613 ( .A(n2648), .Y(n2646) );
XOR2X1TS U3614 ( .A(n2649), .B(n2648), .Y(n2650) );
AOI22X1TS U3615 ( .A0(n2650), .A1(n1944), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B1(n2822), .Y(
n2651) );
OAI2BB1X1TS U3616 ( .A0N(n2701), .A1N(n2652), .B0(n2651), .Y(n1025) );
INVX2TS U3617 ( .A(n2653), .Y(n2655) );
NAND2X1TS U3618 ( .A(n2655), .B(n2654), .Y(n2658) );
INVX2TS U3619 ( .A(n2658), .Y(n2656) );
XOR2X1TS U3620 ( .A(n2659), .B(n2658), .Y(n2660) );
BUFX3TS U3621 ( .A(n3008), .Y(n2768) );
AOI22X1TS U3622 ( .A0(n2660), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n2768), .Y(
n2661) );
OAI2BB1X1TS U3623 ( .A0N(n2701), .A1N(n2662), .B0(n2661), .Y(n1009) );
NAND2X1TS U3624 ( .A(n2664), .B(n2663), .Y(n2667) );
INVX2TS U3625 ( .A(n2667), .Y(n2665) );
XNOR2X1TS U3626 ( .A(n2666), .B(n2665), .Y(n2671) );
XNOR2X1TS U3627 ( .A(n2668), .B(n2667), .Y(n2669) );
AOI22X1TS U3628 ( .A0(n2669), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n2822), .Y(
n2670) );
OAI2BB1X1TS U3629 ( .A0N(n2701), .A1N(n2671), .B0(n2670), .Y(n1010) );
INVX2TS U3630 ( .A(n2672), .Y(n2674) );
NAND2X1TS U3631 ( .A(n2674), .B(n2673), .Y(n2677) );
INVX2TS U3632 ( .A(n2677), .Y(n2675) );
XOR2X1TS U3633 ( .A(n2678), .B(n2677), .Y(n2679) );
AOI22X1TS U3634 ( .A0(n2679), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n2822), .Y(
n2680) );
OAI2BB1X1TS U3635 ( .A0N(n2701), .A1N(n2681), .B0(n2680), .Y(n1014) );
NAND2X1TS U3636 ( .A(n2683), .B(n2682), .Y(n2686) );
INVX2TS U3637 ( .A(n2686), .Y(n2684) );
XNOR2X1TS U3638 ( .A(n2685), .B(n2684), .Y(n2690) );
XNOR2X1TS U3639 ( .A(n2687), .B(n2686), .Y(n2688) );
AOI22X1TS U3640 ( .A0(n2688), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n2768), .Y(
n2689) );
OAI2BB1X1TS U3641 ( .A0N(n2701), .A1N(n2690), .B0(n2689), .Y(n1013) );
INVX2TS U3642 ( .A(n2691), .Y(n2693) );
NAND2X1TS U3643 ( .A(n2693), .B(n2692), .Y(n2696) );
INVX2TS U3644 ( .A(n2696), .Y(n2694) );
XOR2X1TS U3645 ( .A(n2697), .B(n2696), .Y(n2698) );
AOI22X1TS U3646 ( .A0(n2698), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n2768), .Y(
n2699) );
OAI2BB1X1TS U3647 ( .A0N(n2701), .A1N(n2700), .B0(n2699), .Y(n1012) );
BUFX3TS U3648 ( .A(n2702), .Y(n2807) );
NAND2X1TS U3649 ( .A(n2704), .B(n2703), .Y(n2707) );
INVX2TS U3650 ( .A(n2707), .Y(n2705) );
XNOR2X1TS U3651 ( .A(n2706), .B(n2705), .Y(n2711) );
XNOR2X1TS U3652 ( .A(n2708), .B(n2707), .Y(n2709) );
AOI22X1TS U3653 ( .A0(n2709), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n2768), .Y(
n2710) );
OAI2BB1X1TS U3654 ( .A0N(n2807), .A1N(n2711), .B0(n2710), .Y(n1024) );
NAND2X1TS U3655 ( .A(n2713), .B(n2712), .Y(n2716) );
INVX2TS U3656 ( .A(n2716), .Y(n2714) );
XNOR2X1TS U3657 ( .A(n2715), .B(n2714), .Y(n2720) );
XNOR2X1TS U3658 ( .A(n2717), .B(n2716), .Y(n2718) );
AOI22X1TS U3659 ( .A0(n2718), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B1(n2768), .Y(
n2719) );
OAI2BB1X1TS U3660 ( .A0N(n2807), .A1N(n2720), .B0(n2719), .Y(n1028) );
NAND2X1TS U3661 ( .A(n2723), .B(n2722), .Y(n2726) );
INVX2TS U3662 ( .A(n2726), .Y(n2724) );
XOR2X1TS U3663 ( .A(n2727), .B(n2726), .Y(n2728) );
AOI22X1TS U3664 ( .A0(n2728), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2768), .Y(
n2729) );
OAI2BB1X1TS U3665 ( .A0N(n2807), .A1N(n2730), .B0(n2729), .Y(n1029) );
INVX2TS U3666 ( .A(n2731), .Y(n2796) );
INVX2TS U3667 ( .A(n2733), .Y(n2734) );
NAND2X1TS U3668 ( .A(n2737), .B(n2736), .Y(n2742) );
INVX2TS U3669 ( .A(n2742), .Y(n2738) );
XNOR2X1TS U3670 ( .A(n2739), .B(n2738), .Y(n2747) );
XNOR2X1TS U3671 ( .A(n2743), .B(n2742), .Y(n2745) );
AOI22X1TS U3672 ( .A0(n2745), .A1(n2744), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n2768), .Y(
n2746) );
OAI2BB1X1TS U3673 ( .A0N(n2807), .A1N(n2747), .B0(n2746), .Y(n1031) );
NAND2X1TS U3674 ( .A(n2751), .B(n2750), .Y(n2754) );
INVX2TS U3675 ( .A(n2754), .Y(n2752) );
XNOR2X1TS U3676 ( .A(n2753), .B(n2752), .Y(n2757) );
XOR2X1TS U3677 ( .A(n2786), .B(n2754), .Y(n2755) );
AOI22X1TS U3678 ( .A0(n2755), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n2768), .Y(
n2756) );
OAI2BB1X1TS U3679 ( .A0N(n2807), .A1N(n2757), .B0(n2756), .Y(n1032) );
MXI2X1TS U3680 ( .A(n3229), .B(n3172), .S0(n1674), .Y(n1042) );
INVX2TS U3681 ( .A(n2758), .Y(n2760) );
NAND2X1TS U3682 ( .A(n2760), .B(n2759), .Y(n2763) );
INVX2TS U3683 ( .A(n2763), .Y(n2761) );
XOR2X1TS U3684 ( .A(n2763), .B(n2771), .Y(n2764) );
AOI22X1TS U3685 ( .A0(n2764), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n2768), .Y(n2765) );
OAI2BB1X1TS U3686 ( .A0N(n2807), .A1N(n2766), .B0(n2765), .Y(n1039) );
XNOR2X1TS U3687 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
n2767), .Y(n2770) );
AOI22X1TS U3688 ( .A0(n2803), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n2768), .Y(n2769) );
OAI2BB1X1TS U3689 ( .A0N(n2807), .A1N(n2770), .B0(n2769), .Y(n1041) );
OR2X1TS U3690 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2772) );
AOI22X1TS U3691 ( .A0(n2774), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2802), .Y(n2775) );
OAI2BB1X1TS U3692 ( .A0N(n2807), .A1N(n2776), .B0(n2775), .Y(n1040) );
OAI21XLTS U3693 ( .A0(n2796), .A1(n2778), .B0(n2777), .Y(n2783) );
NAND2X1TS U3694 ( .A(n2781), .B(n2780), .Y(n2787) );
INVX2TS U3695 ( .A(n2787), .Y(n2782) );
XNOR2X1TS U3696 ( .A(n2783), .B(n2782), .Y(n2791) );
XNOR2X1TS U3697 ( .A(n2788), .B(n2787), .Y(n2789) );
AOI22X1TS U3698 ( .A0(n2789), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n2802), .Y(
n2790) );
OAI2BB1X1TS U3699 ( .A0N(n2807), .A1N(n2791), .B0(n2790), .Y(n1030) );
INVX2TS U3700 ( .A(n2792), .Y(n2794) );
NAND2X1TS U3701 ( .A(n2794), .B(n2793), .Y(n2800) );
INVX2TS U3702 ( .A(n2800), .Y(n2795) );
XNOR2X1TS U3703 ( .A(n2801), .B(n2800), .Y(n2804) );
AOI22X1TS U3704 ( .A0(n2804), .A1(n2803), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n2802), .Y(n2805) );
OAI2BB1X1TS U3705 ( .A0N(n2807), .A1N(n2806), .B0(n2805), .Y(n1033) );
AOI22X1TS U3706 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(
n2818), .B1(n3266), .Y(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR2BX1TS U3707 ( .AN(beg_fsm_cordic), .B(n2810), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
INVX2TS U3708 ( .A(n2862), .Y(n2857) );
OAI22X1TS U3709 ( .A0(n2857), .A1(n2814), .B0(n2813), .B1(n2812), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U3710 ( .A0(ack_cordic), .A1(n2816), .B0(n2826), .B1(n2815), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
NAND2X1TS U3711 ( .A(n2818), .B(n2817), .Y(n1629) );
INVX2TS U3712 ( .A(n2823), .Y(n2825) );
AOI22X1TS U3713 ( .A0(n2825), .A1(n2820), .B0(n3061), .B1(n2823), .Y(n1626)
);
AOI22X1TS U3714 ( .A0(n2825), .A1(n3061), .B0(n3066), .B1(n2823), .Y(n1625)
);
AOI22X1TS U3715 ( .A0(n2825), .A1(n2822), .B0(n2821), .B1(n2823), .Y(n1622)
);
AOI22X1TS U3716 ( .A0(n2825), .A1(n2824), .B0(n3055), .B1(n2823), .Y(n1621)
);
AOI22X1TS U3717 ( .A0(n2828), .A1(n1709), .B0(n2827), .B1(n2826), .Y(n1620)
);
NAND2X1TS U3718 ( .A(n2830), .B(n2829), .Y(n2831) );
XNOR2X1TS U3719 ( .A(cont_iter_out[3]), .B(n2831), .Y(n1617) );
AOI22X1TS U3720 ( .A0(cont_var_out[0]), .A1(n2833), .B0(n2832), .B1(n3097),
.Y(n1616) );
NAND2X1TS U3721 ( .A(n2837), .B(n2836), .Y(n1613) );
BUFX3TS U3722 ( .A(n2867), .Y(n2980) );
INVX2TS U3723 ( .A(n2869), .Y(n2866) );
AOI22X1TS U3724 ( .A0(n2842), .A1(n2841), .B0(d_ff3_LUT_out[7]), .B1(n2866),
.Y(n2844) );
NAND2X1TS U3725 ( .A(n2844), .B(n2843), .Y(n1601) );
BUFX3TS U3726 ( .A(n2851), .Y(n2852) );
BUFX3TS U3727 ( .A(n2851), .Y(n2847) );
INVX2TS U3728 ( .A(n2852), .Y(n2848) );
BUFX3TS U3729 ( .A(n2852), .Y(n2849) );
INVX2TS U3730 ( .A(n2852), .Y(n2850) );
INVX2TS U3731 ( .A(n2852), .Y(n2853) );
BUFX3TS U3732 ( .A(n2863), .Y(n2954) );
OR3X2TS U3733 ( .A(cont_var_out[1]), .B(n3097), .C(n3267), .Y(n2861) );
BUFX3TS U3734 ( .A(n2856), .Y(n2955) );
INVX2TS U3735 ( .A(n2955), .Y(n2985) );
INVX2TS U3736 ( .A(n2856), .Y(n2886) );
BUFX3TS U3737 ( .A(n2855), .Y(n2990) );
INVX2TS U3738 ( .A(n2855), .Y(n2859) );
BUFX3TS U3739 ( .A(n2855), .Y(n2860) );
INVX2TS U3740 ( .A(n2954), .Y(n2864) );
INVX2TS U3741 ( .A(n2856), .Y(n2952) );
INVX2TS U3742 ( .A(n2855), .Y(n2865) );
BUFX3TS U3743 ( .A(n2861), .Y(n2984) );
BUFX3TS U3744 ( .A(n2855), .Y(n2950) );
BUFX3TS U3745 ( .A(n2863), .Y(n2951) );
INVX2TS U3746 ( .A(n2954), .Y(n2953) );
INVX2TS U3747 ( .A(n2990), .Y(n2991) );
OA22X1TS U3748 ( .A0(d_ff_Xn[1]), .A1(n2093), .B0(n2915), .B1(d_ff2_X[1]),
.Y(n1482) );
OA22X1TS U3749 ( .A0(d_ff_Xn[2]), .A1(n2875), .B0(n2915), .B1(d_ff2_X[2]),
.Y(n1480) );
OA22X1TS U3750 ( .A0(d_ff_Xn[3]), .A1(n2093), .B0(n2874), .B1(d_ff2_X[3]),
.Y(n1478) );
INVX2TS U3751 ( .A(n2915), .Y(n2871) );
INVX2TS U3752 ( .A(n2869), .Y(n2868) );
OA22X1TS U3753 ( .A0(d_ff_Xn[5]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[5]),
.Y(n1474) );
OA22X1TS U3754 ( .A0(d_ff_Xn[6]), .A1(n2093), .B0(n2874), .B1(d_ff2_X[6]),
.Y(n1472) );
OA22X1TS U3755 ( .A0(d_ff_Xn[7]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[7]),
.Y(n1470) );
OA22X1TS U3756 ( .A0(d_ff_Xn[10]), .A1(n2875), .B0(n2091), .B1(d_ff2_X[10]),
.Y(n1464) );
BUFX3TS U3757 ( .A(n2867), .Y(n2989) );
BUFX3TS U3758 ( .A(n2915), .Y(n2873) );
OA22X1TS U3759 ( .A0(d_ff_Xn[12]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[12]),
.Y(n1460) );
OA22X1TS U3760 ( .A0(d_ff_Xn[13]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[13]),
.Y(n1458) );
OA22X1TS U3761 ( .A0(d_ff_Xn[14]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[14]),
.Y(n1456) );
OA22X1TS U3762 ( .A0(d_ff_Xn[16]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[16]),
.Y(n1452) );
OA22X1TS U3763 ( .A0(d_ff_Xn[17]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[17]),
.Y(n1450) );
OA22X1TS U3764 ( .A0(d_ff_Xn[19]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[19]),
.Y(n1446) );
OA22X1TS U3765 ( .A0(d_ff_Xn[20]), .A1(n2875), .B0(n2873), .B1(d_ff2_X[20]),
.Y(n1444) );
INVX2TS U3766 ( .A(n2915), .Y(n2897) );
OA22X1TS U3767 ( .A0(d_ff_Xn[24]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[24]),
.Y(n1437) );
OA22X1TS U3768 ( .A0(d_ff_Xn[25]), .A1(n1688), .B0(n2873), .B1(d_ff2_X[25]),
.Y(n1436) );
OA22X1TS U3769 ( .A0(d_ff_Xn[26]), .A1(n2093), .B0(n2873), .B1(d_ff2_X[26]),
.Y(n1435) );
OA22X1TS U3770 ( .A0(d_ff_Xn[27]), .A1(n1688), .B0(n2874), .B1(d_ff2_X[27]),
.Y(n1434) );
OA22X1TS U3771 ( .A0(n2915), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1688),
.Y(n1433) );
OA22X1TS U3772 ( .A0(d_ff_Xn[29]), .A1(n2875), .B0(n2874), .B1(d_ff2_X[29]),
.Y(n1432) );
NOR2X1TS U3773 ( .A(d_ff2_X[27]), .B(intadd_43_n1), .Y(n2877) );
AOI21X1TS U3774 ( .A0(intadd_43_n1), .A1(d_ff2_X[27]), .B0(n2877), .Y(n2876)
);
OR3X1TS U3775 ( .A(d_ff2_X[27]), .B(d_ff2_X[28]), .C(intadd_43_n1), .Y(n2880) );
NOR2X1TS U3776 ( .A(d_ff2_X[29]), .B(n2880), .Y(n2882) );
AOI21X1TS U3777 ( .A0(d_ff2_X[29]), .A1(n2880), .B0(n2882), .Y(n2881) );
XOR2X1TS U3778 ( .A(d_ff2_X[30]), .B(n2882), .Y(n2883) );
AOI22X1TS U3779 ( .A0(d_ff2_Y[31]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .B1(n2975), .Y(n2885) );
AOI22X1TS U3780 ( .A0(d_ff2_Z[31]), .A1(n2900), .B0(n2062), .B1(d_ff2_X[31]),
.Y(n2884) );
NAND2X1TS U3781 ( .A(n2885), .B(n2884), .Y(n1420) );
OA22X1TS U3782 ( .A0(n2856), .A1(result_add_subt[31]), .B0(d_ff_Yn[31]),
.B1(n2886), .Y(n1418) );
AOI22X1TS U3783 ( .A0(d_ff3_sh_x_out[0]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(n2981), .Y(n2888) );
AOI22X1TS U3784 ( .A0(n2900), .A1(d_ff3_LUT_out[0]), .B0(n2062), .B1(
d_ff3_sh_y_out[0]), .Y(n2887) );
NAND2X1TS U3785 ( .A(n2888), .B(n2887), .Y(n1415) );
AOI22X1TS U3786 ( .A0(d_ff3_sh_x_out[1]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .B1(n2916), .Y(n2891) );
AOI22X1TS U3787 ( .A0(n2889), .A1(d_ff3_LUT_out[1]), .B0(n2931), .B1(
d_ff3_sh_y_out[1]), .Y(n2890) );
NAND2X1TS U3788 ( .A(n2891), .B(n2890), .Y(n1412) );
AOI22X1TS U3789 ( .A0(d_ff3_sh_x_out[2]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B1(n2916), .Y(n2893) );
AOI22X1TS U3790 ( .A0(n2900), .A1(d_ff3_LUT_out[2]), .B0(n2931), .B1(
d_ff3_sh_y_out[2]), .Y(n2892) );
NAND2X1TS U3791 ( .A(n2893), .B(n2892), .Y(n1409) );
BUFX3TS U3792 ( .A(n2906), .Y(n2913) );
INVX2TS U3793 ( .A(n2903), .Y(n2912) );
AOI22X1TS U3794 ( .A0(d_ff3_sh_x_out[4]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .B1(n2943), .Y(n2896) );
BUFX3TS U3795 ( .A(n2894), .Y(n2944) );
AOI22X1TS U3796 ( .A0(n2944), .A1(d_ff3_LUT_out[4]), .B0(n2931), .B1(
d_ff3_sh_y_out[4]), .Y(n2895) );
NAND2X1TS U3797 ( .A(n2896), .B(n2895), .Y(n1403) );
INVX2TS U3798 ( .A(n2915), .Y(n2914) );
AOI22X1TS U3799 ( .A0(d_ff3_sh_x_out[6]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n2981), .Y(n2899) );
AOI22X1TS U3800 ( .A0(n2900), .A1(d_ff3_LUT_out[6]), .B0(n2931), .B1(
d_ff3_sh_y_out[6]), .Y(n2898) );
NAND2X1TS U3801 ( .A(n2899), .B(n2898), .Y(n1397) );
AOI22X1TS U3802 ( .A0(d_ff3_sh_x_out[8]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .B1(n2916), .Y(n2902) );
AOI22X1TS U3803 ( .A0(n2900), .A1(d_ff3_LUT_out[8]), .B0(n2909), .B1(
d_ff3_sh_y_out[8]), .Y(n2901) );
NAND2X1TS U3804 ( .A(n2902), .B(n2901), .Y(n1391) );
AOI22X1TS U3805 ( .A0(d_ff3_sh_x_out[9]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B1(n2943), .Y(n2905) );
AOI22X1TS U3806 ( .A0(n2944), .A1(d_ff3_LUT_out[9]), .B0(n2909), .B1(
d_ff3_sh_y_out[9]), .Y(n2904) );
NAND2X1TS U3807 ( .A(n2905), .B(n2904), .Y(n1388) );
BUFX3TS U3808 ( .A(n2906), .Y(n2920) );
AOI22X1TS U3809 ( .A0(d_ff3_sh_x_out[10]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B1(n2981), .Y(n2908) );
AOI22X1TS U3810 ( .A0(n2944), .A1(d_ff3_LUT_out[10]), .B0(n2931), .B1(
d_ff3_sh_y_out[10]), .Y(n2907) );
NAND2X1TS U3811 ( .A(n2908), .B(n2907), .Y(n1385) );
AOI22X1TS U3812 ( .A0(d_ff3_sh_x_out[12]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(n2943), .Y(n2911) );
AOI22X1TS U3813 ( .A0(n2944), .A1(d_ff3_LUT_out[12]), .B0(n2909), .B1(
d_ff3_sh_y_out[12]), .Y(n2910) );
NAND2X1TS U3814 ( .A(n2911), .B(n2910), .Y(n1379) );
INVX2TS U3815 ( .A(n2915), .Y(n2921) );
AOI22X1TS U3816 ( .A0(d_ff3_sh_x_out[21]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B1(n2981), .Y(n2918) );
AOI22X1TS U3817 ( .A0(n2944), .A1(d_ff3_LUT_out[21]), .B0(n2931), .B1(
d_ff3_sh_y_out[21]), .Y(n2917) );
NAND2X1TS U3818 ( .A(n2918), .B(n2917), .Y(n1352) );
AOI22X1TS U3819 ( .A0(d_ff3_sh_x_out[23]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B1(n2981), .Y(n2924) );
AOI22X1TS U3820 ( .A0(n2944), .A1(d_ff3_LUT_out[23]), .B0(n2931), .B1(
d_ff3_sh_y_out[23]), .Y(n2923) );
NAND2X1TS U3821 ( .A(n2924), .B(n2923), .Y(n1339) );
AOI22X1TS U3822 ( .A0(d_ff3_sh_x_out[24]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B1(n2916), .Y(n2926) );
AOI22X1TS U3823 ( .A0(n2944), .A1(d_ff3_LUT_out[24]), .B0(n2931), .B1(
d_ff3_sh_y_out[24]), .Y(n2925) );
NAND2X1TS U3824 ( .A(n2926), .B(n2925), .Y(n1337) );
AOI22X1TS U3825 ( .A0(d_ff3_sh_x_out[25]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B1(n2916), .Y(n2928) );
AOI22X1TS U3826 ( .A0(n2944), .A1(d_ff3_LUT_out[25]), .B0(n2931), .B1(
d_ff3_sh_y_out[25]), .Y(n2927) );
NAND2X1TS U3827 ( .A(n2928), .B(n2927), .Y(n1335) );
AOI22X1TS U3828 ( .A0(d_ff3_sh_x_out[26]), .A1(n2930), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B1(n2943), .Y(n2933) );
AOI22X1TS U3829 ( .A0(n2944), .A1(d_ff3_LUT_out[26]), .B0(n2931), .B1(
d_ff3_sh_y_out[26]), .Y(n2932) );
NAND2X1TS U3830 ( .A(n2933), .B(n2932), .Y(n1333) );
NOR2X1TS U3831 ( .A(d_ff2_Y[27]), .B(intadd_42_n1), .Y(n2935) );
AOI21X1TS U3832 ( .A0(intadd_42_n1), .A1(d_ff2_Y[27]), .B0(n2935), .Y(n2934)
);
OR3X1TS U3833 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(intadd_42_n1), .Y(n2937) );
NOR2X1TS U3834 ( .A(d_ff2_Y[29]), .B(n2937), .Y(n2941) );
AOI21X1TS U3835 ( .A0(d_ff2_Y[29]), .A1(n2937), .B0(n2941), .Y(n2939) );
XOR2X1TS U3836 ( .A(d_ff2_Y[30]), .B(n2941), .Y(n2942) );
AOI22X1TS U3837 ( .A0(d_ff2_Y[30]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B1(n2943), .Y(n2946) );
AOI22X1TS U3838 ( .A0(n2944), .A1(d_ff2_Z[30]), .B0(n2209), .B1(d_ff2_X[30]),
.Y(n2945) );
NAND2X1TS U3839 ( .A(n2946), .B(n2945), .Y(n1324) );
OAI22X1TS U3840 ( .A0(n2949), .A1(n2948), .B0(n2947), .B1(n3081), .Y(n1323)
);
INVX2TS U3841 ( .A(n2954), .Y(n2956) );
AOI22X1TS U3842 ( .A0(d_ff2_Y[5]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n2965), .Y(n2958) );
AOI22X1TS U3843 ( .A0(n2962), .A1(d_ff2_Z[5]), .B0(n2209), .B1(d_ff2_X[5]),
.Y(n2957) );
NAND2X1TS U3844 ( .A(n2958), .B(n2957), .Y(n1264) );
AOI22X1TS U3845 ( .A0(d_ff2_Y[6]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B1(n2965), .Y(n2960) );
AOI22X1TS U3846 ( .A0(n2962), .A1(d_ff2_Z[6]), .B0(n2209), .B1(d_ff2_X[6]),
.Y(n2959) );
NAND2X1TS U3847 ( .A(n2960), .B(n2959), .Y(n1262) );
AOI22X1TS U3848 ( .A0(d_ff2_Y[7]), .A1(n2961), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B1(n2965), .Y(n2964) );
AOI22X1TS U3849 ( .A0(n2962), .A1(d_ff2_Z[7]), .B0(n2062), .B1(d_ff2_X[7]),
.Y(n2963) );
NAND2X1TS U3850 ( .A(n2964), .B(n2963), .Y(n1260) );
AOI22X1TS U3851 ( .A0(d_ff2_Y[10]), .A1(n2066), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n2965), .Y(n2968) );
AOI22X1TS U3852 ( .A0(n2966), .A1(d_ff2_Z[10]), .B0(n2062), .B1(d_ff2_X[10]),
.Y(n2967) );
NAND2X1TS U3853 ( .A(n2968), .B(n2967), .Y(n1254) );
AOI22X1TS U3854 ( .A0(d_ff2_Y[24]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n2975), .Y(n2970) );
AOI22X1TS U3855 ( .A0(n2889), .A1(d_ff2_Z[24]), .B0(n2972), .B1(d_ff2_X[24]),
.Y(n2969) );
NAND2X1TS U3856 ( .A(n2970), .B(n2969), .Y(n1226) );
AOI22X1TS U3857 ( .A0(d_ff2_Y[25]), .A1(n2971), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .B1(n2975), .Y(n2974) );
AOI22X1TS U3858 ( .A0(n2032), .A1(d_ff2_Z[25]), .B0(n2972), .B1(d_ff2_X[25]),
.Y(n2973) );
NAND2X1TS U3859 ( .A(n2974), .B(n2973), .Y(n1224) );
AOI22X1TS U3860 ( .A0(d_ff2_Y[28]), .A1(n2976), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(n2975), .Y(n2978) );
AOI22X1TS U3861 ( .A0(n2032), .A1(d_ff2_Z[28]), .B0(n2033), .B1(d_ff2_X[28]),
.Y(n2977) );
NAND2X1TS U3862 ( .A(n2978), .B(n2977), .Y(n1218) );
INVX2TS U3863 ( .A(n2983), .Y(n2981) );
AOI22X1TS U3864 ( .A0(n2991), .A1(n3090), .B0(n3173), .B1(n2990), .Y(n1206)
);
XNOR2X1TS U3865 ( .A(n2994), .B(n2993), .Y(n2995) );
CLKBUFX2TS U3866 ( .A(n3057), .Y(n3007) );
AOI21X1TS U3867 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .A1(
n1657), .B0(n2996), .Y(n2997) );
XNOR2X1TS U3868 ( .A(n2998), .B(n2997), .Y(n2999) );
OAI22X1TS U3869 ( .A0(n3003), .A1(n3002), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B1(n3135), .Y(n3005)
);
XNOR2X1TS U3870 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .Y(n3004) );
XOR2X1TS U3871 ( .A(n3005), .B(n3004), .Y(n3006) );
BUFX3TS U3872 ( .A(n3057), .Y(n3020) );
INVX2TS U3873 ( .A(n1660), .Y(n3059) );
INVX2TS U3874 ( .A(n3061), .Y(n3025) );
OAI222X1TS U3875 ( .A0(n3013), .A1(n3134), .B0(n1657), .B1(n3012), .C0(n3069), .C1(n3011), .Y(n1109) );
OAI222X1TS U3876 ( .A0(n3013), .A1(n3086), .B0(n3136), .B1(n3012), .C0(n3118), .C1(n3011), .Y(n1108) );
OAI222X1TS U3877 ( .A0(n3013), .A1(n3087), .B0(n1658), .B1(n3012), .C0(n3117), .C1(n3011), .Y(n1107) );
OAI2BB2XLTS U3878 ( .B0(n3017), .B1(n1664), .A0N(n3055), .A1N(
result_add_subt[22]), .Y(n1101) );
BUFX3TS U3879 ( .A(n1683), .Y(n3029) );
OAI2BB2XLTS U3880 ( .B0(n3018), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[15]), .Y(n1098) );
OAI2BB2XLTS U3881 ( .B0(n3019), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[18]), .Y(n1095) );
OAI2BB2XLTS U3882 ( .B0(n3021), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[21]), .Y(n1092) );
BUFX3TS U3883 ( .A(n3057), .Y(n3033) );
OAI2BB2XLTS U3884 ( .B0(n3022), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[19]), .Y(n1089) );
OAI2BB2XLTS U3885 ( .B0(n3023), .B1(n1664), .A0N(n3029), .A1N(
result_add_subt[20]), .Y(n1086) );
OAI2BB2XLTS U3886 ( .B0(n3024), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[17]), .Y(n1083) );
OAI2BB2XLTS U3887 ( .B0(n3026), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[4]), .Y(n1080) );
INVX2TS U3888 ( .A(n3061), .Y(n3041) );
OAI2BB2XLTS U3889 ( .B0(n3027), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[6]), .Y(n1077) );
OAI2BB2XLTS U3890 ( .B0(n3028), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[13]), .Y(n1074) );
OAI2BB2XLTS U3891 ( .B0(n3030), .B1(n1663), .A0N(n3029), .A1N(
result_add_subt[16]), .Y(n1071) );
BUFX3TS U3892 ( .A(n1683), .Y(n3046) );
OAI2BB2XLTS U3893 ( .B0(n3031), .B1(n1663), .A0N(n3046), .A1N(
result_add_subt[8]), .Y(n1068) );
OAI2BB2XLTS U3894 ( .B0(n3032), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[11]), .Y(n1065) );
OAI2BB2XLTS U3895 ( .B0(n3034), .B1(n1664), .A0N(n3046), .A1N(
result_add_subt[14]), .Y(n1062) );
OAI2BB2XLTS U3896 ( .B0(n3035), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[10]), .Y(n1059) );
OAI2BB2XLTS U3897 ( .B0(n3036), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[12]), .Y(n1056) );
OAI2BB2XLTS U3898 ( .B0(n3042), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[3]), .Y(n1022) );
OAI2BB2XLTS U3899 ( .B0(n3043), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[2]), .Y(n1006) );
OAI2BB2XLTS U3900 ( .B0(n3044), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[7]), .Y(n999) );
OAI2BB2XLTS U3901 ( .B0(n3045), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[0]), .Y(n992) );
OAI2BB2XLTS U3902 ( .B0(n3047), .B1(n3049), .A0N(n3046), .A1N(
result_add_subt[1]), .Y(n985) );
OAI2BB2XLTS U3903 ( .B0(n3048), .B1(n3049), .A0N(n1638), .A1N(
result_add_subt[9]), .Y(n978) );
INVX2TS U3904 ( .A(n3064), .Y(n3058) );
OAI2BB2XLTS U3905 ( .B0(n3050), .B1(n1663), .A0N(n3055), .A1N(
result_add_subt[5]), .Y(n971) );
BUFX3TS U3906 ( .A(n3057), .Y(n3060) );
INVX2TS U3907 ( .A(n1660), .Y(n3063) );
INVX2TS U3908 ( .A(n3064), .Y(n3062) );
initial $sdf_annotate("CORDIC_Arch3_syn.sdf");
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ae_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ae_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_ae_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ae_e
//
// No `defines in this module
module inst_ae_e
//
// Generated Module inst_ae
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_ae_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:18 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_1_V
`define SKY130_FD_SC_HD__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:14:13 05/10/2015
// Design Name:
// Module Name: Expansion
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Expansion(
right,
ouput
);
input [32:1] right;
output reg [48:1] ouput;
wire [32:1] right;
always @ (right)
begin
ouput[1]<= right[32];
ouput[2]<= right[1];
ouput[3]<= right[2];
ouput[4]<= right[3];
ouput[5]<= right[4];
ouput[6]<= right[5];
ouput[7]<= right[4];
ouput[8]<= right[5];
ouput[9]<= right[6];
ouput[10]<= right[7];
ouput[11]<= right[8];
ouput[12]<= right[9];
ouput[13]<= right[8];
ouput[14]<= right[9];
ouput[15]<= right[10];
ouput[16]<= right[11];
ouput[17]<= right[12];
ouput[18]<= right[13];
ouput[19]<= right[12];
ouput[20]<= right[13];
ouput[21]<= right[14];
ouput[22]<= right[15];
ouput[23]<= right[16];
ouput[24]<= right[17];
ouput[25]<= right[16];
ouput[26]<= right[17];
ouput[27]<= right[18];
ouput[28]<= right[19];
ouput[29]<= right[20];
ouput[30]<= right[21];
ouput[31]<= right[20];
ouput[32]<= right[21];
ouput[33]<= right[22];
ouput[34]<= right[23];
ouput[35]<= right[24];
ouput[36]<= right[25];
ouput[37]<= right[24];
ouput[38]<= right[25];
ouput[39]<= right[26];
ouput[40]<= right[27];
ouput[41]<= right[28];
ouput[42]<= right[29];
ouput[43]<= right[28];
ouput[44]<= right[29];
ouput[45]<= right[30];
ouput[46]<= right[31];
ouput[47]<= right[32];
ouput[48]<= right[1];
end
endmodule
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module nexthop(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4 localram0(
.DO (data_out[3:0]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[3:0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram0.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000011111111111;
defparam localram0.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram1(
.DO (data_out[7:4]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[7:4]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram1.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram2(
.DO (data_out[11:8]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[11:8]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram2.INIT_00 = 256'h00000000000000000000000000000000000000000000000000000F08C444000C;
defparam localram2.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram3(
.DO (data_out[15:12]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[15:12]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram3.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram4(
.DO (data_out[19:16]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[19:16]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram4.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram5(
.DO (data_out[23:20]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[23:20]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram5.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram6(
.DO (data_out[27:24]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[27:24]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram6.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram7(
.DO (data_out[31:28]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[31:28]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram7.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdl_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdl_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_bufp1_pa_l, arbpc1_pcxdp_q0_hold_bufp1_pa,
arbpc1_pcxdp_qsel0_bufp1_pa_l, arbpc1_pcxdp_qsel1_bufp1_pa,
arbpc1_pcxdp_shift_bufp1_px_l, arbpc3_pcxdp_grant_bufp1_pa_l,
arbpc3_pcxdp_q0_hold_bufp1_pa, arbpc3_pcxdp_qsel0_bufp1_pa_l,
arbpc3_pcxdp_qsel1_bufp1_pa, arbpc3_pcxdp_shift_bufp1_px_l,
arbpc4_pcxdp_grant_bufp1_pa_l, arbpc4_pcxdp_q0_hold_bufp1_pa,
arbpc4_pcxdp_qsel0_bufp1_pa_l, arbpc4_pcxdp_qsel1_bufp1_pa,
arbpc4_pcxdp_shift_bufp1_px_l
);
output arbpc1_pcxdp_grant_pa ;
output arbpc1_pcxdp_q0_hold_pa_l ;
output arbpc1_pcxdp_qsel0_pa ;
output arbpc1_pcxdp_qsel1_pa_l ;
output arbpc1_pcxdp_shift_px ;
output arbpc3_pcxdp_grant_pa ;
output arbpc3_pcxdp_q0_hold_pa_l ;
output arbpc3_pcxdp_qsel0_pa ;
output arbpc3_pcxdp_qsel1_pa_l ;
output arbpc3_pcxdp_shift_px ;
output arbpc4_pcxdp_grant_pa ;
output arbpc4_pcxdp_q0_hold_pa_l ;
output arbpc4_pcxdp_qsel0_pa ;
output arbpc4_pcxdp_qsel1_pa_l ;
output arbpc4_pcxdp_shift_px ;
input arbpc1_pcxdp_grant_bufp1_pa_l;
input arbpc1_pcxdp_q0_hold_bufp1_pa;
input arbpc1_pcxdp_qsel0_bufp1_pa_l;
input arbpc1_pcxdp_qsel1_bufp1_pa;
input arbpc1_pcxdp_shift_bufp1_px_l;
input arbpc3_pcxdp_grant_bufp1_pa_l;
input arbpc3_pcxdp_q0_hold_bufp1_pa;
input arbpc3_pcxdp_qsel0_bufp1_pa_l;
input arbpc3_pcxdp_qsel1_bufp1_pa;
input arbpc3_pcxdp_shift_bufp1_px_l;
input arbpc4_pcxdp_grant_bufp1_pa_l;
input arbpc4_pcxdp_q0_hold_bufp1_pa;
input arbpc4_pcxdp_qsel0_bufp1_pa_l;
input arbpc4_pcxdp_qsel1_bufp1_pa;
input arbpc4_pcxdp_shift_bufp1_px_l;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp1_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp1_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp1_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp1_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp1_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp1_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp1_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp1_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp1_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp1_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp1_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp1_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp1_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp1_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp1_px_l;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_0_V
`define SKY130_FD_SC_LP__O32A_0_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_0 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_4_V
`define SKY130_FD_SC_HDLL__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_4_V
|
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