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`timescale 1ns / 1ps
`include "../rtl/setup.v"
//`define DEBUG
module top (
input cpci_reset, // CPCI
input cpci_clk,
input gtx_clk, // common TX clk reference 125MHz.
// RGMII interfaces for 4 MACs
output [3:0] rgmii_0_txd,
output rgmii_0_tx_ctl,
output rgmii_0_txc,
input [3:0] rgmii_0_rxd,
input rgmii_0_rx_ctl,
input rgmii_0_rxc,
output [3:0] rgmii_1_txd,
output rgmii_1_tx_ctl,
output rgmii_1_txc,
input [3:0] rgmii_1_rxd,
input rgmii_1_rx_ctl,
input rgmii_1_rxc,
output [3:0] rgmii_2_txd,
output rgmii_2_tx_ctl,
output rgmii_2_txc,
input [3:0] rgmii_2_rxd,
input rgmii_2_rx_ctl,
input rgmii_2_rxc,
output [3:0] rgmii_3_txd,
output rgmii_3_tx_ctl,
output rgmii_3_txc,
input [3:0] rgmii_3_rxd,
input rgmii_3_rx_ctl,
input rgmii_3_rxc,
input PCLK2, // PCI Clock
inout [31:0] AD_IO, // PCI Ports -- do not modify names!
output AD_HIZ,
inout [3:0] CBE_IO,
output CBE_HIZ,
inout PAR_IO,
output PAR_HIZ,
inout FRAME_IO,
output FRAME_HIZ,
inout TRDY_IO,
output TRDY_HIZ,
inout IRDY_IO,
output IRDY_HIZ,
inout STOP_IO,
output STOP_HIZ,
inout DEVSEL_IO,
output DEVSEL_HIZ,
input IDSEL_I,
output INTA_O,
inout PERR_IO,
output PERR_HIZ,
inout SERR_IO,
output SERR_HIZ,
output REQ_O,
input GNT_I,
input [3:0] cpci_id,
output PASS_REQ,
input PASS_READY,
output [31:0] cpci_debug_data,
output DEBUG_PIN0,
output DEBUG_PIN1
);
assign reset = ~cpci_reset;
//assign sys_clk = cpci_clk;
wire rgmii_0_tx_clk, rgmii_1_tx_clk, rgmii_2_tx_clk, rgmii_3_tx_clk;
wire [7:0] gmii_0_txd, gmii_1_txd, gmii_2_txd, gmii_3_txd;
wire [7:0] gmii_0_rxd, gmii_1_rxd, gmii_2_rxd, gmii_3_rxd;
wire gmii_0_link, gmii_1_link, gmii_2_link, gmii_3_link;
wire [1:0] gmii_0_speed, gmii_1_speed, gmii_2_speed, gmii_3_speed;
wire gmii_0_duplex,gmii_1_duplex,gmii_2_duplex,gmii_3_duplex;
IBUF ibufg_gtx_clk (.I(gtx_clk), .O(gtx_clk_ibufg));
assign sys_clk = gtx_clk_ibufg;
wire tx_clk0, tx_clk90;
DCM RGMII_TX_DCM (
.CLKIN(gtx_clk_ibufg),
.CLKFB(rgmii_tx_clk_int),
.DSSEN(1'b0),
.PSINCDEC(1'b0),
.PSEN(1'b0),
.PSCLK(1'b0),
.RST(reset),
.CLK0(tx_clk0),
.CLK90(tx_clk90),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.PSDONE(),
.STATUS(),
.LOCKED());
BUFGMUX BUFGMUX_TXCLK (
.O(rgmii_tx_clk_int),
.I0(tx_clk0),
.I1(tx_clk90), // not used
.S(1'b0)
);
BUFGMUX BUFGMUX_TXCLK90 (
.O(rgmii_tx_clk90),
.I1(tx_clk0), // not used
.I0(tx_clk90),
.S(1'b0)
);
FDDRRSE gmii_0_tx_clk_ddr_iob (
.Q (rgmii_0_txc_obuf),
.D0(1'b1),
.D1(1'b0),
.C0(rgmii_tx_clk90),
.C1(~rgmii_tx_clk90),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE gmii_1_tx_clk_ddr_iob (
.Q (rgmii_1_txc_obuf),
.D0(1'b1),
.D1(1'b0),
.C0(rgmii_tx_clk90),
.C1(~rgmii_tx_clk90),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE gmii_2_tx_clk_ddr_iob (
.Q (rgmii_2_txc_obuf),
.D0(1'b1),
.D1(1'b0),
.C0(rgmii_tx_clk90),
.C1(~rgmii_tx_clk90),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE gmii_3_tx_clk_ddr_iob (
.Q (rgmii_3_txc_obuf),
.D0(1'b1),
.D1(1'b0),
.C0(rgmii_tx_clk90),
.C1(~rgmii_tx_clk90),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
OBUF drive_rgmii_0_txc (.I(rgmii_0_txc_obuf), .O(rgmii_0_txc));
OBUF drive_rgmii_1_txc (.I(rgmii_1_txc_obuf), .O(rgmii_1_txc));
OBUF drive_rgmii_2_txc (.I(rgmii_2_txc_obuf), .O(rgmii_2_txc));
OBUF drive_rgmii_3_txc (.I(rgmii_3_txc_obuf), .O(rgmii_3_txc));
assign not_rgmii_tx_clk = ~rgmii_tx_clk_int;
assign rgmii_tx_clk = not_rgmii_tx_clk;
rgmii_io rgmii_0_io (
.rgmii_txd (rgmii_0_txd),
.rgmii_tx_ctl (rgmii_0_tx_ctl),
.rgmii_tx_clk_int (rgmii_tx_clk_int),
.not_rgmii_tx_clk (not_rgmii_tx_clk),
.rgmii_rxd (rgmii_0_rxd),
.rgmii_rx_ctl (rgmii_0_rx_ctl),
.rgmii_rx_clk (~rgmii_0_rxc),
.gmii_txd (gmii_0_txd),
.gmii_tx_en (gmii_0_tx_en),
.gmii_tx_er (gmii_0_tx_er),
.gmii_rxd (gmii_0_rxd),
.gmii_rx_dv (gmii_0_rx_dv),
.gmii_rx_er (gmii_0_rx_er),
.link (gmii_0_link),
.speed (gmii_0_speed),
.duplex (gmii_0_duplex),
.reset (reset)
);
rgmii_io rgmii_1_io (
.rgmii_txd (rgmii_1_txd),
.rgmii_tx_ctl (rgmii_1_tx_ctl),
.rgmii_tx_clk_int (rgmii_tx_clk_int),
.not_rgmii_tx_clk (not_rgmii_tx_clk),
.rgmii_rxd (rgmii_1_rxd),
.rgmii_rx_ctl (rgmii_1_rx_ctl),
.rgmii_rx_clk (~rgmii_1_rxc),
.gmii_txd (gmii_1_txd),
.gmii_tx_en (gmii_1_tx_en),
.gmii_tx_er (gmii_1_tx_er),
.gmii_rxd (gmii_1_rxd),
.gmii_rx_dv (gmii_1_rx_dv),
.gmii_rx_er (gmii_1_rx_er),
.link (gmii_1_link),
.speed (gmii_1_speed),
.duplex (gmii_1_duplex),
.reset (reset)
);
`ifdef ENABE_RGMII2
rgmii_io rgmii_2_io (
.rgmii_txd (rgmii_2_txd),
.rgmii_tx_ctl (rgmii_2_tx_ctl),
.rgmii_tx_clk_int (rgmii_tx_clk_int),
.not_rgmii_tx_clk (not_rgmii_tx_clk),
.rgmii_rxd (rgmii_2_rxd),
.rgmii_rx_ctl (rgmii_2_rx_ctl),
.rgmii_rx_clk (~rgmii_2_rxc),
.gmii_txd (gmii_2_txd),
.gmii_tx_en (gmii_2_tx_en),
.gmii_tx_er (gmii_2_tx_er),
.gmii_rxd (gmii_2_rxd),
.gmii_rx_dv (gmii_2_rx_dv),
.gmii_rx_er (gmii_2_rx_er),
.link (gmii_2_link),
.speed (gmii_2_speed),
.duplex (gmii_2_duplex),
.reset (reset)
);
`else
assign rgmii_2_txd = 4'hz;
assign rgmii_2_tx_ctl = 1'h0;
assign rgmii_2_txc = 1'hz;
`endif
`ifdef ENABE_RGMII3
rgmii_io rgmii_3_io (
.rgmii_txd (rgmii_3_txd),
.rgmii_tx_ctl (rgmii_3_tx_ctl),
.rgmii_tx_clk_int (rgmii_tx_clk_int),
.not_rgmii_tx_clk (not_rgmii_tx_clk),
.rgmii_rxd (rgmii_3_rxd),
.rgmii_rx_ctl (rgmii_3_rx_ctl),
.rgmii_rx_clk (~rgmii_3_rxc),
.gmii_txd (gmii_3_txd),
.gmii_tx_en (gmii_3_tx_en),
.gmii_tx_er (gmii_3_tx_er),
.gmii_rxd (gmii_3_rxd),
.gmii_rx_dv (gmii_3_rx_dv),
.gmii_rx_er (gmii_3_rx_er),
.link (gmii_3_link),
.speed (gmii_3_speed),
.duplex (gmii_3_duplex),
.reset (reset)
);
`else
assign rgmii_3_txd = 4'hz;
assign rgmii_3_tx_ctl = 1'h0;
assign rgmii_3_txc = 1'hz;
`endif
//-----------------------------------
// PCI user registers
//-----------------------------------
wire tx0_enable;
wire tx0_ipv6;
wire tx0_fullroute;
wire tx0_req_arp;
wire [15:0] tx0_frame_len;
wire [31:0] tx0_inter_frame_gap;
wire [31:0] tx0_ipv4_srcip;
wire [47:0] tx0_src_mac;
wire [31:0] tx0_ipv4_gwip;
wire [127:0] tx0_ipv6_srcip;
wire [127:0] tx0_ipv6_dstip;
wire [47:0] tx0_dst_mac;
wire [31:0] tx0_ipv4_dstip;
wire [31:0] tx0_pps;
wire [31:0] tx0_throughput;
wire [31:0] tx0_ipv4_ip;
wire [31:0] rx1_pps;
wire [31:0] rx1_throughput;
wire [23:0] rx1_latency;
wire [31:0] rx1_ipv4_ip;
wire [31:0] rx2_pps;
wire [31:0] rx2_throughput;
wire [23:0] rx2_latency;
wire [31:0] rx2_ipv4_ip;
wire [31:0] rx3_pps;
wire [31:0] rx3_throughput;
wire [23:0] rx3_latency;
wire [31:0] rx3_ipv4_ip;
measure measure_inst (
.sys_rst(reset),
.sys_clk(sys_clk),
.pci_clk(PCLK2),
.gmii_0_tx_clk(rgmii_tx_clk),
.gmii_0_txd(gmii_0_txd),
.gmii_0_tx_en(gmii_0_tx_en),
.gmii_0_rxd(gmii_0_rxd),
.gmii_0_rx_dv(gmii_0_rx_dv),
.gmii_0_rx_clk(rgmii_0_rxc),
.gmii_1_tx_clk(rgmii_tx_clk),
.gmii_1_txd(gmii_1_txd),
.gmii_1_tx_en(gmii_1_tx_en),
.gmii_1_rxd(gmii_1_rxd),
.gmii_1_rx_dv(gmii_1_rx_dv),
.gmii_1_rx_clk(rgmii_1_rxc),
.gmii_2_tx_clk(rgmii_tx_clk),
.gmii_2_txd(gmii_2_txd),
.gmii_2_tx_en(gmii_2_tx_en),
.gmii_2_rxd(gmii_2_rxd),
.gmii_2_rx_dv(gmii_2_rx_dv),
.gmii_2_rx_clk(rgmii_2_rxc),
.gmii_3_tx_clk(rgmii_tx_clk),
.gmii_3_txd(gmii_3_txd),
.gmii_3_tx_en(gmii_3_tx_en),
.gmii_3_rxd(gmii_3_rxd),
.gmii_3_rx_dv(gmii_3_rx_dv),
.gmii_3_rx_clk(rgmii_3_rxc),
.tx0_enable(tx0_enable),
.tx0_ipv6(tx0_ipv6),
.tx0_fullroute(tx0_fullroute),
.tx0_req_arp(tx0_req_arp),
.tx0_frame_len(tx0_frame_len),
.tx0_inter_frame_gap(tx0_inter_frame_gap),
.tx0_ipv4_srcip(tx0_ipv4_srcip),
.tx0_src_mac(tx0_src_mac),
.tx0_ipv4_gwip(tx0_ipv4_gwip),
.tx0_ipv6_srcip(tx0_ipv6_srcip),
.tx0_ipv6_dstip(tx0_ipv6_dstip),
.tx0_dst_mac(tx0_dst_mac),
.tx0_ipv4_dstip(tx0_ipv4_dstip),
.tx0_pps(tx0_pps),
.tx0_throughput(tx0_throughput),
.tx0_ipv4_ip(tx0_ipv4_ip),
.rx1_pps(rx1_pps),
.rx1_throughput(rx1_throughput),
.rx1_latency(rx1_latency),
.rx1_ipv4_ip(rx1_ipv4_ip),
.rx2_pps(rx2_pps),
.rx2_throughput(rx2_throughput),
.rx2_latency(rx2_latency),
.rx2_ipv4_ip(rx2_ipv4_ip),
.rx3_pps(rx3_pps),
.rx3_throughput(rx3_throughput),
.rx3_latency(rx3_latency),
.rx3_ipv4_ip(rx3_ipv4_ip)
);
assign gmii_0_tx_er = 1'b0;
assign gmii_1_tx_er = 1'b0;
assign gmii_2_tx_er = 1'b0;
assign gmii_3_tx_er = 1'b0;
pci pci_inst (
.sys_rst(reset),
.pci_clk(PCLK2),
.AD_IO(AD_IO),
.AD_HIZ(AD_HIZ),
.CBE_IO(CBE_IO),
.CBE_HIZ(CBE_HIZ),
.PAR_IO(PAR_IO),
.PAR_HIZ(PAR_HIZ),
.FRAME_IO(FRAME_IO),
.FRAME_HIZ(FRAME_HIZ),
.TRDY_IO(TRDY_IO),
.TRDY_HIZ(TRDY_HIZ),
.IRDY_IO(IRDY_IO),
.IRDY_HIZ(IRDY_HIZ),
.STOP_IO(STOP_IO),
.STOP_HIZ(STOP_HIZ),
.DEVSEL_IO(DEVSEL_IO),
.DEVSEL_HIZ(DEVSEL_HIZ),
.IDSEL_I(IDSEL_I),
.INTA_O(INTA_O),
.PERR_IO(PERR_IO),
.PERR_HIZ(PERR_HIZ),
.SERR_IO(SERR_IO),
.SERR_HIZ(SERR_HIZ),
.REQ_O(REQ_O),
.GNT_I(GNT_I),
.cpci_id(cpci_id),
.PASS_REQ(PASS_REQ),
.PASS_READY(PASS_READY),
.cpci_debug_data(cpci_debug_data),
.tx0_enable(tx0_enable),
.tx0_ipv6(tx0_ipv6),
.tx0_fullroute(tx0_fullroute),
.tx0_req_arp(tx0_req_arp),
.tx0_frame_len(tx0_frame_len),
.tx0_inter_frame_gap(tx0_inter_frame_gap),
.tx0_ipv4_srcip(tx0_ipv4_srcip),
.tx0_src_mac(tx0_src_mac),
.tx0_ipv4_gwip(tx0_ipv4_gwip),
.tx0_ipv6_srcip(tx0_ipv6_srcip),
.tx0_ipv6_dstip(tx0_ipv6_dstip),
.tx0_dst_mac(tx0_dst_mac),
.tx0_ipv4_dstip(tx0_ipv4_dstip),
.tx0_pps(tx0_pps),
.tx0_throughput(tx0_throughput),
.tx0_ipv4_ip(tx0_ipv4_ip),
.rx1_pps(rx1_pps),
.rx1_throughput(rx1_throughput),
.rx1_latency(rx1_latency),
.rx1_ipv4_ip(rx1_ipv4_ip),
.rx2_pps(rx2_pps),
.rx2_throughput(rx2_throughput),
.rx2_latency(rx2_latency),
.rx2_ipv4_ip(rx2_ipv4_ip),
.rx3_pps(rx3_pps),
.rx3_throughput(rx3_throughput),
.rx3_latency(rx3_latency),
.rx3_ipv4_ip(rx3_ipv4_ip)
);
`ifdef DEBUG
//-----------------------------------
// Chipscope Pro Module
//-----------------------------------
wire [35 : 0] CONTROL;
wire [ 7: 0] TRIG;
wire [31: 0] DATA;
cs_icon INST_ICON (
.CONTROL0(CONTROL)
);
cs_ila INST_ILA (
.CLK(rgmii_1_rxc),
.CONTROL(CONTROL),
.TRIG0(TRIG),
.DATA(DATA)
);
assign DATA[7:0] = gmii_0_rxd[7:0];
assign DATA[8] = gmii_0_rx_dv;
assign DATA[9] = gmii_0_rx_er;
assign DATA[10] = gmii_0_link;
assign DATA[12:11] = gmii_0_speed[1:0];
assign DATA[13] = gmii_0_duplex;
assign DATA[23:16] = gmii_1_rxd[7:0];
//assign DATA[24] = gmii_1_rx_dv;
//assign DATA[25] = gmii_1_rx_er;
assign DATA[26] = gmii_1_link;
assign DATA[28:27] = gmii_1_speed[1:0];
assign DATA[29] = gmii_1_duplex;
assign DATA[31:30] = 2'h0;
assign TRIG[0] = gmii_0_rx_dv;
//assign TRIG[1] = gmii_1_rx_dv;
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkbuf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_PP_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ram_16x1k_dp.v when simulating
// the core, ram_16x1k_dp. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ram_16x1k_dp(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input enb;
input [1 : 0] web;
input [9 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 22nd May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: alt_lm32.v,v 1.7 2017/08/23 09:17:11 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/rtl/alt_lm32.v,v $
//
//=============================================================
// altera message_level Level1
`include "lm32_include.v"
// Top level for terasIC/Altera DE1 platform based lm32 system
module alt_lm32 (
// Clock Input
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
// Push Button
KEY, // Pushbutton[3:0]
// DPDT Switch
SW, // Toggle Switch[9:0]
// 7-SEG Display
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
// LED
LEDG, // LED Green[7:0]
LEDR, // LED Red[9:0]
// UART
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
// SDRAM Interface
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 1
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
// Flash Interface
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 22 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
// SRAM Interface
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
// SD_Card Interface
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
// USB JTAG link
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
// I2C
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
// PS2
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
// VGA
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red[3:0]
VGA_G, // VGA Green[3:0]
VGA_B, // VGA Blue[3:0]
// Audio CODEC
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
// GPIO
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
parameter sys_clk_period_ps = 20000;
parameter sys_clk_freq_khz = 1000000/(sys_clk_period_ps/1000);
// Clock Input
input [1:0] CLOCK_24; // 24 MHz
input [1:0] CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
// Push Button
input [3:0] KEY; // Pushbutton[3:0]
// DPDT Switch
input [9:0] SW; // Toggle Switch[9:0]
// 7-SEG Display
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
// LED
output [7:0] LEDG; // LED Green[7:0]
output [9:0] LEDR; // LED Red[9:0]
// UART
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
// SDRAM Interface
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
// Flash Interface
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
// SRAM Interface
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM High-byte Data Mask
output SRAM_LB_N; // SRAM Low-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
// SD Card Interface
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
// I2C
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
// PS2
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
// USB JTAG link
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
// VGA
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output [3:0] VGA_R; // VGA Red[3:0]
output [3:0] VGA_G; // VGA Green[3:0]
output [3:0] VGA_B; // VGA Blue[3:0]
// Audio CODEC
output AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
output AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
// GPIO
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// sram_clk synchronous to sys_clk, but 180 deg phase shift.
// ___ ___ ___
// sys_clk _/ \___/ \___/
// _ _ _ _ _ _
// sram_clk \_/ \_/ \_/ \_/ \_/
//
wire sys_clk;
wire sdram_clk;
wire sram_clk;
wire mTCK;
wire nreset;
// SRAM interconnect from controller
wire [17:0] mSR_ADDR;
wire [15:0] mRS2SR_DATA;
wire mSR_OE;
wire mSR_WE;
// SDRAM
wire [15:0] mSDR_DATAC2M;
wire [15:0] mSDR_DATAM2C;
wire mSDR_Done;
wire [21:0] mSDR_ADDR;
wire mSDR_RD;
wire mSDR_WR;
// Async Port Select
wire [1:0] mSR_Select;
// CPU's external interrupt lines
wire [`LM32_INTERRUPT_RNG] interrupt;
// Interrupts from peripherals
wire uart_int;
wire timer_int;
wire ps2_int;
// CPU's bus interconnect
wire wb_ack;
wire wb_ack_ctrl;
wire wb_ack_uart;
wire wb_ack_timer;
wire [31:0] wb_dat_ctrl_i;
wire [7:0] wb_dat_uart_o;
wire [31:0] wb_dat_timer_o;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
wire [31:0] wb_adr;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
// LED control from usb_jtag_cmd
wire [9:0] cmd_ledr;
// Control wires from controller
wire [31:0] status;
wire cpu_done;
wire resetcpu;
// SDRAM non-tristate output data and control
wire SRAM_DQ_OE;
wire [15:0] SRAM_DQ_OUT;
// Address decode
wire sram_stb;
wire uart0_stb;
wire timer_stb;
wire local_stb;
wire [35:0] gpio0_out;
wire [35:0] gpio1_out;
wire [35:0] gpio0_oe;
wire [35:0] gpio1_oe;
wire I2C_SDAT_OUT;
// Unused outputs drive to something 'inactive'
assign FL_ADDR = 22'h000000;
assign FL_WE_N = 1'b1;
assign FL_RST_N = 1'b1;
assign FL_OE_N = 1'b1;
assign FL_CE_N = 1'b1;
assign SD_CLK = 1'b0;
assign VGA_HS = 1'b0;
assign VGA_VS = 1'b0;
assign VGA_R = 4'h0;
assign VGA_G = 4'h0;
assign VGA_B = 4'h0;
assign AUD_DACDAT = 1'b0;
assign AUD_XCK = 1'b0;
// All unused inout ports turn to tri-state
assign FL_DQ = 8'hzz;
assign SD_DAT = 1'bz;
assign SD_DAT3 = 1'bz;
assign SD_CMD = 1'bz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_BCLK = 1'bz;
// Reset from pushbutton input
assign nreset = KEY[0]; // Keys are on a schmitt trigger, so should be bounce free.
// Tri-state SRAM data
assign SRAM_DQ = SRAM_DQ_OE ? SRAM_DQ_OUT : 16'hzzzz;
// Tristate control for GPIO
genvar i;
generate
for (i = 0; i < 36; i = i + 1)
begin : GPIO_ASSIGN
assign GPIO_0[i] = gpio0_oe[i] ? gpio0_out[i] : 1'bz;
assign GPIO_1[i] = gpio1_oe[i] ? gpio1_out[i] : 1'bz;
end
endgenerate
// Tristate for I2C
assign I2C_SDAT = I2C_SDAT_OUT ? 1'bz : 1'b0;
// Connect peripheral interrupts to CPU external interrupt pins
assign interrupt = {{`LM32_INTERRUPT_WIDTH-4{1'b0}}, ps2_int, timer_int, uart_int};
// Read LEDs controlled by command decoder ORed with internal status.
assign LEDR = cmd_ledr | {{9{1'b0}}, cpu_done, ~resetcpu, mSR_Select[0]};
// Export the DRAM clock
assign DRAM_CLK = sdram_clk;
CLK_LOCK p0 (.inclk (TCK),
.outclk (mTCK)
);
// PLL for 50MHz input to 50/100MHz output
PLL1 p1 (.inclk0 (CLOCK_50),
.c0 (sys_clk),
.c1 (sdram_clk),
.c2 (sram_clk)
);
// USB-JTAG command decoder
usb_jtag_cmd u1 (
// Control
.iCLK (sys_clk),
.iRST_n (nreset),
//JTAG
.TDO (TDO),
.TDI (TDI),
.TCS (TCS),
.TCK (mTCK),
// LED + SEG7
.oLED_GREEN (LEDG),
.oLED_RED (cmd_ledr),
// Seven segment display
.iDIG (status),
.oSEG0 (HEX0),
.oSEG1 (HEX1),
.oSEG2 (HEX2),
.oSEG3 (HEX3),
// SRAM
.iSR_DATA (SRAM_DQ),
.oSR_DATA (mRS2SR_DATA),
.oSR_ADDR (mSR_ADDR),
.oSR_WE_N (mSR_WE),
.oSR_OE_N (mSR_OE),
.oSR_Select (mSR_Select),
// SDRAM
.oSDR_DATA (mSDR_DATAC2M),
.iSDR_DATA (mSDR_DATAM2C),
.oSDR_ADDR (mSDR_ADDR),
.iSDR_Done (mSDR_Done),
.oSDR_WR (mSDR_WR),
.oSDR_RD (mSDR_RD)
);
// System controller
controller u2 (.sys_clk (sys_clk),
.sram_clk (sram_clk),
.nreset (nreset),
.wb_cyc (wb_cyc),
.wb_stb_sram (sram_stb),
.wb_stb_local (local_stb),
.wb_we (wb_we),
.wb_sel (wb_sel),
.wb_ack (wb_ack_ctrl),
.wb_adr (wb_adr),
.wb_dat_o (wb_dat_o),
.wb_dat_i (wb_dat_ctrl_i),
.mSR_Select (mSR_Select[0]),
.mSR_WE (mSR_WE),
.mSR_OE (mSR_OE),
.mSR_ADDR (mSR_ADDR),
.mRS2SR_DATA (mRS2SR_DATA),
.mSDR_DATAC2M (mSDR_DATAC2M),
.mSDR_DATAM2C (mSDR_DATAM2C),
.mSDR_ADDR (mSDR_ADDR),
.mSDR_Done (mSDR_Done),
.mSDR_WR (mSDR_WR),
.mSDR_RD (mSDR_RD),
.status (status),
.cpu_done (cpu_done),
.resetcpu (resetcpu),
.gpio0_in (GPIO_0),
.gpio1_in (GPIO_1),
.gpio0_out (gpio0_out),
.gpio1_out (gpio1_out),
.gpio0_oe (gpio0_oe),
.gpio1_oe (gpio1_oe),
.sw (SW),
.key (KEY),
.ps2_clk (PS2_CLK),
.ps2_dat (PS2_DAT),
.ps2_int (ps2_int),
.I2C_SDAT_IN (I2C_SDAT),
.I2C_SDAT_OUT (I2C_SDAT_OUT),
.I2C_SCLK (I2C_SCLK),
.SRAM_DQ (SRAM_DQ),
.SRAM_DQ_OUT (SRAM_DQ_OUT),
.SRAM_DQ_OE (SRAM_DQ_OE),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_OE_N (SRAM_OE_N),
.SRAM_WE_N (SRAM_WE_N),
.SRAM_CE_N (SRAM_CE_N)
);
defparam u2.u2.REF_PER = 600, // 64000 ns / 4096 rows / sys_clk_period in ns - margin
u2.u2.SC_CL = 3,
u2.u2.SC_RRD = 7,
u2.u2.SC_PM = 1,
u2.u2.SC_BL = 1;
// Address decode for CPU data bus
address_decode u3 (
.sys_clk (sys_clk),
.nreset (nreset),
// Data bus inputs
.wb_adr (wb_adr),
.wb_ack_uart (wb_ack_uart),
.wb_ack_timer (wb_ack_timer),
.wb_ack_ctrl (wb_ack_ctrl),
.wb_stb (wb_stb),
.wb_dat_uart_o (wb_dat_uart_o),
.wb_dat_timer_o (wb_dat_timer_o),
.wb_dat_ctrl_i (wb_dat_ctrl_i),
// Decoded strobes (peripheral selects)
.sram_stb (sram_stb),
.uart0_stb (uart0_stb),
.timer_stb (timer_stb),
.local_stb (local_stb),
// Returned ACK and read data
.wb_ack (wb_ack),
.wb_dat_i (wb_dat_i)
);
// LatticeSemi UART
uart_core #(.CLK_IN_MHZ (50),
.BAUD_RATE (115200))
u4 (
// System clock and reset
.CLK (sys_clk),
.RESET (resetcpu),
// Wishbone interface signals
.UART_CYC_I (wb_cyc),
.UART_STB_I (uart0_stb),
.UART_WE_I (wb_we),
.UART_LOCK_I (1'b0),
.UART_CTI_I (3'b000),
.UART_BTE_I (2'b00),
.UART_ADR_I (wb_adr[5:2]),
.UART_DAT_I (wb_dat_o[7:0]),
.UART_SEL_I (wb_sel[0]),
.UART_ACK_O (wb_ack_uart),
.UART_RTY_O (),
.UART_ERR_O (),
.UART_DAT_O (wb_dat_uart_o),
.INTR (uart_int),
// Receiver interface
.SIN (UART_RXD),
.SOUT (UART_TXD)
);
// LatticeSemi Timer
timer #(.PERIOD_WIDTH(32),
.PERIOD_NUM(0))
u5 (
//system clock and reset
.CLK_I (sys_clk),
.RST_I (resetcpu),
.S_ADR_I (wb_adr),
.S_DAT_I (wb_dat_o),
.S_WE_I (wb_we),
.S_STB_I (timer_stb),
.S_CYC_I (wb_cyc),
.S_CTI_I (3'b000),
.S_BTE_I (2'b00),
.S_LOCK_I (1'b0),
.S_SEL_I (wb_sel),
.S_DAT_O (wb_dat_timer_o),
.S_ACK_O (wb_ack_timer),
.S_RTY_O (),
.S_ERR_O (),
.S_INT_O (timer_int),
.RSTREQ_O (),
.TOPULSE_O ()
);
// LatticeMico32 CPU
lm32_wrap u6 (
// Timing
.sys_clk (sys_clk),
.resetcpu (resetcpu),
// Interrupts
.interrupt (interrupt),
// Master CPU bus (wishbone)
.m_ack (wb_ack),
.m_adr (wb_adr),
.m_cyc (wb_cyc),
.m_dat_i (wb_dat_i),
.m_dat_o (wb_dat_o),
.m_sel (wb_sel),
.m_stb (wb_stb),
.m_we (wb_we)
);
endmodule
|
`include "or1200_defines.v"
module or1200_top(
// System
clk_i, rst_i, pic_ints_i, clmode_i,
// Instruction WISHBONE INTERFACE
iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
iwb_cti_o, iwb_bte_o,
`endif
// Data WISHBONE INTERFACE
dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
dwb_cti_o, dwb_bte_o,
`endif
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
//
// I/O
//
//
// System
//
input clk_i;
input rst_i;
input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
input [ppic_ints-1:0] pic_ints_i;
//
// Instruction WISHBONE interface
//
input iwb_clk_i; // clock input
input iwb_rst_i; // reset input
input iwb_ack_i; // normal termination
input iwb_err_i; // termination w/ error
input iwb_rty_i; // termination w/ retry
input [dw-1:0] iwb_dat_i; // input data bus
output iwb_cyc_o; // cycle valid output
output [aw-1:0] iwb_adr_o; // address bus outputs
output iwb_stb_o; // strobe output
output iwb_we_o; // indicates write transfer
output [3:0] iwb_sel_o; // byte select outputs
output [dw-1:0] iwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output iwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] iwb_cti_o; // cycle type identifier
output [1:0] iwb_bte_o; // burst type extension
`endif
//
// Data WISHBONE interface
//
input dwb_clk_i; // clock input
input dwb_rst_i; // reset input
input dwb_ack_i; // normal termination
input dwb_err_i; // termination w/ error
input dwb_rty_i; // termination w/ retry
input [dw-1:0] dwb_dat_i; // input data bus
output dwb_cyc_o; // cycle valid output
output [aw-1:0] dwb_adr_o; // address bus outputs
output dwb_stb_o; // strobe output
output dwb_we_o; // indicates write transfer
output [3:0] dwb_sel_o; // byte select outputs
output [dw-1:0] dwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output dwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] dwb_cti_o; // cycle type identifier
output [1:0] dwb_bte_o; // burst type extension
`endif
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Power Management
//
input pm_cpustall_i;
output [3:0] pm_clksd_o;
output pm_dc_gate_o;
output pm_ic_gate_o;
output pm_dmmu_gate_o;
output pm_immu_gate_o;
output pm_tt_gate_o;
output pm_cpu_gate_o;
output pm_wakeup_o;
output pm_lvolt_o;
endmodule
|
/*
* Memory Interface
*
* Our memory is a ROM with 64 words, 16 bits per word
* can satisfy the spec of MemBank in EPC Gen2 Protocol
*
* We can't provide our ROM verilog module
* because it's generated by Artisan Components, Inc.
* and it's CONFIDENTIAL and PROPRIETARY SOFTWARE OF ARTISAN COMPONENTS, INC.
*
* You can design a 64x16 register file to verify this module
*/
`timescale 1us / 1ns
module mem_if
(
output reg rd_data,
output reg rd_complete,
output reg [5:0]A,
output CEN,
input [18:0]addr,
input [15:0]Q,
input clk_if,
input rst_for_new_package
);
wire clk_if_n;
reg d_1clk;
reg d_flag;
reg [3:0]d_cnt;
reg [5:0]A_cnt;
assign CEN = (addr == 19'h0)? 1'b1 : 1'b0;
assign clk_if_n = ~clk_if;
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_data <= 1'b0;
else rd_data <= Q[d_cnt];
end
always@(*) begin
if(~addr[18]) begin
if(addr[15:8] == 8'b0000_0000) A = 6'h5 + A_cnt;
else A = 6'h11 - {2'b0, addr[15:12]} + A_cnt;
end
else begin
case(addr[17:16])
2'b00 : A = addr[15:8] + A_cnt;
2'b01 : A = addr[15:8] + 6'h4 + A_cnt;
2'b10 : A = addr[15:8] + 6'h27 + A_cnt;
2'b11 : A = 6'h29;
endcase
end
end
always@(posedge clk_if_n or negedge rst_for_new_package) begin
if(~rst_for_new_package) A_cnt <= 6'h0;
else if(d_cnt == 4'h0) A_cnt <= A_cnt + 6'h1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_1clk <= 1'b0;
else d_1clk <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_flag <= 1'b0;
else if(~addr[18] & addr[15:8] != 8'h0) d_flag <= 1'b1;
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) d_cnt <= 4'hf;
else begin
if(~addr[18] & addr[15:8] != 8'h0 & ~d_flag) d_cnt <= addr[11:8];
else if(d_1clk) d_cnt <= d_cnt - 4'h1;
end
end
always@(posedge clk_if or negedge rst_for_new_package) begin
if(~rst_for_new_package) rd_complete <= 1'b0;
else begin
if(~addr[18]) begin
if(A == 6'h12) rd_complete <= 1'b1;
end
else begin
if(addr[17:16] == 2'b00 & addr[7:0] == 8'h0 & addr[15:8] < 8'h4 & A == 6'h4) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] < 8'he & A == 6'h12) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b01 & addr[7:0] == 8'h0 & addr[15:8] > 8'hd & addr[15:8] < 8'h23 & A == 6'h27) rd_complete <= 1'b1;
else if(addr[17:16] == 2'b10 & addr[7:0] == 8'h0 & addr[15:8] < 8'h2 & A == 6'h29) rd_complete <= 1'b1;
else if(addr[7:0] != 0 & A_cnt == addr[7:0]) rd_complete <= 1'b1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Register Block Misc.
// File : der_misc.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the top level register block for Imagine-MI
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_misc
(
input de_clk, /* drawing engine clock input */
input hb_clk, /* host bus clock input */
input prst, /* Pattern Reset */
input cr_pulse,
input [1:0] ps_sel_2, // buf_ctrl_2[10:9]
input bc_co,
input [31:0] mf_sorg_2, /* multi function sorg. */
input [31:0] mf_dorg_2, /* multi function dorg. */
input [1:0] apat_1,
input sd_selector, // buf_ctrl_2[4]
output reg prst_1,
output hb_ca_rdy,
output de_ca_rdy,
output ps16s_2,
output ps565s_2,
output [31:0] de_sorg_2, /* source origin register output */
output [31:0] de_dorg_2, /* destination origin register output */
output [27:0] sorg_2, /* source origin register output */
output [27:0] dorg_2, /* destination origin register output */
output or_apat_1
);
// reg hb_ca_rdy_d;
// reg hb_ca_rdy_ddd;
// reg de_ca_rdy_d;
// reg de_ca_rdy_ddd;
// reg ca_rdy;
// wire crdy_rstn;
// wire hb_ca_rdy_dd;
// wire de_ca_rdy_dd;
assign or_apat_1 = |apat_1;
always @(posedge de_clk) prst_1 <= prst;
assign ps16s_2 = ~ps_sel_2[1] & ps_sel_2[0];
assign ps565s_2 = &ps_sel_2[1:0];
/*
// Cache ready for HB and DE
assign crdy_rstn = rstn;
always @(posedge cr_pulse or negedge crdy_rstn)
if(!crdy_rstn) ca_rdy <= 1'b0;
else ca_rdy <= 1'b1;
always @(posedge hb_clk) hb_ca_rdy_d <= ca_rdy;
always @(posedge hb_clk) hb_ca_rdy_ddd <= hb_ca_rdy_d;
assign hb_ca_rdy = ca_rdy | hb_ca_rdy_ddd;
always @(posedge de_clk) de_ca_rdy_d <= ca_rdy;
always @(posedge de_clk) de_ca_rdy_ddd <= de_ca_rdy_d;
assign de_ca_rdy = (ca_rdy & de_ca_rdy_ddd) | bc_co;
*/
assign hb_ca_rdy = 1'b1;
assign de_ca_rdy = 1'b1;
assign de_sorg_2 = {32{sd_selector}} & mf_sorg_2;
assign de_dorg_2 = {32{sd_selector}} & mf_dorg_2;
// assign sorg_2 = {28{~sd_selector}} & mf_sorg_2[31:4];
// assign dorg_2 = {28{~sd_selector}} & mf_dorg_2[31:4];
assign sorg_2 = {28{~sd_selector}} & {6'h0, mf_sorg_2[25:4]};
assign dorg_2 = {28{~sd_selector}} & {6'h0, mf_dorg_2[25:4]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_PP_BLACKBOX_V
|
`timescale 1ns/10ps
module clock_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("11.288659 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("49.772727 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_BLACKBOX_V
`define SKY130_FD_SC_LS__O41A_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: rd_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module has all the timing control for generating "compare data"
// to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module rd_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6"
parameter MEM_TYPE = "DDR3",
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
input mode_load_i,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
output reg cmd_start_o,
// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
output user_bl_cnt_is_1_o,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
// connect from mcb_rd_empty when used as rd_data_gen in sp6
// connect from rd_data_valid in v6
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
);
//
wire [31:0] prbs_data;
reg cmd_start;
reg [31:0] adata;
reg [31:0] hdata;
reg [31:0] ndata;
reg [31:0] w1data;
reg [NUM_DQ_PINS*4-1:0] v6_w1data;
reg [31:0] w0data;
reg [DWIDTH-1:0] data;
reg cmd_rdy;
reg [BL_WIDTH:0]user_burst_cnt;
reg [31:0] w3data;
reg prefetch;
assign data_port_fifo_rdy = data_rdy_i;
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if (data_port_fifo_rdy)
if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6")
|| (user_burst_cnt == 2 && FAMILY == "VIRTEX6")
)
user_bl_cnt_is_1 <= #TCQ 1'b1;
else
user_bl_cnt_is_1 <= #TCQ 1'b0;
end
//reg cmd_start_b;
always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch)
begin
cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i };
end
else if(data_port_fifo_rdy)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <= #TCQ 'd0;
end
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
//data_valid_o logic
always @( posedge clk_i)
begin
if ( rst_i[0] )
prefetch <= #TCQ 1'b1;
else if (data_port_fifo_rdy || cmd_start)
prefetch <= #TCQ 1'b0;
else if (user_burst_cnt == 0 && ~data_port_fifo_rdy)
prefetch <= #TCQ 1'b1;
end
assign cmd_rdy_o = cmd_rdy ;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch ))
cmd_rdy <= #TCQ 1'b0;
else if ((data_port_fifo_rdy && user_burst_cnt == 2 && MEM_BURST_LEN == 8) ||
(data_port_fifo_rdy && user_burst_cnt == 2 && MEM_BURST_LEN == 4))
cmd_rdy <= #TCQ 1'b1;
end
always @ (data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
data_valid_o = data_port_fifo_rdy;
else
data_valid_o = data_port_fifo_rdy;
/*
generate
if (FAMILY == "SPARTAN6")
begin : SP6_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
end
endgenerate*/
//generate
//if (FAMILY == "VIRTEX6")
//begin : V_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
//end
//endgenerate
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_int_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE
|
//wb_gpio.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_gpio
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x02
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:8
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_BOTH_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_TIMEOUT
*/
`include "project_defines.v"
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0,
parameter DEFAULT_INTERRUPT_BOTH_EDGE = 0,
parameter DEFAULT_INTERRUPT_TIMEOUT = 0
)(
input clk,
input rst,
output [31:0] debug,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
output reg [31:0] gpio_out,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
localparam INTERRUPT_BOTH_EDGE = 32'h00000005;
localparam INTERRUPT_TIMEOUT = 32'h00000006;
localparam READ_CLOCK_RATE = 32'h00000007;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_enable;
reg [31:0] interrupt_edge;
reg [31:0] interrupt_both_edge;
reg [31:0] interrupt_timeout_count;
reg [31:0] interrupt_count;
reg clear_interrupts;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : tsbuf
assign gpio[i] = gpio_direction[i] ? gpio_out[i] : gpio_in[i];
end
endgenerate
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
//reset gpio's
gpio_out <= 32'h00000000;
gpio_direction <= 32'h00000000;
//reset interrupts
interrupt_enable <= DEFAULT_INTERRUPT_MASK;
interrupt_edge <= DEFAULT_INTERRUPT_EDGE;
interrupt_both_edge <= DEFAULT_INTERRUPT_BOTH_EDGE;
interrupt_timeout_count <= DEFAULT_INTERRUPT_TIMEOUT;
clear_interrupts <= 0;
end
else begin
clear_interrupts <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
GPIO: begin
$display("user wrote %h", i_wbs_dat);
gpio_out <= i_wbs_dat & gpio_direction;
end
GPIO_OUTPUT_ENABLE: begin
$display("%h ->gpio_direction", i_wbs_dat);
gpio_direction <= i_wbs_dat;
end
INTERRUPTS: begin
$display("trying to write %h to interrupts?!", i_wbs_dat);
//can't write to the interrupt
end
INTERRUPT_ENABLE: begin
$display("%h -> interrupt enable", i_wbs_dat);
interrupt_enable <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_EDGE: begin
$display("%h -> interrupt_edge", i_wbs_dat);
interrupt_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_BOTH_EDGE: begin
$display("%h -> interrupt_both_edge", i_wbs_dat);
interrupt_both_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_TIMEOUT: begin
interrupt_timeout_count <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
if (!o_wbs_ack) begin //Fix double reads
//read request
case (i_wbs_adr)
GPIO: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio;
clear_interrupts <= 1;
end
GPIO_OUTPUT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio_direction;
end
INTERRUPTS: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupts;
clear_interrupts <= 1;
end
INTERRUPT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_enable;
end
INTERRUPT_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_edge;
end
INTERRUPT_BOTH_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_both_edge;
end
INTERRUPT_TIMEOUT: begin
o_wbs_dat <= interrupt_timeout_count;
end
READ_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
end
o_wbs_ack <= 1;
end
end
end
end
//interrupts
reg [31:0] prev_gpio_in;
//this is the change
wire [31:0] pos_gpio_edge;
wire [31:0] neg_gpio_edge;
assign neg_gpio_edge = ((~interrupt_edge | interrupt_both_edge) & (interrupt_enable & ( prev_gpio_in & ~gpio_in)));
assign pos_gpio_edge = (( interrupt_edge | interrupt_both_edge) & (interrupt_enable & (~prev_gpio_in & gpio_in)));
/*
initial begin
$monitor ("%t, interrupts: %h, mask: %h, edge: %h, gpio_edge: %h", $time, interrupts, interrupt_enable, interrupt_edge, gpio_edge);
end
*/
assign debug[0] = gpio[2];
assign debug[1] = gpio[3];
assign debug[2] = interrupt_enable[2];
assign debug[3] = interrupt_enable[3];
assign debug[4] = interrupt_edge[2];
assign debug[5] = interrupt_edge[3];
assign debug[6] = prev_gpio_in[2];
assign debug[7] = prev_gpio_in[3];
assign debug[8] = pos_gpio_edge[2];
assign debug[9] = pos_gpio_edge[3];
assign debug[10] = neg_gpio_edge[2];
assign debug[11] = neg_gpio_edge[3];
assign debug[12] = interrupts[2];
assign debug[13] = interrupts[3];
assign debug[14] = clear_interrupts;
always @ (posedge clk) begin
if (rst) begin
interrupt_count <= 0;
interrupts <= 32'h00000000;
o_wbs_int <= 0;
end
else begin
//user requests to clear the interrupts
if (clear_interrupts) begin
interrupts <= 32'h00000000;
end
if ((pos_gpio_edge > 0) || (neg_gpio_edge > 0)) begin
//check to see if there was a negative or postive edge that occured
interrupts <= (pos_gpio_edge | neg_gpio_edge);
$display ("found an interrupt in the slave");
end
//Implement timeout behavior
if (interrupts == 0) begin
interrupt_count <= 0;
end
if ((interrupts > 0) && (interrupt_timeout_count > 0)) begin
if (interrupt_count < interrupt_timeout_count) begin
interrupt_count <= interrupt_count + 1;
end
else begin
interrupts <= 32'h00000000;
interrupt_count <= 0;
end
end
//Set the wishbone interrupt pin on this module
if (interrupts > 0) begin
o_wbs_int <= 1;
end
else begin
o_wbs_int <= 0;
end
prev_gpio_in <= gpio_in;
end
end
endmodule
|
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
//assign avs_s0_readdata = 32'b00000000000000000000000000000000;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] data_in;
reg led_out;
reg [31:0] reg_kernel[8:0];
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
// WRITE LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
data_in <= 32'b0;
Reg_Status_Write <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b1000: begin
led_out <= 1'b0;
data_in <= avs_s0_writedata;
end
4'b1001: begin
led_out <= 1'b1;
data_in <= avs_s0_writedata;
end
default:begin
led_out <= avs_s0_writedata[0];
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write)begin
Reg_Status_Write <= 1'b0;
end else begin
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read) begin
case (avs_s0_address[3:0])
4'b0000:reg_out <= 32'h00000000;
4'b0001:reg_out <= 32'h00000001;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_padder1;
// Inputs
reg [31:0] in;
reg [1:0] byte_num;
// Outputs
wire [31:0] out;
reg [31:0] wish;
// Instantiate the Unit Under Test (UUT)
padder1 uut (
.in(in),
.byte_num(byte_num),
.out(out)
);
initial begin
// Initialize Inputs
in = 0;
byte_num = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in = 32'h90ABCDEF;
byte_num = 0;
wish = 32'h01000000;
check;
byte_num = 1;
wish = 32'h90010000;
check;
byte_num = 2;
wish = 32'h90AB0100;
check;
byte_num = 3;
wish = 32'h90ABCD01;
check;
$display("Good!");
$finish;
end
task check;
begin
#(`P);
if (out !== wish)
begin
$display("E");
$finish;
end
end
endtask
endmodule
`undef P
|
// arSRLFIFO.v
// Copyright (c) 2009-2012 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// 2009-05-10 ssiegel Creation in VHDL
// 2009-11-01 ssiegel Converted to Verilog from VHDL
// 2010-07-23 ssiegel Logic change for empty and full
// 2011-06-17 ssiegel No logic change, scrub comments, formatting
// 2012-01-20 ssiegel Place dat[] update logic outside of reset conditional
module arSRLFIFO (CLK,RST_N,ENQ,DEQ,FULL_N,EMPTY_N,D_IN,D_OUT,CLR);
parameter width = 128;
parameter l2depth = 5;
localparam depth = 2**l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input[width-1:0] D_IN;
output[width-1:0] D_OUT;
reg[l2depth-1:0] pos; // head position
reg[width-1:0] dat[depth-1:0]; // SRL FIFO
reg empty, full;
integer i;
// Note that proper SRL inference in XST 13.4 seems to require that there be
// a separate, not-conditional-upon-reset always block for the SRL data
// array to be updated in...
always@(posedge CLK) begin
if (ENQ) begin
for(i=depth-1;i>0;i=i-1) dat[i] <= dat[i-1];
dat[0] <= D_IN;
end
end
always@(posedge CLK) begin
if(!RST_N || CLR) begin
pos <= 1'b0;
empty <= 1'b1;
full <= 1'b0;
end else begin
if (!ENQ && DEQ) pos <= pos - 1;
if ( ENQ && !DEQ) pos <= pos + 1;
empty <= ((pos==0 && !ENQ) || (pos==1 && (DEQ&&!ENQ)));
full <= ((pos==(depth-1) && !DEQ) || (pos==(depth-2) && (ENQ&&!DEQ)));
end
end
assign FULL_N = !full;
assign EMPTY_N = !empty;
assign D_OUT = dat[pos-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_SYMBOL_V
`define SKY130_FD_SC_MS__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:44:08 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_xbar_0 -prefix
// design_1_xbar_0_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module design_1_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
`timescale 1ns/10ps
module controller_testbench();
reg [31:0] ibustm[0:31], ibus, Ref_Aselect[0:31], Ref_Bselect[0:31],Ref_Dselect[0:31];
reg clk, Ref_Imm[0:31], Ref_Cin[0:31];
reg [2:0] Ref_S[0:31];
wire [2:0] S;
wire Cin,Imm;
wire [31:0] Aselect,Bselect, Dselect;
reg [31:0] dontcare;
reg neglect;
reg [2:0] neg;
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SADD = 3'b010;
parameter SSUB = 3'b011;
parameter SXOR = 3'b000;
parameter SAND = 3'b110;
parameter SOR = 3'b100;
controller dut(.ibus(ibus), .clk(clk), .Cin(Cin), .Imm(Imm), .S(S) , .Aselect(Aselect) , .Bselect(Bselect), .Dselect(Dselect));
initial begin
dontcare = 32'hxxxxxxxx;
neglect = 1'bx;
neg = 3'bxxx;
// ----------
// 1. Begin test clear SUB R13, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[0]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
ibustm[1]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
Ref_Aselect[1] = 32'b00000000000000000000000000000001; //input 1
Ref_Bselect[1] = 32'b00000000000000000000000000000001; //input 1
Ref_Dselect[1] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[1] =1'bx;
Ref_Cin[1] =1'bx;
Ref_S[1] = 3'bxxx;
// ----------
// 2. ADDI R1, R0, #FFFF
// ----------
// opcode source1 dest Immediate...
ibustm[2]={ADDI, 5'b00000, 5'b00001, 16'hFFFF};
Ref_Aselect[2] = 32'b00000000000000000000000000000001; //input2
Ref_Bselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input2
Ref_Dselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input2
Ref_Imm[2] =1'b0; //input1
Ref_Cin[2] =1'b1; //input1
Ref_S[2] = SSUB; //input1
// ----------
// 3. ADDI R0, R0, #FFFF
// ----------
// opcode source1 dest Immediate...
ibustm[3]={ADDI, 5'b00000, 5'b00000, 16'hFFFF};
Ref_Aselect[3] = 32'b0000000000000000000000000000001; //input3
Ref_Bselect[3] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input3
Ref_Dselect[3] = 32'b0000000000000000010000000000000; //input1
Ref_Imm[3] =1'b1; //input2
Ref_Cin[3] =1'b0; //input2
Ref_S[3] = SADD; //input2
// ----------
// 4. ADDI R30, R1,#AFC0
// ----------
// opcode source1 dest Immediate...
ibustm[4]={ADDI, 5'b00001, 5'b11110, 16'hAFC0};
Ref_Aselect[4] = 32'b00000000000000000000000000000010; //input4
Ref_Bselect[4] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input4
Ref_Dselect[4] = 32'b00000000000000000000000000000010; //input2
Ref_Imm[4] =1'b1; //input3
Ref_Cin[4] =1'b0; //input3
Ref_S[4] = SADD; //input3
// ----------
// 5. SUB R0, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[5]={Rformat, 5'b00000, 5'b00000, 5'b00000, 5'b00000, SUB};
Ref_Aselect[5] = 32'b0000000000000000000000000000001; //input5
Ref_Bselect[5] = 32'b0000000000000000000000000000001; //input5
Ref_Dselect[5] = 32'b0000000000000000000000000000001; //input3
Ref_Imm[5] =1'b1; //input4
Ref_Cin[5] =1'b0; //input4
Ref_S[5] = SADD; //input4
// ---------- // 6. XORI R3, R0, #8CCB
// ----------
// opcode source1 dest Immediate...
ibustm[6]={XORI, 5'b00000, 5'b00011, 16'h8CCB};
Ref_Aselect[6] = 32'b00000000000000000000000000000001; //input6
Ref_Bselect[6] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input6
Ref_Dselect[6] = 32'b01000000000000000000000000000000; //input4
Ref_Imm[6] =1'b0; //input5
Ref_Cin[6] =1'b1; //input5
Ref_S[6] = SSUB; //input5
// ----------
// 7. ORI R21, R0, #F98B
// ----------
// opcode source1 dest Immediate...
ibustm[7]={ORI, 5'b00000, 5'b10101, 16'hF98B};
Ref_Aselect[7] = 32'b00000000000000000000000000000001;//input7
Ref_Bselect[7] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input7
Ref_Dselect[7] = 32'b00000000000000000000000000000001; //input5
Ref_Imm[7] =1'b1; //input6
Ref_Cin[7] =1'b0; //input6
Ref_S[7] = SXOR; //input6
// ----------
// 8. XOR R16, R1, R3
// ----------
// opcode source1 source2 dest shift Function...
ibustm[8]={Rformat, 5'b00001, 5'b00011, 5'b10000, 5'b00000, XOR};
Ref_Aselect[8] = 32'b00000000000000000000000000000010; //input8
Ref_Bselect[8] = 32'b00000000000000000000000000001000; //input8
Ref_Dselect[8] = 32'b00000000000000000000000000001000; //input6
Ref_Imm[8] =1'b1; //input7
Ref_Cin[8] =1'b0; //input7
Ref_S[8] = SOR; //input7
// ----------
// 9. SUBI R31, R21, #0030
// ----------
// opcode source1 dest Immediate...
ibustm[9]={SUBI, 5'b10101, 5'b11111, 16'h0030};
Ref_Aselect[9] = 32'b00000000001000000000000000000000;//input9
Ref_Bselect[9] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input9
Ref_Dselect[9] = 32'b00000000001000000000000000000000;//input7
Ref_Imm[9] =1'b0; //input8
Ref_Cin[9] =1'b0; //input8
Ref_S[9] = SXOR; //input8
// ----------
// 10. XOR R5, R16, R21
// ----------
// opcode source1 source2 dest shift Function...
ibustm[10]={Rformat, 5'b10000, 5'b10101, 5'b00101, 5'b00000, XOR};
Ref_Aselect[10] = 32'b00000000000000010000000000000000; //input10
Ref_Bselect[10] = 32'b00000000001000000000000000000000; //input10
Ref_Dselect[10] = 32'b00000000000000010000000000000000; //input8
Ref_Imm[10] =1'b1; //input9
Ref_Cin[10] =1'b1; //input9
Ref_S[10] = SSUB; //input9
// ------------
// 11. ORI R10, R0, #34FB
// ------------
// opcode source1 dest Immediate...
ibustm[11]={ORI, 5'b00000, 5'b01010, 16'h34FB};
Ref_Aselect[11] = 32'b00000000000000000000000000000001;//input11
Ref_Bselect[11] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input11
Ref_Dselect[11] = 32'b10000000000000000000000000000000;//input9
Ref_Imm[11] =1'b0; //input10
Ref_Cin[11] =1'b0; //input10
Ref_S[11] = SXOR; //input10
// ------------
// 12. XORI R18, R1, #0B31
// ------------
// opcode source1 dest Immediate...
ibustm[12]={XORI, 5'b00001, 5'b10010, 16'h0B31};
Ref_Aselect[12] = 32'b00000000000000000000000000000010; //input12
Ref_Bselect[12] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input12
Ref_Dselect[12] = 32'b00000000000000000000000000100000; //input10
Ref_Imm[12] =1'b1; //input11
Ref_Cin[12] =1'b0; //input11
Ref_S[12] = SOR; //input11
// ---------
// 13. ADD R24, R16, R3
// ---------
// opcode source1 source2 dest shift Function...
ibustm[13]={Rformat, 5'b10000, 5'b00011, 5'b11000, 5'b00000, ADD};
Ref_Aselect[13] = 32'b00000000000000010000000000000000;//input13
Ref_Bselect[13] = 32'b00000000000000000000000000001000;//input13
Ref_Dselect[13] = 32'b00000000000000000000010000000000;//input11
Ref_Imm[13] =1'b1; //input12
Ref_Cin[13] =1'b0; //input12
Ref_S[13] = SXOR; //input12
// ---------
// 14. OR R7, R10, R10
// ---------
// opcode source1 source2 dest shift Function...
ibustm[14]={Rformat, 5'b01010, 5'b01010, 5'b00111, 5'b00000, OR};
Ref_Aselect[14] = 32'b00000000000000000000010000000000; //input14
Ref_Bselect[14] = 32'b00000000000000000000010000000000; //input14
Ref_Dselect[14] = 32'b00000000000001000000000000000000; //input12
Ref_Imm[14] =1'b0; //input13
Ref_Cin[14] =1'b0; //input13
Ref_S[14] = SADD; //input13
// ---------
// 15. XORI R12, R21, #00F0
// ---------
// opcode source1 dest Immediate...
ibustm[15]={XORI, 5'b10101, 5'b01100, 16'h00F0};
Ref_Aselect[15] = 32'b00000000001000000000000000000000;//input15
Ref_Bselect[15] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input15
Ref_Dselect[15] = 32'b00000001000000000000000000000000;//input13
Ref_Imm[15] =1'b0; //input14
Ref_Cin[15] =1'b0; //input14
Ref_S[15] = SOR; //input14
// ---------
// 16. SUBI R26, R31, #0111
// ---------
// opcode source1 dest Immediate...
ibustm[16]={SUBI, 5'b11111, 5'b11010, 16'h0111};
Ref_Aselect[16] = 32'b10000000000000000000000000000000; //input16
Ref_Bselect[16] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input16
Ref_Dselect[16] = 32'b00000000000000000000000010000000; //input14
Ref_Imm[16] =1'b1; //input15
Ref_Cin[16] =1'b0; //input15
Ref_S[16] = SXOR; //input15
// ---------
// 17. ADD R17, R3, R21
// ---------
// opcode source1 source2 dest shift Function...
ibustm[17]={Rformat, 5'b00011, 5'b10101, 5'b10001, 5'b00000, ADD};
Ref_Aselect[17] = 32'b00000000000000000000000000001000;//input17
Ref_Bselect[17] = 32'b00000000001000000000000000000000;//input17
Ref_Dselect[17] = 32'b00000000000000000001000000000000;//input15
Ref_Imm[17] =1'b1; //input16
Ref_Cin[17] =1'b1; //input16
Ref_S[17] = SSUB; //input16
// ---------
// 18. XOR R15, R7, R21
// ---------
// opcode source1 source2 dest shift Function...
ibustm[18]={Rformat, 5'b00111, 5'b10101, 5'b01111, 5'b00000, XOR};
Ref_Aselect[18] = 32'b00000000000000000000000010000000; //input18
Ref_Bselect[18] = 32'b00000000001000000000000000000000; //input18
Ref_Dselect[18] = 32'b00000100000000000000000000000000; //input16
Ref_Imm[18] =1'b0; //input17
Ref_Cin[18] =1'b0; //input17
Ref_S[18] = SADD; //input17
// ---------
// 19. ADDI R13, R13, #FFFF
// ---------
// opcode source1 dest Immediate...
ibustm[19]={ADDI, 5'b01101, 5'b01101, 16'hFFFF};
Ref_Aselect[19] = 32'b00000000000000000010000000000000; //input19
Ref_Bselect[19] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input19
Ref_Dselect[19] = 32'b00000000000000100000000000000000; //input17
Ref_Imm[19] =1'b0; //input18
Ref_Cin[19] =1'b0; //input18
Ref_S[19] = SXOR; //input18
// ---------
// 20. ADDI R23, R1, #AFC0
// ---------
// opcode source1 dest Immediate...
ibustm[20]={ADDI, 5'b00001, 5'b10111, 16'hAFC0};
Ref_Aselect[20] = 32'b00000000000000000000000000000010;//input20
Ref_Bselect[20] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input20
Ref_Dselect[20] = 32'b00000000000000001000000000000000; //input18
Ref_Imm[20] =1'b1; //input19
Ref_Cin[20] =1'b0; //input19
Ref_S[20] = SADD; //input19
// ---------
// 21. SUB R20, R1, R1
// ---------
// opcode source1 source2 dest shift Function...
ibustm[21]={Rformat, 5'b00001, 5'b00001, 5'b10100, 5'b00000, SUB};
Ref_Aselect[21] = 32'b00000000000000000000000000000010; //input21
Ref_Bselect[21] = 32'b00000000000000000000000000000010; //input21
Ref_Dselect[21] = 32'b00000000000000000010000000000000; //input19
Ref_Imm[21] =1'b1; //input20
Ref_Cin[21] =1'b0; //input20
Ref_S[21] = SADD; //input20
// ---------
// 22. XORI R19, R0, #8CCB
// ---------
// opcode source1 dest Immediate...
ibustm[22]={XORI, 5'b00000, 5'b10011, 16'h8CCB};
Ref_Aselect[22] = 32'b00000000000000000000000000000001;//input22
Ref_Bselect[22] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input22
Ref_Dselect[22] = 32'b00000000100000000000000000000000;//input20
Ref_Imm[22] =1'b0; //input21
Ref_Cin[22] =1'b1; //input21
Ref_S[22] = SSUB; //input21
// --------
// 23. ORI R9, R20, #F98B
// --------
// opcode source1 dest Immediate...
ibustm[23]={ORI, 5'b10100, 5'b01001, 16'hF98B};
Ref_Aselect[23] = 32'b00000000000100000000000000000000; //input23
Ref_Bselect[23] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input23
Ref_Dselect[23] = 32'b00000000000100000000000000000000; //input21
Ref_Imm[23] =1'b1; //input22
Ref_Cin[23] =1'b0; //input22
Ref_S[23] = SXOR; //input22
// --------
// 24. XOR R2, R13, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[24]={Rformat, 5'b01101, 5'b10011, 5'b00010, 5'b00000, XOR};
Ref_Aselect[24] = 32'b00000000000000000010000000000000;//input24
Ref_Bselect[24] = 32'b00000000000010000000000000000000;//input24
Ref_Dselect[24] = 32'b00000000000010000000000000000000;//input22
Ref_Imm[24] =1'b1; //input23
Ref_Cin[24] =1'b0; //input23
Ref_S[24] = SOR; //input23
// --------
// 25. SUBI R26, R9, #0030
// --------
// opcode source1 dest Immediate...
ibustm[25]={SUBI, 5'b01001, 5'b11010, 16'h0030};
Ref_Aselect[25] = 32'b00000000000000000000001000000000; //input25
Ref_Bselect[25] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input25
Ref_Dselect[25] = 32'b00000000000000000000001000000000; //input23
Ref_Imm[25] =1'b0; //input24
Ref_Cin[25] =1'b0; //input24
Ref_S[25] = SXOR; //input24
// --------
// 26. XOR R25, R2, R9
// --------
// opcode source1 source2 dest shift Function...
ibustm[26]={Rformat, 5'b00010, 5'b01001, 5'b11001, 5'b00000, XOR};
Ref_Aselect[26] = 32'b00000000000000000000000000000100;//input26
Ref_Bselect[26] = 32'b00000000000000000000001000000000;//input26
Ref_Dselect[26] = 32'b00000000000000000000000000000100;//input24
Ref_Imm[26] =1'b1; //input25
Ref_Cin[26] =1'b1; //input25
Ref_S[26] = SSUB; //input25
// --------
// 27. ORI R8, R20, #34FB
// --------
// opcode source1 dest Immediate...
ibustm[27]={ORI, 5'b10100, 5'b01000, 16'h34FB};
Ref_Aselect[27] = 32'b00000000000100000000000000000000;//input27
Ref_Bselect[27] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input27
Ref_Dselect[27] = 32'b00000100000000000000000000000000; //input25
Ref_Imm[27] =1'b0; //input26
Ref_Cin[27] =1'b0; //input26
Ref_S[27] = SXOR; //input26
// --------
// 28. XORI R27, R13, #0B31
// --------
// opcode source1 dest Immediate...
ibustm[28]={XORI, 5'b01101, 5'b11011, 16'h0B31};
Ref_Aselect[28] = 32'b00000000000000000010000000000000;//input28
Ref_Bselect[28] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input28
Ref_Dselect[28] = 32'b00000010000000000000000000000000;//input26
Ref_Imm[28] =1'b1; //input27
Ref_Cin[28] =1'b0; //input27
Ref_S[28] = SOR; //input27
// --------
// 29. ADD R14, R2, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[29]={Rformat, 5'b00010, 5'b10011, 5'b01110, 5'b00000, ADD};
Ref_Aselect[29] = 32'b00000000000000000000000000000100;//input29
Ref_Bselect[29] = 32'b00000000000010000000000000000000;//input29
Ref_Dselect[29] = 32'b00000000000000000000000100000000;//input27
Ref_Imm[29] =1'b1; //input28
Ref_Cin[29] =1'b0; //input28
Ref_S[29] = SXOR; //input28
// --------
// 30. OR R4, R8, R8
// --------
// opcode source1 source2 dest shift Function...
ibustm[30]={Rformat, 5'b01000, 5'b01000, 5'b00100, 5'b00000, OR};
Ref_Aselect[30] = 32'b00000000000000000000000100000000;//input30
Ref_Bselect[30] = 32'b00000000000000000000000100000000;//input30
Ref_Dselect[30] = 32'b00001000000000000000000000000000;//input28
Ref_Imm[30] =1'b0; //input29
Ref_Cin[30] =1'b0; //input29
Ref_S[30] = SADD; //input29
// --------
// 31. XORI R12, R21, #5555
// --------
// opcode source1 dest Immediate...
ibustm[31]={XORI, 5'b10101, 5'b01100, 16'h5555};
Ref_Aselect[31] = 32'b00000000001000000000000000000000;//input31
Ref_Bselect[31] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input31
Ref_Dselect[31] = 32'b00000000000000000100000000000000;//input29
Ref_Imm[31] =1'b0; //input30
Ref_Cin[31] =1'b0; //input30
Ref_S[31] = SOR; //input30
ntests = 180;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
$display("-------------------------------");
$display("Time=%t Instruction Number: 0 ",$realtime);
$display("-------------------------------");
ibus = ibustm[0];
#25;
for (k=1; k<= 31; k=k+1) begin
$display("-------------------------------");
$display("Time=%t Instruction Number: %d ",$realtime,k);
$display("-------------------------------");
clk=1;
#5
if (k>=1) begin
$display (" Testing Immediate, Cin and S for instruction %d", k-1);
$display (" Your Imm = %b", Imm);
$display (" Correct Imm = %b", Ref_Imm[k]);
if ( (Imm !== Ref_Imm[k]) && (Ref_Imm[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your Cin = %b", Cin);
$display (" Correct Cin = %b", Ref_Cin[k]);
if ( (Cin !== Ref_Cin[k]) && (Ref_Cin[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your S = %b", S);
$display (" Correct S = %b", Ref_S[k]);
if ( (S !== Ref_S[k]) && (Ref_S[k] !== 3'bxxx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
if (k>=2) begin
$display (" Testing Destination Registers for instruction %d", k-2);
$display (" Your Dselect = %b", Dselect);
$display (" Correct Dselect = %b", Ref_Dselect[k]);
if ( (Dselect !== Ref_Dselect[k]) && (Ref_Dselect[k] !== dontcare) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
#20
clk = 0;
$display ("-------------------------------");
$display (" Time=%t ",$realtime);
$display ("-------------------------------");
ibus = ibustm[k+1];
#5
$display (" Testing Source Registers for instruction %d", k);
$display (" Your Aselect = %b", Aselect);
$display (" Correct Aselect = %b", Ref_Aselect[k]);
if ( (Aselect !== Ref_Aselect[k]) && (Ref_Aselect[k]) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
$display (" Your Bselect = %b", Bselect);
$display (" Correct Bselect = %b", Ref_Bselect[k]);
if ( (Bselect !== Ref_Bselect[k]) && (Ref_Bselect[k] !== dontcare) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
#20
clk = 0;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----------YOU DID IT :-) !!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
module marsohod_3(
input CLK100MHZ,
input KEY0,
input KEY1,
output [7:0] LED,
output [12:1] IO
);
// wires & inputs
wire clk;
wire clkIn = CLK100MHZ;
wire rst_n = KEY0;
wire clkEnable = ~KEY1;
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( 4'b1000 ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( 4'b0010 ),
.regData ( regData )
);
//outputs
assign LED[0] = clk;
assign LED[7:1] = regData[6:0];
wire [11:0] seven_segments;
assign IO[12:1] = seven_segments;
sm_hex_display_digit sm_hex_display_digit
(
.digit1 (digit1),
.digit2 (digit2),
.digit3 (digit3),
.clkIn (clkIn),
.seven_segments (seven_segments)
);
wire [6:0] digit3;
wire [6:0] digit2;
wire [6:0] digit1;
sm_hex_display digit_02 (regData [3:0], digit3 [6:0]);
sm_hex_display digit_01 (regData [7:4], digit2 [6:0]);
sm_hex_display digit_00 (regData [11:8], digit1 [6:0]);
endmodule
|
`include "fpga.v"
module testbed_fpga;
reg spck, mosi, ncs;
wire miso;
reg pck0i, ck_1356meg, ck_1356megb;
wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
reg [7:0] adc_d;
wire adc_clk, adc_noe;
reg ssp_dout;
wire ssp_frame, ssp_din, ssp_clk;
fpga dut(
spck, miso, mosi, ncs,
pck0i, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk
);
integer i;
initial begin
// init inputs
#5 ncs=1;
#5 spck = 1;
#5 mosi = 1;
#50 ncs=0;
for (i = 0 ; i < 8 ; i = i + 1) begin
#5 mosi = $random;
#5 spck = 0;
#5 spck = 1;
end
#5 ncs=1;
#50 ncs=0;
for (i = 0 ; i < 8 ; i = i + 1) begin
#5 mosi = $random;
#5 spck = 0;
#5 spck = 1;
end
#5 ncs=1;
#50 mosi=1;
$finish;
end
endmodule // main
|
`timescale 1ns/1ps
module DdrCtl1Sim;
reg clock0;
reg clock90;
reg clock2x0;
reg clock2x90;
reg clock2x180;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [31:0] page;
wire ready;
wire ddrctl_ddr_cke;
wire ddrctl_ddr_csn;
wire ddrctl_ddr_rasn;
wire ddrctl_ddr_casn;
wire ddrctl_ddr_wen;
wire [1:0] ddrctl_ddr_ba;
wire [12:0] ddrctl_ddr_addr;
wire [1:0] ddrctl_ddr_dm;
wire [15:0] ddrctl_ddr_dq;
wire [1:0] ddrctl_ddr_dqs;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#500000 $finish;
end
initial begin
#0 clock0 = 1;
forever #10 clock0 = ~clock0;
end
initial begin
#5 clock90 = 1;
forever #10 clock90 = ~clock90;
end
initial begin
#0 clock2x0 = 1;
forever #5 clock2x0 = ~clock2x0;
end
initial begin
#2.5 clock2x90 = 1;
forever #5 clock2x90 = ~clock2x90;
end
initial begin
#5 clock2x180 = 1;
forever #5 clock2x180 = ~clock2x180;
end
initial begin
#0 reset = 0;
#60 reset = 1;
#40 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
# 204615 inst = {`DdrCtl1_LA0,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA1,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA2,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA3,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LD0,8'hAA};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hBB};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hCC};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hDD};
inst_en = 1;
#20 inst = {`DdrCtl1_WRP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
#180 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
#5500 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
// // Test disabled instruction.
// #240 inst = {`DdrCtl1_LD1,8'h0A};
// inst_en = 0;
// #20 inst = {`DdrCtl1_LD1,8'h01};
// inst_en = 1;
// // // Test bad instruction.
// // // #20 inst = {8'hF,8'h10};
// // // inst_en = 1;
// // // #20 inst = {`DdrCtl1_LD2,8'hA0};
// // // inst_en = 1;
// // // #40 reset = 1;
// // // #80 reset = 0;
// // // #20 inst = {`DdrCtl1_LD2,8'hAB};
// // // inst_en = 1;
// // // #20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
// // // inst_en = 1;
// // Test writing to another bank.
#200 inst = {`DdrCtl1_LA0,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA1,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA2,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA3,8'h01};
inst_en = 1;
#20 inst = {`DdrCtl1_LD0,8'hEE};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hFF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'h11};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'h22};
inst_en = 1;
#20 inst = {`DdrCtl1_WRP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#200 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#180 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
end // initial begin
Ddr
ddr (.Clk(clock2x0),
.Clk_n(clock2x180),
.Cke(ddrctl_ddr_cke),
.Cs_n(ddrctl_ddr_csn),
.Ras_n(ddrctl_ddr_rasn),
.Cas_n(ddrctl_ddr_casn),
.We_n(ddrctl_ddr_wen),
.Ba(ddrctl_ddr_ba),
.Addr(ddrctl_ddr_addr),
.Dm(ddrctl_ddr_dm),
.Dq(ddrctl_ddr_dq),
.Dqs(ddrctl_ddr_dqs));
DdrCtl1
ddrctl (.clock0(clock0),
.clock90(clock90),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.page(page),
.ready(ready),
.ddr_clock0(clock2x0),
.ddr_clock90(clock2x90),
.ddr_cke(ddrctl_ddr_cke),
.ddr_csn(ddrctl_ddr_csn),
.ddr_rasn(ddrctl_ddr_rasn),
.ddr_casn(ddrctl_ddr_casn),
.ddr_wen(ddrctl_ddr_wen),
.ddr_ba(ddrctl_ddr_ba),
.ddr_addr(ddrctl_ddr_addr),
.ddr_dm(ddrctl_ddr_dm),
.ddr_dq(ddrctl_ddr_dq),
.ddr_dqs(ddrctl_ddr_dqs));
endmodule // DdrCtl1Sim
|
//
// $ ../nli handshake.n
// $ iverilog tb_handshake.v handshake.v
//
`timescale 1ns/1ns
module tb_handshake;
reg clk, rst;
wire [31:0] channel_out_data;
wire channel_out_en;
reg channel_out_ack;
reg [31:0] channel_in_data;
reg channel_in_en;
wire channel_in_ack;
initial begin
clk <= 0;
rst <= 1;
channel_out_ack <= 0;
channel_in_data <= 0;
channel_in_en <= 0;
#105
rst <= 0;
#1000
$finish;
end
always begin
#10 clk = ~clk;
end
always @(posedge clk) begin
if (!rst) begin
if (!channel_in_ack) begin
channel_in_data <= 123;
channel_in_en <= 1;
end else begin
channel_in_en <= 0;
end
if (channel_out_en && !channel_out_ack) begin
channel_out_ack <= 1;
$display("data output %d [%t]", channel_out_data, $time);
end else begin
channel_out_ack <= 0;
end
end
end
handshake dut(.clk(clk), .rst(rst),
.channel_out_data(channel_out_data),
.channel_out_en(channel_out_en),
.channel_out_ack(channel_out_ack),
.channel_in_data(channel_in_data),
.channel_in_en(channel_in_en),
.channel_in_ack(channel_in_ack));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
|
/******************************************************************************
*
* File Name : decode_ctl.v
* Version : 0.1
* Date : Feb 20, 2008
* Description :
* Dependencies :
*
* Company : Beijing Soul
* Author :
*
*****************************************************************************/
module decode_ctl (/*AUTOARG*/
// Outputs
stream_width, stream_ack, out_data, out_valid, out_done,
// Inputs
clk, rst, ce, fo_full, stream_data, stream_valid,
stream_done
);
input clk,
rst,
ce,
fo_full;
input [12:0] stream_data;
input stream_valid;
input stream_done;
output [3:0] stream_width;
output stream_ack;
output [7:0] out_data;
output out_valid;
output out_done;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg stream_ack;
reg [3:0] stream_width;
// End of automatics
parameter [2:0]
S_IDLE = 3'h0,
S_PROC = 3'h1,
S_LEN1 = 3'h2,
S_LEN2 = 3'h3,
S_LEN3 = 3'h4,
S_WAIT = 3'h5,
S_COPY = 3'h6,
S_END = 3'h7;
reg [2:0]
state, state_n;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [3:0] cnt, cnt_n;
reg cnt_load, cnt_dec;
reg [10:0] off, off_n;
reg off_load, off_load_n;
reg out_valid_n;
reg [7:0] out_data_n;
always @(/*AS*/ce or cnt or fo_full or state
or stream_data or stream_done or stream_valid)
begin
stream_width = 4'h0;
stream_ack = 1'b0;
state_n = state;
cnt_load = 1'b0;
cnt_n = cnt;
cnt_dec = 1'b0;
off_n = 11'h0;
off_load_n = 1'b0;
out_data_n = 8'h0;
out_valid_n = 1'b0;
case (state)
S_IDLE: begin
if (ce)
state_n = S_PROC;
end
S_PROC: begin
if (stream_valid) begin
if (stream_data[12:4] == 9'b110000000) begin /* END */
state_n = S_END;
end else if (~stream_data[12]) begin /* uncompress*/
stream_width = 4'h9;
stream_ack = 1'b1;
out_valid_n = 1'b1;
out_data_n = stream_data[11:4];
end else begin /* offset and first len */
if (~stream_data[11]) begin
stream_width = 4'hd; /* 11 + 2 */
off_n = stream_data[10:0];
end else begin
stream_width = 4'h9; /* 7 + 2 */
off_n = stream_data[10:4];
end
off_load_n = 1'b1;
stream_ack = 1'b1;
state_n = S_LEN1;
end // else: !if(~stream_data[12])
end else if (stream_done) begin // if (stream_valid)
state_n = S_END;
end
end // case: S_PROC
S_LEN1: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0010; /* 2 */
2'b01: cnt_n = 4'b0011; /* 3 */
2'b10: cnt_n = 4'b0100; /* 4 */
2'b11: begin
cnt_load = 1'b0;
state_n = S_LEN2;
end
endcase
end else if (stream_done) begin // if (stream_valid)
state_n = S_END;
end
end // case: S_LEN
S_LEN2: begin
if (stream_valid) begin
stream_width = 4'h2;
stream_ack = 1'b1;
cnt_load = 1'b1;
state_n = S_WAIT;
case (stream_data[12:11])
2'b00: cnt_n = 4'b0101; /* 5 */
2'b01: cnt_n = 4'b0110; /* 6 */
2'b10: cnt_n = 4'b0111; /* 7 */
2'b11: begin
cnt_n = 4'b1000;
state_n = S_COPY;
end
endcase
end else if (stream_done) begin // if (stream_valid)
state_n = S_END;
end
end
S_COPY: begin
if (fo_full) begin
state_n = S_COPY;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_LEN3;
end
end
end
S_LEN3: begin
if (stream_valid) begin
stream_width = 4'h4;
stream_ack = 1'b1;
cnt_load = 1'b1;
cnt_n = stream_data[12:09];
if (stream_data[12:09] == 4'b1111) begin
state_n = S_COPY;
end else begin
state_n = S_WAIT;
end
end else if (stream_done) begin // if (stream_valid)
state_n = S_END;
end
end // case: S_LEN3
S_WAIT: begin
if (fo_full) begin
state_n = S_WAIT;
end else begin
if (|cnt) begin
cnt_dec = 1'b1;
end else begin
state_n = S_PROC;
end
end
end
endcase // case(state)
end // always @ (...
/* out data and valid signal */
reg [7:0] out_data_r;
reg out_valid_r;
always @(posedge clk or posedge rst)
begin
if (rst)
out_valid_r <= #1 1'b0;
else
out_valid_r <= #1 out_valid_n;
end
always @(posedge clk)
out_data_r <= #1 out_data_n;
wire [7:0] hdata;
reg [10:0] waddr, raddr;
always @(posedge clk or posedge rst)
begin
if (rst)
waddr <= #1 11'h0;
else if (out_valid)
waddr <= #1 waddr + 1'b1;
end
generic_tpram history_mem (.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.we_a(out_valid),
.oe_a(1'b0),
.addr_a(waddr),
.di_a(out_data),
.do_a(),
.clk_b(clk),
.rst_b(rst),
.ce_b(1'b1),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(raddr),
.di_b(),
.do_b(hdata));
defparam history_mem.aw = 11;
defparam history_mem.dw = 8;
reg hwe;
always @(posedge clk)
hwe <= #1 cnt_dec;
always @(posedge clk)
begin
if (cnt_load)
cnt <= #1 cnt_n;
else if (cnt_dec)
cnt <= #1 cnt - 1'b1;
end
always @(posedge clk)
begin
off <= #1 off_n;
off_load <= #1 off_load_n;
end
always @(posedge clk)
begin
if (off_load)
raddr <= #1 waddr - off;
else if (cnt_dec)
raddr <= #1 raddr + 1'b1;
end
reg [7:0] out_data_d;
always @(posedge clk)
begin
if (out_valid)
out_data_d <= #1 out_data;
end
assign out_done = state == S_END;
assign out_data = out_valid_r ? out_data_r :
waddr == raddr ? out_data_d : hdata;
assign out_valid = out_valid_r | hwe;
endmodule // decode_ctl
|
// MBT 4/1/2014
//
// 2 read-port, 1 write-port ram
//
// reads are asynchronous
//
// this file should not be directly instantiated by end programmers
// use bsg_mem_2r1w instead
//
`include "bsg_defines.v"
module bsg_mem_2r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
);
wire unused = w_reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{w_clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this implementation ignores the r_v_i
assign r1_data_o = mem[r1_addr_i];
assign r0_data_o = mem[r0_addr_i];
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
mem[w_addr_i] <= w_data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_synth)
|
//-----------------------------------------------------------------------------
// Title :Block level wrapper
//-----------------------------------------------------------------------------
// File : xgbaser_gt_same_quad_wrapper.v
//-----------------------------------------------------------------------------
// Description: This file is a wrapper for the 10GBASE-R core. It contains the
// 10GBASE-R core, the transceivers and some transceiver logic.
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps / 1ps
`define DLY #1
module xgbaser_gt_same_quad_wrapper #
(
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "FALSE"
)
(
input gt_txclk322,
output gt_txusrclk,
output gt_txusrclk2,
output qplllock,
output qpllrefclklost,
output qplloutclk,
output qplloutrefclk,
output reg qplllock_txusrclk2,
output reg gttxreset_txusrclk2,
output reg txuserrdy,
output reg areset_clk_156_25_bufh,
output reg areset_clk_156_25,
output reg mmcm_locked_clk156,
output reset_counter_done,
output reg core_reset,
input gt0_tx_resetdone,
input gt1_tx_resetdone,
input gt2_tx_resetdone,
input gt3_tx_resetdone,
input tx_fault,
output gttxreset,
output gtrxreset,
input gt_refclk,
output clk156,
output dclk,
input areset
);
wire clk_156_25_bufh;
wire clk156_buf;
wire dclk_buf;
wire clkfbout;
wire mmcm_locked;
wire qpllreset;
reg [7:0] reset_counter = 8'd0;
reg [3:0] reset_pulse;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [7:0] tied_to_vcc_vec_i;
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 8'hff;
reg core_reset_tmp;
//- Synchronize resets
reg areset_clk_156_25_bufh_tmp;
reg areset_clk156_25_tmp;
reg qplllock_txusrclk2_tmp;
reg mmcm_locked_clk156_tmp;
reg gttxreset_txusrclk2_tmp;
MMCME2_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.500),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE_F (6.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (13),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (6.4),
.REF_JITTER1 (0.010))
clkgen_i
(
.CLKFBIN(clkfbout),
.CLKIN1(clk_156_25_bufh),
.PWRDWN(1'b0),
.RST(!qplllock),
.CLKFBOUT(clkfbout),
.CLKOUT0(clk156_buf),
.CLKOUT1(dclk_buf),
.LOCKED(mmcm_locked)
);
BUFG clk156_bufg_inst
(
.I (clk156_buf),
.O (clk156)
);
BUFG dclk_bufg_inst
(
.I (dclk_buf),
.O (dclk)
);
//synthesis attribute async_reg of core_reset_tmp is "true";
//synthesis attribute async_reg of core_reset is "true";
always @(posedge areset or posedge clk156)
begin
if(areset)
begin
core_reset_tmp <= 1'b1;
core_reset <= 1'b1;
end
else
begin
// Hold core in reset until everything else is ready...
core_reset_tmp <= (!(gt0_tx_resetdone) || !(gt1_tx_resetdone) || !(gt2_tx_resetdone) || !(gt3_tx_resetdone) || areset || tx_fault );
core_reset <= core_reset_tmp;
end
end
//synthesis attribute async_reg of qplllock_txusrclk2_tmp is "true";
//synthesis attribute async_reg of qplllock_txusrclk2 is "true";
always @(negedge qplllock or posedge gt_txusrclk2)
begin
if(!qplllock)
begin
qplllock_txusrclk2_tmp <= 1'b0;
qplllock_txusrclk2 <= 1'b0;
end
else
begin
qplllock_txusrclk2_tmp <= 1'b1;
qplllock_txusrclk2 <= qplllock_txusrclk2_tmp;
end
end
//synthesis attribute async_reg of mmcm_locked_clk156_tmp is "true";
//synthesis attribute async_reg of mmcm_locked_clk156 is "true";
always @(negedge mmcm_locked or posedge clk156)
begin
if(!mmcm_locked)
begin
mmcm_locked_clk156_tmp <= 1'b0;
mmcm_locked_clk156 <= 1'b0;
end
else
begin
mmcm_locked_clk156_tmp <= 1'b1;
mmcm_locked_clk156 <= mmcm_locked_clk156_tmp;
end
end
//synthesis attribute async_reg of gttxreset_txusrclk2_tmp is "true";
//synthesis attribute async_reg of gttxreset_txusrclk2 is "true";
always @(posedge gttxreset or posedge gt_txusrclk2)
begin
if(gttxreset)
begin
gttxreset_txusrclk2_tmp <= 1'b1;
gttxreset_txusrclk2 <= 1'b1;
end
else
begin
gttxreset_txusrclk2_tmp <= 1'b0;
gttxreset_txusrclk2 <= gttxreset_txusrclk2_tmp;
end
end
always @(posedge gt_txusrclk2 or posedge gttxreset_txusrclk2)
begin
if(gttxreset_txusrclk2)
txuserrdy <= 1'b0;
else
txuserrdy <= qplllock_txusrclk2;
end
//synthesis attribute async_reg of areset_clk_156_25_bufh_tmp is "true";
//synthesis attribute async_reg of areset_clk_156_25_bufh is "true";
always @(posedge areset or posedge clk_156_25_bufh)
begin
if(areset)
begin
areset_clk_156_25_bufh_tmp <= 1'b1;
areset_clk_156_25_bufh <= 1'b1;
end
else
begin
areset_clk_156_25_bufh_tmp <= 1'b0;
areset_clk_156_25_bufh <= areset_clk_156_25_bufh_tmp;
end
end
//synthesis attribute async_reg of areset_clk156_25_tmp is "true";
//synthesis attribute async_reg of areset_clk_156_25 is "true";
always @(posedge areset or posedge clk156)
begin
if(areset)
begin
areset_clk156_25_tmp <= 1'b1;
areset_clk_156_25 <= 1'b1;
end
else
begin
areset_clk156_25_tmp <= 1'b0;
areset_clk_156_25 <= areset_clk156_25_tmp;
end
end
BUFHCE bufhce_156_25_inst(
.CE (tied_to_vcc_i),
.I (gt_refclk),
.O (clk_156_25_bufh)
);
BUFG tx322clk_bufg_i
(
.I (gt_txclk322),
.O (gt_txusrclk)
);
assign gt_txusrclk2 = gt_txusrclk;
//***********************************************************************//
// //
//--------------------- Reset Logic -----------------------------------//
// //
//***********************************************************************//
// Hold off release the GT resets until 500ns after configuration.
// 128 ticks at 6.4ns period will be >> 500 ns.
always @(posedge clk_156_25_bufh or posedge areset_clk_156_25_bufh)
begin
if (areset_clk_156_25_bufh == 1'b1)
reset_counter <= 8'd0;
else if (!reset_counter[7])
reset_counter <= reset_counter + 1'b1;
else
reset_counter <= reset_counter;
end
always @(posedge clk_156_25_bufh)
begin
if(!reset_counter[7])
reset_pulse <= 4'b1110;
else
reset_pulse <= {1'b0, reset_pulse[3:1]};
end
assign reset_counter_done = reset_counter[7];
assign gttxreset = reset_pulse[0];
assign gtrxreset = reset_pulse[0];
assign qpllreset = reset_pulse[0];
// Instantiate the 10GBASER/KR GT Common block
ten_gig_eth_pcs_pma_ip_GT_Common_wrapper # (
.WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware
ten_gig_eth_pcs_pma_gt_common_block
(
.refclk (gt_refclk),
.qplllockdetclk (dclk),
.qpllreset (qpllreset),
.qplllock (qplllock),
.qpllrefclklost (qpllrefclklost),
.qplloutclk (qplloutclk),
.qplloutrefclk (qplloutrefclk)
);
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// `default_nettype none
// SNK NeoGeo FPGA hardware definitions (for simulation only)
// furrtek, Charles MacDonald, Kyuusaku, freem and neogeodev contributors ~ 2016
// https://github.com/neogeodev/NeoGeoFPGA-sim
// Todo: VPA for interrupt ACK (NEO-C1)
module neogeo(
input nRESET_BTN, // VCCON on MVS
// Player inputs
input [9:0] P1_IN,
input [9:0] P2_IN,
input [7:0] DIPSW,
// 68K CPU
inout [15:0] M68K_DATA,
output [23:1] M68K_ADDR, // Should only expose [19:1] to cartridge
output M68K_RW, nAS, nLDS, nUDS,
output [2:0] LED_LATCH,
output [7:0] LED_DATA,
// Cartridge clocks
output CLK_68KCLKB, CLK_8M, CLK_4MB,
// Cartridge 68K ROMs
output nROMOE, nSLOTCS,
input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
output nPORTOEL, nPORTOEU,
output nPORTWEL, nPORTWEU,
output nPORTADRS,
// Cartridge PCM ROMs
input [7:0] SDRAD,
output [9:8] SDRA_L,
output [23:20] SDRA_U,
output SDRMPX, nSDROE,
input [7:0] SDPAD,
output [11:8] SDPA,
output SDPMPX, nSDPOE,
// Cartridge Z80 ROMs
output nSDROM, nSDMRD,
output [15:0] SDA,
inout [7:0] SDD,
// Cartridge/onboard gfx ROMs
inout [23:0] PBUS,
output nVCS,
output S2H1, CA4,
output PCK1B, PCK2B,
// Gfx
output CLK_12M, EVEN, LOAD, H,
input [3:0] GAD, GBD,
input [7:0] FIXD_CART,
// Memcard
output [4:0] CDA_U, // Memcard upper address lines
output nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG,
input nCD1, nCD2, nWP,
output [6:0] VIDEO_R,
output [6:0] VIDEO_G,
output [6:0] VIDEO_B,
output VIDEO_SYNC
// Serial video output
//output VIDEO_R_SER, VIDEO_G_SER, VIDEO_B_SER, VIDEO_CLK_SER, VIDEO_LAT_SER,
// I2S audio output
//output I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK
);
parameter SYSTEM_MODE = 1'b1; // MVS
wire [7:0] FIXD;
wire [7:0] FIXD_SFIX;
wire [15:0] G; // SFIX address bus
wire [23:0] CDA;
wire [2:0] BNK;
wire [11:0] PA; // Palette RAM address
wire [15:0] PC; // Palette RAM data
wire [3:0] WE; // LSPC/B1
wire [3:0] CK; // LSPC/B1
wire [5:0] nSLOT;
wire [2:0] P1_OUT;
wire [2:0] P2_OUT;
wire [5:0] ANA; // SSG audio level
/* wire [6:0] VIDEO_R;
wire [6:0] VIDEO_G;
wire [6:0] VIDEO_B;*/
// Implementation specific (unique slot)
assign nSLOTCS = nSLOT[0];
// Are these good ?
assign nBITWD0 = |{nBITW0, M68K_ADDR[6:5]};
assign nCOUNTOUT = |{nBITW0, ~M68K_ADDR[6:5]};
// DEBUG: Disabled 68k
cpu_68k M68KCPU(CLK_68KCLK, nRESET, IPL1, IPL0, nDTACK, M68K_ADDR, M68K_DATA, nLDS, nUDS, nAS, M68K_RW);
/*assign M68K_ADDR = 24'h000000;
assign M68K_DATA = 16'hzzzz;
assign nLDS = 1'b1;
assign nUDS = 1'b1;
assign nAS = 1'b1;
assign M68K_RW = 1'b1;*/
cpu_z80 Z80CPU(CLK_4M, nRESET, SDD, SDA, nIORQ, nMREQ, nSDRD, nSDWR, nZ80INT, nZ80NMI);
neo_c1 C1(M68K_ADDR[21:17], M68K_DATA[15:8], A22Z, A23Z, nLDS, nUDS, M68K_RW, nAS, nROMOEL, nROMOEU,
nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU, nPORTADRS, nWRL, nWRU, nWWL, nWWU, nSROMOEL, nSROMOEU,
nSRAMOEL, nSRAMOEU, nSRAMWEL, nSRAMWEU, nLSPOE, nLSPWE, nCRDO, nCRDW, nCRDC, nSDW, P1_IN, P2_IN,
nCD1, nCD2, nWP, nROMWAIT, nPWAIT0, nPWAIT1, PDTACK, SDD, nSDZ80R, nSDZ80W, nSDZ80CLR, CLK_68KCLK,
nDTACK, nBITW0, nBITW1, nDIPRD0, nDIPRD1, nPAL, SYSTEM_MODE);
neo_d0 D0(CLK_24M, nRESET, nRESETP, CLK_12M, CLK_68KCLK, CLK_68KCLKB, CLK_6MB, CLK_1MB, M68K_ADDR[4],
nBITWD0, M68K_DATA[5:0], SDA[15:11], SDA[4:2], nSDRD, nSDWR, nMREQ, nIORQ, nZ80NMI, nSDW, nSDZ80R,
nSDZ80W, nSDZ80CLR, nSDROM, nSDMRD, nSDMWR, SDRD0, SDRD1, n2610CS, n2610RD, n2610WR, nZRAMCS,
BNK, P1_OUT, P2_OUT);
// Fix to prevent TV80 from going nuts because the data bus is open on port reads for NEO-ZMC
assign SDD = (SDRD0 & SDRD1) ? 8'bzzzzzzzz : 8'b00000000;
neo_e0 E0(M68K_ADDR[23:1], BNK[2:0], nSROMOEU, nSROMOEL, nSROMOE,
nVEC, A23Z, A22Z, CDA);
neo_f0 F0(nRESET, nDIPRD0, nDIPRD1, nBITWD0, DIPSW, M68K_ADDR[7:4], M68K_DATA[7:0], SYSTEMB, nSLOT, SLOTA,
SLOTB, SLOTC, LED_LATCH, LED_DATA, RTC_DOUT, RTC_TP, RTC_DIN, RTC_CLK, RTC_STROBE);
neo_i0 I0(nRESET, nCOUNTOUT, M68K_ADDR[3:1], M68K_ADDR[7], COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2,
PBUS[15:0], PCK2B, G);
syslatch SL(M68K_ADDR[4:1], nBITW1, nRESET,
SHADOW, nVEC, nCARDWEN, CARDWENB, nREGEN, nSYSTEM, nSRAMWEN, PALBNK);
// Normally in ZMC2, saves 2 FPGA inputs
assign {DOTA, DOTB} = {|GAD, |GBD};
assign CDA_U = CDA[23:19];
lspc2_a2 LSPC2(CLK_24M, nRESET, PBUS[15:0], PBUS[23:16], M68K_ADDR[3:1], M68K_DATA, nLSPOE, nLSPWE, DOTA, DOTB, CA4, S2H1,
S1H1, LOAD, H, EVEN1, EVEN2, IPL0, IPL1, TMS0, LD1, LD2, PCK1, PCK2, WE[3:0], CK[3:0], SS1,
SS2, nRESETP, VIDEO_SYNC, CHBL, nBNKB, nVCS, CLK_8M, CLK_4M);
assign EVEN = EVEN1;
neo_b1 B1(CLK_6MB, CLK_1MB, PBUS, FIXD, PCK1, PCK2, CHBL, nBNKB, GAD, GBD, WE[0], WE[1], WE[2], WE[3],
CK[0], CK[1], CK[2], CK[3], TMS0, LD1, LD2, SS1, SS2, S1H1, A23Z, A22Z, PA, nLDS, M68K_RW, nAS,
M68K_ADDR[21:17], M68K_ADDR[12:1], nHALT, nRESET, nRESET_BTN);
ram_68k M68KRAM(M68K_ADDR[15:1], M68K_DATA, nWWL, nWWU, nWRL, nWRU);
z80ram ZRAM(SDA[10:0], SDD, nZRAMCS, nSDMRD, nSDMWR);
palram PALRAM({PALBNK, PA}, PC, nPALWE);
// Embedded ROMs (flash)
rom_sps2 SP(M68K_ADDR[16:1], {M68K_DATA[7:0], M68K_DATA[15:8]}, nSROMOE);
rom_l0 L0(PBUS[15:0], PBUS[23:16], nVCS);
rom_sfix SFIX({G[15:3], S2H1, G[2:0]}, FIXD_SFIX, nSYSTEM);
// SFIX / Cart FIX switch
assign FIXD = nSYSTEM ? FIXD_CART : FIXD_SFIX;
ym2610 YM(CLK_8M, nRESET, SDD, SDA[1:0], nZ80INT, n2610CS, n2610WR, n2610RD, SDRAD, {SDRA_U, SDRA_L}, SDRMPX,
nSDROE, SDPAD, SDPA, SDPMPX, nSDPOE, ANA, SH1, SH2, OP0, PHI_S);
ym2i2s YM2I2S(nRESET, CLK_I2S, ANA, SH1, SH2, OP0, PHI_S, I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK);
// MVS only
upd4990 RTC(CLK_RTC, 1'b1, 1'b1, RTC_CLK, RTC_DIN, RTC_STROBE, RTC_TP, RTC_DOUT);
videout VOUT(CLK_6MB, nBNKB, SHADOW, PC, VIDEO_R, VIDEO_G, VIDEO_B);
/*ser_video SERVID(nRESET, CLK_SERVID, CLK_6MB, VIDEO_R, VIDEO_G, VIDEO_B,
VIDEO_R_SER, VIDEO_G_SER, VIDEO_B_SER, VIDEO_CLK_SER, VIDEO_LAT_SER);*/
// Sim only
logger LOGGER(CLK_6MB, nBNKB, SHADOW, COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2);
// nSRAMCS comes from analog battery backup circuit
assign nSRAMCS = 1'b0;
sram SRAM(M68K_DATA, M68K_ADDR[15:1], nBWL, nBWU, nSRAMOEL, nSRAMOEU, nSRAMCS);
assign nSWE = nSRAMWEN | nSRAMCS;
assign nBWL = nSRAMWEL | nSWE;
assign nBWU = nSRAMWEU | nSWE;
// Unique gates
assign PCK1B = ~PCK1;
assign PCK2B = ~PCK2;
assign nPALWE = M68K_RW | nPAL;
assign SYSTEMB = ~nSYSTEM;
assign nROMOE = nROMOEU & nROMOEL;
// Memcard stuff
assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};
assign CARD_PIN_nREG = nREGEN | nCRDO;
// Palette data bidir buffer from/to 68k
assign M68K_DATA = (nPAL | ~M68K_RW) ? 16'bzzzzzzzzzzzzzzzz : PC;
assign PC = nPALWE ? 16'bzzzzzzzzzzzzzzzz : M68K_DATA;
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module alu_slice_msb(a, b, c, less, sel, ovrflw, out, set);
input a, b, c, less;
input [2:0] sel;
output out, ovrflw, set;
wire overflow;
wire sum, ANDresult,less, ORresult, b_inv;
reg out;
assign b_inv = sel[2] ^ b;
assign ANDresult = a & b;
assign ORresult = a | b;
assign ovrflw = overflow ^ c;
fulladder f1(a, b_inv, c, sum, overflow);
assign set = sum;
always @(a or b or c or less or sel)
begin
case(sel[1:0])
2'b00: out = ANDresult;
2'b01: out = ORresult;
2'b10: out = sum;
2'b11: out = less;
endcase
end
endmodule
|
`timescale 1ns / 1ps
module toplevel(
//i2c stuff
input clk, //100Mhz
input rst, //i2c reset
inout scl, //serial clock line
inout sda, //serial data line
output vcc, //constant 1
output gnd, //constant 0
output wire beat, //beat detection
output [7:0] LED, //motion tracking
//playback stuff
input PB_RST, //playback reset
input PB_PLY, // Play command input from push-button
input [3:0] VOL, // 4-bit volume
output P, // Square wave output
output [3:0] SEGA, //BPM display
output [7:0] SEGD, //BPM display
//RAM stuff
inout [15:0] MemDB,
output [23:1] ADDR, // 23-bit address sent to flash memory
input EppAstb,
input EppDstb,
input EppWr,
input FlashStSts,
input RamWait,
output EppWait,
output FlashCS,
output FlashRp,
output MemOe,
output MemWr,
output RamAdv,
output RamClk,
output RamCre,
output RamCS,
output RamLB,
output RamUB,
inout [7:0] EppDB
);
parameter
NORMAL = 2'b00,
STACCATO = 2'b01,
SLURRED = 2'b10,
BPM_COMM = 2'b11;
//durr
assign gnd = 0;
assign vcc = 1;
//i2c stuff
wire signed [15:0] accel_z; //Raw data coming out of the i2c bus (not always valid)
reg [15:0] accel_out; //Captured data from accel_z when the valid bit goes high. Should always be valid
wire valid; //After a successful read from the z-register this will be high
//BPM calculation stuff
wire [7:0] BPM; //Current BPM of playback
wire clk_slow; //100kHz clock for BPM calculation and stuff
//Music playback stuff
wire [1:0] MODE; // normal / staccato / slurred
wire [3:0] NOTE; // length of the tone
wire [5:0] TONE; // frequency of the tone
wire [15:0] DATA; // raw music data being read from the music file
wire DONE;
wire END_SONG;
wire EN;
reg PLAY;
reg [7:0] DEFAULT_BPM; //BPM stated in the music file
reg LATCH_PB_PLY;
initial begin
DEFAULT_BPM <= 8'd80;
PLAY <= 0;
LATCH_PB_PLY <= 0;
end
always @(posedge clk) begin
// Toggle only on rising edge/ falling edge
if (PB_PLY && ~LATCH_PB_PLY)
PLAY <= ~PLAY;
LATCH_PB_PLY <= PB_PLY;
end
//Capture the i2c z-accveleration output when it's valid
always @ (posedge valid) begin
accel_out <= accel_z;
end
// TODO
// Update the default BPM with the falling edge of DONE to allow for all the bits to be loaded from RAM
// This always reads the wrong byte for me (ie. 192 instead of 100). Why?? -Hugh
/*bv
always @ (negedge DONE) begin
if (PLAY && (DATA[15:8] == 8'd192))
DEFAULT_BPM <= DATA[7:0];
end
*/
// Grabbing everything out of the DATA register
assign MODE = (DATA[15:14] == BPM_COMM) ? NORMAL : DATA[15:14];
assign NOTE = (DATA[15:14] == BPM_COMM) ? 4'b0 : DATA[3:0];
assign TONE = DATA[13:8];
assign END_SONG = PLAY && (DATA[15:14] == BPM_COMM) && (DATA[7:0] == 0);
// Using LEDs for motion tracking / beat signal at the moment
// assign LED = DATA[15:8]; //High Bytes (BPM Command/ Tone)
// assign LED = DATA[7:0]; //Low Bytes (BPM/ Duration)
MPU6050 mpu (
.clk(clk),
.rst(rst),
.scl(scl),
.sda(sda),
.accel_z(accel_z),
.valid(valid),
.error(error)
);
double_thermometer LED_display (
.accel(accel_out),
.out(LED)
);
beatmaker bm (
.clk(clk),
.accel(accel_out),
.beat(beat)
);
clk_divider clkdiv (
.clkin(clk),
.clkout(clk_slow)
);
bpmcalculator bpmcalc (
.clk(clk_slow),
.beat(beat),
.default_bpm(DEFAULT_BPM),
.bpm_out(BPM)
);
memory_controller memory_ctrl_blk (.clk(clk), .EppAstb(EppAstb), .EppDstb(EppDstb), .EppWr(EppWr), .FlashStSts(FlashStSts),
.RamWait(RamWait), .EppWait(EppWait), .FlashCS(FlashCS), .FlashRp(FlashRp), .MemAdr(ADDR), .MemOe(MemOe),
.MemWr(MemWr), .RamAdv(RamAdv), .RamClk(RamClk), .RamCre(RamCre), .RamCS(RamCS), .RamLB(RamLB), .RamUB(RamUB),
.MemDB(MemDB), .EppDB(EppDB), .BTN(DONE & PLAY), .dataOut(DATA), .Reset(PB_RST || END_SONG));
timing_controller timing_ctrl_blk (clk, BPM, MODE, NOTE, PLAY, EN, DONE);
display disp_blk (clk, BPM, PLAY, SEGA, SEGD);
tone tone_blk (clk, TONE, EN & PLAY ,VOL, P);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_PP_SYMBOL_V
|
//32位2选1
module select2_32(
input [31:0] in1,
input [31:0] in2,
input choose,
output reg [31:0] out
);
always@(in1 or in2 or choose)
case(choose)
1'b0:out=in1;
1'b1:out=in2;
default:out=32'b0;
endcase
endmodule
//8位2选1
module select2_8(
input [7:0] in1,
input [7:0] in2,
input choose,
output reg [7:0] out
);
always@(in1 or in2 or choose)
case(choose)
1'b0:out=in1;
1'b1:out=in2;
default:out=8'b0;
endcase
endmodule
//5位2选1
module select2_5(
input [4:0] in1,
input [4:0] in2,
input choose,
output reg [4:0] out
);
always@(in1 or in2 or choose)
case(choose)
1'b0:out=in1;
1'b1:out=in2;
default:out=5'b0;
endcase
endmodule
//5位3选1
module select3_5(
input [4:0] in1,
input [4:0] in2,
input [4:0] in3,
input [1:0] choose,
output reg [4:0] out
);
always@(in1 or in2 or in3 or choose)
case(choose)
2'b00:out=in1;
2'b01:out=in2;
2'b10:out=in3;
default:out=5'b0;
endcase
endmodule
//32位3选1
module select3_32(
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [1:0] choose,
output reg [31:0] out
);
always@(in1 or in2 or in3 or choose)
case(choose)
2'b00:out=in1;
2'b01:out=in2;
2'b10:out=in3;
default:out=32'b0;
endcase
endmodule
//8位3选1
module select3_8(
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
input [1:0] choose,
output reg [7:0] out
);
always@(in1 or in2 or in3 or choose)
case(choose)
2'b00:out=in1;
2'b01:out=in2;
2'b10:out=in3;
default:out=8'b0;
endcase
endmodule
//32位4选1
module select4_32(
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [31:0] in4,
input [1:0] choose,
output reg [31:0] out
);
always@(in1 or in2 or in3 or in4 or choose)
case(choose)
2'b00:out=in1;
2'b01:out=in2;
2'b10:out=in3;
2'b11:out=in4;
default:out=32'b0;
endcase
endmodule
//8位4选1
module select4_8(
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
input [7:0] in4,
input [1:0] choose,
output reg [7:0] out
);
always@(in1 or in2 or in3 or in4 or choose)
case(choose)
2'b00:out=in1;
2'b01:out=in2;
2'b10:out=in3;
2'b11:out=in4;
default:out=8'b0;
endcase
endmodule
//32位5选1
module select5_32(
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [31:0] in4,
input [31:0] in5,
input [2:0] choose,
output reg [31:0] out
);
always@(in1 or in2 or in3 or in4 or in5 or choose)
case(choose)
3'b000:out=in1;
3'b001:out=in2;
3'b010:out=in3;
3'b011:out=in4;
3'b100:out=in5;
default:out=32'b0;
endcase
endmodule
//8位8选1
module select8_8(
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
input [7:0] in4,
input [7:0] in5,
input [7:0] in6,
input [7:0] in7,
input [7:0] in8,
input [2:0] choose,
output reg [7:0] out
);
always@(in1 or in2 or in3 or in4 or in5 or in6 or in7 or in8 or choose)
case(choose)
3'b000:out=in1;
3'b001:out=in2;
3'b010:out=in3;
3'b011:out=in4;
3'b100:out=in5;
3'b101:out=in6;
3'b110:out=in7;
3'b111:out=in8;
default:out=8'b0;
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MM_T_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_MM_T_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_MM_T
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 9)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_MM_T = {digit1,digit0};
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
reg inmod;
generate
if (1) begin
// Traces as genblk1.ingen
integer ingen;
initial $display("ingen: {mod}.genblk1 %m");
end
endgenerate
integer rawmod;
initial begin
begin
integer upa;
begin : d3nameda
// %m='.d3nameda' var=_unnamed#.d3nameda.b1
integer d3a;
$display("d3a: {mod}.d3nameda %m");
end
end
end
initial begin
integer b2;
$display("b2: {mod} %m");
begin : b3named
integer b3n;
$display("b3n: {mod}.b3named: %m");
end
if (1) begin
integer b3;
$display("b3: {mod} %m");
if (1) begin
begin
begin
begin
integer b4;
$display("b4: {mod} %m");
end
end
end
end
else begin
integer b4;
$display("bb %m");
end
end
else begin
integer b4;
$display("b4 %m");
end
tsk;
$write("*-* All Finished *-*\n");
$finish;
end
task tsk;
integer t1;
$display("t1 {mod}.tsk %m");
begin
integer t2;
$display("t2 {mod}.tsk %m");
end
endtask
endmodule
|
module step_ex_cpt(clk, rst_, ena_, rdy_, reg_id,
r0_dout,
r0_din, r1_din, r2_din, r3_din, r4_din, r5_din, fl_din, pc_din,
r0_we_, r1_we_, r2_we_, r3_we_, r4_we_, r5_we_, fl_we_, pc_we_);
input clk;
input rst_;
input ena_;
output rdy_;
input[3:0] reg_id;
input[7:0] r0_dout;
output[7:0] r0_din, r1_din, r2_din, r3_din, r4_din, r5_din, fl_din, pc_din;
output r0_we_, r1_we_, r2_we_, r3_we_, r4_we_, r5_we_, fl_we_, pc_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg state;
wire[7:0] regs_din;
reg regs_din_en;
assign regs_din = regs_din_en ? r0_dout : 8'bZ;
assign r0_din = regs_din;
assign r1_din = regs_din;
assign r2_din = regs_din;
assign r3_din = regs_din;
assign r4_din = regs_din;
assign r5_din = regs_din;
assign fl_din = regs_din;
assign pc_din = regs_din;
reg regs_we_en[15:0];
assign r0_we_ = regs_we_en[0] ? 1'b0 : 1'bZ;
assign r1_we_ = regs_we_en[1] ? 1'b0 : 1'bZ;
assign r2_we_ = regs_we_en[2] ? 1'b0 : 1'bZ;
assign r3_we_ = regs_we_en[3] ? 1'b0 : 1'bZ;
assign r4_we_ = regs_we_en[4] ? 1'b0 : 1'bZ;
assign r5_we_ = regs_we_en[5] ? 1'b0 : 1'bZ;
assign fl_we_ = regs_we_en[10] ? 1'b0 : 1'bZ;
assign pc_we_ = regs_we_en[15] ? 1'b0 : 1'bZ;
integer i;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
regs_din_en <= 0;
for(i = 0; i < 16; i = i+1)
regs_we_en[i] <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
regs_din_en <= 1;
for(i = 0; i < 16; i = i+1)
regs_we_en[i] <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
regs_din_en <= 1;
for(i = 0; i < 16; i = i+1)
regs_we_en[i] <= 0;
regs_we_en[reg_id] <= 1;
state <= 0;
end else begin
rdy_en <= 0;
regs_din_en <= 0;
for(i = 0; i < 16; i = i+1)
regs_we_en[i] <= 0;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// TX_LL_DATAPATH
//
//
// Description: This module pipelines the data path in compliance
// with Local Link protocol. Provides data to Aurora Lane
// in the required format
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_TX_LL_DATAPATH
(
// S_AXI_TX Interface
s_axi_tx_tlast,
s_axi_tx_tdata,
s_axi_tx_tvalid,
s_axi_tx_tready,
// Aurora Lane Interface
TX_PE_DATA_V,
TX_PE_DATA,
// System Interface
CHANNEL_UP,
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// S_AXI_TX Interface
input [0:63] s_axi_tx_tdata;
input s_axi_tx_tready;
input s_axi_tx_tvalid;
input s_axi_tx_tlast;
// Aurora Lane Interface
output TX_PE_DATA_V;
output [0:63] TX_PE_DATA;
// System Interface
input CHANNEL_UP;
input USER_CLK;
//**************************External Register Declarations****************************
reg [0:63] TX_PE_DATA;
reg TX_PE_DATA_V;
//**************************Internal Register Declarations****************************
reg in_frame_r;
//******************************Internal Wire Declarations****************************
wire in_frame_c;
wire ll_valid_c;
wire [0:63] tx_pe_data_c;
//*********************************Main Body of Code**********************************
// LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
assign ll_valid_c = s_axi_tx_tvalid & s_axi_tx_tready;
// Data must only be read if it is within a frame. If the frame will last multiple
// cycles, assert in_frame_r until the frame ends
always @(posedge USER_CLK)
if(!CHANNEL_UP)
in_frame_r <= `DLY 1'b0;
else if(ll_valid_c)
begin
if(s_axi_tx_tvalid && !s_axi_tx_tlast )
in_frame_r <= `DLY 1'b1;
else if(s_axi_tx_tlast)
in_frame_r <= `DLY 1'b0;
end
assign in_frame_c = ll_valid_c & (in_frame_r | s_axi_tx_tvalid);
assign tx_pe_data_c = s_axi_tx_tdata;
// Implement the data out register.
always @(posedge USER_CLK)
begin
TX_PE_DATA <= `DLY tx_pe_data_c;
TX_PE_DATA_V <= `DLY in_frame_c;
end
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
module t
(
input logic clk,
input logic daten,
input logic [8:0] datval,
output logic signed [3:0][3:0][35:0] datao
);
logic signed [3:0][3:0][3:0][8:0] datat;
genvar i;
generate
for (i=0; i<4; i++)begin
testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i]));
end
endgenerate
genvar j;
generate
for (i=0; i<4; i++) begin
for (j=0; j<4; j++) begin
always_comb datat[i][j][0] = daten ? 9'h0 : datval;
always_comb datat[i][j][1] = daten ? 9'h1 : datval;
always_comb datat[i][j][2] = daten ? 9'h2 : datval;
always_comb datat[i][j][3] = daten ? 9'h3 : datval;
end
end
endgenerate
endmodule
module testio
(
input clk,
input logic signed [3:0] [3:0] [8:0] arr3d_in,
output logic signed [3:0] [35:0] arr2d_out
);
logic signed [3:0] [35:0] ar2d_out_pre;
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_ff @(posedge clk) begin
if (clk)
arr2d_out <= ar2d_out_pre;
end
endmodule
|
// 'genx' reads in this file and does text substitutions on the various tokens of form "X_???_X"
// The resulting file is intended to be repeatedly-included into a parent module declaration,
// such that the parent module picks up the params, ports, and logic.
// genx does direct subsitution by value for data width and address width,
// instead of using the C_S_AXI_* parameters which can get stale.
// X-bracketed tags _AXI_ADDR_WIDTH_ and _AXI_DATA_WIDTH_ are the placeholders for the addr and data widths.
// if the register set / count is changed such that the address bus width changes after re-generation,
// Vivado will notice the change (unlike behavior seen with the original C_S_AXI_* parameters where it
// might latch the first seen value when component added to block design)
// if GLUE_SW_RESET is defined (set it acrosss all reinclusions) - a second reset line is provided
// so the slave device can reset itself (including all of the registers in AXI glue)
// that wire must be called SW_AXI_RESETN and must be active low, as it will get ANDed with S_AXI_RESETN.
`ifdef GLUE_EMIT_PARAMS
// ship out one dummy parameter so hosting code doesn't get stuck with an empty parameter list in parens
parameter integer DUMMY_GLUE_PARAM = 42
`endif
// ############################# ports sourced from glue
`ifdef GLUE_EMIT_PORTS
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [X_AXI_ADDR_WIDTH_X-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [X_AXI_DATA_WIDTH_X-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(X_AXI_DATA_WIDTH_X/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [X_AXI_ADDR_WIDTH_X-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [X_AXI_DATA_WIDTH_X-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
`endif
// ############################# logic sourced from glue
`ifdef GLUE_EMIT_LOGIC
`ifdef GLUE_SW_RESET
// client design has to assign to SW_AXI_ARESETN active low wire if GLUE_SW_RESET is defined.
wire SW_AXI_ARESETN;
wire GLUE_RESETN = S_AXI_ARESETN & SW_AXI_ARESETN;
`else
wire GLUE_RESETN = S_AXI_ARESETN;
`endif
// AXI4LITE signals
reg [X_AXI_ADDR_WIDTH_X-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [X_AXI_ADDR_WIDTH_X-1 : 0] axi_araddr;
reg axi_arready;
reg [X_AXI_DATA_WIDTH_X-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit databus width
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (X_AXI_DATA_WIDTH_X/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = X_AXI_OPT_MEM_ADDR_BITS_X;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
// genx inserts physical reg declarations here, including any extra wires / regs for readthrough/writethrough mode
X_GLUE_REGISTER_INSTANCES_X
wire slv_reg_rden;
wire slv_reg_wren;
reg [X_AXI_DATA_WIDTH_X-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
// genx inserts register reset statements here for all regs, no matter what mode
X_GLUE_REGISTER_RESETS_X
end
else begin
// genx inserts assignments for all write tick regs to zero here (one may get set back to 1 below in the switch if a write happens)
X_GLUE_REGISTER_CLEAR_WRTICKS_X
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS-1:ADDR_LSB] )
// genx inserts per-address write handling cases here
// must **omit** any regs which are readthrough (they get assigned below)
// write cases for registers which are writethrough must *also* set the write tick reg paired with that reg.
X_GLUE_REGISTER_WRITECASES_X
endcase
end
// genx inserts source assignments for readthrough regs here
X_GLUE_REGISTER_READTHROUGHS_X
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @( * )
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS-1:ADDR_LSB] )
// genx inserts per-address readcases here
// (plus a default for address miss, return zero)
// note that no reg is ever written in this block
X_GLUE_REGISTER_READCASES_X
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( GLUE_RESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read data
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
`endif
|
`include "alu.v"
`include "sim.v"
`ifndef TESTS
`define TESTS 32
`endif
module test();
wire reset;
wire clk;
// Connecting wires
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [1:0] alu_cmd;
wire [31:0] alu_result;
wire alu_res_valid;
wire alu_ready;
// You can use arrays (even multidimensional
reg [32+32-1:0] tests [0:`TESTS-1];
reg done = 1'b0;
// This is not synthetizable
integer i;
// Initial block
initial begin
for(i = 0; i < `TESTS; i = i + 1) begin
tests[i] <= {{$random},{$random}};
end
end
reg [31:0] t = 5'h0;
reg [31:0] a,b,res;
reg [1:0] op = `OP_NOP;
assign alu_a = a;
assign alu_b = b;
assign alu_cmd = op;
always @(posedge alu_res_valid) begin
if (alu_result != res)
$display("Result wrong!");
end
always @(posedge alu_ready) begin
a <= tests[t][63:32];
b <= tests[t][31:0];
op <= `OP_ADD;
res <= tests[t][63:32] + tests[t][31:0];
if (t + 1 < `TESTS)
t = t + 1;
else begin
//finish here?
t = 0;
done = 1'b1;
end
end
// ALU module
alu my_alu
(
.clk(clk),
.reset(reset),
.i_a(alu_a),
.i_b(alu_b),
.i_cmd(alu_cmd),
.o_result(alu_result),
.o_valid(alu_res_valid),
.o_ready(alu_ready)
);
// Simulator (clock + reset)
sim my_sim(
.clk(clk),
.reset(reset)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_HD__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:55:15 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/system_vga_gaussian_blur_0_0_stub.v
// Design : system_vga_gaussian_blur_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_gaussian_blur,Vivado 2016.4" *)
module system_vga_gaussian_blur_0_0(clk_25, hsync_in, vsync_in, rgb_in, hsync_out,
vsync_out, rgb_blur, rgb_pass)
/* synthesis syn_black_box black_box_pad_pin="clk_25,hsync_in,vsync_in,rgb_in[23:0],hsync_out,vsync_out,rgb_blur[23:0],rgb_pass[23:0]" */;
input clk_25;
input hsync_in;
input vsync_in;
input [23:0]rgb_in;
output hsync_out;
output vsync_out;
output [23:0]rgb_blur;
output [23:0]rgb_pass;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: dtysky:user:CONTROL_UNIT:1.0
// IP Revision: 3
(* X_CORE_INFO = "CONTROL_UNIT,Vivado 2014.2" *)
(* CHECK_LICENSE_TYPE = "MIPS_CPU_CONTROL_UNIT_0_1,CONTROL_UNIT,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MIPS_CPU_CONTROL_UNIT_0_1 (
op,
func,
z,
wreg,
regrt,
jal,
m2reg,
shfit,
aluimm,
sext,
wmem,
aluc,
pcsource
);
input wire [5 : 0] op;
input wire [5 : 0] func;
input wire z;
output wire wreg;
output wire regrt;
output wire jal;
output wire m2reg;
output wire shfit;
output wire aluimm;
output wire sext;
output wire wmem;
output wire [3 : 0] aluc;
output wire [1 : 0] pcsource;
CONTROL_UNIT #(
.cmd_add(6'B100000),
.cmd_sub(6'B100010),
.cmd_and(6'B100100),
.cmd_or(6'B100101),
.cmd_xor(6'B100110),
.cmd_sll(6'B000000),
.cmd_srl(6'B000010),
.cmd_sra(6'B000011),
.cmd_jr(6'B001000),
.cmd_addi(6'B001000),
.cmd_andi(6'B001100),
.cmd_ori(6'B001101),
.cmd_xori(6'B001110),
.cmd_lw(6'B100011),
.cmd_sw(6'B101011),
.cmd_beq(6'B000100),
.cmd_bne(6'B000101),
.cmd_lui(6'B001111),
.cmd_j(6'B000010),
.cmd_jal(6'B000011)
) inst (
.op(op),
.func(func),
.z(z),
.wreg(wreg),
.regrt(regrt),
.jal(jal),
.m2reg(m2reg),
.shfit(shfit),
.aluimm(aluimm),
.sext(sext),
.wmem(wmem),
.aluc(aluc),
.pcsource(pcsource)
);
endmodule
|
`timescale 1ns / 1ps
`define MAX 32'h0A000000
module top(
input main_clk,
input rst_n,
output [3:0] o_led_n,
input [3:0] i_button,
input [1:0] i_switch,
//GPIF Signals
inout [31:0] io_gpif_data,
output o_gpif_clk,
output o_gpif_oe_n,
output o_gpif_re_n,
output o_gpif_we_n,
output o_gpif_pkt_end_n,
input i_gpif_in_ch0_rdy,
input i_gpif_in_ch1_rdy,
input i_gpif_out_ch0_rdy,
input i_gpif_out_ch1_rdy,
output [1:0] o_gpif_socket_addr
);
//Local Parameters
//Registers/Wires
wire rst;
wire clk;
reg [3:0] led;
reg [31:0] count;
//Although this is statically declared, in the future this should be be
//dynamically found by measuring the ready signal of a read or write
wire [31:0] w_packet_size;
//Master Interface
wire w_master_ready;
wire [7:0] w_command;
wire [7:0] w_flag;
wire [31:0] w_rw_count;
wire [31:0] w_address;
wire w_command_rdy_stb;
wire [7:0] w_status;
wire [31:0] w_read_size;
wire w_status_rdy_stb;
wire [31:0] w_status_address;
//Write side FIFO interface
wire w_wpath_ready;
wire w_wpath_activate;
wire [23:0] w_wpath_packet_size;
wire [31:0] w_wpath_data;
wire w_wpath_strobe;
//Read side FIFO interface
wire [1:0] w_rpath_ready;
wire [1:0] w_rpath_activate;
wire [23:0] w_rpath_size;
wire [31:0] w_rpath_data;
wire w_rpath_strobe;
//Master Interface Signals
fx3_bus bus (
.clk (clk ),
.rst (rst ),
.io_data (io_gpif_data ),
.o_oe_n (o_gpif_oe_n ),
.o_we_n (o_gpif_we_n ),
.o_re_n (o_gpif_re_n ),
.o_pkt_end_n (o_gpif_pkt_end_n ),
.i_in_ch0_rdy (i_gpif_in_ch0_rdy ),
.i_in_ch1_rdy (i_gpif_in_ch1_rdy ),
.i_out_ch0_rdy (i_gpif_out_ch0_rdy ),
.i_out_ch1_rdy (i_gpif_out_ch1_rdy ),
.o_socket_addr (o_gpif_socket_addr ),
.i_master_ready (w_master_ready ),
.o_command (w_command ),
.o_flag (w_flag ),
.o_rw_count (w_rw_count ),
.o_address (w_address ),
.o_command_rdy_stb (w_command_rdy_stb ),
.i_status (w_status ),
.i_read_size (w_read_size ),
.i_status_rdy_stb (w_status_rdy_stb ),
.i_address (w_status_address ),
.o_wpath_ready (w_wpath_ready ),
.i_wpath_activate (w_wpath_activate ),
.o_wpath_packet_size (w_wpath_packet_size ),
.o_wpath_data (w_wpath_data ),
.i_wpath_strobe (w_wpath_strobe ),
.o_rpath_ready (w_rpath_ready ),
.i_rpath_activate (w_rpath_activate ),
.o_rpath_size (w_rpath_size ),
.i_rpath_data (w_rpath_data ),
.i_rpath_strobe (w_rpath_strobe )
);
master m (
.clk (clk ),
.rst (rst ),
.o_master_ready (w_master_ready ),
.i_command (w_command ),
.i_flag (w_flag ),
.i_rw_count (w_rw_count ),
.i_address (w_address ),
.i_command_rdy_stb (w_command_rdy_stb ),
.o_status (w_status ),
.o_read_size (w_read_size ),
.o_status_rdy_stb (w_status_rdy_stb ),
.o_address (w_status_address ),
.i_wpath_ready (w_wpath_ready ),
.o_wpath_activate (w_wpath_activate ),
.i_wpath_packet_size (w_wpath_packet_size ),
.i_wpath_data (w_wpath_data ),
.o_wpath_strobe (w_wpath_strobe ),
.i_rpath_ready (w_rpath_ready ),
.o_rpath_activate (w_rpath_activate ),
.i_rpath_size (w_rpath_size ),
.o_rpath_data (w_rpath_data ),
.o_rpath_strobe (w_rpath_strobe )
);
//Asynchronous Logic
assign clk = main_clk;
assign rst = rst_n;
assign o_led_n = ~led;
assign o_gpif_clk= clk;
//A controller should be put in place (within the fx3_bus that will select the
//correct address, this also requires a change of the GPIF
//Guessing 512 per packet (USB 2.0)
assign w_packet_size = 128;
//Synchronous Logic
always @ (posedge main_clk) begin
if (!rst) begin
led[0] <= 0;
led[1] <= 0;
led[2] <= 0;
led[3] <= 0;
count <= 0;
end
else begin
if (count < `MAX) begin
count <= count + 1;
end
else begin
count <= 0;
led[0] <= ~led[0];
end
if (i_button[1]) begin
led[0] <= 1;
led[1] <= 1;
led[2] <= 1;
led[3] <= 1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:04:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0_1/system_processing_system7_0_0_sim_netlist.v
// Design : system_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_processing_system7_0_0
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
system_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module system_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: capture_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [4:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [4:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire [4:0] rdusedw = sub_wire3[4:0];
wire wrempty = sub_wire4;
wire wrfull = sub_wire5;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.rdusedw (sub_wire3),
.wrempty (sub_wire4),
.wrfull (sub_wire5),
.eccstatus (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 16,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 64,
dcfifo_mixed_widths_component.lpm_widthu = 4,
dcfifo_mixed_widths_component.lpm_widthu_r = 5,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "OFF",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "OFF",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_bb.v TRUE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_SYMBOL_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_decapkapwr ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_SYMBOL_V
|
/*
*
* Copyright (c) 2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/* Calculates the hash of the given public key.
* Will use the compressed public key.
*/
module address_hash (
input clk,
input rx_reset,
input [255:0] rx_x,
input [255:0] rx_y,
output tx_done,
output [159:0] tx_hash
);
reg ripe_reset = 1'b1;
wire sha_done;
wire [255:0] sha_hash;
sha256 sha256_blk (
.clk (clk),
.rx_reset (rx_reset),
.rx_public_key ({7'h1, rx_y[0], rx_x}),
.tx_done (sha_done),
.tx_hash (sha_hash)
);
ripemd160 ripemd160_blk (
.clk (clk),
.rx_reset (rx_reset | ripe_reset),
.rx_hash (sha_hash),
.tx_done (tx_done),
.tx_hash (tx_hash)
);
always @ (posedge clk)
begin
if (rx_reset)
ripe_reset <= 1'b1;
else if (sha_done)
ripe_reset <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_SYMBOL_V
`define SKY130_FD_SC_HD__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_bleeder (
SHORT,
VPWR ,
VGND ,
VPB ,
VNB
);
input SHORT;
inout VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:47:53 05/14/2016
// Design Name:
// Module Name: DEA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DEA(
input Clk_100M,
input Reset,
input prevCharBtn, // goes from left to right.
input nextCharBtn, // goes from right to left.
input Rx,
output Tx,
output reg [15:0]LEDs
);
reg prevBusyState;
wire Rx_Ready;
reg Rx_Ack;
wire [7:0] Rx_Data;
reg [7:0] Tx_Data;
reg Tx_Send;
wire Tx_Busy;
reg Tx_Reset;
reg [7:0] Tx_DataIndex;
reg Tx_DataIndexLocked;
reg encrypt_Ack;
reg encrypt_Ready;
wire [7:0] encrypt_Data;
reg [7:0] sizeOfDataInByte;
reg [7:0] currentCharIndex;
reg [7:0] userData [0:99];
reg [7:0] result [0:99];
reg [7:0] charCount;
reg [7:0] sizeOfKeyInByte;
reg [7:0] keys[0:2];
reg [7:0] keyCount;
reg prevCharBtnPreviousState;
reg nextCharBtnPreviousState;
wire prevCharBtnNextState;
wire nextCharBtnNextState;
initial prevBusyState = 1'b0;
reg receivingData;
reg receivingKeys;
reg [7:0] index;
reg [1:0] keyIndex;
reg [7:0] byteOfUserData;
reg [7:0] byteOfKey;
assign encrypt_Data = byteOfUserData ^ byteOfKey;
initial sizeOfDataInByte = 1'b0;
initial sizeOfKeyInByte = 1'b0;
reg sentSizeOfDataInByte;
reg doneEncrypting;
always @(posedge Clk_100M) begin
if(Reset) begin
currentCharIndex <= 1'b0;
charCount <= 1'b0;
keyCount <= 1'b0;
Rx_Ack <= 1'b0;
//encrypt_Ack <= 1'b0;
receivingData <= 1'b0;
receivingKeys <= 1'b0;
end
else begin
if (prevBusyState & Rx_Ready) begin
// very first byte expected to be # characters in data.
if (sizeOfDataInByte == 0) begin
sizeOfDataInByte <= Rx_Data; // get number of charcters in data.
receivingData <= 1'b1; // next up start receiving data.
end
// actual data starts from byte 2.
else if (receivingData) begin
userData[charCount] <= Rx_Data; // actual data.
charCount <= charCount + 1'b1;
// if done receiving data, receive key.
if (charCount == sizeOfDataInByte - 1) begin
receivingData <= 1'b0; // to indicate finish receiving data.
end
end
// next up receive # of keys.
else if (sizeOfKeyInByte == 0) begin
sizeOfKeyInByte <= Rx_Data;
receivingKeys <= 1'b1; // next up we start receiving keys.
end
else if (receivingKeys) begin
keys[keyCount] <= Rx_Data;
keyCount <= keyCount + 1'b1;
// if done receiving data, signal start of encryption.
if (keyCount == sizeOfKeyInByte) begin
receivingKeys <= 1'b0; // to indicate finish receiving keys.
//startEncryption = 1'b1;
end
end
Rx_Ack <= 1'b1;
end else if(~Rx_Ready) begin
Rx_Ack <= 1'b0;
end
prevBusyState <= !Rx_Ready;
//------------------------------------------------------------------------------
// if btn P17 pressed move/shift left
if (prevCharBtnPreviousState == 1'b0 && prevCharBtnNextState == 1'b1) begin
prevCharBtnPreviousState <= prevCharBtnNextState;
if (currentCharIndex > 0)
currentCharIndex <= currentCharIndex - 1'b1;
else
currentCharIndex <= sizeOfDataInByte - 1'b1;
//currentCharIndex <= (currentCharIndex - 1'b1) % sizeOfDataInByte;
end else
prevCharBtnPreviousState <= prevCharBtnNextState;
// if btn M17 pressed move/shift right
if (nextCharBtnPreviousState == 1'b0 && nextCharBtnNextState == 1'b1) begin
nextCharBtnPreviousState <= nextCharBtnNextState;
if (currentCharIndex < sizeOfDataInByte - 1)
currentCharIndex <= currentCharIndex + 1'b1;
else
currentCharIndex <= 1'b0;
end else
nextCharBtnPreviousState <= nextCharBtnNextState;
end
end
//------------------------------------------------------------------------------
always @(posedge Clk_100M) begin
// pull encrypt_Ack low.
// Wait for encrypt_Ready to go high.
// Read the data.
// Make encrypt_Ack high.
// Wait for encrypt_Ready to go low.
// Make encrypt_Ack low.
if (Reset) begin
encrypt_Ack <= 1'b0;
index <= 1'b0; // reset index
keyIndex <= 1'b0;
doneEncrypting <= 1'b0;
end
else begin
if (index < sizeOfDataInByte) begin
if (encrypt_Ready & encrypt_Ack) begin
result[index] <= encrypt_Data;
encrypt_Ack <= 1'b1; // reset encryption engine.
encrypt_Ready <= 1'b0;
if (index == sizeOfDataInByte - 1)
doneEncrypting <= 1;
end
else if (~encrypt_Ready & encrypt_Ack) begin
index <= index + 1'b1;
if (keyIndex < (sizeOfKeyInByte - 1))
keyIndex <= keyIndex + 1'b1;
else
keyIndex <= 1'b0;
encrypt_Ready <= 1'b1;
encrypt_Ack <= 1'b0;
end
else if (~encrypt_Ack) begin
byteOfUserData <= userData[index]; // grab a new byte of data.
byteOfKey <= keys [keyIndex];
encrypt_Ack <= 1'b1;
encrypt_Ready <= 1'b1;
end
end
end
end
// SENDING
always @(posedge Clk_100M) begin
if (Reset) begin
Tx_Data <= 1'b0;
Tx_Send <= 1'b0;
Tx_Reset <= 1'b0;
Tx_DataIndex <= 1'b0;
Tx_DataIndexLocked <= 1'b1; // used to lock Tx_DataIndex to prevent uncontrolled increments.
end
else if (doneEncrypting) begin
if (Tx_Busy == 0 && Tx_DataIndex < sizeOfDataInByte) begin
Tx_Data <= result[Tx_DataIndex];
Tx_Send <= 1'b1;
Tx_DataIndexLocked <= 1'b0;
end
else begin
if (~Tx_DataIndexLocked) begin
Tx_DataIndex <= Tx_DataIndex + 1'b1;
Tx_DataIndexLocked <= 1'b1;
end
Tx_Send <= 1'b0;
end
end
end
UART_Sender #(14, 14'd9999) sender(
Clk_100M,
//Tx_Reset,
Reset,
Tx_Data,
Tx_Send,
Tx_Busy,
Tx
);
UART_Receiver #(14, 14'd9999) receiver(
Clk_100M,
Reset,
Rx_Data,
Rx_Ready,
Rx_Ack,
Rx
);
Debounce debouncePrevBtn(
Clk_100M,
prevCharBtn,
prevCharBtnNextState
);
Debounce debounceNextBtn(
Clk_100M,
nextCharBtn,
nextCharBtnNextState
);
always @(*) begin
// displays characters on the LEDs. Characters are shifted using btn P17 and M17
// going from left to right and right to left respectively.
//LEDs[15:8] <= Tx_DataIndex; // check
LEDs[15:8] <= result[currentCharIndex];
//LEDs[15:8] <= encrypt_Data;
//LEDs[15:8] <= byteOfUserData;
//LEDs[15:8] <= keys[currentCharIndex%3]; // check
//LEDs[15:8] <= index; // check
//LEDs[15:8] <= sizeOfKeyInByte; // check
//LEDs[7:0] <= userData[99-currentCharIndex];
LEDs[7:0] <= userData[currentCharIndex]; // check
//LEDs[15:0] <= 16'b1111111111111111;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON128_NEXT 6'b00_0001
`define S_TXPORTMON128_EVT_2 6'b00_0010
`define S_TXPORTMON128_TXN 6'b00_0100
`define S_TXPORTMON128_READ 6'b00_1000
`define S_TXPORTMON128_END_0 6'b01_0000
`define S_TXPORTMON128_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE4Lo=0, _rLenLE4Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON128_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
assign TXN = rState[2]; // S_TXPORTMON128_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON128_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_EVT_2;
end
`S_TXPORTMON128_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_TXN;
end
`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);
end
`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON128_END_0;
end
`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
end
`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_NEXT;
end
default: begin
_rState = `S_TXPORTMON128_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE4Lo <= #1 _rLenLE4Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[63:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 4, we want to trigger the almost all received flag
_rLenLE4Lo = (LEN[15:0] <= 16'd4);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
endmodule
|
/*******************************************************************************
* Function: ENOC Command Decoder
* Author: Andreas Olofsson
* License: MIT (see LICENSE file in OH! repository)
*
* see ./enoc_pack.v
*
******************************************************************************/
module enoc_decode
(
//Packet Command
input [15:0] cmd_in,
//Write
output cmd_write,
output cmd_write_stop,
//Read
output cmd_read,
output cmd_atomic_add,
output cmd_atomic_and,
output cmd_atomic_or,
output cmd_atomic_xor,
output cmd_cas,
//Fields
output [3:0] cmd_opcode,
output [3:0] cmd_length,
output [2:0] cmd_size,
output [7:0] cmd_user
);
//############################################
// Command Decode
//############################################
//Writes
assign cmd_write = ~cmd_in[3];
assign cmd_write_stop = cmd_in[3:0]==1001;
//Reads/atomics
assign cmd_read = cmd_in[3:0]==1000;
assign cmd_atomic_cas = cmd_in[3:0]==1011;
assign cmd_atomic_add = cmd_in[3:0]==1100;
assign cmd_atomic_and = cmd_in[3:0]==1101;
assign cmd_atomic_or = cmd_in[3:0]==1110;
assign cmd_atomic_xor = cmd_in[3:0]==1111;
//Field Decode
assign cmd_opcode[3:0] = cmd_in[3:0];
assign cmd_length[3:0] = cmd_in[7:4];
assign cmd_size[2:0] = cmd_in[10:8];
assign cmd_user[7:0] = cmd_in[15:8];
endmodule // enoc_decode
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_spc_rpt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
`include "iop.h"
`include "ifu.h"
`include "lsu.h"
module cpx_spc_rpt (/*AUTOARG*/
// Outputs
so, cpx_spc_data_cx3, cpx_spc_data_rdy_cx3,
cpx_spc_data_cx3_b144to140, cpx_spc_data_cx3_b120to118,
cpx_spc_data_cx3_b0, cpx_spc_data_cx3_b4, cpx_spc_data_cx3_b8,
cpx_spc_data_cx3_b12, cpx_spc_data_cx3_b16, cpx_spc_data_cx3_b20,
cpx_spc_data_cx3_b24, cpx_spc_data_cx3_b28, cpx_spc_data_cx3_b32,
cpx_spc_data_cx3_b35, cpx_spc_data_cx3_b38, cpx_spc_data_cx3_b41,
cpx_spc_data_cx3_b44, cpx_spc_data_cx3_b47, cpx_spc_data_cx3_b50,
cpx_spc_data_cx3_b53, cpx_spc_data_cx3_b56, cpx_spc_data_cx3_b60,
cpx_spc_data_cx3_b64, cpx_spc_data_cx3_b68, cpx_spc_data_cx3_b72,
cpx_spc_data_cx3_b76, cpx_spc_data_cx3_b80, cpx_spc_data_cx3_b84,
cpx_spc_data_cx3_b88, cpx_spc_data_cx3_b91, cpx_spc_data_cx3_b94,
cpx_spc_data_cx3_b97, cpx_spc_data_cx3_b100,
cpx_spc_data_cx3_b103, cpx_spc_data_cx3_b106,
cpx_spc_data_cx3_b109,
// Inputs
rclk, si, se, cpx_spc_data_cx2, cpx_spc_data_rdy_cx2
);
input rclk;
input si;
input se;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
input cpx_spc_data_rdy_cx2;
output so;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx3;
output cpx_spc_data_rdy_cx3;
output [`CPX_WIDTH-1:140] cpx_spc_data_cx3_b144to140 ;
output [`CPX_INV_CID_HI:`CPX_INV_CID_LO] cpx_spc_data_cx3_b120to118 ;
output cpx_spc_data_cx3_b0 ;
output cpx_spc_data_cx3_b4 ;
output cpx_spc_data_cx3_b8 ;
output cpx_spc_data_cx3_b12 ;
output cpx_spc_data_cx3_b16 ;
output cpx_spc_data_cx3_b20 ;
output cpx_spc_data_cx3_b24 ;
output cpx_spc_data_cx3_b28 ;
output cpx_spc_data_cx3_b32 ;
output cpx_spc_data_cx3_b35 ;
output cpx_spc_data_cx3_b38 ;
output cpx_spc_data_cx3_b41 ;
output cpx_spc_data_cx3_b44 ;
output cpx_spc_data_cx3_b47 ;
output cpx_spc_data_cx3_b50 ;
output cpx_spc_data_cx3_b53 ;
output cpx_spc_data_cx3_b56 ;
output cpx_spc_data_cx3_b60 ;
output cpx_spc_data_cx3_b64 ;
output cpx_spc_data_cx3_b68 ;
output cpx_spc_data_cx3_b72 ;
output cpx_spc_data_cx3_b76 ;
output cpx_spc_data_cx3_b80 ;
output cpx_spc_data_cx3_b84 ;
output cpx_spc_data_cx3_b88 ;
output cpx_spc_data_cx3_b91 ;
output cpx_spc_data_cx3_b94 ;
output cpx_spc_data_cx3_b97 ;
output cpx_spc_data_cx3_b100 ;
output cpx_spc_data_cx3_b103 ;
output cpx_spc_data_cx3_b106 ;
output cpx_spc_data_cx3_b109 ;
reg [`CPX_WIDTH-1:0] cpx_spc_data_cx3;
reg cpx_spc_data_rdy_cx3;
always @(posedge rclk) begin
cpx_spc_data_cx3 <= cpx_spc_data_cx2;
cpx_spc_data_rdy_cx3 <= cpx_spc_data_rdy_cx2;
end
//timing fix: 9/5/03 - add separate buffer to lsu for signal that are used in bypass i.e. isolate from spu/ffu loading
assign cpx_spc_data_cx3_b144to140[`CPX_WIDTH-1:140] = cpx_spc_data_cx3[`CPX_WIDTH-1:140] ;
assign cpx_spc_data_cx3_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO] = cpx_spc_data_cx3[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
assign cpx_spc_data_cx3_b0 = cpx_spc_data_cx3[0] ;
assign cpx_spc_data_cx3_b4 = cpx_spc_data_cx3[4] ;
assign cpx_spc_data_cx3_b8 = cpx_spc_data_cx3[8] ;
assign cpx_spc_data_cx3_b12 = cpx_spc_data_cx3[12] ;
assign cpx_spc_data_cx3_b16 = cpx_spc_data_cx3[16] ;
assign cpx_spc_data_cx3_b20 = cpx_spc_data_cx3[20] ;
assign cpx_spc_data_cx3_b24 = cpx_spc_data_cx3[24] ;
assign cpx_spc_data_cx3_b28 = cpx_spc_data_cx3[28] ;
assign cpx_spc_data_cx3_b32 = cpx_spc_data_cx3[32] ;
assign cpx_spc_data_cx3_b35 = cpx_spc_data_cx3[35] ;
assign cpx_spc_data_cx3_b38 = cpx_spc_data_cx3[38] ;
assign cpx_spc_data_cx3_b41 = cpx_spc_data_cx3[41] ;
assign cpx_spc_data_cx3_b44 = cpx_spc_data_cx3[44] ;
assign cpx_spc_data_cx3_b47 = cpx_spc_data_cx3[47] ;
assign cpx_spc_data_cx3_b50 = cpx_spc_data_cx3[50] ;
assign cpx_spc_data_cx3_b53 = cpx_spc_data_cx3[53] ;
assign cpx_spc_data_cx3_b56 = cpx_spc_data_cx3[56] ;
assign cpx_spc_data_cx3_b60 = cpx_spc_data_cx3[60] ;
assign cpx_spc_data_cx3_b64 = cpx_spc_data_cx3[64] ;
assign cpx_spc_data_cx3_b68 = cpx_spc_data_cx3[68] ;
assign cpx_spc_data_cx3_b72 = cpx_spc_data_cx3[72] ;
assign cpx_spc_data_cx3_b76 = cpx_spc_data_cx3[76] ;
assign cpx_spc_data_cx3_b80 = cpx_spc_data_cx3[80] ;
assign cpx_spc_data_cx3_b84 = cpx_spc_data_cx3[84] ;
assign cpx_spc_data_cx3_b88 = cpx_spc_data_cx3[88] ;
assign cpx_spc_data_cx3_b91 = cpx_spc_data_cx3[91] ;
assign cpx_spc_data_cx3_b94 = cpx_spc_data_cx3[94] ;
assign cpx_spc_data_cx3_b97 = cpx_spc_data_cx3[97] ;
assign cpx_spc_data_cx3_b100 = cpx_spc_data_cx3[100] ;
assign cpx_spc_data_cx3_b103 = cpx_spc_data_cx3[103] ;
assign cpx_spc_data_cx3_b106 = cpx_spc_data_cx3[106] ;
assign cpx_spc_data_cx3_b109 = cpx_spc_data_cx3[109] ;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:36:53 07/12/2015
// Design Name:
// Module Name: Dirty_Ram
// Project Name:
// Target Devices:
// Tool versions:
// Description: Output of 0 is Clean. Output of 1 is Dirty.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Dirty_Ram(
input Clock_in,
input Reset_in,
input [3:0] Index_in,
input Dirty_in,
input Write_Dirty_in,
output Dirty_out,
input [7:0] Counter_in,
output reg Init_Dirty_out
);
Distributed_RAM #(4,1,16) DIRTY_RAM(
.Clock_in (Clock_in),
.Write_Enable_in ((Init_Dirty_out) ? 1'b1 : Write_Dirty_in),
.Address_in ((Init_Dirty_out) ? Counter_in[3:0] : Index_in),
.Data_in ((Init_Dirty_out) ? 1'b0 : Dirty_in),
.Data_out (Dirty_out)
);
always @ (posedge Clock_in) begin
if (Reset_in) begin
Init_Dirty_out = 1'b1;
end
else begin
if (Counter_in == 8'b00010000) begin
Init_Dirty_out = 1'b0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_SYMBOL_V
`define SKY130_FD_SC_HS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlaveTopAltera.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlaveTopAltera (
clk,
sda,
scl,
LED
);
input clk;
inout sda;
input scl;
output LED;
//local wires and regs
reg [1:0] rstReg;
wire rst;
wire pll_locked;
wire [7:0] myReg0;
assign LED = myReg0[0];
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sda(sda),
.scl(scl),
.myReg0(myReg0),
.myReg1(),
.myReg2(),
.myReg3(),
.myReg4(8'h12),
.myReg5(8'h34),
.myReg6(8'h56),
.myReg7(8'h78)
);
pll_48MHz pll_48MHz_inst (
.inclk0 ( clk ),
.locked( pll_locked)
);
//generate sync reset from pll lock signal
always @(posedge clk) begin
rstReg[1:0] <= {rstReg[0], ~pll_locked};
end
assign rst = rstReg[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_SYMBOL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_PP_SYMBOL_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes 'success' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* 'success' is not available until the next clock cycle.
*
* Prioritised inputs
* ==================
*
* [priority_support = 0 | 1]
*
* Input requested are prioritized by associated 'req_priority' input,
* may be anything from a single bit to N-bits wide.
*
* e.g. for 16 priority levels:
*
* parameter priority_support = 1;
* parameter type priority_type = bit unsigned [3:0];
*
* Note: The priority input is ignored if the associated request is
* not asserted.
*
*/
//#################################
// NOT IMPLEMENTED YET:
//
// - parameter GRANT_HOLD
// don't update matrix state until request
// assoc. with current grant is released
// - winning request will hold grant for as long as it is asserted
//
// - parameter PRIORITIZE first F inputs -
// inputs 0..F are priority inputs
// input 0 will be granted if requested
// input 1 will be granted (if input 0 is not asserted)
// ..etc to input F
//
// weighted arbiter,....
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
parameter priority_support = 0;
input [size-1:0] request;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
assign req = request;
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state<='1; //-1;
next_state<='1; //-1;
end else begin
// **************************************************
// Multistage Arbiter with Late Success Notification (multistage==2)
// **************************************************
if (multistage==2) begin
update<=|req;
if (|req) begin
// This 'next_state' will only be used on next clock cycle if
// 'success' is asserted
next_state <= new_state;
end
if (update) begin
current_state <= state;
end
end else begin
// ************************************
// Multistage Arbiter (multistage==1)
// ************************************
// check request was ultimately successful before updating arbiter state
// we know about success before the next clock cycle.
if ((multistage==1)&!success) begin
// request was not ultimately successful, don't update priorities
end else begin
// **********************************
// Basic Arbiter (multistage==0)
// **********************************
// Update state whenever at least one request has been made
if (|req) begin
current_state<=new_state;
end
end
end
end
end
endmodule
|
/* Verilog implementation of MBUS
*
* < COMPILER DIRECTIVES >
* The following compiler directives may need to be set in a separate file
* depending on user's need. See an example file.
* --------------------------------------------------------------------------
* LNAME_MBUS_FULL_PREFIX [MBus Full Prefix]
* --------------------------------------------------------------------------
*
*
* < DESCRIPTION >
* This block is the new bus controller, maintaining the same interface
* as the previous I2C controller. However, the current implementation of
* MBUS makes certain assumptions about the transmissions:
*
* 1. The transmission each round is always 32-bits, i.e. TX_DATA is 32-bit
* wide. This could be changed in the definitions file include/mbus_def.v
*
* 2. Transmissions only use short (8-bit) addresses.
*
* In addition, MBUS adds new features:
*
* 1. The additional TX_PRIORITY input. This input sets the transmission
* priority. If the TX_PRIORITY input has been asserted, it gives additional
* flexibility for the lower layer to win bus arbitration.
*
* 2. TX_PEND, RX_PEND. These inputs indicate more data coming after first
* transmission, i.e. if TX_REQ and TX_PEND are asserted at the same time,
* when the MBUS controller latches the inputs the BUS controller knows more
* data to the same destination will follow. If the next TX_REQ does not assert
* in time, the bus controller experiences a TX_FAIL (tx buffer underflow).
* Similarly for RX_PEND, if RX_REQ is asserted the layer controller must also
* monitorthe RX_PEND signal, which indicates more data for the same message
* follows.
*
* 3. The broadcast message. Every layer in MBUS will receive and acknowledge
* broadcast messages. The destination address of broadcast message is 0x00.
*
*
* < AUTHORS >
* Last modified date: Dec 16, 2016
* Last modified by: Yejoong Kim <[email protected]>
* Originally Created by: Yoonmyung Lee <[email protected]>
* Ye-sheng Kuo <[email protected]>
*
* < UPDATE LOG >
* 12/16/2016: Included in MBus r04 (Yejoong Kim)
* Removed CLR_BUSY, and added MBUS_BUSY
* Added MBUS_BUSY generation
* 05/21/2016: Included in MBus r03 (Yejoong Kim)
* Replaced CPU_LAYER parameter with MASTER_NODE
* 05/11/2016: Included in MBus r02 (Yejoong Kim)
* 01/06/2016: Added Pat Fix (wrong CTRL0 data bit)
* 11/10/2015: Re-organize & re-name compiler directives
* 11/08/2013: fix MBUS_NODE_POWER_GATING macro
* 09/05/2013: Change port names:
* RELEASE_RST_FROM_SLEEP_CTRL -> MBC_RESET
* POWER_ON_TO_LAYER_CTRL -> LRC_SLEEP
* RELEASE_CLK_TO_LAYER_CTRL -> LRC_CLKENB
* RELEASE_ISO_TO_LAYER_CTRL -> LRC_ISOLATE
* RELEASE_RST_TO_LAYER_CTRL -> LRC_RESET
* 05/09/2013: Change tx_broadcast_latched from TX_ADDR to ADDR
* 05/06/2013: Rename PRIORITY -> TX_PRIORITY
* 05/01/2013: Add CLR_BUSY Port
* 04/28/2013: fixed streaming broadcast RX_REQ asserts in between
* 04/24/2013: change RX_REQ, RX_FAIL and RX_PEND by asynchronize reset from RX_ACK
* 04/16/2013: fixed reset state for control node, since control node has different sleep
* controller, it resets bus controller before clk chain ticks. Thus, it
* should go to BUS_ILDE state for control node
* 04/15/2013: remove BUS_PWR_OVERRIDE port
* 04/14/2013: Add power related signals, these signals are only for simulation, in real
* setting, the isolation block will assert these signals to layer controller
* Add a BUS_PWR_OVERRIDE port, this signal indicates ctrl_wrapper to switch
* the mux
* 04/09/2013: changed to 32-bit long and short address scheme, add external int,
* 03/16/2013: Add power gated signals, move reset state to RX_ADDR
* 03/06/2013: switch clock mux to posedge edge trigger, clock holds at high if a node request
* interrupt, bypass clock once interrupt occurred
* */
`include "include/lname_mbus_def.v"
module lname_mbus_node(
input CIN,
input RESETn,
input DIN,
output reg COUT,
output reg DOUT,
input [`MBUS_ADDR_WIDTH-1:0] TX_ADDR,
input [`MBUS_DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
output reg TX_ACK,
input TX_PRIORITY,
output reg [`MBUS_ADDR_WIDTH-1:0] RX_ADDR,
output reg [`MBUS_DATA_WIDTH-1:0] RX_DATA,
output reg RX_PEND,
output reg RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output reg RX_FAIL,
output reg TX_FAIL,
output reg TX_SUCC,
input TX_RESP_ACK,
output MBC_IN_FWD,
`ifdef MBUS_NODE_POWER_GATING
// power gated signals from sleep controller
input MBC_RESET,
// power gated signals to layer controller
output reg LRC_SLEEP,
output reg LRC_CLKENB,
output reg LRC_RESET,
output reg LRC_ISOLATE,
// power gated signal to sleep controller
output reg SLEEP_REQUEST_TO_SLEEP_CTRL,
// External interrupt
input EXTERNAL_INT,
output reg CLR_EXT_INT,
output reg MBUS_BUSY,
`endif
// interface with local register files (RF)
input [`MBUS_DYNA_WIDTH-1:0] ASSIGNED_ADDR_IN,
output [`MBUS_DYNA_WIDTH-1:0] ASSIGNED_ADDR_OUT,
input ASSIGNED_ADDR_VALID,
output reg ASSIGNED_ADDR_WRITE,
output reg ASSIGNED_ADDR_INVALIDn
);
`include "include/lname_mbus_func.v"
parameter ADDRESS = 20'habcde;
parameter ADDRESS_MASK = {(`MBUS_PRFIX_WIDTH){1'b1}};
parameter ADDRESS_MASK_SHORT = {`MBUS_DYNA_WIDTH{1'b1}};
// Node mode
parameter MODE_TX_NON_PRIO = 2'd0;
parameter MODE_TX = 2'd1;
parameter MODE_RX = 2'd2;
parameter MODE_FWD = 2'd3;
// BUS state
parameter BUS_IDLE = 0;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ADDR = 3;
parameter BUS_DATA_RX_ADDI = 4;
parameter BUS_DATA = 5;
parameter BUS_DATA_RX_CHECK = 6;
parameter BUS_REQ_INTERRUPT = 7;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
// Address enumeration response type
parameter ADDR_ENUM_RESPOND_T1 = 2'b00;
parameter ADDR_ENUM_RESPOND_T2 = 2'b10;
parameter ADDR_ENUM_RESPOND_NONE = 2'b11;
// TX broadcast data length
parameter LENGTH_1BYTE = 2'b00;
parameter LENGTH_2BYTE = 2'b01;
parameter LENGTH_3BYTE = 2'b10;
parameter LENGTH_4BYTE = 2'b11;
parameter RX_ABOVE_TX = 1'b1;
parameter RX_BELOW_TX = 1'b0;
// override this parameter to "1'b1" if the node is master
parameter MASTER_NODE = 1'b0;
wire [1:0] CONTROL_BITS = `MBUS_CONTROL_SEQ; // EOM?, ~ACK?
// general registers
reg [1:0] mode, next_mode, mode_neg, mode_temp;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(`MBUS_DATA_WIDTH-1)-1:0] bit_position, next_bit_position;
reg req_interrupt, next_req_interrupt;
// Pat Fix
reg req_interrupt_because_error, next_req_interrupt_because_error;
reg out_reg_pos, next_out_reg_pos, out_reg_neg;
// tx registers
reg [`MBUS_ADDR_WIDTH-1:0] ADDR, next_addr;
reg [`MBUS_DATA_WIDTH-1:0] DATA, next_data;
reg tx_pend, next_tx_pend;
reg tx_underflow, next_tx_underflow;
reg ctrl_bit_buf, next_ctrl_bit_buf;
// rx registers
reg [`MBUS_ADDR_WIDTH-1:0] next_rx_addr;
reg [`MBUS_DATA_WIDTH-1:0] next_rx_data;
reg [`MBUS_DATA_WIDTH+1:0] rx_data_buf, next_rx_data_buf;
reg next_rx_fail;
// address enumation registers
reg [1:0] enum_addr_resp, next_enum_addr_resp;
reg next_assigned_addr_write;
reg next_assigned_addr_invalidn;
// interrupt register
reg BUS_INT_RSTn;
wire BUS_INT;
// interface registers
reg next_tx_ack;
reg next_tx_fail;
reg next_tx_success;
reg next_rx_req;
reg next_rx_pend;
wire addr_bit_extract = ((ADDR & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
wire data_bit_extract = ((DATA & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
reg [1:0] addr_match_temp;
wire address_match = (addr_match_temp[1] | addr_match_temp[0]);
// Broadcast processing
reg [`MBUS_BROADCAST_CMD_WIDTH -1:0] rx_broadcast_command;
wire rx_long_addr_en = (RX_ADDR[`MBUS_ADDR_WIDTH-1:`MBUS_ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en = (TX_ADDR[`MBUS_ADDR_WIDTH-1:`MBUS_ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en_latched = (ADDR[`MBUS_ADDR_WIDTH-1:`MBUS_ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
reg tx_broadcast_latched;
reg [1:0] tx_dat_length, rx_dat_length;
reg rx_position, rx_dat_length_valid;
reg wakeup_req;
wire [`MBUS_DATA_WIDTH-1:0] broadcast_addr = `MBUS_BROADCAST_ADDR;
wire [`MBUS_DATA_WIDTH-1:0] rx_data_buf_proc = (rx_dat_length_valid)? (rx_position==RX_BELOW_TX)? rx_data_buf[`MBUS_DATA_WIDTH-1:0] : rx_data_buf[`MBUS_DATA_WIDTH+1:2] : {`MBUS_DATA_WIDTH{1'b0}};
// Power gating related signals
`ifdef MBUS_NODE_POWER_GATING
wire RESETn_local = (RESETn & (~MBC_RESET));
`else
wire RESETn_local = RESETn;
`endif
`ifdef MBUS_NODE_POWER_GATING
reg [1:0] powerup_seq_fsm;
reg shutdown, next_shutdown;
reg ext_int;
`endif
wire [15:0] layer_slot = (1'b1<<ASSIGNED_ADDR_IN);
// Assignments
assign RX_BROADCAST = addr_match_temp[0];
assign ASSIGNED_ADDR_OUT = DATA[`MBUS_DYNA_WIDTH-1:0];
assign MBC_IN_FWD = (mode == MODE_FWD);
// MBUS_BUSY generation
always @ (posedge CIN or negedge RESETn_local)
begin
if (~RESETn_local) MBUS_BUSY <= `SD 1'b0;
else if (bus_state == BUS_BACK_TO_IDLE) MBUS_BUSY <= `SD 1'b0;
else MBUS_BUSY <= `SD 1'b1;
end
// Node priority
// Used only when the BUS_STATE == BUS_PRIO, determine the node should be RX or TX
always @ *
begin
mode_temp = MODE_RX;
if (mode==MODE_TX_NON_PRIO)
begin
// Other node request priority,
if (DIN & (~TX_PRIORITY))
mode_temp = MODE_RX;
else
mode_temp = MODE_TX;
end
else
begin
// the node won first trial doesn't request priority
if (TX_REQ & TX_PRIORITY & (~DIN))
mode_temp = MODE_TX;
else
mode_temp = MODE_RX;
end
end
// End of node priority
// TX Broadcast
// For some boradcast message, TX node should take apporiate action, ex: all node sleep
// determined by ADDR flops, not TX_ADDR
always @ *
begin
tx_broadcast_latched = 0;
if (tx_long_addr_en_latched)
begin
if (ADDR[`MBUS_DATA_WIDTH-1:`MBUS_FUNC_WIDTH]==broadcast_addr[`MBUS_DATA_WIDTH-1:`MBUS_FUNC_WIDTH])
tx_broadcast_latched = 1;
end
else
begin
if (ADDR[`MBUS_SHORT_ADDR_WIDTH-1:`MBUS_FUNC_WIDTH]==broadcast_addr[`MBUS_SHORT_ADDR_WIDTH-1:`MBUS_FUNC_WIDTH])
tx_broadcast_latched = 1;
end
end
// End of TX broadcast
// Wake up control
// What type of message should wake up the layer controller (LC)
always @ *
begin
wakeup_req = 0;
// normal messages
if (~RX_BROADCAST)
wakeup_req = address_match;
else
begin
// master node should wake up for every broadcast message
if (MASTER_NODE==1'b1)
wakeup_req = address_match;
// which channels should wake up
case (RX_ADDR[`MBUS_FUNC_WIDTH-1:0])
`MBUS_CHANNEL_POWER:
begin
case (rx_data_buf[`MBUS_BROADCAST_CMD_WIDTH-1:0])
`MBUS_CMD_CHANNEL_POWER_ALL_WAKE: begin wakeup_req = 1; end
endcase
end
default: begin end
endcase
end
end
// End of Wake up control
// Address compare
// This block determine the incoming message has match the address or not
always @ *
begin
addr_match_temp = 2'b00;
if (rx_long_addr_en)
begin
if (RX_ADDR[`MBUS_DATA_WIDTH-1:`MBUS_FUNC_WIDTH]==broadcast_addr[`MBUS_DATA_WIDTH-1:`MBUS_FUNC_WIDTH])
addr_match_temp[0] = 1;
if (((RX_ADDR[`MBUS_DATA_WIDTH-`MBUS_RSVD_WIDTH-1:`MBUS_FUNC_WIDTH] ^ ADDRESS) & ADDRESS_MASK)==0)
addr_match_temp[1] = 1;
end
// short address assigned
else
begin
if (RX_ADDR[`MBUS_SHORT_ADDR_WIDTH-1:`MBUS_FUNC_WIDTH]==broadcast_addr[`MBUS_SHORT_ADDR_WIDTH-1:`MBUS_FUNC_WIDTH])
addr_match_temp[0] = 1;
if (ASSIGNED_ADDR_VALID)
begin
if (((RX_ADDR[`MBUS_SHORT_ADDR_WIDTH-1:`MBUS_FUNC_WIDTH] ^ ASSIGNED_ADDR_IN) & ADDRESS_MASK_SHORT)==0)
addr_match_temp[1] = 1;
end
end
end
// End of address compare
// TX broadcast command length
// This only take care the broadcast command issued from layer controller
// CANNOT use this in self generate enumerate response
always @ *
begin
tx_dat_length = LENGTH_4BYTE;
if (tx_broadcast_latched)
begin
case (ADDR[`MBUS_FUNC_WIDTH-1:0])
`MBUS_CHANNEL_ENUM:
begin
case (DATA[`MBUS_DATA_WIDTH-1:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH])
`MBUS_CMD_CHANNEL_ENUM_QUERRY: begin tx_dat_length = LENGTH_1BYTE; end
`MBUS_CMD_CHANNEL_ENUM_RESPONSE: begin tx_dat_length = LENGTH_4BYTE; end
`MBUS_CMD_CHANNEL_ENUM_ENUMERATE: begin tx_dat_length = LENGTH_1BYTE; end
`MBUS_CMD_CHANNEL_ENUM_INVALIDATE: begin tx_dat_length = LENGTH_1BYTE; end
endcase
end
`MBUS_CHANNEL_POWER:
begin
case (DATA[`MBUS_DATA_WIDTH-1:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH])
`MBUS_CMD_CHANNEL_POWER_ALL_SLEEP: begin tx_dat_length = LENGTH_1BYTE; end
`MBUS_CMD_CHANNEL_POWER_ALL_WAKE: begin tx_dat_length = LENGTH_1BYTE; end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP: begin tx_dat_length = LENGTH_3BYTE; end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP_FULL: begin tx_dat_length = LENGTH_4BYTE; end
`MBUS_CMD_CHANNEL_POWER_SEL_WAKE: begin tx_dat_length = LENGTH_3BYTE; end
endcase
end
endcase
end
end
// This block used to determine the received data length.
// only broadcast can be any byte aligned
// otherwise, regular message has to be word aligned
always @ *
begin
rx_dat_length = LENGTH_4BYTE;
rx_dat_length_valid = 0;
rx_position = RX_ABOVE_TX;
case (bit_position)
1: begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
(`MBUS_DATA_WIDTH-1'b1): begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
9: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
7: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
17: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
15: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
25: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
23: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
endcase
end
always @ *
begin
rx_broadcast_command = rx_data_buf_proc[`MBUS_DATA_WIDTH-1:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH];
case (rx_dat_length)
LENGTH_4BYTE: begin rx_broadcast_command = rx_data_buf_proc[`MBUS_DATA_WIDTH-1:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH]; end
LENGTH_3BYTE: begin rx_broadcast_command = rx_data_buf_proc[`MBUS_DATA_WIDTH-9:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH-8]; end
LENGTH_2BYTE: begin rx_broadcast_command = rx_data_buf_proc[`MBUS_DATA_WIDTH-17:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH-16]; end
LENGTH_1BYTE: begin rx_broadcast_command = rx_data_buf_proc[`MBUS_DATA_WIDTH-25:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH-24]; end
endcase
end
always @ (posedge CIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
`ifdef MBUS_NODE_POWER_GATING
if (MASTER_NODE==1'b1)
bus_state <= `SD BUS_IDLE;
else
bus_state <= `SD BUS_PRIO;
`else
bus_state <= `SD BUS_IDLE;
`endif
BUS_INT_RSTn <= `SD 1;
end
else
begin
if (BUS_INT)
begin
bus_state <= `SD BUS_CONTROL0;
BUS_INT_RSTn <= `SD 0;
end
else
begin
bus_state <= `SD next_bus_state;
BUS_INT_RSTn <= `SD 1;
end
end
end
wire TX_RESP_RSTn = RESETn_local & (~TX_RESP_ACK);
always @ (posedge CIN or negedge TX_RESP_RSTn)
begin
if (~TX_RESP_RSTn)
begin
TX_FAIL <= `SD 0;
TX_SUCC <= `SD 0;
end
else
begin
TX_FAIL <= `SD next_tx_fail;
TX_SUCC <= `SD next_tx_success;
end
end
wire RX_ACK_RSTn = RESETn_local & (~RX_ACK);
always @ (posedge CIN or negedge RX_ACK_RSTn)
begin
if (~RX_ACK_RSTn)
begin
RX_REQ <= `SD 0;
RX_PEND <= `SD 0;
RX_FAIL <= `SD 0;
end
else if (~BUS_INT)
begin
RX_REQ <= `SD next_rx_req;
RX_PEND <= `SD next_rx_pend;
RX_FAIL <= `SD next_rx_fail;
end
end
always @ (posedge CIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
// general registers
mode <= `SD MODE_RX;
bit_position <= `SD `MBUS_ADDR_WIDTH - 1'b1;
req_interrupt <= `SD 0;
// Pat Fix
req_interrupt_because_error <= `SD 0;
out_reg_pos <= `SD 0;
// Transmitter registers
ADDR <= `SD 0;
DATA <= `SD 0;
tx_pend <= `SD 0;
tx_underflow <= `SD 0;
ctrl_bit_buf <= `SD 0;
// Receiver register
RX_ADDR <= `SD 0;
RX_DATA <= `SD 0;
rx_data_buf <= `SD 0;
// Interface registers
TX_ACK <= `SD 0;
`ifdef MBUS_NODE_POWER_GATING
// power gated related signal
shutdown <= `SD 0;
`endif
// address enumeration
enum_addr_resp <= `SD ADDR_ENUM_RESPOND_NONE;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= `SD 0;
ASSIGNED_ADDR_INVALIDn <= `SD 1;
end
else
begin
// general registers
mode <= `SD next_mode;
if (~BUS_INT)
begin
bit_position <= `SD next_bit_position;
rx_data_buf <= `SD next_rx_data_buf;
// Receiver register
RX_ADDR <= `SD next_rx_addr;
RX_DATA <= `SD next_rx_data;
end
req_interrupt <= `SD next_req_interrupt;
// Pat Fix
req_interrupt_because_error <= `SD next_req_interrupt_because_error;
out_reg_pos <= `SD next_out_reg_pos;
// Transmitter registers
ADDR <= `SD next_addr;
DATA <= `SD next_data;
tx_pend <= `SD next_tx_pend;
tx_underflow <= `SD next_tx_underflow;
ctrl_bit_buf <= `SD next_ctrl_bit_buf;
// Interface registers
TX_ACK <= `SD next_tx_ack;
`ifdef MBUS_NODE_POWER_GATING
// power gated related signal
shutdown <= `SD next_shutdown;
`endif
// address enumeration
enum_addr_resp <= `SD next_enum_addr_resp;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= `SD next_assigned_addr_write;
ASSIGNED_ADDR_INVALIDn <= `SD next_assigned_addr_invalidn;
end
end
always @ *
begin
// general registers
next_mode = mode;
next_bus_state = bus_state;
next_bit_position = bit_position;
next_req_interrupt = req_interrupt;
// Pat Fix
next_req_interrupt_because_error = req_interrupt_because_error;
next_out_reg_pos = out_reg_pos;
// Transmitter registers
next_addr = ADDR;
next_data = DATA;
next_tx_pend = tx_pend;
next_tx_underflow = tx_underflow;
next_ctrl_bit_buf = ctrl_bit_buf;
// Receiver register
next_rx_addr = RX_ADDR;
next_rx_data = RX_DATA;
next_rx_fail = RX_FAIL;
next_rx_data_buf = rx_data_buf;
// Interface registers
next_rx_req = RX_REQ;
next_rx_pend = RX_PEND;
next_tx_fail = TX_FAIL;
next_tx_success = TX_SUCC;
next_tx_ack = TX_ACK;
// Address enumeration
next_enum_addr_resp = enum_addr_resp;
// Address enumeratio interface
next_assigned_addr_write = 0;
next_assigned_addr_invalidn = 1;
// Asynchronous interface
if (TX_ACK & (~TX_REQ))
next_tx_ack = 0;
`ifdef MBUS_NODE_POWER_GATING
// power gating signals
next_shutdown = shutdown;
`endif
case (bus_state)
BUS_IDLE:
begin
if (DIN^DOUT)
next_mode = MODE_TX_NON_PRIO;
else
next_mode = MODE_RX;
// general registers
next_bus_state = BUS_ARBITRATE;
next_bit_position = `MBUS_ADDR_WIDTH - 1'b1;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
end
BUS_PRIO:
begin
next_mode = mode_temp;
next_bus_state = BUS_ADDR;
// no matter this node wins the arbitration or not, must clear
// type T1
if (enum_addr_resp== ADDR_ENUM_RESPOND_T1)
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
if (mode_temp==MODE_TX)
begin
case (enum_addr_resp)
// respond to enumeration
ADDR_ENUM_RESPOND_T1:
begin
next_bit_position = `MBUS_SHORT_ADDR_WIDTH - 1'b1;
next_assigned_addr_write = 1;
end
// respond to query
ADDR_ENUM_RESPOND_T2:
begin
next_bit_position = `MBUS_SHORT_ADDR_WIDTH - 1'b1;
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
end
// TX initiated from layer controller
default:
begin
next_addr = TX_ADDR;
next_data = TX_DATA;
next_tx_ack = 1;
next_tx_pend = TX_PEND;
if (tx_long_addr_en)
next_bit_position = `MBUS_ADDR_WIDTH - 1'b1;
else
next_bit_position = `MBUS_SHORT_ADDR_WIDTH - 1'b1;
end
endcase
end
else
// RX mode
begin
next_rx_data_buf = 0;
next_rx_addr = 0;
end
end
BUS_ADDR:
begin
case (mode)
MODE_TX:
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `MBUS_DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA;
end
end
MODE_RX:
begin
// short address
if ((bit_position==`MBUS_ADDR_WIDTH-3'd5)&&(RX_ADDR[3:0]!=4'hf))
next_bit_position = `MBUS_SHORT_ADDR_WIDTH - 3'd6;
else
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `MBUS_DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA_RX_ADDI;
end
end
next_rx_addr = {RX_ADDR[`MBUS_ADDR_WIDTH-2:0], DIN};
end
endcase
end
BUS_DATA_RX_ADDI:
begin
next_rx_data_buf = {rx_data_buf[`MBUS_DATA_WIDTH:0], DIN};
next_bit_position = bit_position - 1'b1;
`ifdef MBUS_NODE_POWER_GATING
next_shutdown = 0;
`endif
if (bit_position==(`MBUS_DATA_WIDTH-2'b10))
begin
next_bus_state = BUS_DATA;
next_bit_position = `MBUS_DATA_WIDTH - 1'b1;
end
if (address_match==0)
next_mode = MODE_FWD;
end
BUS_DATA:
begin
case (mode)
MODE_TX:
begin
// support variable tx length for broadcast messages
if (((tx_dat_length==LENGTH_4BYTE)&&(bit_position>0))||((tx_dat_length==LENGTH_3BYTE)&&(bit_position>8))||((tx_dat_length==LENGTH_2BYTE)&&(bit_position>16))||((tx_dat_length==LENGTH_1BYTE)&&(bit_position>24)))
//if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `MBUS_DATA_WIDTH - 1'b1;
case ({tx_pend, TX_REQ})
// continue next word
2'b11:
begin
next_tx_pend = TX_PEND;
next_data = TX_DATA;
next_tx_ack = 1;
end
// underflow
2'b10:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_tx_underflow = 1;
next_req_interrupt = 1;
// Pat Fix
next_req_interrupt_because_error = 1;
next_tx_fail = 1;
end
default:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
end
endcase
end
end
MODE_RX:
begin
next_rx_data_buf = {rx_data_buf[`MBUS_DATA_WIDTH:0], DIN};
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
if (RX_REQ)
begin
// RX overflow
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
// Pat Fix
next_req_interrupt_because_error = 1;
next_rx_fail = 1;
end
else
begin
next_bus_state = BUS_DATA_RX_CHECK;
next_bit_position = `MBUS_DATA_WIDTH - 1'b1;
end
end
end
endcase
end
BUS_DATA_RX_CHECK:
begin
next_bit_position = bit_position - 1'b1;
next_rx_data_buf = {rx_data_buf[`MBUS_DATA_WIDTH:0], DIN};
if (RX_BROADCAST)
begin
if (MASTER_NODE==1'b1)
next_rx_req = 1;
else
next_rx_req = 0;
end
else
next_rx_req = 1;
next_rx_pend = 1;
next_rx_data = rx_data_buf[`MBUS_DATA_WIDTH+1:2];
next_bus_state = BUS_DATA;
end
BUS_REQ_INTERRUPT:
begin
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
next_ctrl_bit_buf = DIN;
case (mode)
MODE_TX:
begin
if (req_interrupt)
begin
// Prevent wire floating
next_out_reg_pos = ~CONTROL_BITS[0];
if (tx_broadcast_latched)
begin
case (ADDR[`MBUS_FUNC_WIDTH-1:0])
`MBUS_CHANNEL_POWER:
begin
`ifdef MBUS_NODE_POWER_GATING
case (DATA[`MBUS_DATA_WIDTH-1:`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH ])
`MBUS_CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((DATA[27:12]&layer_slot)>0)
next_shutdown = 1;
end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((DATA[`MBUS_PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
`endif
end
endcase
end
end
else
begin
next_tx_fail = 1;
end
end
MODE_RX:
begin
if (req_interrupt)
next_out_reg_pos = ~CONTROL_BITS[0];
else
begin
// End of Message
// correct ending state
// rx above tx = 31
// rx below tx = 1
if ((DIN==CONTROL_BITS[1])&&(rx_dat_length_valid))
begin
// rx overflow
if (RX_REQ)
begin
next_out_reg_pos = ~CONTROL_BITS[0];
next_rx_fail = 1;
end
else
// assert rx_req if not a broadcast
begin
next_rx_data = rx_data_buf_proc;
next_out_reg_pos = CONTROL_BITS[0];
if (~RX_BROADCAST)
next_rx_req = 1;
next_rx_pend = 0;
end
// broadcast message
if (RX_BROADCAST)
begin
// assert broadcast rx_req only in CPU layer
if ((MASTER_NODE==1'b1)&&(~RX_REQ)) // CPU_LAYER -> MASTER_NODE
next_rx_req = 1;
// broadcast channel
case (RX_ADDR[`MBUS_FUNC_WIDTH-1:0])
`MBUS_CHANNEL_ENUM:
begin
case (rx_broadcast_command)
// any node should report its full prefix and short prefix (dynamic allocated address)
// Pad "0" if the dynamic address is invalid
`MBUS_CMD_CHANNEL_ENUM_QUERRY:
begin
// this node doesn't have a valid short address, active low
next_enum_addr_resp = ADDR_ENUM_RESPOND_T2;
next_addr = broadcast_addr[`MBUS_SHORT_ADDR_WIDTH-1:0];
next_data = ((`MBUS_CMD_CHANNEL_ENUM_RESPONSE<<(`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH)) | (ADDRESS<<`MBUS_DYNA_WIDTH) | ASSIGNED_ADDR_IN);
end
// request arbitration, set short prefix if successed
`MBUS_CMD_CHANNEL_ENUM_ENUMERATE:
begin
if (~ASSIGNED_ADDR_VALID)
begin
next_enum_addr_resp = ADDR_ENUM_RESPOND_T1;
next_addr = broadcast_addr[`MBUS_SHORT_ADDR_WIDTH-1:0];
next_data = ((`MBUS_CMD_CHANNEL_ENUM_RESPONSE<<(`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH)) | (ADDRESS<<`MBUS_DYNA_WIDTH) | rx_data_buf_proc[`MBUS_DYNA_WIDTH-1:0]);
end
end
`MBUS_CMD_CHANNEL_ENUM_INVALIDATE:
begin
case (rx_data_buf_proc[`MBUS_DYNA_WIDTH-1:0])
{`MBUS_DYNA_WIDTH{1'b1}}: begin next_assigned_addr_invalidn = 0; end
ASSIGNED_ADDR_IN: begin next_assigned_addr_invalidn = 0; end
default: begin end
endcase
end
endcase
end
`ifdef MBUS_NODE_POWER_GATING
`MBUS_CHANNEL_POWER:
begin
// PWR Command
case (rx_broadcast_command)
`MBUS_CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((rx_data_buf_proc[19:4]&layer_slot)>0)
next_shutdown = 1;
end
`MBUS_CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((rx_data_buf_proc[`MBUS_PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
end
`endif
// shoud only be active at master
`MBUS_CHANNEL_CTRL:
begin
if (MASTER_NODE==1'b1)
next_rx_req = 1;
end
endcase
end // endif rx_broadcast
end // endif valid reception
else
// invalid data length or invalid EOM
begin
next_out_reg_pos = ~CONTROL_BITS[0];
`ifdef MBUS_NODE_POWER_GATING
if (~ext_int)
next_rx_fail = 1;
`else
next_rx_fail = 1;
`endif
end
end
end
endcase
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
if (req_interrupt)
begin
if ((mode==MODE_TX)&&(~tx_underflow))
begin
// ACK received
if ({ctrl_bit_buf, DIN}==CONTROL_BITS)
next_tx_success = 1;
else
next_tx_fail = 1;
end
end
end
BUS_BACK_TO_IDLE:
begin
next_bus_state = BUS_IDLE;
next_req_interrupt = 0;
// Pat Fix
next_req_interrupt_because_error = 0;
next_mode = MODE_RX;
next_tx_underflow = 0;
end
endcase
end
`ifdef MBUS_NODE_POWER_GATING
always @ (negedge CIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
powerup_seq_fsm <= `SD 0;
LRC_SLEEP <= `SD `MBUS_IO_HOLD;
LRC_CLKENB <= `SD `MBUS_IO_HOLD;
LRC_ISOLATE <= `SD `MBUS_IO_HOLD;
LRC_RESET <= `SD `MBUS_IO_HOLD;
SLEEP_REQUEST_TO_SLEEP_CTRL <= `SD 0;
ext_int <= `SD 0;
CLR_EXT_INT <= `SD 0;
end
else
begin
if (CLR_EXT_INT & (~EXTERNAL_INT))
CLR_EXT_INT <= `SD 0;
// master node should wake up layer controller "early"
if (((bus_state==BUS_ADDR)&&(MASTER_NODE==1'b0))||((bus_state==BUS_IDLE)&&(MASTER_NODE==1'b1)))
begin
if (EXTERNAL_INT)
begin
ext_int <= `SD 1;
powerup_seq_fsm <= `SD 1;
LRC_SLEEP <= `SD `MBUS_IO_RELEASE;
end
else
powerup_seq_fsm <= `SD 0;
end
if (bus_state==BUS_CONTROL1)
ext_int <= `SD 0;
if (ext_int)
begin
case (powerup_seq_fsm)
1: begin LRC_ISOLATE <= `SD `MBUS_IO_RELEASE; CLR_EXT_INT <= `SD 1; powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1; end
2: begin LRC_RESET <= `SD `MBUS_IO_RELEASE; powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1; end
3: begin LRC_CLKENB <= `SD `MBUS_IO_RELEASE; powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1; end
0: begin end
endcase
end
else
begin
case (bus_state)
BUS_DATA:
begin
case (powerup_seq_fsm)
0:
begin
// only check the wakeup_req after received broadcast command
// FSM stays at BUS_ADDR_ADDI for 2 cycles before entering BUS_DATA
// the complete command should received after `MBUS_DATA_WIDTH (32) - `MBUS_BROADCAST_CMD_WIDTH(4) + 2(2 BUS_ADDR_ADDI) - 1
if ((wakeup_req)&&(bit_position==`MBUS_DATA_WIDTH-`MBUS_BROADCAST_CMD_WIDTH+1))
begin
LRC_SLEEP <= `SD `MBUS_IO_RELEASE;
powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1;
end
end
1:
begin
LRC_ISOLATE <= `SD `MBUS_IO_RELEASE;
powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1;
end
2:
begin
LRC_RESET <= `SD `MBUS_IO_RELEASE;
powerup_seq_fsm <= `SD powerup_seq_fsm + 1'b1;
end
3:
begin
LRC_CLKENB <= `SD `MBUS_IO_RELEASE;
end
endcase
end
BUS_CONTROL1:
begin
if (shutdown)
begin
SLEEP_REQUEST_TO_SLEEP_CTRL <= `SD 1;
LRC_ISOLATE <= `SD `MBUS_IO_HOLD;
end
end
BUS_BACK_TO_IDLE:
begin
end
endcase
end
end
end
`endif
always @ (negedge CIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
out_reg_neg <= `SD 1;
`ifdef MBUS_NODE_POWER_GATING
if (MASTER_NODE==1'b1)
bus_state_neg <= `SD BUS_IDLE;
else
bus_state_neg <= `SD BUS_PRIO;
`else
bus_state_neg <= `SD BUS_IDLE;
`endif
mode_neg <= `SD MODE_RX;
end
else
begin
if (req_interrupt & BUS_INT)
bus_state_neg <= `SD BUS_CONTROL0;
else
bus_state_neg <= `SD bus_state;
mode_neg <= `SD mode;
case (bus_state)
BUS_ADDR:
begin
if (mode==MODE_TX)
out_reg_neg <= `SD addr_bit_extract;
end
BUS_DATA:
begin
if (mode==MODE_TX)
out_reg_neg <= `SD data_bit_extract;
end
BUS_CONTROL0:
begin
if (req_interrupt)
begin
if (mode==MODE_TX)
begin
if (tx_underflow)
out_reg_neg <= `SD ~CONTROL_BITS[1];
else
out_reg_neg <= `SD CONTROL_BITS[1];
end
else
out_reg_neg <= `SD ~CONTROL_BITS[1];
end
end
BUS_CONTROL1:
begin
out_reg_neg <= `SD out_reg_pos;
end
endcase
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
BUS_ARBITRATE:
begin
if (mode_neg==MODE_TX_NON_PRIO)
DOUT = 0;
end
BUS_PRIO:
begin
if (mode_neg==MODE_TX_NON_PRIO)
begin
if (TX_PRIORITY)
DOUT = 1;
else
DOUT = 0;
end
else if ((mode_neg==MODE_RX)&&(TX_PRIORITY & TX_REQ))
DOUT = 1;
end
BUS_ADDR:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_DATA:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_CONTROL0:
begin
if (req_interrupt)
DOUT = out_reg_neg;
end
BUS_CONTROL1:
begin
if (mode_neg==MODE_RX)
DOUT = out_reg_neg;
// Pat Fix
//else if (req_interrupt)
else if (req_interrupt_because_error)
DOUT = out_reg_neg;
end
BUS_BACK_TO_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
endcase
end
always @ *
begin
// forward clock once interrupt occurred
COUT = CIN;
if ((bus_state==BUS_REQ_INTERRUPT)&&(~BUS_INT))
COUT = 1;
end
lname_mbus_swapper lname_mbus_swapper_0 (
// inputs
.CLK(CIN),
.RESETn(RESETn_local),
.DATA(DIN),
.INT_FLAG_RESETn(BUS_INT_RSTn),
//Outputs
.LAST_CLK(),
.INT_FLAG(BUS_INT));
endmodule // lname_mbus_node
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_M_V
`define SKY130_FD_SC_LP__AND4_M_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_m (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_m (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_M_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: frac_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module frac_rom (
address,
clock,
q);
input [3:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "qrom.rif"
`else
altsyncram_component.init_file = "qrom.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 4,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qrom.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "4"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "qrom.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
input [4:0] sa1_bmaps_sbm,
input sa1_dma_cc1_en,
input [11:0] sa1_xxb,
input [3:0] sa1_xxb_en,
// output srtc_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output sa1_enable
);
parameter [2:0]
//FEAT_DSPX = 0,
//FEAT_ST0010 = 1,
//FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
// Static Inputs
reg [23:0] ROM_MASK_r = 0;
reg [23:0] SAVERAM_MASK_r = 0;
reg iram_battery_r = 0;
always @(posedge CLK) begin
ROM_MASK_r <= ROM_MASK;
SAVERAM_MASK_r <= SAVERAM_MASK;
iram_battery_r <= ~SAVERAM_MASK_r[1] & SAVERAM_MASK_r[0];
end
wire [23:0] SRAM_SNES_ADDR;
wire [2:0] xxb[3:0];
assign {xxb[3], xxb[2], xxb[1], xxb[0]} = sa1_xxb;
wire [3:0] xxb_en = sa1_xxb_en;
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = SAVERAM_MASK_r[0]
& ( // 40-4F:0000-FFFF
( ~SNES_ADDR[23]
& SNES_ADDR[22]
& ~SNES_ADDR[21]
& ~SNES_ADDR[20]
& ~sa1_dma_cc1_en
)
// 00-3F/80-BF:6000-7FFF
| ( ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& &SNES_ADDR[14:13]
)
| ( iram_battery_r
& ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& ~SNES_ADDR[14]
& SNES_ADDR[13]
& SNES_ADDR[12]
& ~SNES_ADDR[11]
)
);
assign IS_WRITABLE = IS_SAVERAM;
// TODO: add programmable address map
assign SRAM_SNES_ADDR = (IS_SAVERAM
// 40-4F:0000-FFFF or 00-3F/80-BF:6000-7FFF (first 8K mirror). Mask handles mirroring. 60 is sa1-only
? (24'hE00000 + (iram_battery_r ? SNES_ADDR[10:0] : ((SNES_ADDR[22] ? SNES_ADDR[19:0] : {sa1_bmaps_sbm,SNES_ADDR[12:0]}) & SAVERAM_MASK_r)))
// C0-FF:0000-FFFF or 00-3F/80-BF:8000-FFFF
: ((SNES_ADDR[22] ? {1'b0, xxb[SNES_ADDR[21:20]], SNES_ADDR[19:0]} : {1'b0, (xxb_en[{SNES_ADDR[23],SNES_ADDR[21]}] ? xxb[{SNES_ADDR[23],SNES_ADDR[21]}] : {1'b0,SNES_ADDR[23],SNES_ADDR[21]}), SNES_ADDR[20:16], SNES_ADDR[14:0]}) & ROM_MASK_r)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Float to int converter.
// File : flt2int.v
// Author : Jim MacLeod
// Created : 31-Dec-2012
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt2int
(
input clk,
input [31:0] afl,
output reg [15:0] fx_int
);
reg [14:0] int_out;
always @* begin
if(afl[30:23] == 8'h7f) int_out = 16'h1; // 1
else begin
casex(afl[30:23])
8'b0xxx_xxxx: int_out = 15'h0; // 0
8'b1000_0000: int_out = {14'h1, afl[22]}; // 2 - 3
8'b1000_0001: int_out = {13'h1, afl[22:21]}; // 4 - 7
8'b1000_0010: int_out = {12'h1, afl[22:20]}; // 8 - 15
8'b1000_0011: int_out = {11'h1, afl[22:19]}; // 16 - 31
8'b1000_0100: int_out = {10'h1, afl[22:18]}; // 32 - 63
8'b1000_0101: int_out = {9'h1, afl[22:17]}; // 64 - 127
8'b1000_0110: int_out = {8'h1, afl[22:16]}; // 128 - 255
8'b1000_0111: int_out = {7'h1, afl[22:15]}; // 256 - 511
8'b1000_1000: int_out = {6'h1, afl[22:14]}; // 512 - 1023
8'b1000_1001: int_out = {5'h1, afl[22:13]}; // 1024 - 2047
8'b1000_1010: int_out = {4'h1, afl[22:12]}; // 2048 - 4095
8'b1000_1011: int_out = {3'h1, afl[22:11]}; // 4096 - 8191
8'b1000_1100: int_out = {2'h1, afl[22:10]}; // 8192 - 16383
8'b1000_1101: int_out = {1'h1, afl[22: 9]}; // 16384 - 32767
default: int_out = 15'h7fff; // Overflow
endcase
end
end
always @(posedge clk) begin
if(afl[31]) fx_int <= ~int_out + 16'h1;
else fx_int <= {1'b0, int_out};
end
endmodule
|
`include "minsoc_bench_defines.v"
`include "minsoc_defines.v"
`include "or1200_defines.v"
`include "timescale.v"
module minsoc_bench();
`ifdef POSITIVE_RESET
localparam RESET_LEVEL = 1'b1;
`elsif NEGATIVE_RESET
localparam RESET_LEVEL = 1'b0;
`else
localparam RESET_LEVEL = 1'b1;
`endif
reg clock, reset;
//Debug interface
wire dbg_tms_i;
wire dbg_tck_i;
wire dbg_tdi_i;
wire dbg_tdo_o;
wire jtag_vref;
wire jtag_gnd;
//SPI wires
wire spi_mosi;
reg spi_miso;
wire spi_sclk;
wire [1:0] spi_ss;
//UART wires
wire uart_stx;
reg uart_srx;
//ETH wires
reg eth_col;
reg eth_crs;
wire eth_trst;
reg eth_tx_clk;
wire eth_tx_en;
wire eth_tx_er;
wire [3:0] eth_txd;
reg eth_rx_clk;
reg eth_rx_dv;
reg eth_rx_er;
reg [3:0] eth_rxd;
reg eth_fds_mdint;
wire eth_mdc;
wire eth_mdio;
//
// TASKS registers to communicate with interfaces
//
reg design_ready;
reg uart_echo;
`ifdef UART
reg [40*8-1:0] line;
reg [12*8-1:0] hello;
reg new_line;
reg new_char;
reg flush_line;
`endif
`ifdef ETHERNET
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536)
localparam ETH_HDR = 14;
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
`endif
//
// Testbench mechanics
//
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
integer initialize, ptr;
reg [8*64:0] file_name;
integer firmware_size; // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters.
integer firmware_size_in_header;
reg load_file;
initial begin
reset = ~RESET_LEVEL;
clock = 1'b0;
eth_tx_clk = 1'b0;
eth_rx_clk = 1'b0;
design_ready = 1'b0;
uart_echo = 1'b1;
`ifndef NO_CLOCK_DIVISION
minsoc_top_0.clk_adjust.clk_int = 1'b0;
minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
`endif
uart_srx = 1'b1;
eth_col = 1'b0;
eth_crs = 1'b0;
eth_fds_mdint = 1'b1;
eth_rx_er = 1'b0;
eth_rxd = 4'h0;
eth_rx_dv = 1'b0;
//dual and two port rams from FPGA memory instances have to be initialized to 0
init_fpga_memory();
load_file = 1'b0;
`ifdef INITIALIZE_MEMORY_MODEL
load_file = 1'b1;
`endif
`ifdef START_UP
load_file = 1'b1;
`endif
//get firmware hex file from command line input
if ( load_file ) begin
if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
$display("ERROR: Please specify the name of the firmware file to load on start-up.");
$finish;
end
// We are passing the firmware size separately as a command-line argument in order
// to avoid this kind of Icarus Verilog warnings:
// WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005.
// WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767].
// Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is,
// Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone
// it's not easy to read the firmware file header without getting such warnings.
if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin
$display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file.");
$finish;
end
$readmemh(file_name, program_mem, 0, firmware_size - 1);
firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
if ( firmware_size != firmware_size_in_header ) begin
$display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?");
$finish;
end
end
`ifdef INITIALIZE_MEMORY_MODEL
// Initialize memory with firmware
initialize = 0;
while ( initialize < firmware_size ) begin
minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
initialize = initialize + 4;
end
$display("Memory model initialized with firmware:");
$display("%s", file_name);
$display("%d Bytes loaded from %d ...", initialize , firmware_size);
`endif
// Reset controller
repeat (2) @ (negedge clock);
reset = RESET_LEVEL;
repeat (16) @ (negedge clock);
reset = ~RESET_LEVEL;
`ifdef START_UP
// Pass firmware over spi to or1k_startup
ptr = 0;
//read dummy
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
//~read dummy
while ( ptr < firmware_size ) begin
send_spi(program_mem[ptr]);
ptr = ptr + 1;
end
$display("Memory start-up completed...");
$display("Loaded firmware:");
$display("%s", file_name);
`endif
//
// Testbench START
//
design_ready = 1'b1;
$display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards.");
fork
begin
`ifdef UART
`ifdef ETHERNET
`ifdef TEST_ETHERNET
$display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)...");
$display("Ethernet firmware encloses UART firmware, testing UART firmware first...");
test_uart();
test_eth();
$display("Stopping simulation.");
$finish;
`endif
`endif
`ifdef TEST_UART
$display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)...");
test_uart();
$display("Stopping simulation.");
$finish;
`endif
`endif
end
begin
`ifdef ETHERNET
`ifdef TEST_ETHERNET
get_mac();
if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
$display("Ethernet firmware started correctly.");
`endif
`endif
end
join
end
//
// Modules instantiations
//
minsoc_top minsoc_top_0(
.clk(clock),
.reset(reset)
//JTAG ports
`ifdef GENERIC_TAP
, .jtag_tdi(dbg_tdi_i),
.jtag_tms(dbg_tms_i),
.jtag_tck(dbg_tck_i),
.jtag_tdo(dbg_tdo_o),
.jtag_vref(jtag_vref),
.jtag_gnd(jtag_gnd)
`endif
//SPI ports
`ifdef START_UP
, .spi_flash_mosi(spi_mosi),
.spi_flash_miso(spi_miso),
.spi_flash_sclk(spi_sclk),
.spi_flash_ss(spi_ss)
`endif
//UART ports
`ifdef UART
, .uart_stx(uart_stx),
.uart_srx(uart_srx)
`endif // !UART
// Ethernet ports
`ifdef ETHERNET
, .eth_col(eth_col),
.eth_crs(eth_crs),
.eth_trste(eth_trst),
.eth_tx_clk(eth_tx_clk),
.eth_tx_en(eth_tx_en),
.eth_tx_er(eth_tx_er),
.eth_txd(eth_txd),
.eth_rx_clk(eth_rx_clk),
.eth_rx_dv(eth_rx_dv),
.eth_rx_er(eth_rx_er),
.eth_rxd(eth_rxd),
.eth_fds_mdint(eth_fds_mdint),
.eth_mdc(eth_mdc),
.eth_mdio(eth_mdio)
`endif // !ETHERNET
);
`ifdef VPI_DEBUG
dbg_comm_vpi dbg_if(
.SYS_CLK(clock),
.P_TMS(dbg_tms_i),
.P_TCK(dbg_tck_i),
.P_TRST(),
.P_TDI(dbg_tdi_i),
.P_TDO(dbg_tdo_o)
);
`else
assign dbg_tdi_i = 1;
assign dbg_tck_i = 0;
assign dbg_tms_i = 1;
`endif
//
// Firmware testers
//
`ifdef UART
task test_uart();
begin
@ (posedge new_line);
$display("UART data received.");
hello = line[12*8-1:0];
//sending character A to UART, B expected
$display("Testing UART interrupt...");
uart_echo = 1'b0;
uart_send(8'h41); //Character A
@ (posedge new_char);
if ( line[7:0] == "B" )
$display("UART interrupt working.");
else
$display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
uart_echo = 1'b1;
if ( hello == "Hello World." )
$display("UART firmware test completed, behaving correctly.");
else
$display("UART firmware test completed, failed.");
end
endtask
`endif
`ifdef ETHERNET
task test_eth();
begin
eth_tx_data[ETH_HDR+0] = 8'hBA;
eth_tx_data[ETH_HDR+1] = 8'h87;
eth_tx_data[ETH_HDR+2] = 8'hAA;
eth_tx_data[ETH_HDR+3] = 8'hBB;
eth_tx_data[ETH_HDR+4] = 8'hCC;
eth_tx_data[ETH_HDR+5] = 8'hDD;
$display("Sending an Ethernet package to the system and waiting for the data to be output through UART...");
send_mac(6);
repeat(3+40) @ (posedge new_line);
$display("Ethernet test completed.");
end
endtask
`endif
//
// Regular clocking and output
//
always begin
#((`CLK_PERIOD)/2) clock <= ~clock;
end
`ifdef WAVEFORM_OUTPUT
initial begin
$dumpfile("../results/minsoc_wave.lxt2");
$dumpvars();
end
`endif
//
// Functionalities tasks: SPI Startup and UART Monitor
//
//SPI START_UP
`ifdef START_UP
task send_spi;
input [7:0] data_in;
integer i;
begin
i = 7;
for ( i = 7 ; i >= 0; i = i - 1 ) begin
spi_miso = data_in[i];
@ (posedge spi_sclk);
end
end
endtask
`endif
//~SPI START_UP
//UART
`ifdef UART
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
task uart_send;
input [7:0] data;
integer i;
begin
uart_srx = 1'b0;
#UART_TX_WAIT;
for ( i = 0; i < 8 ; i = i + 1 ) begin
uart_srx = data[i];
#UART_TX_WAIT;
end
uart_srx = 1'b0;
#UART_TX_WAIT;
uart_srx = 1'b1;
end
endtask
//UART Monitor (prints uart output on the terminal)
// Something to trigger the task
initial
begin
new_line = 1'b0;
new_char = 1'b0;
flush_line = 1'b0;
end
always @ (posedge clock)
if ( design_ready )
uart_decoder;
task uart_decoder;
integer i;
reg [7:0] tx_byte;
begin
new_char = 1'b0;
new_line = 1'b0;
// Wait for start bit
while (uart_stx == 1'b1)
@(uart_stx);
#(UART_TX_WAIT + (UART_TX_WAIT/2));
for ( i = 0; i < 8 ; i = i + 1 ) begin
tx_byte[i] = uart_stx;
#UART_TX_WAIT;
end
//Check for stop bit
if (uart_stx == 1'b0) begin
//$display("* WARNING: user stop bit not received when expected at time %d__", $time);
// Wait for return to idle
while (uart_stx == 1'b0)
@(uart_stx);
//$display("* USER UART returned to idle at time %d",$time);
end
// display the char
if ( uart_echo )
$write("%c", tx_byte);
if ( flush_line ) begin
line = "";
flush_line = 1'b0;
end
if ( tx_byte == "\n" ) begin
new_line = 1'b1;
flush_line = 1'b1;
end
else begin
line = { line[39*8-1:0], tx_byte};
new_char = 1'b1;
end
end
endtask
//~UART Monitor
`endif // !UART
//~UART
//
// TASKS to communicate with interfaces
//
//MAC_DATA
//
`ifdef ETHERNET
reg [31:0] crc32_result;
task get_mac;
integer conta;
reg LSB;
begin
conta = 0;
LSB = 1;
@ ( posedge eth_tx_en);
repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte)
while ( eth_tx_en == 1'b1 ) begin
@ (negedge eth_tx_clk) begin
if ( LSB == 1'b1 )
eth_rx_data[conta][3:0] = eth_txd;
else begin
eth_rx_data[conta][7:4] = eth_txd;
conta = conta + 1;
end
LSB = ~LSB;
end
end
end
endtask
task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518
integer conta;
begin
if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
//DEST MAC
eth_tx_data[0] = 8'h55;
eth_tx_data[1] = 8'h47;
eth_tx_data[2] = 8'h34;
eth_tx_data[3] = 8'h22;
eth_tx_data[4] = 8'h88;
eth_tx_data[5] = 8'h92;
//SOURCE MAC
eth_tx_data[6] = 8'h3D;
eth_tx_data[7] = 8'h4F;
eth_tx_data[8] = 8'h1A;
eth_tx_data[9] = 8'hBE;
eth_tx_data[10] = 8'h68;
eth_tx_data[11] = 8'h72;
//LEN
eth_tx_data[12] = length[7:4];
eth_tx_data[13] = length[3:0];
//DATA input by task caller
//PAD
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
eth_tx_data[conta] = 8'h00;
end
gencrc32(conta);
eth_tx_data[conta] = crc32_result[31:24];
eth_tx_data[conta+1] = crc32_result[23:16];
eth_tx_data[conta+2] = crc32_result[15:8];
eth_tx_data[conta+3] = crc32_result[7:0];
send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
end
else
$display("Warning: Ethernet packet is to big to be sent.");
end
endtask
task send_rx_packet;
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
input [31:0] start_addr; // start address
input [31:0] len; // length of frame in Bytes (without preamble and SFD)
input plus_drible_nibble; // if length is longer for one nibble
integer rx_cnt;
reg [31:0] eth_tx_data_addr_in; // address for reading from RX memory
reg [7:0] eth_tx_data_data_out; // data for reading from RX memory
begin
@(posedge eth_rx_clk);
eth_rx_dv = 1;
// set initial rx memory address
eth_tx_data_addr_in = start_addr;
// send preamble
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
begin
eth_rxd = preamble_data[3:0];
preamble_data = preamble_data >> 4;
@(posedge eth_rx_clk);
end
// send SFD
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
begin
eth_rxd = sfd_data[3:0];
sfd_data = sfd_data >> 4;
@(posedge eth_rx_clk);
end
// send packet's addresses, type/length, data and FCS
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
begin
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
eth_rxd = eth_tx_data_data_out[3:0];
@(posedge eth_rx_clk);
eth_rxd = eth_tx_data_data_out[7:4];
eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
@(posedge eth_rx_clk);
end
if (plus_drible_nibble)
begin
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
eth_rxd = eth_tx_data_data_out[3:0];
@(posedge eth_rx_clk);
end
eth_rx_dv = 0;
@(posedge eth_rx_clk);
end
endtask // send_rx_packet
//CRC32
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
task gencrc32;
input [31:0] crc32_length;
integer byte, bit;
reg msb;
reg [7:0] current_byte;
reg [31:0] temp;
begin
crc32_result = 32'hffffffff;
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
current_byte = eth_tx_data[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_byte[bit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 32; bit = bit + 1)
temp[31-bit] = crc32_result[bit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
//~CRC32
`endif // !ETHERNET
//~MAC_DATA
//Generate tx and rx clocks
always begin
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
end
always begin
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
end
//~Generate tx and rx clocks
//
// TASK to initialize instantiated FPGA dual and two port memory to 0
//
task init_fpga_memory;
integer i;
begin
`ifdef OR1200_RFRAM_TWOPORT
`ifdef OR1200_XILINX_RAMB4
for ( i = 0; i < (1<<8); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
end
`elsif OR1200_XILINX_RAMB16
for ( i = 0; i < (1<<9); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
end
`elsif OR1200_ALTERA_LPM
`ifndef OR1200_ALTERA_LPM_XXX
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
`endif
`ifdef OR1200_ALTERA_LPM_XXX
$display("...Using ALTERA memory for TWOPORT RFRAM!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
end
`else
$display("...Using GENERIC memory!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_XILINX_RAM32X1D
$display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`else
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_RFRAM_DUALPORT
`ifdef OR1200_XILINX_RAMB4
for ( i = 0; i < (1<<8); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
end
`elsif OR1200_XILINX_RAMB16
for ( i = 0; i < (1<<9); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
end
`elsif OR1200_ALTERA_LPM
`ifndef OR1200_ALTERA_LPM_XXX
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
`endif
`ifdef OR1200_ALTERA_LPM_XXX
$display("...Using ALTERA memory for DUALPORT RFRAM!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
end
`else
$display("...Using GENERIC memory!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
for ( i = 0; i < (1<<4); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
end
`else
for ( i = 0; i < (1<<4); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
end
`endif
`else
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`endif
end
endtask
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** (Side note on notation: In .v files, the "forall" quantifier is
spelled out in letters. In the generated HTML files, [forall] is
usually typeset as the usual mathematical "upside down A," but
you'll see the spelled-out "forall" in a few places, as in the
above comments. This is just a quirk of typesetting: there is no
difference in meaning. *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit. If some arguments of a definition don't have
a name, as it is often the case for constructors, they can be
marked with a wildcard pattern [_]. *)
Arguments nil {X}.
Arguments cons {X} _ _.
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(** Now, we don't have to supply type arguments for these functions: *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to the
recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. The reason for that is that marking the
parameter of an inductive type as implicit causes it to become
implicit for the type itself, not just its constructors. For
instance, consider the following alternative definition of the
[list] type: *)
Inductive list' {X:Type} : Type :=
| nil' : list'
| cons' : X -> list' -> list'.
(** Because [X] is declared as implicit for the _entire_ inductive
definition, we can't write an expression such as [list' nat],
which is almost never what we want. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
Fail Definition mynil := nil.
(** The [Fail] qualifier that appears before [Definition] can be
used with _any_ command, and is used to ensure that that command
indeed fails when executed. If the command does fail, Coq prints
the corresponding error message, but continues processing the rest
of the file. Here, Coq gives us an error because it doesn't know
what type argument to supply to [nil]. We can help it by
providing an explicit type declaration (so that Coq has more
information available when it gets to the "application" of [nil]):
*)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
(* FILL IN HERE *) admit.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
(* FILL IN HERE *) Admitted.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
(** Note that the pair notation can also be used in patterns... *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx, ly with
| [], _ => []
| _, [] => []
| x :: tx, y :: ty => (x, y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Compute (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
(* FILL IN HERE *) admit.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
(* FILL IN HERE *) admit.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
(* FILL IN HERE *) admit.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
(* FILL IN HERE *) admit.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(* FILL IN HERE *) admit.
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
(* FILL IN HERE *) admit.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
(* FILL IN HERE *) admit.
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
(* FILL IN HERE *) admit.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
Definition exp (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
End Church.
(** [] *)
(** $Date$ *)
|
//altremote_update CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" check_app_pof="false" config_device_addr_width=24 DEVICE_FAMILY="Cyclone IV E" in_data_width=24 is_epcq="false" operation_mode="remote" out_data_width=29 busy clock ctl_nupdt data_out param read_param read_source reconfig reset reset_timer
//VERSION_BEGIN 15.1 cbx_altremote_update 2015:10:21:18:09:23:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_shiftreg 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_nightfury 2015:10:21:18:09:22:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_rublock 1 lpm_counter 2 reg 62
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103"} *)
module altera_remote_update_core
(
busy,
clock,
ctl_nupdt,
data_out,
param,
read_param,
read_source,
reconfig,
reset,
reset_timer) /* synthesis synthesis_clearbox=1 */;
output busy;
input clock;
input ctl_nupdt;
output [28:0] data_out;
input [2:0] param;
input read_param;
input [1:0] read_source;
input reconfig;
input reset;
input reset_timer;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 ctl_nupdt;
tri0 [2:0] param;
tri0 read_param;
tri0 [1:0] read_source;
tri0 reconfig;
tri0 reset_timer;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] check_busy_dffe;
reg [0:0] dffe1a0;
reg [0:0] dffe1a1;
wire [1:0] wire_dffe1a_ena;
reg [0:0] dffe2a0;
reg [0:0] dffe2a1;
reg [0:0] dffe2a2;
wire [2:0] wire_dffe2a_ena;
reg [0:0] dffe3a0;
reg [0:0] dffe3a1;
reg [0:0] dffe3a2;
wire [2:0] wire_dffe3a_ena;
reg [28:0] dffe7a;
wire [28:0] wire_dffe7a_ena;
reg dffe8;
reg [6:0] dffe9a;
wire [6:0] wire_dffe9a_ena;
reg idle_state;
reg idle_write_wait;
reg read_address_state;
wire wire_read_address_state_ena;
reg read_data_state;
reg read_init_counter_state;
reg read_init_state;
reg read_post_state;
reg read_pre_data_state;
reg read_source_update_state;
reg write_data_state;
reg write_init_counter_state;
reg write_init_state;
reg write_load_state;
reg write_post_data_state;
reg write_pre_data_state;
reg write_source_update_state;
reg write_wait_state;
wire [5:0] wire_cntr5_q;
wire [4:0] wire_cntr6_q;
wire wire_sd4_regout;
wire bit_counter_all_done;
wire bit_counter_clear;
wire bit_counter_enable;
wire [5:0] bit_counter_param_start;
wire bit_counter_param_start_match;
wire [6:0] combine_port;
wire [23:0] data_in;
wire global_gnd;
wire global_vcc;
wire idle;
wire [6:0] param_decoder_param_latch;
wire [22:0] param_decoder_select;
wire power_up;
wire read_address;
wire read_data;
wire read_init;
wire read_init_counter;
wire read_post;
wire read_pre_data;
wire read_source_update;
wire rsource_load;
wire [1:0] rsource_parallel_in;
wire rsource_serial_out;
wire rsource_shift_enable;
wire [2:0] rsource_state_par_ini;
wire rsource_update_done;
wire rublock_captnupdt;
wire rublock_clock;
wire rublock_reconfig;
wire rublock_reconfig_st;
wire rublock_regin;
wire rublock_regout;
wire rublock_regout_reg;
wire rublock_shiftnld;
wire select_shift_nloop;
wire shift_reg_clear;
wire shift_reg_load_enable;
wire shift_reg_serial_in;
wire shift_reg_serial_out;
wire shift_reg_shift_enable;
wire [5:0] start_bit_decoder_out;
wire [22:0] start_bit_decoder_param_select;
wire [1:0] w4w;
wire [5:0] w53w;
wire [4:0] w83w;
wire width_counter_all_done;
wire width_counter_clear;
wire width_counter_enable;
wire [4:0] width_counter_param_width;
wire width_counter_param_width_match;
wire [4:0] width_decoder_out;
wire [22:0] width_decoder_param_select;
wire write_data;
wire write_init;
wire write_init_counter;
wire write_load;
wire write_param;
wire write_post_data;
wire write_pre_data;
wire write_source_update;
wire write_wait;
wire [2:0] wsource_state_par_ini;
wire wsource_update_done;
// synopsys translate_off
initial
check_busy_dffe[0:0] = 0;
// synopsys translate_on
// synopsys translate_off
initial
dffe1a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe1a0 <= 1'b0;
else if (wire_dffe1a_ena[0:0] == 1'b1) dffe1a0 <= ((rsource_load & rsource_parallel_in[0]) | ((~ rsource_load) & dffe1a1[0:0]));
// synopsys translate_off
initial
dffe1a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe1a1 <= 1'b0;
else if (wire_dffe1a_ena[1:1] == 1'b1) dffe1a1 <= (rsource_parallel_in[1] & rsource_load);
assign
wire_dffe1a_ena = {2{(rsource_load | rsource_shift_enable)}};
// synopsys translate_off
initial
dffe2a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a0 <= 1'b0;
else if (wire_dffe2a_ena[0:0] == 1'b1) dffe2a0 <= ((rsource_load & rsource_state_par_ini[0]) | ((~ rsource_load) & dffe2a1[0:0]));
// synopsys translate_off
initial
dffe2a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a1 <= 1'b0;
else if (wire_dffe2a_ena[1:1] == 1'b1) dffe2a1 <= ((rsource_load & rsource_state_par_ini[1]) | ((~ rsource_load) & dffe2a2[0:0]));
// synopsys translate_off
initial
dffe2a2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a2 <= 1'b0;
else if (wire_dffe2a_ena[2:2] == 1'b1) dffe2a2 <= (rsource_state_par_ini[2] & rsource_load);
assign
wire_dffe2a_ena = {3{(rsource_load | global_vcc)}};
// synopsys translate_off
initial
dffe3a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a0 <= 1'b0;
else if (wire_dffe3a_ena[0:0] == 1'b1) dffe3a0 <= ((rsource_load & wsource_state_par_ini[0]) | ((~ rsource_load) & dffe3a1[0:0]));
// synopsys translate_off
initial
dffe3a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a1 <= 1'b0;
else if (wire_dffe3a_ena[1:1] == 1'b1) dffe3a1 <= ((rsource_load & wsource_state_par_ini[1]) | ((~ rsource_load) & dffe3a2[0:0]));
// synopsys translate_off
initial
dffe3a2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a2 <= 1'b0;
else if (wire_dffe3a_ena[2:2] == 1'b1) dffe3a2 <= (wsource_state_par_ini[2] & rsource_load);
assign
wire_dffe3a_ena = {3{(rsource_load | global_vcc)}};
// synopsys translate_off
initial
dffe7a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[0:0] <= 1'b0;
else if (wire_dffe7a_ena[0:0] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[0:0] <= 1'b0;
else dffe7a[0:0] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[2]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[0]))) | ((~ shift_reg_load_enable) & dffe7a[1:1]));
// synopsys translate_off
initial
dffe7a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[1:1] <= 1'b0;
else if (wire_dffe7a_ena[1:1] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[1:1] <= 1'b0;
else dffe7a[1:1] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[3]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[1]))) | ((~ shift_reg_load_enable) & dffe7a[2:2]));
// synopsys translate_off
initial
dffe7a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[2:2] <= 1'b0;
else if (wire_dffe7a_ena[2:2] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[2:2] <= 1'b0;
else dffe7a[2:2] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[4]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[2]))) | ((~ shift_reg_load_enable) & dffe7a[3:3]));
// synopsys translate_off
initial
dffe7a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[3:3] <= 1'b0;
else if (wire_dffe7a_ena[3:3] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[3:3] <= 1'b0;
else dffe7a[3:3] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[5]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[3]))) | ((~ shift_reg_load_enable) & dffe7a[4:4]));
// synopsys translate_off
initial
dffe7a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[4:4] <= 1'b0;
else if (wire_dffe7a_ena[4:4] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[4:4] <= 1'b0;
else dffe7a[4:4] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[6]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[4]))) | ((~ shift_reg_load_enable) & dffe7a[5:5]));
// synopsys translate_off
initial
dffe7a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[5:5] <= 1'b0;
else if (wire_dffe7a_ena[5:5] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[5:5] <= 1'b0;
else dffe7a[5:5] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[7]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[5]))) | ((~ shift_reg_load_enable) & dffe7a[6:6]));
// synopsys translate_off
initial
dffe7a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[6:6] <= 1'b0;
else if (wire_dffe7a_ena[6:6] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[6:6] <= 1'b0;
else dffe7a[6:6] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[8]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[6]))) | ((~ shift_reg_load_enable) & dffe7a[7:7]));
// synopsys translate_off
initial
dffe7a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[7:7] <= 1'b0;
else if (wire_dffe7a_ena[7:7] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[7:7] <= 1'b0;
else dffe7a[7:7] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[9]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[7]))) | ((~ shift_reg_load_enable) & dffe7a[8:8]));
// synopsys translate_off
initial
dffe7a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[8:8] <= 1'b0;
else if (wire_dffe7a_ena[8:8] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[8:8] <= 1'b0;
else dffe7a[8:8] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[10]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[8]))) | ((~ shift_reg_load_enable) & dffe7a[9:9]));
// synopsys translate_off
initial
dffe7a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[9:9] <= 1'b0;
else if (wire_dffe7a_ena[9:9] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[9:9] <= 1'b0;
else dffe7a[9:9] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[11]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[9]))) | ((~ shift_reg_load_enable) & dffe7a[10:10]));
// synopsys translate_off
initial
dffe7a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[10:10] <= 1'b0;
else if (wire_dffe7a_ena[10:10] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[10:10] <= 1'b0;
else dffe7a[10:10] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[12]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[10]))) | ((~ shift_reg_load_enable) & dffe7a[11:11]));
// synopsys translate_off
initial
dffe7a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[11:11] <= 1'b0;
else if (wire_dffe7a_ena[11:11] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[11:11] <= 1'b0;
else dffe7a[11:11] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[13]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[11]))) | ((~ shift_reg_load_enable) & dffe7a[12:12]));
// synopsys translate_off
initial
dffe7a[12:12] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[12:12] <= 1'b0;
else if (wire_dffe7a_ena[12:12] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[12:12] <= 1'b0;
else dffe7a[12:12] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[14]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[12]))) | ((~ shift_reg_load_enable) & dffe7a[13:13]));
// synopsys translate_off
initial
dffe7a[13:13] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[13:13] <= 1'b0;
else if (wire_dffe7a_ena[13:13] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[13:13] <= 1'b0;
else dffe7a[13:13] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[15]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[13]))) | ((~ shift_reg_load_enable) & dffe7a[14:14]));
// synopsys translate_off
initial
dffe7a[14:14] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[14:14] <= 1'b0;
else if (wire_dffe7a_ena[14:14] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[14:14] <= 1'b0;
else dffe7a[14:14] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[16]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[14]))) | ((~ shift_reg_load_enable) & dffe7a[15:15]));
// synopsys translate_off
initial
dffe7a[15:15] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[15:15] <= 1'b0;
else if (wire_dffe7a_ena[15:15] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[15:15] <= 1'b0;
else dffe7a[15:15] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[17]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[15]))) | ((~ shift_reg_load_enable) & dffe7a[16:16]));
// synopsys translate_off
initial
dffe7a[16:16] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[16:16] <= 1'b0;
else if (wire_dffe7a_ena[16:16] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[16:16] <= 1'b0;
else dffe7a[16:16] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[18]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[16]))) | ((~ shift_reg_load_enable) & dffe7a[17:17]));
// synopsys translate_off
initial
dffe7a[17:17] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[17:17] <= 1'b0;
else if (wire_dffe7a_ena[17:17] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[17:17] <= 1'b0;
else dffe7a[17:17] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[19]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[17]))) | ((~ shift_reg_load_enable) & dffe7a[18:18]));
// synopsys translate_off
initial
dffe7a[18:18] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[18:18] <= 1'b0;
else if (wire_dffe7a_ena[18:18] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[18:18] <= 1'b0;
else dffe7a[18:18] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[20]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[18]))) | ((~ shift_reg_load_enable) & dffe7a[19:19]));
// synopsys translate_off
initial
dffe7a[19:19] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[19:19] <= 1'b0;
else if (wire_dffe7a_ena[19:19] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[19:19] <= 1'b0;
else dffe7a[19:19] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[21]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[19]))) | ((~ shift_reg_load_enable) & dffe7a[20:20]));
// synopsys translate_off
initial
dffe7a[20:20] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[20:20] <= 1'b0;
else if (wire_dffe7a_ena[20:20] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[20:20] <= 1'b0;
else dffe7a[20:20] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[22]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[20]))) | ((~ shift_reg_load_enable) & dffe7a[21:21]));
// synopsys translate_off
initial
dffe7a[21:21] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[21:21] <= 1'b0;
else if (wire_dffe7a_ena[21:21] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[21:21] <= 1'b0;
else dffe7a[21:21] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[23]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[21]))) | ((~ shift_reg_load_enable) & dffe7a[22:22]));
// synopsys translate_off
initial
dffe7a[22:22] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[22:22] <= 1'b0;
else if (wire_dffe7a_ena[22:22] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[22:22] <= 1'b0;
else dffe7a[22:22] <= ((~ shift_reg_load_enable) & dffe7a[23:23]);
// synopsys translate_off
initial
dffe7a[23:23] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[23:23] <= 1'b0;
else if (wire_dffe7a_ena[23:23] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[23:23] <= 1'b0;
else dffe7a[23:23] <= ((~ shift_reg_load_enable) & dffe7a[24:24]);
// synopsys translate_off
initial
dffe7a[24:24] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[24:24] <= 1'b0;
else if (wire_dffe7a_ena[24:24] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[24:24] <= 1'b0;
else dffe7a[24:24] <= ((~ shift_reg_load_enable) & dffe7a[25:25]);
// synopsys translate_off
initial
dffe7a[25:25] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[25:25] <= 1'b0;
else if (wire_dffe7a_ena[25:25] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[25:25] <= 1'b0;
else dffe7a[25:25] <= ((~ shift_reg_load_enable) & dffe7a[26:26]);
// synopsys translate_off
initial
dffe7a[26:26] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[26:26] <= 1'b0;
else if (wire_dffe7a_ena[26:26] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[26:26] <= 1'b0;
else dffe7a[26:26] <= ((~ shift_reg_load_enable) & dffe7a[27:27]);
// synopsys translate_off
initial
dffe7a[27:27] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[27:27] <= 1'b0;
else if (wire_dffe7a_ena[27:27] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[27:27] <= 1'b0;
else dffe7a[27:27] <= ((~ shift_reg_load_enable) & dffe7a[28:28]);
// synopsys translate_off
initial
dffe7a[28:28] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[28:28] <= 1'b0;
else if (wire_dffe7a_ena[28:28] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[28:28] <= 1'b0;
else dffe7a[28:28] <= ((~ shift_reg_load_enable) & shift_reg_serial_in);
assign
wire_dffe7a_ena = {29{((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_clear)}};
// synopsys translate_off
initial
dffe8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe8 <= 1'b0;
else dffe8 <= rublock_regout;
// synopsys translate_off
initial
dffe9a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[0:0] <= 1'b0;
else if (wire_dffe9a_ena[0:0] == 1'b1) dffe9a[0:0] <= combine_port[0:0];
// synopsys translate_off
initial
dffe9a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[1:1] <= 1'b0;
else if (wire_dffe9a_ena[1:1] == 1'b1) dffe9a[1:1] <= combine_port[1:1];
// synopsys translate_off
initial
dffe9a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[2:2] <= 1'b0;
else if (wire_dffe9a_ena[2:2] == 1'b1) dffe9a[2:2] <= combine_port[2:2];
// synopsys translate_off
initial
dffe9a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[3:3] <= 1'b0;
else if (wire_dffe9a_ena[3:3] == 1'b1) dffe9a[3:3] <= combine_port[3:3];
// synopsys translate_off
initial
dffe9a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[4:4] <= 1'b0;
else if (wire_dffe9a_ena[4:4] == 1'b1) dffe9a[4:4] <= combine_port[4:4];
// synopsys translate_off
initial
dffe9a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[5:5] <= 1'b0;
else if (wire_dffe9a_ena[5:5] == 1'b1) dffe9a[5:5] <= combine_port[5:5];
// synopsys translate_off
initial
dffe9a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[6:6] <= 1'b0;
else if (wire_dffe9a_ena[6:6] == 1'b1) dffe9a[6:6] <= combine_port[6:6];
assign
wire_dffe9a_ena = {7{(idle & (write_param | read_param))}};
// synopsys translate_off
initial
idle_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_state <= {1{1'b1}};
else idle_state <= ((((((idle & (~ read_param)) & (~ write_param)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up);
// synopsys translate_off
initial
idle_write_wait = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_write_wait <= 1'b0;
else idle_write_wait <= (((((((idle & (~ read_param)) & (~ write_param)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up) & write_load);
// synopsys translate_off
initial
read_address_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_address_state <= 1'b0;
else if (wire_read_address_state_ena == 1'b1) read_address_state <= (((read_param | write_param) & ((param[2] & (~ param[1])) & (~ param[0]))) & (~ (~ idle)));
assign
wire_read_address_state_ena = (read_param | write_param);
// synopsys translate_off
initial
read_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_state <= 1'b0;
else read_data_state <= (((read_init_counter & bit_counter_param_start_match) | (read_pre_data & bit_counter_param_start_match)) | ((read_data & (~ width_counter_param_width_match)) & (~ width_counter_all_done)));
// synopsys translate_off
initial
read_init_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_counter_state <= 1'b0;
else read_init_counter_state <= rsource_update_done;
// synopsys translate_off
initial
read_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_state <= 1'b0;
else read_init_state <= (idle & read_param);
// synopsys translate_off
initial
read_post_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_post_state <= 1'b0;
else read_post_state <= (((read_data & width_counter_param_width_match) & (~ width_counter_all_done)) | (read_post & (~ width_counter_all_done)));
// synopsys translate_off
initial
read_pre_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_pre_data_state <= 1'b0;
else read_pre_data_state <= ((read_init_counter & (~ bit_counter_param_start_match)) | (read_pre_data & (~ bit_counter_param_start_match)));
// synopsys translate_off
initial
read_source_update_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_source_update_state <= 1'b0;
else read_source_update_state <= ((read_init | read_source_update) & (~ rsource_update_done));
// synopsys translate_off
initial
write_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_data_state <= 1'b0;
else write_data_state <= (((write_init_counter & bit_counter_param_start_match) | (write_pre_data & bit_counter_param_start_match)) | ((write_data & (~ width_counter_param_width_match)) & (~ bit_counter_all_done)));
// synopsys translate_off
initial
write_init_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_counter_state <= 1'b0;
else write_init_counter_state <= wsource_update_done;
// synopsys translate_off
initial
write_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_state <= 1'b0;
else write_init_state <= (idle & write_param);
// synopsys translate_off
initial
write_load_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_load_state <= 1'b0;
else write_load_state <= ((write_data & bit_counter_all_done) | (write_post_data & bit_counter_all_done));
// synopsys translate_off
initial
write_post_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_post_data_state <= 1'b0;
else write_post_data_state <= (((write_data & width_counter_param_width_match) & (~ bit_counter_all_done)) | (write_post_data & (~ bit_counter_all_done)));
// synopsys translate_off
initial
write_pre_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_pre_data_state <= 1'b0;
else write_pre_data_state <= ((write_init_counter & (~ bit_counter_param_start_match)) | (write_pre_data & (~ bit_counter_param_start_match)));
// synopsys translate_off
initial
write_source_update_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_source_update_state <= 1'b0;
else write_source_update_state <= ((write_init | write_source_update) & (~ wsource_update_done));
// synopsys translate_off
initial
write_wait_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_wait_state <= 1'b0;
else write_wait_state <= write_load;
lpm_counter cntr5
(
.aclr(reset),
.clock(clock),
.cnt_en(bit_counter_enable),
.cout(),
.eq(),
.q(wire_cntr5_q),
.sclr(bit_counter_clear)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({6{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr5.lpm_direction = "UP",
cntr5.lpm_port_updown = "PORT_UNUSED",
cntr5.lpm_width = 6,
cntr5.lpm_type = "lpm_counter";
lpm_counter cntr6
(
.aclr(reset),
.clock(clock),
.cnt_en(width_counter_enable),
.cout(),
.eq(),
.q(wire_cntr6_q),
.sclr(width_counter_clear)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({5{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr6.lpm_direction = "UP",
cntr6.lpm_port_updown = "PORT_UNUSED",
cntr6.lpm_width = 5,
cntr6.lpm_type = "lpm_counter";
cycloneive_rublock sd4
(
.captnupdt(rublock_captnupdt),
.clk(rublock_clock),
.rconfig(rublock_reconfig),
.regin(rublock_regin),
.regout(wire_sd4_regout),
.rsttimer(reset_timer),
.shiftnld(rublock_shiftnld));
assign
bit_counter_all_done = (((((wire_cntr5_q[0] & (~ wire_cntr5_q[1])) & (~ wire_cntr5_q[2])) & wire_cntr5_q[3]) & (~ wire_cntr5_q[4])) & wire_cntr5_q[5]),
bit_counter_clear = (rsource_update_done | wsource_update_done),
bit_counter_enable = (((((((((rsource_update_done | wsource_update_done) | read_init_counter) | write_init_counter) | read_pre_data) | write_pre_data) | read_data) | write_data) | read_post) | write_post_data),
bit_counter_param_start = start_bit_decoder_out,
bit_counter_param_start_match = ((((((~ w53w[0]) & (~ w53w[1])) & (~ w53w[2])) & (~ w53w[3])) & (~ w53w[4])) & (~ w53w[5])),
busy = (~ idle),
combine_port = {read_param, write_param, read_source, param},
data_in = {24{1'b0}},
data_out = {((read_address & dffe7a[26]) | ((~ read_address) & dffe7a[28])), ((read_address & dffe7a[25]) | ((~ read_address) & dffe7a[27])), ((read_address & dffe7a[24]) | ((~ read_address) & dffe7a[26])), ((read_address & dffe7a[23]) | ((~ read_address) & dffe7a[25])), ((read_address & dffe7a[22]) | ((~ read_address) & dffe7a[24])), ((read_address & dffe7a[21]) | ((~ read_address) & dffe7a[23])), ((read_address & dffe7a[20]) | ((~ read_address) & dffe7a[22])), ((read_address & dffe7a[19]) | ((~ read_address) & dffe7a[21])), ((read_address & dffe7a[18]) | ((~ read_address) & dffe7a[20])), ((read_address & dffe7a[17]) | ((~ read_address) & dffe7a[19])), ((read_address & dffe7a[16]) | ((~ read_address) & dffe7a[18])), ((read_address & dffe7a[15]) | ((~ read_address) & dffe7a[17])), ((read_address & dffe7a[14]) | ((~ read_address) & dffe7a[16])), ((read_address & dffe7a[13]) | ((~ read_address) & dffe7a[15])), ((read_address & dffe7a[12]) | ((~ read_address) & dffe7a[14])), ((read_address & dffe7a[11]) | ((~ read_address) & dffe7a[13])), ((read_address & dffe7a[10]) | ((~ read_address) & dffe7a[12])), ((read_address & dffe7a[9]) | ((~ read_address) & dffe7a[11])), ((read_address & dffe7a[8]) | ((~ read_address) & dffe7a[10])), ((read_address & dffe7a[7]) | ((~ read_address) & dffe7a[9])), ((read_address & dffe7a[6]) | ((~ read_address) & dffe7a[8])), ((read_address & dffe7a[5]) | ((~ read_address) & dffe7a[7])), ((read_address & dffe7a[4]) | ((~ read_address) & dffe7a[6])), ((read_address & dffe7a[3]) | ((~ read_address) & dffe7a[5])), ((read_address & dffe7a[2]) | ((~ read_address) & dffe7a[4])), ((read_address & dffe7a[1]) | ((~ read_address) & dffe7a[3])), ((read_address & dffe7a[0]) | ((~ read_address) & dffe7a[2])), ((~ read_address) & dffe7a[1]), ((~ read_address) & dffe7a[0])},
global_gnd = 1'b0,
global_vcc = 1'b1,
idle = idle_state,
param_decoder_param_latch = dffe9a,
param_decoder_select = {(((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2]
)) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5]
)) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6])},
power_up = (((((((((((((((~ idle) & (~ read_init)) & (~ read_source_update)) & (~ read_init_counter)) & (~ read_pre_data)) & (~ read_data)) & (~ read_post)) & (~ write_init)) & (~ write_init_counter)) & (~ write_source_update)) & (~ write_pre_data)) & (~ write_data)) & (~ write_post_data)) & (~ write_load)) & (~ write_wait)),
read_address = read_address_state,
read_data = read_data_state,
read_init = read_init_state,
read_init_counter = read_init_counter_state,
read_post = read_post_state,
read_pre_data = read_pre_data_state,
read_source_update = read_source_update_state,
rsource_load = (idle & (write_param | read_param)),
rsource_parallel_in = {((w4w[1] & read_param) | write_param), ((w4w[0] & read_param) | write_param)},
rsource_serial_out = dffe1a0[0:0],
rsource_shift_enable = (read_source_update | write_source_update),
rsource_state_par_ini = {read_param, {2{global_gnd}}},
rsource_update_done = dffe2a0[0:0],
rublock_captnupdt = (~ write_load),
rublock_clock = (~ (clock | idle_write_wait)),
rublock_reconfig = rublock_reconfig_st,
rublock_reconfig_st = (idle & reconfig),
rublock_regin = (((((rublock_regout_reg & (~ select_shift_nloop)) & (~ read_source_update)) & (~ write_source_update)) | (((shift_reg_serial_out & select_shift_nloop) & (~ read_source_update)) & (~ write_source_update))) | ((read_source_update | write_source_update) & rsource_serial_out)),
rublock_regout = wire_sd4_regout,
rublock_regout_reg = dffe8,
rublock_shiftnld = (((((((read_pre_data | write_pre_data) | read_data) | write_data) | read_post) | write_post_data) | read_source_update) | write_source_update),
select_shift_nloop = ((read_data & (~ width_counter_param_width_match)) | (write_data & (~ width_counter_param_width_match))),
shift_reg_clear = rsource_update_done,
shift_reg_load_enable = (idle & write_param),
shift_reg_serial_in = (rublock_regout_reg & select_shift_nloop),
shift_reg_serial_out = dffe7a[0:0],
shift_reg_shift_enable = (((read_data | write_data) | read_post) | write_post_data),
start_bit_decoder_out = (((((((((((((((((((((({1'b0, {4{start_bit_decoder_param_select[0]}}, 1'b0} | {6{1'b0}}) | {1'b0, {4{start_bit_decoder_param_select[2]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {3{start_bit_decoder_param_select[4]}}, 1'b0, start_bit_decoder_param_select[4]}) | {1'b0, {4{start_bit_decoder_param_select[5]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[7]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[9]}}, 1'b0, start_bit_decoder_param_select[9], 1'b0}) | {1'b0, {2{start_bit_decoder_param_select[10]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[12]}}, 1'b0, start_bit_decoder_param_select[12], 1'b0}) | {start_bit_decoder_param_select[13], {2{1'b0}}, start_bit_decoder_param_select[13], 1'b0, start_bit_decoder_param_select[13]}) | {6{1'b0}}) | {start_bit_decoder_param_select[15], {3{1'b0}}, {2{start_bit_decoder_param_select[15]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[16]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[17], {2{1'b0}}, start_bit_decoder_param_select[17], {2{1'b0}}}) | {start_bit_decoder_param_select[18], {2{1'b0}}, start_bit_decoder_param_select[18], 1'b0, start_bit_decoder_param_select[18]}) | {6{1'b0}}) | {start_bit_decoder_param_select[20], {3{1'b0}}, {2{start_bit_decoder_param_select[20]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[21]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[22], {2{1'b0}}, start_bit_decoder_param_select[22], {2{1'b0}}}),
start_bit_decoder_param_select = param_decoder_select,
w4w = read_source,
w53w = (wire_cntr5_q ^ bit_counter_param_start),
w83w = (wire_cntr6_q ^ width_counter_param_width),
width_counter_all_done = (((((~ wire_cntr6_q[0]) & (~ wire_cntr6_q[1])) & wire_cntr6_q[2]) & wire_cntr6_q[3]) & wire_cntr6_q[4]),
width_counter_clear = (rsource_update_done | wsource_update_done),
width_counter_enable = ((read_data | write_data) | read_post),
width_counter_param_width = width_decoder_out,
width_counter_param_width_match = (((((~ w83w[0]) & (~ w83w[1])) & (~ w83w[2])) & (~ w83w[3])) & (~ w83w[4])),
width_decoder_out = (((((((((((((((((((((({{3{1'b0}}, width_decoder_param_select[0], 1'b0} | {{2{width_decoder_param_select[1]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[2], 1'b0}) | {{3{width_decoder_param_select[3]}}, 1'b0, width_decoder_param_select[3]}) | {{4{1'b0}}, width_decoder_param_select[4]}) | {{3{1'b0}}, width_decoder_param_select[5], 1'b0}) | {{2{width_decoder_param_select[6]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[7], 1'b0}) | {{2{width_decoder_param_select[8]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[9], 1'b0, width_decoder_param_select[9]}) | {{3{1'b0}}, width_decoder_param_select[10], 1'b0}) | {{2{width_decoder_param_select[11]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[12], 1'b0, width_decoder_param_select[12]}) | {{4{1'b0}}, width_decoder_param_select[13]}) | {1'b0, {2{width_decoder_param_select[14]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[15]}) | {width_decoder_param_select[16], 1'b0, {2{width_decoder_param_select[16]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[17]}) | {{4{1'b0}}, width_decoder_param_select[18]}) | {1'b0, {2{width_decoder_param_select[19]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[20]}) | {width_decoder_param_select[21], 1'b0, {2{width_decoder_param_select[21]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[22]}),
width_decoder_param_select = param_decoder_select,
write_data = write_data_state,
write_init = write_init_state,
write_init_counter = write_init_counter_state,
write_load = write_load_state,
write_param = 1'b0,
write_post_data = write_post_data_state,
write_pre_data = write_pre_data_state,
write_source_update = write_source_update_state,
write_wait = write_wait_state,
wsource_state_par_ini = {write_param, {2{global_gnd}}},
wsource_update_done = dffe3a0[0:0];
endmodule //altera_remote_update_core
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// Major Functions:
// This code is using for configuring the output frequency of
// SI570 I2C Programable XO/VCXO
// ============================================================================
// Design Description:
//
//
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 12/02/20 :| Initial Version
// ============================================================================
module si570_controller (
input wire iCLK, // system clock 50mhz
input wire iRST_n, // system reset
input wire iStart_Go, // system set
input wire [2:0] iFREQ_MODE, //clock frequency mode 000:100Mhz, 001: 125Mhz, 010:156.25Mhz, 011:250Mhz, 100:312.5Mhz , 101:322.26Mhz , 110:644.53Mhz ,111:100Mhz
output wire oController_rdy, // high for si570 controller is rdy
output wire I2C_CLK,
inout wire I2C_DATA,
output wire [7:0] oREAD_Data,
output wire oSI570_ONE_CLK_CONFIG_DONE
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire [6:0] slave_addr;
wire [7:0] byte_addr;
wire [7:0] byte_data;
wire wr_cmd;
//wire [7:0] oREAD_Data;
//wire [2:0] iFREQ_MODE;
wire i2c_control_start;
wire i2c_reg_control_start;
wire i2c_bus_controller_state;
wire iINITIAL_ENABLE;
wire system_start;
wire i2c_clk;
wire i2c_controller_config_done;
//wire oController_rdy;
wire initial_start;
//=============================================================================
// Structural coding
//=============================================================================
i2c_reg_controller u1(
.iCLK(iCLK), // system clock 50mhz
.iRST_n(iRST_n), // system reset
.iENABLE(system_start), // i2c reg contorl enable signale , high for enable .please use pulse
.iI2C_CONTROLLER_STATE(i2c_bus_controller_state), // i2c controller state , high for i2c controller state not in idel
.iFREQ_MODE(iFREQ_MODE), // clock frequency mode
.oSLAVE_ADDR(slave_addr),
.oBYTE_ADDR(byte_addr),
.oBYTE_DATA(byte_data),
.oWR_CMD(wr_cmd), // write or read commnad for i2c controller , 1 for write command
.oStart(i2c_reg_control_start), // i2c controller start control signal, high for start to send signal
.iI2C_CONTROLLER_CONFIG_DONE(i2c_controller_config_done),
.oSI570_ONE_CLK_CONFIG_DONE(oSI570_ONE_CLK_CONFIG_DONE),
.oController_Ready(oController_rdy),
);
initial_config initial_config(
.iCLK(iCLK), // system clock 50mhz
.iRST_n(iRST_n), // system reset
.oINITIAL_START(initial_start),
.iINITIAL_ENABLE(1'b1),
);
assign system_start = iStart_Go|initial_start;
clock_divider u3(
.iCLK(iCLK),
.iRST_n(iRST_n),
.oCLK_OUT(i2c_clk),
);
i2c_bus_controller u4 (
.iCLK(i2c_clk),
.iRST_n(iRST_n),
.iStart(i2c_reg_control_start),
.iSlave_addr(slave_addr),
.iWord_addr(byte_addr),
.iSequential_read(1'b0),
.iRead_length(8'd1),
.i2c_clk(I2C_CLK),
.i2c_data(I2C_DATA),
.i2c_read_data(oREAD_Data),
.wr_data(byte_data),
.wr_cmd(wr_cmd),
.oSYSTEM_STATE(i2c_bus_controller_state),
.oCONFIG_DONE(i2c_controller_config_done),
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// bmu module
///
///////////////////////////////////////////////////////////////////////////////
module bmu (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
// outputs
output [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
// inputs
input cx0, cx1;
// registers
reg [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
always@ (cx0 or cx1)
begin
if (cx0==0 && cx1==0)
begin
bm0 <= 2'd0; // this is going from 00 to 00
bm1 <= 2'd2; // this is going from 00 to 10
bm2 <= 2'd2; // this is going from 01 to 00
bm3 <= 2'd0; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
else if (cx0==0 && cx1==1)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd2; // this is going from 10 to 01
bm5 <= 2'd0; // this is going from 10 to 11
bm6 <= 2'd0; // this is going from 11 to 01
bm7 <= 2'd2; // this is going from 11 to 11
end
else if (cx0==1 && cx1==0)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd0; // this is going from 10 to 01
bm5 <= 2'd2; // this is going from 10 to 11
bm6 <= 2'd2; // this is going from 11 to 01
bm7 <= 2'd0; // this is going from 11 to 11
end
else if (cx0==1 && cx1==1)
begin
bm0 <= 2'd2; // this is going from 00 to 00
bm1 <= 2'd0; // this is going from 00 to 10
bm2 <= 2'd0; // this is going from 01 to 00
bm3 <= 2'd2; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
end // always @ (posedge clk)
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.49d
// \ \ Application: netgen
// / / Filename: div.v
// /___/ /\ Timestamp: Sun Jun 15 23:35:19 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/rkaria/Downloads/Verilog/ipcore_dir/tmp/_cg/div.ngc C:/Users/rkaria/Downloads/Verilog/ipcore_dir/tmp/_cg/div.v
// Device : 6slx16csg324-3
// Input file : C:/Users/rkaria/Downloads/Verilog/ipcore_dir/tmp/_cg/div.ngc
// Output file : C:/Users/rkaria/Downloads/Verilog/ipcore_dir/tmp/_cg/div.v
// # of Modules : 1
// Design Name : div
// Xilinx : C:\Xilinx\14.4\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module div (
aclk, s_axis_divisor_tvalid, s_axis_dividend_tvalid, s_axis_divisor_tready, s_axis_dividend_tready, m_axis_dout_tvalid, s_axis_divisor_tdata,
s_axis_dividend_tdata, m_axis_dout_tdata
)/* synthesis syn_black_box syn_noprune=1 */;
input aclk;
input s_axis_divisor_tvalid;
input s_axis_dividend_tvalid;
output s_axis_divisor_tready;
output s_axis_dividend_tready;
output m_axis_dout_tvalid;
input [15 : 0] s_axis_divisor_tdata;
input [15 : 0] s_axis_dividend_tdata;
output [31 : 0] m_axis_dout_tdata;
// synthesis translate_off
wire NlwRenamedSignal_s_axis_dividend_tready;
wire \blk00000001/sig000005f5 ;
wire \blk00000001/sig000005f4 ;
wire \blk00000001/sig000005f3 ;
wire \blk00000001/sig000005f2 ;
wire \blk00000001/sig000005f1 ;
wire \blk00000001/sig000005f0 ;
wire \blk00000001/sig000005ef ;
wire \blk00000001/sig000005ee ;
wire \blk00000001/sig000005ed ;
wire \blk00000001/sig000005ec ;
wire \blk00000001/sig000005eb ;
wire \blk00000001/sig000005ea ;
wire \blk00000001/sig000005e9 ;
wire \blk00000001/sig000005e8 ;
wire \blk00000001/sig000005e7 ;
wire \blk00000001/sig000005e6 ;
wire \blk00000001/sig000005e5 ;
wire \blk00000001/sig000005e4 ;
wire \blk00000001/sig000005e3 ;
wire \blk00000001/sig000005e2 ;
wire \blk00000001/sig000005e1 ;
wire \blk00000001/sig000005e0 ;
wire \blk00000001/sig000005df ;
wire \blk00000001/sig000005de ;
wire \blk00000001/sig000005dd ;
wire \blk00000001/sig000005dc ;
wire \blk00000001/sig000005db ;
wire \blk00000001/sig000005da ;
wire \blk00000001/sig000005d9 ;
wire \blk00000001/sig000005d8 ;
wire \blk00000001/sig000005d7 ;
wire \blk00000001/sig000005d6 ;
wire \blk00000001/sig000005d5 ;
wire \blk00000001/sig000005d4 ;
wire \blk00000001/sig000005d3 ;
wire \blk00000001/sig000005d2 ;
wire \blk00000001/sig000005d1 ;
wire \blk00000001/sig000005d0 ;
wire \blk00000001/sig000005cf ;
wire \blk00000001/sig000005ce ;
wire \blk00000001/sig000005cd ;
wire \blk00000001/sig000005cc ;
wire \blk00000001/sig000005cb ;
wire \blk00000001/sig000005ca ;
wire \blk00000001/sig000005c9 ;
wire \blk00000001/sig000005c8 ;
wire \blk00000001/sig000005c7 ;
wire \blk00000001/sig000005c6 ;
wire \blk00000001/sig000005c5 ;
wire \blk00000001/sig000005c4 ;
wire \blk00000001/sig000005c3 ;
wire \blk00000001/sig000005c2 ;
wire \blk00000001/sig000005c1 ;
wire \blk00000001/sig000005c0 ;
wire \blk00000001/sig000005bf ;
wire \blk00000001/sig000005be ;
wire \blk00000001/sig000005bd ;
wire \blk00000001/sig000005bc ;
wire \blk00000001/sig000005bb ;
wire \blk00000001/sig000005ba ;
wire \blk00000001/sig000005b9 ;
wire \blk00000001/sig000005b8 ;
wire \blk00000001/sig000005b7 ;
wire \blk00000001/sig000005b6 ;
wire \blk00000001/sig000005b5 ;
wire \blk00000001/sig000005b4 ;
wire \blk00000001/sig000005b3 ;
wire \blk00000001/sig000005b2 ;
wire \blk00000001/sig000005b1 ;
wire \blk00000001/sig000005b0 ;
wire \blk00000001/sig000005af ;
wire \blk00000001/sig000005ae ;
wire \blk00000001/sig000005ad ;
wire \blk00000001/sig000005ac ;
wire \blk00000001/sig000005ab ;
wire \blk00000001/sig000005aa ;
wire \blk00000001/sig000005a9 ;
wire \blk00000001/sig000005a8 ;
wire \blk00000001/sig000005a7 ;
wire \blk00000001/sig000005a6 ;
wire \blk00000001/sig000005a5 ;
wire \blk00000001/sig000005a4 ;
wire \blk00000001/sig000005a3 ;
wire \blk00000001/sig000005a2 ;
wire \blk00000001/sig000005a1 ;
wire \blk00000001/sig000005a0 ;
wire \blk00000001/sig0000059f ;
wire \blk00000001/sig0000059e ;
wire \blk00000001/sig0000059d ;
wire \blk00000001/sig0000059c ;
wire \blk00000001/sig0000059b ;
wire \blk00000001/sig0000059a ;
wire \blk00000001/sig00000599 ;
wire \blk00000001/sig00000598 ;
wire \blk00000001/sig00000597 ;
wire \blk00000001/sig00000596 ;
wire \blk00000001/sig00000595 ;
wire \blk00000001/sig00000594 ;
wire \blk00000001/sig00000593 ;
wire \blk00000001/sig00000592 ;
wire \blk00000001/sig00000591 ;
wire \blk00000001/sig00000590 ;
wire \blk00000001/sig0000058f ;
wire \blk00000001/sig0000058e ;
wire \blk00000001/sig0000058d ;
wire \blk00000001/sig0000058c ;
wire \blk00000001/sig0000058b ;
wire \blk00000001/sig0000058a ;
wire \blk00000001/sig00000589 ;
wire \blk00000001/sig00000588 ;
wire \blk00000001/sig00000587 ;
wire \blk00000001/sig00000586 ;
wire \blk00000001/sig00000585 ;
wire \blk00000001/sig00000584 ;
wire \blk00000001/sig00000583 ;
wire \blk00000001/sig00000582 ;
wire \blk00000001/sig00000581 ;
wire \blk00000001/sig00000580 ;
wire \blk00000001/sig0000057f ;
wire \blk00000001/sig0000057e ;
wire \blk00000001/sig0000057d ;
wire \blk00000001/sig0000057c ;
wire \blk00000001/sig0000057b ;
wire \blk00000001/sig0000057a ;
wire \blk00000001/sig00000579 ;
wire \blk00000001/sig00000578 ;
wire \blk00000001/sig00000577 ;
wire \blk00000001/sig00000576 ;
wire \blk00000001/sig00000575 ;
wire \blk00000001/sig00000574 ;
wire \blk00000001/sig00000573 ;
wire \blk00000001/sig00000572 ;
wire \blk00000001/sig00000571 ;
wire \blk00000001/sig00000570 ;
wire \blk00000001/sig0000056f ;
wire \blk00000001/sig0000056e ;
wire \blk00000001/sig0000056d ;
wire \blk00000001/sig0000056c ;
wire \blk00000001/sig0000056b ;
wire \blk00000001/sig0000056a ;
wire \blk00000001/sig00000569 ;
wire \blk00000001/sig00000568 ;
wire \blk00000001/sig00000567 ;
wire \blk00000001/sig00000566 ;
wire \blk00000001/sig00000565 ;
wire \blk00000001/sig00000564 ;
wire \blk00000001/sig00000563 ;
wire \blk00000001/sig00000562 ;
wire \blk00000001/sig00000561 ;
wire \blk00000001/sig00000560 ;
wire \blk00000001/sig0000055f ;
wire \blk00000001/sig0000055e ;
wire \blk00000001/sig0000055d ;
wire \blk00000001/sig0000055c ;
wire \blk00000001/sig0000055b ;
wire \blk00000001/sig0000055a ;
wire \blk00000001/sig00000559 ;
wire \blk00000001/sig00000558 ;
wire \blk00000001/sig00000557 ;
wire \blk00000001/sig00000556 ;
wire \blk00000001/sig00000555 ;
wire \blk00000001/sig00000554 ;
wire \blk00000001/sig00000553 ;
wire \blk00000001/sig00000552 ;
wire \blk00000001/sig00000551 ;
wire \blk00000001/sig00000550 ;
wire \blk00000001/sig0000054f ;
wire \blk00000001/sig0000054e ;
wire \blk00000001/sig0000054d ;
wire \blk00000001/sig0000054c ;
wire \blk00000001/sig0000054b ;
wire \blk00000001/sig0000054a ;
wire \blk00000001/sig00000549 ;
wire \blk00000001/sig00000548 ;
wire \blk00000001/sig00000547 ;
wire \blk00000001/sig00000546 ;
wire \blk00000001/sig00000545 ;
wire \blk00000001/sig00000544 ;
wire \blk00000001/sig00000543 ;
wire \blk00000001/sig00000542 ;
wire \blk00000001/sig00000541 ;
wire \blk00000001/sig00000540 ;
wire \blk00000001/sig0000053f ;
wire \blk00000001/sig0000053e ;
wire \blk00000001/sig0000053d ;
wire \blk00000001/sig0000053c ;
wire \blk00000001/sig0000053b ;
wire \blk00000001/sig0000053a ;
wire \blk00000001/sig00000539 ;
wire \blk00000001/sig00000538 ;
wire \blk00000001/sig00000537 ;
wire \blk00000001/sig00000536 ;
wire \blk00000001/sig00000535 ;
wire \blk00000001/sig00000534 ;
wire \blk00000001/sig00000533 ;
wire \blk00000001/sig00000532 ;
wire \blk00000001/sig00000531 ;
wire \blk00000001/sig00000530 ;
wire \blk00000001/sig0000052f ;
wire \blk00000001/sig0000052e ;
wire \blk00000001/sig0000052d ;
wire \blk00000001/sig0000052c ;
wire \blk00000001/sig0000052b ;
wire \blk00000001/sig0000052a ;
wire \blk00000001/sig00000529 ;
wire \blk00000001/sig00000528 ;
wire \blk00000001/sig00000527 ;
wire \blk00000001/sig00000526 ;
wire \blk00000001/sig00000525 ;
wire \blk00000001/sig00000524 ;
wire \blk00000001/sig00000523 ;
wire \blk00000001/sig00000522 ;
wire \blk00000001/sig00000521 ;
wire \blk00000001/sig00000520 ;
wire \blk00000001/sig0000051f ;
wire \blk00000001/sig0000051e ;
wire \blk00000001/sig0000051d ;
wire \blk00000001/sig0000051c ;
wire \blk00000001/sig0000051b ;
wire \blk00000001/sig0000051a ;
wire \blk00000001/sig00000519 ;
wire \blk00000001/sig00000518 ;
wire \blk00000001/sig00000517 ;
wire \blk00000001/sig00000516 ;
wire \blk00000001/sig00000515 ;
wire \blk00000001/sig00000514 ;
wire \blk00000001/sig00000513 ;
wire \blk00000001/sig00000512 ;
wire \blk00000001/sig00000511 ;
wire \blk00000001/sig00000510 ;
wire \blk00000001/sig0000050f ;
wire \blk00000001/sig0000050e ;
wire \blk00000001/sig0000050d ;
wire \blk00000001/sig0000050c ;
wire \blk00000001/sig0000050b ;
wire \blk00000001/sig0000050a ;
wire \blk00000001/sig00000509 ;
wire \blk00000001/sig00000508 ;
wire \blk00000001/sig00000507 ;
wire \blk00000001/sig00000506 ;
wire \blk00000001/sig00000505 ;
wire \blk00000001/sig00000504 ;
wire \blk00000001/sig00000503 ;
wire \blk00000001/sig00000502 ;
wire \blk00000001/sig00000501 ;
wire \blk00000001/sig00000500 ;
wire \blk00000001/sig000004ff ;
wire \blk00000001/sig000004fe ;
wire \blk00000001/sig000004fd ;
wire \blk00000001/sig000004fc ;
wire \blk00000001/sig000004fb ;
wire \blk00000001/sig000004fa ;
wire \blk00000001/sig000004f9 ;
wire \blk00000001/sig000004f8 ;
wire \blk00000001/sig000004f7 ;
wire \blk00000001/sig000004f6 ;
wire \blk00000001/sig000004f5 ;
wire \blk00000001/sig000004f4 ;
wire \blk00000001/sig000004f3 ;
wire \blk00000001/sig000004f2 ;
wire \blk00000001/sig000004f1 ;
wire \blk00000001/sig000004f0 ;
wire \blk00000001/sig000004ef ;
wire \blk00000001/sig000004ee ;
wire \blk00000001/sig000004ed ;
wire \blk00000001/sig000004ec ;
wire \blk00000001/sig000004eb ;
wire \blk00000001/sig000004ea ;
wire \blk00000001/sig000004e9 ;
wire \blk00000001/sig000004e8 ;
wire \blk00000001/sig000004e7 ;
wire \blk00000001/sig000004e6 ;
wire \blk00000001/sig000004e5 ;
wire \blk00000001/sig000004e4 ;
wire \blk00000001/sig000004e3 ;
wire \blk00000001/sig000004e2 ;
wire \blk00000001/sig000004e1 ;
wire \blk00000001/sig000004e0 ;
wire \blk00000001/sig000004df ;
wire \blk00000001/sig000004de ;
wire \blk00000001/sig000004dd ;
wire \blk00000001/sig000004dc ;
wire \blk00000001/sig000004db ;
wire \blk00000001/sig000004da ;
wire \blk00000001/sig000004d9 ;
wire \blk00000001/sig000004d8 ;
wire \blk00000001/sig000004d7 ;
wire \blk00000001/sig000004d6 ;
wire \blk00000001/sig000004d5 ;
wire \blk00000001/sig000004d4 ;
wire \blk00000001/sig000004d3 ;
wire \blk00000001/sig000004d2 ;
wire \blk00000001/sig000004d1 ;
wire \blk00000001/sig000004d0 ;
wire \blk00000001/sig000004cf ;
wire \blk00000001/sig000004ce ;
wire \blk00000001/sig000004cd ;
wire \blk00000001/sig000004cc ;
wire \blk00000001/sig000004cb ;
wire \blk00000001/sig000004ca ;
wire \blk00000001/sig000004c9 ;
wire \blk00000001/sig000004c8 ;
wire \blk00000001/sig000004c7 ;
wire \blk00000001/sig000004c6 ;
wire \blk00000001/sig000004c5 ;
wire \blk00000001/sig000004c4 ;
wire \blk00000001/sig000004c3 ;
wire \blk00000001/sig000004c2 ;
wire \blk00000001/sig000004c1 ;
wire \blk00000001/sig000004c0 ;
wire \blk00000001/sig000004bf ;
wire \blk00000001/sig000004be ;
wire \blk00000001/sig000004bd ;
wire \blk00000001/sig000004bc ;
wire \blk00000001/sig000004bb ;
wire \blk00000001/sig000004ba ;
wire \blk00000001/sig000004b9 ;
wire \blk00000001/sig000004b8 ;
wire \blk00000001/sig000004b7 ;
wire \blk00000001/sig000004b6 ;
wire \blk00000001/sig000004b5 ;
wire \blk00000001/sig000004b4 ;
wire \blk00000001/sig000004b3 ;
wire \blk00000001/sig000004b2 ;
wire \blk00000001/sig000004b1 ;
wire \blk00000001/sig000004b0 ;
wire \blk00000001/sig000004af ;
wire \blk00000001/sig000004ae ;
wire \blk00000001/sig000004ad ;
wire \blk00000001/sig000004ac ;
wire \blk00000001/sig000004ab ;
wire \blk00000001/sig000004aa ;
wire \blk00000001/sig000004a9 ;
wire \blk00000001/sig000004a8 ;
wire \blk00000001/sig000004a7 ;
wire \blk00000001/sig000004a6 ;
wire \blk00000001/sig000004a5 ;
wire \blk00000001/sig000004a4 ;
wire \blk00000001/sig000004a3 ;
wire \blk00000001/sig000004a2 ;
wire \blk00000001/sig000004a1 ;
wire \blk00000001/sig000004a0 ;
wire \blk00000001/sig0000049f ;
wire \blk00000001/sig0000049e ;
wire \blk00000001/sig0000049d ;
wire \blk00000001/sig0000049c ;
wire \blk00000001/sig0000049b ;
wire \blk00000001/sig0000049a ;
wire \blk00000001/sig00000499 ;
wire \blk00000001/sig00000498 ;
wire \blk00000001/sig00000497 ;
wire \blk00000001/sig00000496 ;
wire \blk00000001/sig00000495 ;
wire \blk00000001/sig00000494 ;
wire \blk00000001/sig00000493 ;
wire \blk00000001/sig00000492 ;
wire \blk00000001/sig00000491 ;
wire \blk00000001/sig00000490 ;
wire \blk00000001/sig0000048f ;
wire \blk00000001/sig0000048e ;
wire \blk00000001/sig0000048d ;
wire \blk00000001/sig0000048c ;
wire \blk00000001/sig0000048b ;
wire \blk00000001/sig0000048a ;
wire \blk00000001/sig00000489 ;
wire \blk00000001/sig00000488 ;
wire \blk00000001/sig00000487 ;
wire \blk00000001/sig00000486 ;
wire \blk00000001/sig00000485 ;
wire \blk00000001/sig00000484 ;
wire \blk00000001/sig00000483 ;
wire \blk00000001/sig00000482 ;
wire \blk00000001/sig00000481 ;
wire \blk00000001/sig00000480 ;
wire \blk00000001/sig0000047f ;
wire \blk00000001/sig0000047e ;
wire \blk00000001/sig0000047d ;
wire \blk00000001/sig0000047c ;
wire \blk00000001/sig0000047b ;
wire \blk00000001/sig0000047a ;
wire \blk00000001/sig00000479 ;
wire \blk00000001/sig00000478 ;
wire \blk00000001/sig00000477 ;
wire \blk00000001/sig00000476 ;
wire \blk00000001/sig00000475 ;
wire \blk00000001/sig00000474 ;
wire \blk00000001/sig00000473 ;
wire \blk00000001/sig00000472 ;
wire \blk00000001/sig00000471 ;
wire \blk00000001/sig00000470 ;
wire \blk00000001/sig0000046f ;
wire \blk00000001/sig0000046e ;
wire \blk00000001/sig0000046d ;
wire \blk00000001/sig0000046c ;
wire \blk00000001/sig0000046b ;
wire \blk00000001/sig0000046a ;
wire \blk00000001/sig00000469 ;
wire \blk00000001/sig00000468 ;
wire \blk00000001/sig00000467 ;
wire \blk00000001/sig00000466 ;
wire \blk00000001/sig00000465 ;
wire \blk00000001/sig00000464 ;
wire \blk00000001/sig00000463 ;
wire \blk00000001/sig00000462 ;
wire \blk00000001/sig00000461 ;
wire \blk00000001/sig00000460 ;
wire \blk00000001/sig0000045f ;
wire \blk00000001/sig0000045e ;
wire \blk00000001/sig0000045d ;
wire \blk00000001/sig0000045c ;
wire \blk00000001/sig0000045b ;
wire \blk00000001/sig0000045a ;
wire \blk00000001/sig00000459 ;
wire \blk00000001/sig00000458 ;
wire \blk00000001/sig00000457 ;
wire \blk00000001/sig00000456 ;
wire \blk00000001/sig00000455 ;
wire \blk00000001/sig00000454 ;
wire \blk00000001/sig00000453 ;
wire \blk00000001/sig00000452 ;
wire \blk00000001/sig00000451 ;
wire \blk00000001/sig00000450 ;
wire \blk00000001/sig0000044f ;
wire \blk00000001/sig0000044e ;
wire \blk00000001/sig0000044d ;
wire \blk00000001/sig0000044c ;
wire \blk00000001/sig0000044b ;
wire \blk00000001/sig0000044a ;
wire \blk00000001/sig00000449 ;
wire \blk00000001/sig00000448 ;
wire \blk00000001/sig00000447 ;
wire \blk00000001/sig00000446 ;
wire \blk00000001/sig00000445 ;
wire \blk00000001/sig00000444 ;
wire \blk00000001/sig00000443 ;
wire \blk00000001/sig00000442 ;
wire \blk00000001/sig00000441 ;
wire \blk00000001/sig00000440 ;
wire \blk00000001/sig0000043f ;
wire \blk00000001/sig0000043e ;
wire \blk00000001/sig0000043d ;
wire \blk00000001/sig0000043c ;
wire \blk00000001/sig0000043b ;
wire \blk00000001/sig0000043a ;
wire \blk00000001/sig00000439 ;
wire \blk00000001/sig00000438 ;
wire \blk00000001/sig00000437 ;
wire \blk00000001/sig00000436 ;
wire \blk00000001/sig00000435 ;
wire \blk00000001/sig00000434 ;
wire \blk00000001/sig00000433 ;
wire \blk00000001/sig00000432 ;
wire \blk00000001/sig00000431 ;
wire \blk00000001/sig00000430 ;
wire \blk00000001/sig0000042f ;
wire \blk00000001/sig0000042e ;
wire \blk00000001/sig0000042d ;
wire \blk00000001/sig0000042c ;
wire \blk00000001/sig0000042b ;
wire \blk00000001/sig0000042a ;
wire \blk00000001/sig00000429 ;
wire \blk00000001/sig00000428 ;
wire \blk00000001/sig00000427 ;
wire \blk00000001/sig00000426 ;
wire \blk00000001/sig00000425 ;
wire \blk00000001/sig00000424 ;
wire \blk00000001/sig00000423 ;
wire \blk00000001/sig00000422 ;
wire \blk00000001/sig00000421 ;
wire \blk00000001/sig00000420 ;
wire \blk00000001/sig0000041f ;
wire \blk00000001/sig0000041e ;
wire \blk00000001/sig0000041d ;
wire \blk00000001/sig0000041c ;
wire \blk00000001/sig0000041b ;
wire \blk00000001/sig0000041a ;
wire \blk00000001/sig00000419 ;
wire \blk00000001/sig00000418 ;
wire \blk00000001/sig00000417 ;
wire \blk00000001/sig00000416 ;
wire \blk00000001/sig00000415 ;
wire \blk00000001/sig00000414 ;
wire \blk00000001/sig00000413 ;
wire \blk00000001/sig00000412 ;
wire \blk00000001/sig00000411 ;
wire \blk00000001/sig00000410 ;
wire \blk00000001/sig0000040f ;
wire \blk00000001/sig0000040e ;
wire \blk00000001/sig0000040d ;
wire \blk00000001/sig0000040c ;
wire \blk00000001/sig0000040b ;
wire \blk00000001/sig0000040a ;
wire \blk00000001/sig00000409 ;
wire \blk00000001/sig00000408 ;
wire \blk00000001/sig00000407 ;
wire \blk00000001/sig00000406 ;
wire \blk00000001/sig00000405 ;
wire \blk00000001/sig00000404 ;
wire \blk00000001/sig00000403 ;
wire \blk00000001/sig00000402 ;
wire \blk00000001/sig00000401 ;
wire \blk00000001/sig00000400 ;
wire \blk00000001/sig000003ff ;
wire \blk00000001/sig000003fe ;
wire \blk00000001/sig000003fd ;
wire \blk00000001/sig000003fc ;
wire \blk00000001/sig000003fb ;
wire \blk00000001/sig000003fa ;
wire \blk00000001/sig000003f9 ;
wire \blk00000001/sig000003f8 ;
wire \blk00000001/sig000003f7 ;
wire \blk00000001/sig000003f6 ;
wire \blk00000001/sig000003f5 ;
wire \blk00000001/sig000003f4 ;
wire \blk00000001/sig000003f3 ;
wire \blk00000001/sig000003f2 ;
wire \blk00000001/sig000003f1 ;
wire \blk00000001/sig000003f0 ;
wire \blk00000001/sig000003ef ;
wire \blk00000001/sig000003ee ;
wire \blk00000001/sig000003ed ;
wire \blk00000001/sig000003ec ;
wire \blk00000001/sig000003eb ;
wire \blk00000001/sig000003ea ;
wire \blk00000001/sig000003e9 ;
wire \blk00000001/sig000003e8 ;
wire \blk00000001/sig000003e7 ;
wire \blk00000001/sig000003e6 ;
wire \blk00000001/sig000003e5 ;
wire \blk00000001/sig000003e4 ;
wire \blk00000001/sig000003e3 ;
wire \blk00000001/sig000003e2 ;
wire \blk00000001/sig000003e1 ;
wire \blk00000001/sig000003e0 ;
wire \blk00000001/sig000003df ;
wire \blk00000001/sig000003de ;
wire \blk00000001/sig000003dd ;
wire \blk00000001/sig000003dc ;
wire \blk00000001/sig000003db ;
wire \blk00000001/sig000003da ;
wire \blk00000001/sig000003d9 ;
wire \blk00000001/sig000003d8 ;
wire \blk00000001/sig000003d7 ;
wire \blk00000001/sig000003d6 ;
wire \blk00000001/sig000003d5 ;
wire \blk00000001/sig000003d4 ;
wire \blk00000001/sig000003d3 ;
wire \blk00000001/sig000003d2 ;
wire \blk00000001/sig000003d1 ;
wire \blk00000001/sig000003d0 ;
wire \blk00000001/sig000003cf ;
wire \blk00000001/sig000003ce ;
wire \blk00000001/sig000003cd ;
wire \blk00000001/sig000003cc ;
wire \blk00000001/sig000003cb ;
wire \blk00000001/sig000003ca ;
wire \blk00000001/sig000003c9 ;
wire \blk00000001/sig000003c8 ;
wire \blk00000001/sig000003c7 ;
wire \blk00000001/sig000003c6 ;
wire \blk00000001/sig000003c5 ;
wire \blk00000001/sig000003c4 ;
wire \blk00000001/sig000003c3 ;
wire \blk00000001/sig000003c2 ;
wire \blk00000001/sig000003c1 ;
wire \blk00000001/sig000003c0 ;
wire \blk00000001/sig000003bf ;
wire \blk00000001/sig000003be ;
wire \blk00000001/sig000003bd ;
wire \blk00000001/sig000003bc ;
wire \blk00000001/sig000003bb ;
wire \blk00000001/sig000003ba ;
wire \blk00000001/sig000003b9 ;
wire \blk00000001/sig000003b8 ;
wire \blk00000001/sig000003b7 ;
wire \blk00000001/sig000003b6 ;
wire \blk00000001/sig000003b5 ;
wire \blk00000001/sig000003b4 ;
wire \blk00000001/sig000003b3 ;
wire \blk00000001/sig000003b2 ;
wire \blk00000001/sig000003b1 ;
wire \blk00000001/sig000003b0 ;
wire \blk00000001/sig000003af ;
wire \blk00000001/sig000003ae ;
wire \blk00000001/sig000003ad ;
wire \blk00000001/sig000003ac ;
wire \blk00000001/sig000003ab ;
wire \blk00000001/sig000003aa ;
wire \blk00000001/sig000003a9 ;
wire \blk00000001/sig000003a8 ;
wire \blk00000001/sig000003a7 ;
wire \blk00000001/sig000003a6 ;
wire \blk00000001/sig000003a5 ;
wire \blk00000001/sig000003a4 ;
wire \blk00000001/sig000003a3 ;
wire \blk00000001/sig000003a2 ;
wire \blk00000001/sig000003a1 ;
wire \blk00000001/sig000003a0 ;
wire \blk00000001/sig0000039f ;
wire \blk00000001/sig0000039e ;
wire \blk00000001/sig0000039d ;
wire \blk00000001/sig0000039c ;
wire \blk00000001/sig0000039b ;
wire \blk00000001/sig0000039a ;
wire \blk00000001/sig00000399 ;
wire \blk00000001/sig00000398 ;
wire \blk00000001/sig00000397 ;
wire \blk00000001/sig00000396 ;
wire \blk00000001/sig00000395 ;
wire \blk00000001/sig00000394 ;
wire \blk00000001/sig00000393 ;
wire \blk00000001/sig00000392 ;
wire \blk00000001/sig00000391 ;
wire \blk00000001/sig00000390 ;
wire \blk00000001/sig0000038f ;
wire \blk00000001/sig0000038e ;
wire \blk00000001/sig0000038d ;
wire \blk00000001/sig0000038c ;
wire \blk00000001/sig0000038b ;
wire \blk00000001/sig0000038a ;
wire \blk00000001/sig00000389 ;
wire \blk00000001/sig00000388 ;
wire \blk00000001/sig00000387 ;
wire \blk00000001/sig00000386 ;
wire \blk00000001/sig00000385 ;
wire \blk00000001/sig00000384 ;
wire \blk00000001/sig00000383 ;
wire \blk00000001/sig00000382 ;
wire \blk00000001/sig00000381 ;
wire \blk00000001/sig00000380 ;
wire \blk00000001/sig0000037f ;
wire \blk00000001/sig0000037e ;
wire \blk00000001/sig0000037d ;
wire \blk00000001/sig0000037c ;
wire \blk00000001/sig0000037b ;
wire \blk00000001/sig0000037a ;
wire \blk00000001/sig00000379 ;
wire \blk00000001/sig00000378 ;
wire \blk00000001/sig00000377 ;
wire \blk00000001/sig00000376 ;
wire \blk00000001/sig00000375 ;
wire \blk00000001/sig00000374 ;
wire \blk00000001/sig00000373 ;
wire \blk00000001/sig00000372 ;
wire \blk00000001/sig00000371 ;
wire \blk00000001/sig00000370 ;
wire \blk00000001/sig0000036f ;
wire \blk00000001/sig0000036e ;
wire \blk00000001/sig0000036d ;
wire \blk00000001/sig0000036c ;
wire \blk00000001/sig0000036b ;
wire \blk00000001/sig0000036a ;
wire \blk00000001/sig00000369 ;
wire \blk00000001/sig00000368 ;
wire \blk00000001/sig00000367 ;
wire \blk00000001/sig00000366 ;
wire \blk00000001/sig00000365 ;
wire \blk00000001/sig00000364 ;
wire \blk00000001/sig00000363 ;
wire \blk00000001/sig00000362 ;
wire \blk00000001/sig00000361 ;
wire \blk00000001/sig00000360 ;
wire \blk00000001/sig0000035f ;
wire \blk00000001/sig0000035e ;
wire \blk00000001/sig0000035d ;
wire \blk00000001/sig0000035c ;
wire \blk00000001/sig0000035b ;
wire \blk00000001/sig0000035a ;
wire \blk00000001/sig00000359 ;
wire \blk00000001/sig00000358 ;
wire \blk00000001/sig00000357 ;
wire \blk00000001/sig00000356 ;
wire \blk00000001/sig00000355 ;
wire \blk00000001/sig00000354 ;
wire \blk00000001/sig00000353 ;
wire \blk00000001/sig00000352 ;
wire \blk00000001/sig00000351 ;
wire \blk00000001/sig00000350 ;
wire \blk00000001/sig0000034f ;
wire \blk00000001/sig0000034e ;
wire \blk00000001/sig0000034d ;
wire \blk00000001/sig0000034c ;
wire \blk00000001/sig0000034b ;
wire \blk00000001/sig0000034a ;
wire \blk00000001/sig00000349 ;
wire \blk00000001/sig00000348 ;
wire \blk00000001/sig00000347 ;
wire \blk00000001/sig00000346 ;
wire \blk00000001/sig00000345 ;
wire \blk00000001/sig00000344 ;
wire \blk00000001/sig00000343 ;
wire \blk00000001/sig00000342 ;
wire \blk00000001/sig00000341 ;
wire \blk00000001/sig00000340 ;
wire \blk00000001/sig0000033f ;
wire \blk00000001/sig0000033e ;
wire \blk00000001/sig0000033d ;
wire \blk00000001/sig0000033c ;
wire \blk00000001/sig0000033b ;
wire \blk00000001/sig0000033a ;
wire \blk00000001/sig00000339 ;
wire \blk00000001/sig00000338 ;
wire \blk00000001/sig00000337 ;
wire \blk00000001/sig00000336 ;
wire \blk00000001/sig00000335 ;
wire \blk00000001/sig00000334 ;
wire \blk00000001/sig00000333 ;
wire \blk00000001/sig00000332 ;
wire \blk00000001/sig00000331 ;
wire \blk00000001/sig00000330 ;
wire \blk00000001/sig0000032f ;
wire \blk00000001/sig0000032e ;
wire \blk00000001/sig0000032d ;
wire \blk00000001/sig0000032c ;
wire \blk00000001/sig0000032b ;
wire \blk00000001/sig0000032a ;
wire \blk00000001/sig00000329 ;
wire \blk00000001/sig00000328 ;
wire \blk00000001/sig00000327 ;
wire \blk00000001/sig00000326 ;
wire \blk00000001/sig00000325 ;
wire \blk00000001/sig00000324 ;
wire \blk00000001/sig00000323 ;
wire \blk00000001/sig00000322 ;
wire \blk00000001/sig00000321 ;
wire \blk00000001/sig00000320 ;
wire \blk00000001/sig0000031f ;
wire \blk00000001/sig0000031e ;
wire \blk00000001/sig0000031d ;
wire \blk00000001/sig0000031c ;
wire \blk00000001/sig0000031b ;
wire \blk00000001/sig0000031a ;
wire \blk00000001/sig00000319 ;
wire \blk00000001/sig00000318 ;
wire \blk00000001/sig00000317 ;
wire \blk00000001/sig00000316 ;
wire \blk00000001/sig00000315 ;
wire \blk00000001/sig00000314 ;
wire \blk00000001/sig00000313 ;
wire \blk00000001/sig00000312 ;
wire \blk00000001/sig00000311 ;
wire \blk00000001/sig00000310 ;
wire \blk00000001/sig0000030f ;
wire \blk00000001/sig0000030e ;
wire \blk00000001/sig0000030d ;
wire \blk00000001/sig0000030c ;
wire \blk00000001/sig0000030b ;
wire \blk00000001/sig0000030a ;
wire \blk00000001/sig00000309 ;
wire \blk00000001/sig00000308 ;
wire \blk00000001/sig00000307 ;
wire \blk00000001/sig00000306 ;
wire \blk00000001/sig00000305 ;
wire \blk00000001/sig00000304 ;
wire \blk00000001/sig00000303 ;
wire \blk00000001/sig00000302 ;
wire \blk00000001/sig00000301 ;
wire \blk00000001/sig00000300 ;
wire \blk00000001/sig000002ff ;
wire \blk00000001/sig000002fe ;
wire \blk00000001/sig000002fd ;
wire \blk00000001/sig000002fc ;
wire \blk00000001/sig000002fb ;
wire \blk00000001/sig000002fa ;
wire \blk00000001/sig000002f9 ;
wire \blk00000001/sig000002f8 ;
wire \blk00000001/sig000002f7 ;
wire \blk00000001/sig000002f6 ;
wire \blk00000001/sig000002f5 ;
wire \blk00000001/sig000002f4 ;
wire \blk00000001/sig000002f3 ;
wire \blk00000001/sig000002f2 ;
wire \blk00000001/sig000002f1 ;
wire \blk00000001/sig000002f0 ;
wire \blk00000001/sig000002ef ;
wire \blk00000001/sig000002ee ;
wire \blk00000001/sig000002ed ;
wire \blk00000001/sig000002ec ;
wire \blk00000001/sig000002eb ;
wire \blk00000001/sig000002ea ;
wire \blk00000001/sig000002e9 ;
wire \blk00000001/sig000002e8 ;
wire \blk00000001/sig000002e7 ;
wire \blk00000001/sig000002e6 ;
wire \blk00000001/sig000002e5 ;
wire \blk00000001/sig000002e4 ;
wire \blk00000001/sig000002e3 ;
wire \blk00000001/sig000002e2 ;
wire \blk00000001/sig000002e1 ;
wire \blk00000001/sig000002e0 ;
wire \blk00000001/sig000002df ;
wire \blk00000001/sig000002de ;
wire \blk00000001/sig000002dd ;
wire \blk00000001/sig000002dc ;
wire \blk00000001/sig000002db ;
wire \blk00000001/sig000002da ;
wire \blk00000001/sig000002d9 ;
wire \blk00000001/sig000002d8 ;
wire \blk00000001/sig000002d7 ;
wire \blk00000001/sig000002d6 ;
wire \blk00000001/sig000002d5 ;
wire \blk00000001/sig000002d4 ;
wire \blk00000001/sig000002d3 ;
wire \blk00000001/sig000002d2 ;
wire \blk00000001/sig000002d1 ;
wire \blk00000001/sig000002d0 ;
wire \blk00000001/sig000002cf ;
wire \blk00000001/sig000002ce ;
wire \blk00000001/sig000002cd ;
wire \blk00000001/sig000002cc ;
wire \blk00000001/sig000002cb ;
wire \blk00000001/sig000002ca ;
wire \blk00000001/sig000002c9 ;
wire \blk00000001/sig000002c8 ;
wire \blk00000001/sig000002c7 ;
wire \blk00000001/sig000002c6 ;
wire \blk00000001/sig000002c5 ;
wire \blk00000001/sig000002c4 ;
wire \blk00000001/sig000002c3 ;
wire \blk00000001/sig000002c2 ;
wire \blk00000001/sig000002c1 ;
wire \blk00000001/sig000002c0 ;
wire \blk00000001/sig000002bf ;
wire \blk00000001/sig000002be ;
wire \blk00000001/sig000002bd ;
wire \blk00000001/sig000002bc ;
wire \blk00000001/sig000002bb ;
wire \blk00000001/sig000002ba ;
wire \blk00000001/sig000002b9 ;
wire \blk00000001/sig000002b8 ;
wire \blk00000001/sig000002b7 ;
wire \blk00000001/sig000002b6 ;
wire \blk00000001/sig000002b5 ;
wire \blk00000001/sig000002b4 ;
wire \blk00000001/sig000002b3 ;
wire \blk00000001/sig000002b2 ;
wire \blk00000001/sig000002b1 ;
wire \blk00000001/sig000002b0 ;
wire \blk00000001/sig000002af ;
wire \blk00000001/sig000002ae ;
wire \blk00000001/sig000002ad ;
wire \blk00000001/sig000002ac ;
wire \blk00000001/sig000002ab ;
wire \blk00000001/sig000002aa ;
wire \blk00000001/sig000002a9 ;
wire \blk00000001/sig000002a8 ;
wire \blk00000001/sig000002a7 ;
wire \blk00000001/sig000002a6 ;
wire \blk00000001/sig000002a5 ;
wire \blk00000001/sig000002a4 ;
wire \blk00000001/sig000002a3 ;
wire \blk00000001/sig000002a2 ;
wire \blk00000001/sig000002a1 ;
wire \blk00000001/sig000002a0 ;
wire \blk00000001/sig0000029f ;
wire \blk00000001/sig0000029e ;
wire \blk00000001/sig0000029d ;
wire \blk00000001/sig0000029c ;
wire \blk00000001/sig0000029b ;
wire \blk00000001/sig0000029a ;
wire \blk00000001/sig00000299 ;
wire \blk00000001/sig00000298 ;
wire \blk00000001/sig00000297 ;
wire \blk00000001/sig00000296 ;
wire \blk00000001/sig00000295 ;
wire \blk00000001/sig00000294 ;
wire \blk00000001/sig00000293 ;
wire \blk00000001/sig00000292 ;
wire \blk00000001/sig00000291 ;
wire \blk00000001/sig00000290 ;
wire \blk00000001/sig0000028f ;
wire \blk00000001/sig0000028e ;
wire \blk00000001/sig0000028d ;
wire \blk00000001/sig0000028c ;
wire \blk00000001/sig0000028b ;
wire \blk00000001/sig0000028a ;
wire \blk00000001/sig00000289 ;
wire \blk00000001/sig00000288 ;
wire \blk00000001/sig00000287 ;
wire \blk00000001/sig00000286 ;
wire \blk00000001/sig00000285 ;
wire \blk00000001/sig00000284 ;
wire \blk00000001/sig00000283 ;
wire \blk00000001/sig00000282 ;
wire \blk00000001/sig00000281 ;
wire \blk00000001/sig00000280 ;
wire \blk00000001/sig0000027f ;
wire \blk00000001/sig0000027e ;
wire \blk00000001/sig0000027d ;
wire \blk00000001/sig0000027c ;
wire \blk00000001/sig0000027b ;
wire \blk00000001/sig0000027a ;
wire \blk00000001/sig00000279 ;
wire \blk00000001/sig00000278 ;
wire \blk00000001/sig00000277 ;
wire \blk00000001/sig00000276 ;
wire \blk00000001/sig00000275 ;
wire \blk00000001/sig00000274 ;
wire \blk00000001/sig00000273 ;
wire \blk00000001/sig00000272 ;
wire \blk00000001/sig00000271 ;
wire \blk00000001/sig00000270 ;
wire \blk00000001/sig0000026f ;
wire \blk00000001/sig0000026e ;
wire \blk00000001/sig0000026d ;
wire \blk00000001/sig0000026c ;
wire \blk00000001/sig0000026b ;
wire \blk00000001/sig0000026a ;
wire \blk00000001/sig00000269 ;
wire \blk00000001/sig00000268 ;
wire \blk00000001/sig00000267 ;
wire \blk00000001/sig00000266 ;
wire \blk00000001/sig00000265 ;
wire \blk00000001/sig00000264 ;
wire \blk00000001/sig00000263 ;
wire \blk00000001/sig00000262 ;
wire \blk00000001/sig00000261 ;
wire \blk00000001/sig00000260 ;
wire \blk00000001/sig0000025f ;
wire \blk00000001/sig0000025e ;
wire \blk00000001/sig0000025d ;
wire \blk00000001/sig0000025c ;
wire \blk00000001/sig0000025b ;
wire \blk00000001/sig0000025a ;
wire \blk00000001/sig00000259 ;
wire \blk00000001/sig00000258 ;
wire \blk00000001/sig00000257 ;
wire \blk00000001/sig00000256 ;
wire \blk00000001/sig00000255 ;
wire \blk00000001/sig00000254 ;
wire \blk00000001/sig00000253 ;
wire \blk00000001/sig00000252 ;
wire \blk00000001/sig00000251 ;
wire \blk00000001/sig00000250 ;
wire \blk00000001/sig0000024f ;
wire \blk00000001/sig0000024e ;
wire \blk00000001/sig0000024d ;
wire \blk00000001/sig0000024c ;
wire \blk00000001/sig0000024b ;
wire \blk00000001/sig0000024a ;
wire \blk00000001/sig00000249 ;
wire \blk00000001/sig00000248 ;
wire \blk00000001/sig00000247 ;
wire \blk00000001/sig00000246 ;
wire \blk00000001/sig00000245 ;
wire \blk00000001/sig00000244 ;
wire \blk00000001/sig00000243 ;
wire \blk00000001/sig00000242 ;
wire \blk00000001/sig00000241 ;
wire \blk00000001/sig00000240 ;
wire \blk00000001/sig0000023f ;
wire \blk00000001/sig0000023e ;
wire \blk00000001/sig0000023d ;
wire \blk00000001/sig0000023c ;
wire \blk00000001/sig0000023b ;
wire \blk00000001/sig0000023a ;
wire \blk00000001/sig00000239 ;
wire \blk00000001/sig00000238 ;
wire \blk00000001/sig00000237 ;
wire \blk00000001/sig00000236 ;
wire \blk00000001/sig00000235 ;
wire \blk00000001/sig00000234 ;
wire \blk00000001/sig00000233 ;
wire \blk00000001/sig00000232 ;
wire \blk00000001/sig00000231 ;
wire \blk00000001/sig00000230 ;
wire \blk00000001/sig0000022f ;
wire \blk00000001/sig0000022e ;
wire \blk00000001/sig0000022d ;
wire \blk00000001/sig0000022c ;
wire \blk00000001/sig0000022b ;
wire \blk00000001/sig0000022a ;
wire \blk00000001/sig00000229 ;
wire \blk00000001/sig00000228 ;
wire \blk00000001/sig00000227 ;
wire \blk00000001/sig00000226 ;
wire \blk00000001/sig00000225 ;
wire \blk00000001/sig00000224 ;
wire \blk00000001/sig00000223 ;
wire \blk00000001/sig00000222 ;
wire \blk00000001/sig00000221 ;
wire \blk00000001/sig00000220 ;
wire \blk00000001/sig0000021f ;
wire \blk00000001/sig0000021e ;
wire \blk00000001/sig0000021d ;
wire \blk00000001/sig0000021c ;
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/blk000000ae/sig000006d6 ;
wire \blk00000001/blk000000ae/sig000006d5 ;
wire \blk00000001/blk000000ae/sig000006d4 ;
wire \blk00000001/blk000000ae/sig000006d3 ;
wire \blk00000001/blk000000ae/sig000006d2 ;
wire \blk00000001/blk000000ae/sig000006d1 ;
wire \blk00000001/blk000000ae/sig000006d0 ;
wire \blk00000001/blk000000ae/sig000006cf ;
wire \blk00000001/blk000000ae/sig000006ce ;
wire \blk00000001/blk000000ae/sig000006cd ;
wire \blk00000001/blk000000ae/sig000006cc ;
wire \blk00000001/blk000000ae/sig000006cb ;
wire \blk00000001/blk000000ae/sig000006ca ;
wire \blk00000001/blk000000ae/sig000006c9 ;
wire \blk00000001/blk000000ae/sig000006c8 ;
wire \blk00000001/blk000000ae/sig000006c7 ;
wire \blk00000001/blk000000ae/sig000006c6 ;
wire \blk00000001/blk000000ae/sig000006c5 ;
wire \blk00000001/blk000000ae/sig000006c4 ;
wire \blk00000001/blk000000ae/sig000006c3 ;
wire \blk00000001/blk000000ae/sig000006c2 ;
wire \blk00000001/blk000000ae/sig000006c1 ;
wire \blk00000001/blk000000ae/sig000006c0 ;
wire \blk00000001/blk000000ae/sig000006bf ;
wire \blk00000001/blk000000ae/sig000006be ;
wire \blk00000001/blk000000ae/sig000006bd ;
wire \blk00000001/blk000000ae/sig000006bc ;
wire \blk00000001/blk000000ae/sig000006bb ;
wire \blk00000001/blk000000ae/sig000006ba ;
wire \blk00000001/blk000000ae/sig000006b9 ;
wire \blk00000001/blk000000ae/sig000006b8 ;
wire \blk00000001/blk000000ae/sig000006b7 ;
wire \blk00000001/blk000000ae/sig000006b6 ;
wire \blk00000001/blk000000ae/sig000006b5 ;
wire \blk00000001/blk000000ae/sig000006b4 ;
wire \blk00000001/blk000000ae/sig000006b3 ;
wire \blk00000001/blk000000ae/sig000006b2 ;
wire \blk00000001/blk000000ae/sig000006b1 ;
wire \blk00000001/blk000000ae/sig000006b0 ;
wire \blk00000001/blk000000ae/sig000006af ;
wire \blk00000001/blk000000ae/sig000006ae ;
wire \blk00000001/blk000000ae/sig000006ad ;
wire \blk00000001/blk000000ae/sig000006ac ;
wire \blk00000001/blk000000ae/sig000006ab ;
wire \blk00000001/blk000000ae/sig000006aa ;
wire \blk00000001/blk000000ae/sig000006a9 ;
wire \blk00000001/blk000000ae/sig000006a8 ;
wire \blk00000001/blk000000ae/sig000006a7 ;
wire \blk00000001/blk000000ae/sig000006a6 ;
wire \blk00000001/blk000000ae/sig000006a5 ;
wire \blk00000001/blk000000ae/sig000006a4 ;
wire \blk00000001/blk000000ae/sig000006a3 ;
wire \blk00000001/blk000000ae/sig000006a2 ;
wire \blk00000001/blk000000ae/sig000006a1 ;
wire \blk00000001/blk000000ae/sig000006a0 ;
wire \blk00000001/blk000000ae/sig0000069f ;
wire \blk00000001/blk000000ae/sig0000069e ;
wire \blk00000001/blk000000ae/sig0000069d ;
wire \blk00000001/blk000000ae/sig0000069c ;
wire \blk00000001/blk000000ae/sig0000069b ;
wire \blk00000001/blk000000ae/sig0000069a ;
wire \blk00000001/blk000000ae/sig00000699 ;
wire \blk00000001/blk000000ae/sig00000698 ;
wire \blk00000001/blk000000ae/sig00000697 ;
wire \blk00000001/blk000000ae/sig00000696 ;
wire \blk00000001/blk000000ae/sig00000695 ;
wire \blk00000001/blk000000ae/sig00000694 ;
wire \blk00000001/blk000000ae/sig00000693 ;
wire \blk00000001/blk000000ae/sig00000692 ;
wire \blk00000001/blk000000ae/sig00000691 ;
wire \blk00000001/blk000000ae/sig00000690 ;
wire \blk00000001/blk000000ae/sig0000068f ;
wire \blk00000001/blk000000ae/sig0000068e ;
wire \blk00000001/blk000000ae/sig0000068d ;
wire \blk00000001/blk000000ae/sig0000068c ;
wire \blk00000001/blk000000ae/sig0000068b ;
wire \blk00000001/blk000000ae/sig0000068a ;
wire \blk00000001/blk000000ae/sig00000689 ;
wire \blk00000001/blk000000ae/sig00000688 ;
wire \blk00000001/blk000000ae/sig00000687 ;
wire \blk00000001/blk000000ae/sig00000686 ;
wire \blk00000001/blk000000ae/sig00000685 ;
wire \blk00000001/blk000000ae/sig00000684 ;
wire \blk00000001/blk000000ae/sig00000683 ;
wire \blk00000001/blk000000ae/sig00000682 ;
wire \blk00000001/blk000000ae/sig00000681 ;
wire \blk00000001/blk000000ae/sig00000680 ;
wire \blk00000001/blk000000ae/sig0000067f ;
wire \blk00000001/blk000000ae/sig0000067e ;
wire \blk00000001/blk000000ae/sig0000067d ;
wire \blk00000001/blk000000ae/sig0000067c ;
wire \blk00000001/blk000000ae/sig0000067b ;
wire \blk00000001/blk000000ae/sig0000067a ;
wire \blk00000001/blk000000ae/sig00000679 ;
wire \blk00000001/blk000000ae/sig00000678 ;
wire \blk00000001/blk000000ae/sig00000677 ;
wire \blk00000001/blk000000ae/sig00000676 ;
wire \blk00000001/blk000000ae/sig00000675 ;
wire \blk00000001/blk000000ae/sig00000674 ;
wire \blk00000001/blk000000ae/sig00000673 ;
wire \blk00000001/blk000000ae/sig00000672 ;
wire \blk00000001/blk000000ae/sig00000671 ;
wire \blk00000001/blk000000ae/sig00000670 ;
wire \blk00000001/blk000000ae/sig0000066f ;
wire \blk00000001/blk000000ae/sig0000066e ;
wire \blk00000001/blk000000ae/sig0000066d ;
wire \blk00000001/blk000000ae/sig0000066c ;
wire \blk00000001/blk000000ae/sig0000066b ;
wire \blk00000001/blk000000ae/sig0000066a ;
wire \blk00000001/blk000000ae/sig00000669 ;
wire \blk00000001/blk000000ae/sig00000668 ;
wire \blk00000001/blk000000ae/sig00000667 ;
wire \blk00000001/blk000000ae/sig00000666 ;
wire \blk00000001/blk000000ae/sig00000665 ;
wire \blk00000001/blk000000ae/sig00000664 ;
wire \blk00000001/blk000000ae/sig00000663 ;
wire \blk00000001/blk000000ae/sig00000662 ;
wire \blk00000001/blk000000ae/sig00000661 ;
wire \blk00000001/blk000000ae/sig00000660 ;
wire \blk00000001/blk000000ae/sig0000065f ;
wire \blk00000001/blk000000ae/sig0000065e ;
wire \blk00000001/blk000000ae/sig0000065d ;
wire \blk00000001/blk000000ae/sig0000065c ;
wire \blk00000001/blk000000ae/sig0000065b ;
wire \blk00000001/blk000000ae/sig0000065a ;
wire \blk00000001/blk000000ae/sig00000659 ;
wire \blk00000001/blk000000ae/sig00000658 ;
wire \blk00000001/blk000000ae/sig00000657 ;
wire \blk00000001/blk000000ae/sig00000656 ;
wire \blk00000001/blk000000ae/sig00000655 ;
wire \blk00000001/blk000000ae/sig00000654 ;
wire \blk00000001/blk000000ae/sig00000653 ;
wire \blk00000001/blk000000ae/sig00000652 ;
wire \blk00000001/blk000000ae/sig00000651 ;
wire \blk00000001/blk000000ae/sig00000650 ;
wire \blk00000001/blk000000ae/sig0000064f ;
wire \blk00000001/blk000000ae/sig0000064e ;
wire \blk00000001/blk000000ae/sig0000064d ;
wire \blk00000001/blk000000ae/sig0000064c ;
wire \blk00000001/blk000000ae/sig0000064b ;
wire \blk00000001/blk000000ae/sig0000064a ;
wire \blk00000001/blk000000ae/sig00000649 ;
wire \blk00000001/blk000000ae/sig00000648 ;
wire \blk00000001/blk000000ae/sig00000647 ;
wire \blk00000001/blk000000ae/sig00000646 ;
wire \blk00000001/blk000000ae/sig00000645 ;
wire \blk00000001/blk000000ae/sig00000644 ;
wire \blk00000001/blk000000ae/sig00000643 ;
wire \blk00000001/blk000000ae/sig00000642 ;
wire \blk00000001/blk000000ae/sig00000641 ;
wire \blk00000001/blk000000ae/sig00000640 ;
wire \blk00000001/blk000000ae/sig0000063f ;
wire \blk00000001/blk000000ae/sig0000063e ;
wire \blk00000001/blk000000ae/sig0000063d ;
wire \blk00000001/blk000000ae/sig0000063c ;
wire \blk00000001/blk000000ae/sig0000063b ;
wire \blk00000001/blk000000ae/sig0000063a ;
wire \blk00000001/blk000000ae/sig00000639 ;
wire \blk00000001/blk000000ae/sig00000638 ;
wire \blk00000001/blk000000ae/sig00000637 ;
wire \blk00000001/blk000000ae/sig00000636 ;
wire \blk00000001/blk000000ae/sig00000627 ;
wire \blk00000001/blk000000ae/sig00000626 ;
wire \blk00000001/blk000000ae/sig00000625 ;
wire \blk00000001/blk000000ae/sig00000624 ;
wire \blk00000001/blk000000ae/sig00000623 ;
wire \blk00000001/blk000000ae/sig00000622 ;
wire \blk00000001/blk000000ae/sig00000621 ;
wire \blk00000001/blk000000ae/sig00000620 ;
wire \blk00000001/blk000000ae/sig0000061f ;
wire \blk00000001/blk000000ae/sig0000061e ;
wire \blk00000001/blk000000ae/sig0000061d ;
wire \blk00000001/blk000000ae/sig0000061c ;
wire \blk00000001/blk000000ae/sig0000061b ;
wire \blk00000001/blk000000ae/sig0000061a ;
wire \blk00000001/blk000000ae/sig00000619 ;
wire \blk00000001/blk000000ae/sig00000618 ;
wire \NLW_blk00000001/blk000004ac_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004aa_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004a8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004a6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004a4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004a2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000004a0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000049e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000049c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000049a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000498_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000496_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000494_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000492_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000490_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000048e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000048c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000048a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000488_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000486_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000484_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000482_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000480_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000047e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000047c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000047a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000478_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000476_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000474_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000472_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000470_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000046e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000046c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000046a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000468_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000466_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000464_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000462_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000460_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000045e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000045c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000045a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000458_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000456_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000454_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000452_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000450_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000044e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000044c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000044a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000448_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000446_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000444_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000442_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000440_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000043e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000043c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000043a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000438_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000436_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000434_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000432_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000430_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000042e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000042c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000042a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000428_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000426_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000424_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000422_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000420_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000041e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000041c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000041a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000418_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000416_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000414_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000412_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000410_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000040e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000040c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000040a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000408_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000406_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000404_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000402_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000400_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003fe_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003fc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003fa_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003f8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003f6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003f4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003f2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003f0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ee_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ec_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ea_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003e8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003e6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003e4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003e2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003e0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003de_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003dc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003da_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003d8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003d6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003d4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003d2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003d0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ce_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003cc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ca_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003c8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003c6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003c4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003c2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003c0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003be_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003bc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ba_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003b8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003b6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003b4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003b2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003b0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ae_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003ac_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003aa_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003a8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003a6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003a4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003a2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000003a0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000039d_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020e_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001da_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d8_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d6_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ad_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004e_O_UNCONNECTED ;
wire \NLW_blk00000001/blk0000000a_O_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_C<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b2_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ae/blk000000b1_M<0>_UNCONNECTED ;
wire [24 : 24] NlwRenamedSignal_m_axis_dout_tdata;
wire [11 : 0] NlwRenamedSig_OI_m_axis_dout_tdata;
assign
m_axis_dout_tdata[31] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[30] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[29] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[28] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[27] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[26] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[25] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[24] = NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[11] = NlwRenamedSig_OI_m_axis_dout_tdata[11],
m_axis_dout_tdata[10] = NlwRenamedSig_OI_m_axis_dout_tdata[10],
m_axis_dout_tdata[9] = NlwRenamedSig_OI_m_axis_dout_tdata[9],
m_axis_dout_tdata[8] = NlwRenamedSig_OI_m_axis_dout_tdata[8],
m_axis_dout_tdata[7] = NlwRenamedSig_OI_m_axis_dout_tdata[7],
m_axis_dout_tdata[6] = NlwRenamedSig_OI_m_axis_dout_tdata[6],
m_axis_dout_tdata[5] = NlwRenamedSig_OI_m_axis_dout_tdata[5],
m_axis_dout_tdata[4] = NlwRenamedSig_OI_m_axis_dout_tdata[4],
m_axis_dout_tdata[3] = NlwRenamedSig_OI_m_axis_dout_tdata[3],
m_axis_dout_tdata[2] = NlwRenamedSig_OI_m_axis_dout_tdata[2],
m_axis_dout_tdata[1] = NlwRenamedSig_OI_m_axis_dout_tdata[1],
m_axis_dout_tdata[0] = NlwRenamedSig_OI_m_axis_dout_tdata[0],
s_axis_divisor_tready = NlwRenamedSignal_s_axis_dividend_tready,
s_axis_dividend_tready = NlwRenamedSignal_s_axis_dividend_tready;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ad (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f5 ),
.Q(m_axis_dout_tvalid)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004ac (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000003b ),
.Q(\blk00000001/sig000005f5 ),
.Q15(\NLW_blk00000001/blk000004ac_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ab (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f4 ),
.Q(\blk00000001/sig0000009d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004aa (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000192 ),
.Q(\blk00000001/sig000005f4 ),
.Q15(\NLW_blk00000001/blk000004aa_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f3 ),
.Q(\blk00000001/sig0000003b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004a8 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000003c ),
.Q(\blk00000001/sig000005f3 ),
.Q15(\NLW_blk00000001/blk000004a8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f2 ),
.Q(\blk00000001/sig0000007d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004a6 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001de ),
.Q(\blk00000001/sig000005f2 ),
.Q15(\NLW_blk00000001/blk000004a6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f1 ),
.Q(\blk00000001/sig0000007e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004a4 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001df ),
.Q(\blk00000001/sig000005f1 ),
.Q15(\NLW_blk00000001/blk000004a4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005f0 ),
.Q(\blk00000001/sig00000192 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004a2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig000005f0 ),
.Q15(\NLW_blk00000001/blk000004a2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004a1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ef ),
.Q(\blk00000001/sig0000003c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000004a0 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000003d ),
.Q(\blk00000001/sig000005ef ),
.Q15(\NLW_blk00000001/blk000004a0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000049f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ee ),
.Q(\blk00000001/sig00000546 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000049e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000055c ),
.Q(\blk00000001/sig000005ee ),
.Q15(\NLW_blk00000001/blk0000049e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000049d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ed ),
.Q(\blk00000001/sig00000547 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000049c (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000557 ),
.Q(\blk00000001/sig000005ed ),
.Q15(\NLW_blk00000001/blk0000049c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000049b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ec ),
.Q(\blk00000001/sig00000548 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000049a (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000558 ),
.Q(\blk00000001/sig000005ec ),
.Q15(\NLW_blk00000001/blk0000049a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000499 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005eb ),
.Q(\blk00000001/sig00000549 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000498 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000559 ),
.Q(\blk00000001/sig000005eb ),
.Q15(\NLW_blk00000001/blk00000498_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000497 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ea ),
.Q(\blk00000001/sig0000054a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000496 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000055a ),
.Q(\blk00000001/sig000005ea ),
.Q15(\NLW_blk00000001/blk00000496_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000495 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e9 ),
.Q(\blk00000001/sig0000054b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000494 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[0]),
.Q(\blk00000001/sig000005e9 ),
.Q15(\NLW_blk00000001/blk00000494_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000493 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e8 ),
.Q(\blk00000001/sig0000054c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000492 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[1]),
.Q(\blk00000001/sig000005e8 ),
.Q15(\NLW_blk00000001/blk00000492_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000491 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e7 ),
.Q(\blk00000001/sig0000054d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000490 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[2]),
.Q(\blk00000001/sig000005e7 ),
.Q15(\NLW_blk00000001/blk00000490_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000048f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e6 ),
.Q(\blk00000001/sig0000054e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000048e (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[3]),
.Q(\blk00000001/sig000005e6 ),
.Q15(\NLW_blk00000001/blk0000048e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000048d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e5 ),
.Q(\blk00000001/sig0000054f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000048c (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[4]),
.Q(\blk00000001/sig000005e5 ),
.Q15(\NLW_blk00000001/blk0000048c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000048b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e4 ),
.Q(\blk00000001/sig00000550 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000048a (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[5]),
.Q(\blk00000001/sig000005e4 ),
.Q15(\NLW_blk00000001/blk0000048a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000489 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e3 ),
.Q(\blk00000001/sig00000551 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000488 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[6]),
.Q(\blk00000001/sig000005e3 ),
.Q15(\NLW_blk00000001/blk00000488_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000487 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e2 ),
.Q(\blk00000001/sig00000552 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000486 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[7]),
.Q(\blk00000001/sig000005e2 ),
.Q15(\NLW_blk00000001/blk00000486_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000485 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e1 ),
.Q(\blk00000001/sig00000553 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000484 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[8]),
.Q(\blk00000001/sig000005e1 ),
.Q15(\NLW_blk00000001/blk00000484_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000483 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005e0 ),
.Q(\blk00000001/sig00000555 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000482 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[10]),
.Q(\blk00000001/sig000005e0 ),
.Q15(\NLW_blk00000001/blk00000482_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000481 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005df ),
.Q(\blk00000001/sig00000556 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000480 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[11]),
.Q(\blk00000001/sig000005df ),
.Q15(\NLW_blk00000001/blk00000480_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000047f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005de ),
.Q(\blk00000001/sig00000554 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000047e (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(NlwRenamedSig_OI_m_axis_dout_tdata[9]),
.Q(\blk00000001/sig000005de ),
.Q15(\NLW_blk00000001/blk0000047e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000047d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005dd ),
.Q(\blk00000001/sig0000045e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000047c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000044e ),
.Q(\blk00000001/sig000005dd ),
.Q15(\NLW_blk00000001/blk0000047c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000047b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005dc ),
.Q(\blk00000001/sig0000045f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000047a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000044f ),
.Q(\blk00000001/sig000005dc ),
.Q15(\NLW_blk00000001/blk0000047a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000479 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005db ),
.Q(\blk00000001/sig00000460 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000478 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000450 ),
.Q(\blk00000001/sig000005db ),
.Q15(\NLW_blk00000001/blk00000478_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000477 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005da ),
.Q(\blk00000001/sig00000461 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000476 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000451 ),
.Q(\blk00000001/sig000005da ),
.Q15(\NLW_blk00000001/blk00000476_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000475 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d9 ),
.Q(\blk00000001/sig00000462 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000474 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000452 ),
.Q(\blk00000001/sig000005d9 ),
.Q15(\NLW_blk00000001/blk00000474_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000473 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d8 ),
.Q(\blk00000001/sig00000463 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000472 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000453 ),
.Q(\blk00000001/sig000005d8 ),
.Q15(\NLW_blk00000001/blk00000472_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000471 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d7 ),
.Q(\blk00000001/sig00000464 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000470 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000454 ),
.Q(\blk00000001/sig000005d7 ),
.Q15(\NLW_blk00000001/blk00000470_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000046f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d6 ),
.Q(\blk00000001/sig00000465 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000046e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000455 ),
.Q(\blk00000001/sig000005d6 ),
.Q15(\NLW_blk00000001/blk0000046e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000046d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d5 ),
.Q(\blk00000001/sig00000466 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000046c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000456 ),
.Q(\blk00000001/sig000005d5 ),
.Q15(\NLW_blk00000001/blk0000046c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000046b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d4 ),
.Q(\blk00000001/sig00000467 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000046a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000457 ),
.Q(\blk00000001/sig000005d4 ),
.Q15(\NLW_blk00000001/blk0000046a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000469 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d3 ),
.Q(\blk00000001/sig00000468 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000468 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000458 ),
.Q(\blk00000001/sig000005d3 ),
.Q15(\NLW_blk00000001/blk00000468_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000467 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d2 ),
.Q(\blk00000001/sig00000469 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000466 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000459 ),
.Q(\blk00000001/sig000005d2 ),
.Q15(\NLW_blk00000001/blk00000466_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000465 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d1 ),
.Q(\blk00000001/sig0000046a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000464 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000045a ),
.Q(\blk00000001/sig000005d1 ),
.Q15(\NLW_blk00000001/blk00000464_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000463 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005d0 ),
.Q(\blk00000001/sig0000046b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000462 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000045b ),
.Q(\blk00000001/sig000005d0 ),
.Q15(\NLW_blk00000001/blk00000462_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000461 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005cf ),
.Q(\blk00000001/sig0000046d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000460 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000045d ),
.Q(\blk00000001/sig000005cf ),
.Q15(\NLW_blk00000001/blk00000460_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000045f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ce ),
.Q(\blk00000001/sig000003d7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000045e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003c7 ),
.Q(\blk00000001/sig000005ce ),
.Q15(\NLW_blk00000001/blk0000045e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000045d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005cd ),
.Q(\blk00000001/sig0000046c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000045c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000045c ),
.Q(\blk00000001/sig000005cd ),
.Q15(\NLW_blk00000001/blk0000045c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000045b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005cc ),
.Q(\blk00000001/sig000003d8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000045a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003c8 ),
.Q(\blk00000001/sig000005cc ),
.Q15(\NLW_blk00000001/blk0000045a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000459 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005cb ),
.Q(\blk00000001/sig000003d9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000458 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003c9 ),
.Q(\blk00000001/sig000005cb ),
.Q15(\NLW_blk00000001/blk00000458_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000457 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ca ),
.Q(\blk00000001/sig000003da )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000456 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003ca ),
.Q(\blk00000001/sig000005ca ),
.Q15(\NLW_blk00000001/blk00000456_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000455 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c9 ),
.Q(\blk00000001/sig000003db )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000454 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003cb ),
.Q(\blk00000001/sig000005c9 ),
.Q15(\NLW_blk00000001/blk00000454_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000453 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c8 ),
.Q(\blk00000001/sig000003dc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000452 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003cc ),
.Q(\blk00000001/sig000005c8 ),
.Q15(\NLW_blk00000001/blk00000452_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000451 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c7 ),
.Q(\blk00000001/sig000003dd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000450 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003cd ),
.Q(\blk00000001/sig000005c7 ),
.Q15(\NLW_blk00000001/blk00000450_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000044f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c6 ),
.Q(\blk00000001/sig000003de )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000044e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003ce ),
.Q(\blk00000001/sig000005c6 ),
.Q15(\NLW_blk00000001/blk0000044e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000044d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c5 ),
.Q(\blk00000001/sig000003df )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000044c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003cf ),
.Q(\blk00000001/sig000005c5 ),
.Q15(\NLW_blk00000001/blk0000044c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000044b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c4 ),
.Q(\blk00000001/sig000003e0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000044a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d0 ),
.Q(\blk00000001/sig000005c4 ),
.Q15(\NLW_blk00000001/blk0000044a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000449 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c3 ),
.Q(\blk00000001/sig000003e1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000448 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d1 ),
.Q(\blk00000001/sig000005c3 ),
.Q15(\NLW_blk00000001/blk00000448_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000447 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c2 ),
.Q(\blk00000001/sig000003e2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000446 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d2 ),
.Q(\blk00000001/sig000005c2 ),
.Q15(\NLW_blk00000001/blk00000446_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000445 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c1 ),
.Q(\blk00000001/sig000003e3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000444 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d3 ),
.Q(\blk00000001/sig000005c1 ),
.Q15(\NLW_blk00000001/blk00000444_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000443 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005c0 ),
.Q(\blk00000001/sig000003e4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000442 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d4 ),
.Q(\blk00000001/sig000005c0 ),
.Q15(\NLW_blk00000001/blk00000442_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000441 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005bf ),
.Q(\blk00000001/sig000003e5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000440 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d5 ),
.Q(\blk00000001/sig000005bf ),
.Q15(\NLW_blk00000001/blk00000440_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000043f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005be ),
.Q(\blk00000001/sig0000047e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000043e (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000544 ),
.Q(\blk00000001/sig000005be ),
.Q15(\NLW_blk00000001/blk0000043e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000043d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005bd ),
.Q(\blk00000001/sig000004f7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000043c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050a ),
.Q(\blk00000001/sig000005bd ),
.Q15(\NLW_blk00000001/blk0000043c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000043b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005bc ),
.Q(\blk00000001/sig000003e6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000043a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000003d6 ),
.Q(\blk00000001/sig000005bc ),
.Q15(\NLW_blk00000001/blk0000043a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000439 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005bb ),
.Q(\blk00000001/sig000004f8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000438 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050b ),
.Q(\blk00000001/sig000005bb ),
.Q15(\NLW_blk00000001/blk00000438_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000437 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ba ),
.Q(\blk00000001/sig000004f9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000436 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050c ),
.Q(\blk00000001/sig000005ba ),
.Q15(\NLW_blk00000001/blk00000436_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000435 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b9 ),
.Q(\blk00000001/sig000004fa )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000434 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050d ),
.Q(\blk00000001/sig000005b9 ),
.Q15(\NLW_blk00000001/blk00000434_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000433 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b8 ),
.Q(\blk00000001/sig000004fb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000432 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050e ),
.Q(\blk00000001/sig000005b8 ),
.Q15(\NLW_blk00000001/blk00000432_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000431 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b7 ),
.Q(\blk00000001/sig000004fc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000430 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000050f ),
.Q(\blk00000001/sig000005b7 ),
.Q15(\NLW_blk00000001/blk00000430_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000042f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b6 ),
.Q(\blk00000001/sig000004fd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000042e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000510 ),
.Q(\blk00000001/sig000005b6 ),
.Q15(\NLW_blk00000001/blk0000042e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000042d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b5 ),
.Q(\blk00000001/sig000004fe )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000042c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000511 ),
.Q(\blk00000001/sig000005b5 ),
.Q15(\NLW_blk00000001/blk0000042c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000042b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b4 ),
.Q(\blk00000001/sig000004ff )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000042a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000512 ),
.Q(\blk00000001/sig000005b4 ),
.Q15(\NLW_blk00000001/blk0000042a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000429 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b3 ),
.Q(\blk00000001/sig00000500 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000428 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000513 ),
.Q(\blk00000001/sig000005b3 ),
.Q15(\NLW_blk00000001/blk00000428_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000427 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b2 ),
.Q(\blk00000001/sig00000501 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000426 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000514 ),
.Q(\blk00000001/sig000005b2 ),
.Q15(\NLW_blk00000001/blk00000426_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000425 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b1 ),
.Q(\blk00000001/sig00000502 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000424 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000515 ),
.Q(\blk00000001/sig000005b1 ),
.Q15(\NLW_blk00000001/blk00000424_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000423 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005b0 ),
.Q(\blk00000001/sig00000503 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000422 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000516 ),
.Q(\blk00000001/sig000005b0 ),
.Q15(\NLW_blk00000001/blk00000422_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000421 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005af ),
.Q(\blk00000001/sig00000504 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000420 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000517 ),
.Q(\blk00000001/sig000005af ),
.Q15(\NLW_blk00000001/blk00000420_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000041f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ae ),
.Q(\blk00000001/sig00000505 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000041e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000518 ),
.Q(\blk00000001/sig000005ae ),
.Q15(\NLW_blk00000001/blk0000041e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000041d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ad ),
.Q(\blk00000001/sig00000507 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000041c (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000051a ),
.Q(\blk00000001/sig000005ad ),
.Q15(\NLW_blk00000001/blk0000041c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000041b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ac ),
.Q(\blk00000001/sig00000508 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000041a (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000051b ),
.Q(\blk00000001/sig000005ac ),
.Q15(\NLW_blk00000001/blk0000041a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000419 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005ab ),
.Q(\blk00000001/sig00000506 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000418 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000519 ),
.Q(\blk00000001/sig000005ab ),
.Q15(\NLW_blk00000001/blk00000418_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000417 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005aa ),
.Q(\blk00000001/sig00000509 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000416 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000051c ),
.Q(\blk00000001/sig000005aa ),
.Q15(\NLW_blk00000001/blk00000416_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000415 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a9 ),
.Q(\blk00000001/sig0000003f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000414 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000040 ),
.Q(\blk00000001/sig000005a9 ),
.Q15(\NLW_blk00000001/blk00000414_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000413 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a8 ),
.Q(\blk00000001/sig0000006a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000412 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b6 ),
.Q(\blk00000001/sig000005a8 ),
.Q15(\NLW_blk00000001/blk00000412_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000411 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a7 ),
.Q(\blk00000001/sig0000006b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000410 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b7 ),
.Q(\blk00000001/sig000005a7 ),
.Q15(\NLW_blk00000001/blk00000410_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000040f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a6 ),
.Q(\blk00000001/sig0000006c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000040e (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b8 ),
.Q(\blk00000001/sig000005a6 ),
.Q15(\NLW_blk00000001/blk0000040e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000040d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a5 ),
.Q(\blk00000001/sig0000006d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000040c (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b9 ),
.Q(\blk00000001/sig000005a5 ),
.Q15(\NLW_blk00000001/blk0000040c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000040b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a4 ),
.Q(\blk00000001/sig0000006e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000040a (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ba ),
.Q(\blk00000001/sig000005a4 ),
.Q15(\NLW_blk00000001/blk0000040a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000409 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a3 ),
.Q(\blk00000001/sig0000007f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000408 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ac ),
.Q(\blk00000001/sig000005a3 ),
.Q15(\NLW_blk00000001/blk00000408_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000407 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a2 ),
.Q(\blk00000001/sig00000080 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000406 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ad ),
.Q(\blk00000001/sig000005a2 ),
.Q15(\NLW_blk00000001/blk00000406_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000405 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a1 ),
.Q(\blk00000001/sig00000081 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000404 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ae ),
.Q(\blk00000001/sig000005a1 ),
.Q15(\NLW_blk00000001/blk00000404_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000403 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000005a0 ),
.Q(\blk00000001/sig00000082 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000402 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000af ),
.Q(\blk00000001/sig000005a0 ),
.Q15(\NLW_blk00000001/blk00000402_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000401 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059f ),
.Q(\blk00000001/sig00000083 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000400 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b0 ),
.Q(\blk00000001/sig0000059f ),
.Q15(\NLW_blk00000001/blk00000400_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003ff (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059e ),
.Q(\blk00000001/sig00000085 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003fe (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b2 ),
.Q(\blk00000001/sig0000059e ),
.Q15(\NLW_blk00000001/blk000003fe_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003fd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059d ),
.Q(\blk00000001/sig00000086 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003fc (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b3 ),
.Q(\blk00000001/sig0000059d ),
.Q15(\NLW_blk00000001/blk000003fc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003fb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059c ),
.Q(\blk00000001/sig00000084 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003fa (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b1 ),
.Q(\blk00000001/sig0000059c ),
.Q15(\NLW_blk00000001/blk000003fa_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003f9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059b ),
.Q(\blk00000001/sig00000087 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003f8 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b4 ),
.Q(\blk00000001/sig0000059b ),
.Q15(\NLW_blk00000001/blk000003f8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003f7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000059a ),
.Q(\blk00000001/sig00000088 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003f6 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000b5 ),
.Q(\blk00000001/sig0000059a ),
.Q15(\NLW_blk00000001/blk000003f6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003f5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000599 ),
.Q(\blk00000001/sig00000089 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003f4 (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000003a ),
.Q(\blk00000001/sig00000599 ),
.Q15(\NLW_blk00000001/blk000003f4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003f3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000598 ),
.Q(\blk00000001/sig00000195 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003f2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001da ),
.Q(\blk00000001/sig00000598 ),
.Q15(\NLW_blk00000001/blk000003f2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003f1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000597 ),
.Q(\blk00000001/sig00000196 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003f0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001db ),
.Q(\blk00000001/sig00000597 ),
.Q15(\NLW_blk00000001/blk000003f0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003ef (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000596 ),
.Q(\blk00000001/sig00000197 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ee (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001dc ),
.Q(\blk00000001/sig00000596 ),
.Q15(\NLW_blk00000001/blk000003ee_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003ed (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000595 ),
.Q(\blk00000001/sig00000198 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ec (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001dd ),
.Q(\blk00000001/sig00000595 ),
.Q15(\NLW_blk00000001/blk000003ec_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003eb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000594 ),
.Q(\blk00000001/sig00000199 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ea (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001ac ),
.Q(\blk00000001/sig00000594 ),
.Q15(\NLW_blk00000001/blk000003ea_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003e9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000593 ),
.Q(\blk00000001/sig0000019a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003e8 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001ad ),
.Q(\blk00000001/sig00000593 ),
.Q15(\NLW_blk00000001/blk000003e8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003e7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000592 ),
.Q(\blk00000001/sig0000019b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003e6 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001ae ),
.Q(\blk00000001/sig00000592 ),
.Q15(\NLW_blk00000001/blk000003e6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003e5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000591 ),
.Q(\blk00000001/sig0000019c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003e4 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001af ),
.Q(\blk00000001/sig00000591 ),
.Q15(\NLW_blk00000001/blk000003e4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003e3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000590 ),
.Q(\blk00000001/sig0000019d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003e2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b0 ),
.Q(\blk00000001/sig00000590 ),
.Q15(\NLW_blk00000001/blk000003e2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003e1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058f ),
.Q(\blk00000001/sig0000019e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003e0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b1 ),
.Q(\blk00000001/sig0000058f ),
.Q15(\NLW_blk00000001/blk000003e0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003df (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058e ),
.Q(\blk00000001/sig0000019f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003de (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b2 ),
.Q(\blk00000001/sig0000058e ),
.Q15(\NLW_blk00000001/blk000003de_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003dd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058d ),
.Q(\blk00000001/sig000001a1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003dc (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b4 ),
.Q(\blk00000001/sig0000058d ),
.Q15(\NLW_blk00000001/blk000003dc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003db (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058c ),
.Q(\blk00000001/sig000001a2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003da (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b5 ),
.Q(\blk00000001/sig0000058c ),
.Q15(\NLW_blk00000001/blk000003da_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003d9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058b ),
.Q(\blk00000001/sig000001a0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003d8 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b3 ),
.Q(\blk00000001/sig0000058b ),
.Q15(\NLW_blk00000001/blk000003d8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003d7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000058a ),
.Q(\blk00000001/sig000001a3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003d6 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b6 ),
.Q(\blk00000001/sig0000058a ),
.Q15(\NLW_blk00000001/blk000003d6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003d5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000589 ),
.Q(\blk00000001/sig000001a4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003d4 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b7 ),
.Q(\blk00000001/sig00000589 ),
.Q15(\NLW_blk00000001/blk000003d4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003d3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000588 ),
.Q(\blk00000001/sig000001a5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003d2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b8 ),
.Q(\blk00000001/sig00000588 ),
.Q15(\NLW_blk00000001/blk000003d2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003d1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000587 ),
.Q(\blk00000001/sig000001a6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003d0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001b9 ),
.Q(\blk00000001/sig00000587 ),
.Q15(\NLW_blk00000001/blk000003d0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003cf (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000586 ),
.Q(\blk00000001/sig000001a7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ce (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001ba ),
.Q(\blk00000001/sig00000586 ),
.Q15(\NLW_blk00000001/blk000003ce_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003cd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000585 ),
.Q(\blk00000001/sig000001a8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003cc (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001bb ),
.Q(\blk00000001/sig00000585 ),
.Q15(\NLW_blk00000001/blk000003cc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003cb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000584 ),
.Q(\blk00000001/sig000001a9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ca (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001bc ),
.Q(\blk00000001/sig00000584 ),
.Q15(\NLW_blk00000001/blk000003ca_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003c9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000583 ),
.Q(\blk00000001/sig000001aa )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003c8 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000001bd ),
.Q(\blk00000001/sig00000583 ),
.Q15(\NLW_blk00000001/blk000003c8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003c7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000582 ),
.Q(\blk00000001/sig000001de )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003c6 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000aa ),
.Q(\blk00000001/sig00000582 ),
.Q15(\NLW_blk00000001/blk000003c6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003c5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000581 ),
.Q(\blk00000001/sig000001df )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003c4 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ab ),
.Q(\blk00000001/sig00000581 ),
.Q15(\NLW_blk00000001/blk000003c4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003c3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000580 ),
.Q(\blk00000001/sig000001ab )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003c2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig00000194 ),
.Q(\blk00000001/sig00000580 ),
.Q15(\NLW_blk00000001/blk000003c2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003c1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057f ),
.Q(\blk00000001/sig000000cb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003c0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000cf ),
.Q(\blk00000001/sig0000057f ),
.Q15(\NLW_blk00000001/blk000003c0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003bf (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057e ),
.Q(\blk00000001/sig000000f6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003be (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_divisor_tdata[12]),
.Q(\blk00000001/sig0000057e ),
.Q15(\NLW_blk00000001/blk000003be_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003bd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057d ),
.Q(\blk00000001/sig000000fc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003bc (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig0000057d ),
.Q15(\NLW_blk00000001/blk000003bc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003bb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057c ),
.Q(\blk00000001/sig000000ca )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ba (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig000000ce ),
.Q(\blk00000001/sig0000057c ),
.Q15(\NLW_blk00000001/blk000003ba_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003b9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057b ),
.Q(\blk00000001/sig0000009e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003b8 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[0]),
.Q(\blk00000001/sig0000057b ),
.Q15(\NLW_blk00000001/blk000003b8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003b7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000057a ),
.Q(\blk00000001/sig0000009f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003b6 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[1]),
.Q(\blk00000001/sig0000057a ),
.Q15(\NLW_blk00000001/blk000003b6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003b5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000579 ),
.Q(\blk00000001/sig000000a0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003b4 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[2]),
.Q(\blk00000001/sig00000579 ),
.Q15(\NLW_blk00000001/blk000003b4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003b3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000578 ),
.Q(\blk00000001/sig000000a1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003b2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[3]),
.Q(\blk00000001/sig00000578 ),
.Q15(\NLW_blk00000001/blk000003b2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003b1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000577 ),
.Q(\blk00000001/sig000000a2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003b0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[4]),
.Q(\blk00000001/sig00000577 ),
.Q15(\NLW_blk00000001/blk000003b0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003af (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000576 ),
.Q(\blk00000001/sig000000a3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ae (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[5]),
.Q(\blk00000001/sig00000576 ),
.Q15(\NLW_blk00000001/blk000003ae_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003ad (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000575 ),
.Q(\blk00000001/sig000000a4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003ac (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[6]),
.Q(\blk00000001/sig00000575 ),
.Q15(\NLW_blk00000001/blk000003ac_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003ab (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000574 ),
.Q(\blk00000001/sig000000a5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003aa (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[7]),
.Q(\blk00000001/sig00000574 ),
.Q15(\NLW_blk00000001/blk000003aa_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003a9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000573 ),
.Q(\blk00000001/sig000000a6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003a8 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[8]),
.Q(\blk00000001/sig00000573 ),
.Q15(\NLW_blk00000001/blk000003a8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003a7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000572 ),
.Q(\blk00000001/sig000000a7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003a6 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[9]),
.Q(\blk00000001/sig00000572 ),
.Q15(\NLW_blk00000001/blk000003a6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003a5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000571 ),
.Q(\blk00000001/sig000000a8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003a4 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[10]),
.Q(\blk00000001/sig00000571 ),
.Q15(\NLW_blk00000001/blk000003a4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003a3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000570 ),
.Q(\blk00000001/sig000000a9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003a2 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[11]),
.Q(\blk00000001/sig00000570 ),
.Q15(\NLW_blk00000001/blk000003a2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000003a1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000056f ),
.Q(\blk00000001/sig00000237 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000003a0 (
.A0(\blk00000001/sig0000051d ),
.A1(\blk00000001/sig0000003a ),
.A2(\blk00000001/sig0000003a ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(s_axis_dividend_tdata[12]),
.Q(\blk00000001/sig0000056f ),
.Q15(\NLW_blk00000001/blk000003a0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000039f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000056e ),
.Q(\blk00000001/sig0000003d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000039e (
.A0(\blk00000001/sig0000003a ),
.A1(\blk00000001/sig0000051d ),
.A2(\blk00000001/sig0000051d ),
.A3(\blk00000001/sig0000051d ),
.CE(\blk00000001/sig0000003a ),
.CLK(aclk),
.D(\blk00000001/sig0000003e ),
.Q(\blk00000001/sig0000056e ),
.Q15(\NLW_blk00000001/blk0000039e_Q15_UNCONNECTED )
);
RAMB16BWER #(
.INITP_00 ( 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INITP_01 ( 256'h5555555555555555555555555555555555555555556AAAAAAAAAAAAAAAAAAAAA ),
.INITP_02 ( 256'h0000000000000000000000000000000000000015555555555555555555555555 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h775FD7D777D5FFF77FDFF757D557DD77F77F7FF55F755D5D7F5F75F775D5DD55 ),
.INITP_05 ( 256'h5F5D5757DDD5DFD577DF5D7D55F75F5F777D55D5DFD7FDFFD775F5FFDDDF5F5F ),
.INITP_06 ( 256'h75757DD5D5755DFD7FF7557755777D57F777DF57FD57F5D7775FFD77F7DD75DF ),
.INITP_07 ( 256'h7D7D7DD77755F5DFDD77F5F77D55F7F7F55575755FD7555F7DFD5FDFD5FF5575 ),
.INIT_00 ( 256'hC3D3C799CB64CF32D303D6D9DAB2DE8FE26FE654EA3CEE29F219F60DFA05FE01 ),
.INIT_01 ( 256'h894E8CDC906E9403979C9B389ED7A27AA621A9CAAD78B129B4DDB895BC51C010 ),
.INIT_02 ( 256'h5222557D58DB5C3C5FA16308667369E16D5270C6743D77B87B367EB7823B85C3 ),
.INIT_03 ( 256'h1E072133246227932AC82DFF3139347637B73AF93E3F418844D448234B754ECA ),
.INIT_04 ( 256'hECBEEFBFF2C2F5C8F8D0FBDBFEE901F9050C08220B3A0E561174149417B81ADE ),
.INIT_05 ( 256'hBE0EC0E6C3C1C69EC97ECC61CF45D22CD516D802DAF1DDE2E0D6E3CCE6C5E9C0 ),
.INIT_06 ( 256'h91C39476972C99E49C9E9F5BA21AA4DBA79EAA64AD2CAFF6B2C3B592B864BB37 ),
.INIT_07 ( 256'h67AF6A406CD46F697201749B773679D47C747F1781BB8461870A89B58C628F11 ),
.INIT_08 ( 256'h3FA9421B448E4704497B4BF54E7050ED536D55EE58715AF65D7E60076292651F ),
.INIT_09 ( 256'h198B1BE01E36208D22E7254227A029FF2C5F2EC23127338D35F5385F3ACB3D39 ),
.INIT_0A ( 256'hF534F76DF9A7FBE3FE21006102A204E40729096F0BB70E01104C129914E81739 ),
.INIT_0B ( 256'hD284D4A3D6C4D8E6DB0ADD2FDF56E17FE3A9E5D5E802EA31EC61EE94F0C8F2FD ),
.INIT_0C ( 256'hB15FB366B56FB779B984BB91BDA0BFB0C1C2C3D5C5E9C7FFCA17CC30CE4AD066 ),
.INIT_0D ( 256'h91AB939B958E978199769B6D9D649F5DA158A354A551A750A950AB51AD54AF59 ),
.INIT_0E ( 256'h7350752C770978E87AC77CA97E8B806F8253843A8621880A89F48BE08DCD8FBB ),
.INIT_0F ( 256'h563A580259CB5B965D625F2F60FD62CD649E667068436A176BED6DC46F9C7175 ),
.INIT_10 ( 256'h3A533C093DC03F78413142EC44A74664482249E04BA14D624F2450E852AC5472 ),
.INIT_11 ( 256'h1F8B212F22D5247B262327CC29752B202CCC2E79302731D73387353836EB389E ),
.INIT_12 ( 256'h05CF076308F80A8F0C260DBE0F5710F1128C142815C6176419031AA41C451DE7 ),
.INIT_13 ( 256'hED11EE96F01CF1A2F32AF4B2F63CF7C6F951FADEFC6BFDF9FF89011902AA043C ),
.INIT_14 ( 256'hD543D6B9D830D9A8DB21DC9ADE15DF90E10DE28AE408E588E708E889EA0BEB8D ),
.INIT_15 ( 256'hBE56BFBEC127C291C3FCC568C6D5C842C9B1CB20CC90CE01CF73D0E5D259D3CD ),
.INIT_16 ( 256'hA83EA99AAAF6AC53ADB1AF0FB06FB1CFB330B492B5F4B758B8BCBA21BB87BCEE ),
.INIT_17 ( 256'h92F19440959096E1983299849AD79C2B9D7F9ED4A02AA181A2D8A431A58AA6E4 ),
.INIT_18 ( 256'h7E637FA780EB8230837584BB8602874A889389DC8B268C718DBC8F08905591A3 ),
.INIT_19 ( 256'h6A8B6BC36CFC6E366F7070AB71E773247461759F76DD781C795C7A9D7BDE7D20 ),
.INIT_1A ( 256'h575F588D59BB5AEA5C1A5D4B5E7C5FAD60E062136347647B65B066E6681C6953 ),
.INIT_1B ( 256'h44D645FA471F4844496A4A904BB74CDF4E074F2F5059518352AE53D955055632 ),
.INIT_1C ( 256'h32EA3404351F363B3757387439913AAF3BCD3CEC3E0C3F2C404D416E429143B3 ),
.INIT_1D ( 256'h219122A323B424C725DA26ED280229162A2B2B412C582D6F2E862F9E30B731D0 ),
.INIT_1E ( 256'h10C611CE12D813E114EC15F71702180E191A1A271B351C431D511E611F702080 ),
.INIT_1F ( 256'h008101810282038404860588068B078F089309970A9C0BA20CA80DAF0EB60FBD ),
.INIT_20 ( 256'h03B80378033C030402C8028C0250021401D801980158011C00E000A000600040 ),
.INIT_21 ( 256'h073406FC06C80694065C062405EC05B405800548050C04D4049C0464042803F0 ),
.INIT_22 ( 256'h0A680A340A0409D409A00970093C090808D808A40870083C080807D407A0076C ),
.INIT_23 ( 256'h0D580D2C0D000CD00CA00C740C480C140BE80BBC0B880B580B280AFC0ACC0A98 ),
.INIT_24 ( 256'h100C0FE40FB80F900F680F380F0C0EE40EBC0E900E600E340E0C0DE00DB00D84 ),
.INIT_25 ( 256'h128812641240121811EC11C811A411781150112C110010D810B41088105C1034 ),
.INIT_26 ( 256'h14D814B81490146C144C1424140013DC13B4139013701348132012FC12D812B0 ),
.INIT_27 ( 256'h16F816D816B81698167416541634161015EC15CC15AC158415641544151C14F8 ),
.INIT_28 ( 256'h18F418D818B8189818781858183C181C17FC17DC17BC179C177C175C173C171C ),
.INIT_29 ( 256'h1ACC1AAC1A941A781A581A381A1C1A0419E419C419AC198C196C195019301910 ),
.INIT_2A ( 256'h1C801C681C4C1C301C141BFC1BE41BC41BA81B901B741B581B3C1B201B001AE8 ),
.INIT_2B ( 256'h1E181E001DE81DD01DB81D9C1D841D6C1D501D381D201D041CE81CCC1CB81C9C ),
.INIT_2C ( 256'h1F981F801F681F541F3C1F241F081EF01EDC1EC41EAC1E941E7C1E641E4C1E34 ),
.INIT_2D ( 256'h20FC20E820D020BC20A42090207C2064204C20342020200C1FF41FDC1FC41FAC ),
.INIT_2E ( 256'h224C22382220221021F821E421D021BC21A82190217C21682154213C21282110 ),
.INIT_2F ( 256'h23842374235C234C233C2324231022FC22E822D822C422B0229C22882274225C ),
.INIT_30 ( 256'h24A8249C24882474246424502440242C241C240823F423E423D023C023AC2394 ),
.INIT_31 ( 256'h25C025B025A02590257C256C255C2548253825282514250424F424E024D024BC ),
.INIT_32 ( 256'h26C826B826A4269426882678266426542648263426242614260025F425E425D0 ),
.INIT_33 ( 256'h27B827AC27A0279027802770276027542744273027242714270426F826E426D4 ),
.INIT_34 ( 256'h28A4289828882878286C286028502840283028242814280427F827E827DC27CC ),
.INIT_35 ( 256'h297C2974296829582948293C293029202914290828F828E828DC28D028C028B0 ),
.INIT_36 ( 256'h2A502A442A382A282A1C2A102A0429F829E829DC29D029C029B429A8299C298C ),
.INIT_37 ( 256'h2B142B082AFC2AF02AE42AD82ACC2AC02AB42AA42A9C2A902A802A742A682A5C ),
.INIT_38 ( 256'h2BCC2BC42BB82BAC2BA42B982B882B7C2B742B682B582B502B442B382B2C2B20 ),
.INIT_39 ( 256'h2C802C742C6C2C602C542C482C3C2C342C282C1C2C142C082BFC2BF02BE42BD8 ),
.INIT_3A ( 256'h2D282D1C2D142D082CFC2CF42CEC2CE02CD42CC82CC02CB82CA82C9C2C942C8C ),
.INIT_3B ( 256'h2DC82DBC2DB42DA82DA02D982D882D802D7C2D702D642D582D4C2D482D3C2D30 ),
.INIT_3C ( 256'h2E602E542E4C2E442E382E302E282E1C2E142E0C2E002DF42DF02DE42DD82DD4 ),
.INIT_3D ( 256'h2EEC2EE82EE02ED42ECC2EC02EB82EB42EA82E9C2E942E8C2E842E7C2E702E68 ),
.INIT_3E ( 256'h2F782F702F682F602F542F502F482F3C2F342F2C2F242F1C2F102F082F042EF8 ),
.INIT_3F ( 256'h2FF82FF42FEC2FE42FDC2FD42FCC2FC42FBC2FB42FAC2FA02F982F942F8C2F80 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 18 ),
.DATA_WIDTH_B ( 18 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000039d (
.REGCEA(\blk00000001/sig0000051d ),
.CLKA(aclk),
.ENB(\blk00000001/sig0000003a ),
.RSTB(\blk00000001/sig0000051d ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig0000051d ),
.RSTA(\blk00000001/sig0000051d ),
.ENA(\blk00000001/sig0000003a ),
.DIPA({\NLW_blk00000001/blk0000039d_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIPA<2>_UNCONNECTED , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d }),
.WEA({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.DOA({\NLW_blk00000001/blk0000039d_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOA<16>_UNCONNECTED , \blk00000001/sig000001bb ,
\blk00000001/sig000001ba , \blk00000001/sig000001b9 , \blk00000001/sig000001b8 , \blk00000001/sig000001b7 , \blk00000001/sig000001b6 ,
\blk00000001/sig000001b5 , \blk00000001/sig000001b4 , \blk00000001/sig000001b3 , \blk00000001/sig000001b2 , \blk00000001/sig000001b1 ,
\blk00000001/sig000001b0 , \blk00000001/sig000001af , \blk00000001/sig000001ae , \blk00000001/sig000001ad , \blk00000001/sig000001ac }),
.ADDRA({\blk00000001/sig0000051d , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 ,
\blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af , \blk00000001/sig000000ae , \blk00000001/sig000000ad ,
\NLW_blk00000001/blk0000039d_ADDRA<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_ADDRA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_ADDRA<1>_UNCONNECTED , \NLW_blk00000001/blk0000039d_ADDRA<0>_UNCONNECTED }),
.ADDRB({\blk00000001/sig0000003a , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 ,
\blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af , \blk00000001/sig000000ae , \blk00000001/sig000000ad ,
\NLW_blk00000001/blk0000039d_ADDRB<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_ADDRB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_ADDRB<1>_UNCONNECTED , \NLW_blk00000001/blk0000039d_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk00000001/blk0000039d_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIB<16>_UNCONNECTED , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.DOPA({\NLW_blk00000001/blk0000039d_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOPA<2>_UNCONNECTED , \blk00000001/sig000001bd ,
\blk00000001/sig000001bc }),
.DIPB({\NLW_blk00000001/blk0000039d_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIPB<2>_UNCONNECTED , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d }),
.DOPB({\NLW_blk00000001/blk0000039d_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOPB<2>_UNCONNECTED , \blk00000001/sig000001dd ,
\blk00000001/sig000001dc }),
.DOB({\NLW_blk00000001/blk0000039d_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DOB<16>_UNCONNECTED , \blk00000001/sig000001db ,
\blk00000001/sig000001da , \blk00000001/sig000001d9 , \blk00000001/sig000001d8 , \blk00000001/sig000001d7 , \blk00000001/sig000001d6 ,
\blk00000001/sig000001d5 , \blk00000001/sig000001d4 , \blk00000001/sig000001d3 , \blk00000001/sig000001d2 , \blk00000001/sig000001d1 ,
\blk00000001/sig000001d0 , \blk00000001/sig000001cf , \blk00000001/sig000001ce , \blk00000001/sig000001cd , \blk00000001/sig000001cc }),
.WEB({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.DIA({\NLW_blk00000001/blk0000039d_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000039d_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000039d_DIA<16>_UNCONNECTED , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d })
);
INV \blk00000001/blk0000039c (
.I(\blk00000001/sig00000040 ),
.O(\blk00000001/sig0000055b )
);
INV \blk00000001/blk0000039b (
.I(\blk00000001/sig0000006e ),
.O(\blk00000001/sig0000026c )
);
INV \blk00000001/blk0000039a (
.I(\blk00000001/sig0000006d ),
.O(\blk00000001/sig0000026b )
);
INV \blk00000001/blk00000399 (
.I(\blk00000001/sig0000006c ),
.O(\blk00000001/sig0000026a )
);
INV \blk00000001/blk00000398 (
.I(\blk00000001/sig0000006b ),
.O(\blk00000001/sig00000269 )
);
INV \blk00000001/blk00000397 (
.I(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000268 )
);
INV \blk00000001/blk00000396 (
.I(\blk00000001/sig000000ac ),
.O(\blk00000001/sig00000194 )
);
INV \blk00000001/blk00000395 (
.I(\blk00000001/sig0000003d ),
.O(NlwRenamedSignal_s_axis_dividend_tready)
);
LUT4 #(
.INIT ( 16'hA280 ))
\blk00000001/blk00000394 (
.I0(\blk00000001/sig0000006b ),
.I1(\blk00000001/sig0000006a ),
.I2(\blk00000001/sig0000009f ),
.I3(\blk00000001/sig0000009e ),
.O(\blk00000001/sig00000229 )
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
\blk00000001/blk00000393 (
.I0(\blk00000001/sig0000006b ),
.I1(\blk00000001/sig0000006a ),
.I2(\blk00000001/sig000000a9 ),
.I3(\blk00000001/sig000000a8 ),
.I4(\blk00000001/sig00000237 ),
.O(\blk00000001/sig00000235 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000392 (
.I0(\blk00000001/sig0000006b ),
.I1(\blk00000001/sig0000006a ),
.I2(\blk00000001/sig0000009e ),
.O(\blk00000001/sig00000228 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000391 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000260 ),
.I3(\blk00000001/sig0000025c ),
.O(\blk00000001/sig00000213 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000390 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025f ),
.I3(\blk00000001/sig0000025b ),
.O(\blk00000001/sig00000212 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk0000038f (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025e ),
.I3(\blk00000001/sig0000025a ),
.O(\blk00000001/sig00000211 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk0000038e (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025d ),
.I3(\blk00000001/sig00000259 ),
.O(\blk00000001/sig00000210 )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000038d (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025c ),
.O(\blk00000001/sig0000020f )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000038c (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025b ),
.O(\blk00000001/sig0000020e )
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
\blk00000001/blk0000038b (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000267 ),
.I3(\blk00000001/sig00000263 ),
.I4(\blk00000001/sig00000227 ),
.O(\blk00000001/sig00000222 )
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
\blk00000001/blk0000038a (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000266 ),
.I3(\blk00000001/sig00000262 ),
.I4(\blk00000001/sig00000227 ),
.O(\blk00000001/sig00000221 )
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
\blk00000001/blk00000389 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000265 ),
.I3(\blk00000001/sig00000261 ),
.I4(\blk00000001/sig00000227 ),
.O(\blk00000001/sig00000220 )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk00000388 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025a ),
.O(\blk00000001/sig0000020d )
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
\blk00000001/blk00000387 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000264 ),
.I3(\blk00000001/sig00000260 ),
.I4(\blk00000001/sig00000227 ),
.O(\blk00000001/sig0000021f )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk00000386 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000259 ),
.O(\blk00000001/sig0000020c )
);
LUT4 #(
.INIT ( 16'hABA8 ))
\blk00000001/blk00000385 (
.I0(\blk00000001/sig00000237 ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig0000006a ),
.I3(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig00000236 )
);
LUT4 #(
.INIT ( 16'hEA2A ))
\blk00000001/blk00000384 (
.I0(\blk00000001/sig00000227 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000258 ),
.I3(\blk00000001/sig00000267 ),
.O(\blk00000001/sig00000226 )
);
LUT4 #(
.INIT ( 16'hEA2A ))
\blk00000001/blk00000383 (
.I0(\blk00000001/sig00000227 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000258 ),
.I3(\blk00000001/sig00000266 ),
.O(\blk00000001/sig00000225 )
);
LUT4 #(
.INIT ( 16'hEA2A ))
\blk00000001/blk00000382 (
.I0(\blk00000001/sig00000227 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000258 ),
.I3(\blk00000001/sig00000265 ),
.O(\blk00000001/sig00000224 )
);
LUT4 #(
.INIT ( 16'hEA2A ))
\blk00000001/blk00000381 (
.I0(\blk00000001/sig00000227 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000258 ),
.I3(\blk00000001/sig00000264 ),
.O(\blk00000001/sig00000223 )
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
\blk00000001/blk00000380 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d8 ),
.I3(\blk00000001/sig000000d4 ),
.I4(\blk00000001/sig00000126 ),
.I5(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig00000145 )
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
\blk00000001/blk0000037f (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d9 ),
.I3(\blk00000001/sig000000d5 ),
.I4(\blk00000001/sig00000126 ),
.I5(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig00000144 )
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
\blk00000001/blk0000037e (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000da ),
.I3(\blk00000001/sig000000d6 ),
.I4(\blk00000001/sig00000126 ),
.I5(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig00000143 )
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
\blk00000001/blk0000037d (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000db ),
.I3(\blk00000001/sig000000d7 ),
.I4(\blk00000001/sig00000126 ),
.I5(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig00000142 )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000037c (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig0000014d )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000037b (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig0000014c )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000037a (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig0000014b )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk00000379 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig0000014a )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000378 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d6 ),
.I3(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig00000147 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000377 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d7 ),
.I3(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig00000146 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000376 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d4 ),
.I3(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig00000149 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk00000375 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d5 ),
.I3(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig00000148 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000374 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004b3 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002bf )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000373 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004b2 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002be )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000372 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004b1 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002bd )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000371 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004b0 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002bc )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000370 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004af ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002bb )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004ae ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002ba )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004ad ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b9 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004ac ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b8 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004ab ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b7 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004aa ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b6 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk0000036a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a9 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b5 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000369 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a8 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b4 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000368 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a7 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b3 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000367 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a6 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b2 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000366 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a5 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b1 )
);
LUT4 #(
.INIT ( 16'hE444 ))
\blk00000001/blk00000365 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a4 ),
.I2(\blk00000001/sig0000008a ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002b0 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000364 (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a5 ),
.I3(\blk00000001/sig000000a7 ),
.I4(\blk00000001/sig000000a4 ),
.I5(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig00000231 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000363 (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a4 ),
.I3(\blk00000001/sig000000a6 ),
.I4(\blk00000001/sig000000a3 ),
.I5(\blk00000001/sig000000a5 ),
.O(\blk00000001/sig00000230 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000362 (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a3 ),
.I3(\blk00000001/sig000000a5 ),
.I4(\blk00000001/sig000000a2 ),
.I5(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig0000022f )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000361 (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a2 ),
.I3(\blk00000001/sig000000a4 ),
.I4(\blk00000001/sig000000a1 ),
.I5(\blk00000001/sig000000a3 ),
.O(\blk00000001/sig0000022e )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000360 (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a1 ),
.I3(\blk00000001/sig000000a3 ),
.I4(\blk00000001/sig000000a0 ),
.I5(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig0000022d )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000035f (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a0 ),
.I3(\blk00000001/sig000000a2 ),
.I4(\blk00000001/sig0000009f ),
.I5(\blk00000001/sig000000a1 ),
.O(\blk00000001/sig0000022c )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000035e (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig0000009f ),
.I3(\blk00000001/sig000000a1 ),
.I4(\blk00000001/sig0000009e ),
.I5(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig0000022b )
);
LUT5 #(
.INIT ( 32'hEC64A820 ))
\blk00000001/blk0000035d (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig0000009e ),
.I3(\blk00000001/sig000000a0 ),
.I4(\blk00000001/sig0000009f ),
.O(\blk00000001/sig0000022a )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000035c (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a8 ),
.I3(\blk00000001/sig00000237 ),
.I4(\blk00000001/sig000000a7 ),
.I5(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig00000234 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000035b (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a7 ),
.I3(\blk00000001/sig000000a9 ),
.I4(\blk00000001/sig000000a6 ),
.I5(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig00000233 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000035a (
.I0(\blk00000001/sig0000006a ),
.I1(\blk00000001/sig0000006b ),
.I2(\blk00000001/sig000000a6 ),
.I3(\blk00000001/sig000000a8 ),
.I4(\blk00000001/sig000000a5 ),
.I5(\blk00000001/sig000000a7 ),
.O(\blk00000001/sig00000232 )
);
LUT5 #(
.INIT ( 32'h73625140 ))
\blk00000001/blk00000359 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025e ),
.I3(\blk00000001/sig00000262 ),
.I4(\blk00000001/sig0000025a ),
.O(\blk00000001/sig00000215 )
);
LUT5 #(
.INIT ( 32'h73625140 ))
\blk00000001/blk00000358 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025d ),
.I3(\blk00000001/sig00000261 ),
.I4(\blk00000001/sig00000259 ),
.O(\blk00000001/sig00000214 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000357 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000267 ),
.I3(\blk00000001/sig0000025f ),
.I4(\blk00000001/sig00000227 ),
.I5(\blk00000001/sig00000263 ),
.O(\blk00000001/sig0000021e )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000356 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000266 ),
.I3(\blk00000001/sig0000025e ),
.I4(\blk00000001/sig00000227 ),
.I5(\blk00000001/sig00000262 ),
.O(\blk00000001/sig0000021d )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000355 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000265 ),
.I3(\blk00000001/sig0000025d ),
.I4(\blk00000001/sig00000227 ),
.I5(\blk00000001/sig00000261 ),
.O(\blk00000001/sig0000021c )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000354 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000264 ),
.I3(\blk00000001/sig0000025c ),
.I4(\blk00000001/sig00000227 ),
.I5(\blk00000001/sig00000260 ),
.O(\blk00000001/sig0000021b )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000353 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000263 ),
.I3(\blk00000001/sig0000025b ),
.I4(\blk00000001/sig00000267 ),
.I5(\blk00000001/sig0000025f ),
.O(\blk00000001/sig0000021a )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000352 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000262 ),
.I3(\blk00000001/sig0000025a ),
.I4(\blk00000001/sig00000266 ),
.I5(\blk00000001/sig0000025e ),
.O(\blk00000001/sig00000219 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000351 (
.I0(\blk00000001/sig00000258 ),
.I1(\blk00000001/sig00000256 ),
.I2(\blk00000001/sig00000261 ),
.I3(\blk00000001/sig00000259 ),
.I4(\blk00000001/sig00000265 ),
.I5(\blk00000001/sig0000025d ),
.O(\blk00000001/sig00000218 )
);
LUT5 #(
.INIT ( 32'h73625140 ))
\blk00000001/blk00000350 (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig00000260 ),
.I3(\blk00000001/sig00000264 ),
.I4(\blk00000001/sig0000025c ),
.O(\blk00000001/sig00000217 )
);
LUT5 #(
.INIT ( 32'h73625140 ))
\blk00000001/blk0000034f (
.I0(\blk00000001/sig00000256 ),
.I1(\blk00000001/sig00000258 ),
.I2(\blk00000001/sig0000025f ),
.I3(\blk00000001/sig00000263 ),
.I4(\blk00000001/sig0000025b ),
.O(\blk00000001/sig00000216 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000034e (
.I0(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000056d )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000034d (
.I0(\blk00000001/sig0000015c ),
.O(\blk00000001/sig0000056c )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000034c (
.I0(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000056b )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000034b (
.I0(\blk00000001/sig0000015e ),
.O(\blk00000001/sig0000056a )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000034a (
.I0(\blk00000001/sig0000015f ),
.O(\blk00000001/sig00000569 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000349 (
.I0(\blk00000001/sig00000160 ),
.O(\blk00000001/sig00000568 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000348 (
.I0(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000567 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000347 (
.I0(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000566 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000346 (
.I0(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000565 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000345 (
.I0(\blk00000001/sig00000164 ),
.O(\blk00000001/sig00000564 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000344 (
.I0(\blk00000001/sig00000165 ),
.O(\blk00000001/sig00000563 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000343 (
.I0(\blk00000001/sig00000166 ),
.O(\blk00000001/sig00000562 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000342 (
.I0(\blk00000001/sig0000016b ),
.O(\blk00000001/sig00000561 )
);
FD \blk00000001/blk00000341 (
.C(aclk),
.D(\blk00000001/sig000000f7 ),
.Q(\blk00000001/sig000000b6 )
);
FD \blk00000001/blk00000340 (
.C(aclk),
.D(\blk00000001/sig000000f8 ),
.Q(\blk00000001/sig000000b7 )
);
FD \blk00000001/blk0000033f (
.C(aclk),
.D(\blk00000001/sig000000f9 ),
.Q(\blk00000001/sig000000b8 )
);
FD \blk00000001/blk0000033e (
.C(aclk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig000000b9 )
);
FD \blk00000001/blk0000033d (
.C(aclk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig000000ba )
);
LUT6 #(
.INIT ( 64'h0404040037373733 ))
\blk00000001/blk0000033c (
.I0(\blk00000001/sig000000d9 ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig000000d8 ),
.I3(\blk00000001/sig000000d6 ),
.I4(\blk00000001/sig000000d7 ),
.I5(\blk00000001/sig00000560 ),
.O(\blk00000001/sig00000130 )
);
LUT3 #(
.INIT ( 8'hF1 ))
\blk00000001/blk0000033b (
.I0(\blk00000001/sig000000db ),
.I1(\blk00000001/sig000000da ),
.I2(\blk00000001/sig000000dc ),
.O(\blk00000001/sig00000560 )
);
LUT6 #(
.INIT ( 64'h2222020077775755 ))
\blk00000001/blk0000033a (
.I0(\blk00000001/sig00000127 ),
.I1(\blk00000001/sig000000d9 ),
.I2(\blk00000001/sig000000d7 ),
.I3(\blk00000001/sig000000d6 ),
.I4(\blk00000001/sig000000d8 ),
.I5(\blk00000001/sig0000055f ),
.O(\blk00000001/sig00000131 )
);
LUT3 #(
.INIT ( 8'h45 ))
\blk00000001/blk00000339 (
.I0(\blk00000001/sig000000dc ),
.I1(\blk00000001/sig000000db ),
.I2(\blk00000001/sig000000da ),
.O(\blk00000001/sig0000055f )
);
LUT6 #(
.INIT ( 64'h10111010DCDDDCDC ))
\blk00000001/blk00000338 (
.I0(\blk00000001/sig000000d5 ),
.I1(\blk00000001/sig00000126 ),
.I2(\blk00000001/sig000000d4 ),
.I3(\blk00000001/sig000000d3 ),
.I4(\blk00000001/sig000000d2 ),
.I5(\blk00000001/sig0000055e ),
.O(\blk00000001/sig0000012f )
);
LUT2 #(
.INIT ( 4'hB ))
\blk00000001/blk00000337 (
.I0(\blk00000001/sig000000d1 ),
.I1(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig0000055e )
);
LUT6 #(
.INIT ( 64'h4444441444444444 ))
\blk00000001/blk00000336 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig00000101 ),
.I2(\blk00000001/sig000000fd ),
.I3(\blk00000001/sig00000167 ),
.I4(\blk00000001/sig0000055d ),
.I5(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000000fb )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk00000335 (
.I0(\blk00000001/sig00000100 ),
.I1(\blk00000001/sig000000ff ),
.O(\blk00000001/sig0000055d )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000334 (
.I0(\blk00000001/sig00000040 ),
.I1(\blk00000001/sig00000546 ),
.I2(\blk00000001/sig0000009d ),
.O(\blk00000001/sig00000545 )
);
LUT2 #(
.INIT ( 4'hB ))
\blk00000001/blk00000333 (
.I0(\blk00000001/sig0000009c ),
.I1(\blk00000001/sig0000003c ),
.O(\blk00000001/sig0000031c )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000332 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000063 ),
.O(\blk00000001/sig000002aa )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000331 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000062 ),
.O(\blk00000001/sig000002a9 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000330 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000061 ),
.O(\blk00000001/sig000002a8 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000060 ),
.O(\blk00000001/sig000002a7 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005f ),
.O(\blk00000001/sig000002a6 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005e ),
.O(\blk00000001/sig000002a5 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005d ),
.O(\blk00000001/sig000002a4 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005c ),
.O(\blk00000001/sig000002a3 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000032a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005b ),
.O(\blk00000001/sig000002a2 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000329 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000068 ),
.O(\blk00000001/sig000002af )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000328 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000067 ),
.O(\blk00000001/sig000002ae )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000327 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000066 ),
.O(\blk00000001/sig000002ad )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000326 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000065 ),
.O(\blk00000001/sig000002ac )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000325 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000064 ),
.O(\blk00000001/sig000002ab )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000324 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig0000005a ),
.O(\blk00000001/sig000002a1 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000323 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000053 ),
.O(\blk00000001/sig000002f5 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000322 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000052 ),
.O(\blk00000001/sig000002f4 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000321 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000051 ),
.O(\blk00000001/sig000002f3 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000320 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000059 ),
.O(\blk00000001/sig000002fb )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000031f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000058 ),
.O(\blk00000001/sig000002fa )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000031e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000057 ),
.O(\blk00000001/sig000002f9 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000031d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000056 ),
.O(\blk00000001/sig000002f8 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000031c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000055 ),
.O(\blk00000001/sig000002f7 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000031b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000054 ),
.O(\blk00000001/sig000002f6 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000031a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034a ),
.O(\blk00000001/sig00000297 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000319 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000349 ),
.O(\blk00000001/sig00000296 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000318 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000348 ),
.O(\blk00000001/sig00000295 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000317 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000347 ),
.O(\blk00000001/sig00000294 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000316 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000346 ),
.O(\blk00000001/sig00000293 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000315 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000345 ),
.O(\blk00000001/sig00000292 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000314 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000344 ),
.O(\blk00000001/sig00000291 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000313 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000343 ),
.O(\blk00000001/sig00000290 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000312 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000342 ),
.O(\blk00000001/sig0000028f )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000311 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000353 ),
.O(\blk00000001/sig000002a0 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000310 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000352 ),
.O(\blk00000001/sig0000029f )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000351 ),
.O(\blk00000001/sig0000029e )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000350 ),
.O(\blk00000001/sig0000029d )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034f ),
.O(\blk00000001/sig0000029c )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034e ),
.O(\blk00000001/sig0000029b )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034d ),
.O(\blk00000001/sig0000029a )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000030a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034c ),
.O(\blk00000001/sig00000299 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000309 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000034b ),
.O(\blk00000001/sig00000298 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000308 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000341 ),
.O(\blk00000001/sig0000028e )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000307 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e0 ),
.I2(\blk00000001/sig00000076 ),
.O(\blk00000001/sig00000315 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000306 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003df ),
.I2(\blk00000001/sig00000075 ),
.O(\blk00000001/sig00000314 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000305 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003de ),
.I2(\blk00000001/sig00000074 ),
.O(\blk00000001/sig00000313 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000304 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003dd ),
.I2(\blk00000001/sig00000073 ),
.O(\blk00000001/sig00000312 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000303 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003dc ),
.I2(\blk00000001/sig00000072 ),
.O(\blk00000001/sig00000311 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000302 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003db ),
.I2(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000310 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000301 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003da ),
.I2(\blk00000001/sig00000070 ),
.O(\blk00000001/sig0000030f )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000300 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003d9 ),
.I2(\blk00000001/sig0000006f ),
.O(\blk00000001/sig0000030e )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ff (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003d8 ),
.O(\blk00000001/sig0000030d )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002fe (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e6 ),
.I2(\blk00000001/sig0000007c ),
.O(\blk00000001/sig0000031b )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002fd (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e5 ),
.I2(\blk00000001/sig0000007b ),
.O(\blk00000001/sig0000031a )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002fc (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e4 ),
.I2(\blk00000001/sig0000007a ),
.O(\blk00000001/sig00000319 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002fb (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e3 ),
.I2(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000318 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002fa (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e2 ),
.I2(\blk00000001/sig00000078 ),
.O(\blk00000001/sig00000317 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002f9 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003e1 ),
.I2(\blk00000001/sig00000077 ),
.O(\blk00000001/sig00000316 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f8 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig000003d7 ),
.O(\blk00000001/sig0000030c )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f7 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000467 ),
.O(\blk00000001/sig00000305 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f6 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000466 ),
.O(\blk00000001/sig00000304 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f5 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000465 ),
.O(\blk00000001/sig00000303 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f4 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000464 ),
.O(\blk00000001/sig00000302 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f3 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000463 ),
.O(\blk00000001/sig00000301 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f2 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000462 ),
.O(\blk00000001/sig00000300 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f1 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000461 ),
.O(\blk00000001/sig000002ff )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002f0 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000460 ),
.O(\blk00000001/sig000002fe )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ef (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000045f ),
.O(\blk00000001/sig000002fd )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ee (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000046d ),
.O(\blk00000001/sig0000030b )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ed (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000046c ),
.O(\blk00000001/sig0000030a )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ec (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000046b ),
.O(\blk00000001/sig00000309 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002eb (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000046a ),
.O(\blk00000001/sig00000308 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ea (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000469 ),
.O(\blk00000001/sig00000307 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002e9 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig00000468 ),
.O(\blk00000001/sig00000306 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002e8 (
.I0(\blk00000001/sig0000047e ),
.I1(\blk00000001/sig0000045e ),
.O(\blk00000001/sig000002fc )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e7 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000500 ),
.I2(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000538 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e6 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004ff ),
.I2(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000537 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e5 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004fe ),
.I2(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000536 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e4 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004fd ),
.I2(\blk00000001/sig00000090 ),
.O(\blk00000001/sig00000535 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e3 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004fc ),
.I2(\blk00000001/sig0000008f ),
.O(\blk00000001/sig00000534 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e2 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004fb ),
.I2(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000533 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e1 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004fa ),
.I2(\blk00000001/sig0000008d ),
.O(\blk00000001/sig00000532 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002e0 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004f9 ),
.I2(\blk00000001/sig0000008c ),
.O(\blk00000001/sig00000531 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002df (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004f8 ),
.I2(\blk00000001/sig0000008b ),
.O(\blk00000001/sig00000530 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002de (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000509 ),
.I2(\blk00000001/sig0000009c ),
.O(\blk00000001/sig00000541 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002dd (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000508 ),
.I2(\blk00000001/sig0000009b ),
.O(\blk00000001/sig00000540 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002dc (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000507 ),
.I2(\blk00000001/sig0000009a ),
.O(\blk00000001/sig0000053f )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002db (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000506 ),
.I2(\blk00000001/sig00000099 ),
.O(\blk00000001/sig0000053e )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002da (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000505 ),
.I2(\blk00000001/sig00000098 ),
.O(\blk00000001/sig0000053d )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002d9 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000504 ),
.I2(\blk00000001/sig00000097 ),
.O(\blk00000001/sig0000053c )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002d8 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000503 ),
.I2(\blk00000001/sig00000096 ),
.O(\blk00000001/sig0000053b )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002d7 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000502 ),
.I2(\blk00000001/sig00000095 ),
.O(\blk00000001/sig0000053a )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002d6 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000501 ),
.I2(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000539 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002d5 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004f7 ),
.I2(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000542 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002d4 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000456 ),
.O(\blk00000001/sig000002eb )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002d3 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000455 ),
.O(\blk00000001/sig000002ea )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002d2 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000454 ),
.O(\blk00000001/sig000002e9 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002d1 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000453 ),
.O(\blk00000001/sig000002e8 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002d0 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000452 ),
.O(\blk00000001/sig000002e7 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002cf (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000451 ),
.O(\blk00000001/sig000002e6 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ce (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000450 ),
.O(\blk00000001/sig000002e5 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002cd (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000044f ),
.O(\blk00000001/sig000002e4 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002cc (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000044e ),
.O(\blk00000001/sig000002e3 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002cb (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000045d ),
.O(\blk00000001/sig000002f2 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ca (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000045c ),
.O(\blk00000001/sig000002f1 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002c9 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000045b ),
.O(\blk00000001/sig000002f0 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002c8 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000045a ),
.O(\blk00000001/sig000002ef )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002c7 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000459 ),
.O(\blk00000001/sig000002ee )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002c6 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000458 ),
.O(\blk00000001/sig000002ed )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002c5 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000457 ),
.O(\blk00000001/sig000002ec )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002c4 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003cf ),
.I2(\blk00000001/sig00000062 ),
.O(\blk00000001/sig000002c8 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002c3 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003ce ),
.I2(\blk00000001/sig00000061 ),
.O(\blk00000001/sig000002c7 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002c2 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003cd ),
.I2(\blk00000001/sig00000060 ),
.O(\blk00000001/sig000002c6 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002c1 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003cc ),
.I2(\blk00000001/sig0000005f ),
.O(\blk00000001/sig000002c5 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002c0 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003cb ),
.I2(\blk00000001/sig0000005e ),
.O(\blk00000001/sig000002c4 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002bf (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003ca ),
.I2(\blk00000001/sig0000005d ),
.O(\blk00000001/sig000002c3 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002be (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003c9 ),
.I2(\blk00000001/sig0000005c ),
.O(\blk00000001/sig000002c2 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002bd (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003c8 ),
.I2(\blk00000001/sig0000005b ),
.O(\blk00000001/sig000002c1 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002bc (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003c7 ),
.I2(\blk00000001/sig0000005a ),
.O(\blk00000001/sig000002c0 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002bb (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d6 ),
.I2(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000002cf )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002ba (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d5 ),
.I2(\blk00000001/sig00000068 ),
.O(\blk00000001/sig000002ce )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002b9 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d4 ),
.I2(\blk00000001/sig00000067 ),
.O(\blk00000001/sig000002cd )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002b8 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d3 ),
.I2(\blk00000001/sig00000066 ),
.O(\blk00000001/sig000002cc )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002b7 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d2 ),
.I2(\blk00000001/sig00000065 ),
.O(\blk00000001/sig000002cb )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002b6 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d1 ),
.I2(\blk00000001/sig00000064 ),
.O(\blk00000001/sig000002ca )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002b5 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003d0 ),
.I2(\blk00000001/sig00000063 ),
.O(\blk00000001/sig000002c9 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002b4 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049b ),
.O(\blk00000001/sig00000338 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002b3 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049a ),
.O(\blk00000001/sig00000337 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002b2 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000499 ),
.O(\blk00000001/sig00000336 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002b1 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000498 ),
.O(\blk00000001/sig00000335 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002b0 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000497 ),
.O(\blk00000001/sig00000334 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002af (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000496 ),
.O(\blk00000001/sig00000333 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ae (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000495 ),
.O(\blk00000001/sig00000332 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ad (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000494 ),
.O(\blk00000001/sig00000331 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ac (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000493 ),
.O(\blk00000001/sig00000330 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002ab (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a3 ),
.O(\blk00000001/sig00000340 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002aa (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a2 ),
.O(\blk00000001/sig0000033f )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a9 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a1 ),
.O(\blk00000001/sig0000033e )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a8 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000004a0 ),
.O(\blk00000001/sig0000033d )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a7 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049f ),
.O(\blk00000001/sig0000033c )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a6 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049e ),
.O(\blk00000001/sig0000033b )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a5 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049d ),
.O(\blk00000001/sig0000033a )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a4 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000049c ),
.O(\blk00000001/sig00000339 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000002a3 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000492 ),
.O(\blk00000001/sig0000032f )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002a2 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004a ),
.I2(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000326 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002a1 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000049 ),
.I2(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000325 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk000002a0 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000048 ),
.I2(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000324 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000047 ),
.I2(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000323 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000046 ),
.I2(\blk00000001/sig00000090 ),
.O(\blk00000001/sig00000322 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000045 ),
.I2(\blk00000001/sig0000008f ),
.O(\blk00000001/sig00000321 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000044 ),
.I2(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000320 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000043 ),
.I2(\blk00000001/sig0000008d ),
.O(\blk00000001/sig0000031f )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000029a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000042 ),
.I2(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000031e )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000299 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000050 ),
.I2(\blk00000001/sig0000009c ),
.O(\blk00000001/sig0000032e )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000298 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000050 ),
.I2(\blk00000001/sig0000009b ),
.O(\blk00000001/sig0000032d )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000297 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000050 ),
.I2(\blk00000001/sig0000009a ),
.O(\blk00000001/sig0000032c )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000296 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004f ),
.I2(\blk00000001/sig00000099 ),
.O(\blk00000001/sig0000032b )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000295 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004e ),
.I2(\blk00000001/sig00000098 ),
.O(\blk00000001/sig0000032a )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000294 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004d ),
.I2(\blk00000001/sig00000097 ),
.O(\blk00000001/sig00000329 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000293 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004c ),
.I2(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000328 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000292 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000004b ),
.I2(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000327 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000291 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000041 ),
.I2(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000031d )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000290 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000401 ),
.O(\blk00000001/sig000002d9 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000400 ),
.O(\blk00000001/sig000002d8 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003ff ),
.O(\blk00000001/sig000002d7 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003fe ),
.O(\blk00000001/sig000002d6 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003fd ),
.O(\blk00000001/sig000002d5 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003fc ),
.O(\blk00000001/sig000002d4 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000028a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003fb ),
.O(\blk00000001/sig000002d3 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000289 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003fa ),
.O(\blk00000001/sig000002d2 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000288 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003f9 ),
.O(\blk00000001/sig000002d1 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000287 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000040a ),
.O(\blk00000001/sig000002e2 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000286 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000409 ),
.O(\blk00000001/sig000002e1 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000285 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000408 ),
.O(\blk00000001/sig000002e0 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000284 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000407 ),
.O(\blk00000001/sig000002df )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000283 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000406 ),
.O(\blk00000001/sig000002de )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000282 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000405 ),
.O(\blk00000001/sig000002dd )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000281 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000404 ),
.O(\blk00000001/sig000002dc )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000280 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000403 ),
.O(\blk00000001/sig000002db )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000027f (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig00000402 ),
.O(\blk00000001/sig000002da )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000027e (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig000003f8 ),
.O(\blk00000001/sig000002d0 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000027d (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000054 ),
.O(\blk00000001/sig00000288 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000027c (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000053 ),
.O(\blk00000001/sig00000287 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000027b (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000052 ),
.O(\blk00000001/sig00000286 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000027a (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000051 ),
.O(\blk00000001/sig00000285 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000279 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000059 ),
.O(\blk00000001/sig0000028d )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000278 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000058 ),
.O(\blk00000001/sig0000028c )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000277 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000057 ),
.O(\blk00000001/sig0000028b )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000276 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000056 ),
.O(\blk00000001/sig0000028a )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000275 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000055 ),
.O(\blk00000001/sig00000289 )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk00000274 (
.I0(\blk00000001/sig0000003c ),
.I1(\blk00000001/sig0000008a ),
.I2(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000284 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000273 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000242 ),
.O(\blk00000001/sig000001e9 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000272 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000241 ),
.O(\blk00000001/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000271 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000240 ),
.O(\blk00000001/sig000001e7 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000270 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023f ),
.O(\blk00000001/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000026f (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023e ),
.O(\blk00000001/sig000001e5 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000026e (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023d ),
.O(\blk00000001/sig000001e4 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000026d (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000253 ),
.O(\blk00000001/sig0000020a )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000026c (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000252 ),
.O(\blk00000001/sig00000209 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000026b (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000251 ),
.O(\blk00000001/sig00000208 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000026a (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023c ),
.O(\blk00000001/sig000001e3 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000269 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000250 ),
.O(\blk00000001/sig00000207 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000268 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024f ),
.O(\blk00000001/sig00000206 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000267 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024e ),
.O(\blk00000001/sig00000205 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000266 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024d ),
.O(\blk00000001/sig00000204 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000265 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024c ),
.O(\blk00000001/sig00000203 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000264 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024b ),
.O(\blk00000001/sig00000202 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000263 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig0000024a ),
.O(\blk00000001/sig00000201 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000262 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000249 ),
.O(\blk00000001/sig00000200 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000261 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000248 ),
.O(\blk00000001/sig000001ff )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000260 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000247 ),
.O(\blk00000001/sig000001fe )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000025f (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023b ),
.O(\blk00000001/sig000001e2 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000025e (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000246 ),
.O(\blk00000001/sig000001fd )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000025d (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000245 ),
.O(\blk00000001/sig000001fc )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000025c (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000020b ),
.I2(\blk00000001/sig00000244 ),
.O(\blk00000001/sig000001fb )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000025b (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000253 ),
.I2(\blk00000001/sig00000243 ),
.O(\blk00000001/sig000001fa )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk0000025a (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000252 ),
.I2(\blk00000001/sig00000242 ),
.O(\blk00000001/sig000001f9 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000259 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000251 ),
.I2(\blk00000001/sig00000241 ),
.O(\blk00000001/sig000001f8 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000258 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000250 ),
.I2(\blk00000001/sig00000240 ),
.O(\blk00000001/sig000001f7 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000257 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024f ),
.I2(\blk00000001/sig0000023f ),
.O(\blk00000001/sig000001f6 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000256 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024e ),
.I2(\blk00000001/sig0000023e ),
.O(\blk00000001/sig000001f5 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000255 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024d ),
.I2(\blk00000001/sig0000023d ),
.O(\blk00000001/sig000001f4 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000254 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000023a ),
.O(\blk00000001/sig000001e1 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000253 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024c ),
.I2(\blk00000001/sig0000023c ),
.O(\blk00000001/sig000001f3 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000252 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024b ),
.I2(\blk00000001/sig0000023b ),
.O(\blk00000001/sig000001f2 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000251 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig0000024a ),
.I2(\blk00000001/sig0000023a ),
.O(\blk00000001/sig000001f1 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000250 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000249 ),
.I2(\blk00000001/sig00000239 ),
.O(\blk00000001/sig000001f0 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024f (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000248 ),
.O(\blk00000001/sig000001ef )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024e (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000247 ),
.O(\blk00000001/sig000001ee )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024d (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000246 ),
.O(\blk00000001/sig000001ed )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024c (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000245 ),
.O(\blk00000001/sig000001ec )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024b (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000244 ),
.O(\blk00000001/sig000001eb )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000024a (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000243 ),
.O(\blk00000001/sig000001ea )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000249 (
.I0(\blk00000001/sig00000238 ),
.I1(\blk00000001/sig00000239 ),
.O(\blk00000001/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000248 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig00000191 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000247 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig00000190 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000246 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig0000018f )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000245 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig0000018e )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000244 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig0000018c )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000243 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig0000018b )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000242 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig0000018d )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000241 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000bf ),
.O(\blk00000001/sig0000018a )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk00000240 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000be ),
.O(\blk00000001/sig00000189 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000023f (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig00000186 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000023e (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000bd ),
.O(\blk00000001/sig00000188 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk0000023d (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000bc ),
.O(\blk00000001/sig00000187 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk0000023c (
.I0(\blk00000001/sig0000016b ),
.I1(\blk00000001/sig00000161 ),
.O(\blk00000001/sig0000016a )
);
LUT3 #(
.INIT ( 8'h10 ))
\blk00000001/blk0000023b (
.I0(\blk00000001/sig000000cd ),
.I1(\blk00000001/sig000000cc ),
.I2(\blk00000001/sig0000015a ),
.O(\blk00000001/sig00000140 )
);
LUT4 #(
.INIT ( 16'h5410 ))
\blk00000001/blk0000023a (
.I0(\blk00000001/sig000000cd ),
.I1(\blk00000001/sig000000cc ),
.I2(\blk00000001/sig00000159 ),
.I3(\blk00000001/sig0000015a ),
.O(\blk00000001/sig0000013f )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000239 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000150 ),
.I3(\blk00000001/sig00000152 ),
.I4(\blk00000001/sig0000014f ),
.I5(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000135 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000238 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig0000014f ),
.I3(\blk00000001/sig00000151 ),
.I4(\blk00000001/sig0000014e ),
.I5(\blk00000001/sig00000150 ),
.O(\blk00000001/sig00000134 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000237 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000151 ),
.I3(\blk00000001/sig00000153 ),
.I4(\blk00000001/sig00000150 ),
.I5(\blk00000001/sig00000152 ),
.O(\blk00000001/sig00000136 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000236 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000152 ),
.I3(\blk00000001/sig00000154 ),
.I4(\blk00000001/sig00000151 ),
.I5(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000137 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000235 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000153 ),
.I3(\blk00000001/sig00000155 ),
.I4(\blk00000001/sig00000152 ),
.I5(\blk00000001/sig00000154 ),
.O(\blk00000001/sig00000138 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000234 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000154 ),
.I3(\blk00000001/sig00000156 ),
.I4(\blk00000001/sig00000153 ),
.I5(\blk00000001/sig00000155 ),
.O(\blk00000001/sig00000139 )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000233 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000155 ),
.I3(\blk00000001/sig00000157 ),
.I4(\blk00000001/sig00000154 ),
.I5(\blk00000001/sig00000156 ),
.O(\blk00000001/sig0000013a )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000232 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000158 ),
.I3(\blk00000001/sig0000015a ),
.I4(\blk00000001/sig00000157 ),
.I5(\blk00000001/sig00000159 ),
.O(\blk00000001/sig0000013d )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk00000231 (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000156 ),
.I3(\blk00000001/sig00000158 ),
.I4(\blk00000001/sig00000155 ),
.I5(\blk00000001/sig00000157 ),
.O(\blk00000001/sig0000013b )
);
LUT5 #(
.INIT ( 32'h73625140 ))
\blk00000001/blk00000230 (
.I0(\blk00000001/sig000000cd ),
.I1(\blk00000001/sig000000cc ),
.I2(\blk00000001/sig00000159 ),
.I3(\blk00000001/sig00000158 ),
.I4(\blk00000001/sig0000015a ),
.O(\blk00000001/sig0000013e )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000022f (
.I0(\blk00000001/sig000000cc ),
.I1(\blk00000001/sig000000cd ),
.I2(\blk00000001/sig00000157 ),
.I3(\blk00000001/sig00000159 ),
.I4(\blk00000001/sig00000156 ),
.I5(\blk00000001/sig00000158 ),
.O(\blk00000001/sig0000013c )
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
\blk00000001/blk0000022e (
.I0(\blk00000001/sig000000ce ),
.I1(\blk00000001/sig000000cf ),
.I2(\blk00000001/sig000000d8 ),
.I3(\blk00000001/sig000000d0 ),
.I4(\blk00000001/sig000000dc ),
.I5(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig00000141 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000022d (
.I0(\blk00000001/sig00000127 ),
.I1(\blk00000001/sig000000cf ),
.O(\blk00000001/sig00000133 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000022c (
.I0(\blk00000001/sig00000126 ),
.I1(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000132 )
);
LUT5 #(
.INIT ( 32'h01010100 ))
\blk00000001/blk0000022b (
.I0(\blk00000001/sig00000126 ),
.I1(\blk00000001/sig000000d4 ),
.I2(\blk00000001/sig000000d5 ),
.I3(\blk00000001/sig000000d2 ),
.I4(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig0000012e )
);
LUT2 #(
.INIT ( 4'h1 ))
\blk00000001/blk0000022a (
.I0(\blk00000001/sig000000de ),
.I1(\blk00000001/sig000000dd ),
.O(\blk00000001/sig00000124 )
);
LUT4 #(
.INIT ( 16'h0001 ))
\blk00000001/blk00000229 (
.I0(\blk00000001/sig000000e0 ),
.I1(\blk00000001/sig000000df ),
.I2(\blk00000001/sig000000e2 ),
.I3(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig00000123 )
);
LUT4 #(
.INIT ( 16'h0001 ))
\blk00000001/blk00000228 (
.I0(\blk00000001/sig000000e6 ),
.I1(\blk00000001/sig000000e5 ),
.I2(\blk00000001/sig000000e4 ),
.I3(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig00000122 )
);
LUT3 #(
.INIT ( 8'h01 ))
\blk00000001/blk00000227 (
.I0(\blk00000001/sig000000e9 ),
.I1(\blk00000001/sig000000e8 ),
.I2(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig00000121 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000226 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000120 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\blk00000001/blk00000225 (
.I0(\blk00000001/sig000000cf ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig00000126 ),
.O(\blk00000001/sig000000ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000224 (
.I0(\blk00000001/sig000000c9 ),
.I1(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig00000102 )
);
LUT3 #(
.INIT ( 8'h56 ))
\blk00000001/blk00000223 (
.I0(\blk00000001/sig000000ca ),
.I1(\blk00000001/sig000000c9 ),
.I2(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig00000103 )
);
LUT6 #(
.INIT ( 64'h5050505014505050 ))
\blk00000001/blk00000222 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000ff ),
.I2(\blk00000001/sig00000100 ),
.I3(\blk00000001/sig000000fe ),
.I4(\blk00000001/sig000000fd ),
.I5(\blk00000001/sig00000167 ),
.O(\blk00000001/sig000000fa )
);
LUT5 #(
.INIT ( 32'h44441444 ))
\blk00000001/blk00000221 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000ff ),
.I2(\blk00000001/sig000000fe ),
.I3(\blk00000001/sig000000fd ),
.I4(\blk00000001/sig00000167 ),
.O(\blk00000001/sig000000f9 )
);
LUT4 #(
.INIT ( 16'h4414 ))
\blk00000001/blk00000220 (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000fe ),
.I2(\blk00000001/sig000000fd ),
.I3(\blk00000001/sig00000167 ),
.O(\blk00000001/sig000000f8 )
);
LUT3 #(
.INIT ( 8'h41 ))
\blk00000001/blk0000021f (
.I0(\blk00000001/sig000000fc ),
.I1(\blk00000001/sig000000fd ),
.I2(\blk00000001/sig00000167 ),
.O(\blk00000001/sig000000f7 )
);
LUT4 #(
.INIT ( 16'hFFFE ))
\blk00000001/blk0000021e (
.I0(\blk00000001/sig000000cb ),
.I1(\blk00000001/sig000000c8 ),
.I2(\blk00000001/sig000000c9 ),
.I3(\blk00000001/sig000000ca ),
.O(\blk00000001/sig00000105 )
);
LUT4 #(
.INIT ( 16'h5556 ))
\blk00000001/blk0000021d (
.I0(\blk00000001/sig000000cb ),
.I1(\blk00000001/sig000000c8 ),
.I2(\blk00000001/sig000000c9 ),
.I3(\blk00000001/sig000000ca ),
.O(\blk00000001/sig00000104 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000021c (
.I0(s_axis_divisor_tdata[9]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000021b (
.I0(s_axis_divisor_tdata[8]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000021a (
.I0(s_axis_divisor_tdata[7]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000219 (
.I0(s_axis_divisor_tdata[6]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000218 (
.I0(s_axis_divisor_tdata[5]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000ef )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000217 (
.I0(s_axis_divisor_tdata[4]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000ee )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000216 (
.I0(s_axis_divisor_tdata[3]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000ed )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000215 (
.I0(s_axis_divisor_tdata[2]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000ec )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000214 (
.I0(s_axis_divisor_tdata[1]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000eb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000213 (
.I0(s_axis_divisor_tdata[11]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000212 (
.I0(s_axis_divisor_tdata[10]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000f4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000211 (
.I0(s_axis_divisor_tdata[0]),
.I1(s_axis_divisor_tdata[12]),
.O(\blk00000001/sig000000ea )
);
LUT3 #(
.INIT ( 8'h40 ))
\blk00000001/blk00000210 (
.I0(\blk00000001/sig0000003d ),
.I1(s_axis_dividend_tvalid),
.I2(s_axis_divisor_tvalid),
.O(\blk00000001/sig00000039 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020f (
.C(aclk),
.D(\blk00000001/sig00000545 ),
.Q(\blk00000001/sig0000055c )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 0 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk0000020e (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk0000020e_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000051d ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk0000020e_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig0000004f , \blk00000001/sig0000004e ,
\blk00000001/sig0000004d , \blk00000001/sig0000004c , \blk00000001/sig0000004b , \blk00000001/sig0000004a , \blk00000001/sig00000049 ,
\blk00000001/sig00000048 , \blk00000001/sig00000047 , \blk00000001/sig00000046 , \blk00000001/sig00000045 , \blk00000001/sig00000044 ,
\blk00000001/sig00000043 , \blk00000001/sig00000042 , \blk00000001/sig00000041 }),
.BCOUT({\NLW_blk00000001/blk0000020e_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000020e_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.C({\blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 ,
\blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 ,
\blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 ,
\blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000556 , \blk00000001/sig00000555 ,
\blk00000001/sig00000554 , \blk00000001/sig00000553 , \blk00000001/sig00000552 , \blk00000001/sig00000551 , \blk00000001/sig00000550 ,
\blk00000001/sig0000054f , \blk00000001/sig0000054e , \blk00000001/sig0000054d , \blk00000001/sig0000054c , \blk00000001/sig0000054b ,
\blk00000001/sig0000054a , \blk00000001/sig00000549 , \blk00000001/sig00000548 , \blk00000001/sig00000547 , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003f ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk0000020e_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<44>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<42>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<38>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<36>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000020e_P<29>_UNCONNECTED , NlwRenamedSignal_m_axis_dout_tdata[24],
m_axis_dout_tdata[23], m_axis_dout_tdata[22], m_axis_dout_tdata[21], m_axis_dout_tdata[20], m_axis_dout_tdata[19], m_axis_dout_tdata[18],
m_axis_dout_tdata[17], m_axis_dout_tdata[16], m_axis_dout_tdata[15], m_axis_dout_tdata[14], m_axis_dout_tdata[13], m_axis_dout_tdata[12],
NlwRenamedSig_OI_m_axis_dout_tdata[11], NlwRenamedSig_OI_m_axis_dout_tdata[10], NlwRenamedSig_OI_m_axis_dout_tdata[9],
NlwRenamedSig_OI_m_axis_dout_tdata[8], NlwRenamedSig_OI_m_axis_dout_tdata[7], NlwRenamedSig_OI_m_axis_dout_tdata[6],
NlwRenamedSig_OI_m_axis_dout_tdata[5], NlwRenamedSig_OI_m_axis_dout_tdata[4], NlwRenamedSig_OI_m_axis_dout_tdata[3],
NlwRenamedSig_OI_m_axis_dout_tdata[2], NlwRenamedSig_OI_m_axis_dout_tdata[1], NlwRenamedSig_OI_m_axis_dout_tdata[0], \blk00000001/sig0000055a ,
\blk00000001/sig00000559 , \blk00000001/sig00000558 , \blk00000001/sig00000557 }),
.OPMODE({\blk00000001/sig00000545 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000055b ,
\blk00000001/sig0000055b , \blk00000001/sig0000003a , \blk00000001/sig0000003a }),
.D({\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 }),
.PCOUT({\NLW_blk00000001/blk0000020e_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000020e_PCOUT<0>_UNCONNECTED }),
.A({\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 ,
\blk00000001/sig00000050 , \blk00000001/sig00000050 , \blk00000001/sig00000050 }),
.M({\NLW_blk00000001/blk0000020e_M<35>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<33>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<32>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<30>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<29>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<27>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<26>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<24>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<23>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<21>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<20>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<18>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<17>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<15>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<14>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<12>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<11>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<9>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<8>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<6>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<5>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<3>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<2>_UNCONNECTED , \NLW_blk00000001/blk0000020e_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk0000020e_M<0>_UNCONNECTED })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a1 ),
.Q(\blk00000001/sig00000397 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a2 ),
.Q(\blk00000001/sig00000398 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a3 ),
.Q(\blk00000001/sig00000399 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a4 ),
.Q(\blk00000001/sig0000039a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000209 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a5 ),
.Q(\blk00000001/sig0000039b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000208 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a6 ),
.Q(\blk00000001/sig0000039c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000207 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a7 ),
.Q(\blk00000001/sig0000039d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000206 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a8 ),
.Q(\blk00000001/sig0000039e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000205 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a9 ),
.Q(\blk00000001/sig0000039f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000204 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002aa ),
.Q(\blk00000001/sig000003a0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000203 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ab ),
.Q(\blk00000001/sig000003a1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000202 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ac ),
.Q(\blk00000001/sig000003a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000201 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ad ),
.Q(\blk00000001/sig000003a3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000200 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ae ),
.Q(\blk00000001/sig000003a4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ff (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002af ),
.Q(\blk00000001/sig000003a5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fe (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003a7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fc (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b0 ),
.Q(\blk00000001/sig000003a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b1 ),
.Q(\blk00000001/sig000003a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fa (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b2 ),
.Q(\blk00000001/sig000003aa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b3 ),
.Q(\blk00000001/sig000003ab )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b4 ),
.Q(\blk00000001/sig000003ac )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b5 ),
.Q(\blk00000001/sig000003ad )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b6 ),
.Q(\blk00000001/sig000003ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b7 ),
.Q(\blk00000001/sig000003af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b8 ),
.Q(\blk00000001/sig000003b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002b9 ),
.Q(\blk00000001/sig000003b1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ba ),
.Q(\blk00000001/sig000003b2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002bb ),
.Q(\blk00000001/sig000003b3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002bc ),
.Q(\blk00000001/sig000003b4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ef (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002bd ),
.Q(\blk00000001/sig000003b5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ee (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002be ),
.Q(\blk00000001/sig000003b6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ed (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002bf ),
.Q(\blk00000001/sig000003b7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ec (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003b8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001eb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003b9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ea (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003ba )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003bc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003bd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003be )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003bf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001df (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001de (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000003c6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001dd (
.C(aclk),
.D(\blk00000001/sig0000003c ),
.Q(\blk00000001/sig00000544 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001dc (
.C(aclk),
.D(\blk00000001/sig0000031c ),
.Q(\blk00000001/sig00000543 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001db (
.C(aclk),
.D(\blk00000001/sig00000543 ),
.Q(\blk00000001/sig00000491 )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 1 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001da (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001da_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000003a ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001da_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig000003f7 , \blk00000001/sig000003f6 , \blk00000001/sig000003f5 , \blk00000001/sig000003f4 , \blk00000001/sig000003f3 ,
\blk00000001/sig000003f2 , \blk00000001/sig000003f1 , \blk00000001/sig000003f0 , \blk00000001/sig000003ef , \blk00000001/sig000003ee ,
\blk00000001/sig000003ed , \blk00000001/sig000003ec , \blk00000001/sig000003eb , \blk00000001/sig000003ea , \blk00000001/sig000003e9 ,
\blk00000001/sig000003e8 , \blk00000001/sig000003e7 , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000001da_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001da_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig00000383 , \blk00000001/sig00000382 , \blk00000001/sig00000381 , \blk00000001/sig00000380 , \blk00000001/sig0000037f ,
\blk00000001/sig0000037e , \blk00000001/sig0000037d , \blk00000001/sig0000037c , \blk00000001/sig0000037b , \blk00000001/sig0000037a ,
\blk00000001/sig00000379 , \blk00000001/sig00000378 , \blk00000001/sig00000377 , \blk00000001/sig00000376 , \blk00000001/sig00000375 ,
\blk00000001/sig00000374 , \blk00000001/sig00000373 , \blk00000001/sig00000372 , \blk00000001/sig00000371 , \blk00000001/sig00000370 ,
\blk00000001/sig0000036f , \blk00000001/sig0000036e , \blk00000001/sig0000036d , \blk00000001/sig0000036c , \blk00000001/sig0000036b ,
\blk00000001/sig0000036a , \blk00000001/sig00000369 , \blk00000001/sig00000368 , \blk00000001/sig00000367 , \blk00000001/sig00000366 ,
\blk00000001/sig00000365 , \blk00000001/sig00000364 , \blk00000001/sig00000363 , \blk00000001/sig00000362 , \blk00000001/sig00000361 ,
\blk00000001/sig00000360 , \blk00000001/sig0000035f , \blk00000001/sig0000035e , \blk00000001/sig0000035d , \blk00000001/sig0000035c ,
\blk00000001/sig0000035b , \blk00000001/sig0000035a , \blk00000001/sig00000359 , \blk00000001/sig00000358 , \blk00000001/sig00000357 ,
\blk00000001/sig00000356 , \blk00000001/sig00000355 , \blk00000001/sig00000354 }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\blk00000001/sig00000050 , \NLW_blk00000001/blk000001da_P<46>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<45>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<43>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<40>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<39>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<37>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001da_P<34>_UNCONNECTED , \blk00000001/sig0000004f , \blk00000001/sig0000004e
, \blk00000001/sig0000004d , \blk00000001/sig0000004c , \blk00000001/sig0000004b , \blk00000001/sig0000004a , \blk00000001/sig00000049 ,
\blk00000001/sig00000048 , \blk00000001/sig00000047 , \blk00000001/sig00000046 , \blk00000001/sig00000045 , \blk00000001/sig00000044 ,
\blk00000001/sig00000043 , \blk00000001/sig00000042 , \blk00000001/sig00000041 , \blk00000001/sig00000353 , \blk00000001/sig00000352 ,
\blk00000001/sig00000351 , \blk00000001/sig00000350 , \blk00000001/sig0000034f , \blk00000001/sig0000034e , \blk00000001/sig0000034d ,
\blk00000001/sig0000034c , \blk00000001/sig0000034b , \blk00000001/sig0000034a , \blk00000001/sig00000349 , \blk00000001/sig00000348 ,
\blk00000001/sig00000347 , \blk00000001/sig00000346 , \blk00000001/sig00000345 , \blk00000001/sig00000344 , \blk00000001/sig00000343 ,
\blk00000001/sig00000342 , \blk00000001/sig00000341 }),
.OPMODE({\blk00000001/sig00000491 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000003a , \blk00000001/sig0000051d , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\NLW_blk00000001/blk000001da_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001da_PCOUT<0>_UNCONNECTED }),
.A({\blk00000001/sig00000490 , \blk00000001/sig0000048f , \blk00000001/sig0000048e , \blk00000001/sig0000048d , \blk00000001/sig0000048c ,
\blk00000001/sig0000048b , \blk00000001/sig0000048a , \blk00000001/sig00000489 , \blk00000001/sig00000488 , \blk00000001/sig00000487 ,
\blk00000001/sig00000486 , \blk00000001/sig00000485 , \blk00000001/sig00000484 , \blk00000001/sig00000483 , \blk00000001/sig00000482 ,
\blk00000001/sig00000481 , \blk00000001/sig00000480 , \blk00000001/sig0000047f }),
.M({\NLW_blk00000001/blk000001da_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001da_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001da_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 1 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001d9 (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001d9_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000003a ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001d9_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig0000051d , \blk00000001/sig0000047d , \blk00000001/sig0000047c , \blk00000001/sig0000047b , \blk00000001/sig0000047a ,
\blk00000001/sig00000479 , \blk00000001/sig00000478 , \blk00000001/sig00000477 , \blk00000001/sig00000476 , \blk00000001/sig00000475 ,
\blk00000001/sig00000474 , \blk00000001/sig00000473 , \blk00000001/sig00000472 , \blk00000001/sig00000471 , \blk00000001/sig00000470 ,
\blk00000001/sig0000046f , \blk00000001/sig0000046e , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000001d9_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d9_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000043a , \blk00000001/sig00000439 , \blk00000001/sig00000438 , \blk00000001/sig00000437 , \blk00000001/sig00000436 ,
\blk00000001/sig00000435 , \blk00000001/sig00000434 , \blk00000001/sig00000433 , \blk00000001/sig00000432 , \blk00000001/sig00000431 ,
\blk00000001/sig00000430 , \blk00000001/sig0000042f , \blk00000001/sig0000042e , \blk00000001/sig0000042d , \blk00000001/sig0000042c ,
\blk00000001/sig0000042b , \blk00000001/sig0000042a , \blk00000001/sig00000429 , \blk00000001/sig00000428 , \blk00000001/sig00000427 ,
\blk00000001/sig00000426 , \blk00000001/sig00000425 , \blk00000001/sig00000424 , \blk00000001/sig00000423 , \blk00000001/sig00000422 ,
\blk00000001/sig00000421 , \blk00000001/sig00000420 , \blk00000001/sig0000041f , \blk00000001/sig0000041e , \blk00000001/sig0000041d ,
\blk00000001/sig0000041c , \blk00000001/sig0000041b , \blk00000001/sig0000041a , \blk00000001/sig00000419 , \blk00000001/sig00000418 ,
\blk00000001/sig00000417 , \blk00000001/sig00000416 , \blk00000001/sig00000415 , \blk00000001/sig00000414 , \blk00000001/sig00000413 ,
\blk00000001/sig00000412 , \blk00000001/sig00000411 , \blk00000001/sig00000410 , \blk00000001/sig0000040f , \blk00000001/sig0000040e ,
\blk00000001/sig0000040d , \blk00000001/sig0000040c , \blk00000001/sig0000040b }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000001d9_P<47>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<45>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<42>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<39>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<36>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<33>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<32>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<30>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<29>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<27>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<26>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<24>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<23>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_P<21>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<20>_UNCONNECTED , \NLW_blk00000001/blk000001d9_P<19>_UNCONNECTED ,
\blk00000001/sig0000040a , \blk00000001/sig00000409 , \blk00000001/sig00000408 , \blk00000001/sig00000407 , \blk00000001/sig00000406 ,
\blk00000001/sig00000405 , \blk00000001/sig00000404 , \blk00000001/sig00000403 , \blk00000001/sig00000402 , \blk00000001/sig00000401 ,
\blk00000001/sig00000400 , \blk00000001/sig000003ff , \blk00000001/sig000003fe , \blk00000001/sig000003fd , \blk00000001/sig000003fc ,
\blk00000001/sig000003fb , \blk00000001/sig000003fa , \blk00000001/sig000003f9 , \blk00000001/sig000003f8 }),
.OPMODE({\blk00000001/sig00000491 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000003a , \blk00000001/sig0000051d , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\NLW_blk00000001/blk000001d9_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d9_PCOUT<0>_UNCONNECTED }),
.A({\blk00000001/sig00000490 , \blk00000001/sig0000048f , \blk00000001/sig0000048e , \blk00000001/sig0000048d , \blk00000001/sig0000048c ,
\blk00000001/sig0000048b , \blk00000001/sig0000048a , \blk00000001/sig00000489 , \blk00000001/sig00000488 , \blk00000001/sig00000487 ,
\blk00000001/sig00000486 , \blk00000001/sig00000485 , \blk00000001/sig00000484 , \blk00000001/sig00000483 , \blk00000001/sig00000482 ,
\blk00000001/sig00000481 , \blk00000001/sig00000480 , \blk00000001/sig0000047f }),
.M({\NLW_blk00000001/blk000001d9_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001d9_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d9_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 1 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001d8 (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001d8_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000003a ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001d8_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig00000526 , \blk00000001/sig00000525 , \blk00000001/sig00000524 ,
\blk00000001/sig00000523 , \blk00000001/sig00000522 , \blk00000001/sig00000521 , \blk00000001/sig00000520 , \blk00000001/sig0000051f ,
\blk00000001/sig0000051e , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000001d8_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d8_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig000004e3 , \blk00000001/sig000004e2 , \blk00000001/sig000004e1 , \blk00000001/sig000004e0 , \blk00000001/sig000004df ,
\blk00000001/sig000004de , \blk00000001/sig000004dd , \blk00000001/sig000004dc , \blk00000001/sig000004db , \blk00000001/sig000004da ,
\blk00000001/sig000004d9 , \blk00000001/sig000004d8 , \blk00000001/sig000004d7 , \blk00000001/sig000004d6 , \blk00000001/sig000004d5 ,
\blk00000001/sig000004d4 , \blk00000001/sig000004d3 , \blk00000001/sig000004d2 , \blk00000001/sig000004d1 , \blk00000001/sig000004d0 ,
\blk00000001/sig000004cf , \blk00000001/sig000004ce , \blk00000001/sig000004cd , \blk00000001/sig000004cc , \blk00000001/sig000004cb ,
\blk00000001/sig000004ca , \blk00000001/sig000004c9 , \blk00000001/sig000004c8 , \blk00000001/sig000004c7 , \blk00000001/sig000004c6 ,
\blk00000001/sig000004c5 , \blk00000001/sig000004c4 , \blk00000001/sig000004c3 , \blk00000001/sig000004c2 , \blk00000001/sig000004c1 ,
\blk00000001/sig000004c0 , \blk00000001/sig000004bf , \blk00000001/sig000004be , \blk00000001/sig000004bd , \blk00000001/sig000004bc ,
\blk00000001/sig000004bb , \blk00000001/sig000004ba , \blk00000001/sig000004b9 , \blk00000001/sig000004b8 , \blk00000001/sig000004b7 ,
\blk00000001/sig000004b6 , \blk00000001/sig000004b5 , \blk00000001/sig000004b4 }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000001d8_P<47>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_P<45>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_P<42>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_P<39>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_P<36>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001d8_P<34>_UNCONNECTED ,
\blk00000001/sig000004b3 , \blk00000001/sig000004b2 , \blk00000001/sig000004b1 , \blk00000001/sig000004b0 , \blk00000001/sig000004af ,
\blk00000001/sig000004ae , \blk00000001/sig000004ad , \blk00000001/sig000004ac , \blk00000001/sig000004ab , \blk00000001/sig000004aa ,
\blk00000001/sig000004a9 , \blk00000001/sig000004a8 , \blk00000001/sig000004a7 , \blk00000001/sig000004a6 , \blk00000001/sig000004a5 ,
\blk00000001/sig000004a4 , \blk00000001/sig000004a3 , \blk00000001/sig000004a2 , \blk00000001/sig000004a1 , \blk00000001/sig000004a0 ,
\blk00000001/sig0000049f , \blk00000001/sig0000049e , \blk00000001/sig0000049d , \blk00000001/sig0000049c , \blk00000001/sig0000049b ,
\blk00000001/sig0000049a , \blk00000001/sig00000499 , \blk00000001/sig00000498 , \blk00000001/sig00000497 , \blk00000001/sig00000496 ,
\blk00000001/sig00000495 , \blk00000001/sig00000494 , \blk00000001/sig00000493 , \blk00000001/sig00000492 }),
.OPMODE({\blk00000001/sig000004e4 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000003a , \blk00000001/sig0000051d , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\NLW_blk00000001/blk000001d8_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d8_PCOUT<0>_UNCONNECTED }),
.A({\blk00000001/sig0000051c , \blk00000001/sig0000051b , \blk00000001/sig0000051a , \blk00000001/sig00000519 , \blk00000001/sig00000518 ,
\blk00000001/sig00000517 , \blk00000001/sig00000516 , \blk00000001/sig00000515 , \blk00000001/sig00000514 , \blk00000001/sig00000513 ,
\blk00000001/sig00000512 , \blk00000001/sig00000511 , \blk00000001/sig00000510 , \blk00000001/sig0000050f , \blk00000001/sig0000050e ,
\blk00000001/sig0000050d , \blk00000001/sig0000050c , \blk00000001/sig0000050b }),
.M({\NLW_blk00000001/blk000001d8_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001d8_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d8_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 0 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001d7 (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001d7_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000051d ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001d7_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000052f , \blk00000001/sig0000052e ,
\blk00000001/sig0000052d , \blk00000001/sig0000052c , \blk00000001/sig0000052b , \blk00000001/sig0000052a , \blk00000001/sig00000529 ,
\blk00000001/sig00000528 , \blk00000001/sig00000527 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000001d7_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d7_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig000004f6 , \blk00000001/sig000004f5 , \blk00000001/sig000004f4 , \blk00000001/sig000004f3 ,
\blk00000001/sig000004f2 , \blk00000001/sig000004f1 , \blk00000001/sig000004f0 , \blk00000001/sig000004ef , \blk00000001/sig000004ee ,
\blk00000001/sig000004ed , \blk00000001/sig000004ec , \blk00000001/sig000004eb , \blk00000001/sig000004ea , \blk00000001/sig000004e9 ,
\blk00000001/sig000004e8 , \blk00000001/sig000004e7 , \blk00000001/sig000004e6 , \blk00000001/sig000004e5 , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000001d7_P<47>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<45>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<42>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<39>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<36>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<33>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<32>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<30>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<29>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<27>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<26>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<24>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<23>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<21>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<20>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<18>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<17>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<15>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<14>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<12>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<11>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<9>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<8>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<6>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<5>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<3>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<2>_UNCONNECTED , \NLW_blk00000001/blk000001d7_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_P<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003a ,
\blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\blk00000001/sig000004e3 , \blk00000001/sig000004e2 , \blk00000001/sig000004e1 , \blk00000001/sig000004e0 , \blk00000001/sig000004df ,
\blk00000001/sig000004de , \blk00000001/sig000004dd , \blk00000001/sig000004dc , \blk00000001/sig000004db , \blk00000001/sig000004da ,
\blk00000001/sig000004d9 , \blk00000001/sig000004d8 , \blk00000001/sig000004d7 , \blk00000001/sig000004d6 , \blk00000001/sig000004d5 ,
\blk00000001/sig000004d4 , \blk00000001/sig000004d3 , \blk00000001/sig000004d2 , \blk00000001/sig000004d1 , \blk00000001/sig000004d0 ,
\blk00000001/sig000004cf , \blk00000001/sig000004ce , \blk00000001/sig000004cd , \blk00000001/sig000004cc , \blk00000001/sig000004cb ,
\blk00000001/sig000004ca , \blk00000001/sig000004c9 , \blk00000001/sig000004c8 , \blk00000001/sig000004c7 , \blk00000001/sig000004c6 ,
\blk00000001/sig000004c5 , \blk00000001/sig000004c4 , \blk00000001/sig000004c3 , \blk00000001/sig000004c2 , \blk00000001/sig000004c1 ,
\blk00000001/sig000004c0 , \blk00000001/sig000004bf , \blk00000001/sig000004be , \blk00000001/sig000004bd , \blk00000001/sig000004bc ,
\blk00000001/sig000004bb , \blk00000001/sig000004ba , \blk00000001/sig000004b9 , \blk00000001/sig000004b8 , \blk00000001/sig000004b7 ,
\blk00000001/sig000004b6 , \blk00000001/sig000004b5 , \blk00000001/sig000004b4 }),
.A({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.M({\NLW_blk00000001/blk000001d7_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001d7_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d7_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 0 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001d6 (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001d6_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000051d ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001d6_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000001d6_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d6_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000044d , \blk00000001/sig0000044c , \blk00000001/sig0000044b , \blk00000001/sig0000044a , \blk00000001/sig00000449 ,
\blk00000001/sig00000448 , \blk00000001/sig00000447 , \blk00000001/sig00000446 , \blk00000001/sig00000445 , \blk00000001/sig00000444 ,
\blk00000001/sig00000443 , \blk00000001/sig00000442 , \blk00000001/sig00000441 , \blk00000001/sig00000440 , \blk00000001/sig0000043f ,
\blk00000001/sig0000043e , \blk00000001/sig0000043d , \blk00000001/sig0000043c , \blk00000001/sig0000043b , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000001d6_P<47>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<45>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<42>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<39>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<36>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<33>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<32>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<30>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<29>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<27>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<26>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<24>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<23>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<21>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<20>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<18>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<17>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<15>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<14>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<12>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<11>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<9>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<8>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<6>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<5>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<3>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<2>_UNCONNECTED , \NLW_blk00000001/blk000001d6_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_P<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003a ,
\blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\blk00000001/sig0000043a , \blk00000001/sig00000439 , \blk00000001/sig00000438 , \blk00000001/sig00000437 , \blk00000001/sig00000436 ,
\blk00000001/sig00000435 , \blk00000001/sig00000434 , \blk00000001/sig00000433 , \blk00000001/sig00000432 , \blk00000001/sig00000431 ,
\blk00000001/sig00000430 , \blk00000001/sig0000042f , \blk00000001/sig0000042e , \blk00000001/sig0000042d , \blk00000001/sig0000042c ,
\blk00000001/sig0000042b , \blk00000001/sig0000042a , \blk00000001/sig00000429 , \blk00000001/sig00000428 , \blk00000001/sig00000427 ,
\blk00000001/sig00000426 , \blk00000001/sig00000425 , \blk00000001/sig00000424 , \blk00000001/sig00000423 , \blk00000001/sig00000422 ,
\blk00000001/sig00000421 , \blk00000001/sig00000420 , \blk00000001/sig0000041f , \blk00000001/sig0000041e , \blk00000001/sig0000041d ,
\blk00000001/sig0000041c , \blk00000001/sig0000041b , \blk00000001/sig0000041a , \blk00000001/sig00000419 , \blk00000001/sig00000418 ,
\blk00000001/sig00000417 , \blk00000001/sig00000416 , \blk00000001/sig00000415 , \blk00000001/sig00000414 , \blk00000001/sig00000413 ,
\blk00000001/sig00000412 , \blk00000001/sig00000411 , \blk00000001/sig00000410 , \blk00000001/sig0000040f , \blk00000001/sig0000040e ,
\blk00000001/sig0000040d , \blk00000001/sig0000040c , \blk00000001/sig0000040b }),
.A({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.M({\NLW_blk00000001/blk000001d6_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001d6_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d6_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 0 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000001d5 (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000001d5_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000051d ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000001d5_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig000003a8 , \blk00000001/sig000003a7 , \blk00000001/sig000003a6 , \blk00000001/sig000003a5 , \blk00000001/sig000003a4 ,
\blk00000001/sig000003a3 , \blk00000001/sig000003a2 , \blk00000001/sig000003a1 , \blk00000001/sig000003a0 , \blk00000001/sig0000039f ,
\blk00000001/sig0000039e , \blk00000001/sig0000039d , \blk00000001/sig0000039c , \blk00000001/sig0000039b , \blk00000001/sig0000039a ,
\blk00000001/sig00000399 , \blk00000001/sig00000398 , \blk00000001/sig00000397 }),
.BCOUT({\NLW_blk00000001/blk000001d5_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000001d5_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig00000396 , \blk00000001/sig00000395 , \blk00000001/sig00000394 , \blk00000001/sig00000393 , \blk00000001/sig00000392 ,
\blk00000001/sig00000391 , \blk00000001/sig00000390 , \blk00000001/sig0000038f , \blk00000001/sig0000038e , \blk00000001/sig0000038d ,
\blk00000001/sig0000038c , \blk00000001/sig0000038b , \blk00000001/sig0000038a , \blk00000001/sig00000389 , \blk00000001/sig00000388 ,
\blk00000001/sig00000387 , \blk00000001/sig00000386 , \blk00000001/sig00000385 , \blk00000001/sig00000384 , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000001d5_P<47>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<45>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<44>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<42>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<41>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<39>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<38>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<36>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<35>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<33>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<32>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<30>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<29>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<27>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<26>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<24>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<23>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<21>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<20>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<18>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<17>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<15>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<14>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<12>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<11>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<9>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<8>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<6>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<5>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<3>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<2>_UNCONNECTED , \NLW_blk00000001/blk000001d5_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_P<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003a ,
\blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig0000003a }),
.D({\blk00000001/sig000003c6 , \blk00000001/sig000003c6 , \blk00000001/sig000003c6 , \blk00000001/sig000003c6 , \blk00000001/sig000003c6 ,
\blk00000001/sig000003c6 , \blk00000001/sig000003c6 , \blk00000001/sig000003c5 , \blk00000001/sig000003c4 , \blk00000001/sig000003c3 ,
\blk00000001/sig000003c2 , \blk00000001/sig000003c1 , \blk00000001/sig000003c0 , \blk00000001/sig000003bf , \blk00000001/sig000003be ,
\blk00000001/sig000003bd , \blk00000001/sig000003bc , \blk00000001/sig000003bb }),
.PCOUT({\blk00000001/sig00000383 , \blk00000001/sig00000382 , \blk00000001/sig00000381 , \blk00000001/sig00000380 , \blk00000001/sig0000037f ,
\blk00000001/sig0000037e , \blk00000001/sig0000037d , \blk00000001/sig0000037c , \blk00000001/sig0000037b , \blk00000001/sig0000037a ,
\blk00000001/sig00000379 , \blk00000001/sig00000378 , \blk00000001/sig00000377 , \blk00000001/sig00000376 , \blk00000001/sig00000375 ,
\blk00000001/sig00000374 , \blk00000001/sig00000373 , \blk00000001/sig00000372 , \blk00000001/sig00000371 , \blk00000001/sig00000370 ,
\blk00000001/sig0000036f , \blk00000001/sig0000036e , \blk00000001/sig0000036d , \blk00000001/sig0000036c , \blk00000001/sig0000036b ,
\blk00000001/sig0000036a , \blk00000001/sig00000369 , \blk00000001/sig00000368 , \blk00000001/sig00000367 , \blk00000001/sig00000366 ,
\blk00000001/sig00000365 , \blk00000001/sig00000364 , \blk00000001/sig00000363 , \blk00000001/sig00000362 , \blk00000001/sig00000361 ,
\blk00000001/sig00000360 , \blk00000001/sig0000035f , \blk00000001/sig0000035e , \blk00000001/sig0000035d , \blk00000001/sig0000035c ,
\blk00000001/sig0000035b , \blk00000001/sig0000035a , \blk00000001/sig00000359 , \blk00000001/sig00000358 , \blk00000001/sig00000357 ,
\blk00000001/sig00000356 , \blk00000001/sig00000355 , \blk00000001/sig00000354 }),
.A({\blk00000001/sig000003ba , \blk00000001/sig000003b9 , \blk00000001/sig000003b8 , \blk00000001/sig000003b7 , \blk00000001/sig000003b6 ,
\blk00000001/sig000003b5 , \blk00000001/sig000003b4 , \blk00000001/sig000003b3 , \blk00000001/sig000003b2 , \blk00000001/sig000003b1 ,
\blk00000001/sig000003b0 , \blk00000001/sig000003af , \blk00000001/sig000003ae , \blk00000001/sig000003ad , \blk00000001/sig000003ac ,
\blk00000001/sig000003ab , \blk00000001/sig000003aa , \blk00000001/sig000003a9 }),
.M({\NLW_blk00000001/blk000001d5_M<35>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<33>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<32>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<30>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<29>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<27>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<26>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<24>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<23>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<21>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<20>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<18>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<17>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<15>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<14>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<12>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<11>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<9>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<8>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<6>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<5>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<3>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<2>_UNCONNECTED , \NLW_blk00000001/blk000001d5_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000001d5_M<0>_UNCONNECTED })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d4 (
.C(aclk),
.D(\blk00000001/sig0000051c ),
.Q(\blk00000001/sig000004e4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032f ),
.Q(\blk00000001/sig000004e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000330 ),
.Q(\blk00000001/sig000004e6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000331 ),
.Q(\blk00000001/sig000004e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000332 ),
.Q(\blk00000001/sig000004e8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cf (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000333 ),
.Q(\blk00000001/sig000004e9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ce (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000334 ),
.Q(\blk00000001/sig000004ea )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000335 ),
.Q(\blk00000001/sig000004eb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cc (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000336 ),
.Q(\blk00000001/sig000004ec )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000337 ),
.Q(\blk00000001/sig000004ed )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ca (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000338 ),
.Q(\blk00000001/sig000004ee )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000339 ),
.Q(\blk00000001/sig000004ef )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033a ),
.Q(\blk00000001/sig000004f0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033b ),
.Q(\blk00000001/sig000004f1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033c ),
.Q(\blk00000001/sig000004f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033d ),
.Q(\blk00000001/sig000004f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033e ),
.Q(\blk00000001/sig000004f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000033f ),
.Q(\blk00000001/sig000004f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000340 ),
.Q(\blk00000001/sig000004f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000031d ),
.Q(\blk00000001/sig0000047f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000031e ),
.Q(\blk00000001/sig00000480 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bf (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000031f ),
.Q(\blk00000001/sig00000481 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001be (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000320 ),
.Q(\blk00000001/sig00000482 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000321 ),
.Q(\blk00000001/sig00000483 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bc (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000322 ),
.Q(\blk00000001/sig00000484 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000323 ),
.Q(\blk00000001/sig00000485 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ba (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000324 ),
.Q(\blk00000001/sig00000486 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000325 ),
.Q(\blk00000001/sig00000487 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000326 ),
.Q(\blk00000001/sig00000488 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000327 ),
.Q(\blk00000001/sig00000489 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000328 ),
.Q(\blk00000001/sig0000048a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000329 ),
.Q(\blk00000001/sig0000048b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032a ),
.Q(\blk00000001/sig0000048c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032b ),
.Q(\blk00000001/sig0000048d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032c ),
.Q(\blk00000001/sig0000048e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032d ),
.Q(\blk00000001/sig0000048f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000032e ),
.Q(\blk00000001/sig00000490 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001af (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e3 ),
.Q(\blk00000001/sig0000046e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ae (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e4 ),
.Q(\blk00000001/sig0000046f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ad (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e5 ),
.Q(\blk00000001/sig00000470 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ac (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e6 ),
.Q(\blk00000001/sig00000471 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ab (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e7 ),
.Q(\blk00000001/sig00000472 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001aa (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e8 ),
.Q(\blk00000001/sig00000473 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e9 ),
.Q(\blk00000001/sig00000474 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ea ),
.Q(\blk00000001/sig00000475 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002eb ),
.Q(\blk00000001/sig00000476 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ec ),
.Q(\blk00000001/sig00000477 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ed ),
.Q(\blk00000001/sig00000478 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ee ),
.Q(\blk00000001/sig00000479 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ef ),
.Q(\blk00000001/sig0000047a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f0 ),
.Q(\blk00000001/sig0000047b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f1 ),
.Q(\blk00000001/sig0000047c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f2 ),
.Q(\blk00000001/sig0000047d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c0 ),
.Q(\blk00000001/sig000003e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c1 ),
.Q(\blk00000001/sig000003e8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c2 ),
.Q(\blk00000001/sig000003e9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c3 ),
.Q(\blk00000001/sig000003ea )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c4 ),
.Q(\blk00000001/sig000003eb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c5 ),
.Q(\blk00000001/sig000003ec )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000199 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c6 ),
.Q(\blk00000001/sig000003ed )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000198 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c7 ),
.Q(\blk00000001/sig000003ee )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000197 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c8 ),
.Q(\blk00000001/sig000003ef )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000196 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002c9 ),
.Q(\blk00000001/sig000003f0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000195 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ca ),
.Q(\blk00000001/sig000003f1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000194 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002cb ),
.Q(\blk00000001/sig000003f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000193 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002cc ),
.Q(\blk00000001/sig000003f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000192 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002cd ),
.Q(\blk00000001/sig000003f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000191 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ce ),
.Q(\blk00000001/sig000003f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000190 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002cf ),
.Q(\blk00000001/sig000003f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002cf ),
.Q(\blk00000001/sig000003f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000542 ),
.Q(\blk00000001/sig0000050a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000530 ),
.Q(\blk00000001/sig0000050b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000531 ),
.Q(\blk00000001/sig0000050c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000532 ),
.Q(\blk00000001/sig0000050d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000533 ),
.Q(\blk00000001/sig0000050e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000189 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000534 ),
.Q(\blk00000001/sig0000050f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000535 ),
.Q(\blk00000001/sig00000510 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000187 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000536 ),
.Q(\blk00000001/sig00000511 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000537 ),
.Q(\blk00000001/sig00000512 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000185 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000538 ),
.Q(\blk00000001/sig00000513 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000539 ),
.Q(\blk00000001/sig00000514 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000183 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053a ),
.Q(\blk00000001/sig00000515 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053b ),
.Q(\blk00000001/sig00000516 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000181 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053c ),
.Q(\blk00000001/sig00000517 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053d ),
.Q(\blk00000001/sig00000518 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053e ),
.Q(\blk00000001/sig00000519 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000053f ),
.Q(\blk00000001/sig0000051a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000540 ),
.Q(\blk00000001/sig0000051b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000541 ),
.Q(\blk00000001/sig0000051c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d0 ),
.Q(\blk00000001/sig0000043b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d1 ),
.Q(\blk00000001/sig0000043c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000179 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d2 ),
.Q(\blk00000001/sig0000043d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000178 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d3 ),
.Q(\blk00000001/sig0000043e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000177 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d4 ),
.Q(\blk00000001/sig0000043f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000176 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d5 ),
.Q(\blk00000001/sig00000440 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000175 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d6 ),
.Q(\blk00000001/sig00000441 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000174 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d7 ),
.Q(\blk00000001/sig00000442 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000173 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d8 ),
.Q(\blk00000001/sig00000443 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000172 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002d9 ),
.Q(\blk00000001/sig00000444 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000171 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002da ),
.Q(\blk00000001/sig00000445 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000170 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002db ),
.Q(\blk00000001/sig00000446 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002dc ),
.Q(\blk00000001/sig00000447 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002dd ),
.Q(\blk00000001/sig00000448 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002de ),
.Q(\blk00000001/sig00000449 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002df ),
.Q(\blk00000001/sig0000044a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e0 ),
.Q(\blk00000001/sig0000044b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e1 ),
.Q(\blk00000001/sig0000044c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000169 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002e2 ),
.Q(\blk00000001/sig0000044d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000168 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028e ),
.Q(\blk00000001/sig00000384 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000167 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028f ),
.Q(\blk00000001/sig00000385 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000166 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000290 ),
.Q(\blk00000001/sig00000386 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000165 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000291 ),
.Q(\blk00000001/sig00000387 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000164 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000292 ),
.Q(\blk00000001/sig00000388 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000163 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000293 ),
.Q(\blk00000001/sig00000389 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000162 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000294 ),
.Q(\blk00000001/sig0000038a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000161 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000295 ),
.Q(\blk00000001/sig0000038b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000296 ),
.Q(\blk00000001/sig0000038c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000297 ),
.Q(\blk00000001/sig0000038d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000298 ),
.Q(\blk00000001/sig0000038e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000299 ),
.Q(\blk00000001/sig0000038f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029a ),
.Q(\blk00000001/sig00000390 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029b ),
.Q(\blk00000001/sig00000391 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029c ),
.Q(\blk00000001/sig00000392 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000159 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029d ),
.Q(\blk00000001/sig00000393 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029e ),
.Q(\blk00000001/sig00000394 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000157 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000029f ),
.Q(\blk00000001/sig00000395 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002a0 ),
.Q(\blk00000001/sig00000396 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000155 (
.C(aclk),
.D(\blk00000001/sig0000003b ),
.Q(\blk00000001/sig00000040 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000031b ),
.Q(\blk00000001/sig000003d6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000153 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000031a ),
.Q(\blk00000001/sig000003d5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000319 ),
.Q(\blk00000001/sig000003d4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000151 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000318 ),
.Q(\blk00000001/sig000003d3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000317 ),
.Q(\blk00000001/sig000003d2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000316 ),
.Q(\blk00000001/sig000003d1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000315 ),
.Q(\blk00000001/sig000003d0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000314 ),
.Q(\blk00000001/sig000003cf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000313 ),
.Q(\blk00000001/sig000003ce )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000312 ),
.Q(\blk00000001/sig000003cd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000311 ),
.Q(\blk00000001/sig000003cc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000149 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000310 ),
.Q(\blk00000001/sig000003cb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030f ),
.Q(\blk00000001/sig000003ca )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000147 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030e ),
.Q(\blk00000001/sig000003c9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000146 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030d ),
.Q(\blk00000001/sig000003c8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000145 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030c ),
.Q(\blk00000001/sig000003c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000144 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030b ),
.Q(\blk00000001/sig0000045d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000143 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000030a ),
.Q(\blk00000001/sig0000045c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000142 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000309 ),
.Q(\blk00000001/sig0000045b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000141 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000308 ),
.Q(\blk00000001/sig0000045a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000140 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000307 ),
.Q(\blk00000001/sig00000459 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000306 ),
.Q(\blk00000001/sig00000458 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000305 ),
.Q(\blk00000001/sig00000457 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000304 ),
.Q(\blk00000001/sig00000456 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000303 ),
.Q(\blk00000001/sig00000455 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000302 ),
.Q(\blk00000001/sig00000454 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000301 ),
.Q(\blk00000001/sig00000453 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000139 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000300 ),
.Q(\blk00000001/sig00000452 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000138 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002ff ),
.Q(\blk00000001/sig00000451 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000137 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002fe ),
.Q(\blk00000001/sig00000450 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000136 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002fd ),
.Q(\blk00000001/sig0000044f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000135 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002fc ),
.Q(\blk00000001/sig0000044e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000134 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002fb ),
.Q(\blk00000001/sig00000526 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000133 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002fa ),
.Q(\blk00000001/sig00000525 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000132 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f9 ),
.Q(\blk00000001/sig00000524 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000131 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f8 ),
.Q(\blk00000001/sig00000523 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000130 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f7 ),
.Q(\blk00000001/sig00000522 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f6 ),
.Q(\blk00000001/sig00000521 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f5 ),
.Q(\blk00000001/sig00000520 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f4 ),
.Q(\blk00000001/sig0000051f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000002f3 ),
.Q(\blk00000001/sig0000051e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028d ),
.Q(\blk00000001/sig0000052f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028c ),
.Q(\blk00000001/sig0000052e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000129 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028b ),
.Q(\blk00000001/sig0000052d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000128 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000028a ),
.Q(\blk00000001/sig0000052c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000127 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000289 ),
.Q(\blk00000001/sig0000052b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000126 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000288 ),
.Q(\blk00000001/sig0000052a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000125 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000287 ),
.Q(\blk00000001/sig00000529 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000124 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000286 ),
.Q(\blk00000001/sig00000528 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000123 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000285 ),
.Q(\blk00000001/sig00000527 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000122 (
.C(aclk),
.D(\blk00000001/sig000001e0 ),
.Q(\blk00000001/sig00000051 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000121 (
.C(aclk),
.D(\blk00000001/sig000001e1 ),
.Q(\blk00000001/sig00000052 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000120 (
.C(aclk),
.D(\blk00000001/sig000001e2 ),
.Q(\blk00000001/sig00000053 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011f (
.C(aclk),
.D(\blk00000001/sig000001e3 ),
.Q(\blk00000001/sig00000054 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011e (
.C(aclk),
.D(\blk00000001/sig000001e4 ),
.Q(\blk00000001/sig00000055 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011d (
.C(aclk),
.D(\blk00000001/sig000001e5 ),
.Q(\blk00000001/sig00000056 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011c (
.C(aclk),
.D(\blk00000001/sig000001e6 ),
.Q(\blk00000001/sig00000057 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011b (
.C(aclk),
.D(\blk00000001/sig000001e7 ),
.Q(\blk00000001/sig00000058 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011a (
.C(aclk),
.D(\blk00000001/sig000001e8 ),
.Q(\blk00000001/sig00000059 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000119 (
.C(aclk),
.D(\blk00000001/sig000001e9 ),
.Q(\blk00000001/sig0000005a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000118 (
.C(aclk),
.D(\blk00000001/sig000001ea ),
.Q(\blk00000001/sig0000005b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000117 (
.C(aclk),
.D(\blk00000001/sig000001eb ),
.Q(\blk00000001/sig0000005c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(aclk),
.D(\blk00000001/sig000001ec ),
.Q(\blk00000001/sig0000005d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000115 (
.C(aclk),
.D(\blk00000001/sig000001ed ),
.Q(\blk00000001/sig0000005e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000114 (
.C(aclk),
.D(\blk00000001/sig000001ee ),
.Q(\blk00000001/sig0000005f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000113 (
.C(aclk),
.D(\blk00000001/sig000001ef ),
.Q(\blk00000001/sig00000060 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000112 (
.C(aclk),
.D(\blk00000001/sig000001f0 ),
.Q(\blk00000001/sig00000061 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000111 (
.C(aclk),
.D(\blk00000001/sig000001f1 ),
.Q(\blk00000001/sig00000062 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000110 (
.C(aclk),
.D(\blk00000001/sig000001f2 ),
.Q(\blk00000001/sig00000063 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010f (
.C(aclk),
.D(\blk00000001/sig000001f3 ),
.Q(\blk00000001/sig00000064 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010e (
.C(aclk),
.D(\blk00000001/sig000001f4 ),
.Q(\blk00000001/sig00000065 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010d (
.C(aclk),
.D(\blk00000001/sig000001f5 ),
.Q(\blk00000001/sig00000066 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010c (
.C(aclk),
.D(\blk00000001/sig000001f6 ),
.Q(\blk00000001/sig00000067 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010b (
.C(aclk),
.D(\blk00000001/sig000001f7 ),
.Q(\blk00000001/sig00000068 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010a (
.C(aclk),
.D(\blk00000001/sig000001f8 ),
.Q(\blk00000001/sig00000069 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000109 (
.C(aclk),
.D(\blk00000001/sig000001f9 ),
.Q(\blk00000001/sig00000271 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000108 (
.C(aclk),
.D(\blk00000001/sig000001fa ),
.Q(\blk00000001/sig00000272 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000107 (
.C(aclk),
.D(\blk00000001/sig000001fb ),
.Q(\blk00000001/sig00000273 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000106 (
.C(aclk),
.D(\blk00000001/sig000001fc ),
.Q(\blk00000001/sig00000274 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000105 (
.C(aclk),
.D(\blk00000001/sig000001fd ),
.Q(\blk00000001/sig00000275 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000104 (
.C(aclk),
.D(\blk00000001/sig000001fe ),
.Q(\blk00000001/sig00000276 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000103 (
.C(aclk),
.D(\blk00000001/sig000001ff ),
.Q(\blk00000001/sig00000277 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000102 (
.C(aclk),
.D(\blk00000001/sig00000200 ),
.Q(\blk00000001/sig00000278 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000101 (
.C(aclk),
.D(\blk00000001/sig00000201 ),
.Q(\blk00000001/sig00000279 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000100 (
.C(aclk),
.D(\blk00000001/sig00000202 ),
.Q(\blk00000001/sig0000027a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ff (
.C(aclk),
.D(\blk00000001/sig00000203 ),
.Q(\blk00000001/sig0000027b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fe (
.C(aclk),
.D(\blk00000001/sig00000204 ),
.Q(\blk00000001/sig0000027c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(aclk),
.D(\blk00000001/sig00000205 ),
.Q(\blk00000001/sig0000027d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(aclk),
.D(\blk00000001/sig00000206 ),
.Q(\blk00000001/sig0000027e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(aclk),
.D(\blk00000001/sig00000207 ),
.Q(\blk00000001/sig0000027f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(aclk),
.D(\blk00000001/sig00000208 ),
.Q(\blk00000001/sig00000280 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(aclk),
.D(\blk00000001/sig00000209 ),
.Q(\blk00000001/sig00000281 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(aclk),
.D(\blk00000001/sig0000020a ),
.Q(\blk00000001/sig00000282 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(aclk),
.D(\blk00000001/sig0000020b ),
.Q(\blk00000001/sig00000283 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(aclk),
.D(\blk00000001/sig0000020c ),
.Q(\blk00000001/sig00000239 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(aclk),
.D(\blk00000001/sig0000020d ),
.Q(\blk00000001/sig0000023a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(aclk),
.D(\blk00000001/sig0000020e ),
.Q(\blk00000001/sig0000023b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(aclk),
.D(\blk00000001/sig0000020f ),
.Q(\blk00000001/sig0000023c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(aclk),
.D(\blk00000001/sig00000210 ),
.Q(\blk00000001/sig0000023d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(aclk),
.D(\blk00000001/sig00000211 ),
.Q(\blk00000001/sig0000023e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(aclk),
.D(\blk00000001/sig00000212 ),
.Q(\blk00000001/sig0000023f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(aclk),
.D(\blk00000001/sig00000213 ),
.Q(\blk00000001/sig00000240 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ee (
.C(aclk),
.D(\blk00000001/sig00000214 ),
.Q(\blk00000001/sig00000241 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ed (
.C(aclk),
.D(\blk00000001/sig00000215 ),
.Q(\blk00000001/sig00000242 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ec (
.C(aclk),
.D(\blk00000001/sig00000216 ),
.Q(\blk00000001/sig00000243 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000eb (
.C(aclk),
.D(\blk00000001/sig00000217 ),
.Q(\blk00000001/sig00000244 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ea (
.C(aclk),
.D(\blk00000001/sig00000218 ),
.Q(\blk00000001/sig00000245 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e9 (
.C(aclk),
.D(\blk00000001/sig00000219 ),
.Q(\blk00000001/sig00000246 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e8 (
.C(aclk),
.D(\blk00000001/sig0000021a ),
.Q(\blk00000001/sig00000247 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e7 (
.C(aclk),
.D(\blk00000001/sig0000021b ),
.Q(\blk00000001/sig00000248 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e6 (
.C(aclk),
.D(\blk00000001/sig0000021c ),
.Q(\blk00000001/sig00000249 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e5 (
.C(aclk),
.D(\blk00000001/sig0000021d ),
.Q(\blk00000001/sig0000024a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e4 (
.C(aclk),
.D(\blk00000001/sig0000021e ),
.Q(\blk00000001/sig0000024b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e3 (
.C(aclk),
.D(\blk00000001/sig0000021f ),
.Q(\blk00000001/sig0000024c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e2 (
.C(aclk),
.D(\blk00000001/sig00000220 ),
.Q(\blk00000001/sig0000024d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e1 (
.C(aclk),
.D(\blk00000001/sig00000221 ),
.Q(\blk00000001/sig0000024e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e0 (
.C(aclk),
.D(\blk00000001/sig00000222 ),
.Q(\blk00000001/sig0000024f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000df (
.C(aclk),
.D(\blk00000001/sig00000223 ),
.Q(\blk00000001/sig00000250 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000de (
.C(aclk),
.D(\blk00000001/sig00000224 ),
.Q(\blk00000001/sig00000251 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dd (
.C(aclk),
.D(\blk00000001/sig00000225 ),
.Q(\blk00000001/sig00000252 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dc (
.C(aclk),
.D(\blk00000001/sig00000226 ),
.Q(\blk00000001/sig00000253 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000db (
.C(aclk),
.D(\blk00000001/sig00000227 ),
.Q(\blk00000001/sig0000020b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000da (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000268 ),
.Q(\blk00000001/sig00000254 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000269 ),
.Q(\blk00000001/sig00000255 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000026a ),
.Q(\blk00000001/sig00000258 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000026b ),
.Q(\blk00000001/sig00000256 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000026c ),
.Q(\blk00000001/sig00000257 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000254 ),
.Q(\blk00000001/sig0000026d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000255 ),
.Q(\blk00000001/sig0000026e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000258 ),
.Q(\blk00000001/sig0000026f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000256 ),
.Q(\blk00000001/sig00000270 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000257 ),
.Q(\blk00000001/sig00000238 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d0 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000228 ),
.Q(\blk00000001/sig00000259 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cf (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000229 ),
.Q(\blk00000001/sig0000025a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ce (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022a ),
.Q(\blk00000001/sig0000025b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cd (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022b ),
.Q(\blk00000001/sig0000025c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cc (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022c ),
.Q(\blk00000001/sig0000025d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cb (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022d ),
.Q(\blk00000001/sig0000025e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ca (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022e ),
.Q(\blk00000001/sig0000025f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c9 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000022f ),
.Q(\blk00000001/sig00000260 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c8 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000230 ),
.Q(\blk00000001/sig00000261 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c7 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000231 ),
.Q(\blk00000001/sig00000262 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c6 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000232 ),
.Q(\blk00000001/sig00000263 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c5 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000233 ),
.Q(\blk00000001/sig00000264 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c4 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000234 ),
.Q(\blk00000001/sig00000265 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c3 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000235 ),
.Q(\blk00000001/sig00000266 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c2 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000236 ),
.Q(\blk00000001/sig00000267 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c1 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000237 ),
.Q(\blk00000001/sig00000227 )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 1 ),
.MREG ( 1 ),
.OPMODEREG ( 1 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000000ad (
.CECARRYIN(\blk00000001/sig0000051d ),
.RSTC(\blk00000001/sig0000051d ),
.RSTCARRYIN(\blk00000001/sig0000051d ),
.CED(\blk00000001/sig0000003a ),
.RSTD(\blk00000001/sig0000051d ),
.CEOPMODE(\blk00000001/sig0000003a ),
.CEC(\blk00000001/sig0000003a ),
.CARRYOUTF(\NLW_blk00000001/blk000000ad_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig0000051d ),
.RSTM(\blk00000001/sig0000051d ),
.CLK(aclk),
.RSTB(\blk00000001/sig0000051d ),
.CEM(\blk00000001/sig0000003a ),
.CEB(\blk00000001/sig0000003a ),
.CARRYIN(\blk00000001/sig0000051d ),
.CEP(\blk00000001/sig0000003a ),
.CEA(\blk00000001/sig0000003a ),
.CARRYOUT(\NLW_blk00000001/blk000000ad_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig0000051d ),
.RSTP(\blk00000001/sig0000051d ),
.B({\blk00000001/sig000001ab , \blk00000001/sig000001ab , \blk00000001/sig000001df , \blk00000001/sig000001de , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.BCOUT({\NLW_blk00000001/blk000000ad_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ad_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.C({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003a , \blk00000001/sig000001aa ,
\blk00000001/sig000001a9 , \blk00000001/sig000001a8 , \blk00000001/sig000001a7 , \blk00000001/sig000001a6 , \blk00000001/sig000001a5 ,
\blk00000001/sig000001a4 , \blk00000001/sig000001a3 , \blk00000001/sig000001a2 , \blk00000001/sig000001a1 , \blk00000001/sig000001a0 ,
\blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d , \blk00000001/sig0000019c , \blk00000001/sig0000019b ,
\blk00000001/sig0000019a , \blk00000001/sig00000199 , \blk00000001/sig00000198 , \blk00000001/sig00000197 , \blk00000001/sig00000196 ,
\blk00000001/sig00000195 , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.P({\NLW_blk00000001/blk000000ad_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<41>_UNCONNECTED , \blk00000001/sig0000009c , \blk00000001/sig0000009b
, \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 , \blk00000001/sig00000097 , \blk00000001/sig00000096 ,
\blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 , \blk00000001/sig00000092 , \blk00000001/sig00000091 ,
\blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c ,
\blk00000001/sig0000008b , \blk00000001/sig0000008a , \NLW_blk00000001/blk000000ad_P<21>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<20>_UNCONNECTED
, \NLW_blk00000001/blk000000ad_P<19>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<18>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<17>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<16>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<15>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<13>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<12>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<11>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<10>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<9>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<7>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<6>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<5>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<4>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<3>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_P<1>_UNCONNECTED , \NLW_blk00000001/blk000000ad_P<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000003a ,
\blk00000001/sig0000003a , \blk00000001/sig0000051d , \blk00000001/sig0000003a }),
.D({\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d ,
\blk00000001/sig0000051d , \blk00000001/sig0000051d , \blk00000001/sig0000051d }),
.PCOUT({\NLW_blk00000001/blk000000ad_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ad_PCOUT<0>_UNCONNECTED }),
.A({\blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig0000003a , \blk00000001/sig000001cb ,
\blk00000001/sig000001ca , \blk00000001/sig000001c9 , \blk00000001/sig000001c8 , \blk00000001/sig000001c7 , \blk00000001/sig000001c6 ,
\blk00000001/sig000001c5 , \blk00000001/sig000001c4 , \blk00000001/sig000001c3 , \blk00000001/sig000001c2 , \blk00000001/sig000001c1 ,
\blk00000001/sig000001c0 , \blk00000001/sig000001bf , \blk00000001/sig000001be }),
.M({\NLW_blk00000001/blk000000ad_M<35>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<33>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<32>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<30>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<29>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<27>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<26>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<24>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<23>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<21>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<20>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<18>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<17>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<15>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<14>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<12>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<11>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<9>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<8>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<6>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<5>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<3>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<2>_UNCONNECTED , \NLW_blk00000001/blk000000ad_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk000000ad_M<0>_UNCONNECTED })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ac (
.C(aclk),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ab (
.C(aclk),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000aa (
.C(aclk),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001c0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a9 (
.C(aclk),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a8 (
.C(aclk),
.D(\blk00000001/sig000001d0 ),
.Q(\blk00000001/sig000001c2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a7 (
.C(aclk),
.D(\blk00000001/sig000001d1 ),
.Q(\blk00000001/sig000001c3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a6 (
.C(aclk),
.D(\blk00000001/sig000001d2 ),
.Q(\blk00000001/sig000001c4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a5 (
.C(aclk),
.D(\blk00000001/sig000001d3 ),
.Q(\blk00000001/sig000001c5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a4 (
.C(aclk),
.D(\blk00000001/sig000001d4 ),
.Q(\blk00000001/sig000001c6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(aclk),
.D(\blk00000001/sig000001d5 ),
.Q(\blk00000001/sig000001c7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a2 (
.C(aclk),
.D(\blk00000001/sig000001d6 ),
.Q(\blk00000001/sig000001c8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a1 (
.C(aclk),
.D(\blk00000001/sig000001d7 ),
.Q(\blk00000001/sig000001c9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a0 (
.C(aclk),
.D(\blk00000001/sig000001d8 ),
.Q(\blk00000001/sig000001ca )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009f (
.C(aclk),
.D(\blk00000001/sig000001d9 ),
.Q(\blk00000001/sig000001cb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009e (
.C(aclk),
.D(\blk00000001/sig0000051d ),
.Q(\blk00000001/sig00000193 )
);
FD \blk00000001/blk0000009d (
.C(aclk),
.D(\blk00000001/sig00000186 ),
.Q(\blk00000001/sig000000aa )
);
FD \blk00000001/blk0000009c (
.C(aclk),
.D(\blk00000001/sig00000187 ),
.Q(\blk00000001/sig000000ab )
);
FD \blk00000001/blk0000009b (
.C(aclk),
.D(\blk00000001/sig00000188 ),
.Q(\blk00000001/sig000000ac )
);
FD \blk00000001/blk0000009a (
.C(aclk),
.D(\blk00000001/sig00000189 ),
.Q(\blk00000001/sig000000ad )
);
FD \blk00000001/blk00000099 (
.C(aclk),
.D(\blk00000001/sig0000018a ),
.Q(\blk00000001/sig000000ae )
);
FD \blk00000001/blk00000098 (
.C(aclk),
.D(\blk00000001/sig0000018b ),
.Q(\blk00000001/sig000000af )
);
FD \blk00000001/blk00000097 (
.C(aclk),
.D(\blk00000001/sig0000018c ),
.Q(\blk00000001/sig000000b0 )
);
FD \blk00000001/blk00000096 (
.C(aclk),
.D(\blk00000001/sig0000018d ),
.Q(\blk00000001/sig000000b1 )
);
FD \blk00000001/blk00000095 (
.C(aclk),
.D(\blk00000001/sig0000018e ),
.Q(\blk00000001/sig000000b2 )
);
FD \blk00000001/blk00000094 (
.C(aclk),
.D(\blk00000001/sig0000018f ),
.Q(\blk00000001/sig000000b3 )
);
FD \blk00000001/blk00000093 (
.C(aclk),
.D(\blk00000001/sig00000190 ),
.Q(\blk00000001/sig000000b4 )
);
FD \blk00000001/blk00000092 (
.C(aclk),
.D(\blk00000001/sig00000191 ),
.Q(\blk00000001/sig000000b5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000091 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000184 ),
.Q(\blk00000001/sig000000c1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000090 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000182 ),
.Q(\blk00000001/sig000000c2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000180 ),
.Q(\blk00000001/sig000000c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000017e ),
.Q(\blk00000001/sig000000c4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000017c ),
.Q(\blk00000001/sig000000c5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000017a ),
.Q(\blk00000001/sig000000c6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000179 ),
.Q(\blk00000001/sig00000167 )
);
MUXCY \blk00000001/blk0000008a (
.CI(\blk00000001/sig00000168 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000056d ),
.O(\blk00000001/sig00000185 )
);
XORCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig00000168 ),
.LI(\blk00000001/sig0000056d ),
.O(\blk00000001/sig00000184 )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig00000185 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000056c ),
.O(\blk00000001/sig00000183 )
);
XORCY \blk00000001/blk00000087 (
.CI(\blk00000001/sig00000185 ),
.LI(\blk00000001/sig0000056c ),
.O(\blk00000001/sig00000182 )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig00000183 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000056b ),
.O(\blk00000001/sig00000181 )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000183 ),
.LI(\blk00000001/sig0000056b ),
.O(\blk00000001/sig00000180 )
);
MUXCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig00000181 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000056a ),
.O(\blk00000001/sig0000017f )
);
XORCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig00000181 ),
.LI(\blk00000001/sig0000056a ),
.O(\blk00000001/sig0000017e )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000017f ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000569 ),
.O(\blk00000001/sig0000017d )
);
XORCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig0000017f ),
.LI(\blk00000001/sig00000569 ),
.O(\blk00000001/sig0000017c )
);
MUXCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig0000017d ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000568 ),
.O(\blk00000001/sig0000017b )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig0000017d ),
.LI(\blk00000001/sig00000568 ),
.O(\blk00000001/sig0000017a )
);
XORCY \blk00000001/blk0000007e (
.CI(\blk00000001/sig0000017b ),
.LI(\blk00000001/sig0000003a ),
.O(\blk00000001/sig00000179 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000177 ),
.Q(\blk00000001/sig000000bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000175 ),
.Q(\blk00000001/sig000000bc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000173 ),
.Q(\blk00000001/sig000000bd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000171 ),
.Q(\blk00000001/sig000000be )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000079 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000016f ),
.Q(\blk00000001/sig000000bf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000078 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000016e ),
.Q(\blk00000001/sig000000c0 )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000169 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000567 ),
.O(\blk00000001/sig00000178 )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000169 ),
.LI(\blk00000001/sig00000567 ),
.O(\blk00000001/sig00000177 )
);
MUXCY \blk00000001/blk00000075 (
.CI(\blk00000001/sig00000178 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000566 ),
.O(\blk00000001/sig00000176 )
);
XORCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig00000178 ),
.LI(\blk00000001/sig00000566 ),
.O(\blk00000001/sig00000175 )
);
MUXCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig00000176 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000565 ),
.O(\blk00000001/sig00000174 )
);
XORCY \blk00000001/blk00000072 (
.CI(\blk00000001/sig00000176 ),
.LI(\blk00000001/sig00000565 ),
.O(\blk00000001/sig00000173 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig00000174 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000564 ),
.O(\blk00000001/sig00000172 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig00000174 ),
.LI(\blk00000001/sig00000564 ),
.O(\blk00000001/sig00000171 )
);
MUXCY \blk00000001/blk0000006f (
.CI(\blk00000001/sig00000172 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000563 ),
.O(\blk00000001/sig00000170 )
);
XORCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig00000172 ),
.LI(\blk00000001/sig00000563 ),
.O(\blk00000001/sig0000016f )
);
MUXCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig00000170 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000562 ),
.O(\blk00000001/sig00000168 )
);
XORCY \blk00000001/blk0000006c (
.CI(\blk00000001/sig00000170 ),
.LI(\blk00000001/sig00000562 ),
.O(\blk00000001/sig0000016e )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig0000003a ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000561 ),
.O(\blk00000001/sig0000016d )
);
MUXCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig0000016d ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000051d ),
.O(\blk00000001/sig0000016c )
);
MUXCY \blk00000001/blk00000069 (
.CI(\blk00000001/sig0000016c ),
.DI(\blk00000001/sig0000003a ),
.S(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000169 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000068 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000140 ),
.Q(\blk00000001/sig0000016b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000067 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013f ),
.Q(\blk00000001/sig00000161 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000066 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013e ),
.Q(\blk00000001/sig00000162 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000065 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013d ),
.Q(\blk00000001/sig00000163 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000064 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013c ),
.Q(\blk00000001/sig00000164 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000063 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013b ),
.Q(\blk00000001/sig00000165 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000062 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig00000166 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000061 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig0000015b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000060 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig0000015c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig0000015d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig0000015e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig0000015f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig00000160 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000014d ),
.Q(\blk00000001/sig0000015a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000014c ),
.Q(\blk00000001/sig00000159 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000059 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000014b ),
.Q(\blk00000001/sig00000158 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000058 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000014a ),
.Q(\blk00000001/sig00000157 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000057 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000149 ),
.Q(\blk00000001/sig00000156 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000056 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000148 ),
.Q(\blk00000001/sig00000155 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000055 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig00000154 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000054 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000146 ),
.Q(\blk00000001/sig00000153 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000053 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000145 ),
.Q(\blk00000001/sig00000152 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000052 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000144 ),
.Q(\blk00000001/sig00000151 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000051 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000143 ),
.Q(\blk00000001/sig00000150 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000050 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000142 ),
.Q(\blk00000001/sig0000014f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000141 ),
.Q(\blk00000001/sig0000014e )
);
MUXF7 \blk00000001/blk0000004e (
.I0(\blk00000001/sig00000133 ),
.I1(\blk00000001/sig00000132 ),
.S(\blk00000001/sig000000cf ),
.O(\NLW_blk00000001/blk0000004e_O_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000cd ),
.Q(\blk00000001/sig000000c9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000cc ),
.Q(\blk00000001/sig000000c8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000012d ),
.Q(\blk00000001/sig000000cc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000012c ),
.Q(\blk00000001/sig000000cd )
);
MUXF7 \blk00000001/blk00000049 (
.I0(\blk00000001/sig00000131 ),
.I1(\blk00000001/sig0000012f ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig0000012d )
);
MUXF7 \blk00000001/blk00000048 (
.I0(\blk00000001/sig00000130 ),
.I1(\blk00000001/sig0000012e ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig0000012c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000047 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000120 ),
.Q(\blk00000001/sig000000c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000046 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000012b ),
.Q(\blk00000001/sig00000127 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000045 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000012a ),
.Q(\blk00000001/sig000000cf )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig0000003a ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000121 ),
.O(\blk00000001/sig0000012b )
);
MUXCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig0000012b ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000122 ),
.O(\blk00000001/sig0000012a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000042 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000129 ),
.Q(\blk00000001/sig00000126 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000041 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000128 ),
.Q(\blk00000001/sig00000125 )
);
MUXCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig0000003a ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000123 ),
.O(\blk00000001/sig00000129 )
);
MUXCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig00000129 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig00000124 ),
.O(\blk00000001/sig00000128 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000dd ),
.Q(\blk00000001/sig000000d0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000000d1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000000d2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000000d3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e1 ),
.Q(\blk00000001/sig000000d4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e2 ),
.Q(\blk00000001/sig000000d5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000038 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e3 ),
.Q(\blk00000001/sig000000d6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000037 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e4 ),
.Q(\blk00000001/sig000000d7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000036 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e5 ),
.Q(\blk00000001/sig000000d8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000035 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig000000d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000034 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig000000da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000033 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig000000db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000032 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000e9 ),
.Q(\blk00000001/sig000000dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000031 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000011e ),
.Q(\blk00000001/sig000000dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000030 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000011c ),
.Q(\blk00000001/sig000000de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002f (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig000000df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002e (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig000000e0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002d (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig000000e1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002c (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig000000e2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002b (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000112 ),
.Q(\blk00000001/sig000000e3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002a (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig000000e4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig000000e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig000000e6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig000000e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000108 ),
.Q(\blk00000001/sig000000e8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000106 ),
.Q(\blk00000001/sig000000e9 )
);
MUXCY \blk00000001/blk00000024 (
.CI(s_axis_divisor_tdata[12]),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000ea ),
.O(\blk00000001/sig0000011f )
);
XORCY \blk00000001/blk00000023 (
.CI(s_axis_divisor_tdata[12]),
.LI(\blk00000001/sig000000ea ),
.O(\blk00000001/sig0000011e )
);
MUXCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig0000011f ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000eb ),
.O(\blk00000001/sig0000011d )
);
XORCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig0000011f ),
.LI(\blk00000001/sig000000eb ),
.O(\blk00000001/sig0000011c )
);
MUXCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig0000011d ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000ec ),
.O(\blk00000001/sig0000011b )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig0000011d ),
.LI(\blk00000001/sig000000ec ),
.O(\blk00000001/sig0000011a )
);
MUXCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig0000011b ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000ed ),
.O(\blk00000001/sig00000119 )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig0000011b ),
.LI(\blk00000001/sig000000ed ),
.O(\blk00000001/sig00000118 )
);
MUXCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig00000119 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000ee ),
.O(\blk00000001/sig00000117 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig00000119 ),
.LI(\blk00000001/sig000000ee ),
.O(\blk00000001/sig00000116 )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig00000117 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000ef ),
.O(\blk00000001/sig00000115 )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig00000117 ),
.LI(\blk00000001/sig000000ef ),
.O(\blk00000001/sig00000114 )
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig00000115 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig00000113 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig00000115 ),
.LI(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig00000112 )
);
MUXCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig00000113 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f1 ),
.O(\blk00000001/sig00000111 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig00000113 ),
.LI(\blk00000001/sig000000f1 ),
.O(\blk00000001/sig00000110 )
);
MUXCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig00000111 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig0000010f )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig00000111 ),
.LI(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig0000010e )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000010f ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f3 ),
.O(\blk00000001/sig0000010d )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000010f ),
.LI(\blk00000001/sig000000f3 ),
.O(\blk00000001/sig0000010c )
);
MUXCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig0000010d ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig0000010b )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000010d ),
.LI(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig0000010a )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig0000010b ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig000000f5 ),
.O(\blk00000001/sig00000109 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig0000010b ),
.LI(\blk00000001/sig000000f5 ),
.O(\blk00000001/sig00000108 )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000109 ),
.DI(\blk00000001/sig0000051d ),
.S(\blk00000001/sig0000051d ),
.O(\blk00000001/sig00000107 )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000109 ),
.LI(\blk00000001/sig0000051d ),
.O(\blk00000001/sig00000106 )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig00000107 ),
.LI(\blk00000001/sig0000051d ),
.O(\NLW_blk00000001/blk0000000a_O_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig000000c8 ),
.Q(\blk00000001/sig000000fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000102 ),
.Q(\blk00000001/sig000000fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig000000ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000104 ),
.Q(\blk00000001/sig00000100 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(aclk),
.CE(\blk00000001/sig0000003a ),
.D(\blk00000001/sig00000105 ),
.Q(\blk00000001/sig00000101 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(aclk),
.D(\blk00000001/sig00000039 ),
.Q(\blk00000001/sig0000003e )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig0000051d )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig0000003a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000c0 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006b6 ),
.Q(\blk00000001/sig0000006f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000bf (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006b7 ),
.Q(\blk00000001/sig00000070 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000be (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006b8 ),
.Q(\blk00000001/sig00000071 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000bd (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006b9 ),
.Q(\blk00000001/sig00000072 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000bc (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006ba ),
.Q(\blk00000001/sig00000073 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000bb (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006bb ),
.Q(\blk00000001/sig00000074 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000ba (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006bc ),
.Q(\blk00000001/sig00000075 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b9 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006bd ),
.Q(\blk00000001/sig00000076 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b8 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006be ),
.Q(\blk00000001/sig00000077 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b7 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006bf ),
.Q(\blk00000001/sig00000078 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b6 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006c0 ),
.Q(\blk00000001/sig00000079 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b5 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006c1 ),
.Q(\blk00000001/sig0000007a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b4 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006c2 ),
.Q(\blk00000001/sig0000007b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae/blk000000b3 (
.C(aclk),
.D(\blk00000001/blk000000ae/sig000006c3 ),
.Q(\blk00000001/sig0000007c )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PREG ( 0 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000000ae/blk000000b2 (
.CECARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.RSTC(\blk00000001/blk000000ae/sig000006d6 ),
.RSTCARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.CED(\blk00000001/blk000000ae/sig000006d6 ),
.RSTD(\blk00000001/blk000000ae/sig000006d6 ),
.CEOPMODE(\blk00000001/blk000000ae/sig000006d6 ),
.CEC(\blk00000001/blk000000ae/sig000006d6 ),
.CARRYOUTF(\NLW_blk00000001/blk000000ae/blk000000b2_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/blk000000ae/sig000006d6 ),
.RSTM(\blk00000001/blk000000ae/sig000006d6 ),
.CLK(aclk),
.RSTB(\blk00000001/blk000000ae/sig000006d6 ),
.CEM(\blk00000001/blk000000ae/sig00000666 ),
.CEB(\blk00000001/blk000000ae/sig00000666 ),
.CARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.CEP(\blk00000001/blk000000ae/sig000006d6 ),
.CEA(\blk00000001/blk000000ae/sig00000666 ),
.CARRYOUT(\NLW_blk00000001/blk000000ae/blk000000b2_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk000000ae/sig000006d6 ),
.RSTP(\blk00000001/blk000000ae/sig000006d6 ),
.B({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/sig0000051d , \blk00000001/sig00000089 , \blk00000001/sig00000088 , \blk00000001/sig00000087 ,
\blk00000001/sig00000086 , \blk00000001/sig00000085 , \blk00000001/sig00000084 , \blk00000001/sig00000083 , \blk00000001/sig00000082 ,
\blk00000001/sig00000081 , \blk00000001/sig00000080 , \blk00000001/sig0000007f , \blk00000001/sig0000007e , \blk00000001/sig0000007d }),
.BCOUT({\blk00000001/blk000000ae/sig000006d5 , \blk00000001/blk000000ae/sig000006d4 , \blk00000001/blk000000ae/sig000006d3 ,
\blk00000001/blk000000ae/sig000006d2 , \blk00000001/blk000000ae/sig000006d1 , \blk00000001/blk000000ae/sig000006d0 ,
\blk00000001/blk000000ae/sig000006cf , \blk00000001/blk000000ae/sig000006ce , \blk00000001/blk000000ae/sig000006cd ,
\blk00000001/blk000000ae/sig000006cc , \blk00000001/blk000000ae/sig000006cb , \blk00000001/blk000000ae/sig000006ca ,
\blk00000001/blk000000ae/sig000006c9 , \blk00000001/blk000000ae/sig000006c8 , \blk00000001/blk000000ae/sig000006c7 ,
\blk00000001/blk000000ae/sig000006c6 , \blk00000001/blk000000ae/sig000006c5 , \blk00000001/blk000000ae/sig000006c4 }),
.PCIN({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 }),
.C({\NLW_blk00000001/blk000000ae/blk000000b2_C<47>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<45>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<43>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<41>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<39>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<37>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<35>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<33>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<31>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<29>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<27>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<25>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<23>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<21>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<19>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<17>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<15>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<13>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<11>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<9>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<7>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<5>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<3>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_C<1>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_C<0>_UNCONNECTED }),
.P({\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b4 , \blk00000001/blk000000ae/sig000006b3 ,
\blk00000001/blk000000ae/sig000006b2 , \blk00000001/blk000000ae/sig000006b1 , \blk00000001/blk000000ae/sig000006b0 ,
\blk00000001/blk000000ae/sig000006af , \blk00000001/blk000000ae/sig000006ae , \blk00000001/blk000000ae/sig000006ad ,
\blk00000001/blk000000ae/sig000006ac , \blk00000001/blk000000ae/sig000006ab , \blk00000001/blk000000ae/sig000006aa ,
\blk00000001/blk000000ae/sig000006a9 , \blk00000001/blk000000ae/sig000006a8 , \blk00000001/blk000000ae/sig000006a7 ,
\blk00000001/blk000000ae/sig000006a6 , \blk00000001/blk000000ae/sig000006a5 , \blk00000001/blk000000ae/sig000006a4 ,
\blk00000001/blk000000ae/sig000006a3 , \blk00000001/blk000000ae/sig000006a2 , \blk00000001/blk000000ae/sig000006a1 ,
\blk00000001/blk000000ae/sig000006a0 , \blk00000001/blk000000ae/sig0000069f , \blk00000001/blk000000ae/sig0000069e ,
\blk00000001/blk000000ae/sig0000069d , \blk00000001/blk000000ae/sig0000069c , \blk00000001/blk000000ae/sig0000069b ,
\blk00000001/blk000000ae/sig0000069a , \blk00000001/blk000000ae/sig00000699 , \blk00000001/blk000000ae/sig00000698 ,
\blk00000001/blk000000ae/sig00000697 , \NLW_blk00000001/blk000000ae/blk000000b2_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_P<15>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_P<14>_UNCONNECTED ,
\blk00000001/blk000000ae/sig000006c3 , \blk00000001/blk000000ae/sig000006c2 , \blk00000001/blk000000ae/sig000006c1 ,
\blk00000001/blk000000ae/sig000006c0 , \blk00000001/blk000000ae/sig000006bf , \blk00000001/blk000000ae/sig000006be ,
\blk00000001/blk000000ae/sig000006bd , \blk00000001/blk000000ae/sig000006bc , \blk00000001/blk000000ae/sig000006bb ,
\blk00000001/blk000000ae/sig000006ba , \blk00000001/blk000000ae/sig000006b9 , \blk00000001/blk000000ae/sig000006b8 ,
\blk00000001/blk000000ae/sig000006b7 , \blk00000001/blk000000ae/sig000006b6 }),
.OPMODE({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig00000666 }),
.D({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 }),
.PCOUT({\blk00000001/blk000000ae/sig00000696 , \blk00000001/blk000000ae/sig00000695 , \blk00000001/blk000000ae/sig00000694 ,
\blk00000001/blk000000ae/sig00000693 , \blk00000001/blk000000ae/sig00000692 , \blk00000001/blk000000ae/sig00000691 ,
\blk00000001/blk000000ae/sig00000690 , \blk00000001/blk000000ae/sig0000068f , \blk00000001/blk000000ae/sig0000068e ,
\blk00000001/blk000000ae/sig0000068d , \blk00000001/blk000000ae/sig0000068c , \blk00000001/blk000000ae/sig0000068b ,
\blk00000001/blk000000ae/sig0000068a , \blk00000001/blk000000ae/sig00000689 , \blk00000001/blk000000ae/sig00000688 ,
\blk00000001/blk000000ae/sig00000687 , \blk00000001/blk000000ae/sig00000686 , \blk00000001/blk000000ae/sig00000685 ,
\blk00000001/blk000000ae/sig00000684 , \blk00000001/blk000000ae/sig00000683 , \blk00000001/blk000000ae/sig00000682 ,
\blk00000001/blk000000ae/sig00000681 , \blk00000001/blk000000ae/sig00000680 , \blk00000001/blk000000ae/sig0000067f ,
\blk00000001/blk000000ae/sig0000067e , \blk00000001/blk000000ae/sig0000067d , \blk00000001/blk000000ae/sig0000067c ,
\blk00000001/blk000000ae/sig0000067b , \blk00000001/blk000000ae/sig0000067a , \blk00000001/blk000000ae/sig00000679 ,
\blk00000001/blk000000ae/sig00000678 , \blk00000001/blk000000ae/sig00000677 , \blk00000001/blk000000ae/sig00000676 ,
\blk00000001/blk000000ae/sig00000675 , \blk00000001/blk000000ae/sig00000674 , \blk00000001/blk000000ae/sig00000673 ,
\blk00000001/blk000000ae/sig00000672 , \blk00000001/blk000000ae/sig00000671 , \blk00000001/blk000000ae/sig00000670 ,
\blk00000001/blk000000ae/sig0000066f , \blk00000001/blk000000ae/sig0000066e , \blk00000001/blk000000ae/sig0000066d ,
\blk00000001/blk000000ae/sig0000066c , \blk00000001/blk000000ae/sig0000066b , \blk00000001/blk000000ae/sig0000066a ,
\blk00000001/blk000000ae/sig00000669 , \blk00000001/blk000000ae/sig00000668 , \blk00000001/blk000000ae/sig00000667 }),
.A({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 ,
\blk00000001/sig00000097 , \blk00000001/sig00000096 , \blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 ,
\blk00000001/sig00000092 , \blk00000001/sig00000091 , \blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e ,
\blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b , \blk00000001/sig0000008a }),
.M({\NLW_blk00000001/blk000000ae/blk000000b2_M<35>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<33>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<31>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<29>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<27>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<25>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<23>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<21>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<19>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<17>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<15>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<13>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<11>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<9>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<7>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<5>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<3>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b2_M<1>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b2_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 1 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 0 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk000000ae/blk000000b1 (
.CECARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.RSTC(\blk00000001/blk000000ae/sig000006d6 ),
.RSTCARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.CED(\blk00000001/blk000000ae/sig000006d6 ),
.RSTD(\blk00000001/blk000000ae/sig000006d6 ),
.CEOPMODE(\blk00000001/blk000000ae/sig000006d6 ),
.CEC(\blk00000001/blk000000ae/sig000006d6 ),
.CARRYOUTF(\NLW_blk00000001/blk000000ae/blk000000b1_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/blk000000ae/sig000006d6 ),
.RSTM(\blk00000001/blk000000ae/sig000006d6 ),
.CLK(aclk),
.RSTB(\blk00000001/blk000000ae/sig000006d6 ),
.CEM(\blk00000001/blk000000ae/sig000006d6 ),
.CEB(\blk00000001/blk000000ae/sig00000666 ),
.CARRYIN(\blk00000001/blk000000ae/sig000006d6 ),
.CEP(\blk00000001/blk000000ae/sig00000666 ),
.CEA(\blk00000001/blk000000ae/sig00000666 ),
.CARRYOUT(\NLW_blk00000001/blk000000ae/blk000000b1_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk000000ae/sig000006d6 ),
.RSTP(\blk00000001/blk000000ae/sig000006d6 ),
.B({\blk00000001/blk000000ae/sig000006d5 , \blk00000001/blk000000ae/sig000006d4 , \blk00000001/blk000000ae/sig000006d3 ,
\blk00000001/blk000000ae/sig000006d2 , \blk00000001/blk000000ae/sig000006d1 , \blk00000001/blk000000ae/sig000006d0 ,
\blk00000001/blk000000ae/sig000006cf , \blk00000001/blk000000ae/sig000006ce , \blk00000001/blk000000ae/sig000006cd ,
\blk00000001/blk000000ae/sig000006cc , \blk00000001/blk000000ae/sig000006cb , \blk00000001/blk000000ae/sig000006ca ,
\blk00000001/blk000000ae/sig000006c9 , \blk00000001/blk000000ae/sig000006c8 , \blk00000001/blk000000ae/sig000006c7 ,
\blk00000001/blk000000ae/sig000006c6 , \blk00000001/blk000000ae/sig000006c5 , \blk00000001/blk000000ae/sig000006c4 }),
.BCOUT({\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/blk000000ae/sig00000696 , \blk00000001/blk000000ae/sig00000695 , \blk00000001/blk000000ae/sig00000694 ,
\blk00000001/blk000000ae/sig00000693 , \blk00000001/blk000000ae/sig00000692 , \blk00000001/blk000000ae/sig00000691 ,
\blk00000001/blk000000ae/sig00000690 , \blk00000001/blk000000ae/sig0000068f , \blk00000001/blk000000ae/sig0000068e ,
\blk00000001/blk000000ae/sig0000068d , \blk00000001/blk000000ae/sig0000068c , \blk00000001/blk000000ae/sig0000068b ,
\blk00000001/blk000000ae/sig0000068a , \blk00000001/blk000000ae/sig00000689 , \blk00000001/blk000000ae/sig00000688 ,
\blk00000001/blk000000ae/sig00000687 , \blk00000001/blk000000ae/sig00000686 , \blk00000001/blk000000ae/sig00000685 ,
\blk00000001/blk000000ae/sig00000684 , \blk00000001/blk000000ae/sig00000683 , \blk00000001/blk000000ae/sig00000682 ,
\blk00000001/blk000000ae/sig00000681 , \blk00000001/blk000000ae/sig00000680 , \blk00000001/blk000000ae/sig0000067f ,
\blk00000001/blk000000ae/sig0000067e , \blk00000001/blk000000ae/sig0000067d , \blk00000001/blk000000ae/sig0000067c ,
\blk00000001/blk000000ae/sig0000067b , \blk00000001/blk000000ae/sig0000067a , \blk00000001/blk000000ae/sig00000679 ,
\blk00000001/blk000000ae/sig00000678 , \blk00000001/blk000000ae/sig00000677 , \blk00000001/blk000000ae/sig00000676 ,
\blk00000001/blk000000ae/sig00000675 , \blk00000001/blk000000ae/sig00000674 , \blk00000001/blk000000ae/sig00000673 ,
\blk00000001/blk000000ae/sig00000672 , \blk00000001/blk000000ae/sig00000671 , \blk00000001/blk000000ae/sig00000670 ,
\blk00000001/blk000000ae/sig0000066f , \blk00000001/blk000000ae/sig0000066e , \blk00000001/blk000000ae/sig0000066d ,
\blk00000001/blk000000ae/sig0000066c , \blk00000001/blk000000ae/sig0000066b , \blk00000001/blk000000ae/sig0000066a ,
\blk00000001/blk000000ae/sig00000669 , \blk00000001/blk000000ae/sig00000668 , \blk00000001/blk000000ae/sig00000667 }),
.C({\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 , \blk00000001/blk000000ae/sig000006b5 ,
\blk00000001/blk000000ae/sig000006b4 , \blk00000001/blk000000ae/sig000006b3 , \blk00000001/blk000000ae/sig000006b2 ,
\blk00000001/blk000000ae/sig000006b1 , \blk00000001/blk000000ae/sig000006b0 , \blk00000001/blk000000ae/sig000006af ,
\blk00000001/blk000000ae/sig000006ae , \blk00000001/blk000000ae/sig000006ad , \blk00000001/blk000000ae/sig000006ac ,
\blk00000001/blk000000ae/sig000006ab , \blk00000001/blk000000ae/sig000006aa , \blk00000001/blk000000ae/sig000006a9 ,
\blk00000001/blk000000ae/sig000006a8 , \blk00000001/blk000000ae/sig000006a7 , \blk00000001/blk000000ae/sig000006a6 ,
\blk00000001/blk000000ae/sig000006a5 , \blk00000001/blk000000ae/sig000006a4 , \blk00000001/blk000000ae/sig000006a3 ,
\blk00000001/blk000000ae/sig000006a2 , \blk00000001/blk000000ae/sig000006a1 , \blk00000001/blk000000ae/sig000006a0 ,
\blk00000001/blk000000ae/sig0000069f , \blk00000001/blk000000ae/sig0000069e , \blk00000001/blk000000ae/sig0000069d ,
\blk00000001/blk000000ae/sig0000069c , \blk00000001/blk000000ae/sig0000069b , \blk00000001/blk000000ae/sig0000069a ,
\blk00000001/blk000000ae/sig00000699 , \blk00000001/blk000000ae/sig00000698 , \blk00000001/blk000000ae/sig00000697 }),
.P({\NLW_blk00000001/blk000000ae/blk000000b1_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<43>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<37>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<35>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<33>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<31>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<29>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<27>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<25>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<23>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<21>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<19>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_P<17>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_P<16>_UNCONNECTED ,
\blk00000001/blk000000ae/sig00000618 , \blk00000001/blk000000ae/sig00000619 , \blk00000001/blk000000ae/sig0000061a ,
\blk00000001/blk000000ae/sig0000061b , \blk00000001/blk000000ae/sig0000061c , \blk00000001/blk000000ae/sig0000061d ,
\blk00000001/blk000000ae/sig0000061e , \blk00000001/blk000000ae/sig0000061f , \blk00000001/blk000000ae/sig00000620 ,
\blk00000001/blk000000ae/sig00000621 , \blk00000001/blk000000ae/sig00000622 , \blk00000001/blk000000ae/sig00000623 ,
\blk00000001/blk000000ae/sig00000624 , \blk00000001/blk000000ae/sig00000625 , \blk00000001/blk000000ae/sig00000626 ,
\blk00000001/blk000000ae/sig00000627 }),
.OPMODE({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig00000666 , \blk00000001/blk000000ae/sig00000666 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig00000666 }),
.D({\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 ,
\blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 , \blk00000001/blk000000ae/sig000006d6 }),
.PCOUT({\blk00000001/blk000000ae/sig00000636 , \blk00000001/blk000000ae/sig00000637 , \blk00000001/blk000000ae/sig00000638 ,
\blk00000001/blk000000ae/sig00000639 , \blk00000001/blk000000ae/sig0000063a , \blk00000001/blk000000ae/sig0000063b ,
\blk00000001/blk000000ae/sig0000063c , \blk00000001/blk000000ae/sig0000063d , \blk00000001/blk000000ae/sig0000063e ,
\blk00000001/blk000000ae/sig0000063f , \blk00000001/blk000000ae/sig00000640 , \blk00000001/blk000000ae/sig00000641 ,
\blk00000001/blk000000ae/sig00000642 , \blk00000001/blk000000ae/sig00000643 , \blk00000001/blk000000ae/sig00000644 ,
\blk00000001/blk000000ae/sig00000645 , \blk00000001/blk000000ae/sig00000646 , \blk00000001/blk000000ae/sig00000647 ,
\blk00000001/blk000000ae/sig00000648 , \blk00000001/blk000000ae/sig00000649 , \blk00000001/blk000000ae/sig0000064a ,
\blk00000001/blk000000ae/sig0000064b , \blk00000001/blk000000ae/sig0000064c , \blk00000001/blk000000ae/sig0000064d ,
\blk00000001/blk000000ae/sig0000064e , \blk00000001/blk000000ae/sig0000064f , \blk00000001/blk000000ae/sig00000650 ,
\blk00000001/blk000000ae/sig00000651 , \blk00000001/blk000000ae/sig00000652 , \blk00000001/blk000000ae/sig00000653 ,
\blk00000001/blk000000ae/sig00000654 , \blk00000001/blk000000ae/sig00000655 , \blk00000001/blk000000ae/sig00000656 ,
\blk00000001/blk000000ae/sig00000657 , \blk00000001/blk000000ae/sig00000658 , \blk00000001/blk000000ae/sig00000659 ,
\blk00000001/blk000000ae/sig0000065a , \blk00000001/blk000000ae/sig0000065b , \blk00000001/blk000000ae/sig0000065c ,
\blk00000001/blk000000ae/sig0000065d , \blk00000001/blk000000ae/sig0000065e , \blk00000001/blk000000ae/sig0000065f ,
\blk00000001/blk000000ae/sig00000660 , \blk00000001/blk000000ae/sig00000661 , \blk00000001/blk000000ae/sig00000662 ,
\blk00000001/blk000000ae/sig00000663 , \blk00000001/blk000000ae/sig00000664 , \blk00000001/blk000000ae/sig00000665 }),
.A({\blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c ,
\blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c ,
\blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009c ,
\blk00000001/sig0000009c , \blk00000001/sig0000009c , \blk00000001/sig0000009b }),
.M({\NLW_blk00000001/blk000000ae/blk000000b1_M<35>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<33>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<31>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<29>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<27>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<25>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<23>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<21>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<19>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<17>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<15>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<13>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<11>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<9>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<7>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<5>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<3>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ae/blk000000b1_M<1>_UNCONNECTED , \NLW_blk00000001/blk000000ae/blk000000b1_M<0>_UNCONNECTED })
);
GND \blk00000001/blk000000ae/blk000000b0 (
.G(\blk00000001/blk000000ae/sig000006d6 )
);
VCC \blk00000001/blk000000ae/blk000000af (
.P(\blk00000001/blk000000ae/sig00000666 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_register_slice_v2_1_7_axi_register_slice,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_s00_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "zc702_s00_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_s00_regslice_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [11 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2bb2o (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
|
`timescale 1ns / 1ps
`default_nettype none
`include "clk_gen.v"
`include "monopix_core.v"
`include "utils/bus_to_ip.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/reset_gen.v"
`include "utils/CG_MOD_pos.v"
`include "spi/spi_core.v"
`include "spi/spi.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "gpio/gpio.v"
`include "tlu/tlu_controller.v"
`include "tlu/tlu_controller_core.v"
`include "tlu/tlu_controller_fsm.v"
`include "timestamp/timestamp.v"
`include "timestamp/timestamp_core.v"
`include "timestamp640/timestamp640.v"
`include "timestamp640/timestamp640_core.v"
`include "utils/fx2_to_bus.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "sram_fifo/sram_fifo_core.v"
`include "sram_fifo/sram_fifo.v"
`include "utils/3_stage_synchronizer.v"
`include "rrp_arbiter/rrp_arbiter.v"
`include "utils/ddr_des.v"
`include "utils/flag_domain_crossing.v"
`include "mono_data_rx/mono_data_rx.v"
`include "mono_data_rx/mono_data_rx_core.v"
`include "utils/cdc_reset_sync.v"
`ifdef COCOTB_SIM //for simulation
`include "utils/ODDR_sim.v"
`include "utils/IDDR_sim.v"
`include "utils/DCM_sim.v"
`include "utils/clock_multiplier.v"
`include "utils/BUFG_sim.v"
`include "utils/RAMB16_S1_S9_sim.v"
`else
`include "utils/IDDR_s3.v"
`include "utils/ODDR_s3.v"
`endif
module monopix_mio (
input wire FCLK_IN, // 48MHz
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FDATA,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//LED
output wire [4:0] LED,
//SRAM
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
input wire [2:0] LEMO_RX,
output wire [2:0] LEMO_TX, // TX[0] == RJ45 trigger clock output, TX[1] == RJ45 busy output
input wire RJ45_RESET,
input wire RJ45_TRIGGER,
input wire SR_OUT, //DIN4
output wire SR_IN, //DOUT11
output wire LDPIX, //DOUT15
output wire CKCONF, //DOUT10
output wire LDDAC, //DOUT12
output wire SR_EN, //DOUT13
output wire RESET, //DOUT14
output wire INJECTION,
input wire MONITOR, //DIN1
output wire CLK_BX, //DOUT1
output wire READ, //DOUT2
output wire FREEZE, //DOUT3
output wire nRST, //DOUT4
output wire EN_TEST_PATTERN, //DOUT5
output wire RST_GRAY, //DOUT6
output wire EN_DRIVER, //DOUT7
output wire EN_DATA_CMOS, //DOUT8
output wire CLK_OUT, //DOUT9
input wire TOKEN, //DIN2
input wire DATA, //DIN0
input wire DATA_LVDS, //DIN8_LVDS0
output wire DEBUG, //DOUT0
// I2C
inout wire SDA,
inout wire SCL
);
assign SDA = 1'bz;
assign SCL = 1'bz;
// ------- RESRT/CLOCK ------- //
wire BUS_RST;
(* KEEP = "{TRUE}" *)
wire CLK320;
(* KEEP = "{TRUE}" *)
wire CLK160;
(* KEEP = "{TRUE}" *)
wire CLK40;
(* KEEP = "{TRUE}" *)
wire CLK16;
(* KEEP = "{TRUE}" *)
wire BUS_CLK;
(* KEEP = "{TRUE}" *)
wire CLK8;
reset_gen reset_gen(.CLK(BUS_CLK), .RST(BUS_RST));
wire CLK_LOCKED;
clk_gen clk_gen(
.CLKIN(FCLK_IN),
.BUS_CLK(BUS_CLK),
.U1_CLK8(CLK8),
.U2_CLK40(CLK40),
.U2_CLK16(CLK16),
.U2_CLK160(CLK160),
.U2_CLK320(CLK320),
.U2_LOCKED(CLK_LOCKED)
);
// ------- MODULE ADREESSES ------- //
localparam FIFO_BASEADDR = 16'h8000;
localparam FIFO_HIGHADDR = 16'h9000-1;
// ------- BUS SYGNALING ------- //
wire [15:0] BUS_ADD;
wire BUS_RD, BUS_WR;
// ------- BUS SYGNALING ------- //
fx2_to_bus fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
// ------- USER MODULES ------- //
wire FIFO_NEAR_FULL,FIFO_FULL;
wire USB_READ;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
assign USB_READ = FREAD & FSTROBE;
sram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR)
) sram_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(FDATA),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR()
);
monopix_core i_monopix_core(
//local bus
.BUS_CLK(BUS_CLK),
.BUS_DATA(BUS_DATA),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_RST(BUS_RST),
//clocks
.CLK8(CLK8),
.CLK40(CLK40),
.CLK16(CLK16),
.CLK160(CLK160),
.CLK320(CLK320),
//fifo
.ARB_READY_OUT(ARB_READY_OUT),
.ARB_WRITE_OUT(ARB_WRITE_OUT),
.ARB_DATA_OUT(ARB_DATA_OUT),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
//LED
.LED(LED[4:0]),
.LEMO_RX(LEMO_RX),
.LEMO_TX(LEMO_TX), // TX[0] == RJ45 trigger clock output, TX[1] == RJ45 busy output
.RJ45_RESET(RJ45_RESET),
.RJ45_TRIGGER(RJ45_TRIGGER),
.SR_OUT(SR_OUT), //DIN4
.SR_IN(SR_IN), //DOUT11
.LDPIX(LDPIX), //DOUT15
.CKCONF(CKCONF), //DOUT10
.LDDAC(LDDAC), //DOUT12
.SR_EN(SR_EN), //DOUT13
.RESET(RESET), //DOUT14
.INJECTION(INJECTION),
.MONITOR(MONITOR), //DIN1
.CLK_BX(CLK_BX), //DOUT1
.READ(READ), //DOUT2
.FREEZE(FREEZE), //DOUT3
.nRST(nRST), //DOUT4
.EN_TEST_PATTERN(EN_TEST_PATTERN), //DOUT5
.RST_GRAY(RST_GRAY), //DOUT6
.EN_DRIVER(EN_DRIVER), //DOUT7
.EN_DATA_CMOS(EN_DATA_CMOS), //DOUT8
.CLK_OUT(CLK_OUT), //DOUT9
.TOKEN(TOKEN), //DIN2
.DATA(DATA), //DIN0
.DATA_LVDS(DATA_LVDS), //DIN8_LVDS0
.DEBUG(DEBUG) //nc
);
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (which mostly works), and
Scheme (a bit out of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
magic declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(** $Date: 2016-05-26 12:03:56 -0400 (Thu, 26 May 2016) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:44:08 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_sim_netlist.v
// Design : design_1_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd
(m_valid_i,
SR,
aa_grant_rnw,
D,
any_error,
Q,
\m_ready_d_reg[2] ,
s_axi_bvalid,
m_ready_d0,
m_axi_bready,
\gen_axilite.s_axi_bvalid_i_reg ,
s_axi_wready,
m_axi_wvalid,
\m_ready_d_reg[2]_0 ,
\gen_axilite.s_axi_awready_i_reg ,
m_axi_awvalid,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
s_ready_i_reg,
E,
m_axi_arvalid,
s_ready_i_reg_0,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
aclk,
aresetn_d,
m_ready_d,
\gen_axilite.s_axi_awready_i_reg_0 ,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
s_axi_bready,
\m_atarget_hot_reg[1] ,
\gen_axilite.s_axi_awready_i_reg_1 ,
s_axi_wvalid,
m_valid_i_reg,
m_ready_d_0,
\gen_axilite.s_axi_arready_i_reg ,
aa_rready,
\gen_axilite.s_axi_rvalid_i_reg ,
s_axi_rready,
sr_rvalid,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
\m_ready_d_reg[1] ,
s_axi_awvalid);
output m_valid_i;
output [0:0]SR;
output aa_grant_rnw;
output [2:0]D;
output any_error;
output [34:0]Q;
output \m_ready_d_reg[2] ;
output [0:0]s_axi_bvalid;
output [0:0]m_ready_d0;
output [1:0]m_axi_bready;
output \gen_axilite.s_axi_bvalid_i_reg ;
output [0:0]s_axi_wready;
output [1:0]m_axi_wvalid;
output \m_ready_d_reg[2]_0 ;
output \gen_axilite.s_axi_awready_i_reg ;
output [1:0]m_axi_awvalid;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
output s_ready_i_reg;
output [0:0]E;
output [1:0]m_axi_arvalid;
output s_ready_i_reg_0;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
input aclk;
input aresetn_d;
input [2:0]m_ready_d;
input \gen_axilite.s_axi_awready_i_reg_0 ;
input \gen_axilite.s_axi_bvalid_i_reg_0 ;
input [0:0]s_axi_bready;
input [1:0]\m_atarget_hot_reg[1] ;
input \gen_axilite.s_axi_awready_i_reg_1 ;
input [0:0]s_axi_wvalid;
input m_valid_i_reg;
input [1:0]m_ready_d_0;
input \gen_axilite.s_axi_arready_i_reg ;
input aa_rready;
input \gen_axilite.s_axi_rvalid_i_reg ;
input [0:0]s_axi_rready;
input sr_rvalid;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input \m_ready_d_reg[1] ;
input [0:0]s_axi_awvalid;
wire [2:0]D;
wire [0:0]E;
wire [34:0]Q;
wire [0:0]SR;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire any_error;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_reg ;
wire \gen_axilite.s_axi_awready_i_reg ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_awready_i_reg_1 ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_axilite.s_axi_rvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
wire \m_atarget_enc[1]_i_2_n_0 ;
wire \m_atarget_enc[1]_i_3_n_0 ;
wire \m_atarget_enc[1]_i_4_n_0 ;
wire [1:0]\m_atarget_hot_reg[1] ;
wire [1:0]m_axi_arvalid;
wire [1:0]m_axi_awvalid;
wire [1:0]m_axi_bready;
wire [1:0]m_axi_wvalid;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [1:0]m_ready_d_0;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire p_0_in1_in;
wire [48:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire s_awvalid_reg;
wire \s_awvalid_reg[0]_i_1_n_0 ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire sr_rvalid;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFBFF))
\gen_axilite.s_axi_awready_i_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d[1]),
.I3(s_axi_wvalid),
.O(\gen_axilite.s_axi_awready_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0020))
\gen_axilite.s_axi_bvalid_i_i_2
(.I0(s_axi_bready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[0]),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h7))
\gen_axilite.s_axi_rvalid_i_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(s_ready_i_reg_0));
LUT6 #(
.INIT(64'hFFFFFF5300000050))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(SR));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[10]_i_1
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[9]),
.O(s_amesg[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[11]_i_1
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[10]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[12]_i_1
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[11]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[13]_i_1
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[12]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[14]_i_1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[13]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[15]_i_1
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[14]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[16]_i_1
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[15]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[17]_i_1
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[16]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[18]_i_1
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[17]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[19]_i_1
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[18]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[1]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[0]),
.O(s_amesg[1]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[20]_i_1
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[19]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[21]_i_1
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[20]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[22]_i_1
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[21]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[23]_i_1
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[22]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[24]_i_1
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[23]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[25]_i_1
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[24]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[26]_i_1
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[25]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[27]_i_1
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[26]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[28]_i_1
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[27]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[29]_i_1
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[28]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[2]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[1]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[30]_i_1
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[29]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[31]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[30]),
.O(s_amesg[31]));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_1
(.I0(aresetn_d),
.O(SR));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_2
(.I0(aa_grant_any),
.O(p_0_in1_in));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[32]_i_3
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[31]),
.O(s_amesg[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[3]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[2]),
.O(s_amesg[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[46]_i_1
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[0]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[47]_i_1
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[1]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[48]_i_1
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[2]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[4]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[3]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[5]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[4]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[6]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[5]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[7]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[6]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[8]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[7]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[9]_i_1
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[8]),
.O(s_amesg[9]));
FDRE \gen_no_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
.Q(Q[9]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
.Q(Q[10]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
.Q(Q[11]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
.Q(Q[12]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
.Q(Q[13]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
.Q(Q[14]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
.Q(Q[15]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
.Q(Q[16]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
.Q(Q[17]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
.Q(Q[18]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
.Q(Q[0]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
.Q(Q[19]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
.Q(Q[20]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
.Q(Q[21]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
.Q(Q[22]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
.Q(Q[23]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
.Q(Q[24]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
.Q(Q[25]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
.Q(Q[26]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
.Q(Q[27]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
.Q(Q[28]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
.Q(Q[1]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
.Q(Q[29]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
.Q(Q[30]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
.Q(Q[31]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
.Q(Q[2]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
.Q(Q[32]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
.Q(Q[33]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
.Q(Q[34]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
.Q(Q[3]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
.Q(Q[4]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
.Q(Q[5]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
.Q(Q[6]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
.Q(Q[7]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
.Q(Q[8]),
.R(SR));
LUT6 #(
.INIT(64'h0000000088888088))
\gen_no_arbiter.m_grant_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.I1(aresetn_d),
.I2(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
.I3(m_ready_d0),
.I4(\m_ready_d_reg[1] ),
.I5(\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hF0FE))
\gen_no_arbiter.m_grant_hot_i[0]_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_arvalid),
.I2(aa_grant_any),
.I3(m_valid_i),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'hB))
\gen_no_arbiter.m_grant_hot_i[0]_i_3
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h54000000))
\gen_no_arbiter.m_grant_hot_i[0]_i_5
(.I0(m_valid_i_reg),
.I1(m_ready_d_0[1]),
.I2(\gen_axilite.s_axi_arready_i_reg ),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ));
FDRE \gen_no_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
LUT6 #(
.INIT(64'h3AFA3A0A3AFA3AFA))
\gen_no_arbiter.m_valid_i_i_1
(.I0(aa_grant_any),
.I1(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(\m_ready_d_reg[1] ),
.I5(m_ready_d0),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0000FF80))
\gen_no_arbiter.m_valid_i_i_2
(.I0(\gen_axilite.s_axi_arready_i_reg ),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d_0[1]),
.I4(m_valid_i_reg),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
FDRE \gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h40))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(aresetn_d),
.O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
FDRE \gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFEFF))
\m_atarget_enc[1]_i_1
(.I0(\m_atarget_enc[1]_i_2_n_0 ),
.I1(\m_atarget_enc[1]_i_3_n_0 ),
.I2(\m_atarget_enc[1]_i_4_n_0 ),
.I3(Q[30]),
.I4(Q[23]),
.I5(Q[27]),
.O(any_error));
LUT4 #(
.INIT(16'hFFEF))
\m_atarget_enc[1]_i_2
(.I0(Q[25]),
.I1(Q[20]),
.I2(Q[21]),
.I3(Q[29]),
.O(\m_atarget_enc[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFD))
\m_atarget_enc[1]_i_3
(.I0(Q[24]),
.I1(Q[26]),
.I2(Q[19]),
.I3(Q[18]),
.O(\m_atarget_enc[1]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\m_atarget_enc[1]_i_4
(.I0(Q[17]),
.I1(Q[31]),
.I2(Q[22]),
.I3(Q[28]),
.O(\m_atarget_enc[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h04))
\m_atarget_hot[0]_i_1
(.I0(Q[16]),
.I1(aa_grant_any),
.I2(any_error),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h08))
\m_atarget_hot[1]_i_1
(.I0(Q[16]),
.I1(aa_grant_any),
.I2(any_error),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[3]_i_1
(.I0(any_error),
.I1(aa_grant_any),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[1] [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[1] [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[1] [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[1] [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[0]_INST_0
(.I0(\m_atarget_hot_reg[1] [0]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[1]_INST_0
(.I0(\m_atarget_hot_reg[1] [1]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[1] [0]),
.I1(s_axi_wvalid),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[1] [1]),
.I1(s_axi_wvalid),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[1]));
LUT5 #(
.INIT(32'h0080FFFF))
\m_payload_i[34]_i_1
(.I0(s_axi_rready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[0]),
.I4(sr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hF4F0F0F0))
\m_ready_d[2]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d[0]),
.I3(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I4(s_axi_bready),
.O(m_ready_d0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h4555))
\m_ready_d[2]_i_3
(.I0(m_ready_d[2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(\gen_axilite.s_axi_awready_i_reg_0 ),
.O(\m_ready_d_reg[2] ));
LUT5 #(
.INIT(32'h0B0F0F0F))
\m_ready_d[2]_i_4
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d[1]),
.I3(s_axi_wvalid),
.I4(\gen_axilite.s_axi_awready_i_reg_1 ),
.O(\m_ready_d_reg[2]_0 ));
LUT5 #(
.INIT(32'h8AAAAAAA))
m_valid_i_i_2
(.I0(aa_rready),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(\gen_axilite.s_axi_rvalid_i_reg ),
.O(s_ready_i_reg));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(aresetn_d),
.I3(s_ready_i),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
FDRE \s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000D00000))
\s_awvalid_reg[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_awvalid_reg),
.I2(s_axi_awvalid),
.I3(\s_arvalid_reg_reg_n_0_[0] ),
.I4(aresetn_d),
.I5(s_ready_i),
.O(\s_awvalid_reg[0]_i_1_n_0 ));
FDRE \s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
LUT5 #(
.INIT(32'h00000800))
\s_axi_bvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I2(m_ready_d[0]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(s_axi_bvalid));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(sr_rvalid),
.O(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00000800))
\s_axi_wready[0]_INST_0
(.I0(\gen_axilite.s_axi_awready_i_reg_1 ),
.I1(aa_grant_any),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(s_axi_wready));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "192'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "3" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [2:0]m_axi_awid;
output [95:0]m_axi_awaddr;
output [23:0]m_axi_awlen;
output [8:0]m_axi_awsize;
output [5:0]m_axi_awburst;
output [2:0]m_axi_awlock;
output [11:0]m_axi_awcache;
output [8:0]m_axi_awprot;
output [11:0]m_axi_awregion;
output [11:0]m_axi_awqos;
output [2:0]m_axi_awuser;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [2:0]m_axi_wid;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wlast;
output [2:0]m_axi_wuser;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [2:0]m_axi_bid;
input [5:0]m_axi_bresp;
input [2:0]m_axi_buser;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [2:0]m_axi_arid;
output [95:0]m_axi_araddr;
output [23:0]m_axi_arlen;
output [8:0]m_axi_arsize;
output [5:0]m_axi_arburst;
output [2:0]m_axi_arlock;
output [11:0]m_axi_arcache;
output [8:0]m_axi_arprot;
output [11:0]m_axi_arregion;
output [11:0]m_axi_arqos;
output [2:0]m_axi_aruser;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [2:0]m_axi_rid;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rlast;
input [2:0]m_axi_ruser;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [15:0]\^m_axi_araddr ;
wire [2:0]\^m_axi_arprot ;
wire [2:0]m_axi_arready;
wire [1:0]\^m_axi_arvalid ;
wire [95:80]\^m_axi_awaddr ;
wire [2:0]m_axi_awready;
wire [1:0]\^m_axi_awvalid ;
wire [1:0]\^m_axi_bready ;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [1:0]\^m_axi_rready ;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [1:0]\^m_axi_wvalid ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[95:80] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_araddr[63:48] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_araddr[31:16] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_arburst[5] = \<const0> ;
assign m_axi_arburst[4] = \<const0> ;
assign m_axi_arburst[3] = \<const0> ;
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[11] = \<const0> ;
assign m_axi_arcache[10] = \<const0> ;
assign m_axi_arcache[9] = \<const0> ;
assign m_axi_arcache[8] = \<const0> ;
assign m_axi_arcache[7] = \<const0> ;
assign m_axi_arcache[6] = \<const0> ;
assign m_axi_arcache[5] = \<const0> ;
assign m_axi_arcache[4] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[23] = \<const0> ;
assign m_axi_arlen[22] = \<const0> ;
assign m_axi_arlen[21] = \<const0> ;
assign m_axi_arlen[20] = \<const0> ;
assign m_axi_arlen[19] = \<const0> ;
assign m_axi_arlen[18] = \<const0> ;
assign m_axi_arlen[17] = \<const0> ;
assign m_axi_arlen[16] = \<const0> ;
assign m_axi_arlen[15] = \<const0> ;
assign m_axi_arlen[14] = \<const0> ;
assign m_axi_arlen[13] = \<const0> ;
assign m_axi_arlen[12] = \<const0> ;
assign m_axi_arlen[11] = \<const0> ;
assign m_axi_arlen[10] = \<const0> ;
assign m_axi_arlen[9] = \<const0> ;
assign m_axi_arlen[8] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_arqos[11] = \<const0> ;
assign m_axi_arqos[10] = \<const0> ;
assign m_axi_arqos[9] = \<const0> ;
assign m_axi_arqos[8] = \<const0> ;
assign m_axi_arqos[7] = \<const0> ;
assign m_axi_arqos[6] = \<const0> ;
assign m_axi_arqos[5] = \<const0> ;
assign m_axi_arqos[4] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[8] = \<const0> ;
assign m_axi_arsize[7] = \<const0> ;
assign m_axi_arsize[6] = \<const0> ;
assign m_axi_arsize[5] = \<const0> ;
assign m_axi_arsize[4] = \<const0> ;
assign m_axi_arsize[3] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid[2] = \<const0> ;
assign m_axi_arvalid[1:0] = \^m_axi_arvalid [1:0];
assign m_axi_awaddr[95:80] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[63:48] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[31:16] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_awburst[5] = \<const0> ;
assign m_axi_awburst[4] = \<const0> ;
assign m_axi_awburst[3] = \<const0> ;
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[11] = \<const0> ;
assign m_axi_awcache[10] = \<const0> ;
assign m_axi_awcache[9] = \<const0> ;
assign m_axi_awcache[8] = \<const0> ;
assign m_axi_awcache[7] = \<const0> ;
assign m_axi_awcache[6] = \<const0> ;
assign m_axi_awcache[5] = \<const0> ;
assign m_axi_awcache[4] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[23] = \<const0> ;
assign m_axi_awlen[22] = \<const0> ;
assign m_axi_awlen[21] = \<const0> ;
assign m_axi_awlen[20] = \<const0> ;
assign m_axi_awlen[19] = \<const0> ;
assign m_axi_awlen[18] = \<const0> ;
assign m_axi_awlen[17] = \<const0> ;
assign m_axi_awlen[16] = \<const0> ;
assign m_axi_awlen[15] = \<const0> ;
assign m_axi_awlen[14] = \<const0> ;
assign m_axi_awlen[13] = \<const0> ;
assign m_axi_awlen[12] = \<const0> ;
assign m_axi_awlen[11] = \<const0> ;
assign m_axi_awlen[10] = \<const0> ;
assign m_axi_awlen[9] = \<const0> ;
assign m_axi_awlen[8] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_awqos[11] = \<const0> ;
assign m_axi_awqos[10] = \<const0> ;
assign m_axi_awqos[9] = \<const0> ;
assign m_axi_awqos[8] = \<const0> ;
assign m_axi_awqos[7] = \<const0> ;
assign m_axi_awqos[6] = \<const0> ;
assign m_axi_awqos[5] = \<const0> ;
assign m_axi_awqos[4] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[8] = \<const0> ;
assign m_axi_awsize[7] = \<const0> ;
assign m_axi_awsize[6] = \<const0> ;
assign m_axi_awsize[5] = \<const0> ;
assign m_axi_awsize[4] = \<const0> ;
assign m_axi_awsize[3] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid[2] = \<const0> ;
assign m_axi_awvalid[1:0] = \^m_axi_awvalid [1:0];
assign m_axi_bready[2] = \<const0> ;
assign m_axi_bready[1:0] = \^m_axi_bready [1:0];
assign m_axi_rready[2] = \<const0> ;
assign m_axi_rready[1:0] = \^m_axi_rready [1:0];
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid[2] = \<const0> ;
assign m_axi_wvalid[1:0] = \^m_axi_wvalid [1:0];
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_arprot ,\^m_axi_awaddr ,\^m_axi_araddr }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(\^m_axi_arvalid ),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(\^m_axi_awvalid ),
.m_axi_bready(\^m_axi_bready ),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(\^m_axi_rready ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(\^m_axi_wvalid ),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd
(Q,
\s_axi_rdata[31] ,
s_axi_bvalid,
m_axi_bready,
s_axi_wready,
m_axi_wvalid,
m_axi_awvalid,
m_axi_arvalid,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
m_axi_rready,
s_axi_bresp,
s_axi_rready,
aresetn,
aclk,
s_axi_wvalid,
s_axi_bready,
m_axi_arready,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
m_axi_rvalid,
m_axi_rresp,
m_axi_rdata,
m_axi_bresp,
s_axi_awvalid);
output [34:0]Q;
output [33:0]\s_axi_rdata[31] ;
output [0:0]s_axi_bvalid;
output [1:0]m_axi_bready;
output [0:0]s_axi_wready;
output [1:0]m_axi_wvalid;
output [1:0]m_axi_awvalid;
output [1:0]m_axi_arvalid;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [1:0]m_axi_rready;
output [1:0]s_axi_bresp;
input [0:0]s_axi_rready;
input aresetn;
input aclk;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_bready;
input [2:0]m_axi_arready;
input [2:0]m_axi_awready;
input [2:0]m_axi_wready;
input [2:0]m_axi_bvalid;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [2:0]m_axi_rvalid;
input [5:0]m_axi_rresp;
input [95:0]m_axi_rdata;
input [5:0]m_axi_bresp;
input [0:0]s_axi_awvalid;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire addr_arbiter_inst_n_3;
wire addr_arbiter_inst_n_42;
wire addr_arbiter_inst_n_47;
wire addr_arbiter_inst_n_51;
wire addr_arbiter_inst_n_52;
wire addr_arbiter_inst_n_55;
wire addr_arbiter_inst_n_56;
wire addr_arbiter_inst_n_60;
wire any_error;
wire aresetn;
wire aresetn_d;
wire \gen_decerr.decerr_slave_inst_n_0 ;
wire \gen_decerr.decerr_slave_inst_n_1 ;
wire \gen_decerr.decerr_slave_inst_n_2 ;
wire \gen_decerr.decerr_slave_inst_n_3 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire [1:0]m_atarget_enc;
wire \m_atarget_enc[0]_i_1_n_0 ;
wire [3:0]m_atarget_hot;
wire [1:0]m_atarget_hot0;
wire [2:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire [2:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [1:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [1:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [2:0]m_ready_d_0;
wire m_valid_i;
wire p_1_in;
wire reg_slice_r_n_2;
wire reset;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_aw_n_0;
wire sr_rvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
(.D({addr_arbiter_inst_n_3,m_atarget_hot0}),
.E(p_1_in),
.Q(Q),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.any_error(any_error),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_3 ),
.\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_52),
.\gen_axilite.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_2 ),
.\gen_axilite.s_axi_awready_i_reg_1 (\gen_decerr.decerr_slave_inst_n_1 ),
.\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_47),
.\gen_axilite.s_axi_bvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_4 ),
.\gen_axilite.s_axi_rvalid_i_reg (\gen_decerr.decerr_slave_inst_n_5 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (addr_arbiter_inst_n_55),
.\m_atarget_hot_reg[1] (m_atarget_hot[1:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d_0),
.m_ready_d0(m_ready_d0),
.m_ready_d_0(m_ready_d),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_0 ),
.\m_ready_d_reg[2] (addr_arbiter_inst_n_42),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_51),
.m_valid_i(m_valid_i),
.m_valid_i_reg(reg_slice_r_n_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(addr_arbiter_inst_n_56),
.s_ready_i_reg_0(addr_arbiter_inst_n_60),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_enc),
.SR(reset),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_55),
.\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_47),
.\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_60),
.\gen_no_arbiter.grant_rnw_reg_2 (addr_arbiter_inst_n_52),
.\gen_no_arbiter.m_grant_hot_i_reg[0] (\gen_decerr.decerr_slave_inst_n_0 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_1 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_1 (\gen_decerr.decerr_slave_inst_n_2 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_2 (\gen_decerr.decerr_slave_inst_n_4 ),
.\m_atarget_hot_reg[3] (m_atarget_hot[3]),
.m_axi_arready(m_axi_arready),
.m_axi_awready(m_axi_awready),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_ready_d(m_ready_d_0[2:1]),
.m_ready_d_0(m_ready_d[1]),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_ready_d_reg[1]_0 (splitter_aw_n_0),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(\gen_decerr.decerr_slave_inst_n_5 ));
LUT2 #(
.INIT(4'hE))
\m_atarget_enc[0]_i_1
(.I0(Q[16]),
.I1(any_error),
.O(\m_atarget_enc[0]_i_1_n_0 ));
FDRE \m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_enc[0]_i_1_n_0 ),
.Q(m_atarget_enc[0]),
.R(reset));
FDRE \m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(any_error),
.Q(m_atarget_enc[1]),
.R(reset));
FDRE \m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[0]),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE \m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[1]),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE \m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_3),
.Q(m_atarget_hot[3]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q(m_atarget_hot[1:0]),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_60),
.\m_atarget_enc_reg[1] (m_atarget_enc),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_ready_d(m_ready_d[0]),
.\m_ready_d_reg[1] (reg_slice_r_n_2),
.m_valid_i(m_valid_i),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.s_axi_rready(s_axi_rready),
.s_ready_i_reg_0(addr_arbiter_inst_n_56),
.sr_rvalid(sr_rvalid));
LUT5 #(
.INIT(32'hFEF2CEC2))
\s_axi_bresp[0]_INST_0
(.I0(m_axi_bresp[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_axi_bresp[4]),
.I4(m_axi_bresp[2]),
.O(s_axi_bresp[0]));
LUT5 #(
.INIT(32'hFEF2CEC2))
\s_axi_bresp[1]_INST_0
(.I0(m_axi_bresp[1]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_axi_bresp[5]),
.I4(m_axi_bresp[3]),
.O(s_axi_bresp[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
(.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_3 ),
.m_ready_d(m_ready_d),
.m_valid_i(m_valid_i),
.m_valid_i_reg(reg_slice_r_n_2));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter splitter_aw
(.Q(m_atarget_hot[3]),
.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_bvalid_i_reg (splitter_aw_n_0),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_51),
.m_ready_d(m_ready_d_0),
.m_ready_d0(m_ready_d0),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_42),
.m_valid_i(m_valid_i),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave
(\gen_no_arbiter.m_grant_hot_i_reg[0] ,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ,
\m_ready_d_reg[1] ,
\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ,
s_ready_i_reg,
SR,
aclk,
s_axi_wvalid,
m_ready_d,
\gen_no_arbiter.grant_rnw_reg ,
m_axi_arready,
Q,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
m_axi_rvalid,
\m_atarget_hot_reg[3] ,
\gen_no_arbiter.grant_rnw_reg_0 ,
\m_ready_d_reg[1]_0 ,
m_ready_d_0,
\gen_no_arbiter.grant_rnw_reg_1 ,
aa_rready,
aresetn_d,
\gen_no_arbiter.grant_rnw_reg_2 );
output \gen_no_arbiter.m_grant_hot_i_reg[0] ;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
output \m_ready_d_reg[1] ;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
output s_ready_i_reg;
input [0:0]SR;
input aclk;
input [0:0]s_axi_wvalid;
input [1:0]m_ready_d;
input \gen_no_arbiter.grant_rnw_reg ;
input [2:0]m_axi_arready;
input [1:0]Q;
input [2:0]m_axi_awready;
input [2:0]m_axi_wready;
input [2:0]m_axi_bvalid;
input [2:0]m_axi_rvalid;
input [0:0]\m_atarget_hot_reg[3] ;
input \gen_no_arbiter.grant_rnw_reg_0 ;
input \m_ready_d_reg[1]_0 ;
input [0:0]m_ready_d_0;
input \gen_no_arbiter.grant_rnw_reg_1 ;
input aa_rready;
input aresetn_d;
input \gen_no_arbiter.grant_rnw_reg_2 ;
wire [1:0]Q;
wire [0:0]SR;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.grant_rnw_reg_0 ;
wire \gen_no_arbiter.grant_rnw_reg_1 ;
wire \gen_no_arbiter.grant_rnw_reg_2 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0] ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
wire [0:0]\m_atarget_hot_reg[3] ;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_bvalid;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d_0;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire [3:3]mi_arready;
wire [3:3]mi_bvalid;
wire [3:3]mi_rvalid;
wire [3:3]mi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i_reg;
LUT6 #(
.INIT(64'hAAAAA8AA0000AAAA))
\gen_axilite.s_axi_arready_i_i_1
(.I0(aresetn_d),
.I1(\gen_no_arbiter.grant_rnw_reg_1 ),
.I2(m_ready_d_0),
.I3(\m_atarget_hot_reg[3] ),
.I4(mi_rvalid),
.I5(mi_arready),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFEF00000010))
\gen_axilite.s_axi_awready_i_i_1
(.I0(mi_bvalid),
.I1(\gen_no_arbiter.grant_rnw_reg_2 ),
.I2(\m_atarget_hot_reg[3] ),
.I3(m_ready_d[1]),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(mi_wready),
.O(\gen_axilite.s_axi_awready_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_i_1_n_0 ),
.Q(mi_wready),
.R(SR));
LUT5 #(
.INIT(32'h77F07700))
\gen_axilite.s_axi_bvalid_i_i_1
(.I0(\m_atarget_hot_reg[3] ),
.I1(\gen_no_arbiter.grant_rnw_reg_0 ),
.I2(mi_wready),
.I3(mi_bvalid),
.I4(\m_ready_d_reg[1]_0 ),
.O(\gen_axilite.s_axi_bvalid_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_bvalid_i_i_1_n_0 ),
.Q(mi_bvalid),
.R(SR));
LUT6 #(
.INIT(64'h00FFFFFF02020000))
\gen_axilite.s_axi_rvalid_i_i_1
(.I0(mi_arready),
.I1(m_ready_d_0),
.I2(\gen_no_arbiter.grant_rnw_reg_1 ),
.I3(aa_rready),
.I4(\m_atarget_hot_reg[3] ),
.I5(mi_rvalid),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_rvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
.Q(mi_rvalid),
.R(SR));
LUT6 #(
.INIT(64'h0F0F0707FFFF07FF))
\gen_no_arbiter.m_grant_hot_i[0]_i_4
(.I0(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
.I1(s_axi_wvalid),
.I2(m_ready_d[0]),
.I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(m_ready_d[1]),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\m_ready_d[1]_i_2
(.I0(mi_arready),
.I1(m_axi_arready[1]),
.I2(Q[0]),
.I3(m_axi_arready[2]),
.I4(Q[1]),
.I5(m_axi_arready[0]),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\m_ready_d[2]_i_5
(.I0(mi_wready),
.I1(m_axi_awready[1]),
.I2(Q[0]),
.I3(m_axi_awready[2]),
.I4(Q[1]),
.I5(m_axi_awready[0]),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
m_valid_i_i_3
(.I0(mi_rvalid),
.I1(m_axi_rvalid[1]),
.I2(Q[0]),
.I3(m_axi_rvalid[2]),
.I4(Q[1]),
.I5(m_axi_rvalid[0]),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(mi_bvalid),
.I1(m_axi_bvalid[1]),
.I2(Q[0]),
.I3(m_axi_bvalid[2]),
.I4(Q[1]),
.I5(m_axi_bvalid[0]),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_wready[0]_INST_0_i_1
(.I0(mi_wready),
.I1(m_axi_wready[1]),
.I2(Q[0]),
.I3(m_axi_wready[2]),
.I4(Q[1]),
.I5(m_axi_wready[0]),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter
(\gen_axilite.s_axi_bvalid_i_reg ,
m_ready_d,
s_axi_wvalid,
Q,
m_valid_i,
aa_grant_rnw,
aresetn_d,
m_ready_d0,
\m_ready_d_reg[2]_0 ,
\gen_no_arbiter.grant_rnw_reg ,
aclk);
output \gen_axilite.s_axi_bvalid_i_reg ;
output [2:0]m_ready_d;
input [0:0]s_axi_wvalid;
input [0:0]Q;
input m_valid_i;
input aa_grant_rnw;
input aresetn_d;
input [0:0]m_ready_d0;
input \m_ready_d_reg[2]_0 ;
input \gen_no_arbiter.grant_rnw_reg ;
input aclk;
wire [0:0]Q;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i;
wire [0:0]s_axi_wvalid;
LUT6 #(
.INIT(64'h0000000000200000))
\gen_axilite.s_axi_bvalid_i_i_3
(.I0(s_axi_wvalid),
.I1(m_ready_d[1]),
.I2(Q),
.I3(m_ready_d[2]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
LUT4 #(
.INIT(16'h8880))
\m_ready_d[0]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(\m_ready_d_reg[2]_0 ),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.O(\m_ready_d[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h00A2))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(\m_ready_d_reg[2]_0 ),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.O(\m_ready_d[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0A02))
\m_ready_d[2]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(\m_ready_d_reg[2]_0 ),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.O(\m_ready_d[2]_i_1_n_0 ));
FDRE \m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE \m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE \m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0
(m_ready_d,
aresetn_d,
\gen_axilite.s_axi_arready_i_reg ,
m_valid_i,
aa_grant_rnw,
m_valid_i_reg,
aclk);
output [1:0]m_ready_d;
input aresetn_d;
input \gen_axilite.s_axi_arready_i_reg ;
input m_valid_i;
input aa_grant_rnw;
input m_valid_i_reg;
input aclk;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_reg ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire m_valid_i;
wire m_valid_i_reg;
LUT6 #(
.INIT(64'h0000000000002AAA))
\m_ready_d[0]_i_1
(.I0(aresetn_d),
.I1(\gen_axilite.s_axi_arready_i_reg ),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(m_ready_d[1]),
.I5(m_valid_i_reg),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAA800000000000))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(\gen_axilite.s_axi_arready_i_reg ),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(m_ready_d[1]),
.I5(m_valid_i_reg),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE \m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE \m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
(sr_rvalid,
aa_rready,
\m_ready_d_reg[1] ,
m_axi_rready,
\s_axi_rdata[31] ,
aclk,
m_ready_d,
\gen_no_arbiter.grant_rnw_reg ,
s_axi_rready,
s_ready_i_reg_0,
aa_grant_rnw,
m_valid_i,
Q,
m_axi_rresp,
\m_atarget_enc_reg[1] ,
m_axi_rdata,
SR,
E);
output sr_rvalid;
output aa_rready;
output \m_ready_d_reg[1] ;
output [1:0]m_axi_rready;
output [33:0]\s_axi_rdata[31] ;
input aclk;
input [0:0]m_ready_d;
input \gen_no_arbiter.grant_rnw_reg ;
input [0:0]s_axi_rready;
input s_ready_i_reg_0;
input aa_grant_rnw;
input m_valid_i;
input [1:0]Q;
input [5:0]m_axi_rresp;
input [1:0]\m_atarget_enc_reg[1] ;
input [95:0]m_axi_rdata;
input [0:0]SR;
input [0:0]E;
wire [0:0]E;
wire [1:0]Q;
wire [0:0]SR;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire \aresetn_d_reg_n_0_[0] ;
wire \aresetn_d_reg_n_0_[1] ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire [1:0]\m_atarget_enc_reg[1] ;
wire [95:0]m_axi_rdata;
wire [1:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire \m_payload_i[1]_i_2_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
wire \m_payload_i_reg_n_0_[0] ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_i_1_n_0;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1_n_0;
wire s_ready_i_reg_0;
wire [34:0]skid_buffer;
wire \skid_buffer[10]_i_1_n_0 ;
wire \skid_buffer[11]_i_1_n_0 ;
wire \skid_buffer[12]_i_1_n_0 ;
wire \skid_buffer[13]_i_1_n_0 ;
wire \skid_buffer[14]_i_1_n_0 ;
wire \skid_buffer[15]_i_1_n_0 ;
wire \skid_buffer[16]_i_1_n_0 ;
wire \skid_buffer[17]_i_1_n_0 ;
wire \skid_buffer[18]_i_1_n_0 ;
wire \skid_buffer[19]_i_1_n_0 ;
wire \skid_buffer[20]_i_1_n_0 ;
wire \skid_buffer[21]_i_1_n_0 ;
wire \skid_buffer[22]_i_1_n_0 ;
wire \skid_buffer[23]_i_1_n_0 ;
wire \skid_buffer[24]_i_1_n_0 ;
wire \skid_buffer[25]_i_1_n_0 ;
wire \skid_buffer[26]_i_1_n_0 ;
wire \skid_buffer[27]_i_1_n_0 ;
wire \skid_buffer[28]_i_1_n_0 ;
wire \skid_buffer[29]_i_1_n_0 ;
wire \skid_buffer[30]_i_1_n_0 ;
wire \skid_buffer[31]_i_1_n_0 ;
wire \skid_buffer[32]_i_1_n_0 ;
wire \skid_buffer[33]_i_1_n_0 ;
wire \skid_buffer[34]_i_1_n_0 ;
wire \skid_buffer[3]_i_1_n_0 ;
wire \skid_buffer[4]_i_1_n_0 ;
wire \skid_buffer[5]_i_1_n_0 ;
wire \skid_buffer[6]_i_1_n_0 ;
wire \skid_buffer[7]_i_1_n_0 ;
wire \skid_buffer[8]_i_1_n_0 ;
wire \skid_buffer[9]_i_1_n_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg_n_0_[0] ),
.Q(\aresetn_d_reg_n_0_[1] ),
.R(SR));
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(aa_rready),
.I1(Q[0]),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(aa_rready),
.I1(Q[1]),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(\skid_buffer[10]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(\skid_buffer[11]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(\skid_buffer[12]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(\skid_buffer[13]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(\skid_buffer[14]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(\skid_buffer[15]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(\skid_buffer[16]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(\skid_buffer[17]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(\skid_buffer[18]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(\skid_buffer[19]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h0E))
\m_payload_i[1]_i_1
(.I0(\skid_buffer_reg_n_0_[1] ),
.I1(aa_rready),
.I2(\m_payload_i[1]_i_2_n_0 ),
.O(skid_buffer[1]));
LUT6 #(
.INIT(64'h0055330F00000000))
\m_payload_i[1]_i_2
(.I0(m_axi_rresp[4]),
.I1(m_axi_rresp[2]),
.I2(m_axi_rresp[0]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(\m_atarget_enc_reg[1] [1]),
.I5(aa_rready),
.O(\m_payload_i[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(\skid_buffer[20]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(\skid_buffer[21]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(\skid_buffer[22]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(\skid_buffer[23]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(\skid_buffer[24]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(\skid_buffer[25]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(\skid_buffer[26]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(\skid_buffer[27]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(\skid_buffer[28]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(\skid_buffer[29]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h0E))
\m_payload_i[2]_i_1
(.I0(\skid_buffer_reg_n_0_[2] ),
.I1(aa_rready),
.I2(\m_payload_i[2]_i_2_n_0 ),
.O(skid_buffer[2]));
LUT6 #(
.INIT(64'h00220A0000220AAA))
\m_payload_i[2]_i_2
(.I0(aa_rready),
.I1(m_axi_rresp[5]),
.I2(m_axi_rresp[3]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(\m_atarget_enc_reg[1] [1]),
.I5(m_axi_rresp[1]),
.O(\m_payload_i[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(\skid_buffer[30]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(\skid_buffer[31]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(\skid_buffer[32]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(\skid_buffer[33]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_2
(.I0(\skid_buffer[34]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(\skid_buffer[3]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(\skid_buffer[4]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(\skid_buffer[5]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(\skid_buffer[6]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(\skid_buffer[7]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(\skid_buffer[8]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(\skid_buffer[9]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\m_payload_i_reg_n_0_[0] ),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\s_axi_rdata[31] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\s_axi_rdata[31] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\s_axi_rdata[31] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\s_axi_rdata[31] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\s_axi_rdata[31] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\s_axi_rdata[31] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\s_axi_rdata[31] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\s_axi_rdata[31] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\s_axi_rdata[31] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\s_axi_rdata[31] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\s_axi_rdata[31] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\s_axi_rdata[31] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\s_axi_rdata[31] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\s_axi_rdata[31] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\s_axi_rdata[31] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\s_axi_rdata[31] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\s_axi_rdata[31] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\s_axi_rdata[31] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\s_axi_rdata[31] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\s_axi_rdata[31] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\s_axi_rdata[31] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\s_axi_rdata[31] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\s_axi_rdata[31] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\s_axi_rdata[31] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\s_axi_rdata[31] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\s_axi_rdata[31] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\s_axi_rdata[31] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\s_axi_rdata[31] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\s_axi_rdata[31] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\s_axi_rdata[31] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\s_axi_rdata[31] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\s_axi_rdata[31] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\s_axi_rdata[31] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\s_axi_rdata[31] [8]),
.R(1'b0));
LUT6 #(
.INIT(64'h000000007FFFFFFF))
\m_ready_d[1]_i_3
(.I0(sr_rvalid),
.I1(\m_payload_i_reg_n_0_[0] ),
.I2(s_axi_rready),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(m_ready_d),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'hA2A2A222A2A2A2A2))
m_valid_i_i_1
(.I0(\aresetn_d_reg_n_0_[1] ),
.I1(s_ready_i_reg_0),
.I2(sr_rvalid),
.I3(m_ready_d),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(s_axi_rready),
.O(m_valid_i_i_1_n_0));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(sr_rvalid),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAAAAA222A2222))
s_ready_i_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(sr_rvalid),
.I2(m_ready_d),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(s_axi_rready),
.I5(s_ready_i_reg_0),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(aa_rready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'hE))
\skid_buffer[0]_i_1
(.I0(aa_rready),
.I1(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[10]_i_1
(.I0(m_axi_rdata[7]),
.I1(m_axi_rdata[39]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[71]),
.O(\skid_buffer[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[11]_i_1
(.I0(m_axi_rdata[8]),
.I1(m_axi_rdata[40]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[72]),
.O(\skid_buffer[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[12]_i_1
(.I0(m_axi_rdata[9]),
.I1(m_axi_rdata[41]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[73]),
.O(\skid_buffer[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[13]_i_1
(.I0(m_axi_rdata[10]),
.I1(m_axi_rdata[74]),
.I2(\m_atarget_enc_reg[1] [1]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(m_axi_rdata[42]),
.O(\skid_buffer[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[14]_i_1
(.I0(m_axi_rdata[11]),
.I1(m_axi_rdata[43]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[75]),
.O(\skid_buffer[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[15]_i_1
(.I0(m_axi_rdata[12]),
.I1(m_axi_rdata[44]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[76]),
.O(\skid_buffer[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[16]_i_1
(.I0(m_axi_rdata[13]),
.I1(m_axi_rdata[45]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[77]),
.O(\skid_buffer[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[17]_i_1
(.I0(m_axi_rdata[14]),
.I1(m_axi_rdata[46]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[78]),
.O(\skid_buffer[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[18]_i_1
(.I0(m_axi_rdata[15]),
.I1(m_axi_rdata[47]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[79]),
.O(\skid_buffer[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[19]_i_1
(.I0(m_axi_rdata[16]),
.I1(m_axi_rdata[48]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[80]),
.O(\skid_buffer[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[20]_i_1
(.I0(m_axi_rdata[17]),
.I1(m_axi_rdata[49]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[81]),
.O(\skid_buffer[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[21]_i_1
(.I0(m_axi_rdata[18]),
.I1(m_axi_rdata[50]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[82]),
.O(\skid_buffer[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[22]_i_1
(.I0(m_axi_rdata[19]),
.I1(m_axi_rdata[51]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[83]),
.O(\skid_buffer[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[23]_i_1
(.I0(m_axi_rdata[20]),
.I1(m_axi_rdata[52]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[84]),
.O(\skid_buffer[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0CAF0CA0))
\skid_buffer[24]_i_1
(.I0(m_axi_rdata[85]),
.I1(m_axi_rdata[53]),
.I2(\m_atarget_enc_reg[1] [1]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(m_axi_rdata[21]),
.O(\skid_buffer[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[25]_i_1
(.I0(m_axi_rdata[22]),
.I1(m_axi_rdata[54]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[86]),
.O(\skid_buffer[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[26]_i_1
(.I0(m_axi_rdata[23]),
.I1(m_axi_rdata[55]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[87]),
.O(\skid_buffer[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[27]_i_1
(.I0(m_axi_rdata[24]),
.I1(m_axi_rdata[56]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[88]),
.O(\skid_buffer[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[28]_i_1
(.I0(m_axi_rdata[25]),
.I1(m_axi_rdata[89]),
.I2(\m_atarget_enc_reg[1] [1]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(m_axi_rdata[57]),
.O(\skid_buffer[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[29]_i_1
(.I0(m_axi_rdata[26]),
.I1(m_axi_rdata[58]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[90]),
.O(\skid_buffer[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[30]_i_1
(.I0(m_axi_rdata[27]),
.I1(m_axi_rdata[59]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[91]),
.O(\skid_buffer[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[31]_i_1
(.I0(m_axi_rdata[28]),
.I1(m_axi_rdata[60]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[92]),
.O(\skid_buffer[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[32]_i_1
(.I0(m_axi_rdata[29]),
.I1(m_axi_rdata[61]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[93]),
.O(\skid_buffer[32]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[33]_i_1
(.I0(m_axi_rdata[30]),
.I1(m_axi_rdata[62]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[94]),
.O(\skid_buffer[33]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[34]_i_1
(.I0(m_axi_rdata[31]),
.I1(m_axi_rdata[63]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[95]),
.O(\skid_buffer[34]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[3]_i_1
(.I0(m_axi_rdata[0]),
.I1(m_axi_rdata[32]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[64]),
.O(\skid_buffer[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[4]_i_1
(.I0(m_axi_rdata[1]),
.I1(m_axi_rdata[33]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[65]),
.O(\skid_buffer[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[5]_i_1
(.I0(m_axi_rdata[2]),
.I1(m_axi_rdata[34]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[66]),
.O(\skid_buffer[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[6]_i_1
(.I0(m_axi_rdata[3]),
.I1(m_axi_rdata[35]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[67]),
.O(\skid_buffer[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0CAF0CA0))
\skid_buffer[7]_i_1
(.I0(m_axi_rdata[68]),
.I1(m_axi_rdata[36]),
.I2(\m_atarget_enc_reg[1] [1]),
.I3(\m_atarget_enc_reg[1] [0]),
.I4(m_axi_rdata[4]),
.O(\skid_buffer[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[8]_i_1
(.I0(m_axi_rdata[5]),
.I1(m_axi_rdata[37]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[69]),
.O(\skid_buffer[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[9]_i_1
(.I0(m_axi_rdata[6]),
.I1(m_axi_rdata[38]),
.I2(\m_atarget_enc_reg[1] [0]),
.I3(\m_atarget_enc_reg[1] [1]),
.I4(m_axi_rdata[70]),
.O(\skid_buffer[9]_i_1_n_0 ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[10]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[11]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[12]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[13]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[14]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[15]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[16]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[17]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[18]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[19]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[20]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[21]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[22]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[23]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[24]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[25]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[26]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[27]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[28]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[29]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[30]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[31]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[32]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[33]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[34]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[3]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[4]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[5]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[6]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[7]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[8]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[9]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) output [2:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [95:0]m_axi_araddr;
wire [8:0]m_axi_arprot;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [95:0]m_axi_awaddr;
wire [8:0]m_axi_awprot;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [95:0]m_axi_wdata;
wire [2:0]m_axi_wready;
wire [11:0]m_axi_wstrb;
wire [2:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "192'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "3" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module main(
//--Input/Output Definition----------------------------------------------------
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
input int_n,
input nmi_n,
input wait_n,
output res,
input [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
input rompg0_n,
input dos_n, // aka rompg1
input rompg2,
input rompg3,
input rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
input [15:0] rd,
input [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
input [1:0] vred,
input [1:0] vgrn,
input [1:0] vblu,
input vhsync,
input vvsync,
input vcsync,
// AY control and audio/tape
input ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
input [2:0] ide_a,
input [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
input vg_clk,
output vg_cs_n,
output vg_res_n,
input vg_hrdy,
input vg_rclk,
input vg_rawr,
input [1:0] vg_a, // disk drive selection
input vg_wrd,
input vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
input spiint_n
);
//--Dummy----------------------------------------------------------------------
assign iorq1_n = 1'b1;
assign iorq2_n = 1'b1;
assign res= 1'b1;
assign rwe_n = 1'b1;
assign rucas_n = 1'b1;
assign rlcas_n = 1'b1;
assign rras0_n = 1'b1;
assign rras1_n = 1'b1;
assign ay_bdir = 1'b0;
assign ay_bc1 = 1'b0;
assign vg_cs_n = 1'b1;
assign vg_res_n = 1'b0;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs0_n = 1'b1;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign clkz_out = 1'b0;
assign csrom = 1'b0;
assign romoe_n = 1'b1;
assign romwe_n = 1'b1;
//--Main wires-----------------------------------------------------------------
assign sdclk = spick;
assign sddo = spido;
assign spidi = sddi;
assign sdcs_n = spics_n;
assign beep = spiint_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
|
(******************************************************************************)
(** Imports **)
(* Disable notation conflict warnings *)
Set Warnings "-notation-overridden".
(* SSReflect *)
From Coq Require Import ssreflect ssrbool ssrfun.
From mathcomp Require Import ssrnat seq eqtype.
Set Bullet Behavior "Strict Subproofs".
(* Sortedness *)
Require Import Coq.Sorting.Sorted.
(* Basic Haskell libraries *)
Require Import GHC.Base Proofs.GHC.Base.
Require Import GHC.List Proofs.GHC.List.
Require Import GHC.Enum Proofs.GHC.Enum.
Require Import Data.Foldable Proofs.Data.Foldable.
Require Import Data.OldList Proofs.Data.OldList.
Require Import Data.Bits Proofs.Data.Bits.Popcount.
(* Quickcheck *)
Require Import Test.QuickCheck.Property.
(* IntSet library *)
Require Import Data.IntSet.Internal.
(* IntSet proofs *)
Require Import IntSetProperties.
Require Import DyadicIntervals.
Require Import IntSetProofs.
(* Bit manipulation *)
Require Import BitUtils.
(* Working with Haskell *)
Require Import OrdTactic.
Require Import HSUtil IntSetUtil SortedUtil.
(******************************************************************************)
(** Name dismabiguation -- copied from HSUtil **)
Notation list := Coq.Init.Datatypes.list.
Notation seq := Coq.Lists.List.seq.
Notation reflect := ssrbool.reflect.
(******************************************************************************)
(** Theorems **)
(** The quoted comments and the section headers are taken directly from
`intset-properties.hs`. **)
(********************************************************************
Valid IntMaps
********************************************************************)
Theorem thm_Valid : toProp prop_Valid.
Proof.
rewrite /prop_Valid /forValidUnitTree /forValid /=; apply valid_correct.
Qed.
(********************************************************************
Construction validity
********************************************************************)
Theorem thm_EmptyValid : toProp prop_EmptyValid.
Proof. done. Qed.
Theorem thm_SingletonValid : toProp prop_SingletonValid.
Proof.
rewrite /prop_SingletonValid /= => x POS_x.
by apply valid_correct, singleton_WF.
Qed.
Theorem thm_InsertIntoEmptyValid : toProp prop_InsertIntoEmptyValid.
Proof.
rewrite /prop_InsertIntoEmptyValid /= => x POS.
by apply valid_correct, insert_WF.
Qed.
(********************************************************************
Single, Member, Insert, Delete, Member, FromList
********************************************************************)
Theorem thm_Single : toProp prop_Single.
Proof. by rewrite /prop_Single /= => x POS_x; apply/Eq_eq. Qed.
Theorem thm_Member : toProp prop_Member.
Proof.
rewrite /prop_Member /= => xs POS_xs n POS_n.
rewrite !Foldable_all_ssreflect; apply/allP => /= k.
by rewrite fromList_member // Eq_refl.
Qed.
Theorem thm_NotMember : toProp prop_NotMember.
Proof.
rewrite /prop_NotMember /= => xs POS_xs n POS_n.
rewrite !Foldable_all_ssreflect; apply/allP => /= k.
by rewrite /notMember /notElem /= fromList_member // Eq_refl.
Qed.
(* SKIPPED: test_LookupSomething, prop_LookupLT, prop_LookupGT, prop_LookupLE, prop_LookupGE *)
Theorem thm_InsertDelete : toProp prop_InsertDelete.
Proof.
rewrite /prop_InsertDelete /= => x POS s WF_s.
move: (insert_WF x _ WF_s ) => WF_ins.
move: (delete_WF x _ WF_ins) => WF_res.
case x_nin_s: (~~ member x s) => //=; split=> /=; first by apply valid_correct.
apply/eqIntSetMemberP => // k.
rewrite delete_member // insert_member //.
rewrite Eq_inv andb_orr andbN orFb.
case: (EqExact_cases k x) => [[Beq Peq] | [Bneq Pneq]].
- by rewrite Peq; move: x_nin_s => /negbTE->; rewrite andbF.
- by rewrite Bneq andTb.
Qed.
(* Cheating: manually forgetting POS constraint *)
Theorem thm_MemberFromList : toProp prop_MemberFromList.
Proof.
rewrite /prop_MemberFromList /= => xs _.
set abs_xs := flat_map _ xs.
apply/andP; split.
all: rewrite Foldable_all_ssreflect; apply/allP => /= k; rewrite in_elem.
- rewrite fromList_member //.
- rewrite /notMember /notElem /= fromList_member //.
+ move=> k_abs; have k_pos: (0 <= k)%N. {
Nomega.
}
clear k_abs; subst abs_xs; elim: xs => [|x xs IH] //=.
rewrite elem_app negb_orb IH andbT.
by case: k k_pos {IH}; case: x.
Qed.
(********************************************************************
Union, Difference and Intersection
********************************************************************)
Theorem thm_UnionInsert : toProp prop_UnionInsert.
Proof.
rewrite /prop_UnionInsert /= => x POS_x s WF_s.
move: (singleton_WF x) => WF_sing.
move: (union_WF _ _ WF_s WF_sing) => WF_union.
move: (insert_WF x _ WF_s) => WF_ins.
split=> /=; first by apply valid_correct.
apply/eqIntSetMemberP => // k.
by rewrite union_member // singleton_member // insert_member // orbC.
Qed.
Theorem thm_UnionAssoc : toProp prop_UnionAssoc.
Proof.
rewrite /prop_UnionAssoc /= => s1 WF1 s2 WF2 s3 WF3.
move: (union_WF _ _ WF1 WF2) => WF12.
move: (union_WF _ _ WF2 WF3) => WF23.
move: (union_WF _ _ WF12 WF3) => WF123.
move: (union_WF _ _ WF1 WF23) => WF123'.
apply/eqIntSetMemberP => // k.
by rewrite !union_member // orbA.
Qed.
Theorem thm_UnionComm : toProp prop_UnionComm.
Proof.
Proof.
rewrite /prop_UnionComm /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
move: (union_WF _ _ WF2 WF1) => WF21.
apply/eqIntSetMemberP => // k.
by rewrite !union_member // orbC.
Qed.
Theorem thm_Diff : toProp prop_Diff.
Proof.
rewrite /prop_Diff /= => xs POS_xs ys POS_ys.
move: (fromList_WF xs) => WF_xs.
move: (fromList_WF ys) => WF_ys.
move: (difference_WF _ _ WF_xs WF_ys) => WF_diff.
split=> /=; first by apply valid_correct.
apply/Eq_eq/StronglySorted_Ord_eq_In.
- by apply toList_sorted.
- apply StronglySorted_NoDup_Ord; first apply sort_StronglySorted.
rewrite -sort_NoDup.
apply diff_preserves_NoDup, nub_NoDup.
- move=> a.
rewrite !(rwP (elemP _ _)).
rewrite sort_elem.
rewrite diff_NoDup_elem; last apply nub_NoDup.
rewrite !nub_elem.
rewrite toAscList_member // difference_member // !fromList_member //.
Qed.
Theorem thm_Int : toProp prop_Int.
Proof.
rewrite /prop_Int /= => xs _ ys _.
move: (fromList_WF xs) => WF_xs.
move: (fromList_WF ys) => WF_ys.
move: (intersection_WF _ _ WF_xs WF_ys) => WF_both.
split=> /=; first by apply valid_correct.
apply/Eq_eq; fold toList.
apply StronglySorted_Nlt_eq_In;
[by apply to_List_sorted | apply StronglySorted_sort_nub_Nlt | ].
move=> a.
by rewrite !(rwP (elemP _ _))
toList_member // intersection_member // !fromList_member //
sort_elem nub_elem intersect_elem.
Qed.
Theorem thm_disjoint : toProp prop_disjoint.
Proof.
rewrite /prop_disjoint /= => s1 WF1 s2 WF2.
move: (intersection_WF _ _ WF1 WF2) => WF12.
apply/Eq_eq/bool_eq_iff.
rewrite disjoint_member // null_member //.
split=> [is_disjoint | is_not_intersection] k.
- rewrite intersection_member //; apply negbTE.
apply is_disjoint.
- move: (is_not_intersection k).
rewrite intersection_member // => /negbT.
by rewrite negb_andb.
Qed.
(********************************************************************
Lists
********************************************************************)
(* SKIPPED: prop_Ordered *)
Theorem thm_List : toProp prop_List.
Proof.
rewrite /prop_List /=; rewrite -/toList => xs POS_xs.
Proof.
have WF_xs: WF (fromList xs) by apply fromList_WF.
apply/Eq_eq/StronglySorted_Ord_eq_In.
- apply StronglySorted_sort_nub.
- apply toList_sorted, fromList_WF=> //.
- move=> a.
by rewrite !(rwP (elemP _ _))
toList_member // fromList_member //
sort_elem nub_elem.
Qed.
Theorem thm_DescList : toProp prop_DescList.
Proof.
rewrite /prop_DescList /= => xs POS_xs.
replace (toDescList (fromList xs)) with (reverse (toAscList (fromList xs)))
by by rewrite !hs_coq_reverse_rev toDescList_spec //; apply fromList_WF.
apply/Eq_eq; f_equal; apply/Eq_eq.
by apply thm_List.
Qed.
Theorem thm_AscDescList : toProp prop_AscDescList.
Proof.
rewrite /prop_AscDescList /= => xs POS_xs.
rewrite /toAscList toDescList_spec; last by apply fromList_WF.
by rewrite hs_coq_reverse_rev rev_involutive Eq_refl.
Qed.
(* SKIPPED: prop_fromList *)
(********************************************************************
Bin invariants
********************************************************************)
(* "Check the invariant that the mask is a power of 2." *)
Theorem thm_MaskPow2 : toProp prop_MaskPow2.
Proof.
(* We do `...; [|done|done]` and the next rewrite both together instead of
`//=` to avoid ever trying to simplify `powersOf2`, which would both
generate [0..63] *and do the exponentiation*. *)
simpl; elim=> [p m l IHl r IHr | p m | ] WFs; [|done|done].
rewrite /prop_MaskPow2 -/prop_MaskPow2.
move: (WFs) => /WF_Bin_children [WFl WFr].
apply/and3P; split; [| apply IHl, WFl | apply IHr, WFr].
rewrite /powersOf2 flat_map_cons_f; change @GHC.Base.map with @Coq.Lists.List.map.
rewrite fromList_member.
rewrite (lock enumFromTo).
apply/elemP; rewrite in_map_iff.
move: (valid_maskPowerOfTwo _ WFs) => /= /and3P [/Eq_eq/bitcount_0_1_power [i ->] _ _].
exists i; split => //.
admit. (* Unprovable *)
Abort.
(* "Check that the prefix satisfies its invariant." *)
Theorem thm_Prefix : toProp prop_Prefix.
Proof.
elim => [p m | p bm | ] //.
rewrite /prop_Prefix -/prop_Prefix /toList (lock toAscList) /= => l IHl r IHr WFs;
move: (WFs) => /WF_Bin_children [WFl WFr].
move: (WFs) => [fs SEMs];
inversion SEMs as [|s' [ps ms] fs' DESCs]; subst s' fs';
inversion DESCs as [|l' rng_l fl r' rng_r fr p' m' rng_s' fs'
DESCl DESCr POSrng subrange_l subrange_r def_p def_m def_fs];
subst p' m' l' r' rng_s' fs' p m.
apply/and3P; split; try by (apply IHl || apply IHr).
rewrite !Foldable_all_ssreflect. apply/allP => x MEM_x.
rewrite match_nomatch.
rewrite nomatch_spec.
move: MEM_x.
rewrite -(lock toAscList) in_elem toAscList_member // (member_Sem SEMs) => MEM_x.
rewrite negb_involutive.
rewrite def_fs in MEM_x. apply orb_true_iff in MEM_x. destruct MEM_x.
eapply inRange_isSubrange_true; only 2: eapply (Desc_inside DESCl); only 1: isSubrange_true; assumption.
eapply inRange_isSubrange_true; only 2: eapply (Desc_inside DESCr); only 1: isSubrange_true; assumption.
assumption.
Qed.
(* "Check that the left elements don't have the mask bit set, and the right ones
do." *)
Theorem thm_LeftRight : toProp prop_LeftRight.
Proof.
rewrite /prop_LeftRight /= => -[p m l r | // | // ] WFs; move: (WFs) => /WF_Bin_children [WFl WFr].
move: (WFs) => /valid_maskRespected /=.
move => /andP [mask_l mask_r]. move: mask_r.
move => /andP [mask_r _]. move: mask_l mask_r.
rewrite !Foldable_and_all !Foldable_all_ssreflect !flat_map_cons_f /zero /elems /toList.
move=> /allP /= mask_l /allP /= mask_r.
apply/andP; split; apply/allP => /= b /mapP [] /= x x_in {b}->; apply/Eq_eq.
- by move: (mask_l _ x_in) => /N.eqb_spec ->.
- move: (mask_r _ x_in) => /N.eqb_spec.
case: (WF_Bin_mask_power_N WFs) => [i ?]; subst m.
rewrite -N.shiftl_1_l => NEQ_bits.
apply N.bits_inj_iff => ix.
rewrite N.shiftl_1_l N.land_spec N.pow2_bits_eqb.
rewrite -> N.shiftl_1_l in NEQ_bits.
case: (N.eqb_spec i ix) => [? | NEQ]; first subst.
+ rewrite andb_true_r.
rewrite <- N_land_pow2_testbit.
rewrite negb_true_iff.
rewrite N.eqb_neq.
rewrite N.land_comm.
assumption.
+ apply andb_false_r.
Qed.
(********************************************************************
IntSet operations are like Set operations
********************************************************************)
(* "Check that IntSet.isProperSubsetOf is the same as Set.isProperSubsetOf." *)
Theorem thm_isProperSubsetOf : toProp prop_isProperSubsetOf.
Proof.
Abort.
(* "In the above test, isProperSubsetOf almost always returns False (since a
random set is almost never a subset of another random set). So this second
test checks the True case." *)
Theorem thm_isProperSubsetOf2 : toProp prop_isProperSubsetOf2.
Proof.
rewrite /prop_isProperSubsetOf2 /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
apply/Eq_eq/bool_eq_iff.
rewrite isProperSubsetOf_member //; split; first by intuition.
move=> s1_diff; split=> // k k_in_s1.
by rewrite union_member // k_in_s1 orTb.
Qed.
Theorem thm_isSubsetOf : toProp prop_isSubsetOf.
Proof.
rewrite /prop_isSubsetOf /= => s1 WF1 s2 WF2.
Abort.
Theorem thm_isSubsetOf2 : toProp prop_isSubsetOf2.
Proof.
rewrite /prop_isSubsetOf2 /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
rewrite isSubsetOf_member // => k.
by rewrite union_member // => ->; rewrite orTb.
Qed.
Theorem thm_size : toProp prop_size.
Proof.
rewrite /prop_size /= => s WF_s.
rewrite size_spec //.
split=> /=.
- change @foldl' with @foldl; rewrite foldl_spec //.
apply/Eq_eq.
generalize (toList s). intro xs.
rewrite <- fold_left_length.
replace (0%N) with (N.of_nat 0) by reflexivity.
generalize 0.
induction xs.
* reflexivity.
* intros. rewrite IHxs. cbn - [N.of_nat].
f_equal.
rewrite Nat2N.inj_succ.
Nomega.
- apply Eq_refl.
Qed.
(* SKIPPED: prop_findMax, prop_findMin *)
Theorem thm_ord : toProp prop_ord.
Proof.
rewrite /prop_ord /= => s1 WF1 s2 WF2.
apply Eq_refl.
Qed.
(* SKIPPED: prop_readShow *)
Theorem thm_foldR : toProp prop_foldR.
Proof.
rewrite /prop_foldR /= => s WF_s.
by rewrite Eq_refl.
Qed.
Theorem thm_foldR' : toProp prop_foldR'.
Proof.
rewrite /prop_foldR' /= => s WF_s.
by rewrite Eq_refl.
Qed.
Theorem thm_foldL : toProp prop_foldL.
Proof.
rewrite /prop_foldL /= => s WF_s.
by rewrite foldl_spec // -hs_coq_foldl_base Eq_refl.
Qed.
Theorem thm_foldL' : toProp prop_foldL'.
Proof.
rewrite /prop_foldL' /=; change @foldl' with @foldl; apply thm_foldL.
Qed.
Theorem thm_map : toProp prop_map.
Proof.
rewrite /prop_map /map /= => s WF_s.
rewrite map_id.
apply/eqIntSetMemberP=> //; first by apply fromList_WF.
move=> k.
by rewrite fromList_member // toList_member // Eq_refl.
Qed.
(* SKIPPED: prop_maxView, prop_minView *)
Theorem thm_split : toProp prop_split.
Proof.
rewrite /prop_split /= => s WF_ss x POS_x.
rewrite split_filter //.
have WF_lt: WF (filter (fun y => y < x) s) by apply filter_WF.
have WF_gt: WF (filter (fun y => y > x) s) by apply filter_WF.
have WF_del: WF (delete x s) by apply delete_WF.
move: (union_WF _ _ WF_lt WF_gt) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat split=> /=; try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/eqIntSetMemberP => // k.
rewrite delete_member // union_member // !filter_member //.
rewrite -andb_orr andbC; f_equal.
apply Ord_lt_gt_antisym.
Qed.
Theorem thm_splitMember : toProp prop_splitMember.
Proof.
rewrite /prop_splitMember /= => s WF_ss x POS_x.
rewrite splitMember_filter //.
have WF_lt: WF (filter (fun y => y < x) s) by apply filter_WF.
have WF_gt: WF (filter (fun y => y > x) s) by apply filter_WF.
have WF_del: WF (delete x s) by apply delete_WF.
move: (union_WF _ _ WF_lt WF_gt) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat split=> //=; try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- by apply Eq_refl.
- apply/eqIntSetMemberP => // k.
rewrite delete_member // union_member // !filter_member //.
rewrite -andb_orr andbC; f_equal.
apply Ord_lt_gt_antisym.
Qed.
Theorem thm_splitRoot : toProp prop_splitRoot.
Proof.
rewrite /prop_splitRoot /= => -[p m l r | p m | ] WFs //=.
- move: (WFs) => /WF_Bin_children [WFl WFr].
have WFlr: WF (union l r) by apply union_WF.
have WFrl: WF (union r l) by apply union_WF.
have: (m > 0%N). {
move: (WFs) => [fs SEMs];
inversion SEMs as [|s' [ps ms] fs' DESCs];
subst s' fs';
inversion DESCs as [|l' rng_l fl r' rng_r fr p' m' rng_s' fs'
DESCl DESCr POSrng subrange_l subrange_r def_p def_m def_fs];
subst p' m' l' r' rng_s' fs' p m.
unfold ">", Ord_Char___ => /=.
apply/N.ltb_spec0.
apply N_pow_pos_nonneg => //.
}
move=> /(Ord_gt_not_lt _ _)/negbTE ->.
rewrite /unions !hs_coq_foldl'_list /= !(union_eq empty) /=.
apply/andP; split.
+ apply null_list_none => -[x y] /in_flat_map [kl [/elemP IN_kl /in_flat_map [kr [/elemP IN_kr IN_xy]]]].
move: IN_kl IN_kr; rewrite !toList_member // => IN_kl IN_kr.
move: (Bin_left_lt_right WFs _ IN_kl _ IN_kr) IN_xy.
by move=> /(Ord_lt_not_gt _ _)/negbTE ->.
+ by apply/eqIntSetMemberP => // k; rewrite Bin_member // union_member //.
- apply/andP; split; by [elim: (foldrBits _ _ _ _) | apply/Eq_eq].
Qed.
Theorem thm_partition : toProp prop_partition.
Proof.
rewrite /prop_partition /= => s WF_s _ _.
rewrite partition_filter //.
have WF_odd: WF (filter GHC.Real.odd s) by apply filter_WF.
have WF_even: WF (filter (fun k => ~~ GHC.Real.odd k) s) by apply filter_WF.
move: (union_WF _ _ WF_odd WF_even) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat (split=> /=); try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP[].
- apply/allP=> /= k.
rewrite in_elem toList_member // filter_member // => /andP[].
by rewrite /GHC.Real.odd negb_involutive.
- apply/eqIntSetMemberP=> // k.
rewrite union_member // !filter_member //.
by case: (member k s)=> //=; rewrite orb_negb_r.
Qed.
Theorem thm_filter : toProp prop_filter.
Proof.
rewrite /prop_filter /= => s WF_s _ _.
have WF_odd: WF (filter GHC.Real.odd s) by apply filter_WF.
have WF_even: WF (filter GHC.Real.even s) by apply filter_WF.
have WF_even': WF (filter (fun k => ~~ GHC.Real.odd k) s) by apply filter_WF.
move: (union_WF _ _ WF_odd WF_even) => WF_union.
repeat (split=> /=); try by apply valid_correct.
rewrite partition_filter //.
apply/andP; split; first by apply Eq_refl.
apply/eqIntSetMemberP=> // k.
rewrite !filter_member //.
by rewrite /GHC.Real.odd negb_involutive.
Qed.
(* SKIPPED: prop_bitcount *)
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 06:35:31 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.3 2006/06/26 07:42:19 wig Exp $
// $Date: 2006/06/26 07:42:19 $
// $Log: inst_t_e.v,v $
// Revision 1.3 2006/06/26 07:42:19 wig
// Updated io, generic and mde_tests testcases
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:50 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title3/title3_sim_netlist.v
// Design : title3
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "title3,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module title3
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "title3.mem" *)
(* C_INIT_FILE_NAME = "title3.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "3725" *)
(* C_READ_DEPTH_B = "3725" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "3725" *)
(* C_WRITE_DEPTH_B = "3725" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
title3_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module title3_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
title3_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[3:0]),
.douta(douta[3:0]),
.wea(wea));
title3_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:4]),
.douta(douta[11:4]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title3_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
title3_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title3_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
title3_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title3_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000111000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000001110000000000000000000000000000000000000000),
.INIT_04(256'h12E5000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h4E30000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000111100000000000000000000000000000000000000000001),
.INIT_07(256'h00000000000000000000000000000000000000000001FFE54200000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000014FFD442000000000000000),
.INIT_09(256'h00000000000000000000017FF7FFC2000021111000000244444444444316FF10),
.INIT_0A(256'h0000000000000019AAA11DFF5FFB100000000000000000111100000000000000),
.INIT_0B(256'h13FCBFF7200001EEE20000006FFFFFFFFFFFA27AF91000000000000000000000),
.INIT_0C(256'h3FADFF51000000000000000004ED111111000000000000000000000000000000),
.INIT_0D(256'h0006FFFFFFFFFFFF612DF91000000000000000000000000000000000013FFF11),
.INIT_0E(256'h00004DDFFFFF54444443100000000000000000000000112AFB1000001DFF4100),
.INIT_0F(256'hF64310000000000000000000000000000000014FFD1112CF8100000000000000),
.INIT_10(256'h000000000000000000000000001FB00000002FFE1000001366666666665BFB2D),
.INIT_11(256'h000000000000000004FFD10001851392100001110000000002888FFFFFFFFF61),
.INIT_12(256'h000011FB11120002FFE11000001FFFFFFFFFFA18FB2BFFD30000000000000000),
.INIT_13(256'h80000001EFD100012D700000000000016FFD4444310000000000000000000000),
.INIT_14(256'h0000015FF444444FF428FDEFFB200000000000000000000000000000000029FF),
.INIT_15(256'h000000000005FFC100000000000000000000000000000001BFFFFC444426FFB1),
.INIT_16(256'hFFE22000000000000000000000000000000000008FF91000001FFF10009FF920),
.INIT_17(256'h11100000000000000000000000068888AFFFF9BFFB10000003FF444444FF524B),
.INIT_18(256'h00000001781000000005EFC2000018FF910005FFF31000011111103CFE411111),
.INIT_19(256'h111100000002444CFFFFF40000002BFFFFFFFFFA9FA9FA110000000000000000),
.INIT_1A(256'hFF400001EFF300001EFFD110002DDDDDDDEFFEDDDDDDDB211111111111111111),
.INIT_1B(256'h50000000244444445FFFFF28FC1111111111111111111111117FF8100000001D),
.INIT_1C(256'hC10002EEEEEEEEFFEEEEEEEEBAFFFFFFFFFFFFFFFFFFFC200000000000122BFF),
.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFF38FFF510000000CFF510001EFF3000002EFF),
.INIT_1E(256'h11112899999999999999999994000000000000001FFA1000002333333334FFFF),
.INIT_1F(256'h9999999828FFF710000002FFF10005EF810000003CFE4100011111111EFB2111),
.INIT_20(256'h00000000000000000001FFF1000002BFFFFFFFFFFFFFAFFF9EF9999999999999),
.INIT_21(256'h1FFF11008FF8000000009FFE310000000001EFF3100000000000000000000000),
.INIT_22(256'hFF31000006FE8FFFF5FFE4429FF8441000000000000000000110149FF7110000),
.INIT_23(256'hDFFF210000000012FFF100000000000000000000000000000000000000000013),
.INIT_24(256'hACFFFFFF31000000000000000000000002CFFF3100014FFD1008FF8000000002),
.INIT_25(256'h0000000000000000000000000000000000000000003FFE1000006FE7FE8FFFFF),
.INIT_26(256'h00000000000001ACFE720004FFD1008FF80000000002BFFE41000000002BFF61),
.INIT_27(256'h00000000000000000000028FE1000001CFDEFFFFFFFFFFDEFFFE100000000000),
.INIT_28(256'h712AFF7008FF800000000002BFFE31000000002BFF6100000000000000000000),
.INIT_29(256'h06FFA100000CFFFFFFFFFFFFFACFFFF8000000000000000000000000003EFFDC),
.INIT_2A(256'h0002DFFF21000000002EFF310000000000000000000000000000000000000000),
.INIT_2B(256'hFFFE2CFFFFA20000000000000000000000000024FFFFFFFFF9008FF800000000),
.INIT_2C(256'hFF5110000000000000000000000000000166666666669FFB1000002FF5FFFFFF),
.INIT_2D(256'h000000000000000000119ADFFFFFB206A910000000000002BFB91000000001AC),
.INIT_2E(256'h0000000000001FFFFFFFFFFFFFB1000001FF5FFCFCDFEEFC3FFFFF4000000000),
.INIT_2F(256'h0355AFFA20011000000000000002521000000000002BFFC21000000000000000),
.INIT_30(256'h22222220000016FD6FDFFFFA4FFCFFF6F4000000000000000000000000000000),
.INIT_31(256'h00000000000000000000002EFFE1000000000000000000000000000122222222),
.INIT_32(256'h6FF44F54FFD22000000000000000000000000000000000022220000000000000),
.INIT_33(256'h0014B2100000000000000000000000000000000000000000000000003FF3FFFF),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000016FFEB2BBBB41113FFE1000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000003664000002000026651000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:4],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title3_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_01(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_02(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_03(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_04(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_05(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0101014F4F4F4F4F4F4F),
.INIT_06(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_07(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0101014F4F4F4F4F4F4F4F),
.INIT_08(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_09(256'h01020E05004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0A(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0B(256'h040E03004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0C(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01),
.INIT_0D(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F010101014F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0E(256'h4F4F4F4F4F4F4F4F4F4F4F010F0F0E0504024F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0F(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_10(256'h4F4F4F4F4F4F4F4F4F01040F0F0D0404024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_11(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_12(256'h4F4F02010101014F4F4F4F4F4F0204040404040404040404040301060F0F014F),
.INIT_13(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01070F0F070F0F0C024F4F),
.INIT_14(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F010101014F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_15(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F01090A0A0A01010D0F0F050F0F0B014F4F4F),
.INIT_16(256'h0F0F0F0F0A02070A0F09014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_17(256'h01030F0C0B0F0F07024F4F4F4F010E0E0E024F4F4F4F4F4F060F0F0F0F0F0F0F),
.INIT_18(256'h01014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_19(256'h030F0A0D0F0F05014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F040E0D01010101),
.INIT_1A(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F01030F0F0F0101),
.INIT_1B(256'h4F4F00060F0F0F0F0F0F0F0F0F0F0F0F0601020D0F09014F4F4F4F4F4F4F4F4F),
.INIT_1C(256'h4F4F4F4F4F4F4F4F4F4F4F000101020A0F0B014F4F4F4F4F010D0F0F04014F4F),
.INIT_1D(256'h4F4F4F4F040D0D0F0F0F0F0F0504040404040403014F4F4F4F4F4F4F4F4F4F4F),
.INIT_1E(256'h4F4F4F4F0001040F0F0D010101020C0F08014F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_1F(256'h0F060403014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_20(256'h4F4F0000020F0F0E014F4F4F4F00010306060606060606060606050B0F0B020D),
.INIT_21(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F004F00010F0B4F4F4F),
.INIT_22(256'h014F4F4F4F0101014F4F4F4F4F4F000000020808080F0F0F0F0F0F0F0F0F0601),
.INIT_23(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00040F0F0D01004F0001080501030902),
.INIT_24(256'h0F0F0F0F0F0A01080F0B020B0F0F0D034F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_25(256'h4F4F4F4F01010F0B010101024F4F00020F0F0E01014F4F4F0000010F0F0F0F0F),
.INIT_26(256'h060F0F0D0404040403014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_27(256'h084F4F00000000010E0F0D014F4F4F01020D074F4F4F4F4F4F4F4F0000000001),
.INIT_28(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0002090F0F),
.INIT_29(256'h4F4F4F4F0001050F0F0404040404040F0F0402080F0D0E0F0F0B024F4F4F4F4F),
.INIT_2A(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F010B0F0F0F0F0C0404040402060F0F0B01),
.INIT_2B(256'h4F4F4F4F4F4F4F4F4F0000050F0F0C010000004F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_2C(256'h4F4F4F4F4F4F0000080F0F09014F4F4F0000010F0F0F014F4F4F090F0F09024F),
.INIT_2D(256'h0F0F0E02024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_2E(256'h0A0F0F0F0F090B0F0F0B014F4F4F4F0000030F0F0404040404040F0F0502040B),
.INIT_2F(256'h0101014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000608080808),
.INIT_30(256'h09014F4F00050F0F0F03014F4F4F4F01010101010100030C0F0E040101010101),
.INIT_31(256'h4F4F4F4F4F4F4F010708014F4F4F4F4F4F4F00050E0F0C024F4F4F0001080F0F),
.INIT_32(256'h0F0F0F0F0F0F0F0A090F0A090F0A01014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_33(256'h010101014F000000000000020404040C0F0F0F0F0F044F4F4F4F4F00020B0F0F),
.INIT_34(256'h0D0D0E0F0F0E0D0D0D0D0D0D0D0B020101010101010101010101010101010101),
.INIT_35(256'h0F0F044F4F4F4F010E0F0F034F4F4F00010E0F0F0D01014F4F4F020D0D0D0D0D),
.INIT_36(256'h010101010101010101010101010101010101070F0F08014F4F4F4F4F4F00010D),
.INIT_37(256'h05004F4F4F4F00000204040404040404050F0F0F0F0F02080F0C010101010101),
.INIT_38(256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0C024F4F4F4F4F4F00000000000102020B0F0F),
.INIT_39(256'h0C014F4F4F020E0E0E0E0E0E0E0E0F0F0E0E0E0E0E0E0E0E0B0A0F0F0F0F0F0F),
.INIT_3A(256'h0F05014F4F4F4F4F4F000C0F0F05014F4F4F010E0F0F034F4F4F4F00020E0F0F),
.INIT_3B(256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F03080F0F),
.INIT_3C(256'h4F4F4F4F00000000010F0F0A014F4F4F4F4F020303030303030303040F0F0F0F),
.INIT_3D(256'h01010101020809090909090909090909090909090909090909044F4F4F4F4F4F),
.INIT_3E(256'h08014F4F4F4F0000030C0F0E04014F000001010101010101010E0F0B02010101),
.INIT_3F(256'h090909090909090802080F0F0F07014F4F4F4F4F00020F0F0F014F4F4F050E0F),
.INIT_40(256'h0F0F0F0F0F0F0F0F0F0F0F0F0A0F0F0F090E0F09090909090909090909090909),
.INIT_41(256'h0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00010F0F0F014F4F4F4F4F020B0F),
.INIT_42(256'h4F4F00010E0F0F03014F4F4F4F4F000000000000000000000000000000000000),
.INIT_43(256'h010F0F0F01014F4F080F0F084F4F4F4F4F4F0000090F0F0E03014F4F4F4F4F4F),
.INIT_44(256'h00000000000000000000000000000000000101000104090F0F0701014F4F4F00),
.INIT_45(256'h0F0F03014F4F4F0000060F0E080F0F0F0F050F0F0E040402090F0F0804040100),
.INIT_46(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000103),
.INIT_47(256'h0D0F0F0F02014F4F4F4F4F4F4F4F01020F0F0F014F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_48(256'h00020C0F0F0F03014F000001040F0F0D014F00080F0F084F4F4F4F4F4F4F0002),
.INIT_49(256'h0A0C0F0F0F0F0F0F03014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000),
.INIT_4A(256'h4F4F4F4F4F4F4F4F4F00030F0F0E014F4F4F4F00060F0E070F0E080F0F0F0F0F),
.INIT_4B(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_4C(256'h0F084F4F4F4F4F4F4F0000020B0F0F0E04014F4F4F4F4F4F4F00020B0F0F0601),
.INIT_4D(256'h4F4F4F4F4F4F4F4F4F4F4F0000010A0C0F0E0702000000040F0F0D014F00080F),
.INIT_4E(256'h0C0F0D0E0F0F0F0F0F0F0F0F0F0F0D0E0F0F0F0E014F4F4F4F4F4F4F4F4F4F4F),
.INIT_4F(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0002080F0E014F4F4F4F0001),
.INIT_50(256'h4F4F4F4F0000020B0F0F06014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_51(256'h0701020A0F0F074F00080F0F084F4F4F4F4F4F4F4F0000020B0F0F0E03014F4F),
.INIT_52(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000030E0F0F0D0C),
.INIT_53(256'h00060F0F0A014F4F4F00000C0F0F0F0F0F0F0F0F0F0F0F0F0F0A0C0F0F0F0F08),
.INIT_54(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00),
.INIT_55(256'h4F0000020D0F0F0F02014F4F4F4F4F4F0000020E0F0F03014F4F4F4F4F4F4F4F),
.INIT_56(256'h4F4F4F4F000002040F0F0F0F0F0F0F0F0F094F00080F0F084F4F4F4F4F4F4F4F),
.INIT_57(256'h0F0F0F0E020C0F0F0F0F0A02004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_58(256'h4F0106060606060606060606090F0F0B014F4F4F4F00020F0F050F0F0F0F0F0F),
.INIT_59(256'h0F0F0501014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_5A(256'h0A09014F4F4F4F4F4F4F4F4F4F0000020B0F0B09014F4F4F4F4F4F0000010A0C),
.INIT_5B(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000101090A0D0F0F0F0F0F0B020006),
.INIT_5C(256'h00010F0F050F0F0C0F0C0D0F0E0E0F0C030F0F0F0F0F04004F4F4F4F4F4F4F4F),
.INIT_5D(256'h4F4F4F4F4F4F4F4F4F4F4F4F010F0F0F0F0F0F0F0F0F0F0F0F0F0B014F4F4F4F),
.INIT_5E(256'h4F4F4F4F4F4F4F000000020B0F0F0C02014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_5F(256'h000305050A0F0F0A02000001014F4F4F4F4F4F4F4F4F4F4F4F0000020502014F),
.INIT_60(256'h0F044F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000000),
.INIT_61(256'h020202020202024F4F4F4F0001060F0D060F0D0F0F0F0F0A040F0F0C0F0F0F06),
.INIT_62(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00010202020202020202),
.INIT_63(256'h4F4F4F4F4F00004F4F4F4F4F4F4F4F4F4F4F4F4F0000020E0F0F0E014F4F4F4F),
.INIT_64(256'h4F4F4F4F4F4F4F4F4F4F4F00000000020202024F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_65(256'h060F0F04040F05040F0F0D02024F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_66(256'h4F4F000000000000000000000000004F4F4F4F4F4F4F0000030F0F030F0F0F0F),
.INIT_67(256'h000001040B02014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_68(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_69(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000004F4F4F4F),
.INIT_6A(256'h4F4F0001060F0F0E0B020B0B0B0B04010101030F0F0E014F4F4F4F4F4F4F4F4F),
.INIT_6B(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_6C(256'h4F4F4F4F4F4F4F4F4F4F4F4F0000000000334F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_6D(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_6E(256'h05014F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_6F(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F00000306060400000000000200004F00020606),
.INIT_70(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_71(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F2011004F4F4F4F),
.INIT_72(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_73(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_74(256'h000000000000000000000000000000000000004F4F4F4F4F4F0000004F4F4F4F),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module title3_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
title3_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "title3.mem" *)
(* C_INIT_FILE_NAME = "title3.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "3725" *) (* C_READ_DEPTH_B = "3725" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "3725" *) (* C_WRITE_DEPTH_B = "3725" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module title3_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
title3_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module title3_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
title3_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:42 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_sim_netlist.v
// Design : led_controller_design_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
(* NotValidForBitStream *)
module led_controller_design_rst_ps7_0_100M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
led_controller_design_rst_ps7_0_100M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module led_controller_design_rst_ps7_0_100M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module led_controller_design_rst_ps7_0_100M_0_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "lpf" *)
module led_controller_design_rst_ps7_0_100M_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
led_controller_design_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
led_controller_design_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
(* ORIG_REF_NAME = "proc_sys_reset" *)
module led_controller_design_rst_ps7_0_100M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
led_controller_design_rst_ps7_0_100M_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
led_controller_design_rst_ps7_0_100M_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "sequence_psr" *)
module led_controller_design_rst_ps7_0_100M_0_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
led_controller_design_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module led_controller_design_rst_ps7_0_100M_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_SYMBOL_V
`define SKY130_FD_SC_LS__TAPMET1_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_TB_V
`define SKY130_FD_SC_HS__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 B1 = 1'b0;
#380 B2 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B2 = 1'b1;
#500 B1 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B2 = 1'bx;
#640 B1 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_TB_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dec_table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dec_table (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "dec_table.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "dec_table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "dec_table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
`define SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.v
// Design : system_vga_sync_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
module system_vga_sync_reset_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
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